From f1b36a05d9ae8d9728bb971388dacdd6d74e4542 Mon Sep 17 00:00:00 2001
From: wanda-phi <145241585+wanda-phi@users.noreply.github.com>
Date: Sat, 14 Sep 2024 12:15:07 +0000
Subject: [PATCH] =?UTF-8?q?Deploying=20to=20gh-pages=20from=20=20@=20a913c?=
 =?UTF-8?q?85cb41b8515b4b8ca7554718258e267b9cf=20=F0=9F=9A=80?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 _sources/xilinx/spartan3/corner.rst.txt |    5 +-
 _sources/xilinx/virtex5/clock.rst.txt   |   16 +
 _sources/xilinx/virtex5/io.rst.txt      |   12 +
 _sources/xilinx/virtex6/gtx.rst.txt     |   13 +
 _sources/xilinx/virtex6/index.rst.txt   |    1 +
 objects.inv                             |  Bin 2834 -> 2847 bytes
 searchindex.js                          |    2 +-
 xilinx/index.html                       |    1 +
 xilinx/spartan3/corner.html             |  774 +--
 xilinx/virtex2/corner.html              |  740 +-
 xilinx/virtex4/io.html                  |   11 -
 xilinx/virtex5/center.html              |   13 +-
 xilinx/virtex5/clock.html               |  523 +-
 xilinx/virtex5/index.html               |    1 +
 xilinx/virtex5/io.html                  |  522 ++
 xilinx/virtex6/bram.html                |    1 +
 xilinx/virtex6/center.html              |    1 +
 xilinx/virtex6/clb.html                 |    1 +
 xilinx/virtex6/config.html              |    5 +-
 xilinx/virtex6/dsp.html                 |    1 +
 xilinx/virtex6/emac.html                |    1 +
 xilinx/virtex6/geometry.html            |    1 +
 xilinx/virtex6/gtx.html                 | 8385 +++++++++++++++++++++++
 xilinx/virtex6/index.html               |    5 +
 xilinx/virtex6/interconnect.html        |    1 +
 xilinx/virtex6/io.html                  |    1 +
 xilinx/virtex6/pcie.html                |    5 +-
 27 files changed, 10162 insertions(+), 880 deletions(-)
 create mode 100644 _sources/xilinx/virtex6/gtx.rst.txt
 create mode 100644 xilinx/virtex6/gtx.html

diff --git a/_sources/xilinx/spartan3/corner.rst.txt b/_sources/xilinx/spartan3/corner.rst.txt
index b5354f36..e6887600 100644
--- a/_sources/xilinx/spartan3/corner.rst.txt
+++ b/_sources/xilinx/spartan3/corner.rst.txt
@@ -155,10 +155,7 @@ I/O data — Spartan 3E
 =====================
 
 .. raw:: html
-   :file: ../gen/xc3se-iostd-lvdsbias-0.html
-
-.. raw:: html
-   :file: ../gen/xc3se-iostd-lvdsbias-1.html
+   :file: ../gen/xc3se-iostd-lvdsbias.html
 
 
 I/O data — Spartan 3A
diff --git a/_sources/xilinx/virtex5/clock.rst.txt b/_sources/xilinx/virtex5/clock.rst.txt
index a7fcbbbe..9a9a0dc0 100644
--- a/_sources/xilinx/virtex5/clock.rst.txt
+++ b/_sources/xilinx/virtex5/clock.rst.txt
@@ -132,3 +132,19 @@ IO clock nodes
 
 .. raw:: html
    :file: ../gen/tile-xc5v-HCLK_CMT.html
+
+
+I/O standard data
+=================
+
+.. raw:: html
+   :file: ../gen/xc5v-iostd-lvdsbias.html
+
+.. raw:: html
+   :file: ../gen/xc5v-iostd-dci-lvdiv2.html
+
+.. raw:: html
+   :file: ../gen/xc5v-iostd-dci-mask-term-vcc.html
+
+.. raw:: html
+   :file: ../gen/xc5v-iostd-dci-mask-term-split.html
diff --git a/_sources/xilinx/virtex5/io.rst.txt b/_sources/xilinx/virtex5/io.rst.txt
index 11629b33..0d9c6976 100644
--- a/_sources/xilinx/virtex5/io.rst.txt
+++ b/_sources/xilinx/virtex5/io.rst.txt
@@ -148,5 +148,17 @@ The ``SYSMON`` present on the device can use up to 16 IOB pairs from the left I/
 Bitstream
 =========
 
+.. raw:: html
+   :file: ../gen/xc5v-iostd-drive.html
+
+.. raw:: html
+   :file: ../gen/xc5v-iostd-slew.html
+
+.. raw:: html
+   :file: ../gen/xc5v-iostd-misc.html
+
+.. raw:: html
+   :file: ../gen/xc5v-iostd-lvds.html
+
 .. raw:: html
    :file: ../gen/tile-xc5v-IO.html
diff --git a/_sources/xilinx/virtex6/gtx.rst.txt b/_sources/xilinx/virtex6/gtx.rst.txt
new file mode 100644
index 00000000..61545daa
--- /dev/null
+++ b/_sources/xilinx/virtex6/gtx.rst.txt
@@ -0,0 +1,13 @@
+.. _virtex6-gtx:
+
+GTX transceivers
+################
+
+.. todo:: document
+
+
+Bitstream
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-GTX.html
diff --git a/_sources/xilinx/virtex6/index.rst.txt b/_sources/xilinx/virtex6/index.rst.txt
index 9ae02655..807120c9 100644
--- a/_sources/xilinx/virtex6/index.rst.txt
+++ b/_sources/xilinx/virtex6/index.rst.txt
@@ -16,4 +16,5 @@ Virtex 6
    center
    emac
    pcie
+   gtx
    config
diff --git a/objects.inv b/objects.inv
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diff --git a/searchindex.js b/searchindex.js
index 3642801f..7dd30dee 100644
--- a/searchindex.js
+++ b/searchindex.js
@@ -1 +1 @@
-Search.setIndex({"alltitles": {"AIM and FB inputs": [[14, "aim-and-fb-inputs"]], "BRAM.S3": [[45, "bram-s3"]], "BRAM.S3A": [[45, "bram-s3a"]], "BRAM.S3ADSP": [[45, "bram-s3adsp"]], "BRAM.S3E": [[45, "bram-s3e"]], "Backbone": [[55, "backbone"], [91, "backbone"]], "Bank configuration": [[14, "bank-configuration"]], "Bitstream": [[37, "bitstream"], [45, "bitstream"], [46, "bitstream"], [53, "bitstream"], [59, "bitstream"], [64, "bitstream"], [65, "bitstream"], [66, "bitstream"], [69, "bitstream"], [70, "bitstream"], [71, "bitstream"], [73, "bitstream"], [81, "bitstream"], [82, "bitstream"], [88, "bitstream"], [89, "bitstream"], [96, "bitstream"], [97, "bitstream"], [98, "bitstream"], [99, "bitstream"], [102, "bitstream"], [103, "bitstream"], [105, "bitstream"], [107, "bitstream"], [108, "bitstream"], [109, "bitstream"], [110, "bitstream"], [111, "bitstream"], [115, "bitstream"], [116, "bitstream"], [118, "bitstream"], [119, "bitstream"], [121, "bitstream"], [122, "bitstream"], [123, "bitstream"], [124, "bitstream"], [125, "bitstream"], [126, "bitstream"], [129, "bitstream"], [130, "bitstream"], [133, "bitstream"], [134, "bitstream"], [135, "bitstream"], [136, "bitstream"], [138, "bitstream"], [141, "bitstream"], [144, "bitstream"], [145, "bitstream"]], "Bitstream geometry": [[58, "bitstream-geometry"], [87, "bitstream-geometry"], [104, "bitstream-geometry"], [117, "bitstream-geometry"], [131, "bitstream-geometry"], [139, "bitstream-geometry"]], "Bitstream structure": [[1, "bitstream-structure"], [150, "bitstream-structure"]], "Bitstream structure \u2014 XC9500": [[15, "bitstream-structure-xc9500"]], "Bitstream structure \u2014 XC9500XL/XV": [[16, "bitstream-structure-xc9500xl-xv"]], "Bitstream \u2014 CLBLL": [[112, "bitstream-clbll"], [127, "bitstream-clbll"], [137, "bitstream-clbll"]], "Bitstream \u2014 CLBLM": [[112, "bitstream-clblm"], [127, "bitstream-clblm"], [137, "bitstream-clblm"]], "Bitstream \u2014 CLEXL": [[60, "bitstream-clexl"]], "Bitstream \u2014 CLEXM": [[60, "bitstream-clexm"]], "Bitstream \u2014 CLKC": [[61, "bitstream-clkc"]], "Bitstream \u2014 DCM_BUFPLL": [[61, "bitstream-dcm-bufpll"]], "Bitstream \u2014 HCLK": [[61, "bitstream-hclk"]], "Bitstream \u2014 HCLK_ROW": [[61, "bitstream-hclk-row"]], "Bitstream \u2014 INTF": [[121, "bitstream-intf"], [133, "bitstream-intf"], [141, "bitstream-intf"]], "Bitstream \u2014 INTF.BRAM": [[141, "bitstream-intf-bram"]], "Bitstream \u2014 INTF.DELAY": [[121, "bitstream-intf-delay"], [133, "bitstream-intf-delay"], [141, "bitstream-intf-delay"]], "Bitstream \u2014 IOI tile": [[68, "bitstream-ioi-tile"]], "Bitstream \u2014 LLH tiles": [[55, "bitstream-llh-tiles"]], "Bitstream \u2014 LLV tiles": [[55, "bitstream-llv-tiles"]], "Bitstream \u2014 PCILOGICSE": [[61, "bitstream-pcilogicse"]], "Bitstream \u2014 PLL_BUFPLL_B": [[61, "bitstream-pll-bufpll-b"]], "Bitstream \u2014 PLL_BUFPLL_OUT0": [[61, "bitstream-pll-bufpll-out0"]], "Bitstream \u2014 PLL_BUFPLL_OUT1": [[61, "bitstream-pll-bufpll-out1"]], "Bitstream \u2014 PLL_BUFPLL_T": [[61, "bitstream-pll-bufpll-t"]], "Bitstream \u2014 PMVIOB": [[126, "bitstream-pmviob"]], "Bitstream \u2014 PowerPC hole tiles": [[91, "bitstream-powerpc-hole-tiles"]], "Bitstream \u2014 bottom tile": [[61, "bitstream-bottom-tile"]], "Bitstream \u2014 bottom tiles": [[38, "bitstream-bottom-tiles"], [47, "bitstream-bottom-tiles"], [83, "bitstream-bottom-tiles"]], "Bitstream \u2014 column bottom": [[72, "bitstream-column-bottom"]], "Bitstream \u2014 column top": [[72, "bitstream-column-top"]], "Bitstream \u2014 interconnect tiles": [[42, "bitstream-interconnect-tiles"], [55, "bitstream-interconnect-tiles"], [91, "bitstream-interconnect-tiles"]], "Bitstream \u2014 interface tile": [[107, "bitstream-interface-tile"]], "Bitstream \u2014 interface tiles": [[55, "bitstream-interface-tiles"], [68, "bitstream-interface-tiles"], [91, "bitstream-interface-tiles"]], "Bitstream \u2014 left side": [[72, "bitstream-left-side"]], "Bitstream \u2014 left tile": [[61, "bitstream-left-tile"]], "Bitstream \u2014 left tiles": [[47, "bitstream-left-tiles"]], "Bitstream \u2014 middle": [[72, "bitstream-middle"]], "Bitstream \u2014 normal tile": [[68, "bitstream-normal-tile"]], "Bitstream \u2014 right side": [[72, "bitstream-right-side"]], "Bitstream \u2014 right tile": [[61, "bitstream-right-tile"]], "Bitstream \u2014 right tiles": [[47, "bitstream-right-tiles"]], "Bitstream \u2014 terminator tiles": [[91, "bitstream-terminator-tiles"]], "Bitstream \u2014 top tile": [[61, "bitstream-top-tile"]], "Bitstream \u2014 top tiles": [[38, "bitstream-top-tiles"], [47, "bitstream-top-tiles"], [83, "bitstream-top-tiles"]], "Blank check \u2014 XC9500XL/XV": [[35, "blank-check-xc9500xl-xv"]], "Block RAM": [[45, "block-ram"], [59, "block-ram"], [72, "block-ram"], [96, "block-ram"], [110, "block-ram"], [125, "block-ram"], [136, "block-ram"]], "Block RAM \u2014 Virtex 2, Spartan 3": [[81, "block-ram-virtex-2-spartan-3"]], "Bond": [[17, "bond"], [151, "bond"]], "Boundary scan register": [[13, "boundary-scan-register"], [35, "boundary-scan-register"], [161, "boundary-scan-register"]], "CCLK_FREQ": [[49, "cclk-freq"], [62, "cclk-freq"]], "CLKB": [[74, "clkb"], [149, "clkb"]], "CLKB.FC": [[38, "clkb-fc"]], "CLKB.S3": [[47, "clkb-s3"]], "CLKB.S3A": [[47, "clkb-s3a"]], "CLKB.S3E": [[47, "clkb-s3e"]], "CLKB.V2": [[83, "clkb-v2"]], "CLKB.V2P": [[83, "clkb-v2p"]], "CLKB.V2PX": [[83, "clkb-v2px"]], "CLKB_2DLL": [[74, "clkb-2dll"]], "CLKB_4DLL": [[74, "clkb-4dll"]], "CLKH": [[149, "clkh"]], "CLKL": [[80, "clkl"], [149, "clkl"]], "CLKL.S3A": [[47, "clkl-s3a"]], "CLKL.S3E": [[47, "clkl-s3e"]], "CLKR": [[80, "clkr"], [149, "clkr"]], "CLKR.S3A": [[47, "clkr-s3a"]], "CLKR.S3E": [[47, "clkr-s3e"]], "CLKT": [[74, "clkt"], [149, "clkt"]], "CLKT.FC": [[38, "clkt-fc"]], "CLKT.S3": [[47, "clkt-s3"]], "CLKT.S3A": [[47, "clkt-s3a"]], "CLKT.S3E": [[47, "clkt-s3e"]], "CLKT.V2": [[83, "clkt-v2"]], "CLKT.V2P": [[83, "clkt-v2p"]], "CLKT.V2PX": [[83, "clkt-v2px"]], "CLKT_2DLL": [[74, "clkt-2dll"]], "CLKT_4DLL": [[74, "clkt-4dll"]], "CLKV": [[149, "clkv"]], "CLKV.CLKV": [[74, "clkv-clkv"]], "CLKV.GCLKV": [[74, "clkv-gclkv"]], "CLKV_BRAM_BOT": [[74, "clkv-bram-bot"]], "CLKV_BRAM_TOP": [[74, "clkv-bram-top"]], "CLK_CMT_B": [[113, "clk-cmt-b"]], "CLK_CMT_T": [[113, "clk-cmt-t"]], "CLK_DCM_B": [[100, "clk-dcm-b"]], "CLK_DCM_T": [[100, "clk-dcm-t"]], "CLK_HROW": [[100, "clk-hrow"], [113, "clk-hrow"]], "CLK_IOB_B": [[100, "clk-iob-b"], [113, "clk-iob-b"]], "CLK_IOB_T": [[100, "clk-iob-t"], [113, "clk-iob-t"]], "CLK_MGT_B": [[113, "clk-mgt-b"]], "CLK_MGT_T": [[113, "clk-mgt-t"]], "CLK_TERM_B": [[100, "clk-term-b"]], "CLK_TERM_T": [[100, "clk-term-t"]], "CNR.BL": [[76, "cnr-bl"], [146, "cnr-bl"]], "CNR.BR": [[76, "cnr-br"], [146, "cnr-br"]], "CNR.TL": [[76, "cnr-tl"], [146, "cnr-tl"]], "CNR.TR": [[76, "cnr-tr"], [146, "cnr-tr"]], "COR": [[75, "cor"], [84, "cor"], [101, "cor"], [114, "cor"], [128, "cor"]], "COR.FC": [[39, "cor-fc"]], "COR.S3": [[48, "cor-s3"]], "COR.S3E": [[48, "cor-s3e"]], "COR1": [[62, "cor1"], [114, "cor1"], [128, "cor1"]], "COR1.S3A": [[49, "cor1-s3a"]], "COR2": [[62, "cor2"]], "COR2.S3A": [[49, "cor2-s3a"]], "CTL": [[62, "ctl"], [75, "ctl"], [84, "ctl"], [101, "ctl"], [114, "ctl"], [128, "ctl"]], "CTL.S3": [[39, "ctl-s3"], [48, "ctl-s3"]], "CTL.S3A": [[49, "ctl-s3a"]], "CTL1": [[128, "ctl1"]], "Carry logic": [[46, "carry-logic"], [82, "carry-logic"]], "Center column": [[104, "center-column"], [117, "center-column"], [131, "center-column"]], "Center column and configuration center": [[139, "center-column-and-configuration-center"]], "Clock Companion Modules": [[97, "clock-companion-modules"]], "Clock divider": [[14, "clock-divider"]], "Clock interconnect": [[38, "clock-interconnect"], [47, "clock-interconnect"], [61, "clock-interconnect"], [74, "clock-interconnect"], [83, "clock-interconnect"], [100, "clock-interconnect"], [113, "clock-interconnect"]], "Clock rows": [[58, "clock-rows"], [87, "clock-rows"]], "Clock source \u2014 left and right": [[47, "clock-source-left-and-right"]], "Clock source \u2014 spine bottom and top": [[38, "clock-source-spine-bottom-and-top"], [47, "clock-source-spine-bottom-and-top"], [83, "clock-source-spine-bottom-and-top"]], "Clock spine": [[87, "clock-spine"]], "Clock spine top and bottom": [[91, "clock-spine-top-and-bottom"]], "Configurable Logic Block": [[37, "configurable-logic-block"], [46, "configurable-logic-block"], [60, "configurable-logic-block"], [73, "configurable-logic-block"], [82, "configurable-logic-block"], [99, "configurable-logic-block"], [112, "configurable-logic-block"], [127, "configurable-logic-block"], [137, "configurable-logic-block"], [145, "configurable-logic-block"]], "Configuration Center": [[98, "configuration-center"], [111, "configuration-center"], [126, "configuration-center"]], "Configuration pull-ups": [[36, "configuration-pull-ups"]], "Configuration registers": [[39, "configuration-registers"], [62, "configuration-registers"], [75, "configuration-registers"], [84, "configuration-registers"], [101, "configuration-registers"], [114, "configuration-registers"], [128, "configuration-registers"]], "Configuration registers \u2014 Spartan 3, Spartan 3E": [[48, "configuration-registers-spartan-3-spartan-3e"]], "Configuration registers \u2014 Spartan 3A and 3A DSP": [[49, "configuration-registers-spartan-3a-and-3a-dsp"]], "Contents:": [[0, null], [10, null], [11, null], [32, null], [33, null], [41, null], [44, null], [54, null], [67, null], [78, null], [90, null], [106, null], [120, null], [132, null], [140, null], [147, null], [158, null], [159, null]], "Corners": [[40, "corners"], [50, "corners"], [63, "corners"], [76, "corners"], [85, "corners"], [146, "corners"]], "DCM output bus": [[83, "dcm-output-bus"]], "DCM.S3": [[51, "dcm-s3"]], "DCM.S3E.BL": [[52, "dcm-s3e-bl"]], "DCM.S3E.BR": [[52, "dcm-s3e-br"]], "DCM.S3E.LB": [[52, "dcm-s3e-lb"]], "DCM.S3E.LT": [[52, "dcm-s3e-lt"]], "DCM.S3E.RB": [[52, "dcm-s3e-rb"]], "DCM.S3E.RT": [[52, "dcm-s3e-rt"]], "DCM.S3E.TL": [[52, "dcm-s3e-tl"]], "DCM.S3E.TR": [[52, "dcm-s3e-tr"]], "DCM.V2": [[86, "dcm-v2"]], "DCM.V2P": [[86, "dcm-v2p"]], "DCMCONN.BOT": [[83, "dcmconn-bot"]], "DCMCONN.TOP": [[83, "dcmconn-top"]], "DESKEW_ADJUST": [[51, "deskew-adjust"], [52, "deskew-adjust"], [86, "deskew-adjust"]], "DLL.BOT": [[77, "dll-bot"]], "DLL.TOP": [[77, "dll-top"]], "DLLP.BOT": [[77, "dllp-bot"]], "DLLP.TOP": [[77, "dllp-top"]], "DLLS.BOT": [[77, "dlls-bot"]], "DLLS.TOP": [[77, "dlls-top"]], "DSP": [[53, "dsp"], [65, "dsp"], [103, "dsp"], [115, "dsp"], [129, "dsp"], [138, "dsp"]], "Database schema": [[17, "database-schema"], [151, "database-schema"]], "Database \u2014 devices": [[10, "database-devices"], [32, "database-devices"], [158, "database-devices"]], "Default option attributes": [[47, "default-option-attributes"]], "Default option values": [[45, "default-option-values"]], "Delay Locked Loop": [[77, "delay-locked-loop"]], "Device": [[17, "device"], [151, "device"]], "Device geometry": [[58, "device-geometry"], [87, "device-geometry"], [104, "device-geometry"], [117, "device-geometry"], [131, "device-geometry"], [139, "device-geometry"]], "Device pins": [[12, "device-pins"], [34, "device-pins"], [160, "device-pins"]], "Device structure": [[14, "device-structure"], [36, "device-structure"], [162, "device-structure"]], "Device table": [[56, "device-table"], [92, "device-table"]], "Devices": [[12, "devices"], [34, "devices"], [160, "devices"]], "Digital Clock Managers": [[86, "digital-clock-managers"], [102, "digital-clock-managers"]], "Digital Clock Managers \u2014 Spartan 3": [[51, "digital-clock-managers-spartan-3"]], "Digital Clock Managers \u2014 Spartan 3E, 3A": [[52, "digital-clock-managers-spartan-3e-3a"]], "Digital clock manager": [[64, "digital-clock-manager"]], "Dual-port 16\u00d7X RAM": [[46, "dual-port-16x-ram"], [82, "dual-port-16x-ram"]], "Dual-port 32\u00d7X RAM": [[82, "dual-port-32x-ram"]], "Dual-port 64\u00d71 RAM": [[82, "dual-port-641-ram"]], "ECC": [[104, "ecc"], [117, "ecc"], [131, "ecc"], [139, "ecc"]], "ECC mode": [[96, "ecc-mode"]], "EYE_MASK": [[62, "eye-mask"]], "Entering and exiting ISP mode \u2014 XC9500": [[35, "entering-and-exiting-isp-mode-xc9500"]], "Entering and exiting ISP mode \u2014 XC9500XL/XV": [[35, "entering-and-exiting-isp-mode-xc9500xl-xv"]], "Erasing fuses \u2014 XC9500": [[35, "erasing-fuses-xc9500"]], "Erasing fuses \u2014 XC9500XL/XV": [[35, "erasing-fuses-xc9500xl-xv"]], "Ethernet MACs": [[116, "ethernet-macs"], [130, "ethernet-macs"]], "FB columns and rows": [[162, "fb-columns-and-rows"]], "FB global fuses": [[36, "fb-global-fuses"]], "FCLK networks": [[162, "fclk-networks"]], "FIFO mode": [[96, "fifo-mode"]], "FPGAcore": [[41, "fpgacore"]], "Flip-flop": [[36, "flip-flop"]], "Frequency": [[35, "frequency"]], "Fuses \u2014 FB inputs": [[15, "fuses-fb-inputs"], [16, "fuses-fb-inputs"]], "Fuses \u2014 FBs": [[150, "fuses-fbs"]], "Fuses \u2014 IMUX bits": [[150, "fuses-imux-bits"]], "Fuses \u2014 UIM wire-AND": [[15, "fuses-uim-wire-and"]], "Fuses \u2014 global bits": [[150, "fuses-global-bits"]], "Fuses \u2014 input buffer enable": [[15, "fuses-input-buffer-enable"]], "Fuses \u2014 macrocells": [[15, "fuses-macrocells"], [16, "fuses-macrocells"], [150, "fuses-macrocells"]], "Fuses \u2014 per-FB bits and globals": [[15, "fuses-per-fb-bits-and-globals"], [16, "fuses-per-fb-bits-and-globals"]], "Fuses \u2014 product and sum terms": [[150, "fuses-product-and-sum-terms"]], "Fuses \u2014 product terms": [[15, "fuses-product-terms"], [16, "fuses-product-terms"]], "GCLKC": [[83, "gclkc"]], "GCLKC.B": [[83, "gclkc-b"]], "GCLKC.T": [[83, "gclkc-t"]], "GCLKH": [[38, "gclkh"], [47, "gclkh"], [83, "gclkh"]], "GCLKH.N": [[47, "gclkh-n"]], "GCLKH.S": [[47, "gclkh-s"]], "GCLKH.UNI": [[47, "gclkh-uni"]], "GCLKH.UNI.N": [[47, "gclkh-uni-n"]], "GCLKH.UNI.S": [[47, "gclkh-uni-s"]], "GCLKVM.S3": [[38, "gclkvm-s3"], [47, "gclkvm-s3"]], "GCLKVM.S3E": [[47, "gclkvm-s3e"]], "GENERAL5": [[62, "general5"]], "GENERAL[12]": [[49, "general-12"], [62, "general-12"]], "GENERAL[34]": [[62, "general-34"]], "GIGABIT.B": [[88, "gigabit-b"]], "GIGABIT.T": [[88, "gigabit-t"]], "GIGABIT10.B": [[89, "gigabit10-b"]], "GIGABIT10.T": [[89, "gigabit10-t"]], "GTP and GTX right column holes": [[139, "gtp-and-gtx-right-column-holes"]], "GTP transceivers": [[118, "gtp-transceivers"]], "GTX transceivers": [[119, "gtx-transceivers"]], "General Interconnect": [[107, "general-interconnect"]], "General interconnect": [[42, "general-interconnect"], [55, "general-interconnect"], [68, "general-interconnect"], [91, "general-interconnect"]], "General structure": [[58, "general-structure"], [87, "general-structure"], [104, "general-structure"], [117, "general-structure"], [131, "general-structure"], [139, "general-structure"]], "Global bits": [[2, "global-bits"], [3, "global-bits"], [4, "global-bits"], [5, "global-bits"], [6, "global-bits"], [7, "global-bits"], [8, "global-bits"], [9, "global-bits"], [152, "global-bits"], [153, "global-bits"], [154, "global-bits"], [155, "global-bits"], [156, "global-bits"], [157, "global-bits"]], "Global networks": [[14, "global-networks"]], "Global networks \u2014 XC9500": [[36, "global-networks-xc9500"]], "Global networks \u2014 XC9500XL/XV": [[36, "global-networks-xc9500xl-xv"]], "HCLK": [[100, "hclk"], [113, "hclk"]], "HCLK_CENTER": [[100, "hclk-center"]], "HCLK_CENTER_ABOVE_CFG": [[100, "hclk-center-above-cfg"]], "HCLK_CMT": [[113, "hclk-cmt"]], "HCLK_CMT_IOI": [[113, "hclk-cmt-ioi"]], "HCLK_DCM": [[100, "hclk-dcm"]], "HCLK_DCMIOB": [[100, "hclk-dcmiob"]], "HCLK_IOBDCM": [[100, "hclk-iobdcm"]], "HCLK_IOI": [[113, "hclk-ioi"]], "HCLK_IOIS_DCI": [[100, "hclk-iois-dci"]], "HCLK_IOIS_LVDS": [[100, "hclk-iois-lvds"]], "HCLK_IOI_BOTCEN": [[113, "hclk-ioi-botcen"]], "HCLK_IOI_CENTER": [[113, "hclk-ioi-center"]], "HCLK_IOI_CMT": [[113, "hclk-ioi-cmt"]], "HCLK_IOI_TOPCEN": [[113, "hclk-ioi-topcen"]], "HCLK_MGT": [[100, "hclk-mgt"]], "HCLK_TERM_L": [[100, "hclk-term-l"]], "HCLK_TERM_R": [[100, "hclk-term-r"]], "HC_OPT": [[49, "hc-opt"], [62, "hc-opt"]], "Hard PCI logic": [[94, "hard-pci-logic"]], "Hard PowerPC 405 cores": [[95, "hard-powerpc-405-cores"]], "Horizontal clock spine": [[58, "horizontal-clock-spine"]], "I/O banks and special functions": [[108, "i-o-banks-and-special-functions"], [122, "i-o-banks-and-special-functions"], [134, "i-o-banks-and-special-functions"], [142, "i-o-banks-and-special-functions"]], "I/O buffer tiles": [[43, "i-o-buffer-tiles"]], "I/O buffers \u2014 Spartan 3": [[57, "i-o-buffers-spartan-3"]], "I/O buffers \u2014 Spartan 3A": [[57, "i-o-buffers-spartan-3a"]], "I/O buffers \u2014 Spartan 3E": [[57, "i-o-buffers-spartan-3e"]], "I/O buffers \u2014 Virtex": [[79, "i-o-buffers-virtex"]], "I/O buffers \u2014 Virtex 2": [[93, "i-o-buffers-virtex-2"]], "I/O buffers \u2014 Virtex 2 Pro": [[93, "i-o-buffers-virtex-2-pro"]], "I/O buffers \u2014 Virtex E": [[79, "i-o-buffers-virtex-e"]], "I/O data \u2014 Spartan 3": [[50, "i-o-data-spartan-3"]], "I/O data \u2014 Spartan 3A": [[50, "i-o-data-spartan-3a"]], "I/O data \u2014 Spartan 3E": [[50, "i-o-data-spartan-3e"]], "I/O data \u2014 Virtex 2": [[85, "i-o-data-virtex-2"]], "I/O data \u2014 Virtex 2 Pro": [[85, "i-o-data-virtex-2-pro"]], "I/O interface": [[43, "i-o-interface"], [57, "i-o-interface"], [93, "i-o-interface"]], "I/O pins": [[2, "i-o-pins"], [3, "i-o-pins"], [4, "i-o-pins"], [5, "i-o-pins"], [6, "i-o-pins"], [7, "i-o-pins"], [8, "i-o-pins"], [9, "i-o-pins"], [18, "i-o-pins"], [19, "i-o-pins"], [20, "i-o-pins"], [21, "i-o-pins"], [22, "i-o-pins"], [23, "i-o-pins"], [24, "i-o-pins"], [25, "i-o-pins"], [26, "i-o-pins"], [27, "i-o-pins"], [28, "i-o-pins"], [29, "i-o-pins"], [30, "i-o-pins"], [31, "i-o-pins"], [152, "i-o-pins"], [153, "i-o-pins"], [154, "i-o-pins"], [155, "i-o-pins"], [156, "i-o-pins"], [157, "i-o-pins"]], "I/O standard data": [[100, "i-o-standard-data"]], "IDCODE": [[35, "idcode"], [161, "idcode"]], "IMUX bits": [[2, "imux-bits"], [3, "imux-bits"], [4, "imux-bits"], [5, "imux-bits"], [6, "imux-bits"], [7, "imux-bits"], [8, "imux-bits"], [9, "imux-bits"], [18, "imux-bits"], [19, "imux-bits"], [20, "imux-bits"], [21, "imux-bits"], [22, "imux-bits"], [23, "imux-bits"], [24, "imux-bits"], [25, "imux-bits"], [26, "imux-bits"], [27, "imux-bits"], [28, "imux-bits"], [29, "imux-bits"], [30, "imux-bits"], [31, "imux-bits"], [152, "imux-bits"], [153, "imux-bits"], [154, "imux-bits"], [155, "imux-bits"], [156, "imux-bits"], [157, "imux-bits"]], "INT.BRAM": [[91, "int-bram"]], "INT.BRAM.S3": [[55, "int-bram-s3"]], "INT.BRAM.S3A.03": [[55, "int-bram-s3a-03"]], "INT.BRAM.S3A.12": [[55, "int-bram-s3a-12"]], "INT.BRAM.S3ADSP": [[55, "int-bram-s3adsp"]], "INT.BRAM.S3E": [[55, "int-bram-s3e"]], "INT.CLB": [[42, "int-clb"], [55, "int-clb"], [91, "int-clb"]], "INT.CNR": [[91, "int-cnr"]], "INT.DCM": [[55, "int-dcm"]], "INT.DCM.S3E.DUMMY": [[55, "int-dcm-s3e-dummy"]], "INT.DCM.V2": [[91, "int-dcm-v2"]], "INT.DCM.V2P": [[91, "int-dcm-v2p"]], "INT.GT.CLKPAD": [[91, "int-gt-clkpad"]], "INT.IOI": [[91, "int-ioi"]], "INT.IOI.CLK_B": [[91, "int-ioi-clk-b"]], "INT.IOI.CLK_T": [[91, "int-ioi-clk-t"]], "INT.IOI.FC": [[42, "int-ioi-fc"]], "INT.IOI.S3": [[55, "int-ioi-s3"]], "INT.IOI.S3A.LR": [[55, "int-ioi-s3a-lr"]], "INT.IOI.S3A.TB": [[55, "int-ioi-s3a-tb"]], "INT.IOI.S3E": [[55, "int-ioi-s3e"]], "INT.PPC": [[91, "int-ppc"]], "INTF": [[68, "intf"]], "INTF.CMT": [[68, "intf-cmt"]], "INTF.CMT.IOI": [[68, "intf-cmt-ioi"]], "INTF.DSP": [[55, "intf-dsp"]], "INTF.GT.B0": [[91, "intf-gt-b0"]], "INTF.GT.B123": [[91, "intf-gt-b123"]], "INTF.GT.BCLKPAD": [[91, "intf-gt-bclkpad"]], "INTF.GT.T0": [[91, "intf-gt-t0"]], "INTF.GT.T123": [[91, "intf-gt-t123"]], "INTF.GT.TCLKPAD": [[91, "intf-gt-tclkpad"]], "INTF.IOI": [[68, "intf-ioi"]], "INTF.PPC": [[91, "intf-ppc"]], "IO and transceiver placement": [[139, "io-and-transceiver-placement"]], "IO banks and IO buffers": [[58, "io-banks-and-io-buffers"], [87, "io-banks-and-io-buffers"]], "IO clock nodes": [[100, "io-clock-nodes"], [113, "io-clock-nodes"]], "IO.B": [[79, "io-b"], [148, "io-b"]], "IO.L": [[79, "io-l"], [148, "io-l"]], "IO.R": [[79, "io-r"], [148, "io-r"]], "IO.T": [[79, "io-t"], [148, "io-t"]], "IOB.B.V": [[79, "iob-b-v"]], "IOB.B.VE": [[79, "iob-b-ve"]], "IOB.L.V": [[79, "iob-l-v"]], "IOB.L.VE": [[79, "iob-l-ve"]], "IOB.R.V": [[79, "iob-r-v"]], "IOB.R.VE": [[79, "iob-r-ve"]], "IOB.T.V": [[79, "iob-t-v"]], "IOB.T.VE": [[79, "iob-t-ve"]], "IOBS.FC.B": [[43, "iobs-fc-b"]], "IOBS.FC.L": [[43, "iobs-fc-l"]], "IOBS.FC.R": [[43, "iobs-fc-r"]], "IOBS.FC.T": [[43, "iobs-fc-t"]], "IOBS.S3.B2": [[57, "iobs-s3-b2"]], "IOBS.S3.L1": [[57, "iobs-s3-l1"]], "IOBS.S3.R1": [[57, "iobs-s3-r1"]], "IOBS.S3.T2": [[57, "iobs-s3-t2"]], "IOBS.S3A.B2": [[57, "iobs-s3a-b2"]], "IOBS.S3A.L4": [[57, "iobs-s3a-l4"]], "IOBS.S3A.R4": [[57, "iobs-s3a-r4"]], "IOBS.S3A.T2": [[57, "iobs-s3a-t2"]], "IOBS.S3E.B1": [[57, "iobs-s3e-b1"]], "IOBS.S3E.B2": [[57, "iobs-s3e-b2"]], "IOBS.S3E.B3": [[57, "iobs-s3e-b3"]], "IOBS.S3E.B4": [[57, "iobs-s3e-b4"]], "IOBS.S3E.L1": [[57, "iobs-s3e-l1"]], "IOBS.S3E.L2": [[57, "iobs-s3e-l2"]], "IOBS.S3E.L3": [[57, "iobs-s3e-l3"]], "IOBS.S3E.L4": [[57, "iobs-s3e-l4"]], "IOBS.S3E.R1": [[57, "iobs-s3e-r1"]], "IOBS.S3E.R2": [[57, "iobs-s3e-r2"]], "IOBS.S3E.R3": [[57, "iobs-s3e-r3"]], "IOBS.S3E.R4": [[57, "iobs-s3e-r4"]], "IOBS.S3E.T1": [[57, "iobs-s3e-t1"]], "IOBS.S3E.T2": [[57, "iobs-s3e-t2"]], "IOBS.S3E.T3": [[57, "iobs-s3e-t3"]], "IOBS.S3E.T4": [[57, "iobs-s3e-t4"]], "IOBS.V2.B.L2": [[93, "iobs-v2-b-l2"]], "IOBS.V2.B.R2": [[93, "iobs-v2-b-r2"]], "IOBS.V2.L.B2": [[93, "iobs-v2-l-b2"]], "IOBS.V2.L.T2": [[93, "iobs-v2-l-t2"]], "IOBS.V2.R.B2": [[93, "iobs-v2-r-b2"]], "IOBS.V2.R.T2": [[93, "iobs-v2-r-t2"]], "IOBS.V2.T.L2": [[93, "iobs-v2-t-l2"]], "IOBS.V2.T.R2": [[93, "iobs-v2-t-r2"]], "IOBS.V2P.B.L1": [[93, "iobs-v2p-b-l1"]], "IOBS.V2P.B.L1.ALT": [[93, "iobs-v2p-b-l1-alt"]], "IOBS.V2P.B.L2": [[93, "iobs-v2p-b-l2"]], "IOBS.V2P.B.R1": [[93, "iobs-v2p-b-r1"]], "IOBS.V2P.B.R1.ALT": [[93, "iobs-v2p-b-r1-alt"]], "IOBS.V2P.B.R2": [[93, "iobs-v2p-b-r2"]], "IOBS.V2P.B.R2.CLK": [[93, "iobs-v2p-b-r2-clk"]], "IOBS.V2P.L.B2": [[93, "iobs-v2p-l-b2"]], "IOBS.V2P.L.T2": [[93, "iobs-v2p-l-t2"]], "IOBS.V2P.R.B2": [[93, "iobs-v2p-r-b2"]], "IOBS.V2P.R.T2": [[93, "iobs-v2p-r-t2"]], "IOBS.V2P.T.L1": [[93, "iobs-v2p-t-l1"]], "IOBS.V2P.T.L1.ALT": [[93, "iobs-v2p-t-l1-alt"]], "IOBS.V2P.T.L2": [[93, "iobs-v2p-t-l2"]], "IOBS.V2P.T.R1": [[93, "iobs-v2p-t-r1"]], "IOBS.V2P.T.R1.ALT": [[93, "iobs-v2p-t-r1-alt"]], "IOBS.V2P.T.R2": [[93, "iobs-v2p-t-r2"]], "IOBS.V2P.T.R2.CLK": [[93, "iobs-v2p-t-r2-clk"]], "IOI": [[93, "ioi"]], "IOI.CLK_B": [[93, "ioi-clk-b"]], "IOI.CLK_T": [[93, "ioi-clk-t"]], "IOI.FC": [[43, "ioi-fc"]], "IOI.S3": [[57, "ioi-s3"]], "IOI.S3A.B": [[57, "ioi-s3a-b"]], "IOI.S3A.LR": [[57, "ioi-s3a-lr"]], "IOI.S3A.T": [[57, "ioi-s3a-t"]], "IOI.S3E": [[57, "ioi-s3e"]], "IR": [[13, "ir"], [35, "ir"], [161, "ir"]], "ISP DR registers \u2014 XC9500": [[35, "isp-dr-registers-xc9500"]], "ISP DR registers \u2014 XC9500XL/XV": [[35, "isp-dr-registers-xc9500xl-xv"]], "ISP instructions": [[13, "isp-instructions"], [161, "isp-instructions"]], "ISP instructions \u2014 XC9500": [[35, "isp-instructions-xc9500"]], "ISP instructions \u2014 XC9500XL/XV": [[35, "isp-instructions-xc9500xl-xv"]], "Input / Output": [[43, "input-output"], [57, "input-output"], [93, "input-output"]], "Input multiplexers": [[55, "input-multiplexers"], [91, "input-multiplexers"]], "Input/Output": [[79, "input-output"], [108, "input-output"], [122, "input-output"], [134, "input-output"], [142, "input-output"], [148, "input-output"]], "Input/output buffer": [[14, "input-output-buffer"], [36, "input-output-buffer"], [162, "input-output-buffer"]], "Interconnect": [[121, "interconnect"], [133, "interconnect"], [141, "interconnect"]], "Introduction": [[12, "introduction"], [34, "introduction"], [56, "introduction"], [92, "introduction"], [160, "introduction"]], "JED bits": [[151, "jed-bits"]], "JED format mapping": [[15, "jed-format-mapping"], [16, "jed-format-mapping"]], "JED mapping": [[2, "jed-mapping"], [3, "jed-mapping"], [4, "jed-mapping"], [4, "id1"], [5, "jed-mapping"], [5, "id1"], [6, "jed-mapping"], [7, "jed-mapping"], [8, "jed-mapping"], [8, "id1"], [9, "jed-mapping"], [9, "id1"], [150, "jed-mapping"], [152, "jed-mapping"], [153, "jed-mapping"], [154, "jed-mapping"], [155, "jed-mapping"], [156, "jed-mapping"], [157, "jed-mapping"]], "JED mapping \u2014 MCs with IOBs": [[2, "jed-mapping-mcs-with-iobs"], [3, "jed-mapping-mcs-with-iobs"], [6, "jed-mapping-mcs-with-iobs"], [7, "jed-mapping-mcs-with-iobs"]], "JED mapping \u2014 MCs without IOBs": [[2, "jed-mapping-mcs-without-iobs"], [3, "jed-mapping-mcs-without-iobs"], [6, "jed-mapping-mcs-without-iobs"], [7, "jed-mapping-mcs-without-iobs"]], "JED mapping \u2014 macrocells with IOB": [[150, "jed-mapping-macrocells-with-iob"]], "JED mapping \u2014 macrocells without IOB": [[150, "jed-mapping-macrocells-without-iob"]], "JED structure": [[150, "jed-structure"]], "JTAG interface": [[13, "jtag-interface"], [35, "jtag-interface"], [161, "jtag-interface"]], "LL.FC": [[40, "ll-fc"]], "LL.S3": [[50, "ll-s3"]], "LL.S3A": [[50, "ll-s3a"]], "LL.S3E": [[50, "ll-s3e"]], "LL.V2": [[85, "ll-v2"]], "LL.V2P": [[85, "ll-v2p"]], "LLH": [[55, "llh"]], "LLH.CLKB.S3A": [[55, "llh-clkb-s3a"]], "LLH.CLKT.S3A": [[55, "llh-clkt-s3a"]], "LLV.S3A": [[55, "llv-s3a"]], "LLV.S3E": [[55, "llv-s3e"]], "LR.FC": [[40, "lr-fc"]], "LR.S3": [[50, "lr-s3"]], "LR.S3A": [[50, "lr-s3a"]], "LR.S3E": [[50, "lr-s3e"]], "LR.V2": [[85, "lr-v2"]], "LR.V2P": [[85, "lr-v2p"]], "LUT RAM": [[46, "lut-ram"], [82, "lut-ram"]], "LUTs": [[46, "luts"], [82, "luts"]], "Local control terms": [[162, "local-control-terms"]], "Long line splitters": [[55, "long-line-splitters"]], "Lower left": [[40, "lower-left"], [50, "lower-left"], [63, "lower-left"], [85, "lower-left"]], "Lower right": [[40, "lower-right"], [50, "lower-right"], [63, "lower-right"], [85, "lower-right"]], "MC bits": [[2, "mc-bits"], [3, "mc-bits"], [4, "mc-bits"], [5, "mc-bits"], [6, "mc-bits"], [7, "mc-bits"], [8, "mc-bits"], [9, "mc-bits"]], "MGT clock repeater": [[100, "mgt-clock-repeater"], [113, "mgt-clock-repeater"]], "MODE": [[49, "mode"], [62, "mode"]], "Macrocell and IOB outputs": [[14, "macrocell-and-iob-outputs"], [162, "macrocell-and-iob-outputs"]], "Macrocell output \u2014 XC9500": [[36, "macrocell-output-xc9500"]], "Macrocell output \u2014 XC9500XL/XV": [[36, "macrocell-output-xc9500xl-xv"]], "Memory Controller Block": [[69, "memory-controller-block"]], "Middle GTP holes": [[139, "middle-gtp-holes"]], "Misc configuration": [[14, "misc-configuration"], [36, "misc-configuration"], [162, "misc-configuration"]], "Multi-gigabit transceivers": [[66, "multi-gigabit-transceivers"], [105, "multi-gigabit-transceivers"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro": [[88, "multi-gigabit-transceivers-virtex-2-pro"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro X": [[89, "multi-gigabit-transceivers-virtex-2-pro-x"]], "Output multiplexers": [[82, "output-multiplexers"]], "Output multiplexers \u2014 Spartan 3": [[46, "output-multiplexers-spartan-3"]], "Output multiplexers \u2014 Virtex 4": [[46, "output-multiplexers-virtex-4"]], "Overview": [[14, "overview"], [36, "overview"], [162, "overview"]], "PCI Express": [[70, "pci-express"]], "PCI Express Gen2 cores": [[143, "pci-express-gen2-cores"]], "PCI Express Gen3 cores": [[144, "pci-express-gen3-cores"]], "PCI Express cores": [[123, "pci-express-cores"], [135, "pci-express-cores"]], "PCI Express holes": [[139, "pci-express-holes"]], "PCI Logic": [[80, "pci-logic"]], "PCI logic": [[87, "pci-logic"]], "PCIE_L": [[143, "pcie-l"]], "PCIE_R": [[143, "pcie-r"]], "PCI_CE_DELAY": [[61, "pci-ce-delay"]], "PMA_SPEED values": [[89, "pma-speed-values"]], "POWERDOWN": [[49, "powerdown"], [62, "powerdown"]], "PPC.E": [[91, "ppc-e"]], "PPC.N": [[91, "ppc-n"]], "PPC.S": [[91, "ppc-s"]], "PPC.W": [[91, "ppc-w"]], "PT import/export": [[36, "pt-import-export"]], "PU_GTS": [[49, "pu-gts"], [62, "pu-gts"]], "PU_GWE": [[49, "pu-gwe"], [62, "pu-gwe"]], "Packages": [[12, "packages"], [34, "packages"], [160, "packages"]], "Part": [[17, "part"], [151, "part"]], "Phase-locked loop": [[71, "phase-locked-loop"]], "PowerPC cores": [[124, "powerpc-cores"]], "PowerPC holes": [[87, "powerpc-holes"], [91, "powerpc-holes"], [104, "powerpc-holes"], [117, "powerpc-holes"]], "Primary vertical clock spine": [[58, "primary-vertical-clock-spine"]], "Primitive outputs": [[55, "primitive-outputs"], [91, "primitive-outputs"]], "Processing system": [[139, "processing-system"]], "Product terms": [[14, "product-terms"], [36, "product-terms"], [162, "product-terms"]], "Programming fuses \u2014 XC9500": [[35, "programming-fuses-xc9500"]], "Programming fuses \u2014 XC9500XL/XV": [[35, "programming-fuses-xc9500xl-xv"]], "Programming sequence": [[13, "programming-sequence"], [35, "programming-sequence"], [161, "programming-sequence"]], "Project Combine": [[0, "project-combine"]], "RANDOR": [[37, "randor"], [46, "randor"]], "RANDOR_INIT": [[37, "randor-init"], [46, "randor-init"]], "RESERVED_ANDOR": [[37, "reserved-andor"], [46, "reserved-andor"]], "Reading fuses \u2014 XC9500": [[35, "reading-fuses-xc9500"]], "Reading fuses \u2014 XC9500XL/XV": [[35, "reading-fuses-xc9500xl-xv"]], "Register": [[14, "register"], [162, "register"]], "Registers": [[46, "registers"], [82, "registers"]], "Row clock terminators": [[100, "row-clock-terminators"]], "SEU_OPT": [[49, "seu-opt"], [62, "seu-opt"]], "Secondary vertical clock spines": [[58, "secondary-vertical-clock-spines"]], "Shift registers": [[46, "shift-registers"], [82, "shift-registers"]], "Single-port 128\u00d71 RAM": [[82, "single-port-1281-ram"]], "Single-port 16\u00d7X RAM": [[46, "single-port-16x-ram"], [82, "single-port-16x-ram"]], "Single-port 32\u00d7X RAM": [[46, "single-port-32x-ram"], [82, "single-port-32x-ram"]], "Single-port 64\u00d71 RAM": [[46, "single-port-641-ram"]], "Single-port 64\u00d7X RAM": [[82, "single-port-64x-ram"]], "Spartan 3": [[54, "spartan-3"]], "Spartan 3A DCMs": [[58, "spartan-3a-dcms"]], "Spartan 3A and 3A DSP BRAM columns": [[58, "spartan-3a-and-3a-dsp-bram-columns"]], "Spartan 3E BRAM columns": [[58, "spartan-3e-bram-columns"]], "Spartan 3E DCMs": [[58, "spartan-3e-dcms"]], "Spartan 6": [[67, "spartan-6"]], "Speed": [[17, "speed"], [151, "speed"]], "Speed data": [[2, "speed-data"], [3, "speed-data"], [4, "speed-data"], [5, "speed-data"], [6, "speed-data"], [7, "speed-data"], [8, "speed-data"], [9, "speed-data"], [18, "speed-data"], [19, "speed-data"], [20, "speed-data"], [21, "speed-data"], [22, "speed-data"], [23, "speed-data"], [24, "speed-data"], [25, "speed-data"], [26, "speed-data"], [27, "speed-data"], [28, "speed-data"], [29, "speed-data"], [30, "speed-data"], [31, "speed-data"], [152, "speed-data"], [153, "speed-data"], [154, "speed-data"], [155, "speed-data"], [156, "speed-data"], [157, "speed-data"]], "Spine clock terminators": [[100, "spine-clock-terminators"]], "Spine column": [[104, "spine-column"], [117, "spine-column"]], "Spine muxes \u2014 CMT": [[113, "spine-muxes-cmt"]], "Spine muxes \u2014 DCM": [[100, "spine-muxes-dcm"]], "Spine muxes \u2014 IOB": [[100, "spine-muxes-iob"], [113, "spine-muxes-iob"]], "Spine muxes \u2014 MGT": [[113, "spine-muxes-mgt"]], "Splitters": [[149, "splitters"]], "Sum of products": [[82, "sum-of-products"]], "Sum term, LUT2": [[162, "sum-term-lut2"]], "Sum term, XOR gate": [[14, "sum-term-xor-gate"], [36, "sum-term-xor-gate"]], "System monitor": [[109, "system-monitor"]], "TERM.E": [[91, "term-e"]], "TERM.N": [[91, "term-n"]], "TERM.S": [[91, "term-s"]], "TERM.W": [[91, "term-w"]], "TESTMODE": [[62, "testmode"], [128, "testmode"]], "TIMER": [[62, "timer"], [114, "timer"], [128, "timer"]], "TRIM": [[128, "trim"]], "Tables": [[71, "tables"]], "Terminators": [[55, "terminators"], [91, "terminators"]], "The BRAM bel": [[81, "the-bram-bel"]], "The CLKC clock center tile": [[38, "the-clkc-clock-center-tile"], [47, "the-clkc-clock-center-tile"]], "The CLKC_50A clock center tile": [[47, "the-clkc-50a-clock-center-tile"]], "The GCLKC clock spine distribution tiles": [[83, "the-gclkc-clock-spine-distribution-tiles"]], "The GCLKH clock row distribution tiles": [[38, "the-gclkh-clock-row-distribution-tiles"], [47, "the-gclkh-clock-row-distribution-tiles"]], "The GCLKVC clock spine distribution tiles": [[38, "the-gclkvc-clock-spine-distribution-tiles"], [47, "the-gclkvc-clock-spine-distribution-tiles"]], "The GCLKVM secondary clock center tiles": [[38, "the-gclkvm-secondary-clock-center-tiles"], [47, "the-gclkvm-secondary-clock-center-tiles"]], "The MULT bel \u2014 Spartan 3E and Spartan 3A": [[81, "the-mult-bel-spartan-3e-and-spartan-3a"]], "The MULT bel \u2014 Virtex 2 and Spartan 3": [[81, "the-mult-bel-virtex-2-and-spartan-3"]], "The clock row distribution tiles": [[83, "the-clock-row-distribution-tiles"]], "Tile": [[17, "tile"], [151, "tile"]], "Todo": [[1, "id1"], [12, "id1"], [13, "id1"], [13, "id2"], [13, "id3"], [13, "id4"], [14, "id1"], [14, "id2"], [14, "id3"], [14, "id4"], [14, "id5"], [14, "id6"], [14, "id7"], [14, "id8"], [14, "id9"], [14, "id10"], [35, "id1"], [35, "id2"], [36, "id1"], [36, "id2"], [38, "id1"], [38, "id2"], [38, "id3"], [38, "id4"], [38, "id5"], [38, "id6"], [38, "id7"], [38, "id8"], [39, "id1"], [40, "id1"], [40, "id2"], [40, "id3"], [40, "id4"], [40, "id5"], [41, "id1"], [43, "id1"], [43, "id2"], [43, "id3"], [46, "id1"], [47, "id1"], [47, "id2"], [47, "id3"], [47, "id4"], [47, "id5"], [47, "id6"], [47, "id7"], [47, "id8"], [47, "id9"], [47, "id10"], [48, "id1"], [49, "id1"], [50, "id1"], [50, "id2"], [50, "id3"], [50, "id4"], [50, "id5"], [51, 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"9_32000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9_64000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9ce_mux": 150, "9fb_group": [152, 153, 154, 155, 156, 157], "9foe2_mux": [4, 5, 8, 9], "9fsr_enabl": [2, 3, 6, 7], "9ibuf_mod": [2, 3, 6, 7], "9int": [55, 72, 79], "9lct5_inv": 150, "9reg_d_ireg": 150, "9reg_init": [2, 3, 6, 7], "9reg_mod": [4, 5, 8, 9], "9rowcolumn": [98, 100, 111, 123, 126, 143, 144], "9rowcolumn012345678910111213141516171819": 105, "9rowcolumn012345678910111213141516171819202122": [69, 70], "9rowcolumn012345678910111213141516171819202122232425": 66, "9rowcolumn0123456789101112131415161718192021222324252627": [116, 124, 130, 135], "9rowcolumn01234567891011121314151617181920212223242526272829": 143, "9rowcolumn0123456789101112131415161718192021222324252627282930": [64, 71], "9rowcolumn012345678910111213141516171819202122232425262728293031": [118, 119], "A": [12, 14, 17, 35, 36, 46, 58, 81, 82, 87, 96, 104, 117, 122, 131, 134, 139, 142, 151, 162], "AED": [12, 160], "AND": [2, 6, 7, 16, 33, 34, 35, 36, 37, 82, 162], "As": [35, 131, 162], "BY": [37, 46, 55, 73, 82, 91, 99], "For": [34, 35, 36, 55, 58, 87, 91, 104, 117, 131, 139, 162], "ISE": [35, 162], "IT": 91, "If": [35, 36, 81, 82, 96, 104, 117, 131, 134, 139, 162], "In": [15, 16, 36, 46, 55, 82, 91, 104, 108, 117, 122, 131, 134, 139, 142, 162], "It": [12, 34, 35, 36, 46, 47, 55, 58, 81, 82, 87, 91, 96, 104, 117, 131, 134, 139, 142, 151, 160, 162], "Its": [35, 81], "No": 139, "Not": [15, 16, 36, 55, 91, 162], "OR": [2, 6, 7, 36, 37], "On": [12, 15, 16, 36, 46, 47, 55, 58, 81, 87, 139, 162], "Such": [35, 55, 58, 87], "The": [12, 13, 15, 16, 17, 34, 35, 36, 37, 41, 42, 45, 46, 53, 54, 55, 56, 58, 65, 82, 87, 90, 91, 92, 96, 99, 104, 108, 117, 122, 131, 134, 139, 142, 150, 151, 160, 161, 162], "Their": [46, 82], "There": [17, 35, 46, 55, 56, 81, 82, 91, 92, 104, 117, 131, 134, 139, 142], "These": [36, 91, 134, 139], "To": [35, 36, 96], "_": [17, 34, 36, 151, 162], "_chain_down": 36, "_chain_up": 36, "_enabl": [36, 150, 162], "_gclk": 162, "_init": [46, 82], "_inv": [36, 162], "_lct": 162, "_mc": [12, 160], "_mux": [36, 46, 82], "_none": 162, "_reg": [81, 96], "_srval": [46, 82], "_sum": 36, "a0": 45, "a0reg": [53, 65], "a1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 152, 153, 154, 155, 156, 157], "a10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 153, 154, 155, 156, 157], "a11": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 154, 155, 156, 157], "a12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 154, 155, 156, 157], "a13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 154, 155, 156, 157], "a14": [2, 3, 6, 7, 22, 23, 24, 25, 45, 155, 156, 157], "a15": [3, 6, 7, 22, 23, 24, 25, 45, 155, 156, 157], "a16": [3, 6, 7, 22, 23, 24, 25, 45, 155, 156, 157], "a17": [6, 7, 22, 23, 24, 25, 45, 155, 156, 157], "a18": [6, 7, 22, 23, 24, 25, 155, 156, 157], "a19": [6, 7, 22, 23, 24, 25, 155, 156, 157], "a1reg": [53, 65], "a2": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 152, 153, 154, 155, 156, 157], "a20": [6, 7, 22, 23, 24, 156, 157], "a21": [6, 7, 22, 23, 156, 157], "a22": [6, 7, 22, 23, 156, 157], "a23": [22, 23], "a24": [22, 23], "a25": [22, 23], "a26": [22, 23], "a3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 152, 153, 154, 155, 156, 157], "a4": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 152, 153, 154, 155, 156, 157], "a5": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 152, 153, 154, 155, 156, 157], "a5ffinit": [127, 137], "a5ffinitslice0": [127, 137], "a5ffmux": [127, 137], "a5ffsr": [127, 137], "a5ffsrinit": 60, "a5ffsrinitslice0": 60, "a5ffsrslice1": 127, "a5q0": 60, "a5q0100": [60, 127, 137], "a6": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 152, 153, 154, 155, 156, 157], "a6lut": [60, 112, 127, 137], "a7": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 152, 153, 154, 155, 156, 157], "a8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 153, 154, 155, 156, 157], "a9": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 153, 154, 155, 156, 157], "a_fwdclk1001": 105, "a_fwdclk2001": 105, "a_fwdclk3001": 105, "a_fwdclk4001": 105, "a_gtpreset_0": 66, "a_gtpreset_0gtp": 66, "a_gtpreset_1": 66, "a_gtpreset_1gtp": 66, "a_input": [115, 129, 138], "a_loopback_0": 66, "a_loopback_1": 66, "a_plllkdeten_0": 66, "a_plllkdeten_0gtp": 66, "a_plllkdeten_1": 66, "a_plllkdeten_1gtp": 66, "a_pllpowerdown_0": 66, "a_pllpowerdown_0gtp": 66, "a_pllpowerdown_1": 66, "a_pllpowerdown_1gtp": 66, "a_prbscntreset_0": 66, "a_prbscntreset_0gtp": 66, "a_prbscntreset_1": 66, "a_prbscntreset_1gtp": 66, "a_q": 81, "a_rxbufreset_0": 66, "a_rxbufreset_0gtp": 66, "a_rxbufreset_1": 66, "a_rxbufreset_1gtp": 66, "a_rxcdrfreqreset_0": 66, "a_rxcdrfreqreset_0gtp": 66, "a_rxcdrfreqreset_1": 66, "a_rxcdrfreqreset_1gtp": 66, "a_rxcdrhold_0": 66, "a_rxcdrhold_0gtp": 66, "a_rxcdrhold_1": 66, "a_rxcdrhold_1gtp": 66, "a_rxcdrphasereset_0": 66, "a_rxcdrphasereset_0gtp": 66, "a_rxcdrphasereset_1": 66, "a_rxcdrphasereset_1gtp": 66, "a_rxcdrreset_0": 66, "a_rxcdrreset_0gtp": 66, "a_rxcdrreset_1": 66, "a_rxcdrreset_1gtp": 66, "a_rxenpmaphasealign_0": 66, "a_rxenpmaphasealign_0gtp": 66, "a_rxenpmaphasealign_1": 66, "a_rxenpmaphasealign_1gtp": 66, "a_rxenprbstst_0": 66, "a_rxenprbstst_1": 66, "a_rxeqmix_0": 66, "a_rxeqmix_1": 66, "a_rxpmasetphase_0": 66, "a_rxpmasetphase_0gtp": 66, "a_rxpmasetphase_1": 66, "a_rxpmasetphase_1gtp": 66, "a_rxpolarity_0": 66, "a_rxpolarity_0gtp": 66, "a_rxpolarity_1": 66, "a_rxpolarity_1gtp": 66, "a_rxpowerdown_0": 66, "a_rxpowerdown_1": 66, "a_rxreset_0": 66, "a_rxreset_0gtp": 66, "a_rxreset_1": 66, "a_rxreset_1gtp": 66, "a_txbufdiffctrl_0": 66, "a_txbufdiffctrl_1": 66, "a_txdiffctrl_0": 66, "a_txdiffctrl_1": 66, "a_txelecidle_0": 66, "a_txelecidle_0gtp": 66, "a_txelecidle_1": 66, "a_txelecidle_1gtp": 66, "a_txenpmaphasealign_0": 66, "a_txenpmaphasealign_0gtp": 66, "a_txenpmaphasealign_1": 66, "a_txenpmaphasealign_1gtp": 66, "a_txenprbstst_0": 66, "a_txenprbstst_1": 66, "a_txpmasetphase_0": 66, "a_txpmasetphase_0gtp": 66, "a_txpmasetphase_1": 66, "a_txpmasetphase_1gtp": 66, "a_txpolarity_0": 66, "a_txpolarity_0gtp": 66, "a_txpolarity_1": 66, "a_txpolarity_1gtp": 66, "a_txpowerdown_0": 66, "a_txpowerdown_1": 66, "a_txprbsforceerr_0": 66, "a_txprbsforceerr_0gtp": 66, "a_txprbsforceerr_1": 66, "a_txprbsforceerr_1gtp": 66, "a_txpreemphasis_0": 66, "a_txpreemphasis_1": 66, "a_txreset_0": 66, "a_txreset_0gtp": 66, "a_txreset_1": 66, "a_txreset_1gtp": 66, "aa1": [6, 7, 22, 23, 156, 157], "aa10": [6, 7, 156, 157], "aa11": [6, 7, 156, 157], "aa12": [6, 7, 156, 157], "aa13": [6, 7, 156, 157], "aa14": [6, 7, 156, 157], "aa15": [6, 7, 156, 157], "aa16": [6, 7, 156, 157], "aa17": [6, 7, 156, 157], "aa18": [6, 7, 156, 157], "aa19": [6, 7, 156, 157], "aa2": [6, 7, 22, 23, 156, 157], "aa20": [6, 7, 156, 157], "aa21": [6, 7, 156, 157], "aa22": [6, 7, 156, 157], "aa23": [22, 23], "aa24": [22, 23], "aa25": [22, 23], "aa26": [22, 23], "aa3": [6, 7, 22, 23, 156, 157], "aa4": [6, 7, 22, 23, 156, 157], "aa5": [6, 7, 156, 157], "aa6": [6, 7, 156, 157], "aa7": [6, 7, 156, 157], "aa8": [6, 7, 156, 157], "aa9": [6, 7, 156, 157], "ab": [81, 91, 96], "ab1": [6, 7, 22, 23, 156, 157], "ab10": [6, 7, 156, 157], "ab11": [6, 7, 156, 157], "ab12": [6, 7, 156, 157], "ab13": [6, 7, 156, 157], "ab14": [6, 7, 156, 157], "ab15": [6, 7, 156, 157], "ab16": [6, 7, 156, 157], "ab17": [6, 7, 156, 157], "ab18": [6, 7, 156, 157], "ab19": [6, 7, 156, 157], "ab2": [6, 7, 22, 23, 156, 157], "ab20": [6, 7, 156, 157], "ab21": [6, 7, 156, 157], "ab22": [6, 7, 156, 157], "ab23": [22, 23], "ab24": [22, 23], "ab25": [22, 23], "ab26": [22, 23], "ab3": [6, 7, 22, 23, 156, 157], "ab4": [6, 7, 22, 23, 156, 157], "ab5": [6, 7, 156, 157], "ab6": [6, 7, 156, 157], "ab7": [6, 7, 156, 157], "ab8": [6, 7, 156, 157], "ab9": [6, 7, 156, 157], "abort": 35, "about": 35, "abov": [35, 46, 55, 58, 81, 82, 87, 91, 104, 108, 117, 122, 131, 139, 142, 162], "abp": 81, "abs_freq_ref11": 102, "abs_freq_snapshot10": 102, "absolut": 151, "abuff": 40, "ac1": [22, 23], "ac10": [22, 23], "ac11": [22, 23], "ac12": [22, 23], "ac13": [22, 23], "ac14": [22, 23], "ac15": [22, 23], "ac16": [22, 23], "ac17": [22, 23], "ac18": [22, 23], "ac19": [22, 23], "ac2": [22, 23], "ac20": [22, 23], "ac21": [22, 23], "ac22": [22, 23], "ac23": [22, 23], "ac24": [22, 23], "ac25": [22, 23], "ac26": [22, 23], "ac3": [22, 23], "ac4": [22, 23], "ac5": [22, 23], "ac6": [22, 23], "ac7": [22, 23], "ac8": [22, 23], "ac9": [22, 23], "ac_cap_dis_0": [66, 118, 119], "ac_cap_dis_0gtp": 66, "ac_cap_dis_0gtp_du": 118, "ac_cap_dis_0gtx_du": 119, "ac_cap_dis_1": [66, 118, 119], "ac_cap_dis_1gtp": 66, "ac_cap_dis_1gtp_du": 118, "ac_cap_dis_1gtx_du": 119, "acb": [12, 34, 160], "accept": 91, "access": [35, 55, 56, 91, 92], "access_mod": 63, "accordingli": 36, "acd": 34, "acquir": 160, "across": [12, 34, 36, 45, 46, 53, 58, 65, 81, 82, 87, 91, 96, 104, 117, 131, 139, 142, 151, 160, 162], "activ": [35, 36, 46, 82, 161], "activelanesin": 123, "actual": [15, 16, 35, 55, 58, 81, 91, 104, 117, 131, 139, 162], "acy0": [60, 112, 127, 137], "acy0slice0": [112, 127, 137], "acy0slice1": [60, 127], "ad": [55, 56, 58, 81, 91, 92], "ad1": [22, 23], "ad10": [22, 23], "ad11": [22, 23], "ad12": [22, 23], "ad13": [22, 23], "ad14": [22, 23], "ad15": [22, 23], "ad16": [22, 23], "ad17": [22, 23], "ad18": [22, 23], "ad19": [22, 23], "ad2": [22, 23], "ad20": [22, 23], "ad21": [22, 23], "ad22": [22, 23], "ad23": [22, 23], "ad24": [22, 23], "ad25": [22, 23], "ad26": [22, 23], "ad3": [22, 23], "ad4": [22, 23], "ad5": [22, 23], "ad6": [22, 23], "ad7": [22, 23], "ad8": [22, 23], "ad9": [22, 23], "adc10": 109, "add": 92, "addit": [12, 14, 34, 36, 58, 81, 96, 104, 117, 131, 139, 162], "addition": [34, 35, 36, 46, 55, 82, 87, 91, 92, 104, 117, 131], "addr": [15, 16, 81, 96], "addr0": 72, "addr000000001": 72, "addr00000001": 72, "addr000001": 72, "addr000010000": 72, "addr0int": 72, "addr1": 72, "addr10": 72, "addr100000010": 72, "addr10000010": 72, "addr100010": 72, "addr1000100": 72, "addr100100000": 72, "addr10int": 72, "addr11": 72, "addr1101000": 72, "addr11int": 72, "addr12": 72, "addr1200001": 72, "addr1210001": 72, "addr12int": 72, "addr13": 72, "addr1300010": 72, "addr1310010": 72, "addr13int": 72, "addr14": 72, "addr1400100": 72, "addr1410100": 72, "addr14int": 72, "addr15": 72, "addr1501000": 72, "addr1511000": 72, "addr15int": 72, "addr16": 72, "addr1610001": 72, "addr16int": 72, "addr17": 72, "addr1710010": 72, "addr17int": 72, "addr18": 72, "addr1810100": 72, "addr18int": 72, "addr19": 72, "addr1911000": 72, "addr19int": 72, "addr1int": 72, "addr2": 72, "addr20": 72, "addr200000001": 72, "addr2000001": 72, "addr200000100": 72, "addr20000100": 72, "addr200100": 72, "addr20int": 72, "addr21": 72, "addr2100010": 72, "addr21int": 72, "addr22": 72, "addr2200100": 72, "addr22int": 72, "addr23": 72, "addr2301000": 72, "addr23int": 72, "addr24": 72, "addr240000001": 72, "addr2410001": 72, "addr24int": 72, "addr25": 72, "addr250000010": 72, "addr2510010": 72, "addr25int": 72, "addr26": 72, "addr260000100": 72, "addr2610100": 72, "addr26int": 72, "addr27": 72, "addr270001000": 72, "addr2711000": 72, "addr27int": 72, "addr28": 72, "addr2800000100": 72, "addr2800010000": 72, "addr280010000": 72, "addr28int": 72, "addr29": 72, "addr2900001000": 72, "addr2900100000": 72, "addr290100001": 72, "addr29int": 72, "addr2int": 72, "addr3": 72, "addr30": 72, "addr300000010": 72, "addr300001000": 72, "addr30001000": 72, "addr3001000001": 72, "addr300100010": 72, "addr3001010000": 72, "addr301000": 72, "addr30int": 72, "addr31": 72, "addr3101000010": 72, "addr310100100": 72, "addr3101100000": 72, "addr31int": 72, "addr3int": 72, "addr4": 72, "addr410001": 72, "addr4int": 72, "addr5": 72, "addr510010": 72, "addr5int": 72, "addr6": 72, "addr610100": 72, "addr6int": 72, "addr7": 72, "addr711000": 72, "addr7int": 72, "addr8": 72, "addr800001": 72, "addr8int": 72, "addr9": 72, "addr900010": 72, "addr9int": 72, "addr_cascade_out_a": 136, "addr_cascade_out_abram": 136, "addr_cascade_out_b": 136, "addr_cascade_out_bbram": 136, "addra0": 72, "addra1": 72, "addra10": 72, "addra11": 72, "addra2": 72, "addra3": 72, "addra4": 72, "addra5": 72, "addra6": 72, "addra7": 72, "addra8": 72, "addra9": 72, "addral0": 136, "addral1": 136, "addral10": 136, "addral11": 136, "addral12": 136, "addral13": 136, "addral14": 136, "addral2": 136, "addral3": 136, "addral4": 136, "addral5": 136, "addral6": 136, "addral7": 136, "addral8": 136, "addral9": 136, "addrau0": 136, "addrau1": 136, "addrau10": 136, "addrau11": 136, "addrau12": 136, "addrau13": 136, "addrau14": 136, "addrau2": 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118, "clk_cor_precedence_1gtx_du": 119, "clk_cor_repeat_wait": [88, 89], "clk_cor_repeat_wait_0": [66, 118, 119], "clk_cor_repeat_wait_1": [66, 118, 119], "clk_cor_seq_1_1": [88, 89, 105], "clk_cor_seq_1_1_0": [66, 118, 119], "clk_cor_seq_1_1_1": [66, 118, 119], "clk_cor_seq_1_2": [88, 89, 105], "clk_cor_seq_1_2_0": [66, 118, 119], "clk_cor_seq_1_2_1": [66, 118, 119], "clk_cor_seq_1_3": [88, 89, 105], "clk_cor_seq_1_3_0": [66, 118, 119], "clk_cor_seq_1_3_1": [66, 118, 119], "clk_cor_seq_1_4": [88, 89, 105], "clk_cor_seq_1_4_0": [66, 118, 119], "clk_cor_seq_1_4_1": [66, 118, 119], "clk_cor_seq_1_enable_0": [66, 118, 119], "clk_cor_seq_1_enable_1": [66, 118, 119], "clk_cor_seq_1_mask": [89, 105], "clk_cor_seq_2_1": [88, 89, 105], "clk_cor_seq_2_1_0": [66, 118, 119], "clk_cor_seq_2_1_1": [66, 118, 119], "clk_cor_seq_2_2": [88, 89, 105], "clk_cor_seq_2_2_0": [66, 118, 119], "clk_cor_seq_2_2_1": [66, 118, 119], "clk_cor_seq_2_3": [88, 89, 105], "clk_cor_seq_2_3_0": [66, 118, 119], "clk_cor_seq_2_3_1": [66, 118, 119], "clk_cor_seq_2_4": [88, 89, 105], "clk_cor_seq_2_4_0": [66, 118, 119], "clk_cor_seq_2_4_1": [66, 118, 119], "clk_cor_seq_2_enable_0": [66, 118, 119], "clk_cor_seq_2_enable_1": [66, 118, 119], "clk_cor_seq_2_mask": [89, 105], "clk_cor_seq_2_us": [88, 89, 105], "clk_cor_seq_2_use_0": [66, 118, 119], "clk_cor_seq_2_use_0gtp": 66, "clk_cor_seq_2_use_0gtp_du": 118, "clk_cor_seq_2_use_0gtx_du": 119, "clk_cor_seq_2_use_1": [66, 118, 119], "clk_cor_seq_2_use_1gtp": 66, "clk_cor_seq_2_use_1gtp_du": 118, "clk_cor_seq_2_use_1gtx_du": 119, "clk_cor_seq_2_usegt11a": 105, "clk_cor_seq_2_usegt11b": 105, "clk_cor_seq_drop": [89, 105], "clk_cor_seq_dropgt11a": 105, "clk_cor_seq_dropgt11b": 105, "clk_cor_seq_len": [88, 89, 105], "clk_correct_us": [88, 89, 105], "clk_correct_use_0": [66, 118, 119], "clk_correct_use_0gtp": 66, "clk_correct_use_0gtp_du": 118, "clk_correct_use_0gtx_du": 119, "clk_correct_use_1": [66, 118, 119], "clk_correct_use_1gtp": 66, "clk_correct_use_1gtp_du": 118, "clk_correct_use_1gtx_du": 119, "clk_correct_usegt11a": 105, "clk_correct_usegt11b": 105, "clk_dcm": 100, "clk_dcm_": 104, "clk_dcm_b": 104, "clk_dcm_t": 104, "clk_ddr": [2, 3, 4, 5, 6, 7, 8, 9], "clk_feedback": [51, 52, 64, 77, 86, 102], "clk_feedbackdcm": [51, 52, 86], "clk_feedbackdcm0": 64, "clk_feedbackdcm1": 64, "clk_feedbackdl": 77, "clk_from_dcm01100": 71, "clk_from_dcm11000": 71, "clk_from_pll": 64, "clk_from_pll11000": 64, "clk_from_plldcm0": 64, "clk_from_plldcm1": 64, "clk_hrow": [104, 106, 117, 120], "clk_in001001001": 102, "clk_inv": [2, 3, 4, 5, 6, 7, 8, 9, 36, 150, 162], "clk_inv35": 16, "clk_iob": [100, 113], "clk_iob_": [104, 117], "clk_iob_b": [104, 117], "clk_iob_t": [104, 117], "clk_mgt": 113, "clk_mgt_": 117, "clk_mgt_b": 117, "clk_mgt_t": 117, "clk_mux": [2, 3, 4, 5, 6, 7, 8, 9, 36, 150, 162], "clk_mux3433": 16, "clk_mux3736": 15, "clk_out_gtp_sel_0": 66, "clk_out_gtp_sel_0gtp": 66, "clk_out_gtp_sel_1": 66, "clk_out_gtp_sel_1gtp": 66, "clk_sel_typ": 61, "clk_switch_opt": 49, "clk_term": 100, "clk_term_b": 104, "clk_term_t": 104, "clk_to_dcm0": 71, "clk_to_dcm1": 71, "clk_to_pll": 64, "clka": [72, 96, 97], "clka00": 97, "clka1d81010000010000": 97, "clka_en": 97, "clkaint": 72, "clkardclkl": [110, 125, 136], "clkardclklbram": 125, "clkardclku": [110, 125, 136], "clkardclkubram": 125, "clkawrclk": 59, "clkawrclkbram_h0": 59, "clkawrclkbram_h1": 59, "clkb": [58, 72, 78, 87, 96, 97, 147], "clkb01": 97, "clkb_2dll": 78, "clkb_4dll": 78, "clkb_enabl": 97, "clkb_enablepmcd1": 97, "clkbint": 72, "clkbrdclk": 59, "clkbrdclkbram_h0": 59, "clkbrdclkbram_h1": 59, "clkbrst": 71, "clkbwrclkl": [110, 125, 136], "clkbwrclku": [110, 125, 136], "clkbwrclkubram": 125, "clkc": [41, 54, 58, 67, 87, 97], "clkc10": 97, "clkc_50a": [54, 58], "clkc_clkout0": 61, "clkc_clkout1": 61, "clkc_enabl": 97, "clkc_enablepmcd1": 97, "clkc_mux": 103, "clkd": 97, "clkd11": 97, "clkd_enabl": 97, "clkd_enablepmcd1": 97, "clkdiv_delay_en": [2, 3, 6, 7], "clkdiv_div": [2, 3, 6, 7], "clkdiv_en": [2, 3, 6, 7], "clkdsp0": 129, "clkdsp1": 129, "clkdv": [51, 52, 64, 86], "clkdv0010000": 74, "clkdv0010000010": 74, "clkdv00100000110": 74, "clkdv001011": 74, "clkdv01000000110": 74, "clkdv010100": 74, "clkdv0110": 64, "clkdv1000000010": 74, "clkdv10000010010": 74, "clkdv10000011": 102, "clkdv10100000011": 74, "clkdv101101": 74, "clkdv1100001": 74, "clkdv110100": 74, "clkdv1101000": 74, "clkdv1110000": 74, "clkdv_count_fal": [51, 52, 64, 77, 86, 102], "clkdv_count_fall_2": [51, 52, 64, 77, 86, 102], "clkdv_count_max": [51, 52, 64, 77, 86, 102], "clkdv_enabl": 102, "clkdv_enabledcm": 102, "clkdv_mode": [51, 52, 64, 77, 86, 102], "clkdv_modedcm": [51, 52, 86, 102], "clkdv_modedcm0": 64, "clkdv_modedcm1": 64, "clkdv_modedl": 77, "clkdv_phase_fal": [51, 52, 64, 77, 86, 102], "clkdv_phase_ris": [51, 52, 64, 77, 86, 102], "clkdvdcm": [51, 52, 86], "clkdvdcm0": 64, "clkdvdcm1": 64, "clkfb": [51, 64, 77, 86, 102], "clkfb0": [51, 86, 102], "clkfb011": 55, "clkfb_enabl": 102, "clkfb_enabledcm": 102, "clkfb_feedback": 102, "clkfb_feedbackdcm": 102, "clkfb_iob": [51, 52, 64, 86, 102], "clkfb_iobdcm": [51, 52, 86, 102], "clkfb_iobdcm0": 64, "clkfb_iobdcm1": 64, "clkfb_pad": 77, "clkfb_padint": 77, "clkfbdcm": [51, 86], "clkfbdcm10111": 71, "clkfbin": 71, "clkfbin110": 71, "clkfbout10100": 71, "clkfbout111": 71, "clkfx": [51, 52, 64, 86], "clkfx00110001": 102, "clkfx0111": 64, "clkfx180": [51, 86], "clkfx18000101001": 102, "clkfx1801000": 64, "clkfx180_enabl": 102, "clkfx180_enabledcm": 102, "clkfx180dcm": [51, 86], "clkfx_divid": [51, 52, 64, 86, 102], "clkfx_enabl": 102, "clkfx_enabledcm": 102, "clkfx_multipli": [51, 52, 64, 86, 102], "clkfxdcm": [51, 52, 86], "clkfxdcm0": 64, "clkfxdcm1": 64, "clkfxdv_divid": 64, "clkh": 147, "clkin": [64, 71, 77, 102, 118, 119], "clkin011": 55, "clkin1": [51, 86, 102], "clkin1100": 71, "clkin_clkfb_en": 64, "clkin_clkfb_enabledcm0": 64, "clkin_clkfb_enabledcm1": 64, "clkin_clkfbin_us": 71, "clkin_clkfbin_usedpl": 71, "clkin_divide_by_2": [51, 52, 64, 86, 102], "clkin_divide_by_2dcm": [51, 52, 86, 102], "clkin_divide_by_2dcm0": 64, "clkin_divide_by_2dcm1": 64, "clkin_en": 102, "clkin_enabledcm": 102, "clkin_iob": [51, 52, 64, 86, 102], "clkin_iobdcm": [51, 52, 86, 102], "clkin_iobdcm0": 64, "clkin_iobdcm1": 64, "clkin_pad": 77, "clkindc_b": [118, 119], "clkindc_b_0": 66, "clkindc_b_0gtp": 66, "clkindc_b_1": 66, "clkindc_b_1gtp": 66, "clkindc_bgtp_dual": 118, "clkindc_bgtx_dual": 119, "clkineast011": 66, "clkinsel": 71, "clkinsel_mod": 71, "clkinsel_modepl": 71, "clkinsel_stat": 71, "clkinsel_staticpl": 71, "clkint": [73, 79], "clkinwest111": 66, "clkiob1": 79, "clkiob111111110": 146, "clkiob2": 79, "clkiob3": 79, "clkl": [58, 78, 147], "clkout0000": 71, "clkout1001": 71, "clkout2010": 71, "clkout3011": 71, "clkout4100": 71, "clkout5101": 71, "clkout_east": 66, "clkout_eastgtp": 66, "clkout_north": [118, 119], "clkout_north_s0": [118, 119], "clkout_north_s101": [118, 119], "clkout_phase_shift": 64, "clkout_south": [118, 119], "clkout_south_n0": [118, 119], "clkout_south_n001": [118, 119], "clkout_west": 66, "clkout_westgtp": 66, "clkpad": [55, 87], "clkpad00000000000": 74, "clkpad000000000000": 74, "clkpad000000000001": 74, "clkpad000000000001000": 77, "clkpad00000000001": 74, "clkpad0000000001000": 77, "clkpad0000011": 74, "clkpad0000100000100": 91, "clkpad0001000000010000": 55, "clkpad00100010": 74, "clkpad01100100": 74, "clkpad10000000000": 74, "clkpad100000000000": 74, "clkpad100000000001": 74, "clkpad10000000001": 74, "clkpad100000000010000": 77, "clkpad1000000010000": 77, "clkpad10000100": 74, "clkpad1000100001000": 91, "clkpad1001000000100000": 55, "clkpad1100101": 74, "clkpad2001000000100": 91, "clkpad2001000001000000": 55, "clkpad3001000001000": 91, "clkpad3001000010000000": 55, "clkpad4010000000100": 91, "clkpad5010000001000": 91, "clkpad6100000000100": 91, "clkpad7100000001000": 91, "clkpin000": 61, "clkpin0000": 61, "clkpin01": 61, "clkpin1001": 61, "clkpin4100": 61, "clkpin5101": 61, "clkpn011": [118, 119], "clkpn1": [118, 119], "clkr": [58, 78, 147], "clkrcv_trst": 119, "clkrcv_trst_0": 66, "clkrcv_trst_0gtp": 66, "clkrcv_trst_1": 66, "clkrcv_trst_1gtp": 66, "clkrcv_trstgtx_dual": 119, "clkslice0": 112, "clkslice1": [60, 127], "clkt": [58, 78, 87, 147], "clkt_2dll": 78, "clkt_4dll": 78, "clkv": [78, 147], "clkv_bram": 72, "clkv_bram_bot": 78, "clkv_bram_top": 78, "clock": [11, 12, 34, 35, 36, 41, 44, 46, 54, 55, 56, 67, 78, 81, 82, 90, 92, 96, 104, 106, 108, 117, 120, 122, 131, 134, 139, 142, 151, 160, 162], "clock_delai": 124, "clock_invert_m": 115, "clock_invert_p": 115, "clock_invert_pdsp1": 115, "clockwis": [58, 87], "close": [58, 81, 131, 139], "closest": 58, "clr0": 145, "clrmux": 145, "clrmuxlc0": 145, "clrmuxlc1": 145, "clrmuxlc2": 145, "clrmuxlc3": 145, "cm_trim_0": [66, 119], "cm_trim_1": [66, 119], "cmd_intx_impl": [135, 143], "cmd_intx_implementedpci": [135, 143], "cmo": 14, "cmos0": 146, "cmos00": [74, 79], "cmos01": 74, "cmos111": [57, 93, 108], "cmos_hv111": 57, "cmos_lv001": 57, "cmos_vccaux111": 57, "cmos_vccint011": 57, "cmos_vcco100": 57, "cmt": [64, 71, 117, 120, 122, 131, 139], "cmt0": 61, "cmt10": 61, "cmt_bufg_": 131, "cmt_bufg_bot": 131, "cmt_bufg_top": 131, "cmt_clk000001000010000": 113, "cmt_clk000010000000010": 113, "cmt_clk100000000000110": 113, "cmt_clk100000000011000": 113, "cmt_clk1000010100000000": 113, "cmt_clk1000101000000000": 113, "cmt_clk1100001000001000": 113, "cmt_clk1100010000000100": 113, "cmt_clk1200010010000000": 113, "cmt_clk1201001000000000": 113, "cmt_clk1300001000010000": 113, "cmt_clk1300010000000010": 113, "cmt_clk1400010001000000": 113, "cmt_clk1410001000000000": 113, "cmt_clk1500001000100000": 113, "cmt_clk1500010000000001": 113, "cmt_clk1600010100000000": 113, "cmt_clk1600101000000000": 113, "cmt_clk1700000100000100": 113, "cmt_clk1700100000001000": 113, "cmt_clk1800100100000000": 113, "cmt_clk1900000100001000": 113, "cmt_clk1900100000000100": 113, "cmt_clk200000100010000": 113, "cmt_clk2000100010000000": 113, "cmt_clk200100000000010": 113, "cmt_clk2001000100000000": 113, "cmt_clk2100000100010000": 113, "cmt_clk2100100000000010": 113, "cmt_clk2200100001000000": 113, "cmt_clk2210000100000000": 113, "cmt_clk2300000100100000": 113, "cmt_clk2300100000000001": 113, "cmt_clk2400010010000000": 113, "cmt_clk2401001000000000": 113, "cmt_clk2500000010000100": 113, "cmt_clk2501000000001000": 113, "cmt_clk2600100010000000": 113, "cmt_clk2601000100000000": 113, "cmt_clk2700000010001000": 113, "cmt_clk2701000000000100": 113, "cmt_clk300000000001010": 113, "cmt_clk300000000010100": 113, "cmt_clk400000010010000": 113, "cmt_clk401000000000010": 113, "cmt_clk500000000010010": 113, "cmt_clk600000001010000": 113, "cmt_clk610000000000010": 113, "cmt_clk700000000010001": 113, "cmt_clk700000000100010": 113, "cmt_clk800011000000000": 113, "cmt_clk900001000000100": 113, "cmt_clk900010000001000": 113, "cmt_d00100": 61, "cmt_d100100": 61, "cmt_d10100": 61, "cmt_d110100": 61, "cmt_d120100": 61, "cmt_d130100": 61, "cmt_d140100": 61, "cmt_d150100": 61, "cmt_d20100": 61, "cmt_d30100": 61, "cmt_d40100": 61, "cmt_d50100": 61, "cmt_d60100": 61, "cmt_d70100": 61, "cmt_d80100": 61, "cmt_d90100": 61, "cmt_dcm": 64, "cmt_enabl": 61, "cmt_pll": 71, "cmt_u01000": 61, "cmt_u101000": 61, "cmt_u11000": 61, "cmt_u111000": 61, "cmt_u121000": 61, "cmt_u131000": 61, "cmt_u141000": 61, "cmt_u151000": 61, "cmt_u21000": 61, "cmt_u31000": 61, "cmt_u41000": 61, "cmt_u51000": 61, "cmt_u61000": 61, "cmt_u71000": 61, "cmt_u81000": 61, "cmt_u91000": 61, "cmux": 146, "cmuxosc": 146, "cnr": [58, 78, 87, 147], "co01": 145, "co1": 145, "code": 35, "coin_window": [51, 86], "col": [2, 3, 4, 5, 6, 7, 8, 9, 152, 153, 154, 155, 156, 157], "col_hi": [15, 16], "col_lo": [15, 16], "coloc": [58, 81, 104, 117, 131, 139], "column": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 35, 46, 47, 55, 78, 81, 82, 83, 87, 91, 108, 122, 134, 142, 150, 151, 152, 153, 154, 155, 156, 157, 159, 161], "columnar": 104, "com": [51, 86], "com_burst_val_0": [66, 118, 119], "com_burst_val_1": [66, 118, 119], "comb": 36, "comb0": 15, "comb1": 16, "combin": [36, 46, 55, 81, 82, 91, 104, 162], "combination": 81, "combinatori": [14, 36, 162], "come": [12, 34, 36, 46, 58, 81, 87, 104, 108, 117, 122, 131, 139, 160, 162], "comma32": 105, "comma32gt11a": 105, "comma32gt11b": 105, "comma_10b_enable_0": [66, 118, 119], "comma_10b_enable_1": [66, 118, 119], "comma_10b_mask": [88, 89, 105], "comma_double_0": [118, 119], "comma_double_0gtp_du": 118, "comma_double_0gtx_du": 119, "comma_double_1": [118, 119], "comma_double_1gtp_du": 118, "comma_double_1gtx_du": 119, "commerci": [17, 151], "common": [100, 142], "common_hclk_giob": 100, "common_mgt": 100, "common_mgtioclk": 100, "commonli": [139, 150], "companion": [44, 106], "compat": [12, 34, 160], "compens": 82, "complement": [108, 122, 134, 142], "complet": [12, 13, 16, 34, 35, 36, 104, 139, 150, 160], "complex": [15, 16, 139], "comput": [81, 150], "concaten": [15, 16, 81, 96], "conceptu": 58, "concur": [51, 52, 64, 86], "concur00100101": 102, "concur1001": 64, "concur_en": 102, "concur_enabledcm": 102, "concurdcm": [51, 52, 86], "concurdcm0": 64, "concurdcm1": 64, "config": [15, 16, 150], "config10": 102, "config_fallback": [114, 128], "config_r": [39, 48, 49, 75, 84, 101, 114, 128, 146], "configrout": 123, "configur": [11, 12, 15, 33, 34, 35, 41, 44, 47, 54, 55, 56, 67, 78, 87, 90, 91, 92, 104, 106, 108, 117, 120, 122, 131, 132, 134, 140, 142, 147, 150, 159], "configuraton": [15, 16], "conjunct": 36, "connect": [35, 36, 46, 58, 81, 82, 91, 92, 96, 108, 122, 134, 139, 161, 162], "consecut": 131, "consid": [35, 104, 108, 117, 122, 131, 134, 139, 142], "consist": [35, 36, 81, 104, 117, 122, 131, 134, 139], "const": [13, 14, 35, 36, 46, 82, 161, 162], "constant": [36, 46, 82, 108], "constraint": 12, "construct": 162, "consult": 15, "contain": [15, 17, 34, 42, 45, 46, 55, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 117, 122, 131, 134, 139, 142, 161, 162], "content": [35, 46, 82, 131], "contigu": [15, 16], "continu": [35, 142], "control": [12, 14, 35, 36, 44, 46, 56, 67, 82, 92, 96, 108], "convert": [15, 16], "convst": 109, "convstclk": [111, 126], "convstsysmon": 109, "coolrunn": [0, 12, 14], "coordin": [16, 17, 36, 58, 87, 150, 151, 162], "cor": [41, 54, 78, 90, 106, 120, 132], "cor1": [54, 67, 120, 132], "cor2": [54, 67], "core": [12, 34, 36, 44, 55, 87, 90, 91, 92, 104, 117, 120, 132, 140, 160, 162], "corner": [41, 44, 54, 55, 56, 58, 67, 78, 87, 90, 91, 92, 139, 147], "correct": 96, "correspond": [12, 14, 15, 16, 17, 34, 35, 36, 46, 47, 53, 55, 58, 65, 81, 82, 83, 87, 91, 96, 104, 108, 117, 122, 131, 134, 139, 142, 151, 162], "could": 35, "count": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 46, 58, 81, 87, 104, 117, 131, 139, 152, 153, 154, 155, 156, 157], "cout": [46, 82, 148], "coutmux": [60, 112, 127, 137], "coutmuxslice1": 60, "cover": [104, 117, 131, 139, 142, 162], "cp132": [2, 3, 12], "cp56": [4, 5, 8, 9, 12, 153, 160], "cpl_timeout_disable_support": [135, 143], "cpl_timeout_ranges_support": [135, 143], "cpld": [0, 12, 34, 36, 160, 162], "cpmc440clk": 124, "cpmc440timerclock": 124, "cpmdcrclk": 124, "cpmdma0llclk": 124, "cpmdma1llclk": 124, "cpmdma2llclk": 124, "cpmdma3llclk": 124, "cpmfcmclk": 124, "cpminterconnectclk": 124, "cpmmcclk": 124, "cpmppcmplbclk": 124, "cpmppcs0plbclk": 124, "cpmppcs1plbclk": 124, "crammod": [60, 112, 127, 137], "crc": [39, 48, 49, 62, 84, 101, 114, 146], "crc32_0": [118, 119], "crc32_1": [118, 119], "crc32_2": [118, 119], "crc32_3": [118, 119], "crc_end_of_pkt": [88, 89], "crc_format": [88, 89], "crc_init": [118, 119], "crc_start_of_pkt": [88, 89], "crcclk": [118, 119], "crcclkgtp_dual": 118, "crcclkgtx_dual": 119, "creat": [55, 87, 91, 104, 117], "create_edg": [98, 111], "create_edgebufgctrl0": 98, "create_edgebufgctrl1": 98, "create_edgebufgctrl10": 98, "create_edgebufgctrl11": 98, "create_edgebufgctrl12": 98, "create_edgebufgctrl13": 98, "create_edgebufgctrl14": 98, "create_edgebufgctrl15": 98, "create_edgebufgctrl16": 98, "create_edgebufgctrl17": 98, "create_edgebufgctrl18": 98, "create_edgebufgctrl19": 98, "create_edgebufgctrl2": 98, "create_edgebufgctrl20": 98, "create_edgebufgctrl21": 98, "create_edgebufgctrl22": 98, "create_edgebufgctrl23": 98, "create_edgebufgctrl24": 98, "create_edgebufgctrl25": 98, "create_edgebufgctrl26": 98, "create_edgebufgctrl27": 98, "create_edgebufgctrl28": 98, "create_edgebufgctrl29": 98, "create_edgebufgctrl3": 98, "create_edgebufgctrl30": 98, "create_edgebufgctrl31": 98, "create_edgebufgctrl4": 98, "create_edgebufgctrl5": 98, "create_edgebufgctrl6": 98, "create_edgebufgctrl7": 98, "create_edgebufgctrl8": 98, "create_edgebufgctrl9": 98, "creg": [53, 65, 103, 115, 129, 138], "cregdsp": [53, 65], "cregdsp0": [115, 129], "cregdsp1": 129, "crm_core_clk_freq_500": 144, "crm_core_clk_freq_500pcie3": 144, "crm_module_rst": [135, 143], "crm_user_clk_freq": 144, "crmcoreclk": 123, "crmcoreclkdlo": 123, "crmcoreclkpci": 123, "crmcoreclkrxo": 123, "crmcoreclkrxopci": 123, "crmcoreclktxo": 123, "crmcoreclktxopci": 123, "crmuserclk": 123, "crmuserclkrxo": 123, "crmuserclktxo": 123, "cross": [58, 91, 131, 139], "cs144": [20, 21, 34, 154, 160], "cs280": [24, 25, 34, 155, 160], "cs48": [26, 27, 28, 30, 31, 34, 152, 153, 160], "cs_b": [108, 122], "csi_b": [134, 142], "cso2pin": [50, 63], "cso_b": [122, 134, 142], "cspin": [98, 111, 126], "ct": 14, "ct4111": [2, 3, 4, 5, 6, 7, 8, 9], "ct501": [2, 3, 4, 5, 6, 7, 8, 9], "ct601": [2, 3, 4, 5, 6, 7, 8, 9], "ct70001": [2, 3, 4, 5, 6, 7, 8, 9], "ctc": 14, "cte": 14, "ctl": [41, 54, 67, 78, 90, 106, 120, 132], "ctl1": 132, "ctlgo": [51, 52, 64, 86, 102], "ctlgo001": 55, "ctlgodcm": 86, "ctlmode": [51, 52, 64, 86], "ctlmode011": 55, "ctlmodedcm": 86, "ctlosc1": [51, 52, 64, 86, 102], "ctlosc1001": 55, "ctlosc1dcm": [86, 102], "ctlosc2": [51, 52, 64, 86, 102], "ctlosc2001": 55, "ctlosc2dcm": [86, 102], "ctlsel0": [51, 52, 64, 86, 102], "ctlsel0011": 55, "ctlsel0dcm": 86, "ctlsel1": [51, 52, 64, 86, 102], "ctlsel1101": 55, "ctlsel1dcm": [86, 102], "ctlsel2": [51, 52, 64, 86, 102], "ctlsel2100": 55, "ctlsel2dcm": [86, 102], "ctr": 14, "ctrl0": [121, 133, 141], "ctrl00001": [133, 141], "ctrl1": [121, 133, 141], "ctrl10010": [133, 141], "ctrl2": 121, "ctrl3": 121, "ctt": 79, "ctt001100010": 79, "ctt01011": 79, "ctt0111": 79, "curious": [12, 34], "current": [35, 46, 82], "cut": [56, 58, 117, 139], "cv100": [2, 12], "cv64": [5, 9, 12], "cx0": [60, 112, 127, 137], "cx0100": [112, 127, 137], "cx1": [60, 112], "cx10": [127, 137], "cx1010": 60, "cxt": 131, "cy0": 73, "cy0111": 60, "cy0f": [37, 46, 82, 99], "cy0g": [37, 46, 82, 99], "cy1010": [60, 112, 127, 137], "cy110": 112, "cycl": [35, 81, 96], "cycle_limit_sel": 105, "cyinit": [37, 46, 60, 73, 82, 99, 112, 127, 137], "cyinitslice0": [73, 99, 112, 127, 137], "cyinitslice1": [37, 46, 60, 73, 112, 127, 137], "cyinitslice2": 99, "cyinitslice3": [37, 46], "cyself": [37, 46, 73, 82], "cyselfslice0": 73, "cyselfslice1": [37, 46, 73], "cyselfslice3": [37, 46], "cyselg": [37, 46, 73, 82], "cyselgslice0": [73, 82], "cyselgslice1": [37, 46, 73, 82], "cyselgslice3": [37, 46], "d": [14, 36, 81, 96, 108, 122, 134, 142, 162], "d0": [129, 138], "d01": 108, "d1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 129, 138, 152, 153, 154, 155, 156, 157, 162], "d10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 129, 138, 153, 154, 155, 156, 157], "d1001": 108, "d11": [3, 6, 7, 20, 21, 22, 23, 24, 25, 129, 138, 154, 155, 156, 157], "d12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 129, 138, 154, 155, 156, 157], "d13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 129, 138, 154, 155, 156, 157], "d14": [2, 3, 6, 7, 22, 23, 24, 25, 129, 138, 155, 156, 157], "d15": [3, 6, 7, 22, 23, 24, 25, 129, 138, 155, 156, 157], "d16": [3, 6, 7, 22, 23, 24, 25, 129, 138, 155, 156, 157], "d17": [6, 7, 22, 23, 24, 25, 129, 138, 155, 156, 157], "d18": [6, 7, 22, 23, 24, 25, 129, 138, 155, 156, 157], "d19": [6, 7, 22, 23, 24, 25, 129, 138, 155, 156, 157], "d2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 129, 138, 152, 153, 154, 155, 156, 157], "d20": [6, 7, 22, 23, 24, 129, 138, 156, 157], "d21": [6, 7, 22, 23, 129, 138, 156, 157], "d22": [6, 7, 22, 23, 129, 138, 156, 157], "d23": [22, 23, 129, 138], "d24": [22, 23, 129, 138], "d25": [22, 23], "d26": [22, 23], "d2ologic0": 108, "d2ologic1": 108, "d3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 129, 138, 152, 153, 154, 155, 156, 157], "d3iob0": 108, "d3iob1": 108, "d4": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 129, 138, 152, 153, 154, 155, 156, 157], "d4iob0": 108, "d4iob1": 108, "d5": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 108, 129, 138, 154, 155, 156, 157], "d5ffinit": [127, 137], "d5ffinitslice0": [127, 137], "d5ffmux": [127, 137], "d5ffsr": [127, 137], "d5ffsrinit": 60, "d5ffsrinitslice0": 60, "d5ffsrslice1": 127, "d5ologic0": 108, "d5ologic1": 108, "d5q0": 60, "d5q0100": [60, 127, 137], "d6": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 129, 138, 152, 153, 154, 155, 156, 157], "d6lut": [60, 112, 127, 137], "d7": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 129, 138, 152, 153, 154, 155, 156, 157], "d8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 129, 138, 153, 154, 155, 156, 157], "d9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 129, 138, 154, 155, 156, 157], "d_in": [108, 122], "d_out_busi": 122, "daddr0": 102, "daddr1": 102, "daddr1dcm": 102, "daddr2": 102, "daddr2dcm": 102, "daddr3": 102, "daddr4": 102, "daddr4dcm": 102, "daddr5": 102, "daddr5dcm": 102, "daddr6": 102, "daddr6dcm": 102, "data": [10, 12, 14, 17, 32, 35, 37, 42, 45, 46, 53, 54, 55, 58, 59, 65, 72, 81, 82, 87, 90, 91, 96, 99, 104, 106, 108, 117, 122, 131, 139, 146, 150, 151, 158, 162], "data0": [42, 55, 91], "data00001000001": 91, "data00001000100": 91, "data00mux": 55, "data1": [42, 55, 91], "data10": [42, 55], "data10001000010": 91, "data10001001000": 91, "data101mux": 55, "data10mux": 55, "data11": [42, 55], "data110mux": 55, "data11mux": 55, "data12": [42, 55], "data13": [42, 55], "data130mux": 55, "data131mux": 55, "data14": [42, 55], "data140mux": 55, "data15": [42, 55], "data16": [42, 55], "data160mux": 55, "data17": [42, 55], "data170mux": 55, "data171mux": 55, "data18": [42, 55], "data180mux": 55, "data181mux": 55, "data19": [42, 55], "data190mux": 55, "data2": [42, 55, 91], "data20": [42, 55], "data20001000100": 91, "data20001010000": 91, "data20mux": 55, "data21": [42, 55], "data210mux": 55, "data21mux": 55, "data22": [42, 55], "data220mux": 55, "data221mux": 55, "data23": [42, 55], "data24": [42, 55], "data240mux": 55, "data25": [42, 55], "data250mux": 55, "data251mux": 55, "data26": [42, 55], "data261mux": 55, "data27": [42, 55], "data270mux": 55, "data28": [42, 55], "data29": [42, 55], "data290mux": 55, "data3": [42, 55, 91], "data30": [42, 55], "data30001001000": 91, "data30001100000": 91, "data300mux": 55, "data301mux": 55, "data30mux": 55, "data31": [42, 55], "data4": [42, 55, 91], "data40001000001": 91, "data40001000010": 91, "data40001000100": 91, "data5": [42, 55, 91], "data50001000010": 91, "data50001000100": 91, "data50001001000": 91, "data50mux": 55, "data51mux": 55, "data6": [42, 55, 91], "data60001000100": 91, "data60001001000": 91, "data60001010000": 91, "data60mux": 55, "data7": [42, 55, 91], "data70001001000": 91, "data70001010000": 91, "data70001100000": 91, "data8": [42, 55], "data80mux": 55, "data9": [42, 55], "data90mux": 55, "data91mux": 55, "data_l": [110, 125, 136], "data_r": [61, 108], "data_u": [110, 125, 136], "data_width": 108, "data_width_": 81, "data_width_a": [45, 59, 81], "data_width_b": [45, 59, 81], "databas": [11, 15, 16, 33, 35, 36, 150, 159, 161, 162], "dataint": 146, "datap": [45, 59, 81, 96], "datap_l": [110, 125, 136], "datap_u": [110, 125, 136], "datareg": 13, "datastream": [17, 151], "dbl": [38, 42, 47, 55, 68, 83, 91, 107, 121, 133, 141, 145, 148], "dbl0001010000": 121, "dbl0001100000": 121, "dbl0010010000": 121, "dbl0010100000": 121, "dbl0100010000": 121, "dbl0100100000": 121, "dbl1000010000": 121, "dbl1000100000": 121, "dcdr_filter": 105, "dci": [56, 91, 92, 100, 108, 122, 134, 142], "dci0": [50, 85], "dci00": 50, "dci1": [50, 85], "dci11": 50, "dci_altvr": 85, "dci_altvrmisc": 85, "dci_clk_en": [50, 85, 98], "dci_clk_enablemisc": 85, "dci_misc": 108, "dci_mod": [57, 93, 108], "dci_osc_sel": 50, "dci_t": 108, "dci_test_mux": 50, "dcireset": [98, 111, 126], "dcireset0": 50, "dcireset1": 50, "dciupdatemode_asrequir": [57, 93, 108], "dciupdatemode_asrequirediob0": [57, 93], "dciupdatemode_asrequirediob1": [57, 93], "dciupdatemode_asrequirediob2": 93, "dciupdatemode_asrequirediob3": [57, 93], "dciupdatemode_asrequirediob4": [57, 93], "dciupdatemode_asrequirediob5": 93, "dclk": [66, 111, 118, 119, 126], "dclk0": 102, "dclk_divid_2": 109, "dclk_miss": 109, "dclkgtp": 66, "dclkgtp_dual": 118, "dclkgtx_dual": 119, "dclksysmon": 111, "dcm": [54, 56, 81, 87, 90, 102, 104, 106, 108], "dcm0": 64, "dcm0000000000001": 64, "dcm000001000000111111": 100, "dcm0_clk00000000110": 64, "dcm0_clk1800000010110": 64, "dcm0_clk2700000011110": 64, "dcm0_clk2x0000100010": 64, "dcm0_clk2x1800000101010": 64, "dcm0_clk900000001110": 64, "dcm0_clkdv0000110010": 64, "dcm0_clkfb011": 71, "dcm0_clkfx0000111010": 64, "dcm0_clkfx1800000100110": 64, "dcm0_clkin010": 71, "dcm0_concur0000101110": 64, "dcm1": 64, "dcm100001000001011111": 100, "dcm1000010001000011111": 100, "dcm1100010010000011111": 100, "dcm1200100000000111111": 100, "dcm1300100000001011111": 100, "dcm1400100000010011111": 100, "dcm1500100000100011111": 100, "dcm1600100001000011111": 100, "dcm1700100010000011111": 100, "dcm1801000000000111111": 100, "dcm1901000000001011111": 100, "dcm1_clk00001000000": 64, "dcm1_clk1800101000000": 64, "dcm1_clk2700111000000": 64, "dcm1_clk2x1000000000": 64, "dcm1_clk2x1801010000000": 64, "dcm1_clk900011000000": 64, "dcm1_clkdv1100000000": 64, "dcm1_clkfb001": 71, "dcm1_clkfx1110000000": 64, "dcm1_clkfx1801001000000": 64, "dcm1_clkin000": 71, "dcm1_concur1011000000": 64, "dcm200001000010011111": 100, "dcm2001000000010011111": 100, "dcm2101000000100011111": 100, "dcm2201000001000011111": 100, "dcm2301000010000011111": 100, "dcm300001000100011111": 100, "dcm400001001000011111": 100, "dcm500001010000011111": 100, "dcm600010000000111111": 100, "dcm700010000001011111": 100, "dcm800010000010011111": 100, "dcm900010000100011111": 100, "dcm_bufpll": 67, "dcm_clkdv_clkfx_align": 102, "dcm_clkdv_clkfx_alignmentdcm": 102, "dcm_enabl": 50, "dcm_ext_fb_en": 102, "dcm_ext_fb_endcm": 102, "dcm_lock_high": 102, "dcm_lock_highdcm": 102, "dcm_out100": 47, "dcm_out_l0100": [47, 83], "dcm_out_l01000": 47, "dcm_out_r1000": [47, 83], "dcm_out_r10000": 47, "dcm_performance_mod": 102, "dcm_performance_modedcm": 102, "dcm_pulse_width_correction_high": 102, "dcm_pulse_width_correction_low": 102, "dcm_shutdown": [48, 84, 101], "dcm_unused_taps_powerdown": 102, "dcm_unused_taps_powerdowndcm": 102, "dcm_vbg_pd": 102, "dcm_vbg_sel": 102, "dcm_vref_sourc": 102, "dcm_vreg": 52, "dcm_vreg_en": 102, "dcm_vreg_enabledcm": 102, "dcm_vreg_phase_margin": 102, "dcmclk": 91, "dcmclk0": 91, "dcmclk00001000001": 91, "dcmclk0int": 91, "dcmclk1": 91, "dcmclk10001000010": 91, "dcmclk1int": 91, "dcmclk2": 91, "dcmclk20001000001": 91, "dcmclk2int": 91, "dcmclk3": 91, "dcmclk30001000010": 91, "dcmclk3int": 91, "dcr_autolock_en": 124, "dcr_test": 124, "dcremacclk": 116, "dcy0": [60, 112, 127, 137], "dcy0slice0": [112, 127, 137], "dcy0slice1": [60, 137], "dd1": 34, "ddel_a": [45, 59, 81], "ddel_a_default": 45, "ddel_b": [45, 59, 81], "ddel_b_default": 45, "ddr": [56, 92], "ddr0": 108, "ddr01": 69, "ddr1": 61, "ddr210": 69, "ddr300": 69, "ddr_clk_edg": 108, "deal": [58, 87, 91], "dec_mcomma_detect": [88, 89, 105], "dec_mcomma_detect_0": [66, 118, 119], "dec_mcomma_detect_0gtp": 66, "dec_mcomma_detect_0gtp_du": 118, "dec_mcomma_detect_0gtx_du": 119, "dec_mcomma_detect_1": [66, 118, 119], "dec_mcomma_detect_1gtp": 66, "dec_mcomma_detect_1gtp_du": 118, "dec_mcomma_detect_1gtx_du": 119, "dec_mcomma_detectgt11a": 105, "dec_mcomma_detectgt11b": 105, "dec_pcomma_detect": [88, 89, 105], "dec_pcomma_detect_0": [66, 118, 119], "dec_pcomma_detect_0gtp": 66, "dec_pcomma_detect_0gtp_du": 118, "dec_pcomma_detect_0gtx_du": 119, "dec_pcomma_detect_1": [66, 118, 119], "dec_pcomma_detect_1gtp": 66, "dec_pcomma_detect_1gtp_du": 118, "dec_pcomma_detect_1gtx_du": 119, "dec_pcomma_detectgt11a": 105, "dec_pcomma_detectgt11b": 105, "dec_valid_comma_onli": [88, 89, 105], "dec_valid_comma_only_0": [66, 118, 119], "dec_valid_comma_only_0gtp": 66, "dec_valid_comma_only_0gtp_du": 118, "dec_valid_comma_only_0gtx_du": 119, "dec_valid_comma_only_1": [66, 118, 119], "dec_valid_comma_only_1gtp": 66, "dec_valid_comma_only_1gtp_du": 118, "dec_valid_comma_only_1gtx_du": 119, "dec_valid_comma_onlygt11a": 105, "dec_valid_comma_onlygt11b": 105, "decod": 96, "dedic": [12, 14, 34, 36, 45, 46, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 117, 122, 134, 139, 142, 151, 160, 162], "def": [15, 16], "default": [17, 35, 54], "default00": 108, "defin": 162, "definit": 142, "del_clk_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 152, 153, 154, 155, 156, 157], "del_d_q_comb": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_d_q_latch": [2, 3, 4, 5, 6, 7, 8, 9, 152, 153, 154, 155, 156, 157], "del_exp_d": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_exp_exp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_d": [2, 3, 4, 5, 6, 7, 8, 9, 152, 153, 154, 155, 156, 157], "del_ibuf_fclk": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 152, 153, 154, 155, 156, 157], "del_ibuf_fo": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_fsr": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 152, 153, 154, 155, 156, 157], "del_ibuf_plain": [2, 3, 4, 5, 6, 7, 8, 9], "del_ibuf_schmitt": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_ct": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_d_hp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_d_lp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_fbn": [152, 153, 154, 155, 156, 157], "del_imux_or": [2, 3, 4, 5, 6, 7, 8, 9, 152, 153, 154, 155, 156, 157], "del_imux_pt": [2, 3, 4, 5, 6, 7, 8, 9, 152, 153, 154, 155, 156, 157], "del_imux_pt_c": [20, 21, 24, 25, 27, 28, 30, 31], "del_imux_pt_clk": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 152, 153, 154, 155, 156, 157], "del_imux_pt_o": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_pt_sr": [20, 21, 24, 25, 27, 28, 30, 31], "del_mc_fo": [2, 3, 4, 5, 6, 7, 8, 9], "del_obuf_fast": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 152, 153, 154, 155, 156, 157], "del_obuf_o": [2, 3, 4, 5, 6, 7, 8, 9, 152, 153, 154, 155, 156, 157], "del_obuf_slow": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 152, 153, 154, 155, 156, 157], "del_pt_ut": [152, 153, 154, 155, 156, 157], "del_sr_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 152, 153, 154, 155, 156, 157], "del_uim_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 152, 153, 154, 155, 156, 157], "delai": [14, 44, 47, 74, 78, 117, 120, 131, 132, 139, 140], "delay0": 148, "delay_common": 57, "delay_commoniob0": 57, "delay_commoniob1": 57, "delay_commoniob2": 57, "delay_commoniob3": 57, "delay_commoniob4": 57, "delay_commoniob5": 57, "delay_commoniob6": 57, "delay_en": 43, "delay_vari": 57, "delay_variableiob0": 57, "delay_variableiob1": 57, "delay_variableiob3": 57, "delay_variableiob4": 57, "delayed_write0": 136, "delayed_write00": 125, "delaymux": 148, "delaymuxint": 148, "delaymuxiob2": 148, "delaymuxiob3": 148, "depend": [17, 35, 36, 55, 58, 81, 91, 104, 108, 117, 131, 139, 142, 151, 161, 162], "deriv": [12, 34, 56, 92, 160, 162], "describ": [17, 35, 46, 47, 58, 81, 82, 83, 100, 113, 151], "descript": [45, 99], "design": [12, 36, 58, 160, 162], "deskew_adjust": [54, 64, 90, 102], "despit": 139, "destin": 36, "detail": [35, 58, 87, 96, 161], "determin": [12, 34, 35, 46, 82, 162], "dev_cap2_ari_forwarding_support": 143, "dev_cap2_ari_forwarding_supportedpci": 143, "dev_cap2_atomicop32_completer_support": 143, "dev_cap2_atomicop32_completer_supportedpci": 143, "dev_cap2_atomicop64_completer_support": 143, "dev_cap2_atomicop_routing_support": 143, "dev_cap2_cas128_completer_support": 143, "dev_cap2_cas128_completer_supportedpci": 143, "dev_cap2_endend_tlp_prefix_support": 143, "dev_cap2_endend_tlp_prefix_supportedpci": 143, "dev_cap2_extended_fmt_field_support": 143, "dev_cap2_ltr_mechanism_support": 143, "dev_cap2_ltr_mechanism_supportedpci": 143, "dev_cap2_max_endend_tlp_prefix": 143, "dev_cap2_no_ro_enabled_prpr_pass": 143, "dev_cap2_tph_completer_support": 143, "dev_cap_enable_slot_pwr_limit_scal": [135, 143], "dev_cap_enable_slot_pwr_limit_scalepci": [135, 143], "dev_cap_enable_slot_pwr_limit_valu": [135, 143], "dev_cap_endpoint_l0s_lat": [70, 135, 143], "dev_cap_endpoint_l1_lat": [70, 135, 143], "dev_cap_ext_tag_support": [70, 135, 143], "dev_cap_ext_tag_supportedpci": [135, 143], "dev_cap_function_level_reset_cap": [135, 143], "dev_cap_max_payload_support": [70, 135, 143], "dev_cap_phantom_functions_support": [70, 135, 143], "dev_cap_role_based_error": [70, 135, 143], "dev_cap_rsvd_14_12": [135, 143], "dev_cap_rsvd_17_16": [135, 143], "dev_cap_rsvd_31_29": [135, 143], "dev_control_aux_power_support": [135, 143], "dev_control_aux_power_supportedpci": 143, "dev_control_ext_tag_default": 143, "devic": [11, 15, 16, 33, 35, 44, 45, 46, 47, 54, 55, 81, 82, 83, 90, 91, 106, 108, 120, 122, 132, 134, 140, 142, 150, 159, 161], "device_id": 135, "devicebram": 45, "devicecapabilityendpointl0slat": 123, "devicecapabilityendpointl1lat": 123, "devicedcm": [51, 52, 86], "deviceid": 123, "deviceserialnumb": 123, "devicevalu": [47, 61], "devoid": 139, "df": [51, 86], "dfb001": 61, "dfb010": 61, "dfe_cal_tim": 119, "dfe_cfg_0": 119, "dfe_cfg_1": 119, "dff": [14, 36, 162], "dff0": 16, "dff00": [2, 3, 4, 5, 6, 7, 8, 9, 150], "dff1": 15, "dff_latch": 127, "dff_latchslice0": 127, "dffce": 162, "dffce11": [2, 3, 4, 5, 6, 7, 8, 9, 150], "dffinit": [112, 127, 137], "dffinitslice0": [112, 127, 137], "dffmux": [60, 112, 127, 137], "dffmuxslice1": 60, "dffsr": [112, 127, 137], "dffsrinit": 60, "dffsrinitslice1": 60, "dffsrslice0": 137, "dffsrslice1": 127, "dfs_": [52, 64], "dfs_ave_freq_adj_interv": 102, "dfs_ave_freq_gain": 102, "dfs_ave_freq_sample_interv": 102, "dfs_c": [52, 64], "dfs_coarse_sel": 102, "dfs_coarse_seldcm": 102, "dfs_coin_window": 102, "dfs_early_lock": 102, "dfs_early_lockdcm": 102, "dfs_en_relrst": 102, "dfs_en_relrstdcm": 102, "dfs_enabl": [51, 52, 64, 86, 102], "dfs_enabledcm": [51, 52, 86, 102], "dfs_enabledcm0": 64, "dfs_enabledcm1": 64, "dfs_extend_flush_tim": 102, "dfs_extend_flush_timedcm": 102, "dfs_extend_halt_tim": 102, "dfs_extend_halt_timedcm": 102, "dfs_extend_run_tim": 102, "dfs_extend_run_timedcm": 102, "dfs_feedback": [51, 52, 64, 86, 102], "dfs_feedbackdcm": [51, 52, 102], "dfs_feedbackdcm0": 64, "dfs_feedbackdcm1": 64, "dfs_fine_sel": 102, "dfs_fine_seldcm": 102, "dfs_frequency_mod": [51, 52, 64, 86, 102], "dfs_frequency_modedcm": [51, 52, 102], "dfs_frequency_modedcm0": 64, "dfs_frequency_modedcm1": 64, "dfs_hardsync": 102, "dfs_non_stop": 102, "dfs_non_stopdcm": 102, "dfs_oscillator_mod": 102, "dfs_skip_fin": 102, "dfs_skip_finedcm": 102, "dfs_spare": 102, "dfs_tp_sel": 102, "dfs_tp_seldcm": 102, "dfs_trackmod": 102, "dfs_trackmodedcm": 102, "dge": [2, 3, 6, 7, 12, 14], "dge_en": [2, 3, 6, 7], "di": [12, 46, 81, 82, 96, 145], "di0": [102, 145], "di1": 102, "di10": 102, "di10dcm": 102, "di11": [102, 145], "di12": 102, "di126": [2, 12], "di12dcm": 102, "di13": 102, "di13dcm": 102, "di14": 102, "di14dcm": 102, "di15": 102, "di1dcm": 102, "di2": 102, "di222": [3, 12], "di288": [6, 12], "di2dcm": 102, "di3": 102, "di324": [7, 12], "di4": 102, "di44": [4, 5, 12], "di4dcm": 102, "di5": 102, "di5dcm": 102, "di6": 102, "di6dcm": 102, "di7": 102, "di8": 102, "di81": [8, 9, 12], "di9": 102, "di9dcm": 102, "dia": 96, "dia0": 72, "dia1": 72, "dia10": 72, "dia11": 72, "dia12": 72, "dia13": 72, "dia14": 72, "dia15": 72, "dia2": 72, "dia3": 72, "dia4": 72, "dia5": 72, "dia6": 72, "dia7": 72, "dia8": 72, "dia9": 72, "diagon": [55, 91], "dib": 96, "dib0": 72, "dib1": 72, "dib10": 72, "dib11": 72, "dib12": 72, "dib13": 72, "dib14": 72, "dib15": 72, "dib16": 81, "dib2": 72, "dib3": 72, "dib31": 81, "dib4": 72, "dib5": 72, "dib6": 72, "dib7": 72, "dib8": 72, "dib9": 72, "die": [12, 17, 56, 139, 142, 151], "dif": [46, 82], "dif_mux": [37, 46, 82, 99], "dif_muxslice0": 99, "diff010": 108, "diff10": [74, 79], "diff101": [57, 93], "diff110": 57, "differ": [16, 35, 36, 46, 55, 82, 91, 142, 160, 162], "differenti": [14, 56, 108, 122, 134, 142], "dig": [46, 82], "dig_mux": [37, 46, 82, 99], "dig_muxslice0": 99, "dig_muxslice2": 99, "digit": [44, 54, 55, 56, 67, 90, 91, 92, 106], "digrx_fwdclk": 105, "digrx_sync_mod": 105, "digrx_sync_modegt11a": 105, "digrx_sync_modegt11b": 105, "dimens": 58, "dimension": 150, "din": [134, 142], "din0": 72, "din0000": 72, "din0001": 72, "din0int": 72, "din1": 72, "din10": 72, "din1000": 72, "din10000": 72, "din10001": 72, "din1001": 72, "din10int": 72, "din11": 72, "din11001": 72, "din11010": 72, "din11int": 72, "din12": 72, "din12010": 72, "din12011": 72, "din12int": 72, "din13": 72, "din13010": 72, "din13011": 72, "din13int": 72, "din14": 72, "din14010": 72, "din14011": 72, "din14int": 72, "din15": 72, "din15000": 72, "din15011": 72, "din15int": 72, "din16": 72, "din16110": 72, "din16111": 72, "din16int": 72, "din17": 72, "din17100": 72, "din17111": 72, "din17int": 72, "din18": 72, "din18100": 72, "din18101": 72, "din18int": 72, "din19": 72, "din19100": 72, "din19101": 72, "din19int": 72, "din1int": 72, "din2": 72, "din20": 72, "din2000": 72, "din2001": 72, "din20100": 72, "din20101": 72, "din20int": 72, "din21": 72, "din21101": 72, "din21110": 72, "din21int": 72, "din22": 72, "din22110": 72, "din22111": 72, "din22int": 72, "din23": 72, "din23110": 72, "din23111": 72, "din23int": 72, "din24": 72, "din24110": 72, "din24111": 72, "din24int": 72, "din25": 72, "din25100": 72, "din25111": 72, "din25int": 72, "din26": 72, "din26100": 72, "din26101": 72, "din26int": 72, "din27": 72, "din27100": 72, "din27101": 72, "din27int": 72, "din28": 72, "din28100": 72, "din28101": 72, "din28int": 72, "din29": 72, "din29101": 72, "din29110": 72, "din29int": 72, "din2int": 72, "din3": 72, "din30": 72, "din3001": 72, "din3010": 72, "din30110": 72, "din30111": 72, "din30int": 72, "din31": 72, "din31110": 72, "din31111": 72, "din31int": 72, "din3int": 72, "din4": 72, "din4010": 72, "din4011": 72, "din4int": 72, "din5": 72, "din5010": 72, "din5011": 72, "din5int": 72, "din6": 72, "din6010": 72, "din6011": 72, "din6int": 72, "din7": 72, "din7000": 72, "din7011": 72, "din7int": 72, "din8": 72, "din8000": 72, "din8001": 72, "din8int": 72, "din9": 72, "din9000": 72, "din9001": 72, "din9int": 72, "dinpin": [98, 111, 126], "dip": [81, 96], "dipa": 96, "dipb": 96, "direct": [36, 55, 81, 91], "direct0": [45, 53, 65, 103, 115, 129, 138], "directli": [14, 17, 35, 36, 46, 58, 81, 82, 91, 151, 162], "dis_tstblclamp": 136, "dis_tstfiforst": [125, 136], "dis_vgg_reg": 128, "disabl": [36, 162], "disable111": 146, "disable_aspm_l1_tim": [135, 143], "disable_aspm_l1_timerpci": [135, 143], "disable_attr": [47, 61, 74, 83], "disable_attrbufg1": 74, "disable_attrbufgmux0": 47, "disable_attrbufgmux2": 47, "disable_attrbufgmux6": 47, "disable_attrbufgmux7": 47, "disable_attrint": 74, "disable_bar_filt": [70, 135, 143], "disable_err_msg": 143, "disable_gt": [57, 93], "disable_gtsiob0": 57, "disable_gtsiob1": 93, "disable_gtsiob2": [57, 93], "disable_gtsiob3": 57, "disable_gtsiob4": [57, 93], "disable_id_check": [70, 135, 143], "disable_id_checkpci": [135, 143], "disable_jtag": 126, "disable_lane_revers": [135, 143], "disable_lane_reversalpci": 135, "disable_locked_filt": 143, "disable_ppm_filt": 143, "disable_ppm_filterpci": 143, "disable_rx_poisoned_resp": 143, "disable_rx_poisoned_resppci": 143, "disable_rx_tc_filt": [135, 143], "disable_scrambl": [70, 135, 143], "disable_scramblingpci": 143, "disable_vrd_reg": 62, "disablebandgap": 85, "disablebandgapmisc": 85, "disablevgggener": 85, "disablevgggenerationmisc": 85, "disconnect": [55, 162], "displac": 58, "dispmp1": 75, "dispmp2": 75, "distanc": [2, 3, 4, 5, 6, 7, 8, 9, 55, 58, 91], "distribut": [41, 54, 55, 58, 87, 90, 91, 131, 139], "distrubut": 131, "div12110": 69, "div2001": 69, "div201": 69, "div4010": 69, "div410": 69, "div60": 69, "div6011": 69, "div71": 69, "div8100": 69, "divclk11": 61, "divid": [11, 12, 58, 61, 104, 117, 131, 139, 150, 162], "divide_100": 61, "divide_1000": 61, "divide_2001": 61, "divide_201": 61, "divide_300": 61, "divide_3010": 61, "divide_400": 61, "divide_4011": 61, "divide_501": 61, "divide_5100": 61, "divide_601": 61, "divide_6101": 61, "divide_710": 61, "divide_7110": 61, "divide_810": 61, "divide_8111": 61, "divide_bypass": 61, "divis": [96, 160], "dll": [51, 74, 78, 86, 92], "dll_": [52, 64], "dll_c": [52, 64], "dll_control_clock_spe": 102, "dll_control_clock_speeddcm": 102, "dll_ctl_sel_clkin_div2": 102, "dll_ctl_sel_clkin_div2dcm": 102, "dll_dead_tim": 102, "dll_deskew_lock_by1": 102, "dll_deskew_lock_by1dcm": 102, "dll_deskew_maxtap": 102, "dll_deskew_mintap": 102, "dll_enabl": [51, 52, 64, 76, 86, 102], "dll_enabledcm": [51, 52, 102], "dll_enabledcm0": 64, "dll_enabledcm1": 64, "dll_enablemisc": 76, "dll_frequency_mod": [51, 52, 64, 86, 102], "dll_frequency_modedcm": 52, "dll_frequency_modedcm0": 64, "dll_frequency_modedcm1": 64, "dll_live_tim": 102, "dll_pd_dly_sel": 102, "dll_period_lock_by1": 102, "dll_period_lock_by1dcm": 102, "dll_phase_detector_auto_reset": 102, "dll_phase_detector_auto_resetdcm": 102, "dll_phase_detector_mod": 102, "dll_phase_detector_modedcm": 102, "dll_phase_shift_calibr": 102, "dll_phase_shift_hfc": 102, "dll_phase_shift_lfc": 102, "dll_phase_shift_lock_by1": 102, "dll_phase_shift_lock_by1dcm": 102, "dll_settle_tim": 102, "dll_spare": 102, "dll_test_mux_sel": 102, "dll_wait_bl": 75, "dll_wait_br": 75, "dll_wait_tl": 75, "dll_wait_tr": 75, "dllc": [51, 86], "dllp": 78, "dma0_control": 124, "dma0_rxchannelctrl": 124, "dma0_rxirqtim": 124, "dma0_txchannelctrl": 124, "dma0_txirqtim": 124, "dma1_control": 124, "dma1_rxchannelctrl": 124, "dma1_rxirqtim": 124, "dma1_txchannelctrl": 124, "dma1_txirqtim": 124, "dma2_control": 124, "dma2_rxchannelctrl": 124, "dma2_rxirqtim": 124, "dma2_txchannelctrl": 124, "dma2_txirqtim": 124, "dma3_control": 124, "dma3_rxchannelctrl": 124, "dma3_rxirqtim": 124, "dma3_txchannelctrl": 124, "dma3_txirqtim": 124, "dma_test": 124, "dmux": 145, "dna_opt": 63, "dna_port": [56, 63, 126], "dnstream_link_num": [135, 143, 144], "do": [35, 46, 81, 82, 91, 96, 142], "do1": 145, "do11000": 145, "do11001": 145, "do11010": 145, "do11011": 145, "doa": [81, 96], "doa0": [72, 96], "doa0int": 72, "doa1": 72, "doa10": 72, "doa10int": 72, "doa11": 72, "doa11int": 72, "doa12": 72, "doa12int": 72, "doa13": 72, "doa13int": 72, "doa14": 72, "doa14int": 72, "doa15": 72, "doa15int": 72, "doa1int": 72, "doa2": 72, "doa3": 72, "doa31": 96, "doa4": 72, "doa4int": 72, "doa5": 72, "doa6": 72, "doa6int": 72, "doa7": 72, "doa8": 72, "doa8int": 72, "doa9": 72, "doa9int": 72, "doa_reg": [45, 59, 96], "doa_reg_l": [110, 125, 136], "doa_reg_u": [110, 125, 136], "dob": [81, 96], "dob0": 72, "dob0int": 72, "dob1": 72, "dob10": [72, 96], "dob10int": 72, "dob11": [72, 96], "dob11int": 72, "dob12": 72, "dob12int": 72, "dob13": 72, "dob13int": 72, "dob14": 72, "dob14int": 72, "dob15": 72, "dob15int": 72, "dob1int": 72, "dob2": 72, "dob3": 72, "dob4": [72, 96], "dob4int": 72, "dob5": [72, 96], "dob6": [72, 96], "dob6int": 72, "dob7": [72, 96], "dob8": [72, 96], "dob8int": 72, "dob9": [72, 96], "dob9int": 72, "dob_reg": [45, 59, 96], "dob_reg_l": [110, 125, 136], "dob_reg_u": [110, 125, 136], "document": [15, 16, 38, 39, 40, 41, 43, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 57, 60, 62, 63, 64, 65, 66, 67, 69, 71, 75, 78, 81, 82, 83, 84, 85, 86, 88, 89, 93, 94, 95, 98, 99, 101, 104, 105, 106, 107, 108, 111, 112, 114, 117, 118, 119, 120, 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"pmcapabilitydsipci": 123, "pmcapabilitynextptr": 123, "pmcapabilitypmesupport": 123, "pmcd0": 97, "pmcd0_clka10001000001": 97, "pmcd0_clka1d20010000010": 97, "pmcd0_clka1d40010000100": 97, "pmcd0_clka1d80100001000": 97, "pmcd0_clkb10010010000": 97, "pmcd0_clkc10010001000": 97, "pmcd0_clkd10010100000": 97, "pmcd1": 97, "pmcd1_clka10100000010": 97, "pmcd1_clka1d20100000100": 97, "pmcd1_clka1d40100000001": 97, "pmcd1_clka1d81000010000": 97, "pmcd1_clkb10100100000": 97, "pmcd1_clkc10010000001": 97, "pmcd1_clkd10100010000": 97, "pmcd_sync": 102, "pmdata0": 123, "pmdata1": 123, "pmdata2": 123, "pmdata3": 123, "pmdata4": 123, "pmdata5": 123, "pmdata6": 123, "pmdata7": 123, "pmdata8": 123, "pmdatascale0": 123, "pmdatascale1": 123, "pmdatascale2": 123, "pmdatascale3": 123, "pmdatascale4": 123, "pmdatascale5": 123, "pmdatascale6": 123, "pmdatascale7": 123, "pmdatascale8": 123, "pmstatuscontroldatascal": 123, "pmv": [56, 63, 92], "pmviob": [131, 132], "point": [82, 104, 131], "poke": 142, "polar": [34, 36, 162], "polarity_drp_en_0": 66, "polarity_drp_en_1": 66, "polarity_drp_en_1gtp": 66, "por": 162, "port": [56, 81, 91, 92, 96], "port_config": 69, "port_en": [151, 152, 153, 154, 155, 156, 157, 160, 162], "porta_attr": 72, "portb_attr": 72, "portvccapabilityextendedvccount": 123, "portvccapabilityvcarbcap": 123, "portvccapabilityvcarbtableoffset": 123, "pos_edg": 61, "pos_edge_1000": 61, "pos_edge_2001": 61, "pos_edge_3000": 61, "pos_edge_4011": 61, "pos_edge_5000": 61, "pos_edge_6101": 61, "pos_edge_7110": 61, "pos_edge_8111": 61, "posedg": [36, 46, 82, 162], "posit": [35, 139, 150], "possess": 35, "possibl": [17, 55, 81, 91, 142, 151, 162], "post_crc_clk": 128, "post_crc_correct": 128, "post_crc_en": [49, 62, 114, 128], "post_crc_freq": [49, 62, 128], "post_crc_init_flag": [62, 128], "post_crc_keep": [49, 62, 128], "post_crc_no_pin": 114, "post_crc_oneshot": 62, "post_crc_reconfig": [114, 128], "post_crc_sel": [62, 114, 128], "potenti": 36, "power": [12, 17, 34, 35, 36, 151, 160, 162], "power_en": 105, "powerdown": [54, 67], "powerdown_statu": [84, 101], "powerdownpin": [76, 85, 98], "powerdownpinmisc": [76, 85], "powerpc": [44, 82, 90, 92, 96, 120], "powerup_clk": 76, "powerup_delai": 76, "ppc": [87, 90, 104, 117, 124], "ppcdm_asyncmod": 124, "ppcds_asyncmod": 124, "ppcm_arbconfig": 124, "ppcm_control": 124, "ppcm_counter": 124, "ppcs0_addrmap_tmpl0": 124, "ppcs0_addrmap_tmpl1": 124, "ppcs0_addrmap_tmpl2": 124, "ppcs0_addrmap_tmpl3": 124, "ppcs0_control": 124, "ppcs0_width_128n64": 124, "ppcs1_addrmap_tmpl0": 124, "ppcs1_addrmap_tmpl1": 124, "ppcs1_addrmap_tmpl2": 124, "ppcs1_addrmap_tmpl3": 124, "ppcs1_control": 124, "ppcs1_width_128n64": 124, "ppds_250111": 57, "ppds_2501110000101": 50, "ppds_330111": 57, "ppds_3301110000101": 50, "pq100": [18, 19, 29, 34], "pq160": [18, 19, 22, 34], "pq208": [3, 6, 7, 12, 24, 25, 34, 155, 156, 157, 160], "practic": 91, "prbs_drp_en_0": 66, "prbs_drp_en_1": 66, "prbs_drp_en_1gtp": 66, "prbs_err_threshold_0": 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15, 16, 17, 33, 36, 150, 159, 160, 162], "program011": 63, "program_b": [108, 122, 134, 142], "program_tim": 17, "programm": [35, 36, 55, 91, 162], "progress": 35, "prom_data": 109, "propag": [36, 46, 82], "properti": 139, "proport": [104, 117, 131, 139], "protect": [14, 36, 150, 162], "provid": [17, 58, 87, 104, 117, 139, 150, 151], "ps_center": [51, 86, 102], "ps_centereddcm": 102, "ps_direct": 102, "ps_directdcm": 102, "ps_enabl": [51, 52, 86, 102], "ps_enabledcm": [51, 102], "ps_mode": [51, 86, 102], "ps_modedcm": 102, "ps_variabl": 52, "psclk101": 55, "psen": [51, 52, 64, 86, 102], "psen010": 55, "psendcm": [86, 102], "psincdec": [51, 52, 64, 86, 102], "psincdec100": 55, "psincdecdcm": 86, "pslew": [57, 63, 108], "pslew4_in": 126, "pslewiostd": [57, 108], "pt": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 150, 151, 152, 153, 154, 155, 156, 157, 162], "pt0": [16, 162], "pt00": [2, 3, 4, 5, 6, 7, 8, 9, 15], "pt000": 16, "pt0010": [2, 3, 4, 5, 6, 7, 8, 9], "pt01": [2, 3, 4, 5, 6, 7, 8, 9], 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56, 58, 92, 96, 139], "vertic": [38, 46, 47, 54, 55, 81, 82, 87, 91, 96, 131, 139], "vf0_ari_cap_nextptr": 144, "vf0_capability_point": 144, "vf0_msix_cap_pba_offset": 144, "vf0_msix_cap_table_offset": 144, "vf0_msix_cap_table_s": 144, "vf0_pm_cap_id": 144, "vf0_pm_cap_nextptr": 144, "vf0_pm_cap_ver_id": 144, "vf0_tphr_cap_nextptr": 144, "vf0_tphr_cap_st_mode_sel": 144, "vf0_tphr_cap_st_table_loc": 144, "vf0_tphr_cap_st_table_s": 144, "vf0_tphr_cap_ver": 144, "vf1_ari_cap_nextptr": 144, "vf1_msix_cap_pba_offset": 144, "vf1_msix_cap_table_offset": 144, "vf1_msix_cap_table_s": 144, "vf1_pm_cap_id": 144, "vf1_pm_cap_nextptr": 144, "vf1_pm_cap_ver_id": 144, "vf1_tphr_cap_nextptr": 144, "vf1_tphr_cap_st_mode_sel": 144, "vf1_tphr_cap_st_table_loc": 144, "vf1_tphr_cap_st_table_s": 144, "vf1_tphr_cap_ver": 144, "vf2_ari_cap_nextptr": 144, "vf2_msix_cap_pba_offset": 144, "vf2_msix_cap_table_offset": 144, "vf2_msix_cap_table_s": 144, "vf2_pm_cap_id": 144, "vf2_pm_cap_nextptr": 144, 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"yq0111111": 73, "z": 35, "zclk_div2": 85, "zd1_by1": [51, 86], "zd1_by1dcm": 51, "zd2_by1": [51, 86], "zd2_by1dcm": 51, "zero": 162, "zia": [14, 159, 161], "zia_gclk": [150, 162], "zia_gclk0_en": [152, 153, 154, 155, 156, 157], "zia_gclk1_en": [152, 153, 154, 155, 156, 157], "zia_gclk2_en": [152, 153, 154, 155, 156, 157], "zia_gclk3_en": [152, 153, 154, 155, 156, 157], "zynq": 139, "\u00b5": [17, 35]}, "titles": ["Project Combine", "Bitstream structure", "XC2C128, XA2C128", "XC2C256, XA2C256", "XC2C32", "XC2C32A, XA2C32A", "XC2C384, XA2C384", "XC2C512", "XC2C64", "XC2C64A, XA2C64A", "Database \u2014 devices", "Xilinx Coolrunner II CPLDs", "Introduction", "JTAG interface", "Device structure", "Bitstream structure \u2014 XC9500", "Bitstream structure \u2014 XC9500XL/XV", "Database schema", "XC95108", "XC95144", "XC95144XL, XA95144XL", "XC95144XV", "XC95216", "XC95288", "XC95288XL", "XC95288XV", "XC9536", "XC9536XL, XA9536XL", "XC9536XV", "XC9572", "XC9572XL, XA9572XL", "XC9572XV", "Database \u2014 devices", "Xilinx XC9500, XC9500XL, XC9500XV CPLDs", "Introduction", "JTAG interface", "Device structure", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "Corners", "FPGAcore", "General interconnect", "Input / Output", "Xilinx FPGAs", "Block RAM", "Configurable Logic Block", "Clock interconnect", "Configuration registers \u2014 Spartan 3, Spartan 3E", "Configuration registers \u2014 Spartan 3A and 3A DSP", "Corners", "Digital Clock Managers \u2014 Spartan 3", "Digital Clock Managers \u2014 Spartan 3E, 3A", "DSP", "Spartan 3", "General interconnect", "Introduction", "Input / Output", "Device geometry", "Block RAM", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "Corners", "Digital clock manager", "DSP", "Multi-gigabit transceivers", "Spartan 6", "General interconnect", "Memory Controller Block", "PCI Express", "Phase-locked loop", "Block RAM", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "Corners", "Delay Locked Loop", "Virtex", "Input/Output", "PCI Logic", "Block RAM \u2014 Virtex 2, Spartan 3", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "Corners", "Digital Clock Managers", "Device geometry", "Multi-gigabit transceivers \u2014 Virtex 2 Pro", "Multi-gigabit transceivers \u2014 Virtex 2 Pro X", "Virtex 2", "General interconnect", "Introduction", "Input / Output", "Hard PCI logic", "Hard PowerPC 405 cores", "Block RAM", "Clock Companion Modules", "Configuration Center", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "Digital Clock Managers", "DSP", "Device geometry", "Multi-gigabit transceivers", "Virtex 4", "General Interconnect", "Input/Output", "System monitor", "Block RAM", "Configuration Center", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "DSP", "Ethernet MACs", "Device geometry", "GTP transceivers", "GTX transceivers", "Virtex 5", "Interconnect", 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"boundari": [13, 35, 161], "br": [52, 76, 146], "bram": [45, 55, 58, 81, 91, 141], "bu": [36, 83], "buffer": [14, 15, 36, 43, 57, 58, 79, 87, 93, 162], "buse": 82, "carri": [46, 82], "cclk_freq": [49, 62], "center": [38, 47, 98, 104, 111, 117, 126, 131, 139], "check": 35, "clb": [42, 55, 91], "clbll": [112, 127, 137], "clblm": [112, 127, 137], "clexl": 60, "clexm": 60, "clk": 93, "clk_b": [91, 93], "clk_cmt_b": 113, "clk_cmt_t": 113, "clk_dcm_b": 100, "clk_dcm_t": 100, "clk_hrow": [100, 113], "clk_iob_b": [100, 113], "clk_iob_t": [100, 113], "clk_mgt_b": 113, "clk_mgt_t": 113, "clk_t": [91, 93], "clk_term_b": 100, "clk_term_t": 100, "clkb": [38, 47, 55, 74, 83, 149], "clkb_2dll": 74, "clkb_4dll": 74, "clkc": [38, 47, 61], "clkc_50a": 47, "clkh": 149, "clkl": [47, 80, 149], "clkpad": 91, "clkr": [47, 80, 149], "clkt": [38, 47, 55, 74, 83, 149], "clkt_2dll": 74, "clkt_4dll": 74, "clkv": [74, 149], "clkv_bram_bot": 74, "clkv_bram_top": 74, "clock": [14, 38, 47, 51, 52, 58, 61, 64, 74, 83, 86, 87, 91, 97, 100, 102, 113], "cmt": [68, 113], "cnr": [76, 91, 146], "column": [58, 72, 104, 117, 131, 139, 162], "combin": 0, "companion": 97, "configur": [14, 36, 37, 39, 46, 48, 49, 60, 62, 73, 75, 82, 84, 98, 99, 101, 111, 112, 114, 126, 127, 128, 137, 139, 145, 162], "content": [0, 10, 11, 32, 33, 41, 44, 54, 67, 78, 90, 106, 120, 132, 140, 147, 158, 159], "control": [69, 162], "coolrunn": 11, "cor": [39, 48, 75, 84, 101, 114, 128], "cor1": [49, 62, 114, 128], "cor2": [49, 62], "core": [95, 123, 124, 135, 143, 144], "corner": [40, 50, 63, 76, 85, 146], "cpld": [11, 33, 159], "ctl": [39, 48, 49, 62, 75, 84, 101, 114, 128], "ctl1": 128, "data": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 50, 85, 100, 152, 153, 154, 155, 156, 157], "databas": [10, 17, 32, 151, 158], "dcm": [51, 52, 55, 58, 83, 86, 91, 100], "dcm_bufpll": 61, "dcmconn": 83, "default": [45, 47], "delai": [77, 121, 133, 141], "deskew_adjust": [51, 52, 86], "devic": [10, 12, 14, 17, 32, 34, 36, 56, 58, 87, 92, 104, 117, 131, 139, 151, 158, 160, 162], "digit": [51, 52, 64, 86, 102], "distribut": [38, 47, 83], "divid": 14, "dll": 77, "dllp": 77, "dr": 35, "dsp": [49, 53, 55, 58, 65, 103, 115, 129, 138], "dual": [46, 82], "dummi": 55, "e": [79, 91], "ecc": [96, 104, 117, 131, 139], "enabl": 15, "enter": 35, "eras": 35, "ethernet": [116, 130], "exit": 35, "export": 36, "express": [70, 123, 135, 139, 143, 144], "eye_mask": 62, "fb": [14, 15, 16, 36, 150, 162], "fc": [38, 39, 40, 42, 43], "fclk": 162, "fifo": 96, "flip": 36, "flop": 36, "format": [15, 16], "fpga": 44, "fpgacor": 41, "frequenc": 35, "function": [108, 122, 134, 142], "fuse": [15, 16, 35, 36, 150], "gate": [14, 36], "gclkc": 83, "gclkh": [38, 47, 83], "gclkv": 74, "gclkvc": [38, 47], "gclkvm": [38, 47], "gen2": 143, "gen3": 144, "gener": [42, 49, 55, 58, 62, 68, 87, 91, 104, 107, 117, 131, 139], "general5": 62, "geometri": [58, 87, 104, 117, 131, 139], "gigabit": [66, 88, 89, 105], "gigabit10": 89, "global": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 36, 150, 152, 153, 154, 155, 156, 157], "gt": 91, "gtp": [118, 139], "gtx": [119, 139], "hard": [94, 95], "hc_opt": [49, 62], "hclk": [61, 100, 113], "hclk_center": 100, "hclk_center_above_cfg": 100, "hclk_cmt": 113, "hclk_cmt_ioi": 113, "hclk_dcm": 100, "hclk_dcmiob": 100, "hclk_iobdcm": 100, "hclk_ioi": 113, "hclk_ioi_botcen": 113, "hclk_ioi_cent": 113, "hclk_ioi_cmt": 113, "hclk_ioi_topcen": 113, "hclk_iois_dci": 100, "hclk_iois_lvd": 100, "hclk_mgt": 100, "hclk_row": 61, "hclk_term_l": 100, "hclk_term_r": 100, "hole": [87, 91, 104, 117, 139], "horizont": 58, "i": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 57, 79, 85, 93, 100, 108, 122, 134, 142, 152, 153, 154, 155, 156, 157], "ibuf": 23, "idcod": [35, 161], "ii": 11, "import": 36, "imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 150, 152, 153, 154, 155, 156, 157], "input": [14, 15, 16, 36, 43, 55, 57, 79, 91, 93, 108, 122, 134, 142, 148, 162], "instruct": [13, 35, 161], "int": [42, 55, 91], "interconnect": [38, 42, 47, 55, 61, 68, 74, 83, 91, 100, 107, 113, 121, 133, 141], "interfac": [13, 35, 43, 55, 57, 68, 91, 93, 107, 161], "intf": [55, 68, 91, 121, 133, 141], "introduct": [12, 34, 56, 92, 160], "io": [58, 79, 87, 100, 113, 139, 148], "iob": [2, 3, 6, 7, 14, 43, 57, 79, 93, 100, 113, 150, 162], "ioi": [42, 43, 55, 57, 68, 91, 93], "ir": [13, 35, 161], "isp": [13, 35, 161], "jed": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 150, 151, 152, 153, 154, 155, 156, 157], "jtag": [13, 35, 161], "keeper": 36, "l": [43, 79, 93, 148], "l1": [57, 93], "l2": [57, 93], "l3": 57, "l4": 57, "lb": 52, "left": [40, 47, 50, 61, 63, 72, 85], "level": [17, 151], "line": 55, "ll": [40, 50, 85], "llh": 55, "llv": 55, "local": 162, "lock": [71, 77], "logic": [37, 46, 60, 73, 80, 82, 87, 94, 99, 112, 127, 137, 145], "long": 55, "loop": [71, 77], "lower": [40, 50, 63, 85], "lr": [40, 50, 55, 57, 85], "lt": 52, "lut": [46, 82], "lut2": 162, "mac": [116, 130], "macrocel": [14, 15, 16, 36, 150, 162], "manag": [51, 52, 64, 86, 102], "map": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 150, 152, 153, 154, 155, 156, 157], "mc": [2, 3, 4, 5, 6, 7, 8, 9], "memori": 69, "mgt": [100, 113], "middl": [72, 139], "misc": [14, 36, 162], "mode": [35, 49, 62, 96], "modul": 97, "monitor": 109, "mult": 81, "multi": [66, 88, 89, 105], "multiplex": [46, 55, 82, 91], "mux": [100, 113], "n": [47, 91], "network": [14, 36, 162], "node": [100, 113], "normal": 68, "o": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 57, 79, 85, 93, 100, 108, 122, 134, 142, 152, 153, 154, 155, 156, 157], "option": [45, 47], "output": [14, 36, 43, 46, 55, 57, 79, 82, 83, 91, 93, 108, 122, 134, 142, 148, 162], "overview": [14, 36, 162], "packag": [12, 34, 160], "part": [17, 151], "pci": [70, 80, 87, 94, 123, 135, 139, 143, 144], "pci_ce_delai": 61, "pcie_l": 143, "pcie_r": 143, "pcilogics": 61, "per": [15, 16], "phase": 71, "pin": [2, 3, 4, 5, 6, 7, 8, 9, 12, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34, 152, 153, 154, 155, 156, 157, 160], "placement": 139, "pll_bufpll_b": 61, "pll_bufpll_out0": 61, "pll_bufpll_out1": 61, "pll_bufpll_t": 61, "pma_spe": 89, "pmviob": 126, "port": [46, 82], "powerdown": [49, 62], "powerpc": [87, 91, 95, 104, 117, 124], "ppc": 91, "primari": 58, "primit": [55, 91], "pro": [85, 88, 89, 93], "process": 139, "product": [14, 15, 16, 36, 82, 150, 162], "program": [13, 35, 161], "project": 0, "protect": 35, "pt": 36, "pu_gt": [49, 62], "pu_gw": [49, 62], "pull": 36, "r": [43, 79, 93, 148], "r1": [57, 93], "r2": [57, 93], "r3": 57, "r4": 57, "ram": [45, 46, 59, 72, 81, 82, 96, 110, 125, 136], "randor": [37, 46], "randor_init": [37, 46], "rb": 52, "read": 35, "regist": [13, 14, 35, 39, 46, 48, 49, 62, 75, 82, 84, 101, 114, 128, 161, 162], "repeat": [100, 113], "reserved_andor": [37, 46], "right": [40, 47, 50, 61, 63, 72, 85, 139], "row": [38, 47, 58, 83, 87, 100, 162], "rt": 52, "s3": [38, 39, 45, 47, 48, 50, 51, 55, 57], "s3a": [45, 47, 49, 50, 55, 57], "s3adsp": [45, 55], "s3e": [45, 47, 48, 50, 52, 55, 57], "scan": [13, 35, 161], "schema": [17, 151], "secondari": [38, 47, 58], "sequenc": [13, 35, 161], "seu_opt": [49, 62], "shift": [46, 82], "side": 72, "singl": [46, 82], "sourc": [38, 47, 83], "spartan": [46, 48, 49, 50, 51, 52, 54, 57, 58, 67, 81], "special": [108, 122, 134, 142], "speed": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 151, 152, 153, 154, 155, 156, 157], "spine": [38, 47, 58, 83, 87, 91, 100, 104, 113, 117], "splitter": [55, 149], "standard": 100, "structur": [1, 14, 15, 16, 36, 58, 87, 104, 117, 131, 139, 150, 162], "sum": [14, 36, 82, 150, 162], "system": [109, 139], "t": [43, 57, 79, 83, 88, 89, 93, 148], "t0": 91, "t1": 57, "t123": 91, "t2": [57, 93], "t3": 57, "t4": 57, "tabl": [56, 71, 92], "tb": 55, "tbuf": 82, "tclkpad": 91, "term": [14, 15, 16, 36, 91, 150, 162], "termin": [55, 91, 100], "testmod": [62, 128], "tile": [17, 38, 42, 43, 47, 55, 61, 68, 83, 91, 107, 151], "timer": [62, 114, 128], "tl": [52, 76, 146], "todo": [1, 12, 13, 14, 35, 36, 38, 39, 40, 41, 43, 46, 47, 48, 49, 50, 51, 52, 53, 54, 56, 57, 58, 60, 62, 63, 64, 65, 66, 67, 69, 71, 75, 78, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 98, 100, 101, 104, 105, 106, 107, 111, 112, 113, 114, 117, 118, 119, 120, 121, 126, 127, 128, 131, 132, 133, 137, 139, 140, 141, 142, 147, 161, 162], "top": [17, 38, 47, 61, 72, 77, 83, 91, 151], "tr": [52, 76, 146], "transceiv": [66, 88, 89, 105, 118, 119, 139], "trim": 128, "tristat": 82, "uim": [15, 23, 36], "ul": [40, 50, 85], "uni": 47, "univers": 162, "unk1c": 128, "up": 36, "upper": [40, 50, 63, 85], "ur": [40, 50, 85], "v": 79, "v2": [83, 85, 86, 91, 93], "v2p": [83, 85, 86, 91, 93], "v2px": 83, "valu": [45, 89], "ve": 79, "vertic": 58, "virtex": [46, 78, 79, 81, 85, 88, 89, 90, 93, 106, 120, 132, 140], "w": 91, "wide": [46, 82], "wire": 15, "without": [2, 3, 6, 7, 150], "write": 35, "x": [46, 82, 89], "xa2c128": 2, "xa2c256": 3, "xa2c32a": 5, "xa2c384": 6, "xa2c64a": 9, "xa95144xl": 20, "xa9536xl": 27, "xa9572xl": 30, "xc2c128": 2, "xc2c256": 3, "xc2c32": 4, "xc2c32a": 5, "xc2c384": 6, "xc2c512": 7, "xc2c64": 8, "xc2c64a": 9, "xc5200": 147, "xc9500": [15, 33, 35, 36], "xc9500xl": [16, 33, 35, 36], "xc9500xv": 33, "xc95108": 18, "xc95144": 19, "xc95144xl": 20, "xc95144xv": 21, "xc95216": 22, "xc95288": 23, "xc95288xl": 24, "xc95288xv": 25, "xc9536": 26, "xc9536xl": 27, "xc9536xv": 28, "xc9572": 29, "xc9572xl": 30, "xc9572xv": 31, "xcr3032xl": 152, "xcr3064xl": 153, "xcr3128xl": 154, "xcr3256xl": 155, "xcr3384xl": 156, "xcr3512xl": 157, "xilinx": [11, 33, 44, 159], "xor": [14, 36], "xpla3": 159, "xv": [16, 35, 36], "zia": 162}})
\ No newline at end of file
+Search.setIndex({"alltitles": {"AIM and FB inputs": [[14, "aim-and-fb-inputs"]], "BRAM.S3": [[45, "bram-s3"]], "BRAM.S3A": [[45, "bram-s3a"]], "BRAM.S3ADSP": [[45, "bram-s3adsp"]], "BRAM.S3E": [[45, "bram-s3e"]], "Backbone": [[55, "backbone"], [91, "backbone"]], "Bank configuration": [[14, "bank-configuration"]], "Bitstream": [[37, "bitstream"], [45, "bitstream"], [46, "bitstream"], [53, "bitstream"], [59, "bitstream"], [64, "bitstream"], [65, "bitstream"], [66, "bitstream"], [69, "bitstream"], [70, "bitstream"], [71, "bitstream"], [73, "bitstream"], [81, "bitstream"], [82, "bitstream"], [88, "bitstream"], [89, "bitstream"], [96, "bitstream"], [97, "bitstream"], [98, "bitstream"], [99, "bitstream"], [102, "bitstream"], [103, "bitstream"], [105, "bitstream"], [107, "bitstream"], [108, "bitstream"], [109, "bitstream"], [110, "bitstream"], [111, "bitstream"], [115, "bitstream"], [116, "bitstream"], [118, "bitstream"], [119, "bitstream"], [121, "bitstream"], [122, "bitstream"], [123, "bitstream"], [124, "bitstream"], [125, "bitstream"], [126, "bitstream"], [129, "bitstream"], [130, "bitstream"], [132, "bitstream"], [134, "bitstream"], [135, "bitstream"], [136, "bitstream"], [137, "bitstream"], [139, "bitstream"], [142, "bitstream"], [145, "bitstream"], [146, "bitstream"]], "Bitstream geometry": [[58, "bitstream-geometry"], [87, "bitstream-geometry"], [104, "bitstream-geometry"], [117, "bitstream-geometry"], [131, "bitstream-geometry"], [140, "bitstream-geometry"]], "Bitstream structure": [[1, "bitstream-structure"], [151, "bitstream-structure"]], "Bitstream structure \u2014 XC9500": [[15, "bitstream-structure-xc9500"]], "Bitstream structure \u2014 XC9500XL/XV": [[16, "bitstream-structure-xc9500xl-xv"]], "Bitstream \u2014 CLBLL": [[112, "bitstream-clbll"], [127, "bitstream-clbll"], [138, "bitstream-clbll"]], "Bitstream \u2014 CLBLM": [[112, "bitstream-clblm"], [127, "bitstream-clblm"], [138, "bitstream-clblm"]], "Bitstream \u2014 CLEXL": [[60, "bitstream-clexl"]], "Bitstream \u2014 CLEXM": [[60, "bitstream-clexm"]], "Bitstream \u2014 CLKC": [[61, "bitstream-clkc"]], "Bitstream \u2014 DCM_BUFPLL": [[61, "bitstream-dcm-bufpll"]], "Bitstream \u2014 HCLK": [[61, "bitstream-hclk"]], "Bitstream \u2014 HCLK_ROW": [[61, "bitstream-hclk-row"]], "Bitstream \u2014 INTF": [[121, "bitstream-intf"], [134, "bitstream-intf"], [142, "bitstream-intf"]], "Bitstream \u2014 INTF.BRAM": [[142, "bitstream-intf-bram"]], "Bitstream \u2014 INTF.DELAY": [[121, "bitstream-intf-delay"], [134, "bitstream-intf-delay"], [142, "bitstream-intf-delay"]], "Bitstream \u2014 IOI tile": [[68, "bitstream-ioi-tile"]], "Bitstream \u2014 LLH tiles": [[55, "bitstream-llh-tiles"]], "Bitstream \u2014 LLV tiles": [[55, "bitstream-llv-tiles"]], "Bitstream \u2014 PCILOGICSE": [[61, "bitstream-pcilogicse"]], "Bitstream \u2014 PLL_BUFPLL_B": [[61, "bitstream-pll-bufpll-b"]], "Bitstream \u2014 PLL_BUFPLL_OUT0": [[61, "bitstream-pll-bufpll-out0"]], "Bitstream \u2014 PLL_BUFPLL_OUT1": [[61, "bitstream-pll-bufpll-out1"]], "Bitstream \u2014 PLL_BUFPLL_T": [[61, "bitstream-pll-bufpll-t"]], "Bitstream \u2014 PMVIOB": [[126, "bitstream-pmviob"]], "Bitstream \u2014 PowerPC hole tiles": [[91, "bitstream-powerpc-hole-tiles"]], "Bitstream \u2014 bottom tile": [[61, "bitstream-bottom-tile"]], "Bitstream \u2014 bottom tiles": [[38, "bitstream-bottom-tiles"], [47, "bitstream-bottom-tiles"], [83, "bitstream-bottom-tiles"]], "Bitstream \u2014 column bottom": [[72, "bitstream-column-bottom"]], "Bitstream \u2014 column top": [[72, "bitstream-column-top"]], "Bitstream \u2014 interconnect tiles": [[42, "bitstream-interconnect-tiles"], [55, "bitstream-interconnect-tiles"], [91, "bitstream-interconnect-tiles"]], "Bitstream \u2014 interface tile": [[107, "bitstream-interface-tile"]], "Bitstream \u2014 interface tiles": [[55, "bitstream-interface-tiles"], [68, "bitstream-interface-tiles"], [91, "bitstream-interface-tiles"]], "Bitstream \u2014 left side": [[72, "bitstream-left-side"]], "Bitstream \u2014 left tile": [[61, "bitstream-left-tile"]], "Bitstream \u2014 left tiles": [[47, "bitstream-left-tiles"]], "Bitstream \u2014 middle": [[72, "bitstream-middle"]], "Bitstream \u2014 normal tile": [[68, "bitstream-normal-tile"]], "Bitstream \u2014 right side": [[72, "bitstream-right-side"]], "Bitstream \u2014 right tile": [[61, "bitstream-right-tile"]], "Bitstream \u2014 right tiles": [[47, "bitstream-right-tiles"]], "Bitstream \u2014 terminator tiles": [[91, "bitstream-terminator-tiles"]], "Bitstream \u2014 top tile": [[61, "bitstream-top-tile"]], "Bitstream \u2014 top tiles": [[38, "bitstream-top-tiles"], [47, "bitstream-top-tiles"], [83, "bitstream-top-tiles"]], "Blank check \u2014 XC9500XL/XV": [[35, "blank-check-xc9500xl-xv"]], "Block RAM": [[45, "block-ram"], [59, "block-ram"], [72, "block-ram"], [96, "block-ram"], [110, "block-ram"], [125, "block-ram"], [137, "block-ram"]], "Block RAM \u2014 Virtex 2, Spartan 3": [[81, "block-ram-virtex-2-spartan-3"]], "Bond": [[17, "bond"], [152, "bond"]], "Boundary scan register": [[13, "boundary-scan-register"], [35, "boundary-scan-register"], [162, "boundary-scan-register"]], "CCLK_FREQ": [[49, "cclk-freq"], [62, "cclk-freq"]], "CLKB": [[74, "clkb"], [150, "clkb"]], "CLKB.FC": [[38, "clkb-fc"]], "CLKB.S3": [[47, "clkb-s3"]], "CLKB.S3A": [[47, "clkb-s3a"]], "CLKB.S3E": [[47, "clkb-s3e"]], "CLKB.V2": [[83, "clkb-v2"]], "CLKB.V2P": [[83, "clkb-v2p"]], "CLKB.V2PX": [[83, "clkb-v2px"]], "CLKB_2DLL": [[74, "clkb-2dll"]], "CLKB_4DLL": [[74, "clkb-4dll"]], "CLKH": [[150, "clkh"]], "CLKL": [[80, "clkl"], [150, "clkl"]], "CLKL.S3A": [[47, "clkl-s3a"]], "CLKL.S3E": [[47, "clkl-s3e"]], "CLKR": [[80, "clkr"], [150, "clkr"]], "CLKR.S3A": [[47, "clkr-s3a"]], "CLKR.S3E": [[47, "clkr-s3e"]], "CLKT": [[74, "clkt"], [150, "clkt"]], "CLKT.FC": [[38, "clkt-fc"]], "CLKT.S3": [[47, "clkt-s3"]], "CLKT.S3A": [[47, "clkt-s3a"]], "CLKT.S3E": [[47, "clkt-s3e"]], "CLKT.V2": [[83, "clkt-v2"]], "CLKT.V2P": [[83, "clkt-v2p"]], "CLKT.V2PX": [[83, "clkt-v2px"]], "CLKT_2DLL": [[74, "clkt-2dll"]], "CLKT_4DLL": [[74, "clkt-4dll"]], "CLKV": [[150, "clkv"]], "CLKV.CLKV": [[74, "clkv-clkv"]], "CLKV.GCLKV": [[74, "clkv-gclkv"]], "CLKV_BRAM_BOT": [[74, "clkv-bram-bot"]], "CLKV_BRAM_TOP": [[74, "clkv-bram-top"]], "CLK_CMT_B": [[113, "clk-cmt-b"]], "CLK_CMT_T": [[113, "clk-cmt-t"]], "CLK_DCM_B": [[100, "clk-dcm-b"]], "CLK_DCM_T": [[100, "clk-dcm-t"]], "CLK_HROW": [[100, "clk-hrow"], [113, "clk-hrow"]], "CLK_IOB_B": [[100, "clk-iob-b"], [113, "clk-iob-b"]], "CLK_IOB_T": [[100, "clk-iob-t"], [113, "clk-iob-t"]], "CLK_MGT_B": [[113, "clk-mgt-b"]], "CLK_MGT_T": [[113, "clk-mgt-t"]], "CLK_TERM_B": [[100, "clk-term-b"]], "CLK_TERM_T": [[100, "clk-term-t"]], "CNR.BL": [[76, "cnr-bl"], [147, "cnr-bl"]], "CNR.BR": [[76, "cnr-br"], [147, "cnr-br"]], "CNR.TL": [[76, "cnr-tl"], [147, "cnr-tl"]], "CNR.TR": [[76, "cnr-tr"], [147, "cnr-tr"]], "COR": [[75, "cor"], [84, "cor"], [101, "cor"], [114, "cor"], [128, "cor"]], "COR.FC": [[39, "cor-fc"]], "COR.S3": [[48, "cor-s3"]], "COR.S3E": [[48, "cor-s3e"]], "COR1": [[62, "cor1"], [114, "cor1"], [128, "cor1"]], "COR1.S3A": [[49, "cor1-s3a"]], "COR2": [[62, "cor2"]], "COR2.S3A": [[49, "cor2-s3a"]], "CTL": [[62, "ctl"], [75, "ctl"], [84, "ctl"], [101, "ctl"], [114, "ctl"], [128, "ctl"]], "CTL.S3": [[39, "ctl-s3"], [48, "ctl-s3"]], "CTL.S3A": [[49, "ctl-s3a"]], "CTL1": [[128, "ctl1"]], "Carry logic": [[46, "carry-logic"], [82, "carry-logic"]], "Center column": [[104, "center-column"], [117, "center-column"], [131, "center-column"]], "Center column and configuration center": [[140, "center-column-and-configuration-center"]], "Clock Companion Modules": [[97, "clock-companion-modules"]], "Clock divider": [[14, "clock-divider"]], "Clock interconnect": [[38, "clock-interconnect"], [47, "clock-interconnect"], [61, "clock-interconnect"], [74, "clock-interconnect"], [83, "clock-interconnect"], [100, "clock-interconnect"], [113, "clock-interconnect"]], "Clock rows": [[58, "clock-rows"], [87, "clock-rows"]], "Clock source \u2014 left and right": [[47, "clock-source-left-and-right"]], "Clock source \u2014 spine bottom and top": [[38, "clock-source-spine-bottom-and-top"], [47, "clock-source-spine-bottom-and-top"], [83, "clock-source-spine-bottom-and-top"]], "Clock spine": [[87, "clock-spine"]], "Clock spine top and bottom": [[91, "clock-spine-top-and-bottom"]], "Configurable Logic Block": [[37, "configurable-logic-block"], [46, "configurable-logic-block"], [60, "configurable-logic-block"], [73, "configurable-logic-block"], [82, "configurable-logic-block"], [99, "configurable-logic-block"], [112, "configurable-logic-block"], [127, "configurable-logic-block"], [138, "configurable-logic-block"], [146, "configurable-logic-block"]], "Configuration Center": [[98, "configuration-center"], [111, "configuration-center"], [126, "configuration-center"]], "Configuration pull-ups": [[36, "configuration-pull-ups"]], "Configuration registers": [[39, "configuration-registers"], [62, "configuration-registers"], [75, "configuration-registers"], [84, "configuration-registers"], [101, "configuration-registers"], [114, "configuration-registers"], [128, "configuration-registers"]], "Configuration registers \u2014 Spartan 3, Spartan 3E": [[48, "configuration-registers-spartan-3-spartan-3e"]], "Configuration registers \u2014 Spartan 3A and 3A DSP": [[49, "configuration-registers-spartan-3a-and-3a-dsp"]], "Contents:": [[0, null], [10, null], [11, null], [32, null], [33, null], [41, null], [44, null], [54, null], [67, null], [78, null], [90, null], [106, null], [120, null], [133, null], [141, null], [148, null], [159, null], [160, null]], "Corners": [[40, "corners"], [50, "corners"], [63, "corners"], [76, "corners"], [85, "corners"], [147, "corners"]], "DCM output bus": [[83, "dcm-output-bus"]], "DCM.S3": [[51, "dcm-s3"]], "DCM.S3E.BL": [[52, "dcm-s3e-bl"]], "DCM.S3E.BR": [[52, "dcm-s3e-br"]], "DCM.S3E.LB": [[52, "dcm-s3e-lb"]], "DCM.S3E.LT": [[52, "dcm-s3e-lt"]], "DCM.S3E.RB": [[52, "dcm-s3e-rb"]], "DCM.S3E.RT": [[52, "dcm-s3e-rt"]], "DCM.S3E.TL": [[52, "dcm-s3e-tl"]], "DCM.S3E.TR": [[52, "dcm-s3e-tr"]], "DCM.V2": [[86, "dcm-v2"]], "DCM.V2P": [[86, "dcm-v2p"]], "DCMCONN.BOT": [[83, "dcmconn-bot"]], "DCMCONN.TOP": [[83, "dcmconn-top"]], "DESKEW_ADJUST": [[51, "deskew-adjust"], [52, "deskew-adjust"], [86, "deskew-adjust"]], "DLL.BOT": [[77, "dll-bot"]], "DLL.TOP": [[77, "dll-top"]], "DLLP.BOT": [[77, "dllp-bot"]], "DLLP.TOP": [[77, "dllp-top"]], "DLLS.BOT": [[77, "dlls-bot"]], "DLLS.TOP": [[77, "dlls-top"]], "DSP": [[53, "dsp"], [65, "dsp"], [103, "dsp"], [115, "dsp"], [129, "dsp"], [139, "dsp"]], "Database schema": [[17, "database-schema"], [152, "database-schema"]], "Database \u2014 devices": [[10, "database-devices"], [32, "database-devices"], [159, "database-devices"]], "Default option attributes": [[47, "default-option-attributes"]], "Default option values": [[45, "default-option-values"]], "Delay Locked Loop": [[77, "delay-locked-loop"]], "Device": [[17, "device"], [152, "device"]], "Device geometry": [[58, "device-geometry"], [87, "device-geometry"], [104, "device-geometry"], [117, "device-geometry"], [131, "device-geometry"], [140, "device-geometry"]], "Device pins": [[12, "device-pins"], [34, "device-pins"], [161, "device-pins"]], "Device structure": [[14, "device-structure"], [36, "device-structure"], [163, "device-structure"]], "Device table": [[56, "device-table"], [92, "device-table"]], "Devices": [[12, "devices"], [34, "devices"], [161, "devices"]], "Digital Clock Managers": [[86, "digital-clock-managers"], [102, "digital-clock-managers"]], "Digital Clock Managers \u2014 Spartan 3": [[51, "digital-clock-managers-spartan-3"]], "Digital Clock Managers \u2014 Spartan 3E, 3A": [[52, "digital-clock-managers-spartan-3e-3a"]], "Digital clock manager": [[64, "digital-clock-manager"]], "Dual-port 16\u00d7X RAM": [[46, "dual-port-16x-ram"], [82, "dual-port-16x-ram"]], "Dual-port 32\u00d7X RAM": [[82, "dual-port-32x-ram"]], "Dual-port 64\u00d71 RAM": [[82, "dual-port-641-ram"]], "ECC": [[104, "ecc"], [117, "ecc"], [131, "ecc"], [140, "ecc"]], "ECC mode": [[96, "ecc-mode"]], "EYE_MASK": [[62, "eye-mask"]], "Entering and exiting ISP mode \u2014 XC9500": [[35, "entering-and-exiting-isp-mode-xc9500"]], "Entering and exiting ISP mode \u2014 XC9500XL/XV": [[35, "entering-and-exiting-isp-mode-xc9500xl-xv"]], "Erasing fuses \u2014 XC9500": [[35, "erasing-fuses-xc9500"]], "Erasing fuses \u2014 XC9500XL/XV": [[35, "erasing-fuses-xc9500xl-xv"]], "Ethernet MACs": [[116, "ethernet-macs"], [130, "ethernet-macs"]], "FB columns and rows": [[163, "fb-columns-and-rows"]], "FB global fuses": [[36, "fb-global-fuses"]], "FCLK networks": [[163, "fclk-networks"]], "FIFO mode": [[96, "fifo-mode"]], "FPGAcore": [[41, "fpgacore"]], "Flip-flop": [[36, "flip-flop"]], "Frequency": [[35, "frequency"]], "Fuses \u2014 FB inputs": [[15, "fuses-fb-inputs"], [16, "fuses-fb-inputs"]], "Fuses \u2014 FBs": [[151, "fuses-fbs"]], "Fuses \u2014 IMUX bits": [[151, "fuses-imux-bits"]], "Fuses \u2014 UIM wire-AND": [[15, "fuses-uim-wire-and"]], "Fuses \u2014 global bits": [[151, "fuses-global-bits"]], "Fuses \u2014 input buffer enable": [[15, "fuses-input-buffer-enable"]], "Fuses \u2014 macrocells": [[15, "fuses-macrocells"], [16, "fuses-macrocells"], [151, "fuses-macrocells"]], "Fuses \u2014 per-FB bits and globals": [[15, "fuses-per-fb-bits-and-globals"], [16, "fuses-per-fb-bits-and-globals"]], "Fuses \u2014 product and sum terms": [[151, "fuses-product-and-sum-terms"]], "Fuses \u2014 product terms": [[15, "fuses-product-terms"], [16, "fuses-product-terms"]], "GCLKC": [[83, "gclkc"]], "GCLKC.B": [[83, "gclkc-b"]], "GCLKC.T": [[83, "gclkc-t"]], "GCLKH": [[38, "gclkh"], [47, "gclkh"], [83, "gclkh"]], "GCLKH.N": [[47, "gclkh-n"]], "GCLKH.S": [[47, "gclkh-s"]], "GCLKH.UNI": [[47, "gclkh-uni"]], "GCLKH.UNI.N": [[47, "gclkh-uni-n"]], "GCLKH.UNI.S": [[47, "gclkh-uni-s"]], "GCLKVM.S3": [[38, "gclkvm-s3"], [47, "gclkvm-s3"]], "GCLKVM.S3E": [[47, "gclkvm-s3e"]], "GENERAL5": [[62, "general5"]], "GENERAL[12]": [[49, "general-12"], [62, "general-12"]], "GENERAL[34]": [[62, "general-34"]], "GIGABIT.B": [[88, "gigabit-b"]], "GIGABIT.T": [[88, "gigabit-t"]], "GIGABIT10.B": [[89, "gigabit10-b"]], "GIGABIT10.T": [[89, "gigabit10-t"]], "GTP and GTX right column holes": [[140, "gtp-and-gtx-right-column-holes"]], "GTP transceivers": [[118, "gtp-transceivers"]], "GTX transceivers": [[119, "gtx-transceivers"], [132, "gtx-transceivers"]], "General Interconnect": [[107, "general-interconnect"]], "General interconnect": [[42, "general-interconnect"], [55, "general-interconnect"], [68, "general-interconnect"], [91, "general-interconnect"]], "General structure": [[58, "general-structure"], [87, "general-structure"], [104, "general-structure"], [117, "general-structure"], [131, "general-structure"], [140, "general-structure"]], "Global bits": [[2, "global-bits"], [3, "global-bits"], [4, "global-bits"], [5, "global-bits"], [6, "global-bits"], [7, "global-bits"], [8, "global-bits"], [9, "global-bits"], [153, "global-bits"], [154, "global-bits"], [155, "global-bits"], [156, "global-bits"], [157, "global-bits"], [158, "global-bits"]], "Global networks": [[14, "global-networks"]], "Global networks \u2014 XC9500": [[36, "global-networks-xc9500"]], "Global networks \u2014 XC9500XL/XV": [[36, "global-networks-xc9500xl-xv"]], "HCLK": [[100, "hclk"], [113, "hclk"]], "HCLK_CENTER": [[100, "hclk-center"]], "HCLK_CENTER_ABOVE_CFG": [[100, "hclk-center-above-cfg"]], "HCLK_CMT": [[113, "hclk-cmt"]], "HCLK_CMT_IOI": [[113, "hclk-cmt-ioi"]], "HCLK_DCM": [[100, "hclk-dcm"]], "HCLK_DCMIOB": [[100, "hclk-dcmiob"]], "HCLK_IOBDCM": [[100, "hclk-iobdcm"]], "HCLK_IOI": [[113, "hclk-ioi"]], "HCLK_IOIS_DCI": [[100, "hclk-iois-dci"]], "HCLK_IOIS_LVDS": [[100, "hclk-iois-lvds"]], "HCLK_IOI_BOTCEN": [[113, "hclk-ioi-botcen"]], "HCLK_IOI_CENTER": [[113, "hclk-ioi-center"]], "HCLK_IOI_CMT": [[113, "hclk-ioi-cmt"]], "HCLK_IOI_TOPCEN": [[113, "hclk-ioi-topcen"]], "HCLK_MGT": [[100, "hclk-mgt"]], "HCLK_TERM_L": [[100, "hclk-term-l"]], "HCLK_TERM_R": [[100, "hclk-term-r"]], "HC_OPT": [[49, "hc-opt"], [62, "hc-opt"]], "Hard PCI logic": [[94, "hard-pci-logic"]], "Hard PowerPC 405 cores": [[95, "hard-powerpc-405-cores"]], "Horizontal clock spine": [[58, "horizontal-clock-spine"]], "I/O banks and special functions": [[108, "i-o-banks-and-special-functions"], [122, "i-o-banks-and-special-functions"], [135, "i-o-banks-and-special-functions"], [143, "i-o-banks-and-special-functions"]], "I/O buffer tiles": [[43, "i-o-buffer-tiles"]], "I/O buffers \u2014 Spartan 3": [[57, "i-o-buffers-spartan-3"]], "I/O buffers \u2014 Spartan 3A": [[57, "i-o-buffers-spartan-3a"]], "I/O buffers \u2014 Spartan 3E": [[57, "i-o-buffers-spartan-3e"]], "I/O buffers \u2014 Virtex": [[79, "i-o-buffers-virtex"]], "I/O buffers \u2014 Virtex 2": [[93, "i-o-buffers-virtex-2"]], "I/O buffers \u2014 Virtex 2 Pro": [[93, "i-o-buffers-virtex-2-pro"]], "I/O buffers \u2014 Virtex E": [[79, "i-o-buffers-virtex-e"]], "I/O data \u2014 Spartan 3": [[50, "i-o-data-spartan-3"]], "I/O data \u2014 Spartan 3A": [[50, "i-o-data-spartan-3a"]], "I/O data \u2014 Spartan 3E": [[50, "i-o-data-spartan-3e"]], "I/O data \u2014 Virtex 2": [[85, "i-o-data-virtex-2"]], "I/O data \u2014 Virtex 2 Pro": [[85, "i-o-data-virtex-2-pro"]], "I/O interface": [[43, "i-o-interface"], [57, "i-o-interface"], [93, "i-o-interface"]], "I/O pins": [[2, "i-o-pins"], [3, "i-o-pins"], [4, "i-o-pins"], [5, "i-o-pins"], [6, "i-o-pins"], [7, "i-o-pins"], [8, "i-o-pins"], [9, "i-o-pins"], [18, "i-o-pins"], [19, "i-o-pins"], [20, "i-o-pins"], [21, "i-o-pins"], [22, "i-o-pins"], [23, "i-o-pins"], [24, "i-o-pins"], [25, "i-o-pins"], [26, "i-o-pins"], [27, "i-o-pins"], [28, "i-o-pins"], [29, "i-o-pins"], [30, "i-o-pins"], [31, "i-o-pins"], [153, "i-o-pins"], [154, "i-o-pins"], [155, "i-o-pins"], [156, "i-o-pins"], [157, "i-o-pins"], [158, "i-o-pins"]], "I/O standard data": [[100, "i-o-standard-data"], [113, "i-o-standard-data"]], "IDCODE": [[35, "idcode"], [162, "idcode"]], "IMUX bits": [[2, "imux-bits"], [3, "imux-bits"], [4, "imux-bits"], [5, "imux-bits"], [6, "imux-bits"], [7, "imux-bits"], [8, "imux-bits"], [9, "imux-bits"], [18, "imux-bits"], [19, "imux-bits"], [20, "imux-bits"], [21, "imux-bits"], [22, "imux-bits"], [23, "imux-bits"], [24, "imux-bits"], [25, "imux-bits"], [26, "imux-bits"], [27, "imux-bits"], [28, "imux-bits"], [29, "imux-bits"], [30, "imux-bits"], [31, "imux-bits"], [153, "imux-bits"], [154, "imux-bits"], [155, "imux-bits"], [156, "imux-bits"], [157, "imux-bits"], [158, "imux-bits"]], "INT.BRAM": [[91, "int-bram"]], "INT.BRAM.S3": [[55, "int-bram-s3"]], "INT.BRAM.S3A.03": [[55, "int-bram-s3a-03"]], "INT.BRAM.S3A.12": [[55, "int-bram-s3a-12"]], "INT.BRAM.S3ADSP": [[55, "int-bram-s3adsp"]], "INT.BRAM.S3E": [[55, "int-bram-s3e"]], "INT.CLB": [[42, "int-clb"], [55, "int-clb"], [91, "int-clb"]], "INT.CNR": [[91, "int-cnr"]], "INT.DCM": [[55, "int-dcm"]], "INT.DCM.S3E.DUMMY": [[55, "int-dcm-s3e-dummy"]], "INT.DCM.V2": [[91, "int-dcm-v2"]], "INT.DCM.V2P": [[91, "int-dcm-v2p"]], "INT.GT.CLKPAD": [[91, "int-gt-clkpad"]], "INT.IOI": [[91, "int-ioi"]], "INT.IOI.CLK_B": [[91, "int-ioi-clk-b"]], "INT.IOI.CLK_T": [[91, "int-ioi-clk-t"]], "INT.IOI.FC": [[42, "int-ioi-fc"]], "INT.IOI.S3": [[55, "int-ioi-s3"]], "INT.IOI.S3A.LR": [[55, "int-ioi-s3a-lr"]], "INT.IOI.S3A.TB": [[55, "int-ioi-s3a-tb"]], "INT.IOI.S3E": [[55, "int-ioi-s3e"]], "INT.PPC": [[91, "int-ppc"]], "INTF": [[68, "intf"]], "INTF.CMT": [[68, "intf-cmt"]], "INTF.CMT.IOI": [[68, "intf-cmt-ioi"]], "INTF.DSP": [[55, "intf-dsp"]], "INTF.GT.B0": [[91, "intf-gt-b0"]], "INTF.GT.B123": [[91, "intf-gt-b123"]], "INTF.GT.BCLKPAD": [[91, "intf-gt-bclkpad"]], "INTF.GT.T0": [[91, "intf-gt-t0"]], "INTF.GT.T123": [[91, "intf-gt-t123"]], "INTF.GT.TCLKPAD": [[91, "intf-gt-tclkpad"]], "INTF.IOI": [[68, "intf-ioi"]], "INTF.PPC": [[91, "intf-ppc"]], "IO and transceiver placement": [[140, "io-and-transceiver-placement"]], "IO banks and IO buffers": [[58, "io-banks-and-io-buffers"], [87, "io-banks-and-io-buffers"]], "IO clock nodes": [[100, "io-clock-nodes"], [113, "io-clock-nodes"]], "IO.B": [[79, "io-b"], [149, "io-b"]], "IO.L": [[79, "io-l"], [149, "io-l"]], "IO.R": [[79, "io-r"], [149, "io-r"]], "IO.T": [[79, "io-t"], [149, "io-t"]], "IOB.B.V": [[79, "iob-b-v"]], "IOB.B.VE": [[79, "iob-b-ve"]], "IOB.L.V": [[79, "iob-l-v"]], "IOB.L.VE": [[79, "iob-l-ve"]], "IOB.R.V": [[79, "iob-r-v"]], "IOB.R.VE": [[79, "iob-r-ve"]], "IOB.T.V": [[79, "iob-t-v"]], "IOB.T.VE": [[79, "iob-t-ve"]], "IOBS.FC.B": [[43, "iobs-fc-b"]], "IOBS.FC.L": [[43, "iobs-fc-l"]], "IOBS.FC.R": [[43, "iobs-fc-r"]], "IOBS.FC.T": [[43, "iobs-fc-t"]], "IOBS.S3.B2": [[57, "iobs-s3-b2"]], "IOBS.S3.L1": [[57, "iobs-s3-l1"]], "IOBS.S3.R1": [[57, "iobs-s3-r1"]], "IOBS.S3.T2": [[57, "iobs-s3-t2"]], "IOBS.S3A.B2": [[57, "iobs-s3a-b2"]], "IOBS.S3A.L4": [[57, "iobs-s3a-l4"]], "IOBS.S3A.R4": [[57, "iobs-s3a-r4"]], "IOBS.S3A.T2": [[57, "iobs-s3a-t2"]], "IOBS.S3E.B1": [[57, "iobs-s3e-b1"]], "IOBS.S3E.B2": [[57, "iobs-s3e-b2"]], "IOBS.S3E.B3": [[57, "iobs-s3e-b3"]], "IOBS.S3E.B4": [[57, "iobs-s3e-b4"]], "IOBS.S3E.L1": [[57, "iobs-s3e-l1"]], "IOBS.S3E.L2": [[57, "iobs-s3e-l2"]], "IOBS.S3E.L3": [[57, "iobs-s3e-l3"]], "IOBS.S3E.L4": [[57, "iobs-s3e-l4"]], "IOBS.S3E.R1": [[57, "iobs-s3e-r1"]], "IOBS.S3E.R2": [[57, "iobs-s3e-r2"]], "IOBS.S3E.R3": [[57, "iobs-s3e-r3"]], "IOBS.S3E.R4": [[57, "iobs-s3e-r4"]], "IOBS.S3E.T1": [[57, "iobs-s3e-t1"]], "IOBS.S3E.T2": [[57, "iobs-s3e-t2"]], "IOBS.S3E.T3": [[57, "iobs-s3e-t3"]], "IOBS.S3E.T4": [[57, "iobs-s3e-t4"]], "IOBS.V2.B.L2": [[93, "iobs-v2-b-l2"]], "IOBS.V2.B.R2": [[93, "iobs-v2-b-r2"]], "IOBS.V2.L.B2": [[93, "iobs-v2-l-b2"]], "IOBS.V2.L.T2": [[93, "iobs-v2-l-t2"]], "IOBS.V2.R.B2": [[93, "iobs-v2-r-b2"]], "IOBS.V2.R.T2": [[93, "iobs-v2-r-t2"]], "IOBS.V2.T.L2": [[93, "iobs-v2-t-l2"]], "IOBS.V2.T.R2": [[93, "iobs-v2-t-r2"]], "IOBS.V2P.B.L1": [[93, "iobs-v2p-b-l1"]], "IOBS.V2P.B.L1.ALT": [[93, "iobs-v2p-b-l1-alt"]], "IOBS.V2P.B.L2": [[93, "iobs-v2p-b-l2"]], "IOBS.V2P.B.R1": [[93, "iobs-v2p-b-r1"]], "IOBS.V2P.B.R1.ALT": [[93, "iobs-v2p-b-r1-alt"]], "IOBS.V2P.B.R2": [[93, "iobs-v2p-b-r2"]], "IOBS.V2P.B.R2.CLK": [[93, "iobs-v2p-b-r2-clk"]], "IOBS.V2P.L.B2": [[93, "iobs-v2p-l-b2"]], "IOBS.V2P.L.T2": [[93, "iobs-v2p-l-t2"]], "IOBS.V2P.R.B2": [[93, "iobs-v2p-r-b2"]], "IOBS.V2P.R.T2": [[93, "iobs-v2p-r-t2"]], "IOBS.V2P.T.L1": [[93, "iobs-v2p-t-l1"]], "IOBS.V2P.T.L1.ALT": [[93, "iobs-v2p-t-l1-alt"]], "IOBS.V2P.T.L2": [[93, "iobs-v2p-t-l2"]], "IOBS.V2P.T.R1": [[93, "iobs-v2p-t-r1"]], "IOBS.V2P.T.R1.ALT": [[93, "iobs-v2p-t-r1-alt"]], "IOBS.V2P.T.R2": [[93, "iobs-v2p-t-r2"]], "IOBS.V2P.T.R2.CLK": [[93, "iobs-v2p-t-r2-clk"]], "IOI": [[93, "ioi"]], "IOI.CLK_B": [[93, "ioi-clk-b"]], "IOI.CLK_T": [[93, "ioi-clk-t"]], "IOI.FC": [[43, "ioi-fc"]], "IOI.S3": [[57, "ioi-s3"]], "IOI.S3A.B": [[57, "ioi-s3a-b"]], "IOI.S3A.LR": [[57, "ioi-s3a-lr"]], "IOI.S3A.T": [[57, "ioi-s3a-t"]], "IOI.S3E": [[57, "ioi-s3e"]], "IR": [[13, "ir"], [35, "ir"], [162, "ir"]], "ISP DR registers \u2014 XC9500": [[35, "isp-dr-registers-xc9500"]], "ISP DR registers \u2014 XC9500XL/XV": [[35, "isp-dr-registers-xc9500xl-xv"]], "ISP instructions": [[13, "isp-instructions"], [162, "isp-instructions"]], "ISP instructions \u2014 XC9500": [[35, "isp-instructions-xc9500"]], "ISP instructions \u2014 XC9500XL/XV": [[35, "isp-instructions-xc9500xl-xv"]], "Input / Output": [[43, "input-output"], [57, "input-output"], [93, "input-output"]], "Input multiplexers": [[55, "input-multiplexers"], [91, "input-multiplexers"]], "Input/Output": [[79, "input-output"], [108, "input-output"], [122, "input-output"], [135, "input-output"], [143, "input-output"], [149, "input-output"]], "Input/output buffer": [[14, "input-output-buffer"], [36, "input-output-buffer"], [163, "input-output-buffer"]], "Interconnect": [[121, "interconnect"], [134, "interconnect"], [142, "interconnect"]], "Introduction": [[12, "introduction"], [34, "introduction"], [56, "introduction"], [92, "introduction"], [161, "introduction"]], "JED bits": [[152, "jed-bits"]], "JED format mapping": [[15, "jed-format-mapping"], [16, "jed-format-mapping"]], "JED mapping": [[2, "jed-mapping"], [3, "jed-mapping"], [4, "jed-mapping"], [4, "id1"], [5, "jed-mapping"], [5, "id1"], [6, "jed-mapping"], [7, "jed-mapping"], [8, "jed-mapping"], [8, "id1"], [9, "jed-mapping"], [9, "id1"], [151, "jed-mapping"], [153, "jed-mapping"], [154, "jed-mapping"], [155, "jed-mapping"], [156, "jed-mapping"], [157, "jed-mapping"], [158, "jed-mapping"]], "JED mapping \u2014 MCs with IOBs": [[2, "jed-mapping-mcs-with-iobs"], [3, "jed-mapping-mcs-with-iobs"], [6, "jed-mapping-mcs-with-iobs"], [7, "jed-mapping-mcs-with-iobs"]], "JED mapping \u2014 MCs without IOBs": [[2, "jed-mapping-mcs-without-iobs"], [3, "jed-mapping-mcs-without-iobs"], [6, "jed-mapping-mcs-without-iobs"], [7, "jed-mapping-mcs-without-iobs"]], "JED mapping \u2014 macrocells with IOB": [[151, "jed-mapping-macrocells-with-iob"]], "JED mapping \u2014 macrocells without IOB": [[151, "jed-mapping-macrocells-without-iob"]], "JED structure": [[151, "jed-structure"]], "JTAG interface": [[13, "jtag-interface"], [35, "jtag-interface"], [162, "jtag-interface"]], "LL.FC": [[40, "ll-fc"]], "LL.S3": [[50, "ll-s3"]], "LL.S3A": [[50, "ll-s3a"]], "LL.S3E": [[50, "ll-s3e"]], "LL.V2": [[85, "ll-v2"]], "LL.V2P": [[85, "ll-v2p"]], "LLH": [[55, "llh"]], "LLH.CLKB.S3A": [[55, "llh-clkb-s3a"]], "LLH.CLKT.S3A": [[55, "llh-clkt-s3a"]], "LLV.S3A": [[55, "llv-s3a"]], "LLV.S3E": [[55, "llv-s3e"]], "LR.FC": [[40, "lr-fc"]], "LR.S3": [[50, "lr-s3"]], "LR.S3A": [[50, "lr-s3a"]], "LR.S3E": [[50, "lr-s3e"]], "LR.V2": [[85, "lr-v2"]], "LR.V2P": [[85, "lr-v2p"]], "LUT RAM": [[46, "lut-ram"], [82, "lut-ram"]], "LUTs": [[46, "luts"], [82, "luts"]], "Local control terms": [[163, "local-control-terms"]], "Long line splitters": [[55, "long-line-splitters"]], "Lower left": [[40, "lower-left"], [50, "lower-left"], [63, "lower-left"], [85, "lower-left"]], "Lower right": [[40, "lower-right"], [50, "lower-right"], [63, "lower-right"], [85, "lower-right"]], "MC bits": [[2, "mc-bits"], [3, "mc-bits"], [4, "mc-bits"], [5, "mc-bits"], [6, "mc-bits"], [7, "mc-bits"], [8, "mc-bits"], [9, "mc-bits"]], "MGT clock repeater": [[100, "mgt-clock-repeater"], [113, "mgt-clock-repeater"]], "MODE": [[49, "mode"], [62, "mode"]], "Macrocell and IOB outputs": [[14, "macrocell-and-iob-outputs"], [163, "macrocell-and-iob-outputs"]], "Macrocell output \u2014 XC9500": [[36, "macrocell-output-xc9500"]], "Macrocell output \u2014 XC9500XL/XV": [[36, "macrocell-output-xc9500xl-xv"]], "Memory Controller Block": [[69, "memory-controller-block"]], "Middle GTP holes": [[140, "middle-gtp-holes"]], "Misc configuration": [[14, "misc-configuration"], [36, "misc-configuration"], [163, "misc-configuration"]], "Multi-gigabit transceivers": [[66, "multi-gigabit-transceivers"], [105, "multi-gigabit-transceivers"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro": [[88, "multi-gigabit-transceivers-virtex-2-pro"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro X": [[89, "multi-gigabit-transceivers-virtex-2-pro-x"]], "Output multiplexers": [[82, "output-multiplexers"]], "Output multiplexers \u2014 Spartan 3": [[46, "output-multiplexers-spartan-3"]], "Output multiplexers \u2014 Virtex 4": [[46, "output-multiplexers-virtex-4"]], "Overview": [[14, "overview"], [36, "overview"], [163, "overview"]], "PCI Express": [[70, "pci-express"]], "PCI Express Gen2 cores": [[144, "pci-express-gen2-cores"]], "PCI Express Gen3 cores": [[145, "pci-express-gen3-cores"]], "PCI Express cores": [[123, "pci-express-cores"], [136, "pci-express-cores"]], "PCI Express holes": [[140, "pci-express-holes"]], "PCI Logic": [[80, "pci-logic"]], "PCI logic": [[87, "pci-logic"]], "PCIE_L": [[144, "pcie-l"]], "PCIE_R": [[144, "pcie-r"]], "PCI_CE_DELAY": [[61, "pci-ce-delay"]], "PMA_SPEED values": [[89, "pma-speed-values"]], "POWERDOWN": [[49, "powerdown"], [62, "powerdown"]], "PPC.E": [[91, "ppc-e"]], "PPC.N": [[91, "ppc-n"]], "PPC.S": [[91, "ppc-s"]], "PPC.W": [[91, "ppc-w"]], "PT import/export": [[36, "pt-import-export"]], "PU_GTS": [[49, "pu-gts"], [62, "pu-gts"]], "PU_GWE": [[49, "pu-gwe"], [62, "pu-gwe"]], "Packages": [[12, "packages"], [34, "packages"], [161, "packages"]], "Part": [[17, "part"], [152, "part"]], "Phase-locked loop": [[71, "phase-locked-loop"]], "PowerPC cores": [[124, "powerpc-cores"]], "PowerPC holes": [[87, "powerpc-holes"], [91, "powerpc-holes"], [104, "powerpc-holes"], [117, "powerpc-holes"]], "Primary vertical clock spine": [[58, "primary-vertical-clock-spine"]], "Primitive outputs": [[55, "primitive-outputs"], [91, "primitive-outputs"]], "Processing system": [[140, "processing-system"]], "Product terms": [[14, "product-terms"], [36, "product-terms"], [163, "product-terms"]], "Programming fuses \u2014 XC9500": [[35, "programming-fuses-xc9500"]], "Programming fuses \u2014 XC9500XL/XV": [[35, "programming-fuses-xc9500xl-xv"]], "Programming sequence": [[13, "programming-sequence"], [35, "programming-sequence"], [162, "programming-sequence"]], "Project Combine": [[0, "project-combine"]], "RANDOR": [[37, "randor"], [46, "randor"]], "RANDOR_INIT": [[37, "randor-init"], [46, "randor-init"]], "RESERVED_ANDOR": [[37, "reserved-andor"], [46, "reserved-andor"]], "Reading fuses \u2014 XC9500": [[35, "reading-fuses-xc9500"]], "Reading fuses \u2014 XC9500XL/XV": [[35, "reading-fuses-xc9500xl-xv"]], "Register": [[14, "register"], [163, "register"]], "Registers": [[46, "registers"], [82, "registers"]], "Row clock terminators": [[100, "row-clock-terminators"]], "SEU_OPT": [[49, "seu-opt"], [62, "seu-opt"]], "Secondary vertical clock spines": [[58, "secondary-vertical-clock-spines"]], "Shift registers": [[46, "shift-registers"], [82, "shift-registers"]], "Single-port 128\u00d71 RAM": [[82, "single-port-1281-ram"]], "Single-port 16\u00d7X RAM": [[46, "single-port-16x-ram"], [82, "single-port-16x-ram"]], "Single-port 32\u00d7X RAM": [[46, "single-port-32x-ram"], [82, "single-port-32x-ram"]], "Single-port 64\u00d71 RAM": [[46, "single-port-641-ram"]], "Single-port 64\u00d7X RAM": [[82, "single-port-64x-ram"]], "Spartan 3": [[54, "spartan-3"]], "Spartan 3A DCMs": [[58, "spartan-3a-dcms"]], "Spartan 3A and 3A DSP BRAM columns": [[58, "spartan-3a-and-3a-dsp-bram-columns"]], "Spartan 3E BRAM columns": [[58, "spartan-3e-bram-columns"]], "Spartan 3E DCMs": [[58, "spartan-3e-dcms"]], "Spartan 6": [[67, "spartan-6"]], "Speed": [[17, "speed"], [152, "speed"]], "Speed data": [[2, "speed-data"], [3, "speed-data"], [4, "speed-data"], [5, "speed-data"], [6, "speed-data"], [7, "speed-data"], [8, "speed-data"], [9, "speed-data"], [18, "speed-data"], [19, "speed-data"], [20, "speed-data"], [21, "speed-data"], [22, "speed-data"], [23, "speed-data"], [24, "speed-data"], [25, "speed-data"], [26, "speed-data"], [27, "speed-data"], [28, "speed-data"], [29, "speed-data"], [30, "speed-data"], [31, "speed-data"], [153, "speed-data"], [154, "speed-data"], [155, "speed-data"], [156, "speed-data"], [157, "speed-data"], [158, "speed-data"]], "Spine clock terminators": [[100, "spine-clock-terminators"]], "Spine column": [[104, "spine-column"], [117, "spine-column"]], "Spine muxes \u2014 CMT": [[113, "spine-muxes-cmt"]], "Spine muxes \u2014 DCM": [[100, "spine-muxes-dcm"]], "Spine muxes \u2014 IOB": [[100, "spine-muxes-iob"], [113, "spine-muxes-iob"]], "Spine muxes \u2014 MGT": [[113, "spine-muxes-mgt"]], "Splitters": [[150, "splitters"]], "Sum of products": [[82, "sum-of-products"]], "Sum term, LUT2": [[163, "sum-term-lut2"]], "Sum term, XOR gate": [[14, "sum-term-xor-gate"], [36, "sum-term-xor-gate"]], "System monitor": [[109, "system-monitor"]], "TERM.E": [[91, "term-e"]], "TERM.N": [[91, "term-n"]], "TERM.S": [[91, "term-s"]], "TERM.W": [[91, "term-w"]], "TESTMODE": [[62, "testmode"], [128, "testmode"]], "TIMER": [[62, "timer"], [114, "timer"], [128, "timer"]], "TRIM": [[128, "trim"]], "Tables": [[71, "tables"]], "Terminators": [[55, "terminators"], [91, "terminators"]], "The BRAM bel": [[81, "the-bram-bel"]], "The CLKC clock center tile": [[38, "the-clkc-clock-center-tile"], [47, "the-clkc-clock-center-tile"]], "The CLKC_50A clock center tile": [[47, "the-clkc-50a-clock-center-tile"]], "The GCLKC clock spine distribution tiles": [[83, "the-gclkc-clock-spine-distribution-tiles"]], "The GCLKH clock row distribution tiles": [[38, "the-gclkh-clock-row-distribution-tiles"], [47, "the-gclkh-clock-row-distribution-tiles"]], "The GCLKVC clock spine distribution tiles": [[38, "the-gclkvc-clock-spine-distribution-tiles"], [47, "the-gclkvc-clock-spine-distribution-tiles"]], "The GCLKVM secondary clock center tiles": [[38, "the-gclkvm-secondary-clock-center-tiles"], [47, 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96, 110, 125, 137], "9992": [45, 59, 81, 96, 110, 125, 137], "9993": [45, 59, 81, 96, 110, 125, 137], "9994": [45, 59, 81, 96, 110, 125, 137], "9995": [45, 59, 81, 96, 110, 125, 137], "9996": [45, 59, 81, 96, 110, 125, 137], "9997": [45, 59, 81, 96, 110, 125, 137], "9998": [45, 59, 81, 96, 110, 125, 137], "9999": [45, 59, 81, 96, 110, 125, 137], "9_32000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9_64000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9ce_mux": 151, "9fb_group": [153, 154, 155, 156, 157, 158], "9foe2_mux": [4, 5, 8, 9], "9fsr_enabl": [2, 3, 6, 7], "9ibuf_mod": [2, 3, 6, 7], "9int": [55, 72, 79], "9lct5_inv": 151, "9reg_d_ireg": 151, "9reg_init": [2, 3, 6, 7], "9reg_mod": [4, 5, 8, 9], "9rowcolumn": [98, 100, 123, 126, 144, 145], "9rowcolumn012345678910111213141516171819": 105, "9rowcolumn012345678910111213141516171819202122": [69, 70], "9rowcolumn012345678910111213141516171819202122232425": 66, "9rowcolumn0123456789101112131415161718192021222324252627": [111, 116, 124, 130, 136], "9rowcolumn01234567891011121314151617181920212223242526272829": [132, 144], "9rowcolumn0123456789101112131415161718192021222324252627282930": [64, 71], "9rowcolumn012345678910111213141516171819202122232425262728293031": [118, 119], "A": [12, 14, 17, 35, 36, 46, 58, 81, 82, 87, 96, 104, 117, 122, 131, 135, 140, 143, 152, 163], "AED": [12, 161], "AND": [2, 6, 7, 16, 33, 34, 35, 36, 37, 82, 163], "As": [35, 131, 163], "BY": [37, 46, 55, 73, 82, 91, 99], "For": [34, 35, 36, 55, 58, 87, 91, 104, 117, 131, 140, 163], "ISE": [35, 163], "IT": 91, "If": [35, 36, 81, 82, 96, 104, 117, 131, 135, 140, 163], "In": [15, 16, 36, 46, 55, 82, 91, 104, 108, 117, 122, 131, 135, 140, 143, 163], "It": [12, 34, 35, 36, 46, 47, 55, 58, 81, 82, 87, 91, 96, 104, 117, 131, 135, 140, 143, 152, 161, 163], "Its": [35, 81], "No": 140, "Not": [15, 16, 36, 55, 91, 163], "OR": [2, 6, 7, 36, 37], "On": [12, 15, 16, 36, 46, 47, 55, 58, 81, 87, 140, 163], "Such": [35, 55, 58, 87], "The": [12, 13, 15, 16, 17, 34, 35, 36, 37, 41, 42, 45, 46, 53, 54, 55, 56, 58, 65, 82, 87, 90, 91, 92, 96, 99, 104, 108, 117, 122, 131, 135, 140, 143, 151, 152, 161, 162, 163], "Their": [46, 82], "There": [17, 35, 46, 55, 56, 81, 82, 91, 92, 104, 117, 131, 135, 140, 143], "These": [36, 91, 135, 140], "To": [35, 36, 96], "_": [17, 34, 36, 152, 163], "_chain_down": 36, "_chain_up": 36, "_enabl": [36, 151, 163], "_gclk": 163, "_init": [46, 82], "_inv": [36, 163], "_lct": 163, "_mc": [12, 161], "_mux": [36, 46, 82], "_none": 163, "_reg": [81, 96], "_srval": [46, 82], "_sum": 36, "a0": 45, "a0reg": [53, 65], "a1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 153, 154, 155, 156, 157, 158], "a10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 154, 155, 156, 157, 158], "a11": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 155, 156, 157, 158], "a12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 155, 156, 157, 158], "a13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 155, 156, 157, 158], "a14": [2, 3, 6, 7, 22, 23, 24, 25, 45, 156, 157, 158], "a15": [3, 6, 7, 22, 23, 24, 25, 45, 156, 157, 158], "a16": [3, 6, 7, 22, 23, 24, 25, 45, 156, 157, 158], "a17": [6, 7, 22, 23, 24, 25, 45, 156, 157, 158], "a18": [6, 7, 22, 23, 24, 25, 156, 157, 158], "a19": [6, 7, 22, 23, 24, 25, 156, 157, 158], "a1reg": [53, 65], "a2": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 153, 154, 155, 156, 157, 158], "a20": [6, 7, 22, 23, 24, 157, 158], "a21": [6, 7, 22, 23, 157, 158], "a22": [6, 7, 22, 23, 157, 158], "a23": [22, 23], "a24": [22, 23], "a25": [22, 23], "a26": [22, 23], "a3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 153, 154, 155, 156, 157, 158], "a4": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 153, 154, 155, 156, 157, 158], "a5": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 153, 154, 155, 156, 157, 158], "a5ffinit": [127, 138], "a5ffinitslice0": [127, 138], "a5ffmux": [127, 138], "a5ffsr": [127, 138], "a5ffsrinit": 60, "a5ffsrinitslice0": 60, "a5ffsrslice1": 127, "a5q0": 60, "a5q0100": [60, 127, 138], "a6": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 153, 154, 155, 156, 157, 158], "a6lut": [60, 112, 127, 138], "a7": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 153, 154, 155, 156, 157, 158], "a8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 154, 155, 156, 157, 158], "a9": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 154, 155, 156, 157, 158], "a_dfeclkdlyadj": 132, "a_dfedlyovrd": 132, "a_dfedlyovrdgtx0": 132, "a_dfedlyovrdgtx1": 132, "a_dfedlyovrdgtx2": 132, "a_dfedlyovrdgtx3": 132, "a_dfetap1": 132, "a_dfetap2": 132, "a_dfetap3": 132, "a_dfetap4": 132, "a_dfetapovrd": 132, "a_dfetapovrdgtx0": 132, "a_dfetapovrdgtx1": 132, "a_dfetapovrdgtx2": 132, "a_dfetapovrdgtx3": 132, "a_fwdclk1001": 105, "a_fwdclk2001": 105, "a_fwdclk3001": 105, "a_fwdclk4001": 105, "a_gtpreset_0": 66, "a_gtpreset_0gtp": 66, "a_gtpreset_1": 66, "a_gtpreset_1gtp": 66, "a_gtxrxreset": 132, "a_gtxrxresetgtx0": 132, "a_gtxrxresetgtx1": 132, "a_gtxrxresetgtx2": 132, "a_gtxrxresetgtx3": 132, "a_gtxtxreset": 132, "a_gtxtxresetgtx0": 132, "a_gtxtxresetgtx1": 132, "a_gtxtxresetgtx2": 132, "a_gtxtxresetgtx3": 132, "a_input": [115, 129, 139], "a_loopback": 132, "a_loopback_0": 66, "a_loopback_1": 66, "a_pllclkrxreset": 132, "a_pllclkrxresetgtx0": 132, "a_pllclkrxresetgtx1": 132, "a_pllclkrxresetgtx2": 132, "a_pllclkrxresetgtx3": 132, "a_pllclktxreset": 132, "a_pllclktxresetgtx0": 132, "a_pllclktxresetgtx1": 132, "a_pllclktxresetgtx2": 132, "a_pllclktxresetgtx3": 132, "a_plllkdeten_0": 66, "a_plllkdeten_0gtp": 66, "a_plllkdeten_1": 66, "a_plllkdeten_1gtp": 66, "a_pllpowerdown_0": 66, "a_pllpowerdown_0gtp": 66, "a_pllpowerdown_1": 66, "a_pllpowerdown_1gtp": 66, "a_pllrxreset": 132, "a_pllrxresetgtx0": 132, "a_pllrxresetgtx1": 132, "a_pllrxresetgtx2": 132, "a_pllrxresetgtx3": 132, "a_plltxreset": 132, "a_plltxresetgtx0": 132, "a_plltxresetgtx1": 132, "a_plltxresetgtx2": 132, "a_plltxresetgtx3": 132, "a_prbscntreset": 132, "a_prbscntreset_0": 66, "a_prbscntreset_0gtp": 66, "a_prbscntreset_1": 66, "a_prbscntreset_1gtp": 66, "a_prbscntresetgtx0": 132, "a_prbscntresetgtx1": 132, "a_prbscntresetgtx2": 132, "a_prbscntresetgtx3": 132, "a_q": 81, "a_rxbufreset": 132, "a_rxbufreset_0": 66, "a_rxbufreset_0gtp": 66, "a_rxbufreset_1": 66, "a_rxbufreset_1gtp": 66, "a_rxbufresetgtx0": 132, "a_rxbufresetgtx1": 132, "a_rxbufresetgtx2": 132, "a_rxbufresetgtx3": 132, "a_rxcdrfreqreset": 132, "a_rxcdrfreqreset_0": 66, "a_rxcdrfreqreset_0gtp": 66, "a_rxcdrfreqreset_1": 66, "a_rxcdrfreqreset_1gtp": 66, "a_rxcdrfreqresetgtx0": 132, "a_rxcdrfreqresetgtx1": 132, "a_rxcdrfreqresetgtx2": 132, "a_rxcdrfreqresetgtx3": 132, "a_rxcdrhold": 132, "a_rxcdrhold_0": 66, "a_rxcdrhold_0gtp": 66, "a_rxcdrhold_1": 66, "a_rxcdrhold_1gtp": 66, "a_rxcdrholdgtx0": 132, "a_rxcdrholdgtx1": 132, "a_rxcdrholdgtx2": 132, "a_rxcdrholdgtx3": 132, "a_rxcdrphasereset": 132, "a_rxcdrphasereset_0": 66, "a_rxcdrphasereset_0gtp": 66, "a_rxcdrphasereset_1": 66, "a_rxcdrphasereset_1gtp": 66, "a_rxcdrphaseresetgtx0": 132, "a_rxcdrphaseresetgtx1": 132, "a_rxcdrphaseresetgtx2": 132, "a_rxcdrphaseresetgtx3": 132, "a_rxcdrreset": 132, "a_rxcdrreset_0": 66, "a_rxcdrreset_0gtp": 66, "a_rxcdrreset_1": 66, "a_rxcdrreset_1gtp": 66, "a_rxcdrresetgtx0": 132, "a_rxcdrresetgtx1": 132, "a_rxcdrresetgtx2": 132, "a_rxcdrresetgtx3": 132, "a_rxdfereset": 132, "a_rxdferesetgtx0": 132, "a_rxdferesetgtx1": 132, "a_rxdferesetgtx2": 132, "a_rxdferesetgtx3": 132, "a_rxenpmaphasealign": 132, "a_rxenpmaphasealign_0": 66, "a_rxenpmaphasealign_0gtp": 66, "a_rxenpmaphasealign_1": 66, "a_rxenpmaphasealign_1gtp": 66, "a_rxenpmaphasealigngtx0": 132, "a_rxenpmaphasealigngtx1": 132, "a_rxenpmaphasealigngtx2": 132, "a_rxenpmaphasealigngtx3": 132, "a_rxenprbstst": 132, "a_rxenprbstst_0": 66, "a_rxenprbstst_1": 66, "a_rxensamplealign": 132, "a_rxensamplealigngtx0": 132, "a_rxensamplealigngtx1": 132, "a_rxensamplealigngtx2": 132, "a_rxensamplealigngtx3": 132, "a_rxeqmix": 132, "a_rxeqmix_0": 66, "a_rxeqmix_1": 66, "a_rxplllkdeten": 132, "a_rxplllkdetengtx0": 132, "a_rxplllkdetengtx1": 132, "a_rxplllkdetengtx2": 132, "a_rxplllkdetengtx3": 132, "a_rxpllpowerdown": 132, "a_rxpllpowerdowngtx0": 132, "a_rxpllpowerdowngtx1": 132, "a_rxpllpowerdowngtx2": 132, "a_rxpllpowerdowngtx3": 132, "a_rxpmasetphas": 132, "a_rxpmasetphase_0": 66, "a_rxpmasetphase_0gtp": 66, "a_rxpmasetphase_1": 66, "a_rxpmasetphase_1gtp": 66, "a_rxpmasetphasegtx0": 132, "a_rxpmasetphasegtx1": 132, "a_rxpmasetphasegtx2": 132, "a_rxpmasetphasegtx3": 132, "a_rxpolar": 132, "a_rxpolarity_0": 66, "a_rxpolarity_0gtp": 66, "a_rxpolarity_1": 66, "a_rxpolarity_1gtp": 66, "a_rxpolaritygtx0": 132, "a_rxpolaritygtx1": 132, "a_rxpolaritygtx2": 132, "a_rxpolaritygtx3": 132, "a_rxpowerdown": 132, "a_rxpowerdown_0": 66, "a_rxpowerdown_1": 66, "a_rxreset": 132, "a_rxreset_0": 66, "a_rxreset_0gtp": 66, "a_rxreset_1": 66, "a_rxreset_1gtp": 66, "a_rxresetgtx0": 132, "a_rxresetgtx1": 132, "a_rxresetgtx2": 132, "a_rxresetgtx3": 132, "a_txbufdiffctrl": 132, "a_txbufdiffctrl_0": 66, "a_txbufdiffctrl_1": 66, "a_txdeemph": 132, "a_txdeemphgtx0": 132, "a_txdeemphgtx1": 132, "a_txdeemphgtx2": 132, "a_txdeemphgtx3": 132, "a_txdiffctrl": 132, "a_txdiffctrl_0": 66, "a_txdiffctrl_1": 66, "a_txelecidl": 132, "a_txelecidle_0": 66, "a_txelecidle_0gtp": 66, "a_txelecidle_1": 66, "a_txelecidle_1gtp": 66, "a_txelecidlegtx0": 132, "a_txelecidlegtx1": 132, "a_txelecidlegtx2": 132, "a_txelecidlegtx3": 132, "a_txenpmaphasealign": 132, "a_txenpmaphasealign_0": 66, "a_txenpmaphasealign_0gtp": 66, "a_txenpmaphasealign_1": 66, "a_txenpmaphasealign_1gtp": 66, "a_txenpmaphasealigngtx0": 132, "a_txenpmaphasealigngtx1": 132, "a_txenpmaphasealigngtx2": 132, "a_txenpmaphasealigngtx3": 132, "a_txenprbstst": 132, "a_txenprbstst_0": 66, "a_txenprbstst_1": 66, "a_txmargin": 132, "a_txplllkdeten": 132, "a_txplllkdetengtx0": 132, "a_txplllkdetengtx1": 132, "a_txplllkdetengtx2": 132, "a_txplllkdetengtx3": 132, "a_txpllpowerdown": 132, "a_txpllpowerdowngtx0": 132, "a_txpllpowerdowngtx1": 132, "a_txpllpowerdowngtx2": 132, "a_txpllpowerdowngtx3": 132, "a_txpmasetphas": 132, "a_txpmasetphase_0": 66, "a_txpmasetphase_0gtp": 66, "a_txpmasetphase_1": 66, "a_txpmasetphase_1gtp": 66, "a_txpmasetphasegtx0": 132, "a_txpmasetphasegtx1": 132, "a_txpmasetphasegtx2": 132, "a_txpmasetphasegtx3": 132, "a_txpolar": 132, "a_txpolarity_0": 66, "a_txpolarity_0gtp": 66, "a_txpolarity_1": 66, "a_txpolarity_1gtp": 66, "a_txpolaritygtx0": 132, "a_txpolaritygtx1": 132, "a_txpolaritygtx2": 132, "a_txpolaritygtx3": 132, "a_txpostemphasi": 132, "a_txpowerdown": 132, "a_txpowerdown_0": 66, "a_txpowerdown_1": 66, "a_txprbsforceerr": 132, "a_txprbsforceerr_0": 66, "a_txprbsforceerr_0gtp": 66, "a_txprbsforceerr_1": 66, "a_txprbsforceerr_1gtp": 66, "a_txprbsforceerrgtx0": 132, "a_txprbsforceerrgtx1": 132, "a_txprbsforceerrgtx2": 132, "a_txprbsforceerrgtx3": 132, "a_txpreemphasi": 132, "a_txpreemphasis_0": 66, "a_txpreemphasis_1": 66, "a_txreset": 132, "a_txreset_0": 66, "a_txreset_0gtp": 66, "a_txreset_1": 66, "a_txreset_1gtp": 66, "a_txresetgtx0": 132, "a_txresetgtx1": 132, "a_txresetgtx2": 132, "a_txresetgtx3": 132, "a_txsw": 132, "a_txswinggtx0": 132, "a_txswinggtx1": 132, "a_txswinggtx2": 132, "a_txswinggtx3": 132, "aa1": [6, 7, 22, 23, 157, 158], "aa10": [6, 7, 157, 158], "aa11": [6, 7, 157, 158], "aa12": [6, 7, 157, 158], "aa13": [6, 7, 157, 158], "aa14": [6, 7, 157, 158], "aa15": [6, 7, 157, 158], "aa16": [6, 7, 157, 158], "aa17": [6, 7, 157, 158], "aa18": [6, 7, 157, 158], "aa19": [6, 7, 157, 158], "aa2": [6, 7, 22, 23, 157, 158], "aa20": [6, 7, 157, 158], "aa21": [6, 7, 157, 158], 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"clkindc_bgtp_dual": 118, "clkindc_bgtx_dual": 119, "clkineast011": 66, "clkinsel": 71, "clkinsel_mod": 71, "clkinsel_modepl": 71, "clkinsel_stat": 71, "clkinsel_staticpl": 71, "clkint": [73, 79], "clkinwest111": 66, "clkiob1": 79, "clkiob111111110": 147, "clkiob2": 79, "clkiob3": 79, "clkl": [58, 78, 148], "clkout0000": 71, "clkout1001": 71, "clkout2010": 71, "clkout3011": 71, "clkout4100": 71, "clkout5101": 71, "clkout_east": 66, "clkout_eastgtp": 66, "clkout_north": [118, 119], "clkout_north_s0": [118, 119], "clkout_north_s101": [118, 119], "clkout_phase_shift": 64, "clkout_south": [118, 119], "clkout_south_n0": [118, 119], "clkout_south_n001": [118, 119], "clkout_west": 66, "clkout_westgtp": 66, "clkpad": [55, 87], "clkpad00000000000": 74, "clkpad000000000000": 74, "clkpad000000000001": 74, "clkpad000000000001000": 77, "clkpad00000000001": 74, "clkpad0000000001000": 77, "clkpad0000011": 74, "clkpad0000100000100": 91, "clkpad0001000000010000": 55, "clkpad00100010": 74, "clkpad01100100": 74, "clkpad10000000000": 74, "clkpad100000000000": 74, "clkpad100000000001": 74, "clkpad10000000001": 74, "clkpad100000000010000": 77, "clkpad1000000010000": 77, "clkpad10000100": 74, "clkpad1000100001000": 91, "clkpad1001000000100000": 55, "clkpad1100101": 74, "clkpad2001000000100": 91, "clkpad2001000001000000": 55, "clkpad3001000001000": 91, "clkpad3001000010000000": 55, "clkpad4010000000100": 91, "clkpad5010000001000": 91, "clkpad6100000000100": 91, "clkpad7100000001000": 91, "clkpin000": 61, "clkpin0000": 61, "clkpin01": 61, "clkpin1001": 61, "clkpin4100": 61, "clkpin5101": 61, "clkpn011": [118, 119], "clkpn1": [118, 119], "clkr": [58, 78, 148], "clkrcv_trst": [119, 132], "clkrcv_trst_0": 66, "clkrcv_trst_0gtp": 66, "clkrcv_trst_1": 66, "clkrcv_trst_1gtp": 66, "clkrcv_trstgtx1": 132, "clkrcv_trstgtx_dual": 119, "clkslice0": 112, "clkslice1": [60, 127], "clkt": [58, 78, 87, 148], "clkt_2dll": 78, "clkt_4dll": 78, "clktestsig0111": 132, "clktestsig11": 132, "clktestsig1111": 132, "clkv": [78, 148], "clkv_bram": 72, "clkv_bram_bot": 78, "clkv_bram_top": 78, "clock": [11, 12, 34, 35, 36, 41, 44, 46, 54, 55, 56, 67, 78, 81, 82, 90, 92, 96, 104, 106, 108, 117, 120, 122, 131, 135, 140, 143, 152, 161, 163], "clock_delai": 124, "clock_invert_m": 115, "clock_invert_p": 115, "clock_invert_pdsp1": 115, "clockwis": [58, 87], "close": [58, 81, 131, 140], "closest": 58, "clr0": 146, "clrmux": 146, "clrmuxlc0": 146, "clrmuxlc1": 146, "clrmuxlc2": 146, "clrmuxlc3": 146, "cm_trim": 132, "cm_trim_0": [66, 119], "cm_trim_1": [66, 119], "cmd_intx_impl": [136, 144], "cmd_intx_implementedpci": [136, 144], "cmo": 14, "cmos0": 147, "cmos00": [74, 79], "cmos01": 74, "cmos111": [57, 93, 108, 122], "cmos_hv111": 57, "cmos_lv001": 57, "cmos_vccaux111": 57, "cmos_vccint011": 57, "cmos_vcco100": 57, "cmt": [64, 71, 117, 120, 122, 131, 140], "cmt0": 61, "cmt10": 61, "cmt_bufg_": 131, "cmt_bufg_bot": 131, "cmt_bufg_top": 131, "cmt_clk000001000010000": 113, "cmt_clk000010000000010": 113, "cmt_clk100000000000110": 113, "cmt_clk100000000011000": 113, "cmt_clk1000010100000000": 113, "cmt_clk1000101000000000": 113, "cmt_clk1100001000001000": 113, "cmt_clk1100010000000100": 113, "cmt_clk1200010010000000": 113, "cmt_clk1201001000000000": 113, "cmt_clk1300001000010000": 113, "cmt_clk1300010000000010": 113, "cmt_clk1400010001000000": 113, "cmt_clk1410001000000000": 113, "cmt_clk1500001000100000": 113, "cmt_clk1500010000000001": 113, "cmt_clk1600010100000000": 113, "cmt_clk1600101000000000": 113, "cmt_clk1700000100000100": 113, "cmt_clk1700100000001000": 113, "cmt_clk1800100100000000": 113, "cmt_clk1900000100001000": 113, "cmt_clk1900100000000100": 113, "cmt_clk200000100010000": 113, "cmt_clk2000100010000000": 113, "cmt_clk200100000000010": 113, "cmt_clk2001000100000000": 113, "cmt_clk2100000100010000": 113, "cmt_clk2100100000000010": 113, "cmt_clk2200100001000000": 113, "cmt_clk2210000100000000": 113, "cmt_clk2300000100100000": 113, "cmt_clk2300100000000001": 113, "cmt_clk2400010010000000": 113, "cmt_clk2401001000000000": 113, "cmt_clk2500000010000100": 113, "cmt_clk2501000000001000": 113, "cmt_clk2600100010000000": 113, "cmt_clk2601000100000000": 113, "cmt_clk2700000010001000": 113, "cmt_clk2701000000000100": 113, "cmt_clk300000000001010": 113, "cmt_clk300000000010100": 113, "cmt_clk400000010010000": 113, "cmt_clk401000000000010": 113, "cmt_clk500000000010010": 113, "cmt_clk600000001010000": 113, "cmt_clk610000000000010": 113, "cmt_clk700000000010001": 113, "cmt_clk700000000100010": 113, "cmt_clk800011000000000": 113, "cmt_clk900001000000100": 113, "cmt_clk900010000001000": 113, "cmt_d00100": 61, "cmt_d100100": 61, "cmt_d10100": 61, "cmt_d110100": 61, "cmt_d120100": 61, "cmt_d130100": 61, "cmt_d140100": 61, "cmt_d150100": 61, "cmt_d20100": 61, "cmt_d30100": 61, "cmt_d40100": 61, "cmt_d50100": 61, "cmt_d60100": 61, "cmt_d70100": 61, "cmt_d80100": 61, "cmt_d90100": 61, "cmt_dcm": 64, "cmt_enabl": 61, "cmt_pll": 71, "cmt_u01000": 61, "cmt_u101000": 61, "cmt_u11000": 61, "cmt_u111000": 61, "cmt_u121000": 61, "cmt_u131000": 61, "cmt_u141000": 61, "cmt_u151000": 61, "cmt_u21000": 61, "cmt_u31000": 61, "cmt_u41000": 61, "cmt_u51000": 61, "cmt_u61000": 61, "cmt_u71000": 61, "cmt_u81000": 61, "cmt_u91000": 61, "cmux": 147, "cmuxosc": 147, "cnr": [58, 78, 87, 148], "co01": 146, "co1": 146, "code": 35, "coin_window": [51, 86], "col": [2, 3, 4, 5, 6, 7, 8, 9, 153, 154, 155, 156, 157, 158], "col_hi": [15, 16], "col_lo": [15, 16], "coloc": [58, 81, 104, 117, 131, 140], "column": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 35, 46, 47, 55, 78, 81, 82, 83, 87, 91, 108, 122, 135, 143, 151, 152, 153, 154, 155, 156, 157, 158, 160, 162], "columnar": 104, "com": [51, 86], "com_burst_v": 132, "com_burst_val_0": [66, 118, 119], "com_burst_val_1": [66, 118, 119], "comb": 36, "comb0": 15, "comb1": 16, "combin": [36, 46, 55, 81, 82, 91, 104, 163], "combination": 81, "combinatori": [14, 36, 163], "come": [12, 34, 36, 46, 58, 81, 87, 104, 108, 117, 122, 131, 140, 161, 163], "comma32": 105, "comma32gt11a": 105, "comma32gt11b": 105, "comma_10b_en": 132, "comma_10b_enable_0": [66, 118, 119], "comma_10b_enable_1": [66, 118, 119], "comma_10b_mask": [88, 89, 105], "comma_doubl": 132, "comma_double_0": [118, 119], "comma_double_0gtp_du": 118, "comma_double_0gtx_du": 119, "comma_double_1": [118, 119], "comma_double_1gtp_du": 118, "comma_double_1gtx_du": 119, "comma_doublegtx0": 132, "comma_doublegtx1": 132, "comma_doublegtx2": 132, "comma_doublegtx3": 132, "commerci": [17, 152], "common": [100, 143], "common_hclk_giob": 100, "common_mgt": 100, "common_mgtioclk": 100, "commonli": [140, 151], "companion": [44, 106], "compat": [12, 34, 161], "compens": 82, "complement": [108, 122, 135, 143], "complet": [12, 13, 16, 34, 35, 36, 104, 140, 151, 161], "complex": [15, 16, 140], "comput": [81, 151], "concaten": [15, 16, 81, 96], "conceptu": 58, "concur": [51, 52, 64, 86], "concur00100101": 102, "concur1001": 64, "concur_en": 102, "concur_enabledcm": 102, "concurdcm": [51, 52, 86], "concurdcm0": 64, "concurdcm1": 64, "config": [15, 16, 151], "config10": 102, "config_fallback": [114, 128], "config_r": [39, 48, 49, 75, 84, 101, 114, 128, 147], "configrout": 123, "configur": [11, 12, 15, 33, 34, 35, 41, 44, 47, 54, 55, 56, 67, 78, 87, 90, 91, 92, 104, 106, 108, 117, 120, 122, 131, 133, 135, 141, 143, 148, 151, 160], "configuraton": [15, 16], "conjunct": 36, "connect": [35, 36, 46, 58, 81, 82, 91, 92, 96, 108, 122, 135, 140, 162, 163], "consecut": 131, "consid": [35, 104, 108, 117, 122, 131, 135, 140, 143], "consist": [35, 36, 81, 104, 117, 122, 131, 135, 140], "const": [13, 14, 35, 36, 46, 82, 162, 163], "constant": [36, 46, 82, 108], "constraint": 12, "construct": 163, "consult": 15, "contain": [15, 17, 34, 42, 45, 46, 55, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 117, 122, 131, 135, 140, 143, 162, 163], "content": [35, 46, 82, 131], "contigu": [15, 16], "continu": [35, 143], "control": [12, 14, 35, 36, 44, 46, 56, 67, 82, 92, 96, 108], "convert": [15, 16], "convst": 109, "convstclk": [111, 126], "convstsysmon": 109, "coolrunn": [0, 12, 14], "coordin": [16, 17, 36, 58, 87, 151, 152, 163], "cor": [41, 54, 78, 90, 106, 120, 133], "cor1": [54, 67, 120, 133], "cor2": [54, 67], "core": [12, 34, 36, 44, 55, 87, 90, 91, 92, 104, 117, 120, 133, 141, 161, 163], "corner": [41, 44, 54, 55, 56, 58, 67, 78, 87, 90, 91, 92, 140, 148], "correct": 96, "correspond": [12, 14, 15, 16, 17, 34, 35, 36, 46, 47, 53, 55, 58, 65, 81, 82, 83, 87, 91, 96, 104, 108, 117, 122, 131, 135, 140, 143, 152, 163], "could": 35, "count": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 46, 58, 81, 87, 104, 117, 131, 140, 153, 154, 155, 156, 157, 158], "cout": [46, 82, 149], "coutmux": [60, 112, 127, 138], "coutmuxslice1": 60, "cover": [104, 117, 131, 140, 143, 163], "cp132": [2, 3, 12], "cp56": [4, 5, 8, 9, 12, 154, 161], "cpl_timeout_disable_support": [136, 144], "cpl_timeout_ranges_support": [136, 144], "cpld": [0, 12, 34, 36, 161, 163], "cpmc440clk": 124, "cpmc440timerclock": 124, "cpmdcrclk": 124, "cpmdma0llclk": 124, "cpmdma1llclk": 124, "cpmdma2llclk": 124, "cpmdma3llclk": 124, "cpmfcmclk": 124, "cpminterconnectclk": 124, "cpmmcclk": 124, "cpmppcmplbclk": 124, "cpmppcs0plbclk": 124, "cpmppcs1plbclk": 124, "crammod": [60, 112, 127, 138], "crc": [39, 48, 49, 62, 84, 101, 114, 147], "crc32_0": [118, 119], "crc32_1": [118, 119], "crc32_2": [118, 119], "crc32_3": [118, 119], "crc_end_of_pkt": [88, 89], "crc_format": [88, 89], "crc_init": [118, 119], "crc_start_of_pkt": [88, 89], "crcclk": [118, 119], "crcclkgtp_dual": 118, "crcclkgtx_dual": 119, "creat": [55, 87, 91, 104, 117], "create_edg": [98, 111], "create_edgebufgctrl0": 98, "create_edgebufgctrl1": 98, "create_edgebufgctrl10": 98, "create_edgebufgctrl11": 98, "create_edgebufgctrl12": 98, "create_edgebufgctrl13": 98, "create_edgebufgctrl14": 98, "create_edgebufgctrl15": 98, "create_edgebufgctrl16": 98, "create_edgebufgctrl17": 98, "create_edgebufgctrl18": 98, "create_edgebufgctrl19": 98, "create_edgebufgctrl2": 98, "create_edgebufgctrl20": 98, "create_edgebufgctrl21": 98, "create_edgebufgctrl22": 98, "create_edgebufgctrl23": 98, "create_edgebufgctrl24": 98, "create_edgebufgctrl25": 98, "create_edgebufgctrl26": 98, "create_edgebufgctrl27": 98, "create_edgebufgctrl28": 98, "create_edgebufgctrl29": 98, "create_edgebufgctrl3": 98, "create_edgebufgctrl30": 98, "create_edgebufgctrl31": 98, "create_edgebufgctrl4": 98, "create_edgebufgctrl5": 98, "create_edgebufgctrl6": 98, "create_edgebufgctrl7": 98, "create_edgebufgctrl8": 98, "create_edgebufgctrl9": 98, "creg": [53, 65, 103, 115, 129, 139], "cregdsp": [53, 65], "cregdsp0": [115, 129], "cregdsp1": 129, "crm_core_clk_freq_500": 145, "crm_core_clk_freq_500pcie3": 145, "crm_module_rst": [136, 144], "crm_user_clk_freq": 145, "crmcoreclk": 123, "crmcoreclkdlo": 123, "crmcoreclkpci": 123, "crmcoreclkrxo": 123, "crmcoreclkrxopci": 123, "crmcoreclktxo": 123, "crmcoreclktxopci": 123, "crmuserclk": 123, "crmuserclkrxo": 123, "crmuserclktxo": 123, "cross": [58, 91, 131, 140], "cs144": [20, 21, 34, 155, 161], "cs280": [24, 25, 34, 156, 161], "cs48": [26, 27, 28, 30, 31, 34, 153, 154, 161], "cs_b": [108, 122], "csi_b": [135, 143], "cso2pin": [50, 63], "cso_b": [122, 135, 143], "cspin": [98, 111, 126], "ct": 14, "ct4111": [2, 3, 4, 5, 6, 7, 8, 9], "ct501": [2, 3, 4, 5, 6, 7, 8, 9], "ct601": [2, 3, 4, 5, 6, 7, 8, 9], "ct70001": [2, 3, 4, 5, 6, 7, 8, 9], "ctc": 14, "cte": 14, "ctl": [41, 54, 67, 78, 90, 106, 120, 133], "ctl1": 133, "ctlgo": [51, 52, 64, 86, 102], "ctlgo001": 55, "ctlgodcm": 86, "ctlmode": [51, 52, 64, 86], "ctlmode011": 55, "ctlmodedcm": 86, "ctlosc1": [51, 52, 64, 86, 102], "ctlosc1001": 55, "ctlosc1dcm": [86, 102], "ctlosc2": [51, 52, 64, 86, 102], "ctlosc2001": 55, "ctlosc2dcm": [86, 102], "ctlsel0": [51, 52, 64, 86, 102], "ctlsel0011": 55, "ctlsel0dcm": 86, "ctlsel1": [51, 52, 64, 86, 102], "ctlsel1101": 55, "ctlsel1dcm": [86, 102], "ctlsel2": [51, 52, 64, 86, 102], "ctlsel2100": 55, "ctlsel2dcm": [86, 102], "ctr": 14, "ctrl0": [121, 134, 142], "ctrl00001": [134, 142], "ctrl1": [121, 134, 142], "ctrl10010": [134, 142], "ctrl2": 121, "ctrl3": 121, "ctt": 79, "ctt001100010": 79, "ctt01011": 79, "ctt0111": 79, "curious": [12, 34], "current": [35, 46, 82], "cut": [56, 58, 117, 140], "cv100": [2, 12], "cv64": [5, 9, 12], "cx0": [60, 112, 127, 138], "cx0100": [112, 127, 138], "cx1": [60, 112], "cx10": [127, 138], "cx1010": 60, "cxt": 131, "cy0": 73, "cy0111": 60, "cy0f": [37, 46, 82, 99], "cy0g": [37, 46, 82, 99], "cy1010": [60, 112, 127, 138], "cy110": 112, "cycl": [35, 81, 96], "cycle_limit_sel": 105, "cyinit": [37, 46, 60, 73, 82, 99, 112, 127, 138], "cyinitslice0": [73, 99, 112, 127, 138], "cyinitslice1": [37, 46, 60, 73, 112, 127, 138], "cyinitslice2": 99, "cyinitslice3": [37, 46], "cyself": [37, 46, 73, 82], "cyselfslice0": 73, "cyselfslice1": [37, 46, 73], "cyselfslice3": [37, 46], "cyselg": [37, 46, 73, 82], "cyselgslice0": [73, 82], "cyselgslice1": [37, 46, 73, 82], "cyselgslice3": [37, 46], "d": [14, 36, 81, 96, 108, 122, 135, 143, 163], "d0": [129, 139], "d01": 108, "d1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 129, 139, 153, 154, 155, 156, 157, 158, 163], "d10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 129, 139, 154, 155, 156, 157, 158], "d1001": 108, "d11": [3, 6, 7, 20, 21, 22, 23, 24, 25, 129, 139, 155, 156, 157, 158], "d12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 129, 139, 155, 156, 157, 158], "d13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 129, 139, 155, 156, 157, 158], "d14": [2, 3, 6, 7, 22, 23, 24, 25, 129, 139, 156, 157, 158], "d15": [3, 6, 7, 22, 23, 24, 25, 129, 139, 156, 157, 158], "d16": [3, 6, 7, 22, 23, 24, 25, 129, 139, 156, 157, 158], "d17": [6, 7, 22, 23, 24, 25, 129, 139, 156, 157, 158], "d18": [6, 7, 22, 23, 24, 25, 129, 139, 156, 157, 158], "d19": [6, 7, 22, 23, 24, 25, 129, 139, 156, 157, 158], "d2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 129, 139, 153, 154, 155, 156, 157, 158], "d20": [6, 7, 22, 23, 24, 129, 139, 157, 158], "d21": [6, 7, 22, 23, 129, 139, 157, 158], "d22": [6, 7, 22, 23, 129, 139, 157, 158], "d23": [22, 23, 129, 139], "d24": [22, 23, 129, 139], "d25": [22, 23], "d26": [22, 23], "d2ologic0": 108, "d2ologic1": 108, "d3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 129, 139, 153, 154, 155, 156, 157, 158], "d3iob0": 108, "d3iob1": 108, "d4": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 129, 139, 153, 154, 155, 156, 157, 158], "d4iob0": 108, "d4iob1": 108, "d5": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 108, 129, 139, 155, 156, 157, 158], "d5ffinit": [127, 138], "d5ffinitslice0": [127, 138], "d5ffmux": [127, 138], "d5ffsr": [127, 138], "d5ffsrinit": 60, "d5ffsrinitslice0": 60, "d5ffsrslice1": 127, "d5ologic0": 108, "d5ologic1": 108, "d5q0": 60, "d5q0100": [60, 127, 138], "d6": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 129, 139, 153, 154, 155, 156, 157, 158], "d6lut": [60, 112, 127, 138], "d7": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 129, 139, 153, 154, 155, 156, 157, 158], "d8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 129, 139, 154, 155, 156, 157, 158], "d9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 129, 139, 155, 156, 157, 158], "d_in": [108, 122], "d_out_busi": 122, "daddr0": 102, "daddr1": 102, "daddr1dcm": 102, "daddr2": 102, "daddr2dcm": 102, "daddr3": 102, "daddr4": 102, "daddr4dcm": 102, "daddr5": 102, "daddr5dcm": 102, "daddr6": 102, "daddr6dcm": 102, "data": [10, 12, 14, 17, 32, 35, 37, 42, 45, 46, 53, 54, 55, 58, 59, 65, 72, 81, 82, 87, 90, 91, 96, 99, 104, 106, 108, 117, 120, 122, 131, 140, 147, 151, 152, 159, 163], "data0": [42, 55, 91], "data00001000001": 91, "data00001000100": 91, "data00mux": 55, "data1": [42, 55, 91], "data10": [42, 55], "data10001000010": 91, "data10001001000": 91, "data101mux": 55, "data10mux": 55, "data11": [42, 55], "data110mux": 55, "data11mux": 55, "data12": [42, 55], "data13": [42, 55], "data130mux": 55, "data131mux": 55, "data14": [42, 55], "data140mux": 55, "data15": [42, 55], "data16": [42, 55], "data160mux": 55, "data17": [42, 55], "data170mux": 55, "data171mux": 55, "data18": [42, 55], "data180mux": 55, "data181mux": 55, "data19": [42, 55], "data190mux": 55, "data2": [42, 55, 91], "data20": [42, 55], "data20001000100": 91, "data20001010000": 91, "data20mux": 55, "data21": [42, 55], "data210mux": 55, "data21mux": 55, "data22": [42, 55], "data220mux": 55, "data221mux": 55, "data23": [42, 55], "data24": [42, 55], "data240mux": 55, "data25": [42, 55], "data250mux": 55, "data251mux": 55, "data26": [42, 55], "data261mux": 55, "data27": [42, 55], "data270mux": 55, "data28": [42, 55], "data29": [42, 55], "data290mux": 55, "data3": [42, 55, 91], "data30": [42, 55], "data30001001000": 91, "data30001100000": 91, "data300mux": 55, "data301mux": 55, "data30mux": 55, "data31": [42, 55], "data4": [42, 55, 91], "data40001000001": 91, "data40001000010": 91, "data40001000100": 91, "data5": [42, 55, 91], "data50001000010": 91, "data50001000100": 91, "data50001001000": 91, "data50mux": 55, "data51mux": 55, "data6": [42, 55, 91], "data60001000100": 91, "data60001001000": 91, "data60001010000": 91, "data60mux": 55, "data7": [42, 55, 91], "data70001001000": 91, "data70001010000": 91, "data70001100000": 91, "data8": [42, 55], "data80mux": 55, "data9": [42, 55], "data90mux": 55, "data91mux": 55, "data_l": [110, 125, 137], "data_r": [61, 108], "data_u": [110, 125, 137], "data_width": 108, "data_width_": 81, "data_width_a": [45, 59, 81], "data_width_b": [45, 59, 81], "databas": [11, 15, 16, 33, 35, 36, 151, 160, 162, 163], "dataint": 147, "datap": [45, 59, 81, 96], "datap_l": [110, 125, 137], "datap_u": [110, 125, 137], "datareg": 13, "datastream": [17, 152], "dbl": [38, 42, 47, 55, 68, 83, 91, 107, 121, 134, 142, 146, 149], "dbl0001010000": 121, "dbl0001100000": 121, "dbl0010010000": 121, "dbl0010100000": 121, "dbl0100010000": 121, "dbl0100100000": 121, "dbl1000010000": 121, "dbl1000100000": 121, "dcdr_filter": 105, "dci": [56, 91, 92, 100, 108, 113, 122, 135, 143], "dci0": [50, 85], "dci00": 50, "dci1": [50, 85], "dci11": 50, "dci_altvr": 85, "dci_altvrmisc": 85, "dci_clk_en": [50, 85, 98, 111], "dci_clk_enablemisc": 85, "dci_misc": [108, 122], "dci_mod": [57, 93, 108, 122], "dci_osc_sel": 50, "dci_t": [108, 122], "dci_test_mux": 50, "dcireset": [98, 111, 126], "dcireset0": 50, "dcireset1": 50, "dciupdatemode_asrequir": [57, 93, 108, 122], "dciupdatemode_asrequirediob0": [57, 93], "dciupdatemode_asrequirediob1": [57, 93], "dciupdatemode_asrequirediob2": 93, "dciupdatemode_asrequirediob3": [57, 93], "dciupdatemode_asrequirediob4": [57, 93], "dciupdatemode_asrequirediob5": 93, "dclk": [66, 111, 118, 119, 126, 132], "dclk0": 102, "dclk_divid_2": 109, "dclk_miss": 109, "dclkgtp": 66, "dclkgtp_dual": 118, "dclkgtx_dual": 119, "dclksysmon": 111, "dcm": [54, 56, 81, 87, 90, 102, 104, 106, 108], "dcm0": 64, "dcm0000000000001": 64, "dcm000001000000111111": 100, "dcm0_clk00000000110": 64, "dcm0_clk1800000010110": 64, "dcm0_clk2700000011110": 64, "dcm0_clk2x0000100010": 64, "dcm0_clk2x1800000101010": 64, "dcm0_clk900000001110": 64, "dcm0_clkdv0000110010": 64, "dcm0_clkfb011": 71, "dcm0_clkfx0000111010": 64, "dcm0_clkfx1800000100110": 64, "dcm0_clkin010": 71, "dcm0_concur0000101110": 64, "dcm1": 64, "dcm100001000001011111": 100, "dcm1000010001000011111": 100, "dcm1100010010000011111": 100, "dcm1200100000000111111": 100, "dcm1300100000001011111": 100, "dcm1400100000010011111": 100, "dcm1500100000100011111": 100, "dcm1600100001000011111": 100, "dcm1700100010000011111": 100, "dcm1801000000000111111": 100, "dcm1901000000001011111": 100, "dcm1_clk00001000000": 64, "dcm1_clk1800101000000": 64, "dcm1_clk2700111000000": 64, "dcm1_clk2x1000000000": 64, "dcm1_clk2x1801010000000": 64, "dcm1_clk900011000000": 64, "dcm1_clkdv1100000000": 64, "dcm1_clkfb001": 71, "dcm1_clkfx1110000000": 64, "dcm1_clkfx1801001000000": 64, "dcm1_clkin000": 71, "dcm1_concur1011000000": 64, "dcm200001000010011111": 100, "dcm2001000000010011111": 100, "dcm2101000000100011111": 100, "dcm2201000001000011111": 100, "dcm2301000010000011111": 100, "dcm300001000100011111": 100, "dcm400001001000011111": 100, "dcm500001010000011111": 100, "dcm600010000000111111": 100, "dcm700010000001011111": 100, "dcm800010000010011111": 100, "dcm900010000100011111": 100, "dcm_bufpll": 67, "dcm_clkdv_clkfx_align": 102, "dcm_clkdv_clkfx_alignmentdcm": 102, "dcm_enabl": 50, "dcm_ext_fb_en": 102, "dcm_ext_fb_endcm": 102, "dcm_lock_high": 102, "dcm_lock_highdcm": 102, "dcm_out100": 47, "dcm_out_l0100": [47, 83], "dcm_out_l01000": 47, "dcm_out_r1000": [47, 83], "dcm_out_r10000": 47, "dcm_performance_mod": 102, "dcm_performance_modedcm": 102, "dcm_pulse_width_correction_high": 102, "dcm_pulse_width_correction_low": 102, "dcm_shutdown": [48, 84, 101], "dcm_unused_taps_powerdown": 102, "dcm_unused_taps_powerdowndcm": 102, "dcm_vbg_pd": 102, "dcm_vbg_sel": 102, "dcm_vref_sourc": 102, "dcm_vreg": 52, "dcm_vreg_en": 102, "dcm_vreg_enabledcm": 102, "dcm_vreg_phase_margin": 102, "dcmclk": 91, "dcmclk0": 91, "dcmclk00001000001": 91, "dcmclk0int": 91, "dcmclk1": 91, "dcmclk10001000010": 91, "dcmclk1int": 91, "dcmclk2": 91, "dcmclk20001000001": 91, "dcmclk2int": 91, "dcmclk3": 91, "dcmclk30001000010": 91, "dcmclk3int": 91, "dcr_autolock_en": 124, "dcr_test": 124, "dcremacclk": 116, "dcy0": [60, 112, 127, 138], "dcy0slice0": [112, 127, 138], "dcy0slice1": [60, 138], "dd1": 34, "ddel_a": [45, 59, 81], "ddel_a_default": 45, "ddel_b": [45, 59, 81], "ddel_b_default": 45, "ddr": [56, 92], "ddr0": 108, "ddr01": 69, "ddr1": 61, "ddr210": 69, "ddr300": 69, "ddr_clk_edg": 108, "deal": [58, 87, 91], "dec_mcomma_detect": [88, 89, 105, 132], "dec_mcomma_detect_0": [66, 118, 119], "dec_mcomma_detect_0gtp": 66, "dec_mcomma_detect_0gtp_du": 118, "dec_mcomma_detect_0gtx_du": 119, "dec_mcomma_detect_1": [66, 118, 119], "dec_mcomma_detect_1gtp": 66, "dec_mcomma_detect_1gtp_du": 118, "dec_mcomma_detect_1gtx_du": 119, "dec_mcomma_detectgt11a": 105, "dec_mcomma_detectgt11b": 105, "dec_mcomma_detectgtx0": 132, "dec_mcomma_detectgtx1": 132, "dec_mcomma_detectgtx2": 132, "dec_mcomma_detectgtx3": 132, "dec_pcomma_detect": [88, 89, 105, 132], "dec_pcomma_detect_0": [66, 118, 119], "dec_pcomma_detect_0gtp": 66, "dec_pcomma_detect_0gtp_du": 118, "dec_pcomma_detect_0gtx_du": 119, "dec_pcomma_detect_1": [66, 118, 119], "dec_pcomma_detect_1gtp": 66, "dec_pcomma_detect_1gtp_du": 118, "dec_pcomma_detect_1gtx_du": 119, "dec_pcomma_detectgt11a": 105, "dec_pcomma_detectgt11b": 105, "dec_pcomma_detectgtx0": 132, "dec_pcomma_detectgtx1": 132, "dec_pcomma_detectgtx2": 132, "dec_pcomma_detectgtx3": 132, "dec_valid_comma_onli": [88, 89, 105, 132], "dec_valid_comma_only_0": [66, 118, 119], "dec_valid_comma_only_0gtp": 66, "dec_valid_comma_only_0gtp_du": 118, "dec_valid_comma_only_0gtx_du": 119, "dec_valid_comma_only_1": [66, 118, 119], "dec_valid_comma_only_1gtp": 66, "dec_valid_comma_only_1gtp_du": 118, "dec_valid_comma_only_1gtx_du": 119, "dec_valid_comma_onlygt11a": 105, "dec_valid_comma_onlygt11b": 105, "dec_valid_comma_onlygtx0": 132, "dec_valid_comma_onlygtx1": 132, "dec_valid_comma_onlygtx2": 132, "dec_valid_comma_onlygtx3": 132, "decod": 96, "dedic": [12, 14, 34, 36, 45, 46, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 117, 122, 135, 140, 143, 152, 161, 163], "def": [15, 16], "default": [17, 35, 54], "default00": 108, "defin": 163, "definit": 143, "del_clk_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 153, 154, 155, 156, 157, 158], "del_d_q_comb": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_d_q_latch": [2, 3, 4, 5, 6, 7, 8, 9, 153, 154, 155, 156, 157, 158], "del_exp_d": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_exp_exp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_d": [2, 3, 4, 5, 6, 7, 8, 9, 153, 154, 155, 156, 157, 158], "del_ibuf_fclk": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 153, 154, 155, 156, 157, 158], "del_ibuf_fo": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_fsr": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 153, 154, 155, 156, 157, 158], "del_ibuf_plain": [2, 3, 4, 5, 6, 7, 8, 9], "del_ibuf_schmitt": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_ct": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_d_hp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_d_lp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_fbn": [153, 154, 155, 156, 157, 158], "del_imux_or": [2, 3, 4, 5, 6, 7, 8, 9, 153, 154, 155, 156, 157, 158], "del_imux_pt": [2, 3, 4, 5, 6, 7, 8, 9, 153, 154, 155, 156, 157, 158], "del_imux_pt_c": [20, 21, 24, 25, 27, 28, 30, 31], "del_imux_pt_clk": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 153, 154, 155, 156, 157, 158], "del_imux_pt_o": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_pt_sr": [20, 21, 24, 25, 27, 28, 30, 31], "del_mc_fo": [2, 3, 4, 5, 6, 7, 8, 9], "del_obuf_fast": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 153, 154, 155, 156, 157, 158], "del_obuf_o": [2, 3, 4, 5, 6, 7, 8, 9, 153, 154, 155, 156, 157, 158], "del_obuf_slow": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 153, 154, 155, 156, 157, 158], "del_pt_ut": [153, 154, 155, 156, 157, 158], "del_sr_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 153, 154, 155, 156, 157, 158], "del_uim_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 153, 154, 155, 156, 157, 158], "delai": [14, 44, 47, 74, 78, 117, 120, 131, 133, 140, 141], "delay0": 149, "delay_common": 57, "delay_commoniob0": 57, "delay_commoniob1": 57, "delay_commoniob2": 57, "delay_commoniob3": 57, "delay_commoniob4": 57, "delay_commoniob5": 57, "delay_commoniob6": 57, "delay_en": 43, "delay_vari": 57, "delay_variableiob0": 57, "delay_variableiob1": 57, "delay_variableiob3": 57, "delay_variableiob4": 57, "delayed_write0": 137, "delayed_write00": 125, "delaymux": 149, "delaymuxint": 149, "delaymuxiob2": 149, "delaymuxiob3": 149, "depend": [17, 35, 36, 55, 58, 81, 91, 104, 108, 117, 131, 140, 143, 152, 162, 163], "deriv": [12, 34, 56, 92, 161, 163], "describ": [17, 35, 46, 47, 58, 81, 82, 83, 100, 113, 152], "descript": [45, 99], "design": [12, 36, 58, 161, 163], "deskew_adjust": [54, 64, 90, 102], "despit": 140, "destin": 36, "detail": [35, 58, 87, 96, 162], "determin": [12, 34, 35, 46, 82, 163], "dev_cap2_ari_forwarding_support": 144, "dev_cap2_ari_forwarding_supportedpci": 144, "dev_cap2_atomicop32_completer_support": 144, "dev_cap2_atomicop32_completer_supportedpci": 144, "dev_cap2_atomicop64_completer_support": 144, "dev_cap2_atomicop_routing_support": 144, "dev_cap2_cas128_completer_support": 144, "dev_cap2_cas128_completer_supportedpci": 144, "dev_cap2_endend_tlp_prefix_support": 144, "dev_cap2_endend_tlp_prefix_supportedpci": 144, "dev_cap2_extended_fmt_field_support": 144, "dev_cap2_ltr_mechanism_support": 144, "dev_cap2_ltr_mechanism_supportedpci": 144, "dev_cap2_max_endend_tlp_prefix": 144, "dev_cap2_no_ro_enabled_prpr_pass": 144, "dev_cap2_tph_completer_support": 144, "dev_cap_enable_slot_pwr_limit_scal": [136, 144], "dev_cap_enable_slot_pwr_limit_scalepci": [136, 144], "dev_cap_enable_slot_pwr_limit_valu": [136, 144], "dev_cap_endpoint_l0s_lat": [70, 136, 144], "dev_cap_endpoint_l1_lat": [70, 136, 144], "dev_cap_ext_tag_support": [70, 136, 144], "dev_cap_ext_tag_supportedpci": [136, 144], "dev_cap_function_level_reset_cap": [136, 144], "dev_cap_max_payload_support": [70, 136, 144], "dev_cap_phantom_functions_support": [70, 136, 144], "dev_cap_role_based_error": [70, 136, 144], "dev_cap_rsvd_14_12": [136, 144], "dev_cap_rsvd_17_16": [136, 144], "dev_cap_rsvd_31_29": [136, 144], "dev_control_aux_power_support": [136, 144], "dev_control_aux_power_supportedpci": 144, "dev_control_ext_tag_default": 144, "devic": [11, 15, 16, 33, 35, 44, 45, 46, 47, 54, 55, 81, 82, 83, 90, 91, 106, 108, 120, 122, 133, 135, 141, 143, 151, 160, 162], "device_id": 136, "devicebram": 45, "devicecapabilityendpointl0slat": 123, "devicecapabilityendpointl1lat": 123, "devicedcm": [51, 52, 86], "deviceid": 123, "deviceserialnumb": 123, "devicevalu": [47, 61], "devoid": 140, "df": [51, 86], "dfb001": 61, "dfb010": 61, "dfe_cal_tim": [119, 132], "dfe_cfg": 132, "dfe_cfg_0": 119, "dfe_cfg_1": 119, "dfe_drp_en": 132, "dfe_drp_engtx0": 132, "dfe_drp_engtx1": 132, "dfe_drp_engtx2": 132, "dfe_drp_engtx3": 132, "dff": [14, 36, 163], "dff0": 16, "dff00": [2, 3, 4, 5, 6, 7, 8, 9, 151], "dff1": 15, "dff_latch": 127, "dff_latchslice0": 127, "dffce": 163, "dffce11": [2, 3, 4, 5, 6, 7, 8, 9, 151], "dffinit": [112, 127, 138], "dffinitslice0": [112, 127, 138], "dffmux": [60, 112, 127, 138], "dffmuxslice1": 60, "dffsr": [112, 127, 138], "dffsrinit": 60, "dffsrinitslice1": 60, "dffsrslice0": 138, "dffsrslice1": 127, "dfs_": [52, 64], "dfs_ave_freq_adj_interv": 102, "dfs_ave_freq_gain": 102, "dfs_ave_freq_sample_interv": 102, "dfs_c": [52, 64], "dfs_coarse_sel": 102, "dfs_coarse_seldcm": 102, "dfs_coin_window": 102, "dfs_early_lock": 102, "dfs_early_lockdcm": 102, "dfs_en_relrst": 102, "dfs_en_relrstdcm": 102, "dfs_enabl": [51, 52, 64, 86, 102], "dfs_enabledcm": [51, 52, 86, 102], "dfs_enabledcm0": 64, "dfs_enabledcm1": 64, "dfs_extend_flush_tim": 102, "dfs_extend_flush_timedcm": 102, "dfs_extend_halt_tim": 102, "dfs_extend_halt_timedcm": 102, "dfs_extend_run_tim": 102, "dfs_extend_run_timedcm": 102, "dfs_feedback": [51, 52, 64, 86, 102], "dfs_feedbackdcm": [51, 52, 102], "dfs_feedbackdcm0": 64, "dfs_feedbackdcm1": 64, "dfs_fine_sel": 102, "dfs_fine_seldcm": 102, "dfs_frequency_mod": [51, 52, 64, 86, 102], "dfs_frequency_modedcm": [51, 52, 102], "dfs_frequency_modedcm0": 64, "dfs_frequency_modedcm1": 64, "dfs_hardsync": 102, "dfs_non_stop": 102, "dfs_non_stopdcm": 102, "dfs_oscillator_mod": 102, "dfs_skip_fin": 102, "dfs_skip_finedcm": 102, "dfs_spare": 102, "dfs_tp_sel": 102, "dfs_tp_seldcm": 102, "dfs_trackmod": 102, "dfs_trackmodedcm": 102, "dge": [2, 3, 6, 7, 12, 14], "dge_en": [2, 3, 6, 7], "di": [12, 46, 81, 82, 96, 146], "di0": [102, 146], "di1": 102, "di10": 102, "di10dcm": 102, "di11": [102, 146], "di12": 102, "di126": [2, 12], "di12dcm": 102, "di13": 102, "di13dcm": 102, "di14": 102, "di14dcm": 102, "di15": 102, "di1dcm": 102, "di2": 102, "di222": [3, 12], "di288": [6, 12], "di2dcm": 102, "di3": 102, "di324": [7, 12], "di4": 102, "di44": [4, 5, 12], "di4dcm": 102, "di5": 102, "di5dcm": 102, "di6": 102, "di6dcm": 102, "di7": 102, "di8": 102, "di81": [8, 9, 12], "di9": 102, "di9dcm": 102, "dia": 96, "dia0": 72, "dia1": 72, "dia10": 72, "dia11": 72, "dia12": 72, "dia13": 72, "dia14": 72, "dia15": 72, "dia2": 72, "dia3": 72, "dia4": 72, "dia5": 72, "dia6": 72, "dia7": 72, "dia8": 72, "dia9": 72, "diagon": [55, 91], "dib": 96, "dib0": 72, "dib1": 72, "dib10": 72, "dib11": 72, "dib12": 72, "dib13": 72, "dib14": 72, "dib15": 72, "dib16": 81, "dib2": 72, "dib3": 72, "dib31": 81, "dib4": 72, "dib5": 72, "dib6": 72, "dib7": 72, "dib8": 72, "dib9": 72, "die": [12, 17, 56, 140, 143, 152], "dif": [46, 82], "dif_mux": [37, 46, 82, 99], "dif_muxslice0": 99, "diff010": [108, 122], "diff10": [74, 79], "diff101": [57, 93], "diff110": 57, "differ": [16, 35, 36, 46, 55, 82, 91, 143, 161, 163], "differenti": [14, 56, 108, 122, 135, 143], "dig": [46, 82], "dig_mux": [37, 46, 82, 99], "dig_muxslice0": 99, "dig_muxslice2": 99, "digit": [44, 54, 55, 56, 67, 90, 91, 92, 106], "digrx_fwdclk": 105, "digrx_sync_mod": 105, "digrx_sync_modegt11a": 105, "digrx_sync_modegt11b": 105, "dimens": 58, "dimension": 151, "din": [135, 143], "din0": 72, "din0000": 72, "din0001": 72, "din0int": 72, "din1": 72, "din10": 72, "din1000": 72, "din10000": 72, "din10001": 72, "din1001": 72, "din10int": 72, "din11": 72, "din11001": 72, "din11010": 72, "din11int": 72, "din12": 72, "din12010": 72, "din12011": 72, "din12int": 72, "din13": 72, "din13010": 72, "din13011": 72, "din13int": 72, "din14": 72, "din14010": 72, "din14011": 72, "din14int": 72, "din15": 72, "din15000": 72, "din15011": 72, "din15int": 72, "din16": 72, "din16110": 72, "din16111": 72, "din16int": 72, "din17": 72, "din17100": 72, "din17111": 72, "din17int": 72, "din18": 72, "din18100": 72, "din18101": 72, "din18int": 72, "din19": 72, "din19100": 72, "din19101": 72, "din19int": 72, "din1int": 72, "din2": 72, "din20": 72, "din2000": 72, "din2001": 72, "din20100": 72, "din20101": 72, "din20int": 72, "din21": 72, "din21101": 72, "din21110": 72, "din21int": 72, "din22": 72, "din22110": 72, "din22111": 72, "din22int": 72, "din23": 72, "din23110": 72, "din23111": 72, "din23int": 72, "din24": 72, "din24110": 72, "din24111": 72, "din24int": 72, "din25": 72, "din25100": 72, "din25111": 72, "din25int": 72, "din26": 72, "din26100": 72, "din26101": 72, "din26int": 72, "din27": 72, "din27100": 72, "din27101": 72, "din27int": 72, "din28": 72, "din28100": 72, "din28101": 72, "din28int": 72, "din29": 72, "din29101": 72, "din29110": 72, "din29int": 72, "din2int": 72, "din3": 72, "din30": 72, "din3001": 72, "din3010": 72, "din30110": 72, "din30111": 72, "din30int": 72, "din31": 72, "din31110": 72, "din31111": 72, "din31int": 72, "din3int": 72, "din4": 72, "din4010": 72, "din4011": 72, "din4int": 72, "din5": 72, "din5010": 72, "din5011": 72, "din5int": 72, "din6": 72, "din6010": 72, "din6011": 72, "din6int": 72, "din7": 72, "din7000": 72, "din7011": 72, "din7int": 72, "din8": 72, "din8000": 72, "din8001": 72, "din8int": 72, "din9": 72, "din9000": 72, "din9001": 72, "din9int": 72, "dinpin": [98, 111, 126], "dip": [81, 96], "dipa": 96, "dipb": 96, "direct": [36, 55, 81, 91], "direct0": [45, 53, 65, 103, 115, 129, 132, 139], "directli": [14, 17, 35, 36, 46, 58, 81, 82, 91, 152, 163], "dis_tstblclamp": 137, "dis_tstfiforst": [125, 137], "dis_vgg_reg": 128, "disabl": [36, 163], "disable111": 147, "disable_aspm_l1_tim": [136, 144], "disable_aspm_l1_timerpci": [136, 144], "disable_attr": [47, 61, 74, 83], "disable_attrbufg1": 74, "disable_attrbufgmux0": 47, "disable_attrbufgmux2": 47, "disable_attrbufgmux6": 47, "disable_attrbufgmux7": 47, "disable_attrint": 74, "disable_bar_filt": [70, 136, 144], "disable_err_msg": 144, "disable_gt": [57, 93], "disable_gtsiob0": 57, "disable_gtsiob1": 93, "disable_gtsiob2": [57, 93], "disable_gtsiob3": 57, "disable_gtsiob4": [57, 93], "disable_id_check": [70, 136, 144], "disable_id_checkpci": [136, 144], "disable_jtag": 126, "disable_lane_revers": [136, 144], "disable_lane_reversalpci": 136, "disable_locked_filt": 144, "disable_ppm_filt": 144, "disable_ppm_filterpci": 144, "disable_rx_poisoned_resp": 144, "disable_rx_poisoned_resppci": 144, "disable_rx_tc_filt": [136, 144], "disable_scrambl": [70, 136, 144], "disable_scramblingpci": 144, "disable_vrd_reg": 62, "disablebandgap": 85, "disablebandgapmisc": 85, "disablevgggener": 85, "disablevgggenerationmisc": 85, "disconnect": [55, 163], "displac": 58, "dispmp1": 75, "dispmp2": 75, "distanc": [2, 3, 4, 5, 6, 7, 8, 9, 55, 58, 91], "distribut": [41, 54, 55, 58, 87, 90, 91, 131, 140], "distrubut": 131, "div12110": 69, "div2001": 69, "div201": 69, "div4010": 69, "div410": 69, "div60": 69, "div6011": 69, "div71": 69, "div8100": 69, "divclk11": 61, "divid": [11, 12, 58, 61, 104, 117, 131, 140, 151, 163], "divide_100": 61, "divide_1000": 61, "divide_2001": 61, "divide_201": 61, "divide_300": 61, "divide_3010": 61, "divide_400": 61, "divide_4011": 61, "divide_501": 61, "divide_5100": 61, "divide_601": 61, "divide_6101": 61, "divide_710": 61, "divide_7110": 61, "divide_810": 61, "divide_8111": 61, "divide_bypass": 61, "divis": [96, 161], "dll": [51, 74, 78, 86, 92], "dll_": [52, 64], "dll_c": [52, 64], "dll_control_clock_spe": 102, "dll_control_clock_speeddcm": 102, "dll_ctl_sel_clkin_div2": 102, "dll_ctl_sel_clkin_div2dcm": 102, "dll_dead_tim": 102, "dll_deskew_lock_by1": 102, "dll_deskew_lock_by1dcm": 102, "dll_deskew_maxtap": 102, "dll_deskew_mintap": 102, "dll_enabl": [51, 52, 64, 76, 86, 102], "dll_enabledcm": [51, 52, 102], "dll_enabledcm0": 64, "dll_enabledcm1": 64, "dll_enablemisc": 76, "dll_frequency_mod": [51, 52, 64, 86, 102], "dll_frequency_modedcm": 52, "dll_frequency_modedcm0": 64, "dll_frequency_modedcm1": 64, "dll_live_tim": 102, "dll_pd_dly_sel": 102, "dll_period_lock_by1": 102, "dll_period_lock_by1dcm": 102, "dll_phase_detector_auto_reset": 102, "dll_phase_detector_auto_resetdcm": 102, "dll_phase_detector_mod": 102, "dll_phase_detector_modedcm": 102, "dll_phase_shift_calibr": 102, "dll_phase_shift_hfc": 102, "dll_phase_shift_lfc": 102, "dll_phase_shift_lock_by1": 102, "dll_phase_shift_lock_by1dcm": 102, "dll_settle_tim": 102, "dll_spare": 102, "dll_test_mux_sel": 102, "dll_wait_bl": 75, "dll_wait_br": 75, "dll_wait_tl": 75, "dll_wait_tr": 75, "dllc": [51, 86], "dllp": 78, "dma0_control": 124, "dma0_rxchannelctrl": 124, "dma0_rxirqtim": 124, "dma0_txchannelctrl": 124, "dma0_txirqtim": 124, "dma1_control": 124, "dma1_rxchannelctrl": 124, "dma1_rxirqtim": 124, "dma1_txchannelctrl": 124, "dma1_txirqtim": 124, "dma2_control": 124, "dma2_rxchannelctrl": 124, "dma2_rxirqtim": 124, "dma2_txchannelctrl": 124, "dma2_txirqtim": 124, "dma3_control": 124, "dma3_rxchannelctrl": 124, "dma3_rxirqtim": 124, "dma3_txchannelctrl": 124, "dma3_txirqtim": 124, "dma_test": 124, "dmux": 146, "dna_opt": 63, "dna_port": [56, 63, 126], "dnstream_link_num": [136, 144, 145], "do": [35, 46, 81, 82, 91, 96, 143], "do1": 146, "do11000": 146, "do11001": 146, "do11010": 146, "do11011": 146, "doa": [81, 96], "doa0": [72, 96], "doa0int": 72, "doa1": 72, "doa10": 72, "doa10int": 72, "doa11": 72, "doa11int": 72, "doa12": 72, "doa12int": 72, "doa13": 72, "doa13int": 72, "doa14": 72, "doa14int": 72, "doa15": 72, "doa15int": 72, "doa1int": 72, "doa2": 72, "doa3": 72, "doa31": 96, "doa4": 72, "doa4int": 72, "doa5": 72, "doa6": 72, "doa6int": 72, "doa7": 72, "doa8": 72, "doa8int": 72, "doa9": 72, "doa9int": 72, "doa_reg": [45, 59, 96], "doa_reg_l": [110, 125, 137], "doa_reg_u": [110, 125, 137], "dob": [81, 96], "dob0": 72, "dob0int": 72, "dob1": 72, "dob10": [72, 96], "dob10int": 72, "dob11": [72, 96], "dob11int": 72, "dob12": 72, "dob12int": 72, "dob13": 72, "dob13int": 72, "dob14": 72, "dob14int": 72, "dob15": 72, "dob15int": 72, "dob1int": 72, "dob2": 72, "dob3": 72, "dob4": [72, 96], "dob4int": 72, "dob5": [72, 96], "dob6": [72, 96], "dob6int": 72, "dob7": [72, 96], "dob8": [72, 96], "dob8int": 72, "dob9": [72, 96], "dob9int": 72, "dob_reg": [45, 59, 96], "dob_reg_l": [110, 125, 137], "dob_reg_u": [110, 125, 137], "document": [15, 16, 38, 39, 40, 41, 43, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 57, 60, 62, 63, 64, 65, 66, 67, 69, 71, 75, 78, 81, 82, 83, 84, 85, 86, 88, 89, 93, 94, 95, 98, 99, 101, 104, 105, 106, 107, 108, 111, 112, 114, 117, 118, 119, 120, 121, 122, 126, 127, 128, 131, 132, 133, 134, 135, 138, 140, 141, 142, 148], "doe": [34, 140], "doesn": [16, 36, 46, 55, 58, 81, 91, 140, 163], "domux": 146, "domuxlc2": 146, "don": [35, 36, 46, 55, 58, 140, 163], "done": [2, 3, 4, 5, 6, 7, 8, 9, 14, 16, 34, 35, 36, 96, 108, 122, 135, 143], "done110": [39, 48, 75, 84, 101, 114, 128], "done111": [49, 62], "done_act": 147, "done_cycl": [39, 48, 49, 62, 75, 84, 101, 114, 128], "done_in00": 147, "done_pip": [39, 48, 49, 62, 75, 84, 101, 114, 128], "done_signals_powerdown": 128, "donein": 147, "donepin": [50, 63, 76, 85, 98, 111, 126, 147], "donepinint": 147, "donepinmisc": 76, "dont_set1": 115, "dop": [81, 96], "dopa": 96, "doubl": [55, 91], "dout": 143, "dout0": 72, "dout000": 72, "dout0000": 72, "dout001": 72, "dout0int": 72, "dout1": 72, "dout10": 72, "dout100": 72, "dout1000": 72, "dout1001": 72, "dout10010": 72, "dout101": 72, "dout10int": 72, "dout11": 72, "dout1100": 72, "dout1101": 72, "dout11010": 72, "dout11int": 72, "dout12": 72, "dout1200": 72, "dout1201": 72, "dout12011": 72, "dout12int": 72, "dout13": 72, "dout1300": 72, "dout1301": 72, "dout13011": 72, "dout13int": 72, "dout14": 72, "dout1400": 72, "dout1401": 72, "dout14011": 72, "dout14int": 72, "dout15": 72, "dout1500": 72, "dout1501": 72, "dout15011": 72, "dout15int": 72, "dout16": 72, "dout1610": 72, "dout16100": 72, "dout1611": 72, "dout16int": 72, "dout17": 72, "dout1710": 72, "dout17100": 72, "dout1711": 72, "dout17int": 72, "dout18": 72, "dout1810": 72, "dout18100": 72, "dout1811": 72, "dout18int": 72, "dout19": 72, "dout1910": 72, "dout19100": 72, "dout1911": 72, "dout19int": 72, "dout1int": 72, "dout2": 72, "dout20": 72, "dout200": 72, "dout2000": 72, "dout201": 72, "dout2010": 72, "dout20101": 72, "dout2011": 72, "dout20int": 72, "dout21": 72, "dout2110": 72, "dout21101": 72, "dout2111": 72, "dout21int": 72, "dout22": 72, "dout2210": 72, "dout22101": 72, "dout2211": 72, "dout22int": 72, "dout23": 72, "dout2310": 72, "dout23101": 72, "dout2311": 72, "dout23int": 72, "dout24": 72, "dout2410": 72, "dout2411": 72, "dout24110": 72, "dout24int": 72, "dout25": 72, "dout2510": 72, "dout2511": 72, "dout25110": 72, "dout25int": 72, "dout26": 72, "dout2610": 72, "dout2611": 72, "dout26110": 72, "dout26int": 72, "dout27": 72, "dout2710": 72, "dout2711": 72, "dout27110": 72, "dout27int": 72, "dout28": 72, "dout2810": 72, "dout2811": 72, "dout28111": 72, "dout28int": 72, "dout29": 72, "dout2910": 72, "dout2911": 72, "dout29111": 72, "dout29int": 72, "dout2int": 72, "dout3": 72, "dout30": 72, "dout300": 72, "dout3000": 72, "dout301": 72, "dout3010": 72, "dout3011": 72, "dout30111": 72, "dout30int": 72, "dout31": 72, "dout3110": 72, "dout3111": 72, "dout31111": 72, "dout31int": 72, "dout3int": 72, "dout4": 72, "dout400": 72, "dout4001": 72, "dout401": 72, "dout4int": 72, "dout5": 72, "dout500": 72, "dout5001": 72, "dout501": 72, "dout5int": 72, "dout6": 72, "dout600": 72, "dout6001": 72, "dout601": 72, "dout6int": 72, "dout7": 72, "dout700": 72, "dout7001": 72, "dout701": 72, "dout7int": 72, "dout8": 72, "dout800": 72, "dout801": 72, "dout8010": 72, "dout8int": 72, "dout9": 72, "dout900": 72, "dout901": 72, "dout9010": 72, "dout9int": 72, "dout_busi": [108, 135], "doutmux": [60, 112, 127, 138], "doutmuxslice1": 60, "down": [36, 55, 56, 58, 104, 163], "down0": 15, "down1": [16, 151], "downward": [36, 122], "dpm": 97, "dpm_oscout10001000100": 97, "dpm_oscout20001000010": 97, "dpm_refclkout0001010000": 97, "dq": 143, "dqs0011": 61, "dqs2110": 61, "dr": [13, 151], "drain": 14, "drammod": [60, 112, 127, 138], "drck": 147, "drck100": 76, "drck200": 76, "dreg": [53, 65, 129, 139], "dregdsp": [53, 65], "dregdsp0": 129, "dregdsp1": 129, "drive": [12, 14, 17, 34, 35, 36, 55, 56, 58, 72, 73, 74, 76, 79, 82, 91, 108, 122, 135, 143, 161, 163], "drive_awak": [49, 62], "drive_both111": 105, "drive_don": [39, 48, 49, 62, 75, 84, 101, 114, 128], "drive_down110": 105, "drive_last_value0001": 57, "drive_pd_statu": 76, "drive_pd_statusmisc": 76, "drive_up101": 105, "driven": [14, 36, 55, 58, 87, 91, 163], "driver": [12, 34, 55, 91], "drp00": [66, 71, 118, 119, 132], "drp01": [66, 71, 118, 119, 132], "drp02": [66, 71, 118, 119, 132], "drp03": [66, 71, 118, 119, 132], "drp04": [66, 71, 118, 119, 132], "drp05": [66, 71, 118, 119, 132], "drp06": [66, 71, 118, 119, 132], "drp07": [66, 71, 118, 119, 132], "drp08": [66, 71, 118, 119, 132], "drp09": [66, 71, 118, 119, 132], "drp0a": [66, 71, 118, 119, 132], "drp0b": [66, 71, 118, 119, 132], "drp0c": [66, 71, 118, 119, 132], "drp0d": [66, 71, 118, 119, 132], "drp0e": [66, 71, 118, 119, 132], "drp0f": [66, 71, 118, 119, 132], "drp10": [66, 71, 118, 119, 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47, 55, 74, 83, 150], "clkb_2dll": 74, "clkb_4dll": 74, "clkc": [38, 47, 61], "clkc_50a": 47, "clkh": 150, "clkl": [47, 80, 150], "clkpad": 91, "clkr": [47, 80, 150], "clkt": [38, 47, 55, 74, 83, 150], "clkt_2dll": 74, "clkt_4dll": 74, "clkv": [74, 150], "clkv_bram_bot": 74, "clkv_bram_top": 74, "clock": [14, 38, 47, 51, 52, 58, 61, 64, 74, 83, 86, 87, 91, 97, 100, 102, 113], "cmt": [68, 113], "cnr": [76, 91, 147], "column": [58, 72, 104, 117, 131, 140, 163], "combin": 0, "companion": 97, "configur": [14, 36, 37, 39, 46, 48, 49, 60, 62, 73, 75, 82, 84, 98, 99, 101, 111, 112, 114, 126, 127, 128, 138, 140, 146, 163], "content": [0, 10, 11, 32, 33, 41, 44, 54, 67, 78, 90, 106, 120, 133, 141, 148, 159, 160], "control": [69, 163], "coolrunn": 11, "cor": [39, 48, 75, 84, 101, 114, 128], "cor1": [49, 62, 114, 128], "cor2": [49, 62], "core": [95, 123, 124, 136, 144, 145], "corner": [40, 50, 63, 76, 85, 147], "cpld": [11, 33, 160], "ctl": [39, 48, 49, 62, 75, 84, 101, 114, 128], "ctl1": 128, "data": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 50, 85, 100, 113, 153, 154, 155, 156, 157, 158], "databas": [10, 17, 32, 152, 159], "dcm": [51, 52, 55, 58, 83, 86, 91, 100], "dcm_bufpll": 61, "dcmconn": 83, "default": [45, 47], "delai": [77, 121, 134, 142], "deskew_adjust": [51, 52, 86], "devic": [10, 12, 14, 17, 32, 34, 36, 56, 58, 87, 92, 104, 117, 131, 140, 152, 159, 161, 163], "digit": [51, 52, 64, 86, 102], "distribut": [38, 47, 83], "divid": 14, "dll": 77, "dllp": 77, "dr": 35, "dsp": [49, 53, 55, 58, 65, 103, 115, 129, 139], "dual": [46, 82], "dummi": 55, "e": [79, 91], "ecc": [96, 104, 117, 131, 140], "enabl": 15, "enter": 35, "eras": 35, "ethernet": [116, 130], "exit": 35, "export": 36, "express": [70, 123, 136, 140, 144, 145], "eye_mask": 62, "fb": [14, 15, 16, 36, 151, 163], "fc": [38, 39, 40, 42, 43], "fclk": 163, "fifo": 96, "flip": 36, "flop": 36, "format": [15, 16], "fpga": 44, "fpgacor": 41, "frequenc": 35, "function": [108, 122, 135, 143], "fuse": [15, 16, 35, 36, 151], "gate": [14, 36], "gclkc": 83, "gclkh": [38, 47, 83], "gclkv": 74, "gclkvc": [38, 47], "gclkvm": [38, 47], "gen2": 144, "gen3": 145, "gener": [42, 49, 55, 58, 62, 68, 87, 91, 104, 107, 117, 131, 140], "general5": 62, "geometri": [58, 87, 104, 117, 131, 140], "gigabit": [66, 88, 89, 105], "gigabit10": 89, "global": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 36, 151, 153, 154, 155, 156, 157, 158], "gt": 91, "gtp": [118, 140], "gtx": [119, 132, 140], "hard": [94, 95], "hc_opt": [49, 62], "hclk": [61, 100, 113], "hclk_center": 100, "hclk_center_above_cfg": 100, "hclk_cmt": 113, "hclk_cmt_ioi": 113, "hclk_dcm": 100, "hclk_dcmiob": 100, "hclk_iobdcm": 100, "hclk_ioi": 113, "hclk_ioi_botcen": 113, "hclk_ioi_cent": 113, "hclk_ioi_cmt": 113, "hclk_ioi_topcen": 113, "hclk_iois_dci": 100, "hclk_iois_lvd": 100, "hclk_mgt": 100, "hclk_row": 61, "hclk_term_l": 100, "hclk_term_r": 100, "hole": [87, 91, 104, 117, 140], "horizont": 58, "i": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 57, 79, 85, 93, 100, 108, 113, 122, 135, 143, 153, 154, 155, 156, 157, 158], "ibuf": 23, "idcod": [35, 162], "ii": 11, "import": 36, "imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 151, 153, 154, 155, 156, 157, 158], "input": [14, 15, 16, 36, 43, 55, 57, 79, 91, 93, 108, 122, 135, 143, 149, 163], "instruct": [13, 35, 162], "int": [42, 55, 91], "interconnect": [38, 42, 47, 55, 61, 68, 74, 83, 91, 100, 107, 113, 121, 134, 142], "interfac": [13, 35, 43, 55, 57, 68, 91, 93, 107, 162], "intf": [55, 68, 91, 121, 134, 142], "introduct": [12, 34, 56, 92, 161], "io": [58, 79, 87, 100, 113, 140, 149], "iob": [2, 3, 6, 7, 14, 43, 57, 79, 93, 100, 113, 151, 163], "ioi": [42, 43, 55, 57, 68, 91, 93], "ir": [13, 35, 162], "isp": [13, 35, 162], "jed": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 151, 152, 153, 154, 155, 156, 157, 158], "jtag": [13, 35, 162], "keeper": 36, "l": [43, 79, 93, 149], "l1": [57, 93], "l2": [57, 93], "l3": 57, "l4": 57, "lb": 52, "left": [40, 47, 50, 61, 63, 72, 85], "level": [17, 152], "line": 55, "ll": [40, 50, 85], "llh": 55, "llv": 55, "local": 163, "lock": [71, 77], "logic": [37, 46, 60, 73, 80, 82, 87, 94, 99, 112, 127, 138, 146], "long": 55, "loop": [71, 77], "lower": [40, 50, 63, 85], "lr": [40, 50, 55, 57, 85], "lt": 52, "lut": [46, 82], "lut2": 163, "mac": [116, 130], "macrocel": [14, 15, 16, 36, 151, 163], "manag": [51, 52, 64, 86, 102], "map": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 151, 153, 154, 155, 156, 157, 158], "mc": [2, 3, 4, 5, 6, 7, 8, 9], "memori": 69, "mgt": [100, 113], "middl": [72, 140], "misc": [14, 36, 163], "mode": [35, 49, 62, 96], "modul": 97, "monitor": 109, "mult": 81, "multi": [66, 88, 89, 105], "multiplex": [46, 55, 82, 91], "mux": [100, 113], "n": [47, 91], "network": [14, 36, 163], "node": [100, 113], "normal": 68, "o": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 57, 79, 85, 93, 100, 108, 113, 122, 135, 143, 153, 154, 155, 156, 157, 158], "option": [45, 47], "output": [14, 36, 43, 46, 55, 57, 79, 82, 83, 91, 93, 108, 122, 135, 143, 149, 163], "overview": [14, 36, 163], "packag": [12, 34, 161], "part": [17, 152], "pci": [70, 80, 87, 94, 123, 136, 140, 144, 145], "pci_ce_delai": 61, "pcie_l": 144, "pcie_r": 144, "pcilogics": 61, "per": [15, 16], "phase": 71, "pin": [2, 3, 4, 5, 6, 7, 8, 9, 12, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34, 153, 154, 155, 156, 157, 158, 161], "placement": 140, "pll_bufpll_b": 61, "pll_bufpll_out0": 61, "pll_bufpll_out1": 61, "pll_bufpll_t": 61, "pma_spe": 89, "pmviob": 126, "port": [46, 82], "powerdown": [49, 62], "powerpc": [87, 91, 95, 104, 117, 124], "ppc": 91, "primari": 58, "primit": [55, 91], "pro": [85, 88, 89, 93], "process": 140, "product": [14, 15, 16, 36, 82, 151, 163], "program": [13, 35, 162], "project": 0, "protect": 35, "pt": 36, "pu_gt": [49, 62], "pu_gw": [49, 62], "pull": 36, "r": [43, 79, 93, 149], "r1": [57, 93], "r2": [57, 93], "r3": 57, "r4": 57, "ram": [45, 46, 59, 72, 81, 82, 96, 110, 125, 137], "randor": [37, 46], "randor_init": [37, 46], "rb": 52, "read": 35, "regist": [13, 14, 35, 39, 46, 48, 49, 62, 75, 82, 84, 101, 114, 128, 162, 163], "repeat": [100, 113], "reserved_andor": [37, 46], "right": [40, 47, 50, 61, 63, 72, 85, 140], "row": [38, 47, 58, 83, 87, 100, 163], "rt": 52, "s3": [38, 39, 45, 47, 48, 50, 51, 55, 57], "s3a": [45, 47, 49, 50, 55, 57], "s3adsp": [45, 55], "s3e": [45, 47, 48, 50, 52, 55, 57], "scan": [13, 35, 162], "schema": [17, 152], "secondari": [38, 47, 58], "sequenc": [13, 35, 162], "seu_opt": [49, 62], "shift": [46, 82], "side": 72, "singl": [46, 82], "sourc": [38, 47, 83], "spartan": [46, 48, 49, 50, 51, 52, 54, 57, 58, 67, 81], "special": [108, 122, 135, 143], "speed": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 152, 153, 154, 155, 156, 157, 158], "spine": [38, 47, 58, 83, 87, 91, 100, 104, 113, 117], "splitter": [55, 150], "standard": [100, 113], "structur": [1, 14, 15, 16, 36, 58, 87, 104, 117, 131, 140, 151, 163], "sum": [14, 36, 82, 151, 163], "system": [109, 140], "t": [43, 57, 79, 83, 88, 89, 93, 149], "t0": 91, "t1": 57, "t123": 91, "t2": [57, 93], "t3": 57, "t4": 57, "tabl": [56, 71, 92], "tb": 55, "tbuf": 82, "tclkpad": 91, "term": [14, 15, 16, 36, 91, 151, 163], "termin": [55, 91, 100], "testmod": [62, 128], "tile": [17, 38, 42, 43, 47, 55, 61, 68, 83, 91, 107, 152], "timer": [62, 114, 128], "tl": [52, 76, 147], "todo": [1, 12, 13, 14, 35, 36, 38, 39, 40, 41, 43, 46, 47, 48, 49, 50, 51, 52, 53, 54, 56, 57, 58, 60, 62, 63, 64, 65, 66, 67, 69, 71, 75, 78, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 98, 100, 101, 104, 105, 106, 107, 111, 112, 113, 114, 117, 118, 119, 120, 121, 126, 127, 128, 131, 132, 133, 134, 138, 140, 141, 142, 143, 148, 162, 163], "top": [17, 38, 47, 61, 72, 77, 83, 91, 152], "tr": [52, 76, 147], "transceiv": [66, 88, 89, 105, 118, 119, 132, 140], "trim": 128, "tristat": 82, "uim": [15, 23, 36], "ul": [40, 50, 85], "uni": 47, "univers": 163, "unk1c": 128, "up": 36, "upper": [40, 50, 63, 85], "ur": [40, 50, 85], "v": 79, "v2": [83, 85, 86, 91, 93], "v2p": [83, 85, 86, 91, 93], "v2px": 83, "valu": [45, 89], "ve": 79, "vertic": 58, "virtex": [46, 78, 79, 81, 85, 88, 89, 90, 93, 106, 120, 133, 141], "w": 91, "wide": [46, 82], "wire": 15, "without": [2, 3, 6, 7, 151], "write": 35, "x": [46, 82, 89], "xa2c128": 2, "xa2c256": 3, "xa2c32a": 5, "xa2c384": 6, "xa2c64a": 9, "xa95144xl": 20, "xa9536xl": 27, "xa9572xl": 30, "xc2c128": 2, "xc2c256": 3, "xc2c32": 4, "xc2c32a": 5, "xc2c384": 6, "xc2c512": 7, "xc2c64": 8, "xc2c64a": 9, "xc5200": 148, "xc9500": [15, 33, 35, 36], "xc9500xl": [16, 33, 35, 36], "xc9500xv": 33, "xc95108": 18, "xc95144": 19, "xc95144xl": 20, "xc95144xv": 21, "xc95216": 22, "xc95288": 23, "xc95288xl": 24, "xc95288xv": 25, "xc9536": 26, "xc9536xl": 27, "xc9536xv": 28, "xc9572": 29, "xc9572xl": 30, "xc9572xv": 31, "xcr3032xl": 153, "xcr3064xl": 154, "xcr3128xl": 155, "xcr3256xl": 156, "xcr3384xl": 157, "xcr3512xl": 158, "xilinx": [11, 33, 44, 160], "xor": [14, 36], "xpla3": 160, "xv": [16, 35, 36], "zia": 163}})
\ No newline at end of file
diff --git a/xilinx/index.html b/xilinx/index.html
index ceb1de3b..51cd7330 100644
--- a/xilinx/index.html
+++ b/xilinx/index.html
@@ -209,6 +209,7 @@ <h1>Xilinx FPGAs<a class="headerlink" href="#xilinx-fpgas" title="Link to this h
 <li class="toctree-l2"><a class="reference internal" href="virtex6/center.html">Configuration Center</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex6/emac.html">Ethernet MACs</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex6/pcie.html">PCI Express cores</a></li>
+<li class="toctree-l2"><a class="reference internal" href="virtex6/gtx.html">GTX transceivers</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex6/config.html">Configuration registers</a></li>
 </ul>
 </li>
diff --git a/xilinx/spartan3/corner.html b/xilinx/spartan3/corner.html
index 5b8c13fb..6a65ac97 100644
--- a/xilinx/spartan3/corner.html
+++ b/xilinx/spartan3/corner.html
@@ -176,9 +176,9 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.S3</span></c
 <tr><td>22</td>
 <td>-</td><td>-</td></tr>
 <tr><td>23</td>
-<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[11]">DCI0:LVDSBIAS[11]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td><td>-</td></tr>
 <tr><td>24</td>
-<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[12]">DCI0:LVDSBIAS[12]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td><td>-</td></tr>
 <tr><td>25</td>
 <td><a href="#bits-xc3s-LL.S3-MISC:M1PIN" title="MISC:M1PIN[1]">MISC:M1PIN[1]</a></td><td>-</td></tr>
 <tr><td>26</td>
@@ -192,63 +192,63 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.S3</span></c
 <tr><td>30</td>
 <td><a href="#bits-xc3s-LL.S3-MISC:M2PIN" title="MISC:M2PIN[0]">MISC:M2PIN[0]</a></td><td>-</td></tr>
 <tr><td>31</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[11]">DCI1:LVDSBIAS[11]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td></tr>
 <tr><td>32</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[12]">DCI1:LVDSBIAS[12]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td></tr>
 <tr><td>33</td>
-<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[12]">DCI0:LVDSBIAS[12]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[12]">DCI1:LVDSBIAS[12]</a></td></tr>
 <tr><td>34</td>
-<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[11]">DCI0:LVDSBIAS[11]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[11]">DCI1:LVDSBIAS[11]</a></td></tr>
 <tr><td>35</td>
-<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[10]">DCI0:LVDSBIAS[10]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[10]">DCI1:LVDSBIAS[10]</a></td></tr>
 <tr><td>36</td>
-<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[9]">DCI0:LVDSBIAS[9]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[9]">DCI1:LVDSBIAS[9]</a></td></tr>
 <tr><td>37</td>
-<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td></tr>
 <tr><td>38</td>
-<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td></tr>
 <tr><td>39</td>
 <td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[6]">DCI0:LVDSBIAS[6]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[6]">DCI1:LVDSBIAS[6]</a></td></tr>
 <tr><td>40</td>
-<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td></tr>
 <tr><td>41</td>
-<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td></tr>
 <tr><td>42</td>
-<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[9]">DCI0:LVDSBIAS[9]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[9]">DCI1:LVDSBIAS[9]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td></tr>
 <tr><td>43</td>
-<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[10]">DCI0:LVDSBIAS[10]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[10]">DCI1:LVDSBIAS[10]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td><td><a href="#bits-xc3s-LL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td></tr>
 <tr><td>44</td>
 <td><a href="#bits-xc3s-LL.S3-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:ENABLE" title="DCI0:ENABLE">DCI0:ENABLE</a></td></tr>
 <tr><td>45</td>
 <td><a href="#bits-xc3s-LL.S3-DCI1:QUIET" title="DCI1:QUIET">DCI1:QUIET</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:QUIET" title="DCI0:QUIET">DCI0:QUIET</a></td></tr>
 <tr><td>46</td>
-<td><a href="#bits-xc3s-LL.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[2]">DCI1:TERM_SPLIT[2]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[2]">DCI0:TERM_SPLIT[2]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[0]">DCI1:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[0]">DCI0:NMASK_TERM_SPLIT[0]</a></td></tr>
 <tr><td>47</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[1]">DCI1:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[1]">DCI0:NMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>48</td>
-<td><a href="#bits-xc3s-LL.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[0]">DCI1:TERM_SPLIT[0]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[0]">DCI0:TERM_SPLIT[0]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[2]">DCI1:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[2]">DCI0:NMASK_TERM_SPLIT[2]</a></td></tr>
 <tr><td>49</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[3]">DCI1:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[3]">DCI0:NMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>50</td>
 <td>-</td><td><a href="#bits-xc3s-LL.S3-MISC:DCI_TEST_MUX" title="MISC:DCI_TEST_MUX">MISC:DCI_TEST_MUX</a></td></tr>
 <tr><td>51</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[0]">DCI1:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[0]">DCI0:PMASK_TERM_VCC[0]</a></td></tr>
 <tr><td>52</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[1]">DCI1:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[1]">DCI0:PMASK_TERM_VCC[1]</a></td></tr>
 <tr><td>53</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[2]">DCI1:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[2]">DCI0:PMASK_TERM_VCC[2]</a></td></tr>
 <tr><td>54</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[3]">DCI1:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[3]">DCI0:PMASK_TERM_VCC[3]</a></td></tr>
 <tr><td>55</td>
 <td>-</td><td>-</td></tr>
 <tr><td>56</td>
-<td><a href="#bits-xc3s-LL.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[1]">DCI1:TERM_SPLIT[1]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[1]">DCI0:TERM_SPLIT[1]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[0]">DCI1:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[0]">DCI0:PMASK_TERM_SPLIT[0]</a></td></tr>
 <tr><td>57</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[1]">DCI1:PMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[1]">DCI0:PMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>58</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[2]">DCI1:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[2]">DCI0:PMASK_TERM_SPLIT[2]</a></td></tr>
 <tr><td>59</td>
-<td><a href="#bits-xc3s-LL.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[3]">DCI1:TERM_SPLIT[3]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[3]">DCI0:TERM_SPLIT[3]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[3]">DCI1:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc3s-LL.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[3]">DCI0:PMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>60</td>
 <td>-</td><td>-</td></tr>
 <tr><td>61</td>
@@ -258,12 +258,12 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.S3</span></c
 <tr><td>63</td>
 <td><a href="#bits-xc3s-LL.S3-DCIRESET1:ENABLE" title="DCIRESET1:ENABLE">DCIRESET1:ENABLE</a></td><td><a href="#bits-xc3s-LL.S3-DCIRESET0:ENABLE" title="DCIRESET0:ENABLE">DCIRESET0:ENABLE</a></td></tr>
 </table>
-<div id="bits-xc3s-LL.S3-DCI0:TERM_VCC"></div>
-<div id="bits-xc3s-LL.S3-DCI1:TERM_VCC"></div>
+<div id="bits-xc3s-LL.S3-DCI0:LVDSBIAS"></div>
+<div id="bits-xc3s-LL.S3-DCI1:LVDSBIAS"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_VCC</th></tr>
-<tr><th>DCI1:TERM_VCC</th></tr>
-<tr><td>Non-inverted</td></tr>
+<tr><th>DCI0:LVDSBIAS</th><th>[0, 0, 33]</th><th>[0, 0, 34]</th><th>[0, 0, 35]</th><th>[0, 0, 36]</th><th>[0, 0, 37]</th><th>[0, 0, 38]</th><th>[0, 0, 39]</th><th>[0, 0, 40]</th><th>[0, 0, 41]</th><th>[0, 0, 42]</th><th>[0, 0, 43]</th><th>[0, 0, 23]</th><th>[0, 0, 24]</th></tr>
+<tr><th>DCI1:LVDSBIAS</th><th>[0, 1, 33]</th><th>[0, 1, 34]</th><th>[0, 1, 35]</th><th>[0, 1, 36]</th><th>[0, 1, 37]</th><th>[0, 1, 38]</th><th>[0, 1, 39]</th><th>[0, 1, 40]</th><th>[0, 1, 41]</th><th>[0, 1, 42]</th><th>[0, 1, 43]</th><th>[0, 1, 31]</th><th>[0, 1, 32]</th></tr>
+<tr><td>Non-inverted</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc3s-LL.S3-MISC:M0PIN"></div>
 <div id="bits-xc3s-LL.S3-MISC:M1PIN"></div>
@@ -276,13 +276,6 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.S3</span></c
 <tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
 <tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
 </table>
-<div id="bits-xc3s-LL.S3-DCI0:LVDSBIAS"></div>
-<div id="bits-xc3s-LL.S3-DCI1:LVDSBIAS"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:LVDSBIAS</th><th>[0, 0, 24]</th><th>[0, 0, 23]</th><th>[0, 0, 43]</th><th>[0, 0, 42]</th><th>[0, 0, 41]</th><th>[0, 0, 40]</th><th>[0, 0, 39]</th><th>[0, 0, 38]</th><th>[0, 0, 37]</th><th>[0, 0, 36]</th><th>[0, 0, 35]</th><th>[0, 0, 34]</th><th>[0, 0, 33]</th></tr>
-<tr><th>DCI1:LVDSBIAS</th><th>[0, 1, 32]</th><th>[0, 1, 31]</th><th>[0, 1, 43]</th><th>[0, 1, 42]</th><th>[0, 1, 41]</th><th>[0, 1, 40]</th><th>[0, 1, 39]</th><th>[0, 1, 38]</th><th>[0, 1, 37]</th><th>[0, 1, 36]</th><th>[0, 1, 35]</th><th>[0, 1, 34]</th><th>[0, 1, 33]</th></tr>
-<tr><td>Non-inverted</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
-</table>
 <div id="bits-xc3s-LL.S3-DCI0:ENABLE"></div>
 <div id="bits-xc3s-LL.S3-DCI0:FORCE_DONE_HIGH"></div>
 <div id="bits-xc3s-LL.S3-DCI0:QUIET"></div>
@@ -316,12 +309,20 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.S3</span></c
 <tr><th>MISC:VGG_SENDMAX</th><th>[0, 1, 12]</th></tr>
 <tr><td>Non-inverted</td><td>[0]</td></tr>
 </table>
-<div id="bits-xc3s-LL.S3-DCI0:TERM_SPLIT"></div>
-<div id="bits-xc3s-LL.S3-DCI1:TERM_SPLIT"></div>
+<div id="bits-xc3s-LL.S3-DCI0:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-LL.S3-DCI0:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-LL.S3-DCI0:PMASK_TERM_VCC"></div>
+<div id="bits-xc3s-LL.S3-DCI1:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-LL.S3-DCI1:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-LL.S3-DCI1:PMASK_TERM_VCC"></div>
 <div id="bits-xc3s-LL.S3-MISC:SEND_VGG"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_SPLIT</th><th>[0, 1, 59]</th><th>[0, 1, 46]</th><th>[0, 1, 56]</th><th>[0, 1, 48]</th></tr>
-<tr><th>DCI1:TERM_SPLIT</th><th>[0, 0, 59]</th><th>[0, 0, 46]</th><th>[0, 0, 56]</th><th>[0, 0, 48]</th></tr>
+<tr><th>DCI0:NMASK_TERM_SPLIT</th><th>[0, 1, 49]</th><th>[0, 1, 48]</th><th>[0, 1, 47]</th><th>[0, 1, 46]</th></tr>
+<tr><th>DCI0:PMASK_TERM_SPLIT</th><th>[0, 1, 59]</th><th>[0, 1, 58]</th><th>[0, 1, 57]</th><th>[0, 1, 56]</th></tr>
+<tr><th>DCI0:PMASK_TERM_VCC</th><th>[0, 1, 54]</th><th>[0, 1, 53]</th><th>[0, 1, 52]</th><th>[0, 1, 51]</th></tr>
+<tr><th>DCI1:NMASK_TERM_SPLIT</th><th>[0, 0, 49]</th><th>[0, 0, 48]</th><th>[0, 0, 47]</th><th>[0, 0, 46]</th></tr>
+<tr><th>DCI1:PMASK_TERM_SPLIT</th><th>[0, 0, 59]</th><th>[0, 0, 58]</th><th>[0, 0, 57]</th><th>[0, 0, 56]</th></tr>
+<tr><th>DCI1:PMASK_TERM_VCC</th><th>[0, 0, 54]</th><th>[0, 0, 53]</th><th>[0, 0, 52]</th><th>[0, 0, 51]</th></tr>
 <tr><th>MISC:SEND_VGG</th><th>[0, 1, 11]</th><th>[0, 1, 10]</th><th>[0, 1, 9]</th><th>[0, 1, 8]</th></tr>
 <tr><td>Non-inverted</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
@@ -387,49 +388,49 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.S3E</span></
 <tr><td>21</td>
 <td>-</td><td><a href="#bits-xc3s-LL.S3E-MISC:TEMPSENSOR" title="MISC:TEMPSENSOR[0]">MISC:TEMPSENSOR[0]</a></td></tr>
 <tr><td>22</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[7]">BANK:LVDSBIAS_1[7]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[5]">BANK:LVDSBIAS_1[5]</a></td></tr>
 <tr><td>23</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[3]">BANK:LVDSBIAS_0[3]</a></td></tr>
-<tr><td>24</td>
 <td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[4]">BANK:LVDSBIAS_0[4]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[3]">BANK:LVDSBIAS_0[3]</a></td></tr>
 <tr><td>25</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3E-MISC:UNK_ALWAYS_SET" title="MISC:UNK_ALWAYS_SET[0]">MISC:UNK_ALWAYS_SET[0]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[2]">BANK:LVDSBIAS_0[2]</a></td></tr>
 <tr><td>26</td>
-<td>-</td><td>-</td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[1]">BANK:LVDSBIAS_0[1]</a></td></tr>
 <tr><td>27</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[3]">BANK:LVDSBIAS_1[3]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[4]">BANK:LVDSBIAS_1[4]</a></td></tr>
 <tr><td>28</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[5]">BANK:LVDSBIAS_1[5]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[3]">BANK:LVDSBIAS_1[3]</a></td></tr>
 <tr><td>29</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3E-MISC:UNK_ALWAYS_SET" title="MISC:UNK_ALWAYS_SET[1]">MISC:UNK_ALWAYS_SET[1]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[2]">BANK:LVDSBIAS_1[2]</a></td></tr>
 <tr><td>30</td>
-<td>-</td><td>-</td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[1]">BANK:LVDSBIAS_1[1]</a></td></tr>
 <tr><td>31</td>
 <td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[0]">BANK:LVDSBIAS_0[0]</a></td></tr>
 <tr><td>32</td>
 <td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[0]">BANK:LVDSBIAS_1[0]</a></td></tr>
 <tr><td>33</td>
-<td>-</td><td>-</td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[10]">BANK:LVDSBIAS_0[10]</a></td></tr>
 <tr><td>34</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[5]">BANK:LVDSBIAS_0[5]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[9]">BANK:LVDSBIAS_0[9]</a></td></tr>
 <tr><td>35</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[6]">BANK:LVDSBIAS_0[6]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[8]">BANK:LVDSBIAS_0[8]</a></td></tr>
 <tr><td>36</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[1]">BANK:LVDSBIAS_0[1]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[7]">BANK:LVDSBIAS_0[7]</a></td></tr>
 <tr><td>37</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[2]">BANK:LVDSBIAS_0[2]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[6]">BANK:LVDSBIAS_0[6]</a></td></tr>
 <tr><td>38</td>
-<td>-</td><td>-</td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[5]">BANK:LVDSBIAS_0[5]</a></td></tr>
 <tr><td>39</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[8]">BANK:LVDSBIAS_1[8]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[10]">BANK:LVDSBIAS_1[10]</a></td></tr>
 <tr><td>40</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[4]">BANK:LVDSBIAS_1[4]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[9]">BANK:LVDSBIAS_1[9]</a></td></tr>
 <tr><td>41</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[6]">BANK:LVDSBIAS_1[6]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[8]">BANK:LVDSBIAS_1[8]</a></td></tr>
 <tr><td>42</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[1]">BANK:LVDSBIAS_1[1]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[7]">BANK:LVDSBIAS_1[7]</a></td></tr>
 <tr><td>43</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[2]">BANK:LVDSBIAS_1[2]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[6]">BANK:LVDSBIAS_1[6]</a></td></tr>
 </table>
 <div id="bits-xc3s-LL.S3E-MISC:SEND_VGG"></div>
 <table class="docutils align-default prjcombine-enum">
@@ -452,20 +453,12 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.S3E</span></
 <tr><td>BG</td><td>1</td><td>0</td><td>1</td></tr>
 <tr><td>CGATE</td><td>1</td><td>1</td><td>1</td></tr>
 </table>
-<div id="bits-xc3s-LL.S3E-MISC:UNK_ALWAYS_SET"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>MISC:UNK_ALWAYS_SET</th><th>[0, 1, 29]</th><th>[0, 1, 25]</th></tr>
-<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
-</table>
 <div id="bits-xc3s-LL.S3E-BANK:LVDSBIAS_0"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>BANK:LVDSBIAS_0</th><th>[0, 1, 35]</th><th>[0, 1, 34]</th><th>[0, 1, 24]</th><th>[0, 1, 23]</th><th>[0, 1, 37]</th><th>[0, 1, 36]</th><th>[0, 1, 31]</th></tr>
-<tr><td>Non-inverted</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
-</table>
 <div id="bits-xc3s-LL.S3E-BANK:LVDSBIAS_1"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>BANK:LVDSBIAS_1</th><th>[0, 1, 39]</th><th>[0, 1, 22]</th><th>[0, 1, 41]</th><th>[0, 1, 28]</th><th>[0, 1, 40]</th><th>[0, 1, 27]</th><th>[0, 1, 43]</th><th>[0, 1, 42]</th><th>[0, 1, 32]</th></tr>
-<tr><td>Non-inverted</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>BANK:LVDSBIAS_0</th><th>[0, 1, 33]</th><th>[0, 1, 34]</th><th>[0, 1, 35]</th><th>[0, 1, 36]</th><th>[0, 1, 37]</th><th>[0, 1, 38]</th><th>[0, 1, 23]</th><th>[0, 1, 24]</th><th>[0, 1, 25]</th><th>[0, 1, 26]</th><th>[0, 1, 31]</th></tr>
+<tr><th>BANK:LVDSBIAS_1</th><th>[0, 1, 39]</th><th>[0, 1, 40]</th><th>[0, 1, 41]</th><th>[0, 1, 42]</th><th>[0, 1, 43]</th><th>[0, 1, 22]</th><th>[0, 1, 27]</th><th>[0, 1, 28]</th><th>[0, 1, 29]</th><th>[0, 1, 30]</th><th>[0, 1, 32]</th></tr>
+<tr><td>Non-inverted</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 </section>
 <section id="ll-s3a">
@@ -486,17 +479,17 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.S3A</span></
 <tr><td>5</td>
 <td>-</td><td>-</td></tr>
 <tr><td>6</td>
-<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[4]">BANK:LVDSBIAS_1[4]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[11]">BANK:LVDSBIAS_1[11]</a></td><td>-</td></tr>
 <tr><td>7</td>
 <td><a href="#bits-xc3s-LL.S3A-MISC:TEMPSENSOR" title="MISC:TEMPSENSOR[0]">MISC:TEMPSENSOR[0]</a></td><td><a href="#bits-xc3s-LL.S3A-MISC:TEMPSENSOR" title="MISC:TEMPSENSOR[1]">MISC:TEMPSENSOR[1]</a></td></tr>
 <tr><td>8</td>
 <td>-</td><td>-</td></tr>
 <tr><td>9</td>
-<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[4]">BANK:LVDSBIAS_0[4]</a></td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[5]">BANK:LVDSBIAS_1[5]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[11]">BANK:LVDSBIAS_0[11]</a></td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[7]">BANK:LVDSBIAS_1[7]</a></td></tr>
 <tr><td>10</td>
-<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[2]">BANK:LVDSBIAS_0[2]</a></td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[3]">BANK:LVDSBIAS_0[3]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[6]">BANK:LVDSBIAS_0[6]</a></td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[10]">BANK:LVDSBIAS_0[10]</a></td></tr>
 <tr><td>11</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[5]">BANK:LVDSBIAS_0[5]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[7]">BANK:LVDSBIAS_0[7]</a></td></tr>
 <tr><td>12</td>
 <td><a href="#bits-xc3s-LL.S3A-MISC:UNK_ALWAYS_SET" title="MISC:UNK_ALWAYS_SET[0]">MISC:UNK_ALWAYS_SET[0]</a></td><td><a href="#bits-xc3s-LL.S3A-MISC:UNK_ALWAYS_SET" title="MISC:UNK_ALWAYS_SET[2]">MISC:UNK_ALWAYS_SET[2]</a></td></tr>
 <tr><td>13</td>
@@ -526,27 +519,27 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.S3A</span></
 <tr><td>25</td>
 <td>-</td><td>-</td></tr>
 <tr><td>26</td>
-<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[8]">BANK:LVDSBIAS_1[8]</a></td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[10]">BANK:LVDSBIAS_1[10]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[2]">BANK:LVDSBIAS_1[2]</a></td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[3]">BANK:LVDSBIAS_1[3]</a></td></tr>
 <tr><td>27</td>
-<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[0]">BANK:LVDSBIAS_0[0]</a></td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[9]">BANK:LVDSBIAS_1[9]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[1]">BANK:LVDSBIAS_0[1]</a></td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[0]">BANK:LVDSBIAS_1[0]</a></td></tr>
 <tr><td>28</td>
-<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[0]">BANK:LVDSBIAS_1[0]</a></td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[1]">BANK:LVDSBIAS_0[1]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[1]">BANK:LVDSBIAS_1[1]</a></td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[5]">BANK:LVDSBIAS_0[5]</a></td></tr>
 <tr><td>29</td>
-<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[7]">BANK:LVDSBIAS_1[7]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[9]">BANK:LVDSBIAS_1[9]</a></td><td>-</td></tr>
 <tr><td>30</td>
-<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[2]">BANK:LVDSBIAS_1[2]</a></td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[10]">BANK:LVDSBIAS_0[10]</a></td></tr>
+<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[6]">BANK:LVDSBIAS_1[6]</a></td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[3]">BANK:LVDSBIAS_0[3]</a></td></tr>
 <tr><td>31</td>
-<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[8]">BANK:LVDSBIAS_0[8]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[2]">BANK:LVDSBIAS_0[2]</a></td><td>-</td></tr>
 <tr><td>32</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[9]">BANK:LVDSBIAS_0[9]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[0]">BANK:LVDSBIAS_0[0]</a></td></tr>
 <tr><td>33</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[7]">BANK:LVDSBIAS_0[7]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[9]">BANK:LVDSBIAS_0[9]</a></td></tr>
 <tr><td>34</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[6]">BANK:LVDSBIAS_0[6]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[8]">BANK:LVDSBIAS_0[8]</a></td></tr>
 <tr><td>35</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[6]">BANK:LVDSBIAS_1[6]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[8]">BANK:LVDSBIAS_1[8]</a></td></tr>
 <tr><td>36</td>
-<td>-</td><td>-</td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[4]">BANK:LVDSBIAS_0[4]</a></td></tr>
 <tr><td>37</td>
 <td>-</td><td>-</td></tr>
 <tr><td>38</td>
@@ -598,9 +591,9 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.S3A</span></
 <tr><td>61</td>
 <td>-</td><td>-</td></tr>
 <tr><td>62</td>
-<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[3]">BANK:LVDSBIAS_1[3]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[10]">BANK:LVDSBIAS_1[10]</a></td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[4]">BANK:LVDSBIAS_1[4]</a></td></tr>
 <tr><td>63</td>
-<td>-</td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[1]">BANK:LVDSBIAS_1[1]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[5]">BANK:LVDSBIAS_1[5]</a></td></tr>
 </table>
 <div id="bits-xc3s-LL.S3A-MISC:TEMPSENSOR"></div>
 <table class="docutils align-default prjcombine-enum">
@@ -627,13 +620,6 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.S3A</span></
 <tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
 <tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
 </table>
-<div id="bits-xc3s-LL.S3A-BANK:LVDSBIAS_0"></div>
-<div id="bits-xc3s-LL.S3A-BANK:LVDSBIAS_1"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>BANK:LVDSBIAS_0</th><th>[0, 1, 30]</th><th>[0, 1, 32]</th><th>[0, 0, 31]</th><th>[0, 1, 33]</th><th>[0, 1, 34]</th><th>[0, 1, 11]</th><th>[0, 0, 9]</th><th>[0, 1, 10]</th><th>[0, 0, 10]</th><th>[0, 1, 28]</th><th>[0, 0, 27]</th></tr>
-<tr><th>BANK:LVDSBIAS_1</th><th>[0, 1, 26]</th><th>[0, 1, 27]</th><th>[0, 0, 26]</th><th>[0, 0, 29]</th><th>[0, 1, 35]</th><th>[0, 1, 9]</th><th>[0, 0, 6]</th><th>[0, 0, 62]</th><th>[0, 0, 30]</th><th>[0, 1, 63]</th><th>[0, 0, 28]</th></tr>
-<tr><td>Non-inverted</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
-</table>
 <div id="bits-xc3s-LL.S3A-MISC:VGG_ENABLE_OFFCHIP"></div>
 <div id="bits-xc3s-LL.S3A-MISC:VGG_SENDMAX"></div>
 <table class="docutils align-default prjcombine-enum">
@@ -641,6 +627,13 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.S3A</span></
 <tr><th>MISC:VGG_SENDMAX</th><th>[0, 1, 22]</th></tr>
 <tr><td>Non-inverted</td><td>[0]</td></tr>
 </table>
+<div id="bits-xc3s-LL.S3A-BANK:LVDSBIAS_0"></div>
+<div id="bits-xc3s-LL.S3A-BANK:LVDSBIAS_1"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>BANK:LVDSBIAS_0</th><th>[0, 0, 9]</th><th>[0, 1, 10]</th><th>[0, 1, 33]</th><th>[0, 1, 34]</th><th>[0, 1, 11]</th><th>[0, 0, 10]</th><th>[0, 1, 28]</th><th>[0, 1, 36]</th><th>[0, 1, 30]</th><th>[0, 0, 31]</th><th>[0, 0, 27]</th><th>[0, 1, 32]</th></tr>
+<tr><th>BANK:LVDSBIAS_1</th><th>[0, 0, 6]</th><th>[0, 0, 62]</th><th>[0, 0, 29]</th><th>[0, 1, 35]</th><th>[0, 1, 9]</th><th>[0, 0, 30]</th><th>[0, 1, 63]</th><th>[0, 1, 62]</th><th>[0, 1, 26]</th><th>[0, 0, 26]</th><th>[0, 0, 28]</th><th>[0, 1, 27]</th></tr>
+<tr><td>Non-inverted</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
 </section>
 </section>
 <section id="upper-left">
@@ -713,67 +706,67 @@ <h3><code class="docutils literal notranslate"><span class="pre">UL.S3</span></c
 <tr><td>28</td>
 <td>-</td><td><a href="#bits-xc3s-UL.S3-MISC:TDIPIN" title="MISC:TDIPIN[0]">MISC:TDIPIN[0]</a></td></tr>
 <tr><td>29</td>
-<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[11]">DCI1:LVDSBIAS[11]</a></td><td><a href="#bits-xc3s-UL.S3-MISC:TDIPIN" title="MISC:TDIPIN[1]">MISC:TDIPIN[1]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td><td><a href="#bits-xc3s-UL.S3-MISC:TDIPIN" title="MISC:TDIPIN[1]">MISC:TDIPIN[1]</a></td></tr>
 <tr><td>30</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[11]">DCI0:LVDSBIAS[11]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td></tr>
 <tr><td>31</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[12]">DCI0:LVDSBIAS[12]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
 <tr><td>32</td>
-<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[12]">DCI1:LVDSBIAS[12]</a></td><td><a href="#bits-xc3s-UL.S3-MISC:TEST_LL" title="MISC:TEST_LL">MISC:TEST_LL</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td><td><a href="#bits-xc3s-UL.S3-MISC:TEST_LL" title="MISC:TEST_LL">MISC:TEST_LL</a></td></tr>
 <tr><td>33</td>
-<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[12]">DCI1:LVDSBIAS[12]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[12]">DCI0:LVDSBIAS[12]</a></td></tr>
 <tr><td>34</td>
-<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[11]">DCI1:LVDSBIAS[11]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[11]">DCI0:LVDSBIAS[11]</a></td></tr>
 <tr><td>35</td>
-<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[10]">DCI1:LVDSBIAS[10]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[10]">DCI0:LVDSBIAS[10]</a></td></tr>
 <tr><td>36</td>
-<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[9]">DCI1:LVDSBIAS[9]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[9]">DCI0:LVDSBIAS[9]</a></td></tr>
 <tr><td>37</td>
-<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td></tr>
 <tr><td>38</td>
-<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td></tr>
 <tr><td>39</td>
 <td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[6]">DCI1:LVDSBIAS[6]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[6]">DCI0:LVDSBIAS[6]</a></td></tr>
 <tr><td>40</td>
-<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td></tr>
 <tr><td>41</td>
-<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td></tr>
 <tr><td>42</td>
-<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[9]">DCI1:LVDSBIAS[9]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[9]">DCI0:LVDSBIAS[9]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td></tr>
 <tr><td>43</td>
-<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[10]">DCI1:LVDSBIAS[10]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[10]">DCI0:LVDSBIAS[10]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td><td><a href="#bits-xc3s-UL.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
 <tr><td>44</td>
 <td><a href="#bits-xc3s-UL.S3-DCI0:ENABLE" title="DCI0:ENABLE">DCI0:ENABLE</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td></tr>
 <tr><td>45</td>
 <td><a href="#bits-xc3s-UL.S3-DCI0:QUIET" title="DCI0:QUIET">DCI0:QUIET</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:QUIET" title="DCI1:QUIET">DCI1:QUIET</a></td></tr>
 <tr><td>46</td>
-<td><a href="#bits-xc3s-UL.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[2]">DCI0:TERM_SPLIT[2]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[2]">DCI1:TERM_SPLIT[2]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[0]">DCI0:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[0]">DCI1:NMASK_TERM_SPLIT[0]</a></td></tr>
 <tr><td>47</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[1]">DCI0:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[1]">DCI1:NMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>48</td>
-<td><a href="#bits-xc3s-UL.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[0]">DCI0:TERM_SPLIT[0]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[0]">DCI1:TERM_SPLIT[0]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[2]">DCI0:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[2]">DCI1:NMASK_TERM_SPLIT[2]</a></td></tr>
 <tr><td>49</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[3]">DCI0:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[3]">DCI1:NMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>50</td>
 <td><a href="#bits-xc3s-UL.S3-MISC:DCI_TEST_MUX" title="MISC:DCI_TEST_MUX">MISC:DCI_TEST_MUX</a></td><td>-</td></tr>
 <tr><td>51</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[0]">DCI0:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[0]">DCI1:PMASK_TERM_VCC[0]</a></td></tr>
 <tr><td>52</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[1]">DCI0:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[1]">DCI1:PMASK_TERM_VCC[1]</a></td></tr>
 <tr><td>53</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[2]">DCI0:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[2]">DCI1:PMASK_TERM_VCC[2]</a></td></tr>
 <tr><td>54</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[3]">DCI0:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[3]">DCI1:PMASK_TERM_VCC[3]</a></td></tr>
 <tr><td>55</td>
 <td>-</td><td>-</td></tr>
 <tr><td>56</td>
-<td><a href="#bits-xc3s-UL.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[1]">DCI0:TERM_SPLIT[1]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[1]">DCI1:TERM_SPLIT[1]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[0]">DCI0:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[0]">DCI1:PMASK_TERM_SPLIT[0]</a></td></tr>
 <tr><td>57</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[1]">DCI0:PMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[1]">DCI1:PMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>58</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[2]">DCI0:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[2]">DCI1:PMASK_TERM_SPLIT[2]</a></td></tr>
 <tr><td>59</td>
-<td><a href="#bits-xc3s-UL.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[3]">DCI0:TERM_SPLIT[3]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[3]">DCI1:TERM_SPLIT[3]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[3]">DCI0:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc3s-UL.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[3]">DCI1:PMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>60</td>
 <td>-</td><td>-</td></tr>
 <tr><td>61</td>
@@ -783,13 +776,6 @@ <h3><code class="docutils literal notranslate"><span class="pre">UL.S3</span></c
 <tr><td>63</td>
 <td><a href="#bits-xc3s-UL.S3-DCIRESET0:ENABLE" title="DCIRESET0:ENABLE">DCIRESET0:ENABLE</a></td><td><a href="#bits-xc3s-UL.S3-DCIRESET1:ENABLE" title="DCIRESET1:ENABLE">DCIRESET1:ENABLE</a></td></tr>
 </table>
-<div id="bits-xc3s-UL.S3-DCI0:TERM_VCC"></div>
-<div id="bits-xc3s-UL.S3-DCI1:TERM_VCC"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_VCC</th></tr>
-<tr><th>DCI1:TERM_VCC</th></tr>
-<tr><td>Non-inverted</td></tr>
-</table>
 <div id="bits-xc3s-UL.S3-DCI0:ENABLE"></div>
 <div id="bits-xc3s-UL.S3-DCI0:FORCE_DONE_HIGH"></div>
 <div id="bits-xc3s-UL.S3-DCI0:QUIET"></div>
@@ -820,15 +806,23 @@ <h3><code class="docutils literal notranslate"><span class="pre">UL.S3</span></c
 <div id="bits-xc3s-UL.S3-DCI0:LVDSBIAS"></div>
 <div id="bits-xc3s-UL.S3-DCI1:LVDSBIAS"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:LVDSBIAS</th><th>[0, 1, 31]</th><th>[0, 1, 30]</th><th>[0, 1, 43]</th><th>[0, 1, 42]</th><th>[0, 1, 41]</th><th>[0, 1, 40]</th><th>[0, 1, 39]</th><th>[0, 1, 38]</th><th>[0, 1, 37]</th><th>[0, 1, 36]</th><th>[0, 1, 35]</th><th>[0, 1, 34]</th><th>[0, 1, 33]</th></tr>
-<tr><th>DCI1:LVDSBIAS</th><th>[0, 0, 32]</th><th>[0, 0, 29]</th><th>[0, 0, 43]</th><th>[0, 0, 42]</th><th>[0, 0, 41]</th><th>[0, 0, 40]</th><th>[0, 0, 39]</th><th>[0, 0, 38]</th><th>[0, 0, 37]</th><th>[0, 0, 36]</th><th>[0, 0, 35]</th><th>[0, 0, 34]</th><th>[0, 0, 33]</th></tr>
+<tr><th>DCI0:LVDSBIAS</th><th>[0, 1, 33]</th><th>[0, 1, 34]</th><th>[0, 1, 35]</th><th>[0, 1, 36]</th><th>[0, 1, 37]</th><th>[0, 1, 38]</th><th>[0, 1, 39]</th><th>[0, 1, 40]</th><th>[0, 1, 41]</th><th>[0, 1, 42]</th><th>[0, 1, 43]</th><th>[0, 1, 30]</th><th>[0, 1, 31]</th></tr>
+<tr><th>DCI1:LVDSBIAS</th><th>[0, 0, 33]</th><th>[0, 0, 34]</th><th>[0, 0, 35]</th><th>[0, 0, 36]</th><th>[0, 0, 37]</th><th>[0, 0, 38]</th><th>[0, 0, 39]</th><th>[0, 0, 40]</th><th>[0, 0, 41]</th><th>[0, 0, 42]</th><th>[0, 0, 43]</th><th>[0, 0, 29]</th><th>[0, 0, 32]</th></tr>
 <tr><td>Non-inverted</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
-<div id="bits-xc3s-UL.S3-DCI0:TERM_SPLIT"></div>
-<div id="bits-xc3s-UL.S3-DCI1:TERM_SPLIT"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_SPLIT</th><th>[0, 0, 59]</th><th>[0, 0, 46]</th><th>[0, 0, 56]</th><th>[0, 0, 48]</th></tr>
-<tr><th>DCI1:TERM_SPLIT</th><th>[0, 1, 59]</th><th>[0, 1, 46]</th><th>[0, 1, 56]</th><th>[0, 1, 48]</th></tr>
+<div id="bits-xc3s-UL.S3-DCI0:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-UL.S3-DCI0:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-UL.S3-DCI0:PMASK_TERM_VCC"></div>
+<div id="bits-xc3s-UL.S3-DCI1:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-UL.S3-DCI1:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-UL.S3-DCI1:PMASK_TERM_VCC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI0:NMASK_TERM_SPLIT</th><th>[0, 0, 49]</th><th>[0, 0, 48]</th><th>[0, 0, 47]</th><th>[0, 0, 46]</th></tr>
+<tr><th>DCI0:PMASK_TERM_SPLIT</th><th>[0, 0, 59]</th><th>[0, 0, 58]</th><th>[0, 0, 57]</th><th>[0, 0, 56]</th></tr>
+<tr><th>DCI0:PMASK_TERM_VCC</th><th>[0, 0, 54]</th><th>[0, 0, 53]</th><th>[0, 0, 52]</th><th>[0, 0, 51]</th></tr>
+<tr><th>DCI1:NMASK_TERM_SPLIT</th><th>[0, 1, 49]</th><th>[0, 1, 48]</th><th>[0, 1, 47]</th><th>[0, 1, 46]</th></tr>
+<tr><th>DCI1:PMASK_TERM_SPLIT</th><th>[0, 1, 59]</th><th>[0, 1, 58]</th><th>[0, 1, 57]</th><th>[0, 1, 56]</th></tr>
+<tr><th>DCI1:PMASK_TERM_VCC</th><th>[0, 1, 54]</th><th>[0, 1, 53]</th><th>[0, 1, 52]</th><th>[0, 1, 51]</th></tr>
 <tr><td>Non-inverted</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc3s-UL.S3-MISC:DCI_TEST_MUX"></div>
@@ -903,68 +897,60 @@ <h3><code class="docutils literal notranslate"><span class="pre">UL.S3E</span></
 <tr><td>21</td>
 <td>-</td><td>-</td></tr>
 <tr><td>22</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[10]">BANK:LVDSBIAS_0[10]</a></td><td>-</td></tr>
 <tr><td>23</td>
-<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[4]">BANK:LVDSBIAS_0[4]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[9]">BANK:LVDSBIAS_0[9]</a></td><td>-</td></tr>
 <tr><td>24</td>
-<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[5]">BANK:LVDSBIAS_0[5]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[8]">BANK:LVDSBIAS_0[8]</a></td><td>-</td></tr>
 <tr><td>25</td>
-<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[0]">BANK:LVDSBIAS_0[0]</a></td><td><a href="#bits-xc3s-UL.S3E-MISC:PROGPIN" title="MISC:PROGPIN">MISC:PROGPIN</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[7]">BANK:LVDSBIAS_0[7]</a></td><td><a href="#bits-xc3s-UL.S3E-MISC:PROGPIN" title="MISC:PROGPIN">MISC:PROGPIN</a></td></tr>
 <tr><td>26</td>
-<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[1]">BANK:LVDSBIAS_0[1]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[6]">BANK:LVDSBIAS_0[6]</a></td><td>-</td></tr>
 <tr><td>27</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[5]">BANK:LVDSBIAS_0[5]</a></td><td>-</td></tr>
 <tr><td>28</td>
-<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[7]">BANK:LVDSBIAS_1[7]</a></td><td><a href="#bits-xc3s-UL.S3E-MISC:TDIPIN" title="MISC:TDIPIN[0]">MISC:TDIPIN[0]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[10]">BANK:LVDSBIAS_1[10]</a></td><td><a href="#bits-xc3s-UL.S3E-MISC:TDIPIN" title="MISC:TDIPIN[0]">MISC:TDIPIN[0]</a></td></tr>
 <tr><td>29</td>
-<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[4]">BANK:LVDSBIAS_1[4]</a></td><td><a href="#bits-xc3s-UL.S3E-MISC:TDIPIN" title="MISC:TDIPIN[1]">MISC:TDIPIN[1]</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[9]">BANK:LVDSBIAS_1[9]</a></td><td><a href="#bits-xc3s-UL.S3E-MISC:TDIPIN" title="MISC:TDIPIN[1]">MISC:TDIPIN[1]</a></td></tr>
 <tr><td>30</td>
 <td>-</td><td>-</td></tr>
 <tr><td>31</td>
 <td>-</td><td>-</td></tr>
 <tr><td>32</td>
-<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[5]">BANK:LVDSBIAS_1[5]</a></td><td><a href="#bits-xc3s-UL.S3E-MISC:TEST_LL" title="MISC:TEST_LL">MISC:TEST_LL</a></td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[8]">BANK:LVDSBIAS_1[8]</a></td><td><a href="#bits-xc3s-UL.S3E-MISC:TEST_LL" title="MISC:TEST_LL">MISC:TEST_LL</a></td></tr>
 <tr><td>33</td>
-<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[1]">BANK:LVDSBIAS_1[1]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[7]">BANK:LVDSBIAS_1[7]</a></td><td>-</td></tr>
 <tr><td>34</td>
-<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[2]">BANK:LVDSBIAS_1[2]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[6]">BANK:LVDSBIAS_1[6]</a></td><td>-</td></tr>
 <tr><td>35</td>
-<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[8]">BANK:LVDSBIAS_1[8]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[5]">BANK:LVDSBIAS_1[5]</a></td><td>-</td></tr>
 <tr><td>36</td>
-<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[3]">BANK:LVDSBIAS_0[3]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[4]">BANK:LVDSBIAS_0[4]</a></td><td>-</td></tr>
 <tr><td>37</td>
-<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[6]">BANK:LVDSBIAS_0[6]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[3]">BANK:LVDSBIAS_0[3]</a></td><td>-</td></tr>
 <tr><td>38</td>
-<td><a href="#bits-xc3s-UL.S3E-MISC:UNK_ALWAYS_SET" title="MISC:UNK_ALWAYS_SET[0]">MISC:UNK_ALWAYS_SET[0]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[2]">BANK:LVDSBIAS_0[2]</a></td><td>-</td></tr>
 <tr><td>39</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[1]">BANK:LVDSBIAS_0[1]</a></td><td>-</td></tr>
 <tr><td>40</td>
-<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[3]">BANK:LVDSBIAS_1[3]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[4]">BANK:LVDSBIAS_1[4]</a></td><td>-</td></tr>
 <tr><td>41</td>
-<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[6]">BANK:LVDSBIAS_1[6]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[3]">BANK:LVDSBIAS_1[3]</a></td><td>-</td></tr>
 <tr><td>42</td>
-<td><a href="#bits-xc3s-UL.S3E-MISC:UNK_ALWAYS_SET" title="MISC:UNK_ALWAYS_SET[1]">MISC:UNK_ALWAYS_SET[1]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[2]">BANK:LVDSBIAS_1[2]</a></td><td>-</td></tr>
 <tr><td>43</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[1]">BANK:LVDSBIAS_1[1]</a></td><td>-</td></tr>
 <tr><td>44</td>
-<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[2]">BANK:LVDSBIAS_0[2]</a></td><td>-</td></tr>
+<td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[0]">BANK:LVDSBIAS_0[0]</a></td><td>-</td></tr>
 <tr><td>45</td>
 <td><a href="#bits-xc3s-UL.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[0]">BANK:LVDSBIAS_1[0]</a></td><td>-</td></tr>
 </table>
 <div id="bits-xc3s-UL.S3E-BANK:LVDSBIAS_0"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>BANK:LVDSBIAS_0</th><th>[0, 0, 37]</th><th>[0, 0, 24]</th><th>[0, 0, 23]</th><th>[0, 0, 36]</th><th>[0, 0, 44]</th><th>[0, 0, 26]</th><th>[0, 0, 25]</th></tr>
-<tr><td>Non-inverted</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
-</table>
-<div id="bits-xc3s-UL.S3E-MISC:UNK_ALWAYS_SET"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>MISC:UNK_ALWAYS_SET</th><th>[0, 0, 42]</th><th>[0, 0, 38]</th></tr>
-<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
-</table>
 <div id="bits-xc3s-UL.S3E-BANK:LVDSBIAS_1"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>BANK:LVDSBIAS_1</th><th>[0, 0, 35]</th><th>[0, 0, 28]</th><th>[0, 0, 41]</th><th>[0, 0, 32]</th><th>[0, 0, 29]</th><th>[0, 0, 40]</th><th>[0, 0, 34]</th><th>[0, 0, 33]</th><th>[0, 0, 45]</th></tr>
-<tr><td>Non-inverted</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>BANK:LVDSBIAS_0</th><th>[0, 0, 22]</th><th>[0, 0, 23]</th><th>[0, 0, 24]</th><th>[0, 0, 25]</th><th>[0, 0, 26]</th><th>[0, 0, 27]</th><th>[0, 0, 36]</th><th>[0, 0, 37]</th><th>[0, 0, 38]</th><th>[0, 0, 39]</th><th>[0, 0, 44]</th></tr>
+<tr><th>BANK:LVDSBIAS_1</th><th>[0, 0, 28]</th><th>[0, 0, 29]</th><th>[0, 0, 32]</th><th>[0, 0, 33]</th><th>[0, 0, 34]</th><th>[0, 0, 35]</th><th>[0, 0, 40]</th><th>[0, 0, 41]</th><th>[0, 0, 42]</th><th>[0, 0, 43]</th><th>[0, 0, 45]</th></tr>
+<tr><td>Non-inverted</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc3s-UL.S3E-MISC:PROGPIN"></div>
 <table class="docutils align-default prjcombine-enum">
@@ -1071,53 +1057,53 @@ <h3><code class="docutils literal notranslate"><span class="pre">UL.S3A</span></
 <tr><td>39</td>
 <td>-</td><td>-</td></tr>
 <tr><td>40</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[4]">BANK:LVDSBIAS_0[4]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[11]">BANK:LVDSBIAS_0[11]</a></td></tr>
 <tr><td>41</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[3]">BANK:LVDSBIAS_0[3]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[10]">BANK:LVDSBIAS_0[10]</a></td></tr>
 <tr><td>42</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[7]">BANK:LVDSBIAS_0[7]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[9]">BANK:LVDSBIAS_0[9]</a></td></tr>
 <tr><td>43</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[5]">BANK:LVDSBIAS_0[5]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[8]">BANK:LVDSBIAS_0[8]</a></td></tr>
 <tr><td>44</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[6]">BANK:LVDSBIAS_0[6]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[7]">BANK:LVDSBIAS_0[7]</a></td></tr>
 <tr><td>45</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[2]">BANK:LVDSBIAS_0[2]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[6]">BANK:LVDSBIAS_0[6]</a></td></tr>
 <tr><td>46</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[4]">BANK:LVDSBIAS_1[4]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[11]">BANK:LVDSBIAS_1[11]</a></td></tr>
 <tr><td>47</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[3]">BANK:LVDSBIAS_1[3]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[10]">BANK:LVDSBIAS_1[10]</a></td></tr>
 <tr><td>48</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[7]">BANK:LVDSBIAS_1[7]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[9]">BANK:LVDSBIAS_1[9]</a></td></tr>
 <tr><td>49</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[5]">BANK:LVDSBIAS_1[5]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[8]">BANK:LVDSBIAS_1[8]</a></td></tr>
 <tr><td>50</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[6]">BANK:LVDSBIAS_1[6]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[7]">BANK:LVDSBIAS_1[7]</a></td></tr>
 <tr><td>51</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[2]">BANK:LVDSBIAS_1[2]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[6]">BANK:LVDSBIAS_1[6]</a></td></tr>
 <tr><td>52</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[1]">BANK:LVDSBIAS_0[1]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[5]">BANK:LVDSBIAS_0[5]</a></td></tr>
 <tr><td>53</td>
-<td>-</td><td>-</td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[4]">BANK:LVDSBIAS_0[4]</a></td></tr>
 <tr><td>54</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[10]">BANK:LVDSBIAS_0[10]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[3]">BANK:LVDSBIAS_0[3]</a></td></tr>
 <tr><td>55</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[8]">BANK:LVDSBIAS_0[8]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[2]">BANK:LVDSBIAS_0[2]</a></td></tr>
 <tr><td>56</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[1]">BANK:LVDSBIAS_1[1]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[5]">BANK:LVDSBIAS_1[5]</a></td></tr>
 <tr><td>57</td>
-<td>-</td><td>-</td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[4]">BANK:LVDSBIAS_1[4]</a></td></tr>
 <tr><td>58</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[10]">BANK:LVDSBIAS_1[10]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[3]">BANK:LVDSBIAS_1[3]</a></td></tr>
 <tr><td>59</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[8]">BANK:LVDSBIAS_1[8]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[2]">BANK:LVDSBIAS_1[2]</a></td></tr>
 <tr><td>60</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[0]">BANK:LVDSBIAS_0[0]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[1]">BANK:LVDSBIAS_0[1]</a></td></tr>
 <tr><td>61</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[0]">BANK:LVDSBIAS_1[0]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[1]">BANK:LVDSBIAS_1[1]</a></td></tr>
 <tr><td>62</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[9]">BANK:LVDSBIAS_0[9]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[0]">BANK:LVDSBIAS_0[0]</a></td></tr>
 <tr><td>63</td>
-<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[9]">BANK:LVDSBIAS_1[9]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[0]">BANK:LVDSBIAS_1[0]</a></td></tr>
 </table>
 <div id="bits-xc3s-UL.S3A-MISC:TDIPIN"></div>
 <div id="bits-xc3s-UL.S3A-MISC:TMSPIN"></div>
@@ -1142,9 +1128,9 @@ <h3><code class="docutils literal notranslate"><span class="pre">UL.S3A</span></
 <div id="bits-xc3s-UL.S3A-BANK:LVDSBIAS_0"></div>
 <div id="bits-xc3s-UL.S3A-BANK:LVDSBIAS_1"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>BANK:LVDSBIAS_0</th><th>[0, 1, 54]</th><th>[0, 1, 62]</th><th>[0, 1, 55]</th><th>[0, 1, 42]</th><th>[0, 1, 44]</th><th>[0, 1, 43]</th><th>[0, 1, 40]</th><th>[0, 1, 41]</th><th>[0, 1, 45]</th><th>[0, 1, 52]</th><th>[0, 1, 60]</th></tr>
-<tr><th>BANK:LVDSBIAS_1</th><th>[0, 1, 58]</th><th>[0, 1, 63]</th><th>[0, 1, 59]</th><th>[0, 1, 48]</th><th>[0, 1, 50]</th><th>[0, 1, 49]</th><th>[0, 1, 46]</th><th>[0, 1, 47]</th><th>[0, 1, 51]</th><th>[0, 1, 56]</th><th>[0, 1, 61]</th></tr>
-<tr><td>Non-inverted</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>BANK:LVDSBIAS_0</th><th>[0, 1, 40]</th><th>[0, 1, 41]</th><th>[0, 1, 42]</th><th>[0, 1, 43]</th><th>[0, 1, 44]</th><th>[0, 1, 45]</th><th>[0, 1, 52]</th><th>[0, 1, 53]</th><th>[0, 1, 54]</th><th>[0, 1, 55]</th><th>[0, 1, 60]</th><th>[0, 1, 62]</th></tr>
+<tr><th>BANK:LVDSBIAS_1</th><th>[0, 1, 46]</th><th>[0, 1, 47]</th><th>[0, 1, 48]</th><th>[0, 1, 49]</th><th>[0, 1, 50]</th><th>[0, 1, 51]</th><th>[0, 1, 56]</th><th>[0, 1, 57]</th><th>[0, 1, 58]</th><th>[0, 1, 59]</th><th>[0, 1, 61]</th><th>[0, 1, 63]</th></tr>
+<tr><td>Non-inverted</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 </section>
 </section>
@@ -1178,13 +1164,13 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.S3</span></c
 <tr><td>8</td>
 <td>-</td><td>-</td></tr>
 <tr><td>9</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[11]">DCI0:LVDSBIAS[11]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td></tr>
 <tr><td>10</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[12]">DCI0:LVDSBIAS[12]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
 <tr><td>11</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[11]">DCI1:LVDSBIAS[11]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td></tr>
 <tr><td>12</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[12]">DCI1:LVDSBIAS[12]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td></tr>
 <tr><td>13</td>
 <td>-</td><td><a href="#bits-xc3s-LR.S3-MISC:DCM_ENABLE" title="MISC:DCM_ENABLE">MISC:DCM_ENABLE</a></td></tr>
 <tr><td>14</td>
@@ -1204,81 +1190,81 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.S3</span></c
 <tr><td>21</td>
 <td>-</td><td>-</td></tr>
 <tr><td>22</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[12]">DCI0:LVDSBIAS[12]</a></td></tr>
 <tr><td>23</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[11]">DCI0:LVDSBIAS[11]</a></td></tr>
 <tr><td>24</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[10]">DCI0:LVDSBIAS[10]</a></td></tr>
 <tr><td>25</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[9]">DCI0:LVDSBIAS[9]</a></td></tr>
 <tr><td>26</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td></tr>
 <tr><td>27</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td></tr>
 <tr><td>28</td>
 <td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[6]">DCI0:LVDSBIAS[6]</a></td></tr>
 <tr><td>29</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td></tr>
 <tr><td>30</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td></tr>
 <tr><td>31</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[9]">DCI0:LVDSBIAS[9]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td></tr>
 <tr><td>32</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[10]">DCI0:LVDSBIAS[10]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
 <tr><td>33</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[12]">DCI1:LVDSBIAS[12]</a></td></tr>
 <tr><td>34</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[11]">DCI1:LVDSBIAS[11]</a></td></tr>
 <tr><td>35</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[10]">DCI1:LVDSBIAS[10]</a></td></tr>
 <tr><td>36</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[9]">DCI1:LVDSBIAS[9]</a></td></tr>
 <tr><td>37</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td></tr>
 <tr><td>38</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td></tr>
 <tr><td>39</td>
 <td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[6]">DCI1:LVDSBIAS[6]</a></td></tr>
 <tr><td>40</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td></tr>
 <tr><td>41</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td></tr>
 <tr><td>42</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[9]">DCI1:LVDSBIAS[9]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td></tr>
 <tr><td>43</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[10]">DCI1:LVDSBIAS[10]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td></tr>
 <tr><td>44</td>
 <td><a href="#bits-xc3s-LR.S3-DCI0:ENABLE" title="DCI0:ENABLE">DCI0:ENABLE</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td></tr>
 <tr><td>45</td>
 <td><a href="#bits-xc3s-LR.S3-DCI0:QUIET" title="DCI0:QUIET">DCI0:QUIET</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:QUIET" title="DCI1:QUIET">DCI1:QUIET</a></td></tr>
 <tr><td>46</td>
-<td><a href="#bits-xc3s-LR.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[2]">DCI0:TERM_SPLIT[2]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[2]">DCI1:TERM_SPLIT[2]</a></td></tr>
+<td><a href="#bits-xc3s-LR.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[0]">DCI0:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[0]">DCI1:NMASK_TERM_SPLIT[0]</a></td></tr>
 <tr><td>47</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LR.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[1]">DCI0:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[1]">DCI1:NMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>48</td>
-<td><a href="#bits-xc3s-LR.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[0]">DCI0:TERM_SPLIT[0]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[0]">DCI1:TERM_SPLIT[0]</a></td></tr>
+<td><a href="#bits-xc3s-LR.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[2]">DCI0:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[2]">DCI1:NMASK_TERM_SPLIT[2]</a></td></tr>
 <tr><td>49</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LR.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[3]">DCI0:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[3]">DCI1:NMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>50</td>
 <td><a href="#bits-xc3s-LR.S3-MISC:DCI_TEST_MUX" title="MISC:DCI_TEST_MUX">MISC:DCI_TEST_MUX</a></td><td>-</td></tr>
 <tr><td>51</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LR.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[0]">DCI0:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[0]">DCI1:PMASK_TERM_VCC[0]</a></td></tr>
 <tr><td>52</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LR.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[1]">DCI0:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[1]">DCI1:PMASK_TERM_VCC[1]</a></td></tr>
 <tr><td>53</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LR.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[2]">DCI0:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[2]">DCI1:PMASK_TERM_VCC[2]</a></td></tr>
 <tr><td>54</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LR.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[3]">DCI0:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[3]">DCI1:PMASK_TERM_VCC[3]</a></td></tr>
 <tr><td>55</td>
 <td>-</td><td>-</td></tr>
 <tr><td>56</td>
-<td><a href="#bits-xc3s-LR.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[1]">DCI0:TERM_SPLIT[1]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[1]">DCI1:TERM_SPLIT[1]</a></td></tr>
+<td><a href="#bits-xc3s-LR.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[0]">DCI0:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[0]">DCI1:PMASK_TERM_SPLIT[0]</a></td></tr>
 <tr><td>57</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LR.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[1]">DCI0:PMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[1]">DCI1:PMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>58</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-LR.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[2]">DCI0:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[2]">DCI1:PMASK_TERM_SPLIT[2]</a></td></tr>
 <tr><td>59</td>
-<td><a href="#bits-xc3s-LR.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[3]">DCI0:TERM_SPLIT[3]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[3]">DCI1:TERM_SPLIT[3]</a></td></tr>
+<td><a href="#bits-xc3s-LR.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[3]">DCI0:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc3s-LR.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[3]">DCI1:PMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>60</td>
 <td>-</td><td>-</td></tr>
 <tr><td>61</td>
@@ -1288,13 +1274,6 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.S3</span></c
 <tr><td>63</td>
 <td><a href="#bits-xc3s-LR.S3-DCIRESET0:ENABLE" title="DCIRESET0:ENABLE">DCIRESET0:ENABLE</a></td><td><a href="#bits-xc3s-LR.S3-DCIRESET1:ENABLE" title="DCIRESET1:ENABLE">DCIRESET1:ENABLE</a></td></tr>
 </table>
-<div id="bits-xc3s-LR.S3-DCI0:TERM_VCC"></div>
-<div id="bits-xc3s-LR.S3-DCI1:TERM_VCC"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_VCC</th></tr>
-<tr><th>DCI1:TERM_VCC</th></tr>
-<tr><td>Non-inverted</td></tr>
-</table>
 <div id="bits-xc3s-LR.S3-DCI0:ENABLE"></div>
 <div id="bits-xc3s-LR.S3-DCI0:FORCE_DONE_HIGH"></div>
 <div id="bits-xc3s-LR.S3-DCI0:QUIET"></div>
@@ -1328,11 +1307,19 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.S3</span></c
 <tr><th>STARTUP:GTS_SYNC</th><th>[0, 1, 1]</th></tr>
 <tr><td>Non-inverted</td><td>[0]</td></tr>
 </table>
-<div id="bits-xc3s-LR.S3-DCI0:TERM_SPLIT"></div>
-<div id="bits-xc3s-LR.S3-DCI1:TERM_SPLIT"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_SPLIT</th><th>[0, 0, 59]</th><th>[0, 0, 46]</th><th>[0, 0, 56]</th><th>[0, 0, 48]</th></tr>
-<tr><th>DCI1:TERM_SPLIT</th><th>[0, 1, 59]</th><th>[0, 1, 46]</th><th>[0, 1, 56]</th><th>[0, 1, 48]</th></tr>
+<div id="bits-xc3s-LR.S3-DCI0:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-LR.S3-DCI0:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-LR.S3-DCI0:PMASK_TERM_VCC"></div>
+<div id="bits-xc3s-LR.S3-DCI1:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-LR.S3-DCI1:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-LR.S3-DCI1:PMASK_TERM_VCC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI0:NMASK_TERM_SPLIT</th><th>[0, 0, 49]</th><th>[0, 0, 48]</th><th>[0, 0, 47]</th><th>[0, 0, 46]</th></tr>
+<tr><th>DCI0:PMASK_TERM_SPLIT</th><th>[0, 0, 59]</th><th>[0, 0, 58]</th><th>[0, 0, 57]</th><th>[0, 0, 56]</th></tr>
+<tr><th>DCI0:PMASK_TERM_VCC</th><th>[0, 0, 54]</th><th>[0, 0, 53]</th><th>[0, 0, 52]</th><th>[0, 0, 51]</th></tr>
+<tr><th>DCI1:NMASK_TERM_SPLIT</th><th>[0, 1, 49]</th><th>[0, 1, 48]</th><th>[0, 1, 47]</th><th>[0, 1, 46]</th></tr>
+<tr><th>DCI1:PMASK_TERM_SPLIT</th><th>[0, 1, 59]</th><th>[0, 1, 58]</th><th>[0, 1, 57]</th><th>[0, 1, 56]</th></tr>
+<tr><th>DCI1:PMASK_TERM_VCC</th><th>[0, 1, 54]</th><th>[0, 1, 53]</th><th>[0, 1, 52]</th><th>[0, 1, 51]</th></tr>
 <tr><td>Non-inverted</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc3s-LR.S3-MISC:DCI_TEST_MUX"></div>
@@ -1341,6 +1328,13 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.S3</span></c
 <tr><td>DCI0</td><td>0</td></tr>
 <tr><td>DCI1</td><td>1</td></tr>
 </table>
+<div id="bits-xc3s-LR.S3-DCI0:LVDSBIAS"></div>
+<div id="bits-xc3s-LR.S3-DCI1:LVDSBIAS"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI0:LVDSBIAS</th><th>[0, 1, 22]</th><th>[0, 1, 23]</th><th>[0, 1, 24]</th><th>[0, 1, 25]</th><th>[0, 1, 26]</th><th>[0, 1, 27]</th><th>[0, 1, 28]</th><th>[0, 1, 29]</th><th>[0, 1, 30]</th><th>[0, 1, 31]</th><th>[0, 1, 32]</th><th>[0, 1, 9]</th><th>[0, 1, 10]</th></tr>
+<tr><th>DCI1:LVDSBIAS</th><th>[0, 1, 33]</th><th>[0, 1, 34]</th><th>[0, 1, 35]</th><th>[0, 1, 36]</th><th>[0, 1, 37]</th><th>[0, 1, 38]</th><th>[0, 1, 39]</th><th>[0, 1, 40]</th><th>[0, 1, 41]</th><th>[0, 1, 42]</th><th>[0, 1, 43]</th><th>[0, 1, 11]</th><th>[0, 1, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
 <div id="bits-xc3s-LR.S3-MISC:CCLKPIN"></div>
 <div id="bits-xc3s-LR.S3-MISC:DONEPIN"></div>
 <table class="docutils align-default prjcombine-enum">
@@ -1349,13 +1343,6 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.S3</span></c
 <tr><td>PULLUP</td><td>0</td></tr>
 <tr><td>PULLNONE</td><td>1</td></tr>
 </table>
-<div id="bits-xc3s-LR.S3-DCI0:LVDSBIAS"></div>
-<div id="bits-xc3s-LR.S3-DCI1:LVDSBIAS"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:LVDSBIAS</th><th>[0, 1, 10]</th><th>[0, 1, 9]</th><th>[0, 1, 32]</th><th>[0, 1, 31]</th><th>[0, 1, 30]</th><th>[0, 1, 29]</th><th>[0, 1, 28]</th><th>[0, 1, 27]</th><th>[0, 1, 26]</th><th>[0, 1, 25]</th><th>[0, 1, 24]</th><th>[0, 1, 23]</th><th>[0, 1, 22]</th></tr>
-<tr><th>DCI1:LVDSBIAS</th><th>[0, 1, 12]</th><th>[0, 1, 11]</th><th>[0, 1, 43]</th><th>[0, 1, 42]</th><th>[0, 1, 41]</th><th>[0, 1, 40]</th><th>[0, 1, 39]</th><th>[0, 1, 38]</th><th>[0, 1, 37]</th><th>[0, 1, 36]</th><th>[0, 1, 35]</th><th>[0, 1, 34]</th><th>[0, 1, 33]</th></tr>
-<tr><td>Non-inverted</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
-</table>
 </section>
 <section id="lr-s3e">
 <h3><code class="docutils literal notranslate"><span class="pre">LR.S3E</span></code><a class="headerlink" href="#lr-s3e" title="Link to this heading"></a></h3>
@@ -1377,15 +1364,15 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.S3E</span></
 <tr><td>6</td>
 <td>-</td><td>-</td></tr>
 <tr><td>7</td>
-<td>-</td><td>-</td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[1]">BANK:LVDSBIAS_0[1]</a></td></tr>
 <tr><td>8</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[3]">BANK:LVDSBIAS_1[3]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[4]">BANK:LVDSBIAS_1[4]</a></td></tr>
 <tr><td>9</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[5]">BANK:LVDSBIAS_1[5]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[3]">BANK:LVDSBIAS_1[3]</a></td></tr>
 <tr><td>10</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-MISC:UNK_ALWAYS_SET" title="MISC:UNK_ALWAYS_SET[0]">MISC:UNK_ALWAYS_SET[0]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[2]">BANK:LVDSBIAS_1[2]</a></td></tr>
 <tr><td>11</td>
-<td>-</td><td>-</td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[1]">BANK:LVDSBIAS_1[1]</a></td></tr>
 <tr><td>12</td>
 <td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[0]">BANK:LVDSBIAS_0[0]</a></td></tr>
 <tr><td>13</td>
@@ -1407,35 +1394,35 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.S3E</span></
 <tr><td>21</td>
 <td>-</td><td>-</td></tr>
 <tr><td>22</td>
-<td>-</td><td>-</td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[10]">BANK:LVDSBIAS_0[10]</a></td></tr>
 <tr><td>23</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[4]">BANK:LVDSBIAS_0[4]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[9]">BANK:LVDSBIAS_0[9]</a></td></tr>
 <tr><td>24</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[5]">BANK:LVDSBIAS_0[5]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[8]">BANK:LVDSBIAS_0[8]</a></td></tr>
 <tr><td>25</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[1]">BANK:LVDSBIAS_0[1]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[7]">BANK:LVDSBIAS_0[7]</a></td></tr>
 <tr><td>26</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[2]">BANK:LVDSBIAS_0[2]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[6]">BANK:LVDSBIAS_0[6]</a></td></tr>
 <tr><td>27</td>
-<td>-</td><td>-</td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[5]">BANK:LVDSBIAS_0[5]</a></td></tr>
 <tr><td>28</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[7]">BANK:LVDSBIAS_1[7]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[10]">BANK:LVDSBIAS_1[10]</a></td></tr>
 <tr><td>29</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[4]">BANK:LVDSBIAS_1[4]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[9]">BANK:LVDSBIAS_1[9]</a></td></tr>
 <tr><td>30</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[6]">BANK:LVDSBIAS_1[6]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[8]">BANK:LVDSBIAS_1[8]</a></td></tr>
 <tr><td>31</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[1]">BANK:LVDSBIAS_1[1]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[7]">BANK:LVDSBIAS_1[7]</a></td></tr>
 <tr><td>32</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[2]">BANK:LVDSBIAS_1[2]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[6]">BANK:LVDSBIAS_1[6]</a></td></tr>
 <tr><td>33</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[8]">BANK:LVDSBIAS_1[8]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[5]">BANK:LVDSBIAS_1[5]</a></td></tr>
 <tr><td>34</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[3]">BANK:LVDSBIAS_0[3]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[4]">BANK:LVDSBIAS_0[4]</a></td></tr>
 <tr><td>35</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[6]">BANK:LVDSBIAS_0[6]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[3]">BANK:LVDSBIAS_0[3]</a></td></tr>
 <tr><td>36</td>
-<td>-</td><td><a href="#bits-xc3s-LR.S3E-MISC:UNK_ALWAYS_SET" title="MISC:UNK_ALWAYS_SET[1]">MISC:UNK_ALWAYS_SET[1]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[2]">BANK:LVDSBIAS_0[2]</a></td></tr>
 </table>
 <div id="bits-xc3s-LR.S3E-STARTUP:GSR_SYNC"></div>
 <div id="bits-xc3s-LR.S3E-STARTUP:GTS_GSR_ENABLE"></div>
@@ -1446,20 +1433,12 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.S3E</span></
 <tr><th>STARTUP:GTS_SYNC</th><th>[0, 1, 1]</th></tr>
 <tr><td>Non-inverted</td><td>[0]</td></tr>
 </table>
-<div id="bits-xc3s-LR.S3E-MISC:UNK_ALWAYS_SET"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>MISC:UNK_ALWAYS_SET</th><th>[0, 1, 36]</th><th>[0, 1, 10]</th></tr>
-<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
-</table>
 <div id="bits-xc3s-LR.S3E-BANK:LVDSBIAS_0"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>BANK:LVDSBIAS_0</th><th>[0, 1, 35]</th><th>[0, 1, 24]</th><th>[0, 1, 23]</th><th>[0, 1, 34]</th><th>[0, 1, 26]</th><th>[0, 1, 25]</th><th>[0, 1, 12]</th></tr>
-<tr><td>Non-inverted</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
-</table>
 <div id="bits-xc3s-LR.S3E-BANK:LVDSBIAS_1"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>BANK:LVDSBIAS_1</th><th>[0, 1, 33]</th><th>[0, 1, 28]</th><th>[0, 1, 30]</th><th>[0, 1, 9]</th><th>[0, 1, 29]</th><th>[0, 1, 8]</th><th>[0, 1, 32]</th><th>[0, 1, 31]</th><th>[0, 1, 13]</th></tr>
-<tr><td>Non-inverted</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>BANK:LVDSBIAS_0</th><th>[0, 1, 22]</th><th>[0, 1, 23]</th><th>[0, 1, 24]</th><th>[0, 1, 25]</th><th>[0, 1, 26]</th><th>[0, 1, 27]</th><th>[0, 1, 34]</th><th>[0, 1, 35]</th><th>[0, 1, 36]</th><th>[0, 1, 7]</th><th>[0, 1, 12]</th></tr>
+<tr><th>BANK:LVDSBIAS_1</th><th>[0, 1, 28]</th><th>[0, 1, 29]</th><th>[0, 1, 30]</th><th>[0, 1, 31]</th><th>[0, 1, 32]</th><th>[0, 1, 33]</th><th>[0, 1, 8]</th><th>[0, 1, 9]</th><th>[0, 1, 10]</th><th>[0, 1, 11]</th><th>[0, 1, 13]</th></tr>
+<tr><td>Non-inverted</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc3s-LR.S3E-MISC:CCLKPIN"></div>
 <div id="bits-xc3s-LR.S3E-MISC:DONEPIN"></div>
@@ -1539,11 +1518,11 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.S3</span></c
 <tr><td>8</td>
 <td>-</td><td>-</td></tr>
 <tr><td>9</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[11]">DCI1:LVDSBIAS[11]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td></tr>
 <tr><td>10</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[11]">DCI0:LVDSBIAS[11]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[12]">DCI1:LVDSBIAS[12]</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td></tr>
 <tr><td>11</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[12]">DCI0:LVDSBIAS[12]</a></td><td><a href="#bits-xc3s-UR.S3-MISC:DCM_ENABLE" title="MISC:DCM_ENABLE">MISC:DCM_ENABLE</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td><td><a href="#bits-xc3s-UR.S3-MISC:DCM_ENABLE" title="MISC:DCM_ENABLE">MISC:DCM_ENABLE</a></td></tr>
 <tr><td>12</td>
 <td>-</td><td>-</td></tr>
 <tr><td>13</td>
@@ -1587,59 +1566,59 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.S3</span></c
 <tr><td>32</td>
 <td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[1]">~BSCAN:USERID[1]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[0]">~BSCAN:USERID[0]</a></td></tr>
 <tr><td>33</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[12]">DCI0:LVDSBIAS[12]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[12]">DCI1:LVDSBIAS[12]</a></td></tr>
 <tr><td>34</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[11]">DCI0:LVDSBIAS[11]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[11]">DCI1:LVDSBIAS[11]</a></td></tr>
 <tr><td>35</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[10]">DCI0:LVDSBIAS[10]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[10]">DCI1:LVDSBIAS[10]</a></td></tr>
 <tr><td>36</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[9]">DCI0:LVDSBIAS[9]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[9]">DCI1:LVDSBIAS[9]</a></td></tr>
 <tr><td>37</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td></tr>
 <tr><td>38</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td></tr>
 <tr><td>39</td>
 <td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[6]">DCI0:LVDSBIAS[6]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[6]">DCI1:LVDSBIAS[6]</a></td></tr>
 <tr><td>40</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td></tr>
 <tr><td>41</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td></tr>
 <tr><td>42</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[9]">DCI0:LVDSBIAS[9]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[9]">DCI1:LVDSBIAS[9]</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td></tr>
 <tr><td>43</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[10]">DCI0:LVDSBIAS[10]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[10]">DCI1:LVDSBIAS[10]</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td></tr>
 <tr><td>44</td>
 <td><a href="#bits-xc3s-UR.S3-DCI0:ENABLE" title="DCI0:ENABLE">DCI0:ENABLE</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td></tr>
 <tr><td>45</td>
 <td><a href="#bits-xc3s-UR.S3-DCI0:QUIET" title="DCI0:QUIET">DCI0:QUIET</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:QUIET" title="DCI1:QUIET">DCI1:QUIET</a></td></tr>
 <tr><td>46</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[2]">DCI0:TERM_SPLIT[2]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[2]">DCI1:TERM_SPLIT[2]</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[0]">DCI0:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[0]">DCI1:NMASK_TERM_SPLIT[0]</a></td></tr>
 <tr><td>47</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[1]">DCI0:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[1]">DCI1:NMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>48</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[0]">DCI0:TERM_SPLIT[0]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[0]">DCI1:TERM_SPLIT[0]</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[2]">DCI0:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[2]">DCI1:NMASK_TERM_SPLIT[2]</a></td></tr>
 <tr><td>49</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[3]">DCI0:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[3]">DCI1:NMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>50</td>
 <td><a href="#bits-xc3s-UR.S3-MISC:DCI_TEST_MUX" title="MISC:DCI_TEST_MUX">MISC:DCI_TEST_MUX</a></td><td>-</td></tr>
 <tr><td>51</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[0]">DCI0:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[0]">DCI1:PMASK_TERM_VCC[0]</a></td></tr>
 <tr><td>52</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[1]">DCI0:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[1]">DCI1:PMASK_TERM_VCC[1]</a></td></tr>
 <tr><td>53</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[2]">DCI0:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[2]">DCI1:PMASK_TERM_VCC[2]</a></td></tr>
 <tr><td>54</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[3]">DCI0:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[3]">DCI1:PMASK_TERM_VCC[3]</a></td></tr>
 <tr><td>55</td>
 <td>-</td><td>-</td></tr>
 <tr><td>56</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[1]">DCI0:TERM_SPLIT[1]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[1]">DCI1:TERM_SPLIT[1]</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[0]">DCI0:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[0]">DCI1:PMASK_TERM_SPLIT[0]</a></td></tr>
 <tr><td>57</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[1]">DCI0:PMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[1]">DCI1:PMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>58</td>
-<td>-</td><td>-</td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[2]">DCI0:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[2]">DCI1:PMASK_TERM_SPLIT[2]</a></td></tr>
 <tr><td>59</td>
-<td><a href="#bits-xc3s-UR.S3-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[3]">DCI0:TERM_SPLIT[3]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[3]">DCI1:TERM_SPLIT[3]</a></td></tr>
+<td><a href="#bits-xc3s-UR.S3-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[3]">DCI0:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc3s-UR.S3-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[3]">DCI1:PMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>60</td>
 <td>-</td><td>-</td></tr>
 <tr><td>61</td>
@@ -1649,12 +1628,12 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.S3</span></c
 <tr><td>63</td>
 <td><a href="#bits-xc3s-UR.S3-DCIRESET0:ENABLE" title="DCIRESET0:ENABLE">DCIRESET0:ENABLE</a></td><td><a href="#bits-xc3s-UR.S3-DCIRESET1:ENABLE" title="DCIRESET1:ENABLE">DCIRESET1:ENABLE</a></td></tr>
 </table>
-<div id="bits-xc3s-UR.S3-DCI0:TERM_VCC"></div>
-<div id="bits-xc3s-UR.S3-DCI1:TERM_VCC"></div>
+<div id="bits-xc3s-UR.S3-DCI0:LVDSBIAS"></div>
+<div id="bits-xc3s-UR.S3-DCI1:LVDSBIAS"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_VCC</th></tr>
-<tr><th>DCI1:TERM_VCC</th></tr>
-<tr><td>Non-inverted</td></tr>
+<tr><th>DCI0:LVDSBIAS</th><th>[0, 0, 33]</th><th>[0, 0, 34]</th><th>[0, 0, 35]</th><th>[0, 0, 36]</th><th>[0, 0, 37]</th><th>[0, 0, 38]</th><th>[0, 0, 39]</th><th>[0, 0, 40]</th><th>[0, 0, 41]</th><th>[0, 0, 42]</th><th>[0, 0, 43]</th><th>[0, 0, 10]</th><th>[0, 0, 11]</th></tr>
+<tr><th>DCI1:LVDSBIAS</th><th>[0, 1, 33]</th><th>[0, 1, 34]</th><th>[0, 1, 35]</th><th>[0, 1, 36]</th><th>[0, 1, 37]</th><th>[0, 1, 38]</th><th>[0, 1, 39]</th><th>[0, 1, 40]</th><th>[0, 1, 41]</th><th>[0, 1, 42]</th><th>[0, 1, 43]</th><th>[0, 1, 9]</th><th>[0, 1, 10]</th></tr>
+<tr><td>Non-inverted</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc3s-UR.S3-MISC:TCKPIN"></div>
 <div id="bits-xc3s-UR.S3-MISC:TDOPIN"></div>
@@ -1672,13 +1651,6 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.S3</span></c
 <tr><th>BSCAN:TDO_ENABLE</th><th>[0, 1, 16]</th><th>[0, 0, 16]</th></tr>
 <tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
 </table>
-<div id="bits-xc3s-UR.S3-DCI0:LVDSBIAS"></div>
-<div id="bits-xc3s-UR.S3-DCI1:LVDSBIAS"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:LVDSBIAS</th><th>[0, 0, 11]</th><th>[0, 0, 10]</th><th>[0, 0, 43]</th><th>[0, 0, 42]</th><th>[0, 0, 41]</th><th>[0, 0, 40]</th><th>[0, 0, 39]</th><th>[0, 0, 38]</th><th>[0, 0, 37]</th><th>[0, 0, 36]</th><th>[0, 0, 35]</th><th>[0, 0, 34]</th><th>[0, 0, 33]</th></tr>
-<tr><th>DCI1:LVDSBIAS</th><th>[0, 1, 10]</th><th>[0, 1, 9]</th><th>[0, 1, 43]</th><th>[0, 1, 42]</th><th>[0, 1, 41]</th><th>[0, 1, 40]</th><th>[0, 1, 39]</th><th>[0, 1, 38]</th><th>[0, 1, 37]</th><th>[0, 1, 36]</th><th>[0, 1, 35]</th><th>[0, 1, 34]</th><th>[0, 1, 33]</th></tr>
-<tr><td>Non-inverted</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
-</table>
 <div id="bits-xc3s-UR.S3-DCI0:ENABLE"></div>
 <div id="bits-xc3s-UR.S3-DCI0:FORCE_DONE_HIGH"></div>
 <div id="bits-xc3s-UR.S3-DCI0:QUIET"></div>
@@ -1704,11 +1676,19 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.S3</span></c
 <tr><th>MISC:DCM_ENABLE</th><th>[0, 1, 11]</th></tr>
 <tr><td>Non-inverted</td><td>[0]</td></tr>
 </table>
-<div id="bits-xc3s-UR.S3-DCI0:TERM_SPLIT"></div>
-<div id="bits-xc3s-UR.S3-DCI1:TERM_SPLIT"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_SPLIT</th><th>[0, 0, 59]</th><th>[0, 0, 46]</th><th>[0, 0, 56]</th><th>[0, 0, 48]</th></tr>
-<tr><th>DCI1:TERM_SPLIT</th><th>[0, 1, 59]</th><th>[0, 1, 46]</th><th>[0, 1, 56]</th><th>[0, 1, 48]</th></tr>
+<div id="bits-xc3s-UR.S3-DCI0:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-UR.S3-DCI0:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-UR.S3-DCI0:PMASK_TERM_VCC"></div>
+<div id="bits-xc3s-UR.S3-DCI1:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-UR.S3-DCI1:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc3s-UR.S3-DCI1:PMASK_TERM_VCC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI0:NMASK_TERM_SPLIT</th><th>[0, 0, 49]</th><th>[0, 0, 48]</th><th>[0, 0, 47]</th><th>[0, 0, 46]</th></tr>
+<tr><th>DCI0:PMASK_TERM_SPLIT</th><th>[0, 0, 59]</th><th>[0, 0, 58]</th><th>[0, 0, 57]</th><th>[0, 0, 56]</th></tr>
+<tr><th>DCI0:PMASK_TERM_VCC</th><th>[0, 0, 54]</th><th>[0, 0, 53]</th><th>[0, 0, 52]</th><th>[0, 0, 51]</th></tr>
+<tr><th>DCI1:NMASK_TERM_SPLIT</th><th>[0, 1, 49]</th><th>[0, 1, 48]</th><th>[0, 1, 47]</th><th>[0, 1, 46]</th></tr>
+<tr><th>DCI1:PMASK_TERM_SPLIT</th><th>[0, 1, 59]</th><th>[0, 1, 58]</th><th>[0, 1, 57]</th><th>[0, 1, 56]</th></tr>
+<tr><th>DCI1:PMASK_TERM_VCC</th><th>[0, 1, 54]</th><th>[0, 1, 53]</th><th>[0, 1, 52]</th><th>[0, 1, 51]</th></tr>
 <tr><td>Non-inverted</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc3s-UR.S3-MISC:DCI_TEST_MUX"></div>
@@ -1747,7 +1727,7 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.S3E</span></
 <tr><td>8</td>
 <td>-</td><td>-</td></tr>
 <tr><td>9</td>
-<td>-</td><td>-</td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[1]">BANK:LVDSBIAS_1[1]</a></td></tr>
 <tr><td>10</td>
 <td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[0]">BANK:LVDSBIAS_0[0]</a></td></tr>
 <tr><td>11</td>
@@ -1795,43 +1775,43 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.S3E</span></
 <tr><td>32</td>
 <td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[1]">~BSCAN:USERID[1]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[0]">~BSCAN:USERID[0]</a></td></tr>
 <tr><td>33</td>
-<td>-</td><td>-</td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[10]">BANK:LVDSBIAS_0[10]</a></td></tr>
 <tr><td>34</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[4]">BANK:LVDSBIAS_0[4]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[9]">BANK:LVDSBIAS_0[9]</a></td></tr>
 <tr><td>35</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[5]">BANK:LVDSBIAS_0[5]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[8]">BANK:LVDSBIAS_0[8]</a></td></tr>
 <tr><td>36</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[1]">BANK:LVDSBIAS_0[1]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[7]">BANK:LVDSBIAS_0[7]</a></td></tr>
 <tr><td>37</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[2]">BANK:LVDSBIAS_0[2]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[6]">BANK:LVDSBIAS_0[6]</a></td></tr>
 <tr><td>38</td>
-<td>-</td><td>-</td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[5]">BANK:LVDSBIAS_0[5]</a></td></tr>
 <tr><td>39</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[7]">BANK:LVDSBIAS_1[7]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[10]">BANK:LVDSBIAS_1[10]</a></td></tr>
 <tr><td>40</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[4]">BANK:LVDSBIAS_1[4]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[9]">BANK:LVDSBIAS_1[9]</a></td></tr>
 <tr><td>41</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[5]">BANK:LVDSBIAS_1[5]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[8]">BANK:LVDSBIAS_1[8]</a></td></tr>
 <tr><td>42</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[1]">BANK:LVDSBIAS_1[1]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[7]">BANK:LVDSBIAS_1[7]</a></td></tr>
 <tr><td>43</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[2]">BANK:LVDSBIAS_1[2]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[6]">BANK:LVDSBIAS_1[6]</a></td></tr>
 <tr><td>44</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[8]">BANK:LVDSBIAS_1[8]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[5]">BANK:LVDSBIAS_1[5]</a></td></tr>
 <tr><td>45</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[3]">BANK:LVDSBIAS_0[3]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[4]">BANK:LVDSBIAS_0[4]</a></td></tr>
 <tr><td>46</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[6]">BANK:LVDSBIAS_0[6]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[3]">BANK:LVDSBIAS_0[3]</a></td></tr>
 <tr><td>47</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-MISC:UNK_ALWAYS_SET" title="MISC:UNK_ALWAYS_SET[0]">MISC:UNK_ALWAYS_SET[0]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[2]">BANK:LVDSBIAS_0[2]</a></td></tr>
 <tr><td>48</td>
-<td>-</td><td>-</td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_0" title="BANK:LVDSBIAS_0[1]">BANK:LVDSBIAS_0[1]</a></td></tr>
 <tr><td>49</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[3]">BANK:LVDSBIAS_1[3]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[4]">BANK:LVDSBIAS_1[4]</a></td></tr>
 <tr><td>50</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[6]">BANK:LVDSBIAS_1[6]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[3]">BANK:LVDSBIAS_1[3]</a></td></tr>
 <tr><td>51</td>
-<td>-</td><td><a href="#bits-xc3s-UR.S3E-MISC:UNK_ALWAYS_SET" title="MISC:UNK_ALWAYS_SET[1]">MISC:UNK_ALWAYS_SET[1]</a></td></tr>
+<td>-</td><td><a href="#bits-xc3s-UR.S3E-BANK:LVDSBIAS_1" title="BANK:LVDSBIAS_1[2]">BANK:LVDSBIAS_1[2]</a></td></tr>
 </table>
 <div id="bits-xc3s-UR.S3E-MISC:TCKPIN"></div>
 <div id="bits-xc3s-UR.S3E-MISC:TDOPIN"></div>
@@ -1845,21 +1825,16 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.S3E</span></
 <tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
 </table>
 <div id="bits-xc3s-UR.S3E-BSCAN:TDO_ENABLE"></div>
-<div id="bits-xc3s-UR.S3E-MISC:UNK_ALWAYS_SET"></div>
 <table class="docutils align-default prjcombine-enum">
 <tr><th>BSCAN:TDO_ENABLE</th><th>[0, 1, 16]</th><th>[0, 0, 16]</th></tr>
-<tr><th>MISC:UNK_ALWAYS_SET</th><th>[0, 1, 51]</th><th>[0, 1, 47]</th></tr>
 <tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc3s-UR.S3E-BANK:LVDSBIAS_0"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>BANK:LVDSBIAS_0</th><th>[0, 1, 46]</th><th>[0, 1, 35]</th><th>[0, 1, 34]</th><th>[0, 1, 45]</th><th>[0, 1, 37]</th><th>[0, 1, 36]</th><th>[0, 1, 10]</th></tr>
-<tr><td>Non-inverted</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
-</table>
 <div id="bits-xc3s-UR.S3E-BANK:LVDSBIAS_1"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>BANK:LVDSBIAS_1</th><th>[0, 1, 44]</th><th>[0, 1, 39]</th><th>[0, 1, 50]</th><th>[0, 1, 41]</th><th>[0, 1, 40]</th><th>[0, 1, 49]</th><th>[0, 1, 43]</th><th>[0, 1, 42]</th><th>[0, 1, 11]</th></tr>
-<tr><td>Non-inverted</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>BANK:LVDSBIAS_0</th><th>[0, 1, 33]</th><th>[0, 1, 34]</th><th>[0, 1, 35]</th><th>[0, 1, 36]</th><th>[0, 1, 37]</th><th>[0, 1, 38]</th><th>[0, 1, 45]</th><th>[0, 1, 46]</th><th>[0, 1, 47]</th><th>[0, 1, 48]</th><th>[0, 1, 10]</th></tr>
+<tr><th>BANK:LVDSBIAS_1</th><th>[0, 1, 39]</th><th>[0, 1, 40]</th><th>[0, 1, 41]</th><th>[0, 1, 42]</th><th>[0, 1, 43]</th><th>[0, 1, 44]</th><th>[0, 1, 49]</th><th>[0, 1, 50]</th><th>[0, 1, 51]</th><th>[0, 1, 9]</th><th>[0, 1, 11]</th></tr>
+<tr><td>Non-inverted</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc3s-UR.S3E-BSCAN:USERID"></div>
 <table class="docutils align-default prjcombine-enum">
@@ -2031,71 +2006,64 @@ <h2>I/O data — Spartan 3<a class="headerlink" href="#i-o-data-spartan-3" title
 <table class="docutils align-default">
 <tr><th rowspan="2">Name</th><th colspan="13">IOSTD:S3:LVDSBIAS</th></tr>
 <tr><th>[12]</th><th>[11]</th><th>[10]</th><th>[9]</th><th>[8]</th><th>[7]</th><th>[6]</th><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
-<tr><td>LDT_25</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDSEXT_25</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
-<tr><td>LVDSEXT_25_DCI</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
-<tr><td>LVDS_25</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
-<tr><td>LVDS_25_DCI</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
-<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>RSDS_25</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
-<tr><td>ULVDS_25</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LDT_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>LVDSEXT_25</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>LVDSEXT_25_DCI</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVDS_25</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>LVDS_25_DCI</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>RSDS_25</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>ULVDS_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
 </table>
 <table class="docutils align-default">
-<tr><th rowspan="2">Name</th><th colspan="4">IOSTD:S3:TERM_SPLIT</th></tr>
-<tr><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
-<tr><td>HSTL_II_DCI_18</td><td>1</td><td>0</td><td>1</td><td>1</td></tr>
-<tr><td>HSTL_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>HSTL_I_DCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDSEXT_25_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDS_25_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>SSTL18_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>SSTL2_II_DCI</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
-<tr><td>SSTL2_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><th rowspan="2">Name</th><th colspan="4">IOSTD:S3:PMASK_TERM_SPLIT</th><th colspan="4">IOSTD:S3:NMASK_TERM_SPLIT</th></tr>
+<tr><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>HSTL_II_DCI_18</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_I_DCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDSEXT_25_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDS_25_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL2_II_DCI</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>SSTL2_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 </table>
 <table class="docutils align-default">
-<tr><th rowspan="2">Name</th><th colspan="0">IOSTD:S3:TERM_VCC</th></tr>
-<tr></tr>
-<tr><td>GTLP_DCI</td></tr>
-<tr><td>GTL_DCI</td></tr>
-<tr><td>HSTL_III_DCI</td></tr>
-<tr><td>HSTL_III_DCI_18</td></tr>
-<tr><td>NONE</td></tr>
+<tr><th rowspan="2">Name</th><th colspan="4">IOSTD:S3:PMASK_TERM_VCC</th></tr>
+<tr><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>GTLP_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>GTL_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_III_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_III_DCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 </table>
 </section>
 <section id="i-o-data-spartan-3e">
 <h2>I/O data — Spartan 3E<a class="headerlink" href="#i-o-data-spartan-3e" title="Link to this heading"></a></h2>
 <table class="docutils align-default">
-<tr><th rowspan="2">Name</th><th colspan="7">IOSTD:S3E:LVDSBIAS_0</th></tr>
-<tr><th>[6]</th><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
-<tr><td>MINI_LVDS_25</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
-<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>RSDS_25</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
-</table>
-<table class="docutils align-default">
-<tr><th rowspan="2">Name</th><th colspan="9">IOSTD:S3E:LVDSBIAS_1</th></tr>
-<tr><th>[8]</th><th>[7]</th><th>[6]</th><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
-<tr><td>LVDS_25</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
-<tr><td>MINI_LVDS_25</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
-<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>RSDS_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><th rowspan="2">Name</th><th colspan="11">IOSTD:S3E:LVDSBIAS</th></tr>
+<tr><th>[10]</th><th>[9]</th><th>[8]</th><th>[7]</th><th>[6]</th><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>LVDS_25</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>MINI_LVDS_25</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>RSDS_25</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
 </table>
 </section>
 <section id="i-o-data-spartan-3a">
 <h2>I/O data — Spartan 3A<a class="headerlink" href="#i-o-data-spartan-3a" title="Link to this heading"></a></h2>
 <table class="docutils align-default">
-<tr><th rowspan="2">Name</th><th colspan="11">IOSTD:S3A.TB:LVDSBIAS</th></tr>
-<tr><th>[10]</th><th>[9]</th><th>[8]</th><th>[7]</th><th>[6]</th><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
-<tr><td>LVDS_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
-<tr><td>LVDS_33</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
-<tr><td>MINI_LVDS_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
-<tr><td>MINI_LVDS_33</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
-<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>PPDS_25</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
-<tr><td>PPDS_33</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
-<tr><td>RSDS_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
-<tr><td>RSDS_33</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
-<tr><td>TMDS_33</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><th rowspan="2">Name</th><th colspan="12">IOSTD:S3A.TB:LVDSBIAS</th></tr>
+<tr><th>[11]</th><th>[10]</th><th>[9]</th><th>[8]</th><th>[7]</th><th>[6]</th><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>LVDS_25</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVDS_33</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>MINI_LVDS_25</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>MINI_LVDS_33</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>PPDS_25</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>PPDS_33</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>RSDS_25</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>RSDS_33</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>TMDS_33</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
 </table>
 </section>
 </section>
diff --git a/xilinx/virtex2/corner.html b/xilinx/virtex2/corner.html
index e057d7f6..c0567c5e 100644
--- a/xilinx/virtex2/corner.html
+++ b/xilinx/virtex2/corner.html
@@ -194,21 +194,21 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.V2</span></c
 <tr><td>31</td>
 <td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:TEST_ENABLE" title="DCI0:TEST_ENABLE">DCI0:TEST_ENABLE</a></td><td><a href="#bits-xc2v-LL.V2-DCI0:FORCE_DONE_HIGH" title="DCI0:FORCE_DONE_HIGH">DCI0:FORCE_DONE_HIGH</a></td></tr>
 <tr><td>32</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[0]">DCI0:TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LL.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[2]">DCI0:TERM_SPLIT[2]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[4]">DCI0:PMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LL.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[3]">DCI0:PMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>33</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[3]">DCI0:TERM_SPLIT[3]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[2]">DCI0:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-LL.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[1]">DCI0:PMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>34</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[5]">DCI0:TERM_SPLIT[5]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[0]">DCI0:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LL.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[4]">DCI0:PMASK_TERM_VCC[4]</a></td></tr>
 <tr><td>35</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[3]">DCI0:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-LL.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[2]">DCI0:PMASK_TERM_VCC[2]</a></td></tr>
 <tr><td>36</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:TERM_VCC" title="DCI0:TERM_VCC">DCI0:TERM_VCC</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[1]">DCI0:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-LL.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[0]">DCI0:PMASK_TERM_VCC[0]</a></td></tr>
 <tr><td>37</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[1]">DCI0:TERM_SPLIT[1]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[4]">DCI0:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LL.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[3]">DCI0:NMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>38</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[4]">DCI0:TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LL.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[6]">DCI0:TERM_SPLIT[6]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[2]">DCI0:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-LL.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[1]">DCI0:NMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>39</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[0]">DCI0:NMASK_TERM_SPLIT[0]</a></td><td>-</td></tr>
 <tr><td>40</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>41</td>
@@ -218,15 +218,15 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.V2</span></c
 <tr><td>43</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>44</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td></tr>
 <tr><td>45</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td><td><a href="#bits-xc2v-LL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[6]">DCI0:LVDSBIAS[6]</a></td></tr>
 <tr><td>46</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-LL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td></tr>
 <tr><td>47</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td><td><a href="#bits-xc2v-LL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
 <tr><td>48</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td><td><a href="#bits-xc2v-LL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
 </table>
 <table class="docutils align-default prjcombine-tile">
 <tr><th colspan="21">LL.V2 bittile 1</th></tr><tr><th rowspan="2">Row</th><th colspan="20">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th></tr>
@@ -243,25 +243,23 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.V2</span></c
 <tr><td>5</td>
 <td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>6</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[2]">DCI1:TERM_SPLIT[2]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:DISABLEBANDGAP" title="MISC:DISABLEBANDGAP">MISC:DISABLEBANDGAP</a></td><td><a href="#bits-xc2v-LL.V2-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[2]">MISC:BCLK_DIV2[2]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:RAISEVGG" title="MISC:RAISEVGG[0]">MISC:RAISEVGG[0]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[1]">DCI1:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[4]">DCI1:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:DISABLEBANDGAP" title="MISC:DISABLEBANDGAP">MISC:DISABLEBANDGAP</a></td><td><a href="#bits-xc2v-LL.V2-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[2]">MISC:BCLK_DIV2[2]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:RAISEVGG" title="MISC:RAISEVGG[0]">MISC:RAISEVGG[0]</a></td></tr>
 <tr><td>7</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[0]">DCI1:TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[6]">DCI1:TERM_SPLIT[6]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:M2PIN" title="MISC:M2PIN[0]">MISC:M2PIN[0]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[3]">MISC:BCLK_DIV2[3]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[3]">MISC:ZCLK_DIV2[3]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[2]">DCI1:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[3]">DCI1:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[1]">DCI1:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:M2PIN" title="MISC:M2PIN[0]">MISC:M2PIN[0]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[3]">MISC:BCLK_DIV2[3]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[3]">MISC:ZCLK_DIV2[3]</a></td></tr>
 <tr><td>8</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:TERM_VCC" title="DCI1:TERM_VCC">DCI1:TERM_VCC</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:M2PIN" title="MISC:M2PIN[1]">MISC:M2PIN[1]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[4]">MISC:BCLK_DIV2[4]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:RAISEVGG" title="MISC:RAISEVGG[1]">MISC:RAISEVGG[1]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[0]">DCI1:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[3]">DCI1:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:M2PIN" title="MISC:M2PIN[1]">MISC:M2PIN[1]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[4]">MISC:BCLK_DIV2[4]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:RAISEVGG" title="MISC:RAISEVGG[1]">MISC:RAISEVGG[1]</a></td></tr>
 <tr><td>9</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[5]">DCI1:TERM_SPLIT[5]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:M1PIN" title="MISC:M1PIN[0]">MISC:M1PIN[0]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[1]">MISC:BCLK_DIV2[1]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:DCI_ALTVR" title="MISC:DCI_ALTVR">MISC:DCI_ALTVR</a></td><td><a href="#bits-xc2v-LL.V2-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[1]">MISC:ZCLK_DIV2[1]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[0]">DCI1:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[1]">DCI1:PMASK_TERM_SPLIT[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[6]">DCI1:LVDSBIAS[6]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:M1PIN" title="MISC:M1PIN[0]">MISC:M1PIN[0]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[1]">MISC:BCLK_DIV2[1]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:DCI_ALTVR" title="MISC:DCI_ALTVR">MISC:DCI_ALTVR</a></td><td><a href="#bits-xc2v-LL.V2-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[1]">MISC:ZCLK_DIV2[1]</a></td></tr>
 <tr><td>10</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[1]">DCI1:TERM_SPLIT[1]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[4]">DCI1:TERM_SPLIT[4]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:M0PIN" title="MISC:M0PIN[0]">MISC:M0PIN[0]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[0]">MISC:BCLK_DIV2[0]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:DCI_CLK_ENABLE" title="MISC:DCI_CLK_ENABLE">MISC:DCI_CLK_ENABLE</a></td><td><a href="#bits-xc2v-LL.V2-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[4]">MISC:ZCLK_DIV2[4]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[4]">DCI1:PMASK_TERM_VCC[4]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[4]">DCI1:PMASK_TERM_SPLIT[4]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[2]">DCI1:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:M0PIN" title="MISC:M0PIN[0]">MISC:M0PIN[0]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[0]">MISC:BCLK_DIV2[0]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:DCI_CLK_ENABLE" title="MISC:DCI_CLK_ENABLE">MISC:DCI_CLK_ENABLE</a></td><td><a href="#bits-xc2v-LL.V2-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[4]">MISC:ZCLK_DIV2[4]</a></td></tr>
 <tr><td>11</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[3]">DCI1:TERM_SPLIT[3]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:M0PIN" title="MISC:M0PIN[1]">MISC:M0PIN[1]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:M1PIN" title="MISC:M1PIN[1]">MISC:M1PIN[1]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[0]">MISC:ZCLK_DIV2[0]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[2]">MISC:ZCLK_DIV2[2]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[3]">DCI1:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[2]">DCI1:PMASK_TERM_SPLIT[2]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[0]">DCI1:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td><td><a href="#bits-xc2v-LL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2-MISC:M0PIN" title="MISC:M0PIN[1]">MISC:M0PIN[1]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:M1PIN" title="MISC:M1PIN[1]">MISC:M1PIN[1]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[0]">MISC:ZCLK_DIV2[0]</a></td><td><a href="#bits-xc2v-LL.V2-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[2]">MISC:ZCLK_DIV2[2]</a></td></tr>
 </table>
 <div id="bits-xc2v-LL.V2-DCI0:ENABLE"></div>
 <div id="bits-xc2v-LL.V2-DCI0:FORCE_DONE_HIGH"></div>
-<div id="bits-xc2v-LL.V2-DCI0:TERM_VCC"></div>
 <div id="bits-xc2v-LL.V2-DCI0:TEST_ENABLE"></div>
 <div id="bits-xc2v-LL.V2-DCI1:ENABLE"></div>
 <div id="bits-xc2v-LL.V2-DCI1:FORCE_DONE_HIGH"></div>
-<div id="bits-xc2v-LL.V2-DCI1:TERM_VCC"></div>
 <div id="bits-xc2v-LL.V2-DCI1:TEST_ENABLE"></div>
 <div id="bits-xc2v-LL.V2-MISC:DCI_ALTVR"></div>
 <div id="bits-xc2v-LL.V2-MISC:DCI_CLK_ENABLE"></div>
@@ -269,30 +267,40 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.V2</span></c
 <table class="docutils align-default prjcombine-enum">
 <tr><th>DCI0:ENABLE</th><th>[0, 2, 42]</th></tr>
 <tr><th>DCI0:FORCE_DONE_HIGH</th><th>[0, 3, 31]</th></tr>
-<tr><th>DCI0:TERM_VCC</th><th>[0, 3, 36]</th></tr>
 <tr><th>DCI0:TEST_ENABLE</th><th>[0, 2, 31]</th></tr>
 <tr><th>DCI1:ENABLE</th><th>[1, 10, 7]</th></tr>
 <tr><th>DCI1:FORCE_DONE_HIGH</th><th>[1, 9, 8]</th></tr>
-<tr><th>DCI1:TERM_VCC</th><th>[1, 8, 8]</th></tr>
 <tr><th>DCI1:TEST_ENABLE</th><th>[1, 9, 6]</th></tr>
 <tr><th>MISC:DCI_ALTVR</th><th>[1, 18, 9]</th></tr>
 <tr><th>MISC:DCI_CLK_ENABLE</th><th>[1, 18, 10]</th></tr>
 <tr><th>MISC:DISABLEBANDGAP</th><th>[1, 16, 6]</th></tr>
 <tr><td>Non-inverted</td><td>[0]</td></tr>
 </table>
-<div id="bits-xc2v-LL.V2-DCI0:TERM_SPLIT"></div>
-<div id="bits-xc2v-LL.V2-DCI1:TERM_SPLIT"></div>
+<div id="bits-xc2v-LL.V2-DCI0:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LL.V2-DCI0:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LL.V2-DCI0:PMASK_TERM_VCC"></div>
+<div id="bits-xc2v-LL.V2-DCI1:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LL.V2-DCI1:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LL.V2-DCI1:PMASK_TERM_VCC"></div>
+<div id="bits-xc2v-LL.V2-MISC:BCLK_DIV2"></div>
+<div id="bits-xc2v-LL.V2-MISC:ZCLK_DIV2"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_SPLIT</th><th>[0, 3, 38]</th><th>[0, 2, 34]</th><th>[0, 2, 38]</th><th>[0, 2, 33]</th><th>[0, 3, 32]</th><th>[0, 2, 37]</th><th>[0, 2, 32]</th></tr>
-<tr><th>DCI1:TERM_SPLIT</th><th>[1, 11, 7]</th><th>[1, 8, 9]</th><th>[1, 11, 10]</th><th>[1, 9, 11]</th><th>[1, 11, 6]</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th></tr>
-<tr><td>Non-inverted</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>DCI0:NMASK_TERM_SPLIT</th><th>[0, 2, 37]</th><th>[0, 3, 37]</th><th>[0, 2, 38]</th><th>[0, 3, 38]</th><th>[0, 2, 39]</th></tr>
+<tr><th>DCI0:PMASK_TERM_SPLIT</th><th>[0, 2, 32]</th><th>[0, 3, 32]</th><th>[0, 2, 33]</th><th>[0, 3, 33]</th><th>[0, 2, 34]</th></tr>
+<tr><th>DCI0:PMASK_TERM_VCC</th><th>[0, 3, 34]</th><th>[0, 2, 35]</th><th>[0, 3, 35]</th><th>[0, 2, 36]</th><th>[0, 3, 36]</th></tr>
+<tr><th>DCI1:NMASK_TERM_SPLIT</th><th>[1, 11, 6]</th><th>[1, 11, 8]</th><th>[1, 11, 10]</th><th>[1, 11, 7]</th><th>[1, 11, 11]</th></tr>
+<tr><th>DCI1:PMASK_TERM_SPLIT</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th><th>[1, 9, 11]</th><th>[1, 9, 9]</th><th>[1, 8, 9]</th></tr>
+<tr><th>DCI1:PMASK_TERM_VCC</th><th>[1, 8, 10]</th><th>[1, 8, 11]</th><th>[1, 8, 7]</th><th>[1, 8, 6]</th><th>[1, 8, 8]</th></tr>
+<tr><th>MISC:BCLK_DIV2</th><th>[1, 17, 8]</th><th>[1, 17, 7]</th><th>[1, 17, 6]</th><th>[1, 17, 9]</th><th>[1, 17, 10]</th></tr>
+<tr><th>MISC:ZCLK_DIV2</th><th>[1, 19, 10]</th><th>[1, 19, 7]</th><th>[1, 19, 11]</th><th>[1, 19, 9]</th><th>[1, 18, 11]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc2v-LL.V2-DCI0:LVDSBIAS"></div>
 <div id="bits-xc2v-LL.V2-DCI1:LVDSBIAS"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 46]</th><th>[0, 3, 48]</th><th>[0, 3, 45]</th></tr>
-<tr><th>DCI1:LVDSBIAS</th><th>[1, 12, 11]</th><th>[1, 13, 9]</th><th>[1, 12, 8]</th></tr>
-<tr><td>Non-inverted</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 44]</th><th>[0, 2, 45]</th><th>[0, 3, 45]</th><th>[0, 2, 46]</th><th>[0, 3, 46]</th><th>[0, 2, 47]</th><th>[0, 3, 47]</th><th>[0, 2, 48]</th><th>[0, 3, 48]</th></tr>
+<tr><th>DCI1:LVDSBIAS</th><th>[1, 13, 7]</th><th>[1, 13, 11]</th><th>[1, 13, 9]</th><th>[1, 12, 9]</th><th>[1, 12, 11]</th><th>[1, 12, 10]</th><th>[1, 12, 7]</th><th>[1, 12, 6]</th><th>[1, 12, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc2v-LL.V2-MISC:M0PIN"></div>
 <div id="bits-xc2v-LL.V2-MISC:M1PIN"></div>
@@ -305,13 +313,6 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.V2</span></c
 <tr><td>PULLDOWN</td><td>0</td><td>1</td></tr>
 <tr><td>PULLNONE</td><td>1</td><td>0</td></tr>
 </table>
-<div id="bits-xc2v-LL.V2-MISC:BCLK_DIV2"></div>
-<div id="bits-xc2v-LL.V2-MISC:ZCLK_DIV2"></div>
-<table class="docutils align-default prjcombine-enum">
-<tr><th>MISC:BCLK_DIV2</th><th>[1, 17, 8]</th><th>[1, 17, 7]</th><th>[1, 17, 6]</th><th>[1, 17, 9]</th><th>[1, 17, 10]</th></tr>
-<tr><th>MISC:ZCLK_DIV2</th><th>[1, 19, 10]</th><th>[1, 19, 7]</th><th>[1, 19, 11]</th><th>[1, 19, 9]</th><th>[1, 18, 11]</th></tr>
-<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
-</table>
 <div id="bits-xc2v-LL.V2-MISC:RAISEVGG"></div>
 <table class="docutils align-default prjcombine-enum">
 <tr><th>MISC:RAISEVGG</th><th>[1, 19, 8]</th><th>[1, 19, 6]</th></tr>
@@ -388,21 +389,21 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.V2P</span></
 <tr><td>31</td>
 <td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:TEST_ENABLE" title="DCI0:TEST_ENABLE">DCI0:TEST_ENABLE</a></td><td><a href="#bits-xc2v-LL.V2P-DCI0:FORCE_DONE_HIGH" title="DCI0:FORCE_DONE_HIGH">DCI0:FORCE_DONE_HIGH</a></td></tr>
 <tr><td>32</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[3]">DCI0:TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[5]">DCI0:TERM_SPLIT[5]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[4]">DCI0:PMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[3]">DCI0:PMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>33</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[2]">DCI0:TERM_SPLIT[2]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[2]">DCI0:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[1]">DCI0:PMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>34</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[4]">DCI0:TERM_SPLIT[4]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[0]">DCI0:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[4]">DCI0:PMASK_TERM_VCC[4]</a></td></tr>
 <tr><td>35</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:TERM_VCC" title="DCI0:TERM_VCC">DCI0:TERM_VCC</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[3]">DCI0:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[2]">DCI0:PMASK_TERM_VCC[2]</a></td></tr>
 <tr><td>36</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[1]">DCI0:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[0]">DCI0:PMASK_TERM_VCC[0]</a></td></tr>
 <tr><td>37</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[0]">DCI0:TERM_SPLIT[0]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[4]">DCI0:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[3]">DCI0:NMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>38</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[1]">DCI0:TERM_SPLIT[1]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[6]">DCI0:TERM_SPLIT[6]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[2]">DCI0:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[1]">DCI0:NMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>39</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:QUIET" title="DCI0:QUIET">DCI0:QUIET</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[0]">DCI0:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI0:QUIET" title="DCI0:QUIET">DCI0:QUIET</a></td></tr>
 <tr><td>40</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>41</td>
@@ -412,15 +413,15 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.V2P</span></
 <tr><td>43</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>44</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td></tr>
 <tr><td>45</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[6]">DCI0:LVDSBIAS[6]</a></td></tr>
 <tr><td>46</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td></tr>
 <tr><td>47</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
 <tr><td>48</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
 </table>
 <table class="docutils align-default prjcombine-tile">
 <tr><th colspan="21">LL.V2P bittile 1</th></tr><tr><th rowspan="2">Row</th><th colspan="20">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th></tr>
@@ -437,27 +438,25 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.V2P</span></
 <tr><td>5</td>
 <td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>6</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[0]">DCI1:TERM_SPLIT[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:DISABLEBANDGAP" title="MISC:DISABLEBANDGAP">MISC:DISABLEBANDGAP</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[2]">MISC:BCLK_DIV2[2]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:RAISEVGG" title="MISC:RAISEVGG[0]">MISC:RAISEVGG[0]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[1]">DCI1:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[4]">DCI1:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:DISABLEBANDGAP" title="MISC:DISABLEBANDGAP">MISC:DISABLEBANDGAP</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[2]">MISC:BCLK_DIV2[2]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:RAISEVGG" title="MISC:RAISEVGG[0]">MISC:RAISEVGG[0]</a></td></tr>
 <tr><td>7</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:TERM_VCC" title="DCI1:TERM_VCC">DCI1:TERM_VCC</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[4]">DCI1:TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[6]">DCI1:TERM_SPLIT[6]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:M2PIN" title="MISC:M2PIN[0]">MISC:M2PIN[0]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[3]">MISC:BCLK_DIV2[3]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[3]">MISC:ZCLK_DIV2[3]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[2]">DCI1:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[3]">DCI1:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[1]">DCI1:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:M2PIN" title="MISC:M2PIN[0]">MISC:M2PIN[0]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[3]">MISC:BCLK_DIV2[3]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[3]">MISC:ZCLK_DIV2[3]</a></td></tr>
 <tr><td>8</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:M2PIN" title="MISC:M2PIN[1]">MISC:M2PIN[1]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[4]">MISC:BCLK_DIV2[4]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:DISABLEVGGGENERATION" title="MISC:DISABLEVGGGENERATION">MISC:DISABLEVGGGENERATION</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:RAISEVGG" title="MISC:RAISEVGG[1]">MISC:RAISEVGG[1]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[0]">DCI1:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[3]">DCI1:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:M2PIN" title="MISC:M2PIN[1]">MISC:M2PIN[1]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[4]">MISC:BCLK_DIV2[4]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:DISABLEVGGGENERATION" title="MISC:DISABLEVGGGENERATION">MISC:DISABLEVGGGENERATION</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:RAISEVGG" title="MISC:RAISEVGG[1]">MISC:RAISEVGG[1]</a></td></tr>
 <tr><td>9</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[3]">DCI1:TERM_SPLIT[3]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:QUIET" title="DCI1:QUIET">DCI1:QUIET</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:M1PIN" title="MISC:M1PIN[0]">MISC:M1PIN[0]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[1]">MISC:BCLK_DIV2[1]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[1]">MISC:ZCLK_DIV2[1]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[0]">DCI1:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[1]">DCI1:PMASK_TERM_SPLIT[1]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:QUIET" title="DCI1:QUIET">DCI1:QUIET</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[6]">DCI1:LVDSBIAS[6]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:M1PIN" title="MISC:M1PIN[0]">MISC:M1PIN[0]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[1]">MISC:BCLK_DIV2[1]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[1]">MISC:ZCLK_DIV2[1]</a></td></tr>
 <tr><td>10</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[5]">DCI1:TERM_SPLIT[5]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[1]">DCI1:TERM_SPLIT[1]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:M0PIN" title="MISC:M0PIN[0]">MISC:M0PIN[0]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[0]">MISC:BCLK_DIV2[0]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:DCI_CLK_ENABLE" title="MISC:DCI_CLK_ENABLE">MISC:DCI_CLK_ENABLE</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[4]">MISC:ZCLK_DIV2[4]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[4]">DCI1:PMASK_TERM_VCC[4]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[4]">DCI1:PMASK_TERM_SPLIT[4]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[2]">DCI1:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:M0PIN" title="MISC:M0PIN[0]">MISC:M0PIN[0]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[0]">MISC:BCLK_DIV2[0]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:DCI_CLK_ENABLE" title="MISC:DCI_CLK_ENABLE">MISC:DCI_CLK_ENABLE</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[4]">MISC:ZCLK_DIV2[4]</a></td></tr>
 <tr><td>11</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[2]">DCI1:TERM_SPLIT[2]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:M0PIN" title="MISC:M0PIN[1]">MISC:M0PIN[1]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:M1PIN" title="MISC:M1PIN[1]">MISC:M1PIN[1]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[0]">MISC:ZCLK_DIV2[0]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[2]">MISC:ZCLK_DIV2[2]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[3]">DCI1:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[2]">DCI1:PMASK_TERM_SPLIT[2]</a></td><td>-</td><td><a href="#bits-xc2v-LL.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[0]">DCI1:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td><td><a href="#bits-xc2v-LL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL.V2P-MISC:M0PIN" title="MISC:M0PIN[1]">MISC:M0PIN[1]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:M1PIN" title="MISC:M1PIN[1]">MISC:M1PIN[1]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[0]">MISC:ZCLK_DIV2[0]</a></td><td><a href="#bits-xc2v-LL.V2P-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[2]">MISC:ZCLK_DIV2[2]</a></td></tr>
 </table>
 <div id="bits-xc2v-LL.V2P-DCI0:ENABLE"></div>
 <div id="bits-xc2v-LL.V2P-DCI0:FORCE_DONE_HIGH"></div>
 <div id="bits-xc2v-LL.V2P-DCI0:QUIET"></div>
-<div id="bits-xc2v-LL.V2P-DCI0:TERM_VCC"></div>
 <div id="bits-xc2v-LL.V2P-DCI0:TEST_ENABLE"></div>
 <div id="bits-xc2v-LL.V2P-DCI1:ENABLE"></div>
 <div id="bits-xc2v-LL.V2P-DCI1:FORCE_DONE_HIGH"></div>
 <div id="bits-xc2v-LL.V2P-DCI1:QUIET"></div>
-<div id="bits-xc2v-LL.V2P-DCI1:TERM_VCC"></div>
 <div id="bits-xc2v-LL.V2P-DCI1:TEST_ENABLE"></div>
 <div id="bits-xc2v-LL.V2P-MISC:DCI_CLK_ENABLE"></div>
 <div id="bits-xc2v-LL.V2P-MISC:DISABLEBANDGAP"></div>
@@ -466,33 +465,41 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.V2P</span></
 <tr><th>DCI0:ENABLE</th><th>[0, 2, 42]</th></tr>
 <tr><th>DCI0:FORCE_DONE_HIGH</th><th>[0, 3, 31]</th></tr>
 <tr><th>DCI0:QUIET</th><th>[0, 3, 39]</th></tr>
-<tr><th>DCI0:TERM_VCC</th><th>[0, 3, 35]</th></tr>
 <tr><th>DCI0:TEST_ENABLE</th><th>[0, 2, 31]</th></tr>
 <tr><th>DCI1:ENABLE</th><th>[1, 10, 7]</th></tr>
 <tr><th>DCI1:FORCE_DONE_HIGH</th><th>[1, 9, 8]</th></tr>
 <tr><th>DCI1:QUIET</th><th>[1, 11, 9]</th></tr>
-<tr><th>DCI1:TERM_VCC</th><th>[1, 8, 7]</th></tr>
 <tr><th>DCI1:TEST_ENABLE</th><th>[1, 9, 6]</th></tr>
 <tr><th>MISC:DCI_CLK_ENABLE</th><th>[1, 18, 10]</th></tr>
 <tr><th>MISC:DISABLEBANDGAP</th><th>[1, 16, 6]</th></tr>
 <tr><th>MISC:DISABLEVGGGENERATION</th><th>[1, 18, 8]</th></tr>
 <tr><td>Non-inverted</td><td>[0]</td></tr>
 </table>
-<div id="bits-xc2v-LL.V2P-DCI0:TERM_SPLIT"></div>
-<div id="bits-xc2v-LL.V2P-DCI1:TERM_SPLIT"></div>
+<div id="bits-xc2v-LL.V2P-DCI0:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LL.V2P-DCI0:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LL.V2P-DCI0:PMASK_TERM_VCC"></div>
+<div id="bits-xc2v-LL.V2P-DCI1:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LL.V2P-DCI1:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LL.V2P-DCI1:PMASK_TERM_VCC"></div>
+<div id="bits-xc2v-LL.V2P-MISC:BCLK_DIV2"></div>
+<div id="bits-xc2v-LL.V2P-MISC:ZCLK_DIV2"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_SPLIT</th><th>[0, 3, 38]</th><th>[0, 3, 32]</th><th>[0, 2, 34]</th><th>[0, 2, 32]</th><th>[0, 2, 33]</th><th>[0, 2, 38]</th><th>[0, 2, 37]</th></tr>
-<tr><th>DCI1:TERM_SPLIT</th><th>[1, 11, 7]</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th><th>[1, 8, 9]</th><th>[1, 9, 11]</th><th>[1, 11, 10]</th><th>[1, 11, 6]</th></tr>
-<tr><td>Non-inverted</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>DCI0:NMASK_TERM_SPLIT</th><th>[0, 2, 37]</th><th>[0, 3, 37]</th><th>[0, 2, 38]</th><th>[0, 3, 38]</th><th>[0, 2, 39]</th></tr>
+<tr><th>DCI0:PMASK_TERM_SPLIT</th><th>[0, 2, 32]</th><th>[0, 3, 32]</th><th>[0, 2, 33]</th><th>[0, 3, 33]</th><th>[0, 2, 34]</th></tr>
+<tr><th>DCI0:PMASK_TERM_VCC</th><th>[0, 3, 34]</th><th>[0, 2, 35]</th><th>[0, 3, 35]</th><th>[0, 2, 36]</th><th>[0, 3, 36]</th></tr>
+<tr><th>DCI1:NMASK_TERM_SPLIT</th><th>[1, 11, 6]</th><th>[1, 11, 8]</th><th>[1, 11, 10]</th><th>[1, 11, 7]</th><th>[1, 11, 11]</th></tr>
+<tr><th>DCI1:PMASK_TERM_SPLIT</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th><th>[1, 9, 11]</th><th>[1, 9, 9]</th><th>[1, 8, 9]</th></tr>
+<tr><th>DCI1:PMASK_TERM_VCC</th><th>[1, 8, 10]</th><th>[1, 8, 11]</th><th>[1, 8, 7]</th><th>[1, 8, 6]</th><th>[1, 8, 8]</th></tr>
+<tr><th>MISC:BCLK_DIV2</th><th>[1, 17, 8]</th><th>[1, 17, 7]</th><th>[1, 17, 6]</th><th>[1, 17, 9]</th><th>[1, 17, 10]</th></tr>
+<tr><th>MISC:ZCLK_DIV2</th><th>[1, 19, 10]</th><th>[1, 19, 7]</th><th>[1, 19, 11]</th><th>[1, 19, 9]</th><th>[1, 18, 11]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc2v-LL.V2P-DCI0:LVDSBIAS"></div>
 <div id="bits-xc2v-LL.V2P-DCI1:LVDSBIAS"></div>
-<div id="bits-xc2v-LL.V2P-MISC:RAISEVGG"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 48]</th><th>[0, 2, 46]</th></tr>
-<tr><th>DCI1:LVDSBIAS</th><th>[1, 12, 9]</th><th>[1, 12, 8]</th></tr>
-<tr><th>MISC:RAISEVGG</th><th>[1, 19, 8]</th><th>[1, 19, 6]</th></tr>
-<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 44]</th><th>[0, 2, 45]</th><th>[0, 3, 45]</th><th>[0, 2, 46]</th><th>[0, 3, 46]</th><th>[0, 2, 47]</th><th>[0, 3, 47]</th><th>[0, 2, 48]</th><th>[0, 3, 48]</th></tr>
+<tr><th>DCI1:LVDSBIAS</th><th>[1, 13, 7]</th><th>[1, 13, 11]</th><th>[1, 13, 9]</th><th>[1, 12, 9]</th><th>[1, 12, 11]</th><th>[1, 12, 10]</th><th>[1, 12, 7]</th><th>[1, 12, 6]</th><th>[1, 12, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc2v-LL.V2P-MISC:M0PIN"></div>
 <div id="bits-xc2v-LL.V2P-MISC:M1PIN"></div>
@@ -505,12 +512,10 @@ <h3><code class="docutils literal notranslate"><span class="pre">LL.V2P</span></
 <tr><td>PULLDOWN</td><td>0</td><td>1</td></tr>
 <tr><td>PULLNONE</td><td>1</td><td>0</td></tr>
 </table>
-<div id="bits-xc2v-LL.V2P-MISC:BCLK_DIV2"></div>
-<div id="bits-xc2v-LL.V2P-MISC:ZCLK_DIV2"></div>
+<div id="bits-xc2v-LL.V2P-MISC:RAISEVGG"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>MISC:BCLK_DIV2</th><th>[1, 17, 8]</th><th>[1, 17, 7]</th><th>[1, 17, 6]</th><th>[1, 17, 9]</th><th>[1, 17, 10]</th></tr>
-<tr><th>MISC:ZCLK_DIV2</th><th>[1, 19, 10]</th><th>[1, 19, 7]</th><th>[1, 19, 11]</th><th>[1, 19, 9]</th><th>[1, 18, 11]</th></tr>
-<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>MISC:RAISEVGG</th><th>[1, 19, 8]</th><th>[1, 19, 6]</th></tr>
+<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
 </table>
 </section>
 </section>
@@ -590,21 +595,21 @@ <h3><code class="docutils literal notranslate"><span class="pre">UL.V2</span></c
 <tr><td>31</td>
 <td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:TEST_ENABLE" title="DCI0:TEST_ENABLE">DCI0:TEST_ENABLE</a></td><td><a href="#bits-xc2v-UL.V2-DCI0:FORCE_DONE_HIGH" title="DCI0:FORCE_DONE_HIGH">DCI0:FORCE_DONE_HIGH</a></td></tr>
 <tr><td>32</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[0]">DCI0:TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UL.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[2]">DCI0:TERM_SPLIT[2]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[4]">DCI0:PMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UL.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[3]">DCI0:PMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>33</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[3]">DCI0:TERM_SPLIT[3]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[2]">DCI0:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-UL.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[1]">DCI0:PMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>34</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[5]">DCI0:TERM_SPLIT[5]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[0]">DCI0:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UL.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[4]">DCI0:PMASK_TERM_VCC[4]</a></td></tr>
 <tr><td>35</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[3]">DCI0:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-UL.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[2]">DCI0:PMASK_TERM_VCC[2]</a></td></tr>
 <tr><td>36</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:TERM_VCC" title="DCI0:TERM_VCC">DCI0:TERM_VCC</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[1]">DCI0:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-UL.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[0]">DCI0:PMASK_TERM_VCC[0]</a></td></tr>
 <tr><td>37</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[1]">DCI0:TERM_SPLIT[1]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[4]">DCI0:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UL.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[3]">DCI0:NMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>38</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[4]">DCI0:TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UL.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[6]">DCI0:TERM_SPLIT[6]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[2]">DCI0:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-UL.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[1]">DCI0:NMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>39</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[0]">DCI0:NMASK_TERM_SPLIT[0]</a></td><td>-</td></tr>
 <tr><td>40</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>41</td>
@@ -614,15 +619,15 @@ <h3><code class="docutils literal notranslate"><span class="pre">UL.V2</span></c
 <tr><td>43</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>44</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td></tr>
 <tr><td>45</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td><td><a href="#bits-xc2v-UL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[6]">DCI0:LVDSBIAS[6]</a></td></tr>
 <tr><td>46</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-UL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td></tr>
 <tr><td>47</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td><td><a href="#bits-xc2v-UL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
 <tr><td>48</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td><td><a href="#bits-xc2v-UL.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
 </table>
 <table class="docutils align-default prjcombine-tile">
 <tr><th colspan="15">UL.V2 bittile 1</th></tr><tr><th rowspan="2">Row</th><th colspan="14">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th></tr>
@@ -639,52 +644,56 @@ <h3><code class="docutils literal notranslate"><span class="pre">UL.V2</span></c
 <tr><td>5</td>
 <td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>6</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-MISC:TDIPIN" title="MISC:TDIPIN[1]">MISC:TDIPIN[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[2]">DCI1:TERM_SPLIT[2]</a></td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-MISC:TDIPIN" title="MISC:TDIPIN[1]">MISC:TDIPIN[1]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[1]">DCI1:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[4]">DCI1:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td><td>-</td></tr>
 <tr><td>7</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-MISC:TDIPIN" title="MISC:TDIPIN[0]">MISC:TDIPIN[0]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[0]">DCI1:TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[6]">DCI1:TERM_SPLIT[6]</a></td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-MISC:TDIPIN" title="MISC:TDIPIN[0]">MISC:TDIPIN[0]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[2]">DCI1:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[3]">DCI1:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[1]">DCI1:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td></tr>
 <tr><td>8</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-MISC:HSWAPENPIN" title="MISC:HSWAPENPIN[1]">MISC:HSWAPENPIN[1]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:TERM_VCC" title="DCI1:TERM_VCC">DCI1:TERM_VCC</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-MISC:HSWAPENPIN" title="MISC:HSWAPENPIN[1]">MISC:HSWAPENPIN[1]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[0]">DCI1:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[3]">DCI1:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td><td>-</td></tr>
 <tr><td>9</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-MISC:TEST_LL" title="MISC:TEST_LL">MISC:TEST_LL</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[5]">DCI1:TERM_SPLIT[5]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-MISC:TEST_LL" title="MISC:TEST_LL">MISC:TEST_LL</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[0]">DCI1:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[1]">DCI1:PMASK_TERM_SPLIT[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[6]">DCI1:LVDSBIAS[6]</a></td></tr>
 <tr><td>10</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-MISC:HSWAPENPIN" title="MISC:HSWAPENPIN[0]">MISC:HSWAPENPIN[0]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[1]">DCI1:TERM_SPLIT[1]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[4]">DCI1:TERM_SPLIT[4]</a></td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-MISC:HSWAPENPIN" title="MISC:HSWAPENPIN[0]">MISC:HSWAPENPIN[0]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[4]">DCI1:PMASK_TERM_VCC[4]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[4]">DCI1:PMASK_TERM_SPLIT[4]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[2]">DCI1:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td><td>-</td></tr>
 <tr><td>11</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-MISC:PROGPIN" title="MISC:PROGPIN">MISC:PROGPIN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[3]">DCI1:TERM_SPLIT[3]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2-MISC:PROGPIN" title="MISC:PROGPIN">MISC:PROGPIN</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[3]">DCI1:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[2]">DCI1:PMASK_TERM_SPLIT[2]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[0]">DCI1:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td><td><a href="#bits-xc2v-UL.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td></tr>
 </table>
 <div id="bits-xc2v-UL.V2-DCI0:ENABLE"></div>
 <div id="bits-xc2v-UL.V2-DCI0:FORCE_DONE_HIGH"></div>
-<div id="bits-xc2v-UL.V2-DCI0:TERM_VCC"></div>
 <div id="bits-xc2v-UL.V2-DCI0:TEST_ENABLE"></div>
 <div id="bits-xc2v-UL.V2-DCI1:ENABLE"></div>
 <div id="bits-xc2v-UL.V2-DCI1:FORCE_DONE_HIGH"></div>
-<div id="bits-xc2v-UL.V2-DCI1:TERM_VCC"></div>
 <div id="bits-xc2v-UL.V2-DCI1:TEST_ENABLE"></div>
 <div id="bits-xc2v-UL.V2-MISC:TEST_LL"></div>
 <table class="docutils align-default prjcombine-enum">
 <tr><th>DCI0:ENABLE</th><th>[0, 2, 42]</th></tr>
 <tr><th>DCI0:FORCE_DONE_HIGH</th><th>[0, 3, 31]</th></tr>
-<tr><th>DCI0:TERM_VCC</th><th>[0, 3, 36]</th></tr>
 <tr><th>DCI0:TEST_ENABLE</th><th>[0, 2, 31]</th></tr>
 <tr><th>DCI1:ENABLE</th><th>[1, 10, 7]</th></tr>
 <tr><th>DCI1:FORCE_DONE_HIGH</th><th>[1, 9, 8]</th></tr>
-<tr><th>DCI1:TERM_VCC</th><th>[1, 8, 8]</th></tr>
 <tr><th>DCI1:TEST_ENABLE</th><th>[1, 9, 6]</th></tr>
 <tr><th>MISC:TEST_LL</th><th>[1, 6, 9]</th></tr>
 <tr><td>Non-inverted</td><td>[0]</td></tr>
 </table>
-<div id="bits-xc2v-UL.V2-DCI0:TERM_SPLIT"></div>
-<div id="bits-xc2v-UL.V2-DCI1:TERM_SPLIT"></div>
+<div id="bits-xc2v-UL.V2-DCI0:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UL.V2-DCI0:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UL.V2-DCI0:PMASK_TERM_VCC"></div>
+<div id="bits-xc2v-UL.V2-DCI1:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UL.V2-DCI1:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UL.V2-DCI1:PMASK_TERM_VCC"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_SPLIT</th><th>[0, 3, 38]</th><th>[0, 2, 34]</th><th>[0, 2, 38]</th><th>[0, 2, 33]</th><th>[0, 3, 32]</th><th>[0, 2, 37]</th><th>[0, 2, 32]</th></tr>
-<tr><th>DCI1:TERM_SPLIT</th><th>[1, 11, 7]</th><th>[1, 8, 9]</th><th>[1, 11, 10]</th><th>[1, 9, 11]</th><th>[1, 11, 6]</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th></tr>
-<tr><td>Non-inverted</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>DCI0:NMASK_TERM_SPLIT</th><th>[0, 2, 37]</th><th>[0, 3, 37]</th><th>[0, 2, 38]</th><th>[0, 3, 38]</th><th>[0, 2, 39]</th></tr>
+<tr><th>DCI0:PMASK_TERM_SPLIT</th><th>[0, 2, 32]</th><th>[0, 3, 32]</th><th>[0, 2, 33]</th><th>[0, 3, 33]</th><th>[0, 2, 34]</th></tr>
+<tr><th>DCI0:PMASK_TERM_VCC</th><th>[0, 3, 34]</th><th>[0, 2, 35]</th><th>[0, 3, 35]</th><th>[0, 2, 36]</th><th>[0, 3, 36]</th></tr>
+<tr><th>DCI1:NMASK_TERM_SPLIT</th><th>[1, 11, 6]</th><th>[1, 11, 8]</th><th>[1, 11, 10]</th><th>[1, 11, 7]</th><th>[1, 11, 11]</th></tr>
+<tr><th>DCI1:PMASK_TERM_SPLIT</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th><th>[1, 9, 11]</th><th>[1, 9, 9]</th><th>[1, 8, 9]</th></tr>
+<tr><th>DCI1:PMASK_TERM_VCC</th><th>[1, 8, 10]</th><th>[1, 8, 11]</th><th>[1, 8, 7]</th><th>[1, 8, 6]</th><th>[1, 8, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc2v-UL.V2-DCI0:LVDSBIAS"></div>
 <div id="bits-xc2v-UL.V2-DCI1:LVDSBIAS"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 46]</th><th>[0, 3, 48]</th><th>[0, 3, 45]</th></tr>
-<tr><th>DCI1:LVDSBIAS</th><th>[1, 12, 11]</th><th>[1, 13, 9]</th><th>[1, 12, 8]</th></tr>
-<tr><td>Non-inverted</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 44]</th><th>[0, 2, 45]</th><th>[0, 3, 45]</th><th>[0, 2, 46]</th><th>[0, 3, 46]</th><th>[0, 2, 47]</th><th>[0, 3, 47]</th><th>[0, 2, 48]</th><th>[0, 3, 48]</th></tr>
+<tr><th>DCI1:LVDSBIAS</th><th>[1, 13, 7]</th><th>[1, 13, 11]</th><th>[1, 13, 9]</th><th>[1, 12, 9]</th><th>[1, 12, 11]</th><th>[1, 12, 10]</th><th>[1, 12, 7]</th><th>[1, 12, 6]</th><th>[1, 12, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc2v-UL.V2-MISC:HSWAPENPIN"></div>
 <div id="bits-xc2v-UL.V2-MISC:TDIPIN"></div>
@@ -772,21 +781,21 @@ <h3><code class="docutils literal notranslate"><span class="pre">UL.V2P</span></
 <tr><td>31</td>
 <td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:TEST_ENABLE" title="DCI0:TEST_ENABLE">DCI0:TEST_ENABLE</a></td><td><a href="#bits-xc2v-UL.V2P-DCI0:FORCE_DONE_HIGH" title="DCI0:FORCE_DONE_HIGH">DCI0:FORCE_DONE_HIGH</a></td></tr>
 <tr><td>32</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[3]">DCI0:TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[5]">DCI0:TERM_SPLIT[5]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[4]">DCI0:PMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[3]">DCI0:PMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>33</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[2]">DCI0:TERM_SPLIT[2]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[2]">DCI0:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[1]">DCI0:PMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>34</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[4]">DCI0:TERM_SPLIT[4]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[0]">DCI0:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[4]">DCI0:PMASK_TERM_VCC[4]</a></td></tr>
 <tr><td>35</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:TERM_VCC" title="DCI0:TERM_VCC">DCI0:TERM_VCC</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[3]">DCI0:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[2]">DCI0:PMASK_TERM_VCC[2]</a></td></tr>
 <tr><td>36</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[1]">DCI0:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[0]">DCI0:PMASK_TERM_VCC[0]</a></td></tr>
 <tr><td>37</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[0]">DCI0:TERM_SPLIT[0]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[4]">DCI0:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[3]">DCI0:NMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>38</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[1]">DCI0:TERM_SPLIT[1]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[6]">DCI0:TERM_SPLIT[6]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[2]">DCI0:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[1]">DCI0:NMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>39</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:QUIET" title="DCI0:QUIET">DCI0:QUIET</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[0]">DCI0:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI0:QUIET" title="DCI0:QUIET">DCI0:QUIET</a></td></tr>
 <tr><td>40</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>41</td>
@@ -796,81 +805,85 @@ <h3><code class="docutils literal notranslate"><span class="pre">UL.V2P</span></
 <tr><td>43</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>44</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td></tr>
 <tr><td>45</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[6]">DCI0:LVDSBIAS[6]</a></td></tr>
 <tr><td>46</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td></tr>
 <tr><td>47</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
 <tr><td>48</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
 </table>
 <table class="docutils align-default prjcombine-tile">
-<tr><th colspan="14">UL.V2P bittile 1</th></tr><tr><th rowspan="2">Row</th><th colspan="13">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th></tr>
+<tr><th colspan="15">UL.V2P bittile 1</th></tr><tr><th rowspan="2">Row</th><th colspan="14">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th></tr>
 <tr><td>0</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>1</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>2</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>3</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>4</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>5</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>6</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-MISC:TDIPIN" title="MISC:TDIPIN[1]">MISC:TDIPIN[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[0]">DCI1:TERM_SPLIT[0]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-MISC:TDIPIN" title="MISC:TDIPIN[1]">MISC:TDIPIN[1]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[1]">DCI1:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[4]">DCI1:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td><td>-</td></tr>
 <tr><td>7</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-MISC:TDIPIN" title="MISC:TDIPIN[0]">MISC:TDIPIN[0]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:TERM_VCC" title="DCI1:TERM_VCC">DCI1:TERM_VCC</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[4]">DCI1:TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[6]">DCI1:TERM_SPLIT[6]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-MISC:TDIPIN" title="MISC:TDIPIN[0]">MISC:TDIPIN[0]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[2]">DCI1:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[3]">DCI1:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[1]">DCI1:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td></tr>
 <tr><td>8</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-MISC:HSWAPENPIN" title="MISC:HSWAPENPIN[1]">MISC:HSWAPENPIN[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-MISC:HSWAPENPIN" title="MISC:HSWAPENPIN[1]">MISC:HSWAPENPIN[1]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[0]">DCI1:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[3]">DCI1:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td><td>-</td></tr>
 <tr><td>9</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-MISC:TEST_LL" title="MISC:TEST_LL">MISC:TEST_LL</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[3]">DCI1:TERM_SPLIT[3]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:QUIET" title="DCI1:QUIET">DCI1:QUIET</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-MISC:TEST_LL" title="MISC:TEST_LL">MISC:TEST_LL</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[0]">DCI1:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[1]">DCI1:PMASK_TERM_SPLIT[1]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:QUIET" title="DCI1:QUIET">DCI1:QUIET</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[6]">DCI1:LVDSBIAS[6]</a></td></tr>
 <tr><td>10</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-MISC:HSWAPENPIN" title="MISC:HSWAPENPIN[0]">MISC:HSWAPENPIN[0]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[5]">DCI1:TERM_SPLIT[5]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[1]">DCI1:TERM_SPLIT[1]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-MISC:HSWAPENPIN" title="MISC:HSWAPENPIN[0]">MISC:HSWAPENPIN[0]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[4]">DCI1:PMASK_TERM_VCC[4]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[4]">DCI1:PMASK_TERM_SPLIT[4]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[2]">DCI1:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td><td>-</td></tr>
 <tr><td>11</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-MISC:PROGPIN" title="MISC:PROGPIN">MISC:PROGPIN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[2]">DCI1:TERM_SPLIT[2]</a></td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL.V2P-MISC:PROGPIN" title="MISC:PROGPIN">MISC:PROGPIN</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[3]">DCI1:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[2]">DCI1:PMASK_TERM_SPLIT[2]</a></td><td>-</td><td><a href="#bits-xc2v-UL.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[0]">DCI1:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td><td><a href="#bits-xc2v-UL.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td></tr>
 </table>
 <div id="bits-xc2v-UL.V2P-DCI0:ENABLE"></div>
 <div id="bits-xc2v-UL.V2P-DCI0:FORCE_DONE_HIGH"></div>
 <div id="bits-xc2v-UL.V2P-DCI0:QUIET"></div>
-<div id="bits-xc2v-UL.V2P-DCI0:TERM_VCC"></div>
 <div id="bits-xc2v-UL.V2P-DCI0:TEST_ENABLE"></div>
 <div id="bits-xc2v-UL.V2P-DCI1:ENABLE"></div>
 <div id="bits-xc2v-UL.V2P-DCI1:FORCE_DONE_HIGH"></div>
 <div id="bits-xc2v-UL.V2P-DCI1:QUIET"></div>
-<div id="bits-xc2v-UL.V2P-DCI1:TERM_VCC"></div>
 <div id="bits-xc2v-UL.V2P-DCI1:TEST_ENABLE"></div>
 <div id="bits-xc2v-UL.V2P-MISC:TEST_LL"></div>
 <table class="docutils align-default prjcombine-enum">
 <tr><th>DCI0:ENABLE</th><th>[0, 2, 42]</th></tr>
 <tr><th>DCI0:FORCE_DONE_HIGH</th><th>[0, 3, 31]</th></tr>
 <tr><th>DCI0:QUIET</th><th>[0, 3, 39]</th></tr>
-<tr><th>DCI0:TERM_VCC</th><th>[0, 3, 35]</th></tr>
 <tr><th>DCI0:TEST_ENABLE</th><th>[0, 2, 31]</th></tr>
 <tr><th>DCI1:ENABLE</th><th>[1, 10, 7]</th></tr>
 <tr><th>DCI1:FORCE_DONE_HIGH</th><th>[1, 9, 8]</th></tr>
 <tr><th>DCI1:QUIET</th><th>[1, 11, 9]</th></tr>
-<tr><th>DCI1:TERM_VCC</th><th>[1, 8, 7]</th></tr>
 <tr><th>DCI1:TEST_ENABLE</th><th>[1, 9, 6]</th></tr>
 <tr><th>MISC:TEST_LL</th><th>[1, 6, 9]</th></tr>
 <tr><td>Non-inverted</td><td>[0]</td></tr>
 </table>
-<div id="bits-xc2v-UL.V2P-DCI0:TERM_SPLIT"></div>
-<div id="bits-xc2v-UL.V2P-DCI1:TERM_SPLIT"></div>
+<div id="bits-xc2v-UL.V2P-DCI0:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UL.V2P-DCI0:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UL.V2P-DCI0:PMASK_TERM_VCC"></div>
+<div id="bits-xc2v-UL.V2P-DCI1:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UL.V2P-DCI1:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UL.V2P-DCI1:PMASK_TERM_VCC"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_SPLIT</th><th>[0, 3, 38]</th><th>[0, 3, 32]</th><th>[0, 2, 34]</th><th>[0, 2, 32]</th><th>[0, 2, 33]</th><th>[0, 2, 38]</th><th>[0, 2, 37]</th></tr>
-<tr><th>DCI1:TERM_SPLIT</th><th>[1, 11, 7]</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th><th>[1, 8, 9]</th><th>[1, 9, 11]</th><th>[1, 11, 10]</th><th>[1, 11, 6]</th></tr>
-<tr><td>Non-inverted</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>DCI0:NMASK_TERM_SPLIT</th><th>[0, 2, 37]</th><th>[0, 3, 37]</th><th>[0, 2, 38]</th><th>[0, 3, 38]</th><th>[0, 2, 39]</th></tr>
+<tr><th>DCI0:PMASK_TERM_SPLIT</th><th>[0, 2, 32]</th><th>[0, 3, 32]</th><th>[0, 2, 33]</th><th>[0, 3, 33]</th><th>[0, 2, 34]</th></tr>
+<tr><th>DCI0:PMASK_TERM_VCC</th><th>[0, 3, 34]</th><th>[0, 2, 35]</th><th>[0, 3, 35]</th><th>[0, 2, 36]</th><th>[0, 3, 36]</th></tr>
+<tr><th>DCI1:NMASK_TERM_SPLIT</th><th>[1, 11, 6]</th><th>[1, 11, 8]</th><th>[1, 11, 10]</th><th>[1, 11, 7]</th><th>[1, 11, 11]</th></tr>
+<tr><th>DCI1:PMASK_TERM_SPLIT</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th><th>[1, 9, 11]</th><th>[1, 9, 9]</th><th>[1, 8, 9]</th></tr>
+<tr><th>DCI1:PMASK_TERM_VCC</th><th>[1, 8, 10]</th><th>[1, 8, 11]</th><th>[1, 8, 7]</th><th>[1, 8, 6]</th><th>[1, 8, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc2v-UL.V2P-DCI0:LVDSBIAS"></div>
 <div id="bits-xc2v-UL.V2P-DCI1:LVDSBIAS"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 48]</th><th>[0, 2, 46]</th></tr>
-<tr><th>DCI1:LVDSBIAS</th><th>[1, 12, 9]</th><th>[1, 12, 8]</th></tr>
-<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 44]</th><th>[0, 2, 45]</th><th>[0, 3, 45]</th><th>[0, 2, 46]</th><th>[0, 3, 46]</th><th>[0, 2, 47]</th><th>[0, 3, 47]</th><th>[0, 2, 48]</th><th>[0, 3, 48]</th></tr>
+<tr><th>DCI1:LVDSBIAS</th><th>[1, 13, 7]</th><th>[1, 13, 11]</th><th>[1, 13, 9]</th><th>[1, 12, 9]</th><th>[1, 12, 11]</th><th>[1, 12, 10]</th><th>[1, 12, 7]</th><th>[1, 12, 6]</th><th>[1, 12, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc2v-UL.V2P-MISC:HSWAPENPIN"></div>
 <div id="bits-xc2v-UL.V2P-MISC:TDIPIN"></div>
@@ -965,21 +978,21 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.V2</span></c
 <tr><td>31</td>
 <td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:TEST_ENABLE" title="DCI0:TEST_ENABLE">DCI0:TEST_ENABLE</a></td><td><a href="#bits-xc2v-LR.V2-DCI0:FORCE_DONE_HIGH" title="DCI0:FORCE_DONE_HIGH">DCI0:FORCE_DONE_HIGH</a></td></tr>
 <tr><td>32</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[0]">DCI0:TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LR.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[2]">DCI0:TERM_SPLIT[2]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[4]">DCI0:PMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LR.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[3]">DCI0:PMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>33</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[3]">DCI0:TERM_SPLIT[3]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[2]">DCI0:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-LR.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[1]">DCI0:PMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>34</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[5]">DCI0:TERM_SPLIT[5]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[0]">DCI0:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LR.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[4]">DCI0:PMASK_TERM_VCC[4]</a></td></tr>
 <tr><td>35</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[3]">DCI0:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-LR.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[2]">DCI0:PMASK_TERM_VCC[2]</a></td></tr>
 <tr><td>36</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:TERM_VCC" title="DCI0:TERM_VCC">DCI0:TERM_VCC</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[1]">DCI0:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-LR.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[0]">DCI0:PMASK_TERM_VCC[0]</a></td></tr>
 <tr><td>37</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[1]">DCI0:TERM_SPLIT[1]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[4]">DCI0:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LR.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[3]">DCI0:NMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>38</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[4]">DCI0:TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LR.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[6]">DCI0:TERM_SPLIT[6]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[2]">DCI0:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-LR.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[1]">DCI0:NMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>39</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[0]">DCI0:NMASK_TERM_SPLIT[0]</a></td><td>-</td></tr>
 <tr><td>40</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>41</td>
@@ -989,15 +1002,15 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.V2</span></c
 <tr><td>43</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>44</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td></tr>
 <tr><td>45</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td><td><a href="#bits-xc2v-LR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[6]">DCI0:LVDSBIAS[6]</a></td></tr>
 <tr><td>46</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-LR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td></tr>
 <tr><td>47</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td><td><a href="#bits-xc2v-LR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
 <tr><td>48</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td><td><a href="#bits-xc2v-LR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
 </table>
 <table class="docutils align-default prjcombine-tile">
 <tr><th colspan="15">LR.V2 bittile 1</th></tr><tr><th rowspan="2">Row</th><th colspan="14">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th></tr>
@@ -1014,25 +1027,23 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.V2</span></c
 <tr><td>5</td>
 <td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>6</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[2]">DCI1:TERM_SPLIT[2]</a></td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[1]">DCI1:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[4]">DCI1:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td><td>-</td></tr>
 <tr><td>7</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[0]">DCI1:TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[6]">DCI1:TERM_SPLIT[6]</a></td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[2]">DCI1:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[3]">DCI1:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[1]">DCI1:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td></tr>
 <tr><td>8</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:TERM_VCC" title="DCI1:TERM_VCC">DCI1:TERM_VCC</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[0]">DCI1:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[3]">DCI1:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td><td>-</td></tr>
 <tr><td>9</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[5]">DCI1:TERM_SPLIT[5]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[0]">DCI1:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[1]">DCI1:PMASK_TERM_SPLIT[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[6]">DCI1:LVDSBIAS[6]</a></td></tr>
 <tr><td>10</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[1]">DCI1:TERM_SPLIT[1]</a></td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[4]">DCI1:TERM_SPLIT[4]</a></td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[4]">DCI1:PMASK_TERM_VCC[4]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[4]">DCI1:PMASK_TERM_SPLIT[4]</a></td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[2]">DCI1:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td><td>-</td></tr>
 <tr><td>11</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[3]">DCI1:TERM_SPLIT[3]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[3]">DCI1:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[2]">DCI1:PMASK_TERM_SPLIT[2]</a></td><td>-</td><td><a href="#bits-xc2v-LR.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[0]">DCI1:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td><td><a href="#bits-xc2v-LR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td></tr>
 </table>
 <div id="bits-xc2v-LR.V2-DCI0:ENABLE"></div>
 <div id="bits-xc2v-LR.V2-DCI0:FORCE_DONE_HIGH"></div>
-<div id="bits-xc2v-LR.V2-DCI0:TERM_VCC"></div>
 <div id="bits-xc2v-LR.V2-DCI0:TEST_ENABLE"></div>
 <div id="bits-xc2v-LR.V2-DCI1:ENABLE"></div>
 <div id="bits-xc2v-LR.V2-DCI1:FORCE_DONE_HIGH"></div>
-<div id="bits-xc2v-LR.V2-DCI1:TERM_VCC"></div>
 <div id="bits-xc2v-LR.V2-DCI1:TEST_ENABLE"></div>
 <div id="bits-xc2v-LR.V2-ICAP:ENABLE"></div>
 <div id="bits-xc2v-LR.V2-STARTUP:GSR_SYNC"></div>
@@ -1042,11 +1053,9 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.V2</span></c
 <table class="docutils align-default prjcombine-enum">
 <tr><th>DCI0:ENABLE</th><th>[0, 2, 42]</th></tr>
 <tr><th>DCI0:FORCE_DONE_HIGH</th><th>[0, 3, 31]</th></tr>
-<tr><th>DCI0:TERM_VCC</th><th>[0, 3, 36]</th></tr>
 <tr><th>DCI0:TEST_ENABLE</th><th>[0, 2, 31]</th></tr>
 <tr><th>DCI1:ENABLE</th><th>[1, 10, 7]</th></tr>
 <tr><th>DCI1:FORCE_DONE_HIGH</th><th>[1, 9, 8]</th></tr>
-<tr><th>DCI1:TERM_VCC</th><th>[1, 8, 8]</th></tr>
 <tr><th>DCI1:TEST_ENABLE</th><th>[1, 9, 6]</th></tr>
 <tr><th>ICAP:ENABLE</th><th>[0, 2, 6]</th></tr>
 <tr><th>STARTUP:GSR_SYNC</th><th>[0, 3, 5]</th></tr>
@@ -1065,19 +1074,27 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.V2</span></c
 <tr><td>PULLUP</td><td>0</td></tr>
 <tr><td>PULLNONE</td><td>1</td></tr>
 </table>
-<div id="bits-xc2v-LR.V2-DCI0:TERM_SPLIT"></div>
-<div id="bits-xc2v-LR.V2-DCI1:TERM_SPLIT"></div>
+<div id="bits-xc2v-LR.V2-DCI0:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LR.V2-DCI0:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LR.V2-DCI0:PMASK_TERM_VCC"></div>
+<div id="bits-xc2v-LR.V2-DCI1:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LR.V2-DCI1:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LR.V2-DCI1:PMASK_TERM_VCC"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_SPLIT</th><th>[0, 3, 38]</th><th>[0, 2, 34]</th><th>[0, 2, 38]</th><th>[0, 2, 33]</th><th>[0, 3, 32]</th><th>[0, 2, 37]</th><th>[0, 2, 32]</th></tr>
-<tr><th>DCI1:TERM_SPLIT</th><th>[1, 11, 7]</th><th>[1, 8, 9]</th><th>[1, 11, 10]</th><th>[1, 9, 11]</th><th>[1, 11, 6]</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th></tr>
-<tr><td>Non-inverted</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>DCI0:NMASK_TERM_SPLIT</th><th>[0, 2, 37]</th><th>[0, 3, 37]</th><th>[0, 2, 38]</th><th>[0, 3, 38]</th><th>[0, 2, 39]</th></tr>
+<tr><th>DCI0:PMASK_TERM_SPLIT</th><th>[0, 2, 32]</th><th>[0, 3, 32]</th><th>[0, 2, 33]</th><th>[0, 3, 33]</th><th>[0, 2, 34]</th></tr>
+<tr><th>DCI0:PMASK_TERM_VCC</th><th>[0, 3, 34]</th><th>[0, 2, 35]</th><th>[0, 3, 35]</th><th>[0, 2, 36]</th><th>[0, 3, 36]</th></tr>
+<tr><th>DCI1:NMASK_TERM_SPLIT</th><th>[1, 11, 6]</th><th>[1, 11, 8]</th><th>[1, 11, 10]</th><th>[1, 11, 7]</th><th>[1, 11, 11]</th></tr>
+<tr><th>DCI1:PMASK_TERM_SPLIT</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th><th>[1, 9, 11]</th><th>[1, 9, 9]</th><th>[1, 8, 9]</th></tr>
+<tr><th>DCI1:PMASK_TERM_VCC</th><th>[1, 8, 10]</th><th>[1, 8, 11]</th><th>[1, 8, 7]</th><th>[1, 8, 6]</th><th>[1, 8, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc2v-LR.V2-DCI0:LVDSBIAS"></div>
 <div id="bits-xc2v-LR.V2-DCI1:LVDSBIAS"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 46]</th><th>[0, 3, 48]</th><th>[0, 3, 45]</th></tr>
-<tr><th>DCI1:LVDSBIAS</th><th>[1, 12, 11]</th><th>[1, 13, 9]</th><th>[1, 12, 8]</th></tr>
-<tr><td>Non-inverted</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 44]</th><th>[0, 2, 45]</th><th>[0, 3, 45]</th><th>[0, 2, 46]</th><th>[0, 3, 46]</th><th>[0, 2, 47]</th><th>[0, 3, 47]</th><th>[0, 2, 48]</th><th>[0, 3, 48]</th></tr>
+<tr><th>DCI1:LVDSBIAS</th><th>[1, 13, 7]</th><th>[1, 13, 11]</th><th>[1, 13, 9]</th><th>[1, 12, 9]</th><th>[1, 12, 11]</th><th>[1, 12, 10]</th><th>[1, 12, 7]</th><th>[1, 12, 6]</th><th>[1, 12, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 </section>
 <section id="lr-v2p">
@@ -1150,21 +1167,21 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.V2P</span></
 <tr><td>31</td>
 <td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:TEST_ENABLE" title="DCI0:TEST_ENABLE">DCI0:TEST_ENABLE</a></td><td><a href="#bits-xc2v-LR.V2P-DCI0:FORCE_DONE_HIGH" title="DCI0:FORCE_DONE_HIGH">DCI0:FORCE_DONE_HIGH</a></td></tr>
 <tr><td>32</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[3]">DCI0:TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[5]">DCI0:TERM_SPLIT[5]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[4]">DCI0:PMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[3]">DCI0:PMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>33</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[2]">DCI0:TERM_SPLIT[2]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[2]">DCI0:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[1]">DCI0:PMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>34</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[4]">DCI0:TERM_SPLIT[4]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[0]">DCI0:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[4]">DCI0:PMASK_TERM_VCC[4]</a></td></tr>
 <tr><td>35</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:TERM_VCC" title="DCI0:TERM_VCC">DCI0:TERM_VCC</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[3]">DCI0:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[2]">DCI0:PMASK_TERM_VCC[2]</a></td></tr>
 <tr><td>36</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[1]">DCI0:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[0]">DCI0:PMASK_TERM_VCC[0]</a></td></tr>
 <tr><td>37</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[0]">DCI0:TERM_SPLIT[0]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[4]">DCI0:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[3]">DCI0:NMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>38</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[1]">DCI0:TERM_SPLIT[1]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[6]">DCI0:TERM_SPLIT[6]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[2]">DCI0:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[1]">DCI0:NMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>39</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:QUIET" title="DCI0:QUIET">DCI0:QUIET</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[0]">DCI0:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI0:QUIET" title="DCI0:QUIET">DCI0:QUIET</a></td></tr>
 <tr><td>40</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>41</td>
@@ -1174,52 +1191,50 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.V2P</span></
 <tr><td>43</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>44</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td></tr>
 <tr><td>45</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[6]">DCI0:LVDSBIAS[6]</a></td></tr>
 <tr><td>46</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td></tr>
 <tr><td>47</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
 <tr><td>48</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
 </table>
 <table class="docutils align-default prjcombine-tile">
-<tr><th colspan="14">LR.V2P bittile 1</th></tr><tr><th rowspan="2">Row</th><th colspan="13">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th></tr>
+<tr><th colspan="15">LR.V2P bittile 1</th></tr><tr><th rowspan="2">Row</th><th colspan="14">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th></tr>
 <tr><td>0</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>1</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>2</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>3</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>4</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>5</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>6</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[0]">DCI1:TERM_SPLIT[0]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[1]">DCI1:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[4]">DCI1:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td><td>-</td></tr>
 <tr><td>7</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:TERM_VCC" title="DCI1:TERM_VCC">DCI1:TERM_VCC</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[4]">DCI1:TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[6]">DCI1:TERM_SPLIT[6]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[2]">DCI1:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[3]">DCI1:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[1]">DCI1:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td></tr>
 <tr><td>8</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[0]">DCI1:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[3]">DCI1:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td><td>-</td></tr>
 <tr><td>9</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[3]">DCI1:TERM_SPLIT[3]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:QUIET" title="DCI1:QUIET">DCI1:QUIET</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[0]">DCI1:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[1]">DCI1:PMASK_TERM_SPLIT[1]</a></td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:QUIET" title="DCI1:QUIET">DCI1:QUIET</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[6]">DCI1:LVDSBIAS[6]</a></td></tr>
 <tr><td>10</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[5]">DCI1:TERM_SPLIT[5]</a></td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[1]">DCI1:TERM_SPLIT[1]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[4]">DCI1:PMASK_TERM_VCC[4]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[4]">DCI1:PMASK_TERM_SPLIT[4]</a></td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[2]">DCI1:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td><td>-</td></tr>
 <tr><td>11</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[2]">DCI1:TERM_SPLIT[2]</a></td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[3]">DCI1:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[2]">DCI1:PMASK_TERM_SPLIT[2]</a></td><td>-</td><td><a href="#bits-xc2v-LR.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[0]">DCI1:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td><td><a href="#bits-xc2v-LR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td></tr>
 </table>
 <div id="bits-xc2v-LR.V2P-DCI0:ENABLE"></div>
 <div id="bits-xc2v-LR.V2P-DCI0:FORCE_DONE_HIGH"></div>
 <div id="bits-xc2v-LR.V2P-DCI0:QUIET"></div>
-<div id="bits-xc2v-LR.V2P-DCI0:TERM_VCC"></div>
 <div id="bits-xc2v-LR.V2P-DCI0:TEST_ENABLE"></div>
 <div id="bits-xc2v-LR.V2P-DCI1:ENABLE"></div>
 <div id="bits-xc2v-LR.V2P-DCI1:FORCE_DONE_HIGH"></div>
 <div id="bits-xc2v-LR.V2P-DCI1:QUIET"></div>
-<div id="bits-xc2v-LR.V2P-DCI1:TERM_VCC"></div>
 <div id="bits-xc2v-LR.V2P-DCI1:TEST_ENABLE"></div>
 <div id="bits-xc2v-LR.V2P-ICAP:ENABLE"></div>
 <div id="bits-xc2v-LR.V2P-STARTUP:GSR_SYNC"></div>
@@ -1230,12 +1245,10 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.V2P</span></
 <tr><th>DCI0:ENABLE</th><th>[0, 2, 42]</th></tr>
 <tr><th>DCI0:FORCE_DONE_HIGH</th><th>[0, 3, 31]</th></tr>
 <tr><th>DCI0:QUIET</th><th>[0, 3, 39]</th></tr>
-<tr><th>DCI0:TERM_VCC</th><th>[0, 3, 35]</th></tr>
 <tr><th>DCI0:TEST_ENABLE</th><th>[0, 2, 31]</th></tr>
 <tr><th>DCI1:ENABLE</th><th>[1, 10, 7]</th></tr>
 <tr><th>DCI1:FORCE_DONE_HIGH</th><th>[1, 9, 8]</th></tr>
 <tr><th>DCI1:QUIET</th><th>[1, 11, 9]</th></tr>
-<tr><th>DCI1:TERM_VCC</th><th>[1, 8, 7]</th></tr>
 <tr><th>DCI1:TEST_ENABLE</th><th>[1, 9, 6]</th></tr>
 <tr><th>ICAP:ENABLE</th><th>[0, 2, 6]</th></tr>
 <tr><th>STARTUP:GSR_SYNC</th><th>[0, 3, 5]</th></tr>
@@ -1254,19 +1267,27 @@ <h3><code class="docutils literal notranslate"><span class="pre">LR.V2P</span></
 <tr><td>PULLUP</td><td>0</td></tr>
 <tr><td>PULLNONE</td><td>1</td></tr>
 </table>
-<div id="bits-xc2v-LR.V2P-DCI0:TERM_SPLIT"></div>
-<div id="bits-xc2v-LR.V2P-DCI1:TERM_SPLIT"></div>
+<div id="bits-xc2v-LR.V2P-DCI0:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LR.V2P-DCI0:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LR.V2P-DCI0:PMASK_TERM_VCC"></div>
+<div id="bits-xc2v-LR.V2P-DCI1:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LR.V2P-DCI1:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-LR.V2P-DCI1:PMASK_TERM_VCC"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_SPLIT</th><th>[0, 3, 38]</th><th>[0, 3, 32]</th><th>[0, 2, 34]</th><th>[0, 2, 32]</th><th>[0, 2, 33]</th><th>[0, 2, 38]</th><th>[0, 2, 37]</th></tr>
-<tr><th>DCI1:TERM_SPLIT</th><th>[1, 11, 7]</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th><th>[1, 8, 9]</th><th>[1, 9, 11]</th><th>[1, 11, 10]</th><th>[1, 11, 6]</th></tr>
-<tr><td>Non-inverted</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>DCI0:NMASK_TERM_SPLIT</th><th>[0, 2, 37]</th><th>[0, 3, 37]</th><th>[0, 2, 38]</th><th>[0, 3, 38]</th><th>[0, 2, 39]</th></tr>
+<tr><th>DCI0:PMASK_TERM_SPLIT</th><th>[0, 2, 32]</th><th>[0, 3, 32]</th><th>[0, 2, 33]</th><th>[0, 3, 33]</th><th>[0, 2, 34]</th></tr>
+<tr><th>DCI0:PMASK_TERM_VCC</th><th>[0, 3, 34]</th><th>[0, 2, 35]</th><th>[0, 3, 35]</th><th>[0, 2, 36]</th><th>[0, 3, 36]</th></tr>
+<tr><th>DCI1:NMASK_TERM_SPLIT</th><th>[1, 11, 6]</th><th>[1, 11, 8]</th><th>[1, 11, 10]</th><th>[1, 11, 7]</th><th>[1, 11, 11]</th></tr>
+<tr><th>DCI1:PMASK_TERM_SPLIT</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th><th>[1, 9, 11]</th><th>[1, 9, 9]</th><th>[1, 8, 9]</th></tr>
+<tr><th>DCI1:PMASK_TERM_VCC</th><th>[1, 8, 10]</th><th>[1, 8, 11]</th><th>[1, 8, 7]</th><th>[1, 8, 6]</th><th>[1, 8, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc2v-LR.V2P-DCI0:LVDSBIAS"></div>
 <div id="bits-xc2v-LR.V2P-DCI1:LVDSBIAS"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 48]</th><th>[0, 2, 46]</th></tr>
-<tr><th>DCI1:LVDSBIAS</th><th>[1, 12, 9]</th><th>[1, 12, 8]</th></tr>
-<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 44]</th><th>[0, 2, 45]</th><th>[0, 3, 45]</th><th>[0, 2, 46]</th><th>[0, 3, 46]</th><th>[0, 2, 47]</th><th>[0, 3, 47]</th><th>[0, 2, 48]</th><th>[0, 3, 48]</th></tr>
+<tr><th>DCI1:LVDSBIAS</th><th>[1, 13, 7]</th><th>[1, 13, 11]</th><th>[1, 13, 9]</th><th>[1, 12, 9]</th><th>[1, 12, 11]</th><th>[1, 12, 10]</th><th>[1, 12, 7]</th><th>[1, 12, 6]</th><th>[1, 12, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 </section>
 </section>
@@ -1346,21 +1367,21 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.V2</span></c
 <tr><td>31</td>
 <td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:TEST_ENABLE" title="DCI0:TEST_ENABLE">DCI0:TEST_ENABLE</a></td><td><a href="#bits-xc2v-UR.V2-DCI0:FORCE_DONE_HIGH" title="DCI0:FORCE_DONE_HIGH">DCI0:FORCE_DONE_HIGH</a></td></tr>
 <tr><td>32</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[0]">DCI0:TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UR.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[2]">DCI0:TERM_SPLIT[2]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[4]">DCI0:PMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UR.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[3]">DCI0:PMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>33</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[3]">DCI0:TERM_SPLIT[3]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[2]">DCI0:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-UR.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[1]">DCI0:PMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>34</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[5]">DCI0:TERM_SPLIT[5]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[0]">DCI0:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UR.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[4]">DCI0:PMASK_TERM_VCC[4]</a></td></tr>
 <tr><td>35</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[3]">DCI0:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-UR.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[2]">DCI0:PMASK_TERM_VCC[2]</a></td></tr>
 <tr><td>36</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:TERM_VCC" title="DCI0:TERM_VCC">DCI0:TERM_VCC</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[1]">DCI0:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-UR.V2-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[0]">DCI0:PMASK_TERM_VCC[0]</a></td></tr>
 <tr><td>37</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[1]">DCI0:TERM_SPLIT[1]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[4]">DCI0:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UR.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[3]">DCI0:NMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>38</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[4]">DCI0:TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UR.V2-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[6]">DCI0:TERM_SPLIT[6]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[2]">DCI0:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-UR.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[1]">DCI0:NMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>39</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[0]">DCI0:NMASK_TERM_SPLIT[0]</a></td><td>-</td></tr>
 <tr><td>40</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>41</td>
@@ -1370,15 +1391,15 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.V2</span></c
 <tr><td>43</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>44</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td></tr>
 <tr><td>45</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td><td><a href="#bits-xc2v-UR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[6]">DCI0:LVDSBIAS[6]</a></td></tr>
 <tr><td>46</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-UR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td></tr>
 <tr><td>47</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td><td><a href="#bits-xc2v-UR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
 <tr><td>48</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td><td><a href="#bits-xc2v-UR.V2-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
 </table>
 <table class="docutils align-default prjcombine-tile">
 <tr><th colspan="15">UR.V2 bittile 1</th></tr><tr><th rowspan="2">Row</th><th colspan="14">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th></tr>
@@ -1395,17 +1416,17 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.V2</span></c
 <tr><td>5</td>
 <td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>6</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TMSPIN" title="MISC:TMSPIN[1]">MISC:TMSPIN[1]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[2]">DCI1:TERM_SPLIT[2]</a></td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TMSPIN" title="MISC:TMSPIN[1]">MISC:TMSPIN[1]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[1]">DCI1:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[4]">DCI1:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td><td>-</td></tr>
 <tr><td>7</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TCKPIN" title="MISC:TCKPIN[1]">MISC:TCKPIN[1]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[0]">DCI1:TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[6]">DCI1:TERM_SPLIT[6]</a></td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TCKPIN" title="MISC:TCKPIN[1]">MISC:TCKPIN[1]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[2]">DCI1:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[3]">DCI1:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[1]">DCI1:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td></tr>
 <tr><td>8</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TMSPIN" title="MISC:TMSPIN[0]">MISC:TMSPIN[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:TERM_VCC" title="DCI1:TERM_VCC">DCI1:TERM_VCC</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TMSPIN" title="MISC:TMSPIN[0]">MISC:TMSPIN[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[0]">DCI1:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[3]">DCI1:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td><td>-</td></tr>
 <tr><td>9</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TDOPIN" title="MISC:TDOPIN[1]">MISC:TDOPIN[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TEST_LL" title="MISC:TEST_LL">MISC:TEST_LL</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[5]">DCI1:TERM_SPLIT[5]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TDOPIN" title="MISC:TDOPIN[1]">MISC:TDOPIN[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TEST_LL" title="MISC:TEST_LL">MISC:TEST_LL</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[0]">DCI1:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[1]">DCI1:PMASK_TERM_SPLIT[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[6]">DCI1:LVDSBIAS[6]</a></td></tr>
 <tr><td>10</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TCKPIN" title="MISC:TCKPIN[0]">MISC:TCKPIN[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[1]">DCI1:TERM_SPLIT[1]</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[4]">DCI1:TERM_SPLIT[4]</a></td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TCKPIN" title="MISC:TCKPIN[0]">MISC:TCKPIN[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[4]">DCI1:PMASK_TERM_VCC[4]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[4]">DCI1:PMASK_TERM_SPLIT[4]</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[2]">DCI1:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td><td>-</td></tr>
 <tr><td>11</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TDOPIN" title="MISC:TDOPIN[0]">MISC:TDOPIN[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[3]">DCI1:TERM_SPLIT[3]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TDOPIN" title="MISC:TDOPIN[0]">MISC:TDOPIN[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[3]">DCI1:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[2]">DCI1:PMASK_TERM_SPLIT[2]</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[0]">DCI1:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td><td><a href="#bits-xc2v-UR.V2-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td></tr>
 </table>
 <div id="bits-xc2v-UR.V2-BSCAN:USERID"></div>
 <table class="docutils align-default prjcombine-enum">
@@ -1419,38 +1440,42 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.V2</span></c
 </table>
 <div id="bits-xc2v-UR.V2-DCI0:ENABLE"></div>
 <div id="bits-xc2v-UR.V2-DCI0:FORCE_DONE_HIGH"></div>
-<div id="bits-xc2v-UR.V2-DCI0:TERM_VCC"></div>
 <div id="bits-xc2v-UR.V2-DCI0:TEST_ENABLE"></div>
 <div id="bits-xc2v-UR.V2-DCI1:ENABLE"></div>
 <div id="bits-xc2v-UR.V2-DCI1:FORCE_DONE_HIGH"></div>
-<div id="bits-xc2v-UR.V2-DCI1:TERM_VCC"></div>
 <div id="bits-xc2v-UR.V2-DCI1:TEST_ENABLE"></div>
 <div id="bits-xc2v-UR.V2-MISC:TEST_LL"></div>
 <table class="docutils align-default prjcombine-enum">
 <tr><th>DCI0:ENABLE</th><th>[0, 2, 42]</th></tr>
 <tr><th>DCI0:FORCE_DONE_HIGH</th><th>[0, 3, 31]</th></tr>
-<tr><th>DCI0:TERM_VCC</th><th>[0, 3, 36]</th></tr>
 <tr><th>DCI0:TEST_ENABLE</th><th>[0, 2, 31]</th></tr>
 <tr><th>DCI1:ENABLE</th><th>[1, 10, 7]</th></tr>
 <tr><th>DCI1:FORCE_DONE_HIGH</th><th>[1, 9, 8]</th></tr>
-<tr><th>DCI1:TERM_VCC</th><th>[1, 8, 8]</th></tr>
 <tr><th>DCI1:TEST_ENABLE</th><th>[1, 9, 6]</th></tr>
 <tr><th>MISC:TEST_LL</th><th>[1, 6, 9]</th></tr>
 <tr><td>Non-inverted</td><td>[0]</td></tr>
 </table>
-<div id="bits-xc2v-UR.V2-DCI0:TERM_SPLIT"></div>
-<div id="bits-xc2v-UR.V2-DCI1:TERM_SPLIT"></div>
+<div id="bits-xc2v-UR.V2-DCI0:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UR.V2-DCI0:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UR.V2-DCI0:PMASK_TERM_VCC"></div>
+<div id="bits-xc2v-UR.V2-DCI1:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UR.V2-DCI1:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UR.V2-DCI1:PMASK_TERM_VCC"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_SPLIT</th><th>[0, 3, 38]</th><th>[0, 2, 34]</th><th>[0, 2, 38]</th><th>[0, 2, 33]</th><th>[0, 3, 32]</th><th>[0, 2, 37]</th><th>[0, 2, 32]</th></tr>
-<tr><th>DCI1:TERM_SPLIT</th><th>[1, 11, 7]</th><th>[1, 8, 9]</th><th>[1, 11, 10]</th><th>[1, 9, 11]</th><th>[1, 11, 6]</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th></tr>
-<tr><td>Non-inverted</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>DCI0:NMASK_TERM_SPLIT</th><th>[0, 2, 37]</th><th>[0, 3, 37]</th><th>[0, 2, 38]</th><th>[0, 3, 38]</th><th>[0, 2, 39]</th></tr>
+<tr><th>DCI0:PMASK_TERM_SPLIT</th><th>[0, 2, 32]</th><th>[0, 3, 32]</th><th>[0, 2, 33]</th><th>[0, 3, 33]</th><th>[0, 2, 34]</th></tr>
+<tr><th>DCI0:PMASK_TERM_VCC</th><th>[0, 3, 34]</th><th>[0, 2, 35]</th><th>[0, 3, 35]</th><th>[0, 2, 36]</th><th>[0, 3, 36]</th></tr>
+<tr><th>DCI1:NMASK_TERM_SPLIT</th><th>[1, 11, 6]</th><th>[1, 11, 8]</th><th>[1, 11, 10]</th><th>[1, 11, 7]</th><th>[1, 11, 11]</th></tr>
+<tr><th>DCI1:PMASK_TERM_SPLIT</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th><th>[1, 9, 11]</th><th>[1, 9, 9]</th><th>[1, 8, 9]</th></tr>
+<tr><th>DCI1:PMASK_TERM_VCC</th><th>[1, 8, 10]</th><th>[1, 8, 11]</th><th>[1, 8, 7]</th><th>[1, 8, 6]</th><th>[1, 8, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc2v-UR.V2-DCI0:LVDSBIAS"></div>
 <div id="bits-xc2v-UR.V2-DCI1:LVDSBIAS"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 46]</th><th>[0, 3, 48]</th><th>[0, 3, 45]</th></tr>
-<tr><th>DCI1:LVDSBIAS</th><th>[1, 12, 11]</th><th>[1, 13, 9]</th><th>[1, 12, 8]</th></tr>
-<tr><td>Non-inverted</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 44]</th><th>[0, 2, 45]</th><th>[0, 3, 45]</th><th>[0, 2, 46]</th><th>[0, 3, 46]</th><th>[0, 2, 47]</th><th>[0, 3, 47]</th><th>[0, 2, 48]</th><th>[0, 3, 48]</th></tr>
+<tr><th>DCI1:LVDSBIAS</th><th>[1, 13, 7]</th><th>[1, 13, 11]</th><th>[1, 13, 9]</th><th>[1, 12, 9]</th><th>[1, 12, 11]</th><th>[1, 12, 10]</th><th>[1, 12, 7]</th><th>[1, 12, 6]</th><th>[1, 12, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc2v-UR.V2-MISC:TCKPIN"></div>
 <div id="bits-xc2v-UR.V2-MISC:TDOPIN"></div>
@@ -1534,21 +1559,21 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.V2P</span></
 <tr><td>31</td>
 <td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:TEST_ENABLE" title="DCI0:TEST_ENABLE">DCI0:TEST_ENABLE</a></td><td><a href="#bits-xc2v-UR.V2P-DCI0:FORCE_DONE_HIGH" title="DCI0:FORCE_DONE_HIGH">DCI0:FORCE_DONE_HIGH</a></td></tr>
 <tr><td>32</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[3]">DCI0:TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[5]">DCI0:TERM_SPLIT[5]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[4]">DCI0:PMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[3]">DCI0:PMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>33</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[2]">DCI0:TERM_SPLIT[2]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[2]">DCI0:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[1]">DCI0:PMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>34</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[4]">DCI0:TERM_SPLIT[4]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:PMASK_TERM_SPLIT" title="DCI0:PMASK_TERM_SPLIT[0]">DCI0:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[4]">DCI0:PMASK_TERM_VCC[4]</a></td></tr>
 <tr><td>35</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:TERM_VCC" title="DCI0:TERM_VCC">DCI0:TERM_VCC</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[3]">DCI0:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[2]">DCI0:PMASK_TERM_VCC[2]</a></td></tr>
 <tr><td>36</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[1]">DCI0:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI0:PMASK_TERM_VCC" title="DCI0:PMASK_TERM_VCC[0]">DCI0:PMASK_TERM_VCC[0]</a></td></tr>
 <tr><td>37</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[0]">DCI0:TERM_SPLIT[0]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[4]">DCI0:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[3]">DCI0:NMASK_TERM_SPLIT[3]</a></td></tr>
 <tr><td>38</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[1]">DCI0:TERM_SPLIT[1]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI0:TERM_SPLIT" title="DCI0:TERM_SPLIT[6]">DCI0:TERM_SPLIT[6]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[2]">DCI0:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[1]">DCI0:NMASK_TERM_SPLIT[1]</a></td></tr>
 <tr><td>39</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:QUIET" title="DCI0:QUIET">DCI0:QUIET</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:NMASK_TERM_SPLIT" title="DCI0:NMASK_TERM_SPLIT[0]">DCI0:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI0:QUIET" title="DCI0:QUIET">DCI0:QUIET</a></td></tr>
 <tr><td>40</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>41</td>
@@ -1558,42 +1583,42 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.V2P</span></
 <tr><td>43</td>
 <td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>44</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[8]">DCI0:LVDSBIAS[8]</a></td></tr>
 <tr><td>45</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[7]">DCI0:LVDSBIAS[7]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[6]">DCI0:LVDSBIAS[6]</a></td></tr>
 <tr><td>46</td>
-<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[5]">DCI0:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[4]">DCI0:LVDSBIAS[4]</a></td></tr>
 <tr><td>47</td>
-<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[3]">DCI0:LVDSBIAS[3]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[2]">DCI0:LVDSBIAS[2]</a></td></tr>
 <tr><td>48</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[1]">DCI0:LVDSBIAS[1]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI0:LVDSBIAS" title="DCI0:LVDSBIAS[0]">DCI0:LVDSBIAS[0]</a></td></tr>
 </table>
 <table class="docutils align-default prjcombine-tile">
-<tr><th colspan="14">UR.V2P bittile 1</th></tr><tr><th rowspan="2">Row</th><th colspan="13">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th></tr>
+<tr><th colspan="15">UR.V2P bittile 1</th></tr><tr><th rowspan="2">Row</th><th colspan="14">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th></tr>
 <tr><td>0</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>1</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>2</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>3</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>4</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>5</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>6</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TMSPIN" title="MISC:TMSPIN[1]">MISC:TMSPIN[1]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[0]">DCI1:TERM_SPLIT[0]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TMSPIN" title="MISC:TMSPIN[1]">MISC:TMSPIN[1]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[1]">DCI1:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:TEST_ENABLE" title="DCI1:TEST_ENABLE">DCI1:TEST_ENABLE</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[4]">DCI1:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td><td>-</td></tr>
 <tr><td>7</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TCKPIN" title="MISC:TCKPIN[1]">MISC:TCKPIN[1]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:TERM_VCC" title="DCI1:TERM_VCC">DCI1:TERM_VCC</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[4]">DCI1:TERM_SPLIT[4]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[6]">DCI1:TERM_SPLIT[6]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TCKPIN" title="MISC:TCKPIN[1]">MISC:TCKPIN[1]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[2]">DCI1:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[3]">DCI1:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:ENABLE" title="DCI1:ENABLE">DCI1:ENABLE</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[1]">DCI1:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[2]">DCI1:LVDSBIAS[2]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[8]">DCI1:LVDSBIAS[8]</a></td></tr>
 <tr><td>8</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TMSPIN" title="MISC:TMSPIN[0]">MISC:TMSPIN[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TMSPIN" title="MISC:TMSPIN[0]">MISC:TMSPIN[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[0]">DCI1:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:FORCE_DONE_HIGH" title="DCI1:FORCE_DONE_HIGH">DCI1:FORCE_DONE_HIGH</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[3]">DCI1:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[0]">DCI1:LVDSBIAS[0]</a></td><td>-</td></tr>
 <tr><td>9</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TDOPIN" title="MISC:TDOPIN[1]">MISC:TDOPIN[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TEST_LL" title="MISC:TEST_LL">MISC:TEST_LL</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[3]">DCI1:TERM_SPLIT[3]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:QUIET" title="DCI1:QUIET">DCI1:QUIET</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[1]">DCI1:LVDSBIAS[1]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TDOPIN" title="MISC:TDOPIN[1]">MISC:TDOPIN[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TEST_LL" title="MISC:TEST_LL">MISC:TEST_LL</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[0]">DCI1:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[1]">DCI1:PMASK_TERM_SPLIT[1]</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:QUIET" title="DCI1:QUIET">DCI1:QUIET</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[5]">DCI1:LVDSBIAS[5]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[6]">DCI1:LVDSBIAS[6]</a></td></tr>
 <tr><td>10</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TCKPIN" title="MISC:TCKPIN[0]">MISC:TCKPIN[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[5]">DCI1:TERM_SPLIT[5]</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[1]">DCI1:TERM_SPLIT[1]</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TCKPIN" title="MISC:TCKPIN[0]">MISC:TCKPIN[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[4]">DCI1:PMASK_TERM_VCC[4]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[4]">DCI1:PMASK_TERM_SPLIT[4]</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[2]">DCI1:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[3]">DCI1:LVDSBIAS[3]</a></td><td>-</td></tr>
 <tr><td>11</td>
-<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TDOPIN" title="MISC:TDOPIN[0]">MISC:TDOPIN[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:TERM_SPLIT" title="DCI1:TERM_SPLIT[2]">DCI1:TERM_SPLIT[2]</a></td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TDOPIN" title="MISC:TDOPIN[0]">MISC:TDOPIN[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:PMASK_TERM_VCC" title="DCI1:PMASK_TERM_VCC[3]">DCI1:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:PMASK_TERM_SPLIT" title="DCI1:PMASK_TERM_SPLIT[2]">DCI1:PMASK_TERM_SPLIT[2]</a></td><td>-</td><td><a href="#bits-xc2v-UR.V2P-DCI1:NMASK_TERM_SPLIT" title="DCI1:NMASK_TERM_SPLIT[0]">DCI1:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[4]">DCI1:LVDSBIAS[4]</a></td><td><a href="#bits-xc2v-UR.V2P-DCI1:LVDSBIAS" title="DCI1:LVDSBIAS[7]">DCI1:LVDSBIAS[7]</a></td></tr>
 </table>
 <div id="bits-xc2v-UR.V2P-BSCAN:USERID"></div>
 <table class="docutils align-default prjcombine-enum">
@@ -1601,23 +1626,17 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.V2P</span></
 <tr><td>Inverted</td><td>~[31]</td><td>~[30]</td><td>~[29]</td><td>~[28]</td><td>~[27]</td><td>~[26]</td><td>~[25]</td><td>~[24]</td><td>~[23]</td><td>~[22]</td><td>~[21]</td><td>~[20]</td><td>~[19]</td><td>~[18]</td><td>~[17]</td><td>~[16]</td><td>~[15]</td><td>~[14]</td><td>~[13]</td><td>~[12]</td><td>~[11]</td><td>~[10]</td><td>~[9]</td><td>~[8]</td><td>~[7]</td><td>~[6]</td><td>~[5]</td><td>~[4]</td><td>~[3]</td><td>~[2]</td><td>~[1]</td><td>~[0]</td></tr>
 </table>
 <div id="bits-xc2v-UR.V2P-BSCAN:TDO_ENABLE"></div>
-<div id="bits-xc2v-UR.V2P-DCI0:LVDSBIAS"></div>
-<div id="bits-xc2v-UR.V2P-DCI1:LVDSBIAS"></div>
 <table class="docutils align-default prjcombine-enum">
 <tr><th>BSCAN:TDO_ENABLE</th><th>[0, 3, 20]</th><th>[0, 2, 20]</th></tr>
-<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 48]</th><th>[0, 2, 46]</th></tr>
-<tr><th>DCI1:LVDSBIAS</th><th>[1, 12, 9]</th><th>[1, 12, 8]</th></tr>
 <tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc2v-UR.V2P-DCI0:ENABLE"></div>
 <div id="bits-xc2v-UR.V2P-DCI0:FORCE_DONE_HIGH"></div>
 <div id="bits-xc2v-UR.V2P-DCI0:QUIET"></div>
-<div id="bits-xc2v-UR.V2P-DCI0:TERM_VCC"></div>
 <div id="bits-xc2v-UR.V2P-DCI0:TEST_ENABLE"></div>
 <div id="bits-xc2v-UR.V2P-DCI1:ENABLE"></div>
 <div id="bits-xc2v-UR.V2P-DCI1:FORCE_DONE_HIGH"></div>
 <div id="bits-xc2v-UR.V2P-DCI1:QUIET"></div>
-<div id="bits-xc2v-UR.V2P-DCI1:TERM_VCC"></div>
 <div id="bits-xc2v-UR.V2P-DCI1:TEST_ENABLE"></div>
 <div id="bits-xc2v-UR.V2P-JTAGPPC:ENABLE"></div>
 <div id="bits-xc2v-UR.V2P-MISC:TEST_LL"></div>
@@ -1625,23 +1644,36 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.V2P</span></
 <tr><th>DCI0:ENABLE</th><th>[0, 2, 42]</th></tr>
 <tr><th>DCI0:FORCE_DONE_HIGH</th><th>[0, 3, 31]</th></tr>
 <tr><th>DCI0:QUIET</th><th>[0, 3, 39]</th></tr>
-<tr><th>DCI0:TERM_VCC</th><th>[0, 3, 35]</th></tr>
 <tr><th>DCI0:TEST_ENABLE</th><th>[0, 2, 31]</th></tr>
 <tr><th>DCI1:ENABLE</th><th>[1, 10, 7]</th></tr>
 <tr><th>DCI1:FORCE_DONE_HIGH</th><th>[1, 9, 8]</th></tr>
 <tr><th>DCI1:QUIET</th><th>[1, 11, 9]</th></tr>
-<tr><th>DCI1:TERM_VCC</th><th>[1, 8, 7]</th></tr>
 <tr><th>DCI1:TEST_ENABLE</th><th>[1, 9, 6]</th></tr>
 <tr><th>JTAGPPC:ENABLE</th><th>[0, 3, 42]</th></tr>
 <tr><th>MISC:TEST_LL</th><th>[1, 6, 9]</th></tr>
 <tr><td>Non-inverted</td><td>[0]</td></tr>
 </table>
-<div id="bits-xc2v-UR.V2P-DCI0:TERM_SPLIT"></div>
-<div id="bits-xc2v-UR.V2P-DCI1:TERM_SPLIT"></div>
+<div id="bits-xc2v-UR.V2P-DCI0:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UR.V2P-DCI0:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UR.V2P-DCI0:PMASK_TERM_VCC"></div>
+<div id="bits-xc2v-UR.V2P-DCI1:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UR.V2P-DCI1:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc2v-UR.V2P-DCI1:PMASK_TERM_VCC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI0:NMASK_TERM_SPLIT</th><th>[0, 2, 37]</th><th>[0, 3, 37]</th><th>[0, 2, 38]</th><th>[0, 3, 38]</th><th>[0, 2, 39]</th></tr>
+<tr><th>DCI0:PMASK_TERM_SPLIT</th><th>[0, 2, 32]</th><th>[0, 3, 32]</th><th>[0, 2, 33]</th><th>[0, 3, 33]</th><th>[0, 2, 34]</th></tr>
+<tr><th>DCI0:PMASK_TERM_VCC</th><th>[0, 3, 34]</th><th>[0, 2, 35]</th><th>[0, 3, 35]</th><th>[0, 2, 36]</th><th>[0, 3, 36]</th></tr>
+<tr><th>DCI1:NMASK_TERM_SPLIT</th><th>[1, 11, 6]</th><th>[1, 11, 8]</th><th>[1, 11, 10]</th><th>[1, 11, 7]</th><th>[1, 11, 11]</th></tr>
+<tr><th>DCI1:PMASK_TERM_SPLIT</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th><th>[1, 9, 11]</th><th>[1, 9, 9]</th><th>[1, 8, 9]</th></tr>
+<tr><th>DCI1:PMASK_TERM_VCC</th><th>[1, 8, 10]</th><th>[1, 8, 11]</th><th>[1, 8, 7]</th><th>[1, 8, 6]</th><th>[1, 8, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-UR.V2P-DCI0:LVDSBIAS"></div>
+<div id="bits-xc2v-UR.V2P-DCI1:LVDSBIAS"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>DCI0:TERM_SPLIT</th><th>[0, 3, 38]</th><th>[0, 3, 32]</th><th>[0, 2, 34]</th><th>[0, 2, 32]</th><th>[0, 2, 33]</th><th>[0, 2, 38]</th><th>[0, 2, 37]</th></tr>
-<tr><th>DCI1:TERM_SPLIT</th><th>[1, 11, 7]</th><th>[1, 9, 10]</th><th>[1, 9, 7]</th><th>[1, 8, 9]</th><th>[1, 9, 11]</th><th>[1, 11, 10]</th><th>[1, 11, 6]</th></tr>
-<tr><td>Non-inverted</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+<tr><th>DCI0:LVDSBIAS</th><th>[0, 3, 44]</th><th>[0, 2, 45]</th><th>[0, 3, 45]</th><th>[0, 2, 46]</th><th>[0, 3, 46]</th><th>[0, 2, 47]</th><th>[0, 3, 47]</th><th>[0, 2, 48]</th><th>[0, 3, 48]</th></tr>
+<tr><th>DCI1:LVDSBIAS</th><th>[1, 13, 7]</th><th>[1, 13, 11]</th><th>[1, 13, 9]</th><th>[1, 12, 9]</th><th>[1, 12, 11]</th><th>[1, 12, 10]</th><th>[1, 12, 7]</th><th>[1, 12, 6]</th><th>[1, 12, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
 </table>
 <div id="bits-xc2v-UR.V2P-MISC:TCKPIN"></div>
 <div id="bits-xc2v-UR.V2P-MISC:TDOPIN"></div>
@@ -1659,89 +1691,89 @@ <h3><code class="docutils literal notranslate"><span class="pre">UR.V2P</span></
 <section id="i-o-data-virtex-2">
 <h2>I/O data — Virtex 2<a class="headerlink" href="#i-o-data-virtex-2" title="Link to this heading"></a></h2>
 <table class="docutils align-default">
-<tr><th rowspan="2">Name</th><th colspan="3">IOSTD:V2:LVDSBIAS</th></tr>
-<tr><th>[2]</th><th>[1]</th><th>[0]</th></tr>
-<tr><td>LDT_25</td><td>0</td><td>1</td><td>1</td></tr>
-<tr><td>LVDSEXT_25</td><td>0</td><td>1</td><td>1</td></tr>
-<tr><td>LVDSEXT_25_DCI</td><td>0</td><td>1</td><td>1</td></tr>
-<tr><td>LVDSEXT_33</td><td>1</td><td>1</td><td>1</td></tr>
-<tr><td>LVDSEXT_33_DCI</td><td>1</td><td>1</td><td>1</td></tr>
-<tr><td>LVDS_25</td><td>0</td><td>1</td><td>1</td></tr>
-<tr><td>LVDS_25_DCI</td><td>0</td><td>1</td><td>1</td></tr>
-<tr><td>LVDS_33</td><td>1</td><td>1</td><td>1</td></tr>
-<tr><td>LVDS_33_DCI</td><td>1</td><td>1</td><td>1</td></tr>
-<tr><td>NONE</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>ULVDS_25</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><th rowspan="2">Name</th><th colspan="9">IOSTD:V2:LVDSBIAS</th></tr>
+<tr><th>[8]</th><th>[7]</th><th>[6]</th><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>LDT_25</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVDSEXT_25</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVDSEXT_25_DCI</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVDSEXT_33</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVDSEXT_33_DCI</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVDS_25</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVDS_25_DCI</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVDS_33</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVDS_33_DCI</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>ULVDS_25</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
 </table>
 <table class="docutils align-default">
-<tr><th rowspan="2">Name</th><th colspan="7">IOSTD:V2:TERM_SPLIT</th></tr>
-<tr><th>[6]</th><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
-<tr><td>HSTL_II_DCI</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
-<tr><td>HSTL_II_DCI_18</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
-<tr><td>HSTL_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>HSTL_I_DCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDSEXT_25_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDSEXT_33_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDS_25_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDS_33_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>SSTL18_II_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>SSTL18_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>SSTL2_II_DCI</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>SSTL2_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>SSTL3_II_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
-<tr><td>SSTL3_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><th rowspan="2">Name</th><th colspan="5">IOSTD:V2:PMASK_TERM_SPLIT</th><th colspan="5">IOSTD:V2:NMASK_TERM_SPLIT</th></tr>
+<tr><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>HSTL_II_DCI</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_II_DCI_18</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_I_DCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDSEXT_25_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDSEXT_33_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDS_25_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDS_33_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_II_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL2_II_DCI</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL2_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL3_II_DCI</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL3_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 </table>
 <table class="docutils align-default">
-<tr><th rowspan="2">Name</th><th colspan="1">IOSTD:V2:TERM_VCC</th></tr>
-<tr><th>[0]</th></tr>
-<tr><td>GTLP_DCI</td><td>0</td></tr>
-<tr><td>GTL_DCI</td><td>0</td></tr>
-<tr><td>HSTL_III_DCI</td><td>0</td></tr>
-<tr><td>HSTL_III_DCI_18</td><td>0</td></tr>
-<tr><td>HSTL_IV_DCI</td><td>1</td></tr>
-<tr><td>HSTL_IV_DCI_18</td><td>1</td></tr>
-<tr><td>NONE</td><td>0</td></tr>
+<tr><th rowspan="2">Name</th><th colspan="5">IOSTD:V2:PMASK_TERM_VCC</th></tr>
+<tr><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>GTLP_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>GTL_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_III_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_III_DCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_IV_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>HSTL_IV_DCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 </table>
 </section>
 <section id="i-o-data-virtex-2-pro">
 <h2>I/O data — Virtex 2 Pro<a class="headerlink" href="#i-o-data-virtex-2-pro" title="Link to this heading"></a></h2>
 <table class="docutils align-default">
-<tr><th rowspan="2">Name</th><th colspan="2">IOSTD:V2P:LVDSBIAS</th></tr>
-<tr><th>[1]</th><th>[0]</th></tr>
-<tr><td>LDT_25</td><td>1</td><td>1</td></tr>
-<tr><td>LVDSEXT_25</td><td>1</td><td>1</td></tr>
-<tr><td>LVDSEXT_25_DCI</td><td>1</td><td>1</td></tr>
-<tr><td>LVDS_25</td><td>1</td><td>1</td></tr>
-<tr><td>LVDS_25_DCI</td><td>1</td><td>1</td></tr>
-<tr><td>NONE</td><td>0</td><td>0</td></tr>
-<tr><td>ULVDS_25</td><td>1</td><td>1</td></tr>
+<tr><th rowspan="2">Name</th><th colspan="9">IOSTD:V2P:LVDSBIAS</th></tr>
+<tr><th>[8]</th><th>[7]</th><th>[6]</th><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>LDT_25</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVDSEXT_25</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVDSEXT_25_DCI</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVDS_25</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVDS_25_DCI</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>ULVDS_25</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
 </table>
 <table class="docutils align-default">
-<tr><th rowspan="2">Name</th><th colspan="7">IOSTD:V2P:TERM_SPLIT</th></tr>
-<tr><th>[6]</th><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
-<tr><td>HSTL_II_DCI</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
-<tr><td>HSTL_II_DCI_18</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
-<tr><td>HSTL_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>HSTL_I_DCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDSEXT_25_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDS_25_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>SSTL18_II_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
-<tr><td>SSTL18_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>SSTL2_II_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
-<tr><td>SSTL2_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><th rowspan="2">Name</th><th colspan="5">IOSTD:V2P:PMASK_TERM_SPLIT</th><th colspan="5">IOSTD:V2P:NMASK_TERM_SPLIT</th></tr>
+<tr><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>HSTL_II_DCI</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_II_DCI_18</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_I_DCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDSEXT_25_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDS_25_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_II_DCI</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL2_II_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL2_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 </table>
 <table class="docutils align-default">
-<tr><th rowspan="2">Name</th><th colspan="1">IOSTD:V2P:TERM_VCC</th></tr>
-<tr><th>[0]</th></tr>
-<tr><td>GTLP_DCI</td><td>0</td></tr>
-<tr><td>GTL_DCI</td><td>0</td></tr>
-<tr><td>HSTL_III_DCI</td><td>0</td></tr>
-<tr><td>HSTL_III_DCI_18</td><td>0</td></tr>
-<tr><td>HSTL_IV_DCI</td><td>1</td></tr>
-<tr><td>HSTL_IV_DCI_18</td><td>1</td></tr>
-<tr><td>NONE</td><td>0</td></tr>
+<tr><th rowspan="2">Name</th><th colspan="5">IOSTD:V2P:PMASK_TERM_VCC</th></tr>
+<tr><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>GTLP_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>GTL_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_III_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_III_DCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_IV_DCI</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_IV_DCI_18</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 </table>
 </section>
 </section>
diff --git a/xilinx/virtex4/io.html b/xilinx/virtex4/io.html
index f05e2c5c..38b0d286 100644
--- a/xilinx/virtex4/io.html
+++ b/xilinx/virtex4/io.html
@@ -222,10 +222,6 @@ <h2>Bitstream<a class="headerlink" href="#bitstream" title="Link to this heading
 <tr><td>GTLP</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>GTLP_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>GTL_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
-<tr><td>HSLVDCI_15</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>HSLVDCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>HSLVDCI_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>HSLVDCI_33</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>HSTL_I</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
 <tr><td>HSTL_II</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
 <tr><td>HSTL_III</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
@@ -271,13 +267,6 @@ <h2>Bitstream<a class="headerlink" href="#bitstream" title="Link to this heading
 <tr><td>LVCMOS33.4</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
 <tr><td>LVCMOS33.6</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
 <tr><td>LVCMOS33.8</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
-<tr><td>LVDCI_15</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDCI_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDCI_33</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDCI_DV2_15</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDCI_DV2_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDCI_DV2_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>LVPECL_25</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td></tr>
 <tr><td>LVTTL.12</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
 <tr><td>LVTTL.16</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
diff --git a/xilinx/virtex5/center.html b/xilinx/virtex5/center.html
index 1726ec7b..92cabe6c 100644
--- a/xilinx/virtex5/center.html
+++ b/xilinx/virtex5/center.html
@@ -249,7 +249,13 @@ <h2>Bitstream<a class="headerlink" href="#bitstream" title="Link to this heading
 <td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-CFG-JTAGPPC:NUM_PPC" title="JTAGPPC:NUM_PPC[2]">JTAGPPC:NUM_PPC[2]</a></td></tr>
 </table>
 <table class="docutils align-default prjcombine-tile">
-<tr><th colspan="1">CFG bittile 9</th></tr><tr><th rowspan="2">Row</th><th colspan="0">Column</th></tr><tr></tr>
+<tr><th colspan="29">CFG bittile 9</th></tr><tr><th rowspan="2">Row</th><th colspan="28">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-CFG-MISC:DCI_CLK_ENABLE" title="MISC:DCI_CLK_ENABLE[1]">MISC:DCI_CLK_ENABLE[1]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-CFG-MISC:DCI_CLK_ENABLE" title="MISC:DCI_CLK_ENABLE[0]">MISC:DCI_CLK_ENABLE[0]</a></td><td>-</td></tr>
 </table>
 <table class="docutils align-default prjcombine-tile">
 <tr><th colspan="29">CFG bittile 10</th></tr><tr><th rowspan="2">Row</th><th colspan="28">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th></tr>
@@ -2545,6 +2551,11 @@ <h2>Bitstream<a class="headerlink" href="#bitstream" title="Link to this heading
 <tr><td>3</td><td>0</td><td>1</td><td>1</td></tr>
 <tr><td>4</td><td>1</td><td>0</td><td>0</td></tr>
 </table>
+<div id="bits-xc5v-CFG-MISC:DCI_CLK_ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:DCI_CLK_ENABLE</th><th>[9, 27, 1]</th><th>[9, 26, 2]</th></tr>
+<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
+</table>
 <div id="bits-xc5v-CFG-MISC:CCLKPIN"></div>
 <div id="bits-xc5v-CFG-MISC:DONEPIN"></div>
 <div id="bits-xc5v-CFG-MISC:INITPIN"></div>
diff --git a/xilinx/virtex5/clock.html b/xilinx/virtex5/clock.html
index 9a8a1678..d81edda4 100644
--- a/xilinx/virtex5/clock.html
+++ b/xilinx/virtex5/clock.html
@@ -71,6 +71,7 @@
 <li class="toctree-l4"><a class="reference internal" href="#spine-muxes-mgt">Spine muxes — MGT</a></li>
 <li class="toctree-l4"><a class="reference internal" href="#mgt-clock-repeater">MGT clock repeater</a></li>
 <li class="toctree-l4"><a class="reference internal" href="#io-clock-nodes">IO clock nodes</a></li>
+<li class="toctree-l4"><a class="reference internal" href="#i-o-standard-data">I/O standard data</a></li>
 </ul>
 </li>
 <li class="toctree-l3"><a class="reference internal" href="ppc.html">PowerPC cores</a></li>
@@ -5055,39 +5056,39 @@ <h2>IO clock nodes<a class="headerlink" href="#io-clock-nodes" title="Link to th
 <section id="hclk-ioi">
 <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI</span></code><a class="headerlink" href="#hclk-ioi" title="Link to this heading"></a></h3>
 <table class="docutils align-default prjcombine-tile">
-<tr><th colspan="35">HCLK_IOI bittile 0</th></tr><tr><th rowspan="2">Row</th><th colspan="34">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th><th>30</th><th>31</th><th>32</th><th>33</th></tr>
+<tr><th colspan="55">HCLK_IOI bittile 0</th></tr><tr><th rowspan="2">Row</th><th colspan="54">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th><th>30</th><th>31</th><th>32</th><th>33</th><th>34</th><th>35</th><th>36</th><th>37</th><th>38</th><th>39</th><th>40</th><th>41</th><th>42</th><th>43</th><th>44</th><th>45</th><th>46</th><th>47</th><th>48</th><th>49</th><th>50</th><th>51</th><th>52</th><th>53</th></tr>
 <tr><td>0</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>1</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>2</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>3</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>4</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>5</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>6</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>7</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>8</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>9</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>10</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>11</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>12</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:ENABLE" title="BUFR1:ENABLE">BUFR1:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[0]">IDELAYCTRL:MUX.REFCLK[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[8]">BUFR1:MUX.I[8]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.RCLK1" title="IOCLK:BUF.RCLK1">IOCLK:BUF.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[5]">IDELAYCTRL:MUX.REFCLK[5]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFIO3:ENABLE" title="BUFIO3:ENABLE">BUFIO3:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK1" title="IOCLK:BUF.HCLK1">IOCLK:BUF.HCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK0" title="IOCLK:BUF.HCLK0">IOCLK:BUF.HCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK2" title="IOCLK:BUF.HCLK2">IOCLK:BUF.HCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[6]">BUFR1:MUX.I[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFIO0:ENABLE" title="BUFIO0:ENABLE">BUFIO0:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK3" title="RCLK:MUX.RCLK3[2]">RCLK:MUX.RCLK3[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[7]">BUFR1:MUX.I[7]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[10]">BUFR1:MUX.I[10]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[9]">BUFR1:MUX.I[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[1]">BUFR1:MUX.I[1]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK2" title="RCLK:MUX.RCLK2[2]">RCLK:MUX.RCLK2[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.RCLK2" title="IOCLK:BUF.RCLK2">IOCLK:BUF.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK5" title="IOCLK:BUF.HCLK5">IOCLK:BUF.HCLK5</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK6" title="IOCLK:BUF.HCLK6">IOCLK:BUF.HCLK6</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[10]">BUFR0:MUX.I[10]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:ENABLE" title="BUFR0:ENABLE">BUFR0:ENABLE</a></td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:ENABLE" title="BUFR1:ENABLE">BUFR1:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[0]">IDELAYCTRL:MUX.REFCLK[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[8]">BUFR1:MUX.I[8]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.RCLK1" title="IOCLK:BUF.RCLK1">IOCLK:BUF.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[5]">IDELAYCTRL:MUX.REFCLK[5]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFIO3:ENABLE" title="BUFIO3:ENABLE">BUFIO3:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK1" title="IOCLK:BUF.HCLK1">IOCLK:BUF.HCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK0" title="IOCLK:BUF.HCLK0">IOCLK:BUF.HCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK2" title="IOCLK:BUF.HCLK2">IOCLK:BUF.HCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[6]">BUFR1:MUX.I[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFIO0:ENABLE" title="BUFIO0:ENABLE">BUFIO0:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK3" title="RCLK:MUX.RCLK3[2]">RCLK:MUX.RCLK3[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[7]">BUFR1:MUX.I[7]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[10]">BUFR1:MUX.I[10]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[9]">BUFR1:MUX.I[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[1]">BUFR1:MUX.I[1]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK2" title="RCLK:MUX.RCLK2[2]">RCLK:MUX.RCLK2[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.RCLK2" title="IOCLK:BUF.RCLK2">IOCLK:BUF.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK5" title="IOCLK:BUF.HCLK5">IOCLK:BUF.HCLK5</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK6" title="IOCLK:BUF.HCLK6">IOCLK:BUF.HCLK6</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[10]">BUFR0:MUX.I[10]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:ENABLE" title="BUFR0:ENABLE">BUFR0:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[11]">LVDS:LVDSBIAS[11]</a></td><td><a href="#bits-xc5v-HCLK_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[10]">LVDS:LVDSBIAS[10]</a></td><td><a href="#bits-xc5v-HCLK_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[6]">LVDS:LVDSBIAS[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[7]">LVDS:LVDSBIAS[7]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[1]">INTERNAL_VREF:VREF[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[0]">INTERNAL_VREF:VREF[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[1]">DCI:PMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[2]">DCI:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[3]">DCI:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[2]">DCI:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:PREF" title="DCI:PREF[1]">DCI:PREF[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:PREF" title="DCI:PREF[0]">DCI:PREF[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:LVDIV2" title="DCI:LVDIV2[0]">DCI:LVDIV2[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:LVDIV2" title="DCI:LVDIV2[1]">DCI:LVDIV2[1]</a></td></tr>
 <tr><td>13</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.RCLK0" title="IOCLK:BUF.RCLK0">IOCLK:BUF.RCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[3]">IDELAYCTRL:MUX.REFCLK[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK3" title="IOCLK:BUF.HCLK3">IOCLK:BUF.HCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK4" title="IOCLK:BUF.HCLK4">IOCLK:BUF.HCLK4</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[5]">BUFR1:MUX.I[5]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK3" title="RCLK:MUX.RCLK3[3]">RCLK:MUX.RCLK3[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK2" title="RCLK:MUX.RCLK2[0]">RCLK:MUX.RCLK2[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK3" title="RCLK:MUX.RCLK3[0]">RCLK:MUX.RCLK3[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK3" title="RCLK:MUX.RCLK3[1]">RCLK:MUX.RCLK3[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFIO2:ENABLE" title="BUFIO2:ENABLE">BUFIO2:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFIO1:ENABLE" title="BUFIO1:ENABLE">BUFIO1:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[0]">BUFR1:MUX.I[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[4]">BUFR1:MUX.I[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[3]">BUFR1:MUX.I[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[2]">BUFR1:MUX.I[2]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[2]">IDELAYCTRL:MUX.REFCLK[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[1]">IDELAYCTRL:MUX.REFCLK[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK8" title="IOCLK:BUF.HCLK8">IOCLK:BUF.HCLK8</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK7" title="IOCLK:BUF.HCLK7">IOCLK:BUF.HCLK7</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[9]">BUFR0:MUX.I[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[2]">BUFR0:MUX.I[2]</a></td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.RCLK0" title="IOCLK:BUF.RCLK0">IOCLK:BUF.RCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[3]">IDELAYCTRL:MUX.REFCLK[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK3" title="IOCLK:BUF.HCLK3">IOCLK:BUF.HCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK4" title="IOCLK:BUF.HCLK4">IOCLK:BUF.HCLK4</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[5]">BUFR1:MUX.I[5]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK3" title="RCLK:MUX.RCLK3[3]">RCLK:MUX.RCLK3[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK2" title="RCLK:MUX.RCLK2[0]">RCLK:MUX.RCLK2[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK3" title="RCLK:MUX.RCLK3[0]">RCLK:MUX.RCLK3[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK3" title="RCLK:MUX.RCLK3[1]">RCLK:MUX.RCLK3[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFIO2:ENABLE" title="BUFIO2:ENABLE">BUFIO2:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFIO1:ENABLE" title="BUFIO1:ENABLE">BUFIO1:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[0]">BUFR1:MUX.I[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[4]">BUFR1:MUX.I[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[3]">BUFR1:MUX.I[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:MUX.I" title="BUFR1:MUX.I[2]">BUFR1:MUX.I[2]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[2]">IDELAYCTRL:MUX.REFCLK[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[1]">IDELAYCTRL:MUX.REFCLK[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK8" title="IOCLK:BUF.HCLK8">IOCLK:BUF.HCLK8</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK7" title="IOCLK:BUF.HCLK7">IOCLK:BUF.HCLK7</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[9]">BUFR0:MUX.I[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[2]">BUFR0:MUX.I[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[8]">LVDS:LVDSBIAS[8]</a></td><td><a href="#bits-xc5v-HCLK_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[9]">LVDS:LVDSBIAS[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[5]">LVDS:LVDSBIAS[5]</a></td><td><a href="#bits-xc5v-HCLK_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[4]">LVDS:LVDSBIAS[4]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[2]">INTERNAL_VREF:VREF[2]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[0]">DCI:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:CASCADE_FROM_BELOW" title="DCI:CASCADE_FROM_BELOW">DCI:CASCADE_FROM_BELOW</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[0]">DCI:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[1]">DCI:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[4]">DCI:PMASK_TERM_VCC[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[3]">DCI:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:NREF" title="DCI:NREF[1]">DCI:NREF[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:TEST_ENABLE" title="DCI:TEST_ENABLE[1]">DCI:TEST_ENABLE[1]</a></td></tr>
 <tr><td>14</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK1" title="RCLK:MUX.RCLK1[2]">RCLK:MUX.RCLK1[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK1" title="RCLK:MUX.RCLK1[1]">RCLK:MUX.RCLK1[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[7]">IDELAYCTRL:MUX.REFCLK[7]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[6]">IDELAYCTRL:MUX.REFCLK[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK1" title="RCLK:MUX.RCLK1[0]">RCLK:MUX.RCLK1[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[0]">IOCLK:IOCLK_ENABLE[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:BUFR_DIVIDE" title="BUFR0:BUFR_DIVIDE[2]">BUFR0:BUFR_DIVIDE[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:BUFR_DIVIDE" title="BUFR0:BUFR_DIVIDE[1]">BUFR0:BUFR_DIVIDE[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:BUFR_DIVIDE" title="BUFR0:BUFR_DIVIDE[0]">BUFR0:BUFR_DIVIDE[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[4]">IDELAYCTRL:MUX.REFCLK[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:BUFR_DIVIDE" title="BUFR1:BUFR_DIVIDE[3]">BUFR1:BUFR_DIVIDE[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK9" title="IOCLK:BUF.HCLK9">IOCLK:BUF.HCLK9</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK0" title="RCLK:MUX.RCLK0[3]">RCLK:MUX.RCLK0[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[4]">BUFR0:MUX.I[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[3]">BUFR0:MUX.I[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[0]">BUFR0:MUX.I[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[1]">BUFR0:MUX.I[1]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK1" title="RCLK:MUX.RCLK1[2]">RCLK:MUX.RCLK1[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK1" title="RCLK:MUX.RCLK1[1]">RCLK:MUX.RCLK1[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[7]">IDELAYCTRL:MUX.REFCLK[7]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[6]">IDELAYCTRL:MUX.REFCLK[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK1" title="RCLK:MUX.RCLK1[0]">RCLK:MUX.RCLK1[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[0]">IOCLK:IOCLK_ENABLE[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:BUFR_DIVIDE" title="BUFR0:BUFR_DIVIDE[2]">BUFR0:BUFR_DIVIDE[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:BUFR_DIVIDE" title="BUFR0:BUFR_DIVIDE[1]">BUFR0:BUFR_DIVIDE[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:BUFR_DIVIDE" title="BUFR0:BUFR_DIVIDE[0]">BUFR0:BUFR_DIVIDE[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[4]">IDELAYCTRL:MUX.REFCLK[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:BUFR_DIVIDE" title="BUFR1:BUFR_DIVIDE[3]">BUFR1:BUFR_DIVIDE[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK9" title="IOCLK:BUF.HCLK9">IOCLK:BUF.HCLK9</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK0" title="RCLK:MUX.RCLK0[3]">RCLK:MUX.RCLK0[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[4]">BUFR0:MUX.I[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[3]">BUFR0:MUX.I[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[0]">BUFR0:MUX.I[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[1]">BUFR0:MUX.I[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[2]">LVDS:LVDSBIAS[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[3]">LVDS:LVDSBIAS[3]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-DCI:ENABLE" title="DCI:ENABLE">DCI:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:CASCADE_FROM_ABOVE" title="DCI:CASCADE_FROM_ABOVE">DCI:CASCADE_FROM_ABOVE</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:QUIET" title="DCI:QUIET">DCI:QUIET</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:TEST_ENABLE" title="DCI:TEST_ENABLE[0]">DCI:TEST_ENABLE[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[1]">DCI:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[2]">DCI:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:NREF" title="DCI:NREF[0]">DCI:NREF[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:PREF" title="DCI:PREF[2]">DCI:PREF[2]</a></td></tr>
 <tr><td>15</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:BUFR_DIVIDE" title="BUFR1:BUFR_DIVIDE[1]">BUFR1:BUFR_DIVIDE[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.RCLK3" title="IOCLK:BUF.RCLK3">IOCLK:BUF.RCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[9]">IDELAYCTRL:MUX.REFCLK[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[8]">IDELAYCTRL:MUX.REFCLK[8]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK2" title="RCLK:MUX.RCLK2[3]">RCLK:MUX.RCLK2[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK2" title="RCLK:MUX.RCLK2[1]">RCLK:MUX.RCLK2[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:BUFR_DIVIDE" title="BUFR1:BUFR_DIVIDE[0]">BUFR1:BUFR_DIVIDE[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[1]">IOCLK:IOCLK_ENABLE[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:BUFR_DIVIDE" title="BUFR0:BUFR_DIVIDE[3]">BUFR0:BUFR_DIVIDE[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK1" title="RCLK:MUX.RCLK1[3]">RCLK:MUX.RCLK1[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK0" title="RCLK:MUX.RCLK0[0]">RCLK:MUX.RCLK0[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:BUFR_DIVIDE" title="BUFR1:BUFR_DIVIDE[2]">BUFR1:BUFR_DIVIDE[2]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK0" title="RCLK:MUX.RCLK0[2]">RCLK:MUX.RCLK0[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK0" title="RCLK:MUX.RCLK0[1]">RCLK:MUX.RCLK0[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[5]">BUFR0:MUX.I[5]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[6]">BUFR0:MUX.I[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[8]">BUFR0:MUX.I[8]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[7]">BUFR0:MUX.I[7]</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:BUFR_DIVIDE" title="BUFR1:BUFR_DIVIDE[1]">BUFR1:BUFR_DIVIDE[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:BUF.RCLK3" title="IOCLK:BUF.RCLK3">IOCLK:BUF.RCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[9]">IDELAYCTRL:MUX.REFCLK[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[8]">IDELAYCTRL:MUX.REFCLK[8]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK2" title="RCLK:MUX.RCLK2[3]">RCLK:MUX.RCLK2[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK2" title="RCLK:MUX.RCLK2[1]">RCLK:MUX.RCLK2[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:BUFR_DIVIDE" title="BUFR1:BUFR_DIVIDE[0]">BUFR1:BUFR_DIVIDE[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[1]">IOCLK:IOCLK_ENABLE[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:BUFR_DIVIDE" title="BUFR0:BUFR_DIVIDE[3]">BUFR0:BUFR_DIVIDE[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK1" title="RCLK:MUX.RCLK1[3]">RCLK:MUX.RCLK1[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK0" title="RCLK:MUX.RCLK0[0]">RCLK:MUX.RCLK0[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-BUFR1:BUFR_DIVIDE" title="BUFR1:BUFR_DIVIDE[2]">BUFR1:BUFR_DIVIDE[2]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK0" title="RCLK:MUX.RCLK0[2]">RCLK:MUX.RCLK0[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI-RCLK:MUX.RCLK0" title="RCLK:MUX.RCLK0[1]">RCLK:MUX.RCLK0[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[5]">BUFR0:MUX.I[5]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[6]">BUFR0:MUX.I[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[8]">BUFR0:MUX.I[8]</a></td><td><a href="#bits-xc5v-HCLK_IOI-BUFR0:MUX.I" title="BUFR0:MUX.I[7]">BUFR0:MUX.I[7]</a></td><td><a href="#bits-xc5v-HCLK_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[1]">LVDS:LVDSBIAS[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[0]">LVDS:LVDSBIAS[0]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[3]">INTERNAL_VREF:VREF[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[4]">INTERNAL_VREF:VREF[4]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[3]">DCI:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[4]">DCI:PMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[0]">DCI:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[4]">DCI:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:PREF" title="DCI:PREF[3]">DCI:PREF[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI-DCI:LVDIV2" title="DCI:LVDIV2[2]">DCI:LVDIV2[2]</a></td></tr>
 </table>
 <div id="bits-xc5v-HCLK_IOI-BUFIO0:ENABLE"></div>
 <div id="bits-xc5v-HCLK_IOI-BUFIO1:ENABLE"></div>
@@ -5095,6 +5096,10 @@ <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI</span>
 <div id="bits-xc5v-HCLK_IOI-BUFIO3:ENABLE"></div>
 <div id="bits-xc5v-HCLK_IOI-BUFR0:ENABLE"></div>
 <div id="bits-xc5v-HCLK_IOI-BUFR1:ENABLE"></div>
+<div id="bits-xc5v-HCLK_IOI-DCI:CASCADE_FROM_ABOVE"></div>
+<div id="bits-xc5v-HCLK_IOI-DCI:CASCADE_FROM_BELOW"></div>
+<div id="bits-xc5v-HCLK_IOI-DCI:ENABLE"></div>
+<div id="bits-xc5v-HCLK_IOI-DCI:QUIET"></div>
 <div id="bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK0"></div>
 <div id="bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK1"></div>
 <div id="bits-xc5v-HCLK_IOI-IOCLK:BUF.HCLK2"></div>
@@ -5116,6 +5121,10 @@ <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI</span>
 <tr><th>BUFIO3:ENABLE</th><th>[0, 14, 12]</th></tr>
 <tr><th>BUFR0:ENABLE</th><th>[0, 31, 12]</th></tr>
 <tr><th>BUFR1:ENABLE</th><th>[0, 9, 12]</th></tr>
+<tr><th>DCI:CASCADE_FROM_ABOVE</th><th>[0, 47, 14]</th></tr>
+<tr><th>DCI:CASCADE_FROM_BELOW</th><th>[0, 47, 13]</th></tr>
+<tr><th>DCI:ENABLE</th><th>[0, 46, 14]</th></tr>
+<tr><th>DCI:QUIET</th><th>[0, 48, 14]</th></tr>
 <tr><th>IOCLK:BUF.HCLK0</th><th>[0, 16, 12]</th></tr>
 <tr><th>IOCLK:BUF.HCLK1</th><th>[0, 15, 12]</th></tr>
 <tr><th>IOCLK:BUF.HCLK2</th><th>[0, 17, 12]</th></tr>
@@ -5179,8 +5188,12 @@ <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI</span>
 <tr><td>7</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
 <tr><td>8</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
 </table>
+<div id="bits-xc5v-HCLK_IOI-DCI:NREF"></div>
+<div id="bits-xc5v-HCLK_IOI-DCI:TEST_ENABLE"></div>
 <div id="bits-xc5v-HCLK_IOI-IOCLK:IOCLK_ENABLE"></div>
 <table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:NREF</th><th>[0, 52, 13]</th><th>[0, 52, 14]</th></tr>
+<tr><th>DCI:TEST_ENABLE</th><th>[0, 53, 13]</th><th>[0, 49, 14]</th></tr>
 <tr><th>IOCLK:IOCLK_ENABLE</th><th>[0, 15, 15]</th><th>[0, 15, 14]</th></tr>
 <tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
 </table>
@@ -5202,48 +5215,85 @@ <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI</span>
 <tr><td>MGT3</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>MGT4</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 </table>
+<div id="bits-xc5v-HCLK_IOI-LVDS:LVDSBIAS"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>LVDS:LVDSBIAS</th><th>[0, 32, 12]</th><th>[0, 33, 12]</th><th>[0, 33, 13]</th><th>[0, 32, 13]</th><th>[0, 35, 12]</th><th>[0, 34, 12]</th><th>[0, 34, 13]</th><th>[0, 35, 13]</th><th>[0, 35, 14]</th><th>[0, 34, 14]</th><th>[0, 34, 15]</th><th>[0, 35, 15]</th></tr>
+<tr><td>Non-inverted</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI-INTERNAL_VREF:VREF"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>INTERNAL_VREF:VREF</th><th>[0, 39, 15]</th><th>[0, 38, 15]</th><th>[0, 38, 13]</th><th>[0, 38, 12]</th><th>[0, 39, 12]</th></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>750</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>900</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>1080</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>1250</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI-DCI:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc5v-HCLK_IOI-DCI:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc5v-HCLK_IOI-DCI:PMASK_TERM_VCC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:NMASK_TERM_SPLIT</th><th>[0, 51, 15]</th><th>[0, 48, 12]</th><th>[0, 49, 12]</th><th>[0, 49, 13]</th><th>[0, 48, 13]</th></tr>
+<tr><th>DCI:PMASK_TERM_SPLIT</th><th>[0, 49, 15]</th><th>[0, 48, 15]</th><th>[0, 47, 12]</th><th>[0, 46, 12]</th><th>[0, 46, 13]</th></tr>
+<tr><th>DCI:PMASK_TERM_VCC</th><th>[0, 50, 13]</th><th>[0, 51, 13]</th><th>[0, 51, 14]</th><th>[0, 50, 14]</th><th>[0, 50, 15]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI-DCI:PREF"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:PREF</th><th>[0, 52, 15]</th><th>[0, 53, 14]</th><th>[0, 50, 12]</th><th>[0, 51, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI-DCI:LVDIV2"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:LVDIV2</th><th>[0, 53, 15]</th><th>[0, 53, 12]</th><th>[0, 52, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
 </section>
 <section id="hclk-ioi-center">
 <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI_CENTER</span></code><a class="headerlink" href="#hclk-ioi-center" title="Link to this heading"></a></h3>
 <table class="docutils align-default prjcombine-tile">
-<tr><th colspan="31">HCLK_IOI_CENTER bittile 0</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><th colspan="55">HCLK_IOI_CENTER bittile 0</th></tr><tr><th rowspan="2">Row</th><th colspan="54">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th><th>30</th><th>31</th><th>32</th><th>33</th><th>34</th><th>35</th><th>36</th><th>37</th><th>38</th><th>39</th><th>40</th><th>41</th><th>42</th><th>43</th><th>44</th><th>45</th><th>46</th><th>47</th><th>48</th><th>49</th><th>50</th><th>51</th><th>52</th><th>53</th></tr>
 <tr><td>0</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>1</td>
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 <tr><td>2</td>
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+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>3</td>
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+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>4</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>5</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>6</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>7</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>8</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>9</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>10</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>11</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>12</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[0]">IDELAYCTRL:MUX.REFCLK[0]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.RCLK1" title="IOCLK:BUF.RCLK1">IOCLK:BUF.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[5]">IDELAYCTRL:MUX.REFCLK[5]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-BUFIO3:ENABLE" title="BUFIO3:ENABLE">BUFIO3:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK1" title="IOCLK:BUF.HCLK1">IOCLK:BUF.HCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK0" title="IOCLK:BUF.HCLK0">IOCLK:BUF.HCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK2" title="IOCLK:BUF.HCLK2">IOCLK:BUF.HCLK2</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-BUFIO0:ENABLE" title="BUFIO0:ENABLE">BUFIO0:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.RCLK2" title="IOCLK:BUF.RCLK2">IOCLK:BUF.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK5" title="IOCLK:BUF.HCLK5">IOCLK:BUF.HCLK5</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK6" title="IOCLK:BUF.HCLK6">IOCLK:BUF.HCLK6</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[0]">IDELAYCTRL:MUX.REFCLK[0]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.RCLK1" title="IOCLK:BUF.RCLK1">IOCLK:BUF.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[5]">IDELAYCTRL:MUX.REFCLK[5]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-BUFIO3:ENABLE" title="BUFIO3:ENABLE">BUFIO3:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK1" title="IOCLK:BUF.HCLK1">IOCLK:BUF.HCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK0" title="IOCLK:BUF.HCLK0">IOCLK:BUF.HCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK2" title="IOCLK:BUF.HCLK2">IOCLK:BUF.HCLK2</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-BUFIO0:ENABLE" title="BUFIO0:ENABLE">BUFIO0:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.RCLK2" title="IOCLK:BUF.RCLK2">IOCLK:BUF.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK5" title="IOCLK:BUF.HCLK5">IOCLK:BUF.HCLK5</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK6" title="IOCLK:BUF.HCLK6">IOCLK:BUF.HCLK6</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[11]">LVDS:LVDSBIAS[11]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[10]">LVDS:LVDSBIAS[10]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[6]">LVDS:LVDSBIAS[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[7]">LVDS:LVDSBIAS[7]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[1]">INTERNAL_VREF:VREF[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[0]">INTERNAL_VREF:VREF[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[1]">DCI:PMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[2]">DCI:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[3]">DCI:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[2]">DCI:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:PREF" title="DCI:PREF[1]">DCI:PREF[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:PREF" title="DCI:PREF[0]">DCI:PREF[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:LVDIV2" title="DCI:LVDIV2[0]">DCI:LVDIV2[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:LVDIV2" title="DCI:LVDIV2[1]">DCI:LVDIV2[1]</a></td></tr>
 <tr><td>13</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.RCLK0" title="IOCLK:BUF.RCLK0">IOCLK:BUF.RCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[3]">IDELAYCTRL:MUX.REFCLK[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK3" title="IOCLK:BUF.HCLK3">IOCLK:BUF.HCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK4" title="IOCLK:BUF.HCLK4">IOCLK:BUF.HCLK4</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:ENABLE.RCLK2" title="IOCLK:ENABLE.RCLK2">IOCLK:ENABLE.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:ENABLE.RCLK3" title="IOCLK:ENABLE.RCLK3">IOCLK:ENABLE.RCLK3</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-BUFIO2:ENABLE" title="BUFIO2:ENABLE">BUFIO2:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-BUFIO1:ENABLE" title="BUFIO1:ENABLE">BUFIO1:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[2]">IDELAYCTRL:MUX.REFCLK[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[1]">IDELAYCTRL:MUX.REFCLK[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK8" title="IOCLK:BUF.HCLK8">IOCLK:BUF.HCLK8</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK7" title="IOCLK:BUF.HCLK7">IOCLK:BUF.HCLK7</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.RCLK0" title="IOCLK:BUF.RCLK0">IOCLK:BUF.RCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[3]">IDELAYCTRL:MUX.REFCLK[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK3" title="IOCLK:BUF.HCLK3">IOCLK:BUF.HCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK4" title="IOCLK:BUF.HCLK4">IOCLK:BUF.HCLK4</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:ENABLE.RCLK2" title="IOCLK:ENABLE.RCLK2">IOCLK:ENABLE.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:ENABLE.RCLK3" title="IOCLK:ENABLE.RCLK3">IOCLK:ENABLE.RCLK3</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-BUFIO2:ENABLE" title="BUFIO2:ENABLE">BUFIO2:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-BUFIO1:ENABLE" title="BUFIO1:ENABLE">BUFIO1:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[2]">IDELAYCTRL:MUX.REFCLK[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[1]">IDELAYCTRL:MUX.REFCLK[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK8" title="IOCLK:BUF.HCLK8">IOCLK:BUF.HCLK8</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK7" title="IOCLK:BUF.HCLK7">IOCLK:BUF.HCLK7</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[8]">LVDS:LVDSBIAS[8]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[9]">LVDS:LVDSBIAS[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[5]">LVDS:LVDSBIAS[5]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[4]">LVDS:LVDSBIAS[4]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[2]">INTERNAL_VREF:VREF[2]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[0]">DCI:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:CASCADE_FROM_BELOW" title="DCI:CASCADE_FROM_BELOW">DCI:CASCADE_FROM_BELOW</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[0]">DCI:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[1]">DCI:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[4]">DCI:PMASK_TERM_VCC[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[3]">DCI:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:NREF" title="DCI:NREF[1]">DCI:NREF[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:TEST_ENABLE" title="DCI:TEST_ENABLE[1]">DCI:TEST_ENABLE[1]</a></td></tr>
 <tr><td>14</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[7]">IDELAYCTRL:MUX.REFCLK[7]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[6]">IDELAYCTRL:MUX.REFCLK[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:ENABLE.RCLK1" title="IOCLK:ENABLE.RCLK1">IOCLK:ENABLE.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[0]">IOCLK:IOCLK_ENABLE[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[4]">IDELAYCTRL:MUX.REFCLK[4]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK9" title="IOCLK:BUF.HCLK9">IOCLK:BUF.HCLK9</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[7]">IDELAYCTRL:MUX.REFCLK[7]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[6]">IDELAYCTRL:MUX.REFCLK[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:ENABLE.RCLK1" title="IOCLK:ENABLE.RCLK1">IOCLK:ENABLE.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[0]">IOCLK:IOCLK_ENABLE[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[4]">IDELAYCTRL:MUX.REFCLK[4]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK9" title="IOCLK:BUF.HCLK9">IOCLK:BUF.HCLK9</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[2]">LVDS:LVDSBIAS[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[3]">LVDS:LVDSBIAS[3]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:ENABLE" title="DCI:ENABLE">DCI:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:CASCADE_FROM_ABOVE" title="DCI:CASCADE_FROM_ABOVE">DCI:CASCADE_FROM_ABOVE</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:QUIET" title="DCI:QUIET">DCI:QUIET</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:TEST_ENABLE" title="DCI:TEST_ENABLE[0]">DCI:TEST_ENABLE[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[1]">DCI:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[2]">DCI:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:NREF" title="DCI:NREF[0]">DCI:NREF[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:PREF" title="DCI:PREF[2]">DCI:PREF[2]</a></td></tr>
 <tr><td>15</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.RCLK3" title="IOCLK:BUF.RCLK3">IOCLK:BUF.RCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[9]">IDELAYCTRL:MUX.REFCLK[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[8]">IDELAYCTRL:MUX.REFCLK[8]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[1]">IOCLK:IOCLK_ENABLE[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:ENABLE.RCLK0" title="IOCLK:ENABLE.RCLK0">IOCLK:ENABLE.RCLK0</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.RCLK3" title="IOCLK:BUF.RCLK3">IOCLK:BUF.RCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[9]">IDELAYCTRL:MUX.REFCLK[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[8]">IDELAYCTRL:MUX.REFCLK[8]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[1]">IOCLK:IOCLK_ENABLE[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-IOCLK:ENABLE.RCLK0" title="IOCLK:ENABLE.RCLK0">IOCLK:ENABLE.RCLK0</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[1]">LVDS:LVDSBIAS[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[0]">LVDS:LVDSBIAS[0]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[3]">INTERNAL_VREF:VREF[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[4]">INTERNAL_VREF:VREF[4]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[3]">DCI:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[4]">DCI:PMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[0]">DCI:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[4]">DCI:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:PREF" title="DCI:PREF[3]">DCI:PREF[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CENTER-DCI:LVDIV2" title="DCI:LVDIV2[2]">DCI:LVDIV2[2]</a></td></tr>
 </table>
 <div id="bits-xc5v-HCLK_IOI_CENTER-BUFIO0:ENABLE"></div>
 <div id="bits-xc5v-HCLK_IOI_CENTER-BUFIO1:ENABLE"></div>
 <div id="bits-xc5v-HCLK_IOI_CENTER-BUFIO2:ENABLE"></div>
 <div id="bits-xc5v-HCLK_IOI_CENTER-BUFIO3:ENABLE"></div>
+<div id="bits-xc5v-HCLK_IOI_CENTER-DCI:CASCADE_FROM_ABOVE"></div>
+<div id="bits-xc5v-HCLK_IOI_CENTER-DCI:CASCADE_FROM_BELOW"></div>
+<div id="bits-xc5v-HCLK_IOI_CENTER-DCI:ENABLE"></div>
+<div id="bits-xc5v-HCLK_IOI_CENTER-DCI:QUIET"></div>
 <div id="bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK0"></div>
 <div id="bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK1"></div>
 <div id="bits-xc5v-HCLK_IOI_CENTER-IOCLK:BUF.HCLK2"></div>
@@ -5267,6 +5317,10 @@ <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI_CENTER
 <tr><th>BUFIO1:ENABLE</th><th>[0, 19, 13]</th></tr>
 <tr><th>BUFIO2:ENABLE</th><th>[0, 18, 13]</th></tr>
 <tr><th>BUFIO3:ENABLE</th><th>[0, 14, 12]</th></tr>
+<tr><th>DCI:CASCADE_FROM_ABOVE</th><th>[0, 47, 14]</th></tr>
+<tr><th>DCI:CASCADE_FROM_BELOW</th><th>[0, 47, 13]</th></tr>
+<tr><th>DCI:ENABLE</th><th>[0, 46, 14]</th></tr>
+<tr><th>DCI:QUIET</th><th>[0, 48, 14]</th></tr>
 <tr><th>IOCLK:BUF.HCLK0</th><th>[0, 16, 12]</th></tr>
 <tr><th>IOCLK:BUF.HCLK1</th><th>[0, 15, 12]</th></tr>
 <tr><th>IOCLK:BUF.HCLK2</th><th>[0, 17, 12]</th></tr>
@@ -5302,51 +5356,92 @@ <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI_CENTER
 <tr><td>HCLK8</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>HCLK9</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 </table>
+<div id="bits-xc5v-HCLK_IOI_CENTER-DCI:NREF"></div>
+<div id="bits-xc5v-HCLK_IOI_CENTER-DCI:TEST_ENABLE"></div>
 <div id="bits-xc5v-HCLK_IOI_CENTER-IOCLK:IOCLK_ENABLE"></div>
 <table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:NREF</th><th>[0, 52, 13]</th><th>[0, 52, 14]</th></tr>
+<tr><th>DCI:TEST_ENABLE</th><th>[0, 53, 13]</th><th>[0, 49, 14]</th></tr>
 <tr><th>IOCLK:IOCLK_ENABLE</th><th>[0, 15, 15]</th><th>[0, 15, 14]</th></tr>
 <tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
 </table>
+<div id="bits-xc5v-HCLK_IOI_CENTER-LVDS:LVDSBIAS"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>LVDS:LVDSBIAS</th><th>[0, 32, 12]</th><th>[0, 33, 12]</th><th>[0, 33, 13]</th><th>[0, 32, 13]</th><th>[0, 35, 12]</th><th>[0, 34, 12]</th><th>[0, 34, 13]</th><th>[0, 35, 13]</th><th>[0, 35, 14]</th><th>[0, 34, 14]</th><th>[0, 34, 15]</th><th>[0, 35, 15]</th></tr>
+<tr><td>Non-inverted</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_CENTER-INTERNAL_VREF:VREF"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>INTERNAL_VREF:VREF</th><th>[0, 39, 15]</th><th>[0, 38, 15]</th><th>[0, 38, 13]</th><th>[0, 38, 12]</th><th>[0, 39, 12]</th></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>750</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>900</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>1080</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>1250</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_CENTER-DCI:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc5v-HCLK_IOI_CENTER-DCI:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc5v-HCLK_IOI_CENTER-DCI:PMASK_TERM_VCC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:NMASK_TERM_SPLIT</th><th>[0, 51, 15]</th><th>[0, 48, 12]</th><th>[0, 49, 12]</th><th>[0, 49, 13]</th><th>[0, 48, 13]</th></tr>
+<tr><th>DCI:PMASK_TERM_SPLIT</th><th>[0, 49, 15]</th><th>[0, 48, 15]</th><th>[0, 47, 12]</th><th>[0, 46, 12]</th><th>[0, 46, 13]</th></tr>
+<tr><th>DCI:PMASK_TERM_VCC</th><th>[0, 50, 13]</th><th>[0, 51, 13]</th><th>[0, 51, 14]</th><th>[0, 50, 14]</th><th>[0, 50, 15]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_CENTER-DCI:PREF"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:PREF</th><th>[0, 52, 15]</th><th>[0, 53, 14]</th><th>[0, 50, 12]</th><th>[0, 51, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_CENTER-DCI:LVDIV2"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:LVDIV2</th><th>[0, 53, 15]</th><th>[0, 53, 12]</th><th>[0, 52, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
 </section>
 <section id="hclk-ioi-botcen">
 <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI_BOTCEN</span></code><a class="headerlink" href="#hclk-ioi-botcen" title="Link to this heading"></a></h3>
 <table class="docutils align-default prjcombine-tile">
-<tr><th colspan="31">HCLK_IOI_BOTCEN bittile 0</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><th colspan="55">HCLK_IOI_BOTCEN bittile 0</th></tr><tr><th rowspan="2">Row</th><th colspan="54">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th><th>30</th><th>31</th><th>32</th><th>33</th><th>34</th><th>35</th><th>36</th><th>37</th><th>38</th><th>39</th><th>40</th><th>41</th><th>42</th><th>43</th><th>44</th><th>45</th><th>46</th><th>47</th><th>48</th><th>49</th><th>50</th><th>51</th><th>52</th><th>53</th></tr>
 <tr><td>0</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>1</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>2</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>3</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>4</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>5</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>6</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>7</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>8</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>9</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>10</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>11</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>12</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[0]">IDELAYCTRL:MUX.REFCLK[0]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.RCLK1" title="IOCLK:BUF.RCLK1">IOCLK:BUF.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[5]">IDELAYCTRL:MUX.REFCLK[5]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-BUFIO3:ENABLE" title="BUFIO3:ENABLE">BUFIO3:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK1" title="IOCLK:BUF.HCLK1">IOCLK:BUF.HCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK0" title="IOCLK:BUF.HCLK0">IOCLK:BUF.HCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK2" title="IOCLK:BUF.HCLK2">IOCLK:BUF.HCLK2</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.RCLK2" title="IOCLK:BUF.RCLK2">IOCLK:BUF.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK5" title="IOCLK:BUF.HCLK5">IOCLK:BUF.HCLK5</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK6" title="IOCLK:BUF.HCLK6">IOCLK:BUF.HCLK6</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[0]">IDELAYCTRL:MUX.REFCLK[0]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.RCLK1" title="IOCLK:BUF.RCLK1">IOCLK:BUF.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[5]">IDELAYCTRL:MUX.REFCLK[5]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-BUFIO3:ENABLE" title="BUFIO3:ENABLE">BUFIO3:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK1" title="IOCLK:BUF.HCLK1">IOCLK:BUF.HCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK0" title="IOCLK:BUF.HCLK0">IOCLK:BUF.HCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK2" title="IOCLK:BUF.HCLK2">IOCLK:BUF.HCLK2</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.RCLK2" title="IOCLK:BUF.RCLK2">IOCLK:BUF.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK5" title="IOCLK:BUF.HCLK5">IOCLK:BUF.HCLK5</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK6" title="IOCLK:BUF.HCLK6">IOCLK:BUF.HCLK6</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[11]">LVDS:LVDSBIAS[11]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[10]">LVDS:LVDSBIAS[10]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[6]">LVDS:LVDSBIAS[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[7]">LVDS:LVDSBIAS[7]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[1]">INTERNAL_VREF:VREF[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[0]">INTERNAL_VREF:VREF[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[1]">DCI:PMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[2]">DCI:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[3]">DCI:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[2]">DCI:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:PREF" title="DCI:PREF[1]">DCI:PREF[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:PREF" title="DCI:PREF[0]">DCI:PREF[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:LVDIV2" title="DCI:LVDIV2[0]">DCI:LVDIV2[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:LVDIV2" title="DCI:LVDIV2[1]">DCI:LVDIV2[1]</a></td></tr>
 <tr><td>13</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.RCLK0" title="IOCLK:BUF.RCLK0">IOCLK:BUF.RCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[3]">IDELAYCTRL:MUX.REFCLK[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK3" title="IOCLK:BUF.HCLK3">IOCLK:BUF.HCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK4" title="IOCLK:BUF.HCLK4">IOCLK:BUF.HCLK4</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:ENABLE.RCLK2" title="IOCLK:ENABLE.RCLK2">IOCLK:ENABLE.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:ENABLE.RCLK3" title="IOCLK:ENABLE.RCLK3">IOCLK:ENABLE.RCLK3</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-BUFIO2:ENABLE" title="BUFIO2:ENABLE">BUFIO2:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[2]">IDELAYCTRL:MUX.REFCLK[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[1]">IDELAYCTRL:MUX.REFCLK[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK8" title="IOCLK:BUF.HCLK8">IOCLK:BUF.HCLK8</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK7" title="IOCLK:BUF.HCLK7">IOCLK:BUF.HCLK7</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.RCLK0" title="IOCLK:BUF.RCLK0">IOCLK:BUF.RCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[3]">IDELAYCTRL:MUX.REFCLK[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK3" title="IOCLK:BUF.HCLK3">IOCLK:BUF.HCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK4" title="IOCLK:BUF.HCLK4">IOCLK:BUF.HCLK4</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:ENABLE.RCLK2" title="IOCLK:ENABLE.RCLK2">IOCLK:ENABLE.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:ENABLE.RCLK3" title="IOCLK:ENABLE.RCLK3">IOCLK:ENABLE.RCLK3</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-BUFIO2:ENABLE" title="BUFIO2:ENABLE">BUFIO2:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[2]">IDELAYCTRL:MUX.REFCLK[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[1]">IDELAYCTRL:MUX.REFCLK[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK8" title="IOCLK:BUF.HCLK8">IOCLK:BUF.HCLK8</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK7" title="IOCLK:BUF.HCLK7">IOCLK:BUF.HCLK7</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[8]">LVDS:LVDSBIAS[8]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[9]">LVDS:LVDSBIAS[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[5]">LVDS:LVDSBIAS[5]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[4]">LVDS:LVDSBIAS[4]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[2]">INTERNAL_VREF:VREF[2]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[0]">DCI:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:CASCADE_FROM_BELOW" title="DCI:CASCADE_FROM_BELOW">DCI:CASCADE_FROM_BELOW</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[0]">DCI:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[1]">DCI:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[4]">DCI:PMASK_TERM_VCC[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[3]">DCI:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:NREF" title="DCI:NREF[1]">DCI:NREF[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:TEST_ENABLE" title="DCI:TEST_ENABLE[1]">DCI:TEST_ENABLE[1]</a></td></tr>
 <tr><td>14</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[7]">IDELAYCTRL:MUX.REFCLK[7]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[6]">IDELAYCTRL:MUX.REFCLK[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:ENABLE.RCLK1" title="IOCLK:ENABLE.RCLK1">IOCLK:ENABLE.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[0]">IOCLK:IOCLK_ENABLE[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[4]">IDELAYCTRL:MUX.REFCLK[4]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK9" title="IOCLK:BUF.HCLK9">IOCLK:BUF.HCLK9</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[7]">IDELAYCTRL:MUX.REFCLK[7]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[6]">IDELAYCTRL:MUX.REFCLK[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:ENABLE.RCLK1" title="IOCLK:ENABLE.RCLK1">IOCLK:ENABLE.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[0]">IOCLK:IOCLK_ENABLE[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[4]">IDELAYCTRL:MUX.REFCLK[4]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK9" title="IOCLK:BUF.HCLK9">IOCLK:BUF.HCLK9</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[2]">LVDS:LVDSBIAS[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[3]">LVDS:LVDSBIAS[3]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:ENABLE" title="DCI:ENABLE">DCI:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:CASCADE_FROM_ABOVE" title="DCI:CASCADE_FROM_ABOVE">DCI:CASCADE_FROM_ABOVE</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:QUIET" title="DCI:QUIET">DCI:QUIET</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:TEST_ENABLE" title="DCI:TEST_ENABLE[0]">DCI:TEST_ENABLE[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[1]">DCI:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[2]">DCI:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:NREF" title="DCI:NREF[0]">DCI:NREF[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:PREF" title="DCI:PREF[2]">DCI:PREF[2]</a></td></tr>
 <tr><td>15</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.RCLK3" title="IOCLK:BUF.RCLK3">IOCLK:BUF.RCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[9]">IDELAYCTRL:MUX.REFCLK[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[8]">IDELAYCTRL:MUX.REFCLK[8]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[1]">IOCLK:IOCLK_ENABLE[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:ENABLE.RCLK0" title="IOCLK:ENABLE.RCLK0">IOCLK:ENABLE.RCLK0</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.RCLK3" title="IOCLK:BUF.RCLK3">IOCLK:BUF.RCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[9]">IDELAYCTRL:MUX.REFCLK[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[8]">IDELAYCTRL:MUX.REFCLK[8]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[1]">IOCLK:IOCLK_ENABLE[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:ENABLE.RCLK0" title="IOCLK:ENABLE.RCLK0">IOCLK:ENABLE.RCLK0</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[1]">LVDS:LVDSBIAS[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[0]">LVDS:LVDSBIAS[0]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[3]">INTERNAL_VREF:VREF[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[4]">INTERNAL_VREF:VREF[4]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[3]">DCI:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[4]">DCI:PMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[0]">DCI:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[4]">DCI:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:PREF" title="DCI:PREF[3]">DCI:PREF[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_BOTCEN-DCI:LVDIV2" title="DCI:LVDIV2[2]">DCI:LVDIV2[2]</a></td></tr>
 </table>
 <div id="bits-xc5v-HCLK_IOI_BOTCEN-BUFIO2:ENABLE"></div>
 <div id="bits-xc5v-HCLK_IOI_BOTCEN-BUFIO3:ENABLE"></div>
+<div id="bits-xc5v-HCLK_IOI_BOTCEN-DCI:CASCADE_FROM_ABOVE"></div>
+<div id="bits-xc5v-HCLK_IOI_BOTCEN-DCI:CASCADE_FROM_BELOW"></div>
+<div id="bits-xc5v-HCLK_IOI_BOTCEN-DCI:ENABLE"></div>
+<div id="bits-xc5v-HCLK_IOI_BOTCEN-DCI:QUIET"></div>
 <div id="bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK0"></div>
 <div id="bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK1"></div>
 <div id="bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:BUF.HCLK2"></div>
@@ -5368,6 +5463,10 @@ <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI_BOTCEN
 <table class="docutils align-default prjcombine-enum">
 <tr><th>BUFIO2:ENABLE</th><th>[0, 18, 13]</th></tr>
 <tr><th>BUFIO3:ENABLE</th><th>[0, 14, 12]</th></tr>
+<tr><th>DCI:CASCADE_FROM_ABOVE</th><th>[0, 47, 14]</th></tr>
+<tr><th>DCI:CASCADE_FROM_BELOW</th><th>[0, 47, 13]</th></tr>
+<tr><th>DCI:ENABLE</th><th>[0, 46, 14]</th></tr>
+<tr><th>DCI:QUIET</th><th>[0, 48, 14]</th></tr>
 <tr><th>IOCLK:BUF.HCLK0</th><th>[0, 16, 12]</th></tr>
 <tr><th>IOCLK:BUF.HCLK1</th><th>[0, 15, 12]</th></tr>
 <tr><th>IOCLK:BUF.HCLK2</th><th>[0, 17, 12]</th></tr>
@@ -5403,51 +5502,92 @@ <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI_BOTCEN
 <tr><td>HCLK8</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>HCLK9</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 </table>
+<div id="bits-xc5v-HCLK_IOI_BOTCEN-DCI:NREF"></div>
+<div id="bits-xc5v-HCLK_IOI_BOTCEN-DCI:TEST_ENABLE"></div>
 <div id="bits-xc5v-HCLK_IOI_BOTCEN-IOCLK:IOCLK_ENABLE"></div>
 <table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:NREF</th><th>[0, 52, 13]</th><th>[0, 52, 14]</th></tr>
+<tr><th>DCI:TEST_ENABLE</th><th>[0, 53, 13]</th><th>[0, 49, 14]</th></tr>
 <tr><th>IOCLK:IOCLK_ENABLE</th><th>[0, 15, 15]</th><th>[0, 15, 14]</th></tr>
 <tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
 </table>
+<div id="bits-xc5v-HCLK_IOI_BOTCEN-LVDS:LVDSBIAS"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>LVDS:LVDSBIAS</th><th>[0, 32, 12]</th><th>[0, 33, 12]</th><th>[0, 33, 13]</th><th>[0, 32, 13]</th><th>[0, 35, 12]</th><th>[0, 34, 12]</th><th>[0, 34, 13]</th><th>[0, 35, 13]</th><th>[0, 35, 14]</th><th>[0, 34, 14]</th><th>[0, 34, 15]</th><th>[0, 35, 15]</th></tr>
+<tr><td>Non-inverted</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_BOTCEN-INTERNAL_VREF:VREF"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>INTERNAL_VREF:VREF</th><th>[0, 39, 15]</th><th>[0, 38, 15]</th><th>[0, 38, 13]</th><th>[0, 38, 12]</th><th>[0, 39, 12]</th></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>750</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>900</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>1080</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>1250</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_BOTCEN-DCI:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc5v-HCLK_IOI_BOTCEN-DCI:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc5v-HCLK_IOI_BOTCEN-DCI:PMASK_TERM_VCC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:NMASK_TERM_SPLIT</th><th>[0, 51, 15]</th><th>[0, 48, 12]</th><th>[0, 49, 12]</th><th>[0, 49, 13]</th><th>[0, 48, 13]</th></tr>
+<tr><th>DCI:PMASK_TERM_SPLIT</th><th>[0, 49, 15]</th><th>[0, 48, 15]</th><th>[0, 47, 12]</th><th>[0, 46, 12]</th><th>[0, 46, 13]</th></tr>
+<tr><th>DCI:PMASK_TERM_VCC</th><th>[0, 50, 13]</th><th>[0, 51, 13]</th><th>[0, 51, 14]</th><th>[0, 50, 14]</th><th>[0, 50, 15]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_BOTCEN-DCI:PREF"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:PREF</th><th>[0, 52, 15]</th><th>[0, 53, 14]</th><th>[0, 50, 12]</th><th>[0, 51, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_BOTCEN-DCI:LVDIV2"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:LVDIV2</th><th>[0, 53, 15]</th><th>[0, 53, 12]</th><th>[0, 52, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
 </section>
 <section id="hclk-ioi-topcen">
 <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI_TOPCEN</span></code><a class="headerlink" href="#hclk-ioi-topcen" title="Link to this heading"></a></h3>
 <table class="docutils align-default prjcombine-tile">
-<tr><th colspan="31">HCLK_IOI_TOPCEN bittile 0</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><th colspan="55">HCLK_IOI_TOPCEN bittile 0</th></tr><tr><th rowspan="2">Row</th><th colspan="54">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th><th>30</th><th>31</th><th>32</th><th>33</th><th>34</th><th>35</th><th>36</th><th>37</th><th>38</th><th>39</th><th>40</th><th>41</th><th>42</th><th>43</th><th>44</th><th>45</th><th>46</th><th>47</th><th>48</th><th>49</th><th>50</th><th>51</th><th>52</th><th>53</th></tr>
 <tr><td>0</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>1</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>2</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>3</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>4</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>5</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>6</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>7</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>8</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>9</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>10</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>11</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>12</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[0]">IDELAYCTRL:MUX.REFCLK[0]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.RCLK1" title="IOCLK:BUF.RCLK1">IOCLK:BUF.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[5]">IDELAYCTRL:MUX.REFCLK[5]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK1" title="IOCLK:BUF.HCLK1">IOCLK:BUF.HCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK0" title="IOCLK:BUF.HCLK0">IOCLK:BUF.HCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK2" title="IOCLK:BUF.HCLK2">IOCLK:BUF.HCLK2</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-BUFIO0:ENABLE" title="BUFIO0:ENABLE">BUFIO0:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.RCLK2" title="IOCLK:BUF.RCLK2">IOCLK:BUF.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK5" title="IOCLK:BUF.HCLK5">IOCLK:BUF.HCLK5</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK6" title="IOCLK:BUF.HCLK6">IOCLK:BUF.HCLK6</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[0]">IDELAYCTRL:MUX.REFCLK[0]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.RCLK1" title="IOCLK:BUF.RCLK1">IOCLK:BUF.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[5]">IDELAYCTRL:MUX.REFCLK[5]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK1" title="IOCLK:BUF.HCLK1">IOCLK:BUF.HCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK0" title="IOCLK:BUF.HCLK0">IOCLK:BUF.HCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK2" title="IOCLK:BUF.HCLK2">IOCLK:BUF.HCLK2</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-BUFIO0:ENABLE" title="BUFIO0:ENABLE">BUFIO0:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.RCLK2" title="IOCLK:BUF.RCLK2">IOCLK:BUF.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK5" title="IOCLK:BUF.HCLK5">IOCLK:BUF.HCLK5</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK6" title="IOCLK:BUF.HCLK6">IOCLK:BUF.HCLK6</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[11]">LVDS:LVDSBIAS[11]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[10]">LVDS:LVDSBIAS[10]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[6]">LVDS:LVDSBIAS[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[7]">LVDS:LVDSBIAS[7]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[1]">INTERNAL_VREF:VREF[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[0]">INTERNAL_VREF:VREF[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[1]">DCI:PMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[2]">DCI:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[3]">DCI:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[2]">DCI:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:PREF" title="DCI:PREF[1]">DCI:PREF[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:PREF" title="DCI:PREF[0]">DCI:PREF[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:LVDIV2" title="DCI:LVDIV2[0]">DCI:LVDIV2[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:LVDIV2" title="DCI:LVDIV2[1]">DCI:LVDIV2[1]</a></td></tr>
 <tr><td>13</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.RCLK0" title="IOCLK:BUF.RCLK0">IOCLK:BUF.RCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[3]">IDELAYCTRL:MUX.REFCLK[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK3" title="IOCLK:BUF.HCLK3">IOCLK:BUF.HCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK4" title="IOCLK:BUF.HCLK4">IOCLK:BUF.HCLK4</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:ENABLE.RCLK2" title="IOCLK:ENABLE.RCLK2">IOCLK:ENABLE.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:ENABLE.RCLK3" title="IOCLK:ENABLE.RCLK3">IOCLK:ENABLE.RCLK3</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-BUFIO1:ENABLE" title="BUFIO1:ENABLE">BUFIO1:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[2]">IDELAYCTRL:MUX.REFCLK[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[1]">IDELAYCTRL:MUX.REFCLK[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK8" title="IOCLK:BUF.HCLK8">IOCLK:BUF.HCLK8</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK7" title="IOCLK:BUF.HCLK7">IOCLK:BUF.HCLK7</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.RCLK0" title="IOCLK:BUF.RCLK0">IOCLK:BUF.RCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[3]">IDELAYCTRL:MUX.REFCLK[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK3" title="IOCLK:BUF.HCLK3">IOCLK:BUF.HCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK4" title="IOCLK:BUF.HCLK4">IOCLK:BUF.HCLK4</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:ENABLE.RCLK2" title="IOCLK:ENABLE.RCLK2">IOCLK:ENABLE.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:ENABLE.RCLK3" title="IOCLK:ENABLE.RCLK3">IOCLK:ENABLE.RCLK3</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-BUFIO1:ENABLE" title="BUFIO1:ENABLE">BUFIO1:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[2]">IDELAYCTRL:MUX.REFCLK[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[1]">IDELAYCTRL:MUX.REFCLK[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK8" title="IOCLK:BUF.HCLK8">IOCLK:BUF.HCLK8</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK7" title="IOCLK:BUF.HCLK7">IOCLK:BUF.HCLK7</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[8]">LVDS:LVDSBIAS[8]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[9]">LVDS:LVDSBIAS[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[5]">LVDS:LVDSBIAS[5]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[4]">LVDS:LVDSBIAS[4]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[2]">INTERNAL_VREF:VREF[2]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[0]">DCI:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:CASCADE_FROM_BELOW" title="DCI:CASCADE_FROM_BELOW">DCI:CASCADE_FROM_BELOW</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[0]">DCI:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[1]">DCI:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[4]">DCI:PMASK_TERM_VCC[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[3]">DCI:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:NREF" title="DCI:NREF[1]">DCI:NREF[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:TEST_ENABLE" title="DCI:TEST_ENABLE[1]">DCI:TEST_ENABLE[1]</a></td></tr>
 <tr><td>14</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[7]">IDELAYCTRL:MUX.REFCLK[7]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[6]">IDELAYCTRL:MUX.REFCLK[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:ENABLE.RCLK1" title="IOCLK:ENABLE.RCLK1">IOCLK:ENABLE.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[0]">IOCLK:IOCLK_ENABLE[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[4]">IDELAYCTRL:MUX.REFCLK[4]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK9" title="IOCLK:BUF.HCLK9">IOCLK:BUF.HCLK9</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[7]">IDELAYCTRL:MUX.REFCLK[7]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[6]">IDELAYCTRL:MUX.REFCLK[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:ENABLE.RCLK1" title="IOCLK:ENABLE.RCLK1">IOCLK:ENABLE.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[0]">IOCLK:IOCLK_ENABLE[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[4]">IDELAYCTRL:MUX.REFCLK[4]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK9" title="IOCLK:BUF.HCLK9">IOCLK:BUF.HCLK9</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[2]">LVDS:LVDSBIAS[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[3]">LVDS:LVDSBIAS[3]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:ENABLE" title="DCI:ENABLE">DCI:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:CASCADE_FROM_ABOVE" title="DCI:CASCADE_FROM_ABOVE">DCI:CASCADE_FROM_ABOVE</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:QUIET" title="DCI:QUIET">DCI:QUIET</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:TEST_ENABLE" title="DCI:TEST_ENABLE[0]">DCI:TEST_ENABLE[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[1]">DCI:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[2]">DCI:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:NREF" title="DCI:NREF[0]">DCI:NREF[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:PREF" title="DCI:PREF[2]">DCI:PREF[2]</a></td></tr>
 <tr><td>15</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.RCLK3" title="IOCLK:BUF.RCLK3">IOCLK:BUF.RCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[9]">IDELAYCTRL:MUX.REFCLK[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[8]">IDELAYCTRL:MUX.REFCLK[8]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[1]">IOCLK:IOCLK_ENABLE[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:ENABLE.RCLK0" title="IOCLK:ENABLE.RCLK0">IOCLK:ENABLE.RCLK0</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-SYSMON:ENABLE" title="SYSMON:ENABLE">SYSMON:ENABLE</a></td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.RCLK3" title="IOCLK:BUF.RCLK3">IOCLK:BUF.RCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[9]">IDELAYCTRL:MUX.REFCLK[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[8]">IDELAYCTRL:MUX.REFCLK[8]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[1]">IOCLK:IOCLK_ENABLE[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:ENABLE.RCLK0" title="IOCLK:ENABLE.RCLK0">IOCLK:ENABLE.RCLK0</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-SYSMON:ENABLE" title="SYSMON:ENABLE">SYSMON:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[1]">LVDS:LVDSBIAS[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[0]">LVDS:LVDSBIAS[0]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[3]">INTERNAL_VREF:VREF[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[4]">INTERNAL_VREF:VREF[4]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[3]">DCI:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[4]">DCI:PMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[0]">DCI:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[4]">DCI:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:PREF" title="DCI:PREF[3]">DCI:PREF[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_TOPCEN-DCI:LVDIV2" title="DCI:LVDIV2[2]">DCI:LVDIV2[2]</a></td></tr>
 </table>
 <div id="bits-xc5v-HCLK_IOI_TOPCEN-BUFIO0:ENABLE"></div>
 <div id="bits-xc5v-HCLK_IOI_TOPCEN-BUFIO1:ENABLE"></div>
+<div id="bits-xc5v-HCLK_IOI_TOPCEN-DCI:CASCADE_FROM_ABOVE"></div>
+<div id="bits-xc5v-HCLK_IOI_TOPCEN-DCI:CASCADE_FROM_BELOW"></div>
+<div id="bits-xc5v-HCLK_IOI_TOPCEN-DCI:ENABLE"></div>
+<div id="bits-xc5v-HCLK_IOI_TOPCEN-DCI:QUIET"></div>
 <div id="bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK0"></div>
 <div id="bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK1"></div>
 <div id="bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:BUF.HCLK2"></div>
@@ -5470,6 +5610,10 @@ <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI_TOPCEN
 <table class="docutils align-default prjcombine-enum">
 <tr><th>BUFIO0:ENABLE</th><th>[0, 19, 12]</th></tr>
 <tr><th>BUFIO1:ENABLE</th><th>[0, 19, 13]</th></tr>
+<tr><th>DCI:CASCADE_FROM_ABOVE</th><th>[0, 47, 14]</th></tr>
+<tr><th>DCI:CASCADE_FROM_BELOW</th><th>[0, 47, 13]</th></tr>
+<tr><th>DCI:ENABLE</th><th>[0, 46, 14]</th></tr>
+<tr><th>DCI:QUIET</th><th>[0, 48, 14]</th></tr>
 <tr><th>IOCLK:BUF.HCLK0</th><th>[0, 16, 12]</th></tr>
 <tr><th>IOCLK:BUF.HCLK1</th><th>[0, 15, 12]</th></tr>
 <tr><th>IOCLK:BUF.HCLK2</th><th>[0, 17, 12]</th></tr>
@@ -5506,51 +5650,92 @@ <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI_TOPCEN
 <tr><td>HCLK8</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>HCLK9</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 </table>
+<div id="bits-xc5v-HCLK_IOI_TOPCEN-DCI:NREF"></div>
+<div id="bits-xc5v-HCLK_IOI_TOPCEN-DCI:TEST_ENABLE"></div>
 <div id="bits-xc5v-HCLK_IOI_TOPCEN-IOCLK:IOCLK_ENABLE"></div>
 <table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:NREF</th><th>[0, 52, 13]</th><th>[0, 52, 14]</th></tr>
+<tr><th>DCI:TEST_ENABLE</th><th>[0, 53, 13]</th><th>[0, 49, 14]</th></tr>
 <tr><th>IOCLK:IOCLK_ENABLE</th><th>[0, 15, 15]</th><th>[0, 15, 14]</th></tr>
 <tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
 </table>
+<div id="bits-xc5v-HCLK_IOI_TOPCEN-LVDS:LVDSBIAS"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>LVDS:LVDSBIAS</th><th>[0, 32, 12]</th><th>[0, 33, 12]</th><th>[0, 33, 13]</th><th>[0, 32, 13]</th><th>[0, 35, 12]</th><th>[0, 34, 12]</th><th>[0, 34, 13]</th><th>[0, 35, 13]</th><th>[0, 35, 14]</th><th>[0, 34, 14]</th><th>[0, 34, 15]</th><th>[0, 35, 15]</th></tr>
+<tr><td>Non-inverted</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_TOPCEN-INTERNAL_VREF:VREF"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>INTERNAL_VREF:VREF</th><th>[0, 39, 15]</th><th>[0, 38, 15]</th><th>[0, 38, 13]</th><th>[0, 38, 12]</th><th>[0, 39, 12]</th></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>750</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>900</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>1080</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>1250</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_TOPCEN-DCI:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc5v-HCLK_IOI_TOPCEN-DCI:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc5v-HCLK_IOI_TOPCEN-DCI:PMASK_TERM_VCC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:NMASK_TERM_SPLIT</th><th>[0, 51, 15]</th><th>[0, 48, 12]</th><th>[0, 49, 12]</th><th>[0, 49, 13]</th><th>[0, 48, 13]</th></tr>
+<tr><th>DCI:PMASK_TERM_SPLIT</th><th>[0, 49, 15]</th><th>[0, 48, 15]</th><th>[0, 47, 12]</th><th>[0, 46, 12]</th><th>[0, 46, 13]</th></tr>
+<tr><th>DCI:PMASK_TERM_VCC</th><th>[0, 50, 13]</th><th>[0, 51, 13]</th><th>[0, 51, 14]</th><th>[0, 50, 14]</th><th>[0, 50, 15]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_TOPCEN-DCI:PREF"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:PREF</th><th>[0, 52, 15]</th><th>[0, 53, 14]</th><th>[0, 50, 12]</th><th>[0, 51, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_TOPCEN-DCI:LVDIV2"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:LVDIV2</th><th>[0, 53, 15]</th><th>[0, 53, 12]</th><th>[0, 52, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
 </section>
 <section id="hclk-ioi-cmt">
 <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI_CMT</span></code><a class="headerlink" href="#hclk-ioi-cmt" title="Link to this heading"></a></h3>
 <table class="docutils align-default prjcombine-tile">
-<tr><th colspan="31">HCLK_IOI_CMT bittile 0</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><th colspan="55">HCLK_IOI_CMT bittile 0</th></tr><tr><th rowspan="2">Row</th><th colspan="54">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th><th>30</th><th>31</th><th>32</th><th>33</th><th>34</th><th>35</th><th>36</th><th>37</th><th>38</th><th>39</th><th>40</th><th>41</th><th>42</th><th>43</th><th>44</th><th>45</th><th>46</th><th>47</th><th>48</th><th>49</th><th>50</th><th>51</th><th>52</th><th>53</th></tr>
 <tr><td>0</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>1</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>2</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>3</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>4</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>5</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>6</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>7</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>8</td>
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+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>9</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>10</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>11</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>12</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[0]">IDELAYCTRL:MUX.REFCLK[0]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.RCLK1" title="IOCLK:BUF.RCLK1">IOCLK:BUF.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[5]">IDELAYCTRL:MUX.REFCLK[5]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK1" title="IOCLK:BUF.HCLK1">IOCLK:BUF.HCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK0" title="IOCLK:BUF.HCLK0">IOCLK:BUF.HCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK2" title="IOCLK:BUF.HCLK2">IOCLK:BUF.HCLK2</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-BUFIO0:ENABLE" title="BUFIO0:ENABLE">BUFIO0:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.RCLK2" title="IOCLK:BUF.RCLK2">IOCLK:BUF.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK5" title="IOCLK:BUF.HCLK5">IOCLK:BUF.HCLK5</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK6" title="IOCLK:BUF.HCLK6">IOCLK:BUF.HCLK6</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[0]">IDELAYCTRL:MUX.REFCLK[0]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.RCLK1" title="IOCLK:BUF.RCLK1">IOCLK:BUF.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[5]">IDELAYCTRL:MUX.REFCLK[5]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK1" title="IOCLK:BUF.HCLK1">IOCLK:BUF.HCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK0" title="IOCLK:BUF.HCLK0">IOCLK:BUF.HCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK2" title="IOCLK:BUF.HCLK2">IOCLK:BUF.HCLK2</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-BUFIO0:ENABLE" title="BUFIO0:ENABLE">BUFIO0:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.RCLK2" title="IOCLK:BUF.RCLK2">IOCLK:BUF.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK5" title="IOCLK:BUF.HCLK5">IOCLK:BUF.HCLK5</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK6" title="IOCLK:BUF.HCLK6">IOCLK:BUF.HCLK6</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[11]">LVDS:LVDSBIAS[11]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[10]">LVDS:LVDSBIAS[10]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[6]">LVDS:LVDSBIAS[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[7]">LVDS:LVDSBIAS[7]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[1]">INTERNAL_VREF:VREF[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[0]">INTERNAL_VREF:VREF[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[1]">DCI:PMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[2]">DCI:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[3]">DCI:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[2]">DCI:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:PREF" title="DCI:PREF[1]">DCI:PREF[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:PREF" title="DCI:PREF[0]">DCI:PREF[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:LVDIV2" title="DCI:LVDIV2[0]">DCI:LVDIV2[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:LVDIV2" title="DCI:LVDIV2[1]">DCI:LVDIV2[1]</a></td></tr>
 <tr><td>13</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.RCLK0" title="IOCLK:BUF.RCLK0">IOCLK:BUF.RCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[3]">IDELAYCTRL:MUX.REFCLK[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK3" title="IOCLK:BUF.HCLK3">IOCLK:BUF.HCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK4" title="IOCLK:BUF.HCLK4">IOCLK:BUF.HCLK4</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:ENABLE.RCLK2" title="IOCLK:ENABLE.RCLK2">IOCLK:ENABLE.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:ENABLE.RCLK3" title="IOCLK:ENABLE.RCLK3">IOCLK:ENABLE.RCLK3</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-BUFIO1:ENABLE" title="BUFIO1:ENABLE">BUFIO1:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[2]">IDELAYCTRL:MUX.REFCLK[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[1]">IDELAYCTRL:MUX.REFCLK[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK8" title="IOCLK:BUF.HCLK8">IOCLK:BUF.HCLK8</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK7" title="IOCLK:BUF.HCLK7">IOCLK:BUF.HCLK7</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.RCLK0" title="IOCLK:BUF.RCLK0">IOCLK:BUF.RCLK0</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[3]">IDELAYCTRL:MUX.REFCLK[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK3" title="IOCLK:BUF.HCLK3">IOCLK:BUF.HCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK4" title="IOCLK:BUF.HCLK4">IOCLK:BUF.HCLK4</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:ENABLE.RCLK2" title="IOCLK:ENABLE.RCLK2">IOCLK:ENABLE.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:ENABLE.RCLK3" title="IOCLK:ENABLE.RCLK3">IOCLK:ENABLE.RCLK3</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-BUFIO1:ENABLE" title="BUFIO1:ENABLE">BUFIO1:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[2]">IDELAYCTRL:MUX.REFCLK[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[1]">IDELAYCTRL:MUX.REFCLK[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK8" title="IOCLK:BUF.HCLK8">IOCLK:BUF.HCLK8</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK7" title="IOCLK:BUF.HCLK7">IOCLK:BUF.HCLK7</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[8]">LVDS:LVDSBIAS[8]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[9]">LVDS:LVDSBIAS[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[5]">LVDS:LVDSBIAS[5]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[4]">LVDS:LVDSBIAS[4]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[2]">INTERNAL_VREF:VREF[2]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[0]">DCI:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:CASCADE_FROM_BELOW" title="DCI:CASCADE_FROM_BELOW">DCI:CASCADE_FROM_BELOW</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[0]">DCI:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[1]">DCI:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[4]">DCI:PMASK_TERM_VCC[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[3]">DCI:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:NREF" title="DCI:NREF[1]">DCI:NREF[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:TEST_ENABLE" title="DCI:TEST_ENABLE[1]">DCI:TEST_ENABLE[1]</a></td></tr>
 <tr><td>14</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[7]">IDELAYCTRL:MUX.REFCLK[7]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[6]">IDELAYCTRL:MUX.REFCLK[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:ENABLE.RCLK1" title="IOCLK:ENABLE.RCLK1">IOCLK:ENABLE.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[0]">IOCLK:IOCLK_ENABLE[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[4]">IDELAYCTRL:MUX.REFCLK[4]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK9" title="IOCLK:BUF.HCLK9">IOCLK:BUF.HCLK9</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[7]">IDELAYCTRL:MUX.REFCLK[7]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[6]">IDELAYCTRL:MUX.REFCLK[6]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:ENABLE.RCLK1" title="IOCLK:ENABLE.RCLK1">IOCLK:ENABLE.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[0]">IOCLK:IOCLK_ENABLE[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[4]">IDELAYCTRL:MUX.REFCLK[4]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK9" title="IOCLK:BUF.HCLK9">IOCLK:BUF.HCLK9</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[2]">LVDS:LVDSBIAS[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[3]">LVDS:LVDSBIAS[3]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:ENABLE" title="DCI:ENABLE">DCI:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:CASCADE_FROM_ABOVE" title="DCI:CASCADE_FROM_ABOVE">DCI:CASCADE_FROM_ABOVE</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:QUIET" title="DCI:QUIET">DCI:QUIET</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:TEST_ENABLE" title="DCI:TEST_ENABLE[0]">DCI:TEST_ENABLE[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[1]">DCI:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[2]">DCI:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:NREF" title="DCI:NREF[0]">DCI:NREF[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:PREF" title="DCI:PREF[2]">DCI:PREF[2]</a></td></tr>
 <tr><td>15</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.RCLK3" title="IOCLK:BUF.RCLK3">IOCLK:BUF.RCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[9]">IDELAYCTRL:MUX.REFCLK[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[8]">IDELAYCTRL:MUX.REFCLK[8]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[1]">IOCLK:IOCLK_ENABLE[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:ENABLE.RCLK0" title="IOCLK:ENABLE.RCLK0">IOCLK:ENABLE.RCLK0</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.RCLK3" title="IOCLK:BUF.RCLK3">IOCLK:BUF.RCLK3</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[9]">IDELAYCTRL:MUX.REFCLK[9]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[8]">IDELAYCTRL:MUX.REFCLK[8]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[1]">IOCLK:IOCLK_ENABLE[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-IOCLK:ENABLE.RCLK0" title="IOCLK:ENABLE.RCLK0">IOCLK:ENABLE.RCLK0</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[1]">LVDS:LVDSBIAS[1]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[0]">LVDS:LVDSBIAS[0]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[3]">INTERNAL_VREF:VREF[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[4]">INTERNAL_VREF:VREF[4]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[3]">DCI:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[4]">DCI:PMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[0]">DCI:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[4]">DCI:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:PREF" title="DCI:PREF[3]">DCI:PREF[3]</a></td><td><a href="#bits-xc5v-HCLK_IOI_CMT-DCI:LVDIV2" title="DCI:LVDIV2[2]">DCI:LVDIV2[2]</a></td></tr>
 </table>
 <div id="bits-xc5v-HCLK_IOI_CMT-BUFIO0:ENABLE"></div>
 <div id="bits-xc5v-HCLK_IOI_CMT-BUFIO1:ENABLE"></div>
+<div id="bits-xc5v-HCLK_IOI_CMT-DCI:CASCADE_FROM_ABOVE"></div>
+<div id="bits-xc5v-HCLK_IOI_CMT-DCI:CASCADE_FROM_BELOW"></div>
+<div id="bits-xc5v-HCLK_IOI_CMT-DCI:ENABLE"></div>
+<div id="bits-xc5v-HCLK_IOI_CMT-DCI:QUIET"></div>
 <div id="bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK0"></div>
 <div id="bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK1"></div>
 <div id="bits-xc5v-HCLK_IOI_CMT-IOCLK:BUF.HCLK2"></div>
@@ -5572,6 +5757,10 @@ <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI_CMT</s
 <table class="docutils align-default prjcombine-enum">
 <tr><th>BUFIO0:ENABLE</th><th>[0, 19, 12]</th></tr>
 <tr><th>BUFIO1:ENABLE</th><th>[0, 19, 13]</th></tr>
+<tr><th>DCI:CASCADE_FROM_ABOVE</th><th>[0, 47, 14]</th></tr>
+<tr><th>DCI:CASCADE_FROM_BELOW</th><th>[0, 47, 13]</th></tr>
+<tr><th>DCI:ENABLE</th><th>[0, 46, 14]</th></tr>
+<tr><th>DCI:QUIET</th><th>[0, 48, 14]</th></tr>
 <tr><th>IOCLK:BUF.HCLK0</th><th>[0, 16, 12]</th></tr>
 <tr><th>IOCLK:BUF.HCLK1</th><th>[0, 15, 12]</th></tr>
 <tr><th>IOCLK:BUF.HCLK2</th><th>[0, 17, 12]</th></tr>
@@ -5607,51 +5796,92 @@ <h3><code class="docutils literal notranslate"><span class="pre">HCLK_IOI_CMT</s
 <tr><td>HCLK8</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>HCLK9</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 </table>
+<div id="bits-xc5v-HCLK_IOI_CMT-DCI:NREF"></div>
+<div id="bits-xc5v-HCLK_IOI_CMT-DCI:TEST_ENABLE"></div>
 <div id="bits-xc5v-HCLK_IOI_CMT-IOCLK:IOCLK_ENABLE"></div>
 <table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:NREF</th><th>[0, 52, 13]</th><th>[0, 52, 14]</th></tr>
+<tr><th>DCI:TEST_ENABLE</th><th>[0, 53, 13]</th><th>[0, 49, 14]</th></tr>
 <tr><th>IOCLK:IOCLK_ENABLE</th><th>[0, 15, 15]</th><th>[0, 15, 14]</th></tr>
 <tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
 </table>
+<div id="bits-xc5v-HCLK_IOI_CMT-LVDS:LVDSBIAS"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>LVDS:LVDSBIAS</th><th>[0, 32, 12]</th><th>[0, 33, 12]</th><th>[0, 33, 13]</th><th>[0, 32, 13]</th><th>[0, 35, 12]</th><th>[0, 34, 12]</th><th>[0, 34, 13]</th><th>[0, 35, 13]</th><th>[0, 35, 14]</th><th>[0, 34, 14]</th><th>[0, 34, 15]</th><th>[0, 35, 15]</th></tr>
+<tr><td>Non-inverted</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_CMT-INTERNAL_VREF:VREF"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>INTERNAL_VREF:VREF</th><th>[0, 39, 15]</th><th>[0, 38, 15]</th><th>[0, 38, 13]</th><th>[0, 38, 12]</th><th>[0, 39, 12]</th></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>750</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>900</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>1080</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>1250</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_CMT-DCI:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc5v-HCLK_IOI_CMT-DCI:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc5v-HCLK_IOI_CMT-DCI:PMASK_TERM_VCC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:NMASK_TERM_SPLIT</th><th>[0, 51, 15]</th><th>[0, 48, 12]</th><th>[0, 49, 12]</th><th>[0, 49, 13]</th><th>[0, 48, 13]</th></tr>
+<tr><th>DCI:PMASK_TERM_SPLIT</th><th>[0, 49, 15]</th><th>[0, 48, 15]</th><th>[0, 47, 12]</th><th>[0, 46, 12]</th><th>[0, 46, 13]</th></tr>
+<tr><th>DCI:PMASK_TERM_VCC</th><th>[0, 50, 13]</th><th>[0, 51, 13]</th><th>[0, 51, 14]</th><th>[0, 50, 14]</th><th>[0, 50, 15]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_CMT-DCI:PREF"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:PREF</th><th>[0, 52, 15]</th><th>[0, 53, 14]</th><th>[0, 50, 12]</th><th>[0, 51, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_IOI_CMT-DCI:LVDIV2"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:LVDIV2</th><th>[0, 53, 15]</th><th>[0, 53, 12]</th><th>[0, 52, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
 </section>
 <section id="hclk-cmt-ioi">
 <h3><code class="docutils literal notranslate"><span class="pre">HCLK_CMT_IOI</span></code><a class="headerlink" href="#hclk-cmt-ioi" title="Link to this heading"></a></h3>
 <table class="docutils align-default prjcombine-tile">
-<tr><th colspan="31">HCLK_CMT_IOI bittile 0</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><th colspan="55">HCLK_CMT_IOI bittile 0</th></tr><tr><th rowspan="2">Row</th><th colspan="54">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th><th>30</th><th>31</th><th>32</th><th>33</th><th>34</th><th>35</th><th>36</th><th>37</th><th>38</th><th>39</th><th>40</th><th>41</th><th>42</th><th>43</th><th>44</th><th>45</th><th>46</th><th>47</th><th>48</th><th>49</th><th>50</th><th>51</th><th>52</th><th>53</th></tr>
 <tr><td>0</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>1</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>2</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>3</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>4</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>5</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>6</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>7</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>8</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>9</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>10</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>11</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
 <tr><td>12</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[0]">IDELAYCTRL:MUX.REFCLK[0]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.RCLK1" title="IOCLK:BUF.RCLK1">IOCLK:BUF.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[5]">IDELAYCTRL:MUX.REFCLK[5]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-BUFIO3:ENABLE" title="BUFIO3:ENABLE">BUFIO3:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK1" title="IOCLK:BUF.HCLK1">IOCLK:BUF.HCLK1</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK0" title="IOCLK:BUF.HCLK0">IOCLK:BUF.HCLK0</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK2" title="IOCLK:BUF.HCLK2">IOCLK:BUF.HCLK2</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.RCLK2" title="IOCLK:BUF.RCLK2">IOCLK:BUF.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK5" title="IOCLK:BUF.HCLK5">IOCLK:BUF.HCLK5</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK6" title="IOCLK:BUF.HCLK6">IOCLK:BUF.HCLK6</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[0]">IDELAYCTRL:MUX.REFCLK[0]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.RCLK1" title="IOCLK:BUF.RCLK1">IOCLK:BUF.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[5]">IDELAYCTRL:MUX.REFCLK[5]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-BUFIO3:ENABLE" title="BUFIO3:ENABLE">BUFIO3:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK1" title="IOCLK:BUF.HCLK1">IOCLK:BUF.HCLK1</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK0" title="IOCLK:BUF.HCLK0">IOCLK:BUF.HCLK0</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK2" title="IOCLK:BUF.HCLK2">IOCLK:BUF.HCLK2</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.RCLK2" title="IOCLK:BUF.RCLK2">IOCLK:BUF.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK5" title="IOCLK:BUF.HCLK5">IOCLK:BUF.HCLK5</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK6" title="IOCLK:BUF.HCLK6">IOCLK:BUF.HCLK6</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[11]">LVDS:LVDSBIAS[11]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[10]">LVDS:LVDSBIAS[10]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[6]">LVDS:LVDSBIAS[6]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[7]">LVDS:LVDSBIAS[7]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[1]">INTERNAL_VREF:VREF[1]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[0]">INTERNAL_VREF:VREF[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[1]">DCI:PMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[2]">DCI:PMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[3]">DCI:NMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[2]">DCI:NMASK_TERM_SPLIT[2]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:PREF" title="DCI:PREF[1]">DCI:PREF[1]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:PREF" title="DCI:PREF[0]">DCI:PREF[0]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:LVDIV2" title="DCI:LVDIV2[0]">DCI:LVDIV2[0]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:LVDIV2" title="DCI:LVDIV2[1]">DCI:LVDIV2[1]</a></td></tr>
 <tr><td>13</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.RCLK0" title="IOCLK:BUF.RCLK0">IOCLK:BUF.RCLK0</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[3]">IDELAYCTRL:MUX.REFCLK[3]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK3" title="IOCLK:BUF.HCLK3">IOCLK:BUF.HCLK3</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK4" title="IOCLK:BUF.HCLK4">IOCLK:BUF.HCLK4</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:ENABLE.RCLK2" title="IOCLK:ENABLE.RCLK2">IOCLK:ENABLE.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:ENABLE.RCLK3" title="IOCLK:ENABLE.RCLK3">IOCLK:ENABLE.RCLK3</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-BUFIO2:ENABLE" title="BUFIO2:ENABLE">BUFIO2:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[2]">IDELAYCTRL:MUX.REFCLK[2]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[1]">IDELAYCTRL:MUX.REFCLK[1]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK8" title="IOCLK:BUF.HCLK8">IOCLK:BUF.HCLK8</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK7" title="IOCLK:BUF.HCLK7">IOCLK:BUF.HCLK7</a></td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.RCLK0" title="IOCLK:BUF.RCLK0">IOCLK:BUF.RCLK0</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[3]">IDELAYCTRL:MUX.REFCLK[3]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK3" title="IOCLK:BUF.HCLK3">IOCLK:BUF.HCLK3</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK4" title="IOCLK:BUF.HCLK4">IOCLK:BUF.HCLK4</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:ENABLE.RCLK2" title="IOCLK:ENABLE.RCLK2">IOCLK:ENABLE.RCLK2</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:ENABLE.RCLK3" title="IOCLK:ENABLE.RCLK3">IOCLK:ENABLE.RCLK3</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-BUFIO2:ENABLE" title="BUFIO2:ENABLE">BUFIO2:ENABLE</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[2]">IDELAYCTRL:MUX.REFCLK[2]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[1]">IDELAYCTRL:MUX.REFCLK[1]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK8" title="IOCLK:BUF.HCLK8">IOCLK:BUF.HCLK8</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK7" title="IOCLK:BUF.HCLK7">IOCLK:BUF.HCLK7</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[8]">LVDS:LVDSBIAS[8]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[9]">LVDS:LVDSBIAS[9]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[5]">LVDS:LVDSBIAS[5]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[4]">LVDS:LVDSBIAS[4]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[2]">INTERNAL_VREF:VREF[2]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[0]">DCI:PMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:CASCADE_FROM_BELOW" title="DCI:CASCADE_FROM_BELOW">DCI:CASCADE_FROM_BELOW</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[0]">DCI:NMASK_TERM_SPLIT[0]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[1]">DCI:NMASK_TERM_SPLIT[1]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[4]">DCI:PMASK_TERM_VCC[4]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[3]">DCI:PMASK_TERM_VCC[3]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:NREF" title="DCI:NREF[1]">DCI:NREF[1]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:TEST_ENABLE" title="DCI:TEST_ENABLE[1]">DCI:TEST_ENABLE[1]</a></td></tr>
 <tr><td>14</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[7]">IDELAYCTRL:MUX.REFCLK[7]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[6]">IDELAYCTRL:MUX.REFCLK[6]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:ENABLE.RCLK1" title="IOCLK:ENABLE.RCLK1">IOCLK:ENABLE.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[0]">IOCLK:IOCLK_ENABLE[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[4]">IDELAYCTRL:MUX.REFCLK[4]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK9" title="IOCLK:BUF.HCLK9">IOCLK:BUF.HCLK9</a></td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[7]">IDELAYCTRL:MUX.REFCLK[7]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[6]">IDELAYCTRL:MUX.REFCLK[6]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:ENABLE.RCLK1" title="IOCLK:ENABLE.RCLK1">IOCLK:ENABLE.RCLK1</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[0]">IOCLK:IOCLK_ENABLE[0]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[4]">IDELAYCTRL:MUX.REFCLK[4]</a></td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK9" title="IOCLK:BUF.HCLK9">IOCLK:BUF.HCLK9</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[2]">LVDS:LVDSBIAS[2]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[3]">LVDS:LVDSBIAS[3]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:ENABLE" title="DCI:ENABLE">DCI:ENABLE</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:CASCADE_FROM_ABOVE" title="DCI:CASCADE_FROM_ABOVE">DCI:CASCADE_FROM_ABOVE</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:QUIET" title="DCI:QUIET">DCI:QUIET</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:TEST_ENABLE" title="DCI:TEST_ENABLE[0]">DCI:TEST_ENABLE[0]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[1]">DCI:PMASK_TERM_VCC[1]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[2]">DCI:PMASK_TERM_VCC[2]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:NREF" title="DCI:NREF[0]">DCI:NREF[0]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:PREF" title="DCI:PREF[2]">DCI:PREF[2]</a></td></tr>
 <tr><td>15</td>
-<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.RCLK3" title="IOCLK:BUF.RCLK3">IOCLK:BUF.RCLK3</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[9]">IDELAYCTRL:MUX.REFCLK[9]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[8]">IDELAYCTRL:MUX.REFCLK[8]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[1]">IOCLK:IOCLK_ENABLE[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:ENABLE.RCLK0" title="IOCLK:ENABLE.RCLK0">IOCLK:ENABLE.RCLK0</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.RCLK3" title="IOCLK:BUF.RCLK3">IOCLK:BUF.RCLK3</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[9]">IDELAYCTRL:MUX.REFCLK[9]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IDELAYCTRL:MUX.REFCLK" title="IDELAYCTRL:MUX.REFCLK[8]">IDELAYCTRL:MUX.REFCLK[8]</a></td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:IOCLK_ENABLE" title="IOCLK:IOCLK_ENABLE[1]">IOCLK:IOCLK_ENABLE[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-IOCLK:ENABLE.RCLK0" title="IOCLK:ENABLE.RCLK0">IOCLK:ENABLE.RCLK0</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[1]">LVDS:LVDSBIAS[1]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-LVDS:LVDSBIAS" title="LVDS:LVDSBIAS[0]">LVDS:LVDSBIAS[0]</a></td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[3]">INTERNAL_VREF:VREF[3]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-INTERNAL_VREF:VREF" title="INTERNAL_VREF:VREF[4]">INTERNAL_VREF:VREF[4]</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[3]">DCI:PMASK_TERM_SPLIT[3]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:PMASK_TERM_SPLIT" title="DCI:PMASK_TERM_SPLIT[4]">DCI:PMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:PMASK_TERM_VCC" title="DCI:PMASK_TERM_VCC[0]">DCI:PMASK_TERM_VCC[0]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:NMASK_TERM_SPLIT" title="DCI:NMASK_TERM_SPLIT[4]">DCI:NMASK_TERM_SPLIT[4]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:PREF" title="DCI:PREF[3]">DCI:PREF[3]</a></td><td><a href="#bits-xc5v-HCLK_CMT_IOI-DCI:LVDIV2" title="DCI:LVDIV2[2]">DCI:LVDIV2[2]</a></td></tr>
 </table>
 <div id="bits-xc5v-HCLK_CMT_IOI-BUFIO2:ENABLE"></div>
 <div id="bits-xc5v-HCLK_CMT_IOI-BUFIO3:ENABLE"></div>
+<div id="bits-xc5v-HCLK_CMT_IOI-DCI:CASCADE_FROM_ABOVE"></div>
+<div id="bits-xc5v-HCLK_CMT_IOI-DCI:CASCADE_FROM_BELOW"></div>
+<div id="bits-xc5v-HCLK_CMT_IOI-DCI:ENABLE"></div>
+<div id="bits-xc5v-HCLK_CMT_IOI-DCI:QUIET"></div>
 <div id="bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK0"></div>
 <div id="bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK1"></div>
 <div id="bits-xc5v-HCLK_CMT_IOI-IOCLK:BUF.HCLK2"></div>
@@ -5673,6 +5903,10 @@ <h3><code class="docutils literal notranslate"><span class="pre">HCLK_CMT_IOI</s
 <table class="docutils align-default prjcombine-enum">
 <tr><th>BUFIO2:ENABLE</th><th>[0, 18, 13]</th></tr>
 <tr><th>BUFIO3:ENABLE</th><th>[0, 14, 12]</th></tr>
+<tr><th>DCI:CASCADE_FROM_ABOVE</th><th>[0, 47, 14]</th></tr>
+<tr><th>DCI:CASCADE_FROM_BELOW</th><th>[0, 47, 13]</th></tr>
+<tr><th>DCI:ENABLE</th><th>[0, 46, 14]</th></tr>
+<tr><th>DCI:QUIET</th><th>[0, 48, 14]</th></tr>
 <tr><th>IOCLK:BUF.HCLK0</th><th>[0, 16, 12]</th></tr>
 <tr><th>IOCLK:BUF.HCLK1</th><th>[0, 15, 12]</th></tr>
 <tr><th>IOCLK:BUF.HCLK2</th><th>[0, 17, 12]</th></tr>
@@ -5708,11 +5942,48 @@ <h3><code class="docutils literal notranslate"><span class="pre">HCLK_CMT_IOI</s
 <tr><td>HCLK8</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>HCLK9</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 </table>
+<div id="bits-xc5v-HCLK_CMT_IOI-DCI:NREF"></div>
+<div id="bits-xc5v-HCLK_CMT_IOI-DCI:TEST_ENABLE"></div>
 <div id="bits-xc5v-HCLK_CMT_IOI-IOCLK:IOCLK_ENABLE"></div>
 <table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:NREF</th><th>[0, 52, 13]</th><th>[0, 52, 14]</th></tr>
+<tr><th>DCI:TEST_ENABLE</th><th>[0, 53, 13]</th><th>[0, 49, 14]</th></tr>
 <tr><th>IOCLK:IOCLK_ENABLE</th><th>[0, 15, 15]</th><th>[0, 15, 14]</th></tr>
 <tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
 </table>
+<div id="bits-xc5v-HCLK_CMT_IOI-LVDS:LVDSBIAS"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>LVDS:LVDSBIAS</th><th>[0, 32, 12]</th><th>[0, 33, 12]</th><th>[0, 33, 13]</th><th>[0, 32, 13]</th><th>[0, 35, 12]</th><th>[0, 34, 12]</th><th>[0, 34, 13]</th><th>[0, 35, 13]</th><th>[0, 35, 14]</th><th>[0, 34, 14]</th><th>[0, 34, 15]</th><th>[0, 35, 15]</th></tr>
+<tr><td>Non-inverted</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_CMT_IOI-INTERNAL_VREF:VREF"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>INTERNAL_VREF:VREF</th><th>[0, 39, 15]</th><th>[0, 38, 15]</th><th>[0, 38, 13]</th><th>[0, 38, 12]</th><th>[0, 39, 12]</th></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>750</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>900</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>1080</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>1250</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_CMT_IOI-DCI:NMASK_TERM_SPLIT"></div>
+<div id="bits-xc5v-HCLK_CMT_IOI-DCI:PMASK_TERM_SPLIT"></div>
+<div id="bits-xc5v-HCLK_CMT_IOI-DCI:PMASK_TERM_VCC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:NMASK_TERM_SPLIT</th><th>[0, 51, 15]</th><th>[0, 48, 12]</th><th>[0, 49, 12]</th><th>[0, 49, 13]</th><th>[0, 48, 13]</th></tr>
+<tr><th>DCI:PMASK_TERM_SPLIT</th><th>[0, 49, 15]</th><th>[0, 48, 15]</th><th>[0, 47, 12]</th><th>[0, 46, 12]</th><th>[0, 46, 13]</th></tr>
+<tr><th>DCI:PMASK_TERM_VCC</th><th>[0, 50, 13]</th><th>[0, 51, 13]</th><th>[0, 51, 14]</th><th>[0, 50, 14]</th><th>[0, 50, 15]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_CMT_IOI-DCI:PREF"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:PREF</th><th>[0, 52, 15]</th><th>[0, 53, 14]</th><th>[0, 50, 12]</th><th>[0, 51, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-HCLK_CMT_IOI-DCI:LVDIV2"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCI:LVDIV2</th><th>[0, 53, 15]</th><th>[0, 53, 12]</th><th>[0, 52, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
 </section>
 <section id="hclk-cmt">
 <h3><code class="docutils literal notranslate"><span class="pre">HCLK_CMT</span></code><a class="headerlink" href="#hclk-cmt" title="Link to this heading"></a></h3>
@@ -5796,6 +6067,54 @@ <h3><code class="docutils literal notranslate"><span class="pre">HCLK_CMT</span>
 </table>
 </section>
 </section>
+<section id="i-o-standard-data">
+<h2>I/O standard data<a class="headerlink" href="#i-o-standard-data" title="Link to this heading"></a></h2>
+<table class="docutils align-default">
+<tr><th rowspan="2">Name</th><th colspan="12">IOSTD:LVDSBIAS</th></tr>
+<tr><th>[11]</th><th>[10]</th><th>[9]</th><th>[8]</th><th>[7]</th><th>[6]</th><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>HT_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDSEXT_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDS_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>RSDS_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+</table>
+<table class="docutils align-default">
+<tr><th rowspan="2">Name</th><th colspan="3">IOSTD:DCI:LVDIV2</th></tr>
+<tr><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>LVDCI_DV2_15</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDCI_DV2_18</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVDCI_DV2_25</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td></tr>
+</table>
+<table class="docutils align-default">
+<tr><th rowspan="2">Name</th><th colspan="5">IOSTD:DCI:PMASK_TERM_VCC</th></tr>
+<tr><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>GTLP_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>GTL_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_III_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_III_DCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_IV_DCI</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_IV_DCI_18</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+</table>
+<table class="docutils align-default">
+<tr><th rowspan="2">Name</th><th colspan="5">IOSTD:DCI:PMASK_TERM_SPLIT</th><th colspan="5">IOSTD:DCI:NMASK_TERM_SPLIT</th></tr>
+<tr><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>HSTL_II_DCI</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_II_DCI_18</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_II_T_DCI</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_II_T_DCI_18</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_I_DCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_II_DCI</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_II_T_DCI</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL2_II_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL2_II_T_DCI</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL2_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+</table>
+</section>
 </section>
 
 
diff --git a/xilinx/virtex5/index.html b/xilinx/virtex5/index.html
index f254a019..90294d9d 100644
--- a/xilinx/virtex5/index.html
+++ b/xilinx/virtex5/index.html
@@ -153,6 +153,7 @@ <h1>Virtex 5<a class="headerlink" href="#virtex-5" title="Link to this heading">
 <li class="toctree-l2"><a class="reference internal" href="clock.html#spine-muxes-mgt">Spine muxes — MGT</a></li>
 <li class="toctree-l2"><a class="reference internal" href="clock.html#mgt-clock-repeater">MGT clock repeater</a></li>
 <li class="toctree-l2"><a class="reference internal" href="clock.html#io-clock-nodes">IO clock nodes</a></li>
+<li class="toctree-l2"><a class="reference internal" href="clock.html#i-o-standard-data">I/O standard data</a></li>
 </ul>
 </li>
 <li class="toctree-l1"><a class="reference internal" href="ppc.html">PowerPC cores</a><ul>
diff --git a/xilinx/virtex5/io.html b/xilinx/virtex5/io.html
index 7ded8b61..014ada9a 100644
--- a/xilinx/virtex5/io.html
+++ b/xilinx/virtex5/io.html
@@ -255,6 +255,528 @@ <h2>I/O banks and special functions<a class="headerlink" href="#i-o-banks-and-sp
 </section>
 <section id="bitstream">
 <h2>Bitstream<a class="headerlink" href="#bitstream" title="Link to this heading"></a></h2>
+<table class="docutils align-default">
+<tr><th rowspan="2">Name</th><th colspan="5">IOSTD:PDRIVE</th><th colspan="5">IOSTD:NDRIVE</th></tr>
+<tr><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>BLVDS_25</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>GTL</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>GTLP</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>GTLP_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>GTL_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>HSTL_I</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>HSTL_II</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_III</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>HSTL_III_18</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_III_DCI</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>HSTL_III_DCI_18</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_II_18</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>HSTL_II_DCI</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_II_DCI_18</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>HSTL_II_T_DCI</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>HSTL_II_T_DCI_18</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>HSTL_IV</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_IV_18</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>HSTL_IV_DCI</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_IV_DCI_18</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>HSTL_I_12</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_I_18</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>HSTL_I_DCI</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>HSTL_I_DCI_18</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS12.2</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS12.4</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS12.6</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>LVCMOS12.8</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVCMOS15.12</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS15.16</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS15.2</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS15.4</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS15.6</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS15.8</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>LVCMOS18.12</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS18.16</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVCMOS18.2</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVCMOS18.4</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS18.6</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS18.8</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS25.12</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS25.16</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS25.2</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS25.24</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS25.4</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS25.6</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS25.8</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>LVCMOS33.12</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS33.16</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS33.2</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS33.24</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS33.4</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS33.6</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS33.8</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>LVPECL_25</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>LVTTL.12</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVTTL.16</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVTTL.2</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVTTL.24</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVTTL.4</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>LVTTL.6</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>LVTTL.8</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>PCI33_3</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>PCI66_3</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>PCIX</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_I</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_II</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_II_DCI</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>SSTL18_II_T_DCI</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>SSTL18_I_DCI</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>SSTL2_I</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL2_II</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>SSTL2_II_DCI</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>SSTL2_II_T_DCI</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>SSTL2_I_DCI</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>VR</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+</table>
+<table class="docutils align-default">
+<tr><th rowspan="2">Name</th><th colspan="6">IOSTD:PSLEW</th><th colspan="6">IOSTD:NSLEW</th></tr>
+<tr><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>BLVDS_25</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>GTL</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>GTLP</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>GTLP_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>GTL_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>HSLVDCI_15</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSLVDCI_18</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSLVDCI_25</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>HSLVDCI_33</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>HSTL_I</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>HSTL_II</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_III</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_III_18</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_III_DCI</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>HSTL_III_DCI_18</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>HSTL_II_18</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_II_DCI</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>HSTL_II_DCI_18</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>HSTL_II_T_DCI</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_II_T_DCI_18</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_IV</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_IV_18</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_IV_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>HSTL_IV_DCI_18</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>HSTL_I_12</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_I_18</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>HSTL_I_DCI</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_I_DCI_18</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS12.2.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS12.2.SLOW</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS12.4.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS12.4.SLOW</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS12.6.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS12.6.SLOW</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS12.8.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS12.8.SLOW</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS15.12.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS15.12.SLOW</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS15.16.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS15.16.SLOW</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS15.2.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS15.2.SLOW</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS15.4.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS15.4.SLOW</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS15.6.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS15.6.SLOW</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS15.8.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS15.8.SLOW</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS18.12.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS18.12.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVCMOS18.16.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS18.16.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS18.2.FAST</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS18.2.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS18.4.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS18.4.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>LVCMOS18.6.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS18.6.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVCMOS18.8.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS18.8.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVCMOS25.12.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS25.12.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS25.16.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS25.16.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS25.2.FAST</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS25.2.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS25.24.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS25.24.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS25.4.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS25.4.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS25.6.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS25.6.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS25.8.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVCMOS25.8.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS33.12.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS33.12.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS33.16.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS33.16.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS33.2.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS33.2.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS33.24.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS33.24.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVCMOS33.4.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS33.4.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>LVCMOS33.6.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS33.6.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVCMOS33.8.FAST</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVCMOS33.8.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>LVDCI_15</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVDCI_18</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDCI_25</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVDCI_33</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVDCI_DV2_15</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>LVDCI_DV2_18</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVDCI_DV2_25</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>LVPECL_25</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVTTL.12.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVTTL.12.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>LVTTL.16.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVTTL.16.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>LVTTL.2.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVTTL.2.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>LVTTL.24.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVTTL.24.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>LVTTL.4.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVTTL.4.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>LVTTL.6.FAST</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVTTL.6.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>LVTTL.8.FAST</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>LVTTL.8.SLOW</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>PCI33_3</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>PCI66_3</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>PCIX</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_I</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>SSTL18_II</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>SSTL18_II_DCI</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>SSTL18_II_T_DCI</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_I_DCI</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL2_I</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>SSTL2_II</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>SSTL2_II_DCI</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>SSTL2_II_T_DCI</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>SSTL2_I_DCI</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>VR</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+</table>
+<table class="docutils align-default">
+<tr><th rowspan="2">Name</th><th colspan="6">IOSTD:OUTPUT_MISC</th></tr>
+<tr><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>BLVDS_25</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>GTL</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>GTLP</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>GTLP_DCI</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>GTL_DCI</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>HSLVDCI_15</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSLVDCI_18</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSLVDCI_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSLVDCI_33</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_I</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_II</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_III</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_III_18</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_III_DCI</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_III_DCI_18</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_II_18</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_II_DCI</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_II_DCI_18</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_II_T_DCI</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_II_T_DCI_18</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_IV</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_IV_18</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_IV_DCI</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_IV_DCI_18</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>HSTL_I_12</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_I_18</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_I_DCI</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>HSTL_I_DCI_18</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS12</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS15</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS18</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVCMOS33</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDCI_15</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDCI_18</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDCI_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDCI_33</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDCI_DV2_15</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDCI_DV2_18</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVDCI_DV2_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVPECL_25</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>LVTTL</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>PCI33_3</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>PCI66_3</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>PCIX</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_I</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_II</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_II_DCI</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_II_T_DCI</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL18_I_DCI</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL2_I</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL2_II</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL2_II_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL2_II_T_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>SSTL2_I_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+</table>
+<table class="docutils align-default">
+<tr><th rowspan="2">Name</th><th colspan="9">IOSTD:LVDS_T</th><th colspan="9">IOSTD:LVDS_C</th></tr>
+<tr><th>[8]</th><th>[7]</th><th>[6]</th><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th><th>[8]</th><th>[7]</th><th>[6]</th><th>[5]</th><th>[4]</th><th>[3]</th><th>[2]</th><th>[1]</th><th>[0]</th></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OUTPUT_HT_25</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>OUTPUT_LVDSEXT_25</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>OUTPUT_LVDS_25</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>OUTPUT_RSDS_25</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>TERM_HT_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>TERM_LVDSEXT_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>TERM_LVDS_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>TERM_RSDS_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="39">IO bittile 0</th></tr><tr><th rowspan="2">Row</th><th colspan="38">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th><th>30</th><th>31</th><th>32</th><th>33</th><th>34</th><th>35</th><th>36</th><th>37</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:PDRIVE" title="IOB0:PDRIVE[1]">IOB0:PDRIVE[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:NDRIVE" title="~IOB0:NDRIVE[1]">~IOB0:NDRIVE[1]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:VR" title="IOB0:VR">IOB0:VR</a></td><td><a href="#bits-xc5v-IO-IOB0:OUTPUT_MISC" title="IOB0:OUTPUT_MISC[5]">IOB0:OUTPUT_MISC[5]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:OUTPUT_MISC" title="IOB0:OUTPUT_MISC[4]">IOB0:OUTPUT_MISC[4]</a></td><td>-</td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:LVDS" title="IOB0:LVDS[8]">IOB0:LVDS[8]</a></td><td><a href="#bits-xc5v-IO-IOB0:DCIUPDATEMODE_ASREQUIRED" title="~IOB0:DCIUPDATEMODE_ASREQUIRED">~IOB0:DCIUPDATEMODE_ASREQUIRED</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:NDRIVE" title="IOB0:NDRIVE[3]">IOB0:NDRIVE[3]</a></td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:OUTPUT_DELAY" title="IOB0:OUTPUT_DELAY">IOB0:OUTPUT_DELAY</a></td><td><a href="#bits-xc5v-IO-IOB0:DCI_MODE" title="IOB0:DCI_MODE[0]">IOB0:DCI_MODE[0]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:DCI_MODE" title="IOB0:DCI_MODE[1]">IOB0:DCI_MODE[1]</a></td><td><a href="#bits-xc5v-IO-IOB0:DCI_MODE" title="IOB0:DCI_MODE[2]">IOB0:DCI_MODE[2]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:PDRIVE" title="~IOB0:PDRIVE[3]">~IOB0:PDRIVE[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:NDRIVE" title="~IOB0:NDRIVE[0]">~IOB0:NDRIVE[0]</a></td><td><a href="#bits-xc5v-IO-IOB0:PDRIVE" title="IOB0:PDRIVE[4]">IOB0:PDRIVE[4]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:NDRIVE" title="IOB0:NDRIVE[4]">IOB0:NDRIVE[4]</a></td><td><a href="#bits-xc5v-IO-IOB0:LVDS" title="IOB0:LVDS[0]">IOB0:LVDS[0]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:DCI_T" title="IOB0:DCI_T">IOB0:DCI_T</a></td><td>-</td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:LVDS" title="IOB0:LVDS[1]">IOB0:LVDS[1]</a></td><td><a href="#bits-xc5v-IO-IOB0:PDRIVE" title="IOB0:PDRIVE[2]">IOB0:PDRIVE[2]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:PDRIVE" title="~IOB0:PDRIVE[0]">~IOB0:PDRIVE[0]</a></td><td><a href="#bits-xc5v-IO-IOB0:NDRIVE" title="~IOB0:NDRIVE[2]">~IOB0:NDRIVE[2]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:PULL" title="IOB0:PULL[1]">IOB0:PULL[1]</a></td><td><a href="#bits-xc5v-IO-IOB0:LVDS" title="IOB0:LVDS[2]">IOB0:LVDS[2]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:PULL" title="IOB0:PULL[0]">IOB0:PULL[0]</a></td><td><a href="#bits-xc5v-IO-IOB0:DCI_MISC" title="IOB0:DCI_MISC[0]">IOB0:DCI_MISC[0]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:LVDS" title="IOB0:LVDS[3]">IOB0:LVDS[3]</a></td><td><a href="#bits-xc5v-IO-IOB0:PSLEW" title="IOB0:PSLEW[0]">IOB0:PSLEW[0]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:LVDS" title="IOB0:LVDS[4]">IOB0:LVDS[4]</a></td><td><a href="#bits-xc5v-IO-IOB0:IBUF_MODE" title="IOB0:IBUF_MODE[0]">IOB0:IBUF_MODE[0]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:OUTPUT_ENABLE" title="IOB0:OUTPUT_ENABLE[0]">IOB0:OUTPUT_ENABLE[0]</a></td><td><a href="#bits-xc5v-IO-IOB0:PULL" title="IOB0:PULL[2]">IOB0:PULL[2]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:OUTPUT_MISC" title="IOB0:OUTPUT_MISC[3]">IOB0:OUTPUT_MISC[3]</a></td><td><a href="#bits-xc5v-IO-IOB0:NSLEW" title="IOB0:NSLEW[5]">IOB0:NSLEW[5]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:LVDS" title="IOB0:LVDS[5]">IOB0:LVDS[5]</a></td><td><a href="#bits-xc5v-IO-IOB0:LVDS" title="IOB0:LVDS[6]">IOB0:LVDS[6]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:OUTPUT_ENABLE" title="IOB0:OUTPUT_ENABLE[1]">IOB0:OUTPUT_ENABLE[1]</a></td><td><a href="#bits-xc5v-IO-IOB0:LVDS" title="IOB0:LVDS[7]">IOB0:LVDS[7]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:INV.I" title="~IOB0:INV.I">~IOB0:INV.I</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:PSLEW" title="IOB0:PSLEW[1]">IOB0:PSLEW[1]</a></td><td><a href="#bits-xc5v-IO-IOB0:PSLEW" title="IOB0:PSLEW[2]">IOB0:PSLEW[2]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:OUTPUT_MISC" title="IOB0:OUTPUT_MISC[0]">IOB0:OUTPUT_MISC[0]</a></td><td><a href="#bits-xc5v-IO-IOB0:OUTPUT_MISC" title="IOB0:OUTPUT_MISC[1]">IOB0:OUTPUT_MISC[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:IBUF_MODE" title="IOB0:IBUF_MODE[1]">IOB0:IBUF_MODE[1]</a></td><td><a href="#bits-xc5v-IO-IOB0:OUTPUT_MISC" title="IOB0:OUTPUT_MISC[2]">IOB0:OUTPUT_MISC[2]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:NSLEW" title="IOB0:NSLEW[4]">IOB0:NSLEW[4]</a></td><td><a href="#bits-xc5v-IO-IOB0:DCI_MISC" title="IOB0:DCI_MISC[1]">IOB0:DCI_MISC[1]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:NSLEW" title="IOB0:NSLEW[1]">IOB0:NSLEW[1]</a></td><td><a href="#bits-xc5v-IO-IOB0:PSLEW" title="IOB0:PSLEW[5]">IOB0:PSLEW[5]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:NSLEW" title="IOB0:NSLEW[3]">IOB0:NSLEW[3]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:IBUF_MODE" title="IOB0:IBUF_MODE[2]">IOB0:IBUF_MODE[2]</a></td><td><a href="#bits-xc5v-IO-IOB0:PSLEW" title="IOB0:PSLEW[4]">IOB0:PSLEW[4]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:VREF_SYSMON" title="IOB0:VREF_SYSMON">IOB0:VREF_SYSMON</a></td><td><a href="#bits-xc5v-IO-IOB0:PSLEW" title="IOB0:PSLEW[3]">IOB0:PSLEW[3]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB0:NSLEW" title="IOB0:NSLEW[0]">IOB0:NSLEW[0]</a></td><td><a href="#bits-xc5v-IO-IOB0:NSLEW" title="IOB0:NSLEW[2]">IOB0:NSLEW[2]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:NSLEW" title="IOB1:NSLEW[0]">IOB1:NSLEW[0]</a></td><td><a href="#bits-xc5v-IO-IOB1:NSLEW" title="IOB1:NSLEW[2]">IOB1:NSLEW[2]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:VREF_SYSMON" title="IOB1:VREF_SYSMON">IOB1:VREF_SYSMON</a></td><td><a href="#bits-xc5v-IO-IOB1:PSLEW" title="IOB1:PSLEW[3]">IOB1:PSLEW[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:IBUF_MODE" title="IOB1:IBUF_MODE[2]">IOB1:IBUF_MODE[2]</a></td><td><a href="#bits-xc5v-IO-IOB1:PSLEW" title="IOB1:PSLEW[4]">IOB1:PSLEW[4]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:NSLEW" title="IOB1:NSLEW[3]">IOB1:NSLEW[3]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:NSLEW" title="IOB1:NSLEW[1]">IOB1:NSLEW[1]</a></td><td><a href="#bits-xc5v-IO-IOB1:PSLEW" title="IOB1:PSLEW[5]">IOB1:PSLEW[5]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:NSLEW" title="IOB1:NSLEW[4]">IOB1:NSLEW[4]</a></td><td><a href="#bits-xc5v-IO-IOB1:DCI_MISC" title="IOB1:DCI_MISC[1]">IOB1:DCI_MISC[1]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:IBUF_MODE" title="IOB1:IBUF_MODE[1]">IOB1:IBUF_MODE[1]</a></td><td><a href="#bits-xc5v-IO-IOB1:OUTPUT_MISC" title="IOB1:OUTPUT_MISC[2]">IOB1:OUTPUT_MISC[2]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:OUTPUT_MISC" title="IOB1:OUTPUT_MISC[0]">IOB1:OUTPUT_MISC[0]</a></td><td><a href="#bits-xc5v-IO-IOB1:OUTPUT_MISC" title="IOB1:OUTPUT_MISC[1]">IOB1:OUTPUT_MISC[1]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:INV.I" title="~IOB1:INV.I">~IOB1:INV.I</a></td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:PSLEW" title="IOB1:PSLEW[1]">IOB1:PSLEW[1]</a></td><td><a href="#bits-xc5v-IO-IOB1:PSLEW" title="IOB1:PSLEW[2]">IOB1:PSLEW[2]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:OUTPUT_ENABLE" title="IOB1:OUTPUT_ENABLE[0]">IOB1:OUTPUT_ENABLE[0]</a></td><td><a href="#bits-xc5v-IO-IOB1:LVDS" title="IOB1:LVDS[7]">IOB1:LVDS[7]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:LVDS" title="IOB1:LVDS[5]">IOB1:LVDS[5]</a></td><td><a href="#bits-xc5v-IO-IOB1:LVDS" title="IOB1:LVDS[6]">IOB1:LVDS[6]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:OUTPUT_MISC" title="IOB1:OUTPUT_MISC[3]">IOB1:OUTPUT_MISC[3]</a></td><td><a href="#bits-xc5v-IO-IOB1:NSLEW" title="IOB1:NSLEW[5]">IOB1:NSLEW[5]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:OUTPUT_ENABLE" title="IOB1:OUTPUT_ENABLE[1]">IOB1:OUTPUT_ENABLE[1]</a></td><td><a href="#bits-xc5v-IO-IOB1:PULL" title="IOB1:PULL[2]">IOB1:PULL[2]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:LVDS" title="IOB1:LVDS[4]">IOB1:LVDS[4]</a></td><td><a href="#bits-xc5v-IO-IOB1:IBUF_MODE" title="IOB1:IBUF_MODE[0]">IOB1:IBUF_MODE[0]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:LVDS" title="IOB1:LVDS[3]">IOB1:LVDS[3]</a></td><td><a href="#bits-xc5v-IO-IOB1:PSLEW" title="IOB1:PSLEW[0]">IOB1:PSLEW[0]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:PULL" title="IOB1:PULL[0]">IOB1:PULL[0]</a></td><td><a href="#bits-xc5v-IO-IOB1:DCI_MISC" title="IOB1:DCI_MISC[0]">IOB1:DCI_MISC[0]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:PULL" title="IOB1:PULL[1]">IOB1:PULL[1]</a></td><td><a href="#bits-xc5v-IO-IOB1:LVDS" title="IOB1:LVDS[2]">IOB1:LVDS[2]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:PDRIVE" title="~IOB1:PDRIVE[0]">~IOB1:PDRIVE[0]</a></td><td><a href="#bits-xc5v-IO-IOB1:NDRIVE" title="~IOB1:NDRIVE[2]">~IOB1:NDRIVE[2]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:LVDS" title="IOB1:LVDS[1]">IOB1:LVDS[1]</a></td><td><a href="#bits-xc5v-IO-IOB1:PDRIVE" title="IOB1:PDRIVE[2]">IOB1:PDRIVE[2]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:DCI_T" title="IOB1:DCI_T">IOB1:DCI_T</a></td><td>-</td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:NDRIVE" title="IOB1:NDRIVE[4]">IOB1:NDRIVE[4]</a></td><td><a href="#bits-xc5v-IO-IOB1:LVDS" title="IOB1:LVDS[0]">IOB1:LVDS[0]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:NDRIVE" title="~IOB1:NDRIVE[0]">~IOB1:NDRIVE[0]</a></td><td><a href="#bits-xc5v-IO-IOB1:PDRIVE" title="IOB1:PDRIVE[4]">IOB1:PDRIVE[4]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:PDRIVE" title="~IOB1:PDRIVE[3]">~IOB1:PDRIVE[3]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:DCI_MODE" title="IOB1:DCI_MODE[1]">IOB1:DCI_MODE[1]</a></td><td><a href="#bits-xc5v-IO-IOB1:DCI_MODE" title="IOB1:DCI_MODE[2]">IOB1:DCI_MODE[2]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:OUTPUT_DELAY" title="IOB1:OUTPUT_DELAY">IOB1:OUTPUT_DELAY</a></td><td><a href="#bits-xc5v-IO-IOB1:DCI_MODE" title="IOB1:DCI_MODE[0]">IOB1:DCI_MODE[0]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:NDRIVE" title="IOB1:NDRIVE[3]">IOB1:NDRIVE[3]</a></td><td>-</td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:LVDS" title="IOB1:LVDS[8]">IOB1:LVDS[8]</a></td><td><a href="#bits-xc5v-IO-IOB1:DCIUPDATEMODE_ASREQUIRED" title="~IOB1:DCIUPDATEMODE_ASREQUIRED">~IOB1:DCIUPDATEMODE_ASREQUIRED</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:OUTPUT_MISC" title="IOB1:OUTPUT_MISC[4]">IOB1:OUTPUT_MISC[4]</a></td><td>-</td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:VR" title="IOB1:VR">IOB1:VR</a></td><td><a href="#bits-xc5v-IO-IOB1:OUTPUT_MISC" title="IOB1:OUTPUT_MISC[5]">IOB1:OUTPUT_MISC[5]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:NDRIVE" title="~IOB1:NDRIVE[1]">~IOB1:NDRIVE[1]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-IO-IOB1:PDRIVE" title="IOB1:PDRIVE[1]">IOB1:PDRIVE[1]</a></td></tr>
+</table>
+<div id="bits-xc5v-IO-IOB0:DCIUPDATEMODE_ASREQUIRED"></div>
+<div id="bits-xc5v-IO-IOB0:INV.I"></div>
+<div id="bits-xc5v-IO-IOB1:DCIUPDATEMODE_ASREQUIRED"></div>
+<div id="bits-xc5v-IO-IOB1:INV.I"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOB0:DCIUPDATEMODE_ASREQUIRED</th><th>[0, 37, 5]</th></tr>
+<tr><th>IOB0:INV.I</th><th>[0, 31, 23]</th></tr>
+<tr><th>IOB1:DCIUPDATEMODE_ASREQUIRED</th><th>[0, 37, 58]</th></tr>
+<tr><th>IOB1:INV.I</th><th>[0, 31, 40]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc5v-IO-IOB0:DCI_T"></div>
+<div id="bits-xc5v-IO-IOB0:OUTPUT_DELAY"></div>
+<div id="bits-xc5v-IO-IOB0:VR"></div>
+<div id="bits-xc5v-IO-IOB0:VREF_SYSMON"></div>
+<div id="bits-xc5v-IO-IOB1:DCI_T"></div>
+<div id="bits-xc5v-IO-IOB1:OUTPUT_DELAY"></div>
+<div id="bits-xc5v-IO-IOB1:VR"></div>
+<div id="bits-xc5v-IO-IOB1:VREF_SYSMON"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOB0:DCI_T</th><th>[0, 36, 12]</th></tr>
+<tr><th>IOB0:OUTPUT_DELAY</th><th>[0, 36, 7]</th></tr>
+<tr><th>IOB0:VR</th><th>[0, 36, 3]</th></tr>
+<tr><th>IOB0:VREF_SYSMON</th><th>[0, 36, 30]</th></tr>
+<tr><th>IOB1:DCI_T</th><th>[0, 36, 51]</th></tr>
+<tr><th>IOB1:OUTPUT_DELAY</th><th>[0, 36, 56]</th></tr>
+<tr><th>IOB1:VR</th><th>[0, 36, 60]</th></tr>
+<tr><th>IOB1:VREF_SYSMON</th><th>[0, 36, 33]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-IO-IOB0:NDRIVE"></div>
+<div id="bits-xc5v-IO-IOB1:NDRIVE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOB0:NDRIVE</th><th>[0, 36, 11]</th><th>[0, 36, 6]</th><th>[0, 37, 14]</th><th>[0, 37, 2]</th><th>[0, 36, 10]</th></tr>
+<tr><th>IOB1:NDRIVE</th><th>[0, 36, 52]</th><th>[0, 36, 57]</th><th>[0, 37, 49]</th><th>[0, 37, 61]</th><th>[0, 36, 53]</th></tr>
+<tr><td>Mixed inversion</td><td>[4]</td><td>[3]</td><td>~[2]</td><td>~[1]</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc5v-IO-IOB0:PDRIVE"></div>
+<div id="bits-xc5v-IO-IOB1:PDRIVE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOB0:PDRIVE</th><th>[0, 37, 10]</th><th>[0, 37, 9]</th><th>[0, 37, 13]</th><th>[0, 37, 0]</th><th>[0, 36, 14]</th></tr>
+<tr><th>IOB1:PDRIVE</th><th>[0, 37, 53]</th><th>[0, 37, 54]</th><th>[0, 37, 50]</th><th>[0, 37, 63]</th><th>[0, 36, 49]</th></tr>
+<tr><td>Mixed inversion</td><td>[4]</td><td>~[3]</td><td>[2]</td><td>[1]</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc5v-IO-IOB0:PULL"></div>
+<div id="bits-xc5v-IO-IOB1:PULL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOB0:PULL</th><th>[0, 37, 19]</th><th>[0, 36, 15]</th><th>[0, 36, 16]</th></tr>
+<tr><th>IOB1:PULL</th><th>[0, 37, 44]</th><th>[0, 36, 48]</th><th>[0, 36, 47]</th></tr>
+<tr><td>PULLDOWN</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>PULLUP</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>KEEPER</td><td>1</td><td>0</td><td>1</td></tr>
+</table>
+<div id="bits-xc5v-IO-IOB0:DCI_MISC"></div>
+<div id="bits-xc5v-IO-IOB0:OUTPUT_ENABLE"></div>
+<div id="bits-xc5v-IO-IOB1:DCI_MISC"></div>
+<div id="bits-xc5v-IO-IOB1:OUTPUT_ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOB0:DCI_MISC</th><th>[0, 37, 26]</th><th>[0, 37, 16]</th></tr>
+<tr><th>IOB0:OUTPUT_ENABLE</th><th>[0, 36, 22]</th><th>[0, 36, 19]</th></tr>
+<tr><th>IOB1:DCI_MISC</th><th>[0, 37, 37]</th><th>[0, 37, 47]</th></tr>
+<tr><th>IOB1:OUTPUT_ENABLE</th><th>[0, 36, 44]</th><th>[0, 36, 41]</th></tr>
+<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-IO-IOB0:NSLEW"></div>
+<div id="bits-xc5v-IO-IOB0:OUTPUT_MISC"></div>
+<div id="bits-xc5v-IO-IOB0:PSLEW"></div>
+<div id="bits-xc5v-IO-IOB1:NSLEW"></div>
+<div id="bits-xc5v-IO-IOB1:OUTPUT_MISC"></div>
+<div id="bits-xc5v-IO-IOB1:PSLEW"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOB0:NSLEW</th><th>[0, 37, 20]</th><th>[0, 36, 26]</th><th>[0, 37, 28]</th><th>[0, 37, 31]</th><th>[0, 36, 27]</th><th>[0, 36, 31]</th></tr>
+<tr><th>IOB0:OUTPUT_MISC</th><th>[0, 37, 3]</th><th>[0, 36, 4]</th><th>[0, 36, 20]</th><th>[0, 37, 25]</th><th>[0, 37, 24]</th><th>[0, 36, 24]</th></tr>
+<tr><th>IOB0:PSLEW</th><th>[0, 37, 27]</th><th>[0, 37, 29]</th><th>[0, 37, 30]</th><th>[0, 37, 23]</th><th>[0, 36, 23]</th><th>[0, 37, 17]</th></tr>
+<tr><th>IOB1:NSLEW</th><th>[0, 37, 43]</th><th>[0, 36, 37]</th><th>[0, 37, 35]</th><th>[0, 37, 32]</th><th>[0, 36, 36]</th><th>[0, 36, 32]</th></tr>
+<tr><th>IOB1:OUTPUT_MISC</th><th>[0, 37, 60]</th><th>[0, 36, 59]</th><th>[0, 36, 43]</th><th>[0, 37, 38]</th><th>[0, 37, 39]</th><th>[0, 36, 39]</th></tr>
+<tr><th>IOB1:PSLEW</th><th>[0, 37, 36]</th><th>[0, 37, 34]</th><th>[0, 37, 33]</th><th>[0, 37, 40]</th><th>[0, 36, 40]</th><th>[0, 37, 46]</th></tr>
+<tr><td>Non-inverted</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-IO-IOB0:DCI_MODE"></div>
+<div id="bits-xc5v-IO-IOB1:DCI_MODE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOB0:DCI_MODE</th><th>[0, 37, 8]</th><th>[0, 36, 8]</th><th>[0, 37, 7]</th></tr>
+<tr><th>IOB1:DCI_MODE</th><th>[0, 37, 55]</th><th>[0, 36, 55]</th><th>[0, 37, 56]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OUTPUT</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>OUTPUT_HALF</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>TERM_VCC</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>TERM_SPLIT</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc5v-IO-IOB0:LVDS"></div>
+<div id="bits-xc5v-IO-IOB1:LVDS"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOB0:LVDS</th><th>[0, 36, 5]</th><th>[0, 37, 22]</th><th>[0, 37, 21]</th><th>[0, 36, 21]</th><th>[0, 36, 18]</th><th>[0, 36, 17]</th><th>[0, 37, 15]</th><th>[0, 36, 13]</th><th>[0, 37, 11]</th></tr>
+<tr><th>IOB1:LVDS</th><th>[0, 36, 58]</th><th>[0, 37, 41]</th><th>[0, 37, 42]</th><th>[0, 36, 42]</th><th>[0, 36, 45]</th><th>[0, 36, 46]</th><th>[0, 37, 48]</th><th>[0, 36, 50]</th><th>[0, 37, 52]</th></tr>
+<tr><td>Non-inverted</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc5v-IO-IOB0:IBUF_MODE"></div>
+<div id="bits-xc5v-IO-IOB1:IBUF_MODE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOB0:IBUF_MODE</th><th>[0, 36, 29]</th><th>[0, 36, 25]</th><th>[0, 37, 18]</th></tr>
+<tr><th>IOB1:IBUF_MODE</th><th>[0, 36, 34]</th><th>[0, 36, 38]</th><th>[0, 37, 45]</th></tr>
+<tr><td>OFF</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>VREF</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>DIFF</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>CMOS</td><td>1</td><td>1</td><td>1</td></tr>
+</table>
 </section>
 </section>
 
diff --git a/xilinx/virtex6/bram.html b/xilinx/virtex6/bram.html
index 6b1ebeb4..f5727f9e 100644
--- a/xilinx/virtex6/bram.html
+++ b/xilinx/virtex6/bram.html
@@ -69,6 +69,7 @@
 <li class="toctree-l3"><a class="reference internal" href="center.html">Configuration Center</a></li>
 <li class="toctree-l3"><a class="reference internal" href="emac.html">Ethernet MACs</a></li>
 <li class="toctree-l3"><a class="reference internal" href="pcie.html">PCI Express cores</a></li>
+<li class="toctree-l3"><a class="reference internal" href="gtx.html">GTX transceivers</a></li>
 <li class="toctree-l3"><a class="reference internal" href="config.html">Configuration registers</a></li>
 </ul>
 </li>
diff --git a/xilinx/virtex6/center.html b/xilinx/virtex6/center.html
index 8f5a28a5..4e86f0ee 100644
--- a/xilinx/virtex6/center.html
+++ b/xilinx/virtex6/center.html
@@ -70,6 +70,7 @@
 </li>
 <li class="toctree-l3"><a class="reference internal" href="emac.html">Ethernet MACs</a></li>
 <li class="toctree-l3"><a class="reference internal" href="pcie.html">PCI Express cores</a></li>
+<li class="toctree-l3"><a class="reference internal" href="gtx.html">GTX transceivers</a></li>
 <li class="toctree-l3"><a class="reference internal" href="config.html">Configuration registers</a></li>
 </ul>
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index 450254a6..e5ac392c 100644
--- a/xilinx/virtex6/clb.html
+++ b/xilinx/virtex6/clb.html
@@ -70,6 +70,7 @@
 <li class="toctree-l3"><a class="reference internal" href="center.html">Configuration Center</a></li>
 <li class="toctree-l3"><a class="reference internal" href="emac.html">Ethernet MACs</a></li>
 <li class="toctree-l3"><a class="reference internal" href="pcie.html">PCI Express cores</a></li>
+<li class="toctree-l3"><a class="reference internal" href="gtx.html">GTX transceivers</a></li>
 <li class="toctree-l3"><a class="reference internal" href="config.html">Configuration registers</a></li>
 </ul>
 </li>
diff --git a/xilinx/virtex6/config.html b/xilinx/virtex6/config.html
index d8961434..114ce8af 100644
--- a/xilinx/virtex6/config.html
+++ b/xilinx/virtex6/config.html
@@ -20,7 +20,7 @@
     <link rel="index" title="Index" href="../../genindex.html" />
     <link rel="search" title="Search" href="../../search.html" />
     <link rel="next" title="Virtex 7" href="../virtex7/index.html" />
-    <link rel="prev" title="PCI Express cores" href="pcie.html" /> 
+    <link rel="prev" title="GTX transceivers" href="gtx.html" /> 
 </head>
 
 <body class="wy-body-for-nav"> 
@@ -66,6 +66,7 @@
 <li class="toctree-l3"><a class="reference internal" href="center.html">Configuration Center</a></li>
 <li class="toctree-l3"><a class="reference internal" href="emac.html">Ethernet MACs</a></li>
 <li class="toctree-l3"><a class="reference internal" href="pcie.html">PCI Express cores</a></li>
+<li class="toctree-l3"><a class="reference internal" href="gtx.html">GTX transceivers</a></li>
 <li class="toctree-l3 current"><a class="current reference internal" href="#">Configuration registers</a><ul>
 <li class="toctree-l4"><a class="reference internal" href="#cor"><code class="docutils literal notranslate"><span class="pre">COR</span></code></a></li>
 <li class="toctree-l4"><a class="reference internal" href="#cor1"><code class="docutils literal notranslate"><span class="pre">COR1</span></code></a></li>
@@ -821,7 +822,7 @@ <h2><code class="docutils literal notranslate"><span class="pre">UNK1C</span></c
            </div>
           </div>
           <footer><div class="rst-footer-buttons" role="navigation" aria-label="Footer">
-        <a href="pcie.html" class="btn btn-neutral float-left" title="PCI Express cores" accesskey="p" rel="prev"><span class="fa fa-arrow-circle-left" aria-hidden="true"></span> Previous</a>
+        <a href="gtx.html" class="btn btn-neutral float-left" title="GTX transceivers" accesskey="p" rel="prev"><span class="fa fa-arrow-circle-left" aria-hidden="true"></span> Previous</a>
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diff --git a/xilinx/virtex6/dsp.html b/xilinx/virtex6/dsp.html
index 22b99b28..e007ce9d 100644
--- a/xilinx/virtex6/dsp.html
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@@ -69,6 +69,7 @@
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+<li class="toctree-l3"><a class="reference internal" href="gtx.html">GTX transceivers</a></li>
 <li class="toctree-l3"><a class="reference internal" href="config.html">Configuration registers</a></li>
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index c1df096b..85394cc2 100644
--- a/xilinx/virtex6/emac.html
+++ b/xilinx/virtex6/emac.html
@@ -69,6 +69,7 @@
 </ul>
 </li>
 <li class="toctree-l3"><a class="reference internal" href="pcie.html">PCI Express cores</a></li>
+<li class="toctree-l3"><a class="reference internal" href="gtx.html">GTX transceivers</a></li>
 <li class="toctree-l3"><a class="reference internal" href="config.html">Configuration registers</a></li>
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index c0cbf015..dc1138f1 100644
--- a/xilinx/virtex6/geometry.html
+++ b/xilinx/virtex6/geometry.html
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+<li class="toctree-l3"><a class="reference internal" href="gtx.html">GTX transceivers</a></li>
 <li class="toctree-l3"><a class="reference internal" href="config.html">Configuration registers</a></li>
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diff --git a/xilinx/virtex6/gtx.html b/xilinx/virtex6/gtx.html
new file mode 100644
index 00000000..26ccec7d
--- /dev/null
+++ b/xilinx/virtex6/gtx.html
@@ -0,0 +1,8385 @@
+<!DOCTYPE html>
+<html class="writer-html5" lang="en" >
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+  <title>GTX transceivers &mdash; Project Combine  documentation</title>
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+<ul class="current">
+<li class="toctree-l1"><a class="reference internal" href="../../xc9500/index.html">Xilinx XC9500, XC9500XL, XC9500XV CPLDs</a></li>
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+<li class="toctree-l3"><a class="reference internal" href="geometry.html">Device geometry</a></li>
+<li class="toctree-l3"><a class="reference internal" href="interconnect.html">Interconnect</a></li>
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+<li class="toctree-l3 current"><a class="current reference internal" href="#">GTX transceivers</a><ul>
+<li class="toctree-l4"><a class="reference internal" href="#bitstream">Bitstream</a></li>
+</ul>
+</li>
+<li class="toctree-l3"><a class="reference internal" href="config.html">Configuration registers</a></li>
+</ul>
+</li>
+<li class="toctree-l2"><a class="reference internal" href="../virtex7/index.html">Virtex 7</a></li>
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+            <a href="../../_sources/xilinx/virtex6/gtx.rst.txt" rel="nofollow"> View page source</a>
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+          <div role="main" class="document" itemscope="itemscope" itemtype="http://schema.org/Article">
+           <div itemprop="articleBody">
+             
+  <section id="gtx-transceivers">
+<span id="virtex6-gtx"></span><h1>GTX transceivers<a class="headerlink" href="#gtx-transceivers" title="Link to this heading"></a></h1>
+<div class="admonition-todo admonition" id="id1">
+<p class="admonition-title">Todo</p>
+<p>document</p>
+</div>
+<section id="bitstream">
+<h2>Bitstream<a class="headerlink" href="#bitstream" title="Link to this heading"></a></h2>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 0</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[0]">GTX0:DRP00[0]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[0]">GTX0:PMA_RX_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[1]">GTX0:DRP00[1]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[1]">GTX0:PMA_RX_CFG[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[2]">GTX0:DRP00[2]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[2]">GTX0:PMA_RX_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[3]">GTX0:DRP00[3]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[3]">GTX0:PMA_RX_CFG[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[4]">GTX0:DRP00[4]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[4]">GTX0:PMA_RX_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[5]">GTX0:DRP00[5]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[5]">GTX0:PMA_RX_CFG[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[6]">GTX0:DRP00[6]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[6]">GTX0:PMA_RX_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[7]">GTX0:DRP00[7]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[7]">GTX0:PMA_RX_CFG[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[8]">GTX0:DRP00[8]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[8]">GTX0:PMA_RX_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[9]">GTX0:DRP00[9]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[9]">GTX0:PMA_RX_CFG[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[10]">GTX0:DRP00[10]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[10]">GTX0:PMA_RX_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[11]">GTX0:DRP00[11]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[11]">GTX0:PMA_RX_CFG[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[12]">GTX0:DRP00[12]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[12]">GTX0:PMA_RX_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[13]">GTX0:DRP00[13]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[13]">GTX0:PMA_RX_CFG[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[14]">GTX0:DRP00[14]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[14]">GTX0:PMA_RX_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP00" title="GTX0:DRP00[15]">GTX0:DRP00[15]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[15]">GTX0:PMA_RX_CFG[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[0]">GTX0:DRP01[0]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[16]">GTX0:PMA_RX_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[1]">GTX0:DRP01[1]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[17]">GTX0:PMA_RX_CFG[17]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[2]">GTX0:DRP01[2]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[18]">GTX0:PMA_RX_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[3]">GTX0:DRP01[3]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[19]">GTX0:PMA_RX_CFG[19]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[4]">GTX0:DRP01[4]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[20]">GTX0:PMA_RX_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[5]">GTX0:DRP01[5]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[21]">GTX0:PMA_RX_CFG[21]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[6]">GTX0:DRP01[6]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[22]">GTX0:PMA_RX_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[7]">GTX0:DRP01[7]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[23]">GTX0:PMA_RX_CFG[23]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[8]">GTX0:DRP01[8]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RX_CFG" title="GTX0:PMA_RX_CFG[24]">GTX0:PMA_RX_CFG[24]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[9]">GTX0:DRP01[9]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RXSYNC_CFG" title="GTX0:PMA_RXSYNC_CFG[0]">GTX0:PMA_RXSYNC_CFG[0]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[10]">GTX0:DRP01[10]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RXSYNC_CFG" title="GTX0:PMA_RXSYNC_CFG[1]">GTX0:PMA_RXSYNC_CFG[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[11]">GTX0:DRP01[11]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RXSYNC_CFG" title="GTX0:PMA_RXSYNC_CFG[2]">GTX0:PMA_RXSYNC_CFG[2]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[12]">GTX0:DRP01[12]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RXSYNC_CFG" title="GTX0:PMA_RXSYNC_CFG[3]">GTX0:PMA_RXSYNC_CFG[3]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[13]">GTX0:DRP01[13]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RXSYNC_CFG" title="GTX0:PMA_RXSYNC_CFG[4]">GTX0:PMA_RXSYNC_CFG[4]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[14]">GTX0:DRP01[14]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RXSYNC_CFG" title="GTX0:PMA_RXSYNC_CFG[5]">GTX0:PMA_RXSYNC_CFG[5]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP01" title="GTX0:DRP01[15]">GTX0:DRP01[15]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_RXSYNC_CFG" title="GTX0:PMA_RXSYNC_CFG[6]">GTX0:PMA_RXSYNC_CFG[6]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[0]">GTX0:DRP02[0]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[0]">GTX0:RXUSRCLK_DLY[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[1]">GTX0:DRP02[1]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[1]">GTX0:RXUSRCLK_DLY[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[2]">GTX0:DRP02[2]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[2]">GTX0:RXUSRCLK_DLY[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[3]">GTX0:DRP02[3]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[3]">GTX0:RXUSRCLK_DLY[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[4]">GTX0:DRP02[4]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[4]">GTX0:RXUSRCLK_DLY[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[5]">GTX0:DRP02[5]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[5]">GTX0:RXUSRCLK_DLY[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[6]">GTX0:DRP02[6]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[6]">GTX0:RXUSRCLK_DLY[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[7]">GTX0:DRP02[7]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[7]">GTX0:RXUSRCLK_DLY[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[8]">GTX0:DRP02[8]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[8]">GTX0:RXUSRCLK_DLY[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[9]">GTX0:DRP02[9]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[9]">GTX0:RXUSRCLK_DLY[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[10]">GTX0:DRP02[10]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[10]">GTX0:RXUSRCLK_DLY[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[11]">GTX0:DRP02[11]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[11]">GTX0:RXUSRCLK_DLY[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[12]">GTX0:DRP02[12]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[12]">GTX0:RXUSRCLK_DLY[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[13]">GTX0:DRP02[13]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[13]">GTX0:RXUSRCLK_DLY[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[14]">GTX0:DRP02[14]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[14]">GTX0:RXUSRCLK_DLY[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP02" title="GTX0:DRP02[15]">GTX0:DRP02[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RXUSRCLK_DLY" title="GTX0:RXUSRCLK_DLY[15]">GTX0:RXUSRCLK_DLY[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[0]">GTX0:BIAS_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[0]">GTX0:DRP03[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[1]">GTX0:BIAS_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[1]">GTX0:DRP03[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[2]">GTX0:BIAS_CFG[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[2]">GTX0:DRP03[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[3]">GTX0:BIAS_CFG[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[3]">GTX0:DRP03[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[4]">GTX0:BIAS_CFG[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[4]">GTX0:DRP03[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[5]">GTX0:BIAS_CFG[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[5]">GTX0:DRP03[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[6]">GTX0:BIAS_CFG[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[6]">GTX0:DRP03[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[7]">GTX0:BIAS_CFG[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[7]">GTX0:DRP03[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[8]">GTX0:BIAS_CFG[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[8]">GTX0:DRP03[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[9]">GTX0:BIAS_CFG[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[9]">GTX0:DRP03[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[10]">GTX0:BIAS_CFG[10]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[10]">GTX0:DRP03[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[11]">GTX0:BIAS_CFG[11]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[11]">GTX0:DRP03[11]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[12]">GTX0:BIAS_CFG[12]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[12]">GTX0:DRP03[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[13]">GTX0:BIAS_CFG[13]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[13]">GTX0:DRP03[13]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[14]">GTX0:BIAS_CFG[14]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[14]">GTX0:DRP03[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[15]">GTX0:BIAS_CFG[15]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP03" title="GTX0:DRP03[15]">GTX0:DRP03[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_1" title="GTX0:CHAN_BOND_SEQ_1_1[0]">GTX0:CHAN_BOND_SEQ_1_1[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[0]">GTX0:DRP04[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_1" title="GTX0:CHAN_BOND_SEQ_1_1[1]">GTX0:CHAN_BOND_SEQ_1_1[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[1]">GTX0:DRP04[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_1" title="GTX0:CHAN_BOND_SEQ_1_1[2]">GTX0:CHAN_BOND_SEQ_1_1[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[2]">GTX0:DRP04[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_1" title="GTX0:CHAN_BOND_SEQ_1_1[3]">GTX0:CHAN_BOND_SEQ_1_1[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[3]">GTX0:DRP04[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_1" title="GTX0:CHAN_BOND_SEQ_1_1[4]">GTX0:CHAN_BOND_SEQ_1_1[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[4]">GTX0:DRP04[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_1" title="GTX0:CHAN_BOND_SEQ_1_1[5]">GTX0:CHAN_BOND_SEQ_1_1[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[5]">GTX0:DRP04[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_1" title="GTX0:CHAN_BOND_SEQ_1_1[6]">GTX0:CHAN_BOND_SEQ_1_1[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[6]">GTX0:DRP04[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_1" title="GTX0:CHAN_BOND_SEQ_1_1[7]">GTX0:CHAN_BOND_SEQ_1_1[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[7]">GTX0:DRP04[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_1" title="GTX0:CHAN_BOND_SEQ_1_1[8]">GTX0:CHAN_BOND_SEQ_1_1[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[8]">GTX0:DRP04[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_1" title="GTX0:CHAN_BOND_SEQ_1_1[9]">GTX0:CHAN_BOND_SEQ_1_1[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[9]">GTX0:DRP04[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_ENABLE" title="GTX0:CHAN_BOND_SEQ_1_ENABLE[0]">GTX0:CHAN_BOND_SEQ_1_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[10]">GTX0:DRP04[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_ENABLE" title="GTX0:CHAN_BOND_SEQ_1_ENABLE[1]">GTX0:CHAN_BOND_SEQ_1_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[11]">GTX0:DRP04[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_ENABLE" title="GTX0:CHAN_BOND_SEQ_1_ENABLE[2]">GTX0:CHAN_BOND_SEQ_1_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[12]">GTX0:DRP04[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_ENABLE" title="GTX0:CHAN_BOND_SEQ_1_ENABLE[3]">GTX0:CHAN_BOND_SEQ_1_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[13]">GTX0:DRP04[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[14]">GTX0:DRP04[14]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_BUFFER_USE" title="GTX0:RX_BUFFER_USE">GTX0:RX_BUFFER_USE</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP04" title="GTX0:DRP04[15]">GTX0:DRP04[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_LOSS_OF_SYNC_FSM" title="GTX0:RX_LOSS_OF_SYNC_FSM">GTX0:RX_LOSS_OF_SYNC_FSM</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_2" title="GTX0:CHAN_BOND_SEQ_1_2[0]">GTX0:CHAN_BOND_SEQ_1_2[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[0]">GTX0:DRP05[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_2" title="GTX0:CHAN_BOND_SEQ_1_2[1]">GTX0:CHAN_BOND_SEQ_1_2[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[1]">GTX0:DRP05[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_2" title="GTX0:CHAN_BOND_SEQ_1_2[2]">GTX0:CHAN_BOND_SEQ_1_2[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[2]">GTX0:DRP05[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_2" title="GTX0:CHAN_BOND_SEQ_1_2[3]">GTX0:CHAN_BOND_SEQ_1_2[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[3]">GTX0:DRP05[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_2" title="GTX0:CHAN_BOND_SEQ_1_2[4]">GTX0:CHAN_BOND_SEQ_1_2[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[4]">GTX0:DRP05[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_2" title="GTX0:CHAN_BOND_SEQ_1_2[5]">GTX0:CHAN_BOND_SEQ_1_2[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[5]">GTX0:DRP05[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_2" title="GTX0:CHAN_BOND_SEQ_1_2[6]">GTX0:CHAN_BOND_SEQ_1_2[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[6]">GTX0:DRP05[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_2" title="GTX0:CHAN_BOND_SEQ_1_2[7]">GTX0:CHAN_BOND_SEQ_1_2[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[7]">GTX0:DRP05[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_2" title="GTX0:CHAN_BOND_SEQ_1_2[8]">GTX0:CHAN_BOND_SEQ_1_2[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[8]">GTX0:DRP05[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_2" title="GTX0:CHAN_BOND_SEQ_1_2[9]">GTX0:CHAN_BOND_SEQ_1_2[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[9]">GTX0:DRP05[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_1_MAX_SKEW" title="GTX0:CHAN_BOND_1_MAX_SKEW[0]">GTX0:CHAN_BOND_1_MAX_SKEW[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[10]">GTX0:DRP05[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_1_MAX_SKEW" title="GTX0:CHAN_BOND_1_MAX_SKEW[1]">GTX0:CHAN_BOND_1_MAX_SKEW[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[11]">GTX0:DRP05[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_1_MAX_SKEW" title="GTX0:CHAN_BOND_1_MAX_SKEW[2]">GTX0:CHAN_BOND_1_MAX_SKEW[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[12]">GTX0:DRP05[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_1_MAX_SKEW" title="GTX0:CHAN_BOND_1_MAX_SKEW[3]">GTX0:CHAN_BOND_1_MAX_SKEW[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[13]">GTX0:DRP05[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[14]">GTX0:DRP05[14]</a><br><a href="#bits-xc6v-GTX-GTX0:INV.RXUSRCLK" title="~GTX0:INV.RXUSRCLK">~GTX0:INV.RXUSRCLK</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP05" title="GTX0:DRP05[15]">GTX0:DRP05[15]</a><br><a href="#bits-xc6v-GTX-GTX0:INV.RXUSRCLK2" title="~GTX0:INV.RXUSRCLK2">~GTX0:INV.RXUSRCLK2</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_3" title="GTX0:CHAN_BOND_SEQ_1_3[0]">GTX0:CHAN_BOND_SEQ_1_3[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[0]">GTX0:DRP06[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_3" title="GTX0:CHAN_BOND_SEQ_1_3[1]">GTX0:CHAN_BOND_SEQ_1_3[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[1]">GTX0:DRP06[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_3" title="GTX0:CHAN_BOND_SEQ_1_3[2]">GTX0:CHAN_BOND_SEQ_1_3[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[2]">GTX0:DRP06[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_3" title="GTX0:CHAN_BOND_SEQ_1_3[3]">GTX0:CHAN_BOND_SEQ_1_3[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[3]">GTX0:DRP06[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_3" title="GTX0:CHAN_BOND_SEQ_1_3[4]">GTX0:CHAN_BOND_SEQ_1_3[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[4]">GTX0:DRP06[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_3" title="GTX0:CHAN_BOND_SEQ_1_3[5]">GTX0:CHAN_BOND_SEQ_1_3[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[5]">GTX0:DRP06[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_3" title="GTX0:CHAN_BOND_SEQ_1_3[6]">GTX0:CHAN_BOND_SEQ_1_3[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[6]">GTX0:DRP06[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_3" title="GTX0:CHAN_BOND_SEQ_1_3[7]">GTX0:CHAN_BOND_SEQ_1_3[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[7]">GTX0:DRP06[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_3" title="GTX0:CHAN_BOND_SEQ_1_3[8]">GTX0:CHAN_BOND_SEQ_1_3[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[8]">GTX0:DRP06[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_3" title="GTX0:CHAN_BOND_SEQ_1_3[9]">GTX0:CHAN_BOND_SEQ_1_3[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[9]">GTX0:DRP06[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[10]">GTX0:DRP06[10]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_LOS_THRESHOLD" title="GTX0:RX_LOS_THRESHOLD[0]">GTX0:RX_LOS_THRESHOLD[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[11]">GTX0:DRP06[11]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_LOS_THRESHOLD" title="GTX0:RX_LOS_THRESHOLD[1]">GTX0:RX_LOS_THRESHOLD[1]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[12]">GTX0:DRP06[12]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_LOS_THRESHOLD" title="GTX0:RX_LOS_THRESHOLD[2]">GTX0:RX_LOS_THRESHOLD[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[13]">GTX0:DRP06[13]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_LOS_INVALID_INCR" title="GTX0:RX_LOS_INVALID_INCR[0]">GTX0:RX_LOS_INVALID_INCR[0]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[14]">GTX0:DRP06[14]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_LOS_INVALID_INCR" title="GTX0:RX_LOS_INVALID_INCR[1]">GTX0:RX_LOS_INVALID_INCR[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP06" title="GTX0:DRP06[15]">GTX0:DRP06[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_LOS_INVALID_INCR" title="GTX0:RX_LOS_INVALID_INCR[2]">GTX0:RX_LOS_INVALID_INCR[2]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_4" title="GTX0:CHAN_BOND_SEQ_1_4[0]">GTX0:CHAN_BOND_SEQ_1_4[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[0]">GTX0:DRP07[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_4" title="GTX0:CHAN_BOND_SEQ_1_4[1]">GTX0:CHAN_BOND_SEQ_1_4[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[1]">GTX0:DRP07[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_4" title="GTX0:CHAN_BOND_SEQ_1_4[2]">GTX0:CHAN_BOND_SEQ_1_4[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[2]">GTX0:DRP07[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_4" title="GTX0:CHAN_BOND_SEQ_1_4[3]">GTX0:CHAN_BOND_SEQ_1_4[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[3]">GTX0:DRP07[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_4" title="GTX0:CHAN_BOND_SEQ_1_4[4]">GTX0:CHAN_BOND_SEQ_1_4[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[4]">GTX0:DRP07[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_4" title="GTX0:CHAN_BOND_SEQ_1_4[5]">GTX0:CHAN_BOND_SEQ_1_4[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[5]">GTX0:DRP07[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_4" title="GTX0:CHAN_BOND_SEQ_1_4[6]">GTX0:CHAN_BOND_SEQ_1_4[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[6]">GTX0:DRP07[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_4" title="GTX0:CHAN_BOND_SEQ_1_4[7]">GTX0:CHAN_BOND_SEQ_1_4[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[7]">GTX0:DRP07[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_4" title="GTX0:CHAN_BOND_SEQ_1_4[8]">GTX0:CHAN_BOND_SEQ_1_4[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[8]">GTX0:DRP07[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_4" title="GTX0:CHAN_BOND_SEQ_1_4[9]">GTX0:CHAN_BOND_SEQ_1_4[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[9]">GTX0:DRP07[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_LEN" title="GTX0:CHAN_BOND_SEQ_LEN[0]">GTX0:CHAN_BOND_SEQ_LEN[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[10]">GTX0:DRP07[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_LEN" title="GTX0:CHAN_BOND_SEQ_LEN[1]">GTX0:CHAN_BOND_SEQ_LEN[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[11]">GTX0:DRP07[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[12]">GTX0:DRP07[12]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_IDLE_LO_CNT" title="GTX0:RX_IDLE_LO_CNT[0]">GTX0:RX_IDLE_LO_CNT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[13]">GTX0:DRP07[13]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_IDLE_LO_CNT" title="GTX0:RX_IDLE_LO_CNT[1]">GTX0:RX_IDLE_LO_CNT[1]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[14]">GTX0:DRP07[14]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_IDLE_LO_CNT" title="GTX0:RX_IDLE_LO_CNT[2]">GTX0:RX_IDLE_LO_CNT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP07" title="GTX0:DRP07[15]">GTX0:DRP07[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_IDLE_LO_CNT" title="GTX0:RX_IDLE_LO_CNT[3]">GTX0:RX_IDLE_LO_CNT[3]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 1</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_1" title="GTX0:CHAN_BOND_SEQ_2_1[0]">GTX0:CHAN_BOND_SEQ_2_1[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[0]">GTX0:DRP08[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_1" title="GTX0:CHAN_BOND_SEQ_2_1[1]">GTX0:CHAN_BOND_SEQ_2_1[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[1]">GTX0:DRP08[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_1" title="GTX0:CHAN_BOND_SEQ_2_1[2]">GTX0:CHAN_BOND_SEQ_2_1[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[2]">GTX0:DRP08[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_1" title="GTX0:CHAN_BOND_SEQ_2_1[3]">GTX0:CHAN_BOND_SEQ_2_1[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[3]">GTX0:DRP08[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_1" title="GTX0:CHAN_BOND_SEQ_2_1[4]">GTX0:CHAN_BOND_SEQ_2_1[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[4]">GTX0:DRP08[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_1" title="GTX0:CHAN_BOND_SEQ_2_1[5]">GTX0:CHAN_BOND_SEQ_2_1[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[5]">GTX0:DRP08[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_1" title="GTX0:CHAN_BOND_SEQ_2_1[6]">GTX0:CHAN_BOND_SEQ_2_1[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[6]">GTX0:DRP08[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_1" title="GTX0:CHAN_BOND_SEQ_2_1[7]">GTX0:CHAN_BOND_SEQ_2_1[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[7]">GTX0:DRP08[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_1" title="GTX0:CHAN_BOND_SEQ_2_1[8]">GTX0:CHAN_BOND_SEQ_2_1[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[8]">GTX0:DRP08[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_1" title="GTX0:CHAN_BOND_SEQ_2_1[9]">GTX0:CHAN_BOND_SEQ_2_1[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[9]">GTX0:DRP08[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_ENABLE" title="GTX0:CHAN_BOND_SEQ_2_ENABLE[0]">GTX0:CHAN_BOND_SEQ_2_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[10]">GTX0:DRP08[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_ENABLE" title="GTX0:CHAN_BOND_SEQ_2_ENABLE[1]">GTX0:CHAN_BOND_SEQ_2_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[11]">GTX0:DRP08[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_ENABLE" title="GTX0:CHAN_BOND_SEQ_2_ENABLE[2]">GTX0:CHAN_BOND_SEQ_2_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[12]">GTX0:DRP08[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_ENABLE" title="GTX0:CHAN_BOND_SEQ_2_ENABLE[3]">GTX0:CHAN_BOND_SEQ_2_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[13]">GTX0:DRP08[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[14]">GTX0:DRP08[14]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EN_REALIGN_RESET_BUF" title="GTX0:RX_EN_REALIGN_RESET_BUF">GTX0:RX_EN_REALIGN_RESET_BUF</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP08" title="GTX0:DRP08[15]">GTX0:DRP08[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EN_RATE_RESET_BUF" title="GTX0:RX_EN_RATE_RESET_BUF">GTX0:RX_EN_RATE_RESET_BUF</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_2" title="GTX0:CHAN_BOND_SEQ_2_2[0]">GTX0:CHAN_BOND_SEQ_2_2[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[0]">GTX0:DRP09[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_2" title="GTX0:CHAN_BOND_SEQ_2_2[1]">GTX0:CHAN_BOND_SEQ_2_2[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[1]">GTX0:DRP09[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_2" title="GTX0:CHAN_BOND_SEQ_2_2[2]">GTX0:CHAN_BOND_SEQ_2_2[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[2]">GTX0:DRP09[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_2" title="GTX0:CHAN_BOND_SEQ_2_2[3]">GTX0:CHAN_BOND_SEQ_2_2[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[3]">GTX0:DRP09[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_2" title="GTX0:CHAN_BOND_SEQ_2_2[4]">GTX0:CHAN_BOND_SEQ_2_2[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[4]">GTX0:DRP09[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_2" title="GTX0:CHAN_BOND_SEQ_2_2[5]">GTX0:CHAN_BOND_SEQ_2_2[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[5]">GTX0:DRP09[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_2" title="GTX0:CHAN_BOND_SEQ_2_2[6]">GTX0:CHAN_BOND_SEQ_2_2[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[6]">GTX0:DRP09[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_2" title="GTX0:CHAN_BOND_SEQ_2_2[7]">GTX0:CHAN_BOND_SEQ_2_2[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[7]">GTX0:DRP09[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_2" title="GTX0:CHAN_BOND_SEQ_2_2[8]">GTX0:CHAN_BOND_SEQ_2_2[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[8]">GTX0:DRP09[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_2" title="GTX0:CHAN_BOND_SEQ_2_2[9]">GTX0:CHAN_BOND_SEQ_2_2[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[9]">GTX0:DRP09[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_2_MAX_SKEW" title="GTX0:CHAN_BOND_2_MAX_SKEW[0]">GTX0:CHAN_BOND_2_MAX_SKEW[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[10]">GTX0:DRP09[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_2_MAX_SKEW" title="GTX0:CHAN_BOND_2_MAX_SKEW[1]">GTX0:CHAN_BOND_2_MAX_SKEW[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[11]">GTX0:DRP09[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_2_MAX_SKEW" title="GTX0:CHAN_BOND_2_MAX_SKEW[2]">GTX0:CHAN_BOND_2_MAX_SKEW[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[12]">GTX0:DRP09[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_2_MAX_SKEW" title="GTX0:CHAN_BOND_2_MAX_SKEW[3]">GTX0:CHAN_BOND_2_MAX_SKEW[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[13]">GTX0:DRP09[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_KEEP_ALIGN" title="GTX0:CHAN_BOND_KEEP_ALIGN">GTX0:CHAN_BOND_KEEP_ALIGN</a><br><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[14]">GTX0:DRP09[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP09" title="GTX0:DRP09[15]">GTX0:DRP09[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EN_MODE_RESET_BUF" title="GTX0:RX_EN_MODE_RESET_BUF">GTX0:RX_EN_MODE_RESET_BUF</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_3" title="GTX0:CHAN_BOND_SEQ_2_3[0]">GTX0:CHAN_BOND_SEQ_2_3[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[0]">GTX0:DRP0A[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_3" title="GTX0:CHAN_BOND_SEQ_2_3[1]">GTX0:CHAN_BOND_SEQ_2_3[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[1]">GTX0:DRP0A[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_3" title="GTX0:CHAN_BOND_SEQ_2_3[2]">GTX0:CHAN_BOND_SEQ_2_3[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[2]">GTX0:DRP0A[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_3" title="GTX0:CHAN_BOND_SEQ_2_3[3]">GTX0:CHAN_BOND_SEQ_2_3[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[3]">GTX0:DRP0A[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_3" title="GTX0:CHAN_BOND_SEQ_2_3[4]">GTX0:CHAN_BOND_SEQ_2_3[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[4]">GTX0:DRP0A[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_3" title="GTX0:CHAN_BOND_SEQ_2_3[5]">GTX0:CHAN_BOND_SEQ_2_3[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[5]">GTX0:DRP0A[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_3" title="GTX0:CHAN_BOND_SEQ_2_3[6]">GTX0:CHAN_BOND_SEQ_2_3[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[6]">GTX0:DRP0A[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_3" title="GTX0:CHAN_BOND_SEQ_2_3[7]">GTX0:CHAN_BOND_SEQ_2_3[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[7]">GTX0:DRP0A[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_3" title="GTX0:CHAN_BOND_SEQ_2_3[8]">GTX0:CHAN_BOND_SEQ_2_3[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[8]">GTX0:DRP0A[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_3" title="GTX0:CHAN_BOND_SEQ_2_3[9]">GTX0:CHAN_BOND_SEQ_2_3[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[9]">GTX0:DRP0A[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_CFG" title="GTX0:CHAN_BOND_SEQ_2_CFG[0]">GTX0:CHAN_BOND_SEQ_2_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[10]">GTX0:DRP0A[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_CFG" title="GTX0:CHAN_BOND_SEQ_2_CFG[1]">GTX0:CHAN_BOND_SEQ_2_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[11]">GTX0:DRP0A[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_CFG" title="GTX0:CHAN_BOND_SEQ_2_CFG[2]">GTX0:CHAN_BOND_SEQ_2_CFG[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[12]">GTX0:DRP0A[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_CFG" title="GTX0:CHAN_BOND_SEQ_2_CFG[3]">GTX0:CHAN_BOND_SEQ_2_CFG[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[13]">GTX0:DRP0A[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_USE" title="GTX0:CHAN_BOND_SEQ_2_USE">GTX0:CHAN_BOND_SEQ_2_USE</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[14]">GTX0:DRP0A[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP0A" title="GTX0:DRP0A[15]">GTX0:DRP0A[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EN_IDLE_RESET_PH" title="GTX0:RX_EN_IDLE_RESET_PH">GTX0:RX_EN_IDLE_RESET_PH</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_4" title="GTX0:CHAN_BOND_SEQ_2_4[0]">GTX0:CHAN_BOND_SEQ_2_4[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[0]">GTX0:DRP0B[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_4" title="GTX0:CHAN_BOND_SEQ_2_4[1]">GTX0:CHAN_BOND_SEQ_2_4[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[1]">GTX0:DRP0B[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_4" title="GTX0:CHAN_BOND_SEQ_2_4[2]">GTX0:CHAN_BOND_SEQ_2_4[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[2]">GTX0:DRP0B[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_4" title="GTX0:CHAN_BOND_SEQ_2_4[3]">GTX0:CHAN_BOND_SEQ_2_4[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[3]">GTX0:DRP0B[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_4" title="GTX0:CHAN_BOND_SEQ_2_4[4]">GTX0:CHAN_BOND_SEQ_2_4[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[4]">GTX0:DRP0B[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_4" title="GTX0:CHAN_BOND_SEQ_2_4[5]">GTX0:CHAN_BOND_SEQ_2_4[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[5]">GTX0:DRP0B[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_4" title="GTX0:CHAN_BOND_SEQ_2_4[6]">GTX0:CHAN_BOND_SEQ_2_4[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[6]">GTX0:DRP0B[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_4" title="GTX0:CHAN_BOND_SEQ_2_4[7]">GTX0:CHAN_BOND_SEQ_2_4[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[7]">GTX0:DRP0B[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_4" title="GTX0:CHAN_BOND_SEQ_2_4[8]">GTX0:CHAN_BOND_SEQ_2_4[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[8]">GTX0:DRP0B[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_4" title="GTX0:CHAN_BOND_SEQ_2_4[9]">GTX0:CHAN_BOND_SEQ_2_4[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[9]">GTX0:DRP0B[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[10]">GTX0:DRP0B[10]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EN_IDLE_RESET_BUF" title="GTX0:RX_EN_IDLE_RESET_BUF">GTX0:RX_EN_IDLE_RESET_BUF</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[11]">GTX0:DRP0B[11]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_XCLK_SEL" title="GTX0:RX_XCLK_SEL">GTX0:RX_XCLK_SEL</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[12]">GTX0:DRP0B[12]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_IDLE_HI_CNT" title="GTX0:RX_IDLE_HI_CNT[0]">GTX0:RX_IDLE_HI_CNT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[13]">GTX0:DRP0B[13]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_IDLE_HI_CNT" title="GTX0:RX_IDLE_HI_CNT[1]">GTX0:RX_IDLE_HI_CNT[1]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[14]">GTX0:DRP0B[14]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_IDLE_HI_CNT" title="GTX0:RX_IDLE_HI_CNT[2]">GTX0:RX_IDLE_HI_CNT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP0B" title="GTX0:DRP0B[15]">GTX0:DRP0B[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_IDLE_HI_CNT" title="GTX0:RX_IDLE_HI_CNT[3]">GTX0:RX_IDLE_HI_CNT[3]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[0]">GTX0:DRP0C[0]</a><br><a href="#bits-xc6v-GTX-GTX0:RXBUF_OVFL_THRESH" title="GTX0:RXBUF_OVFL_THRESH[0]">GTX0:RXBUF_OVFL_THRESH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[1]">GTX0:DRP0C[1]</a><br><a href="#bits-xc6v-GTX-GTX0:RXBUF_OVFL_THRESH" title="GTX0:RXBUF_OVFL_THRESH[1]">GTX0:RXBUF_OVFL_THRESH[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[2]">GTX0:DRP0C[2]</a><br><a href="#bits-xc6v-GTX-GTX0:RXBUF_OVFL_THRESH" title="GTX0:RXBUF_OVFL_THRESH[2]">GTX0:RXBUF_OVFL_THRESH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[3]">GTX0:DRP0C[3]</a><br><a href="#bits-xc6v-GTX-GTX0:RXBUF_OVFL_THRESH" title="GTX0:RXBUF_OVFL_THRESH[3]">GTX0:RXBUF_OVFL_THRESH[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[4]">GTX0:DRP0C[4]</a><br><a href="#bits-xc6v-GTX-GTX0:RXBUF_OVFL_THRESH" title="GTX0:RXBUF_OVFL_THRESH[4]">GTX0:RXBUF_OVFL_THRESH[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[5]">GTX0:DRP0C[5]</a><br><a href="#bits-xc6v-GTX-GTX0:RXBUF_OVFL_THRESH" title="GTX0:RXBUF_OVFL_THRESH[5]">GTX0:RXBUF_OVFL_THRESH[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[6]">GTX0:DRP0C[6]</a><br><a href="#bits-xc6v-GTX-GTX0:RXBUF_UDFL_THRESH" title="GTX0:RXBUF_UDFL_THRESH[0]">GTX0:RXBUF_UDFL_THRESH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[7]">GTX0:DRP0C[7]</a><br><a href="#bits-xc6v-GTX-GTX0:RXBUF_UDFL_THRESH" title="GTX0:RXBUF_UDFL_THRESH[1]">GTX0:RXBUF_UDFL_THRESH[1]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[8]">GTX0:DRP0C[8]</a><br><a href="#bits-xc6v-GTX-GTX0:RXBUF_UDFL_THRESH" title="GTX0:RXBUF_UDFL_THRESH[2]">GTX0:RXBUF_UDFL_THRESH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[9]">GTX0:DRP0C[9]</a><br><a href="#bits-xc6v-GTX-GTX0:RXBUF_UDFL_THRESH" title="GTX0:RXBUF_UDFL_THRESH[3]">GTX0:RXBUF_UDFL_THRESH[3]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[10]">GTX0:DRP0C[10]</a><br><a href="#bits-xc6v-GTX-GTX0:RXBUF_UDFL_THRESH" title="GTX0:RXBUF_UDFL_THRESH[4]">GTX0:RXBUF_UDFL_THRESH[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[11]">GTX0:DRP0C[11]</a><br><a href="#bits-xc6v-GTX-GTX0:RXBUF_UDFL_THRESH" title="GTX0:RXBUF_UDFL_THRESH[5]">GTX0:RXBUF_UDFL_THRESH[5]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[12]">GTX0:DRP0C[12]</a><br><a href="#bits-xc6v-GTX-GTX0:RXBUF_OVRD_THRESH" title="GTX0:RXBUF_OVRD_THRESH">GTX0:RXBUF_OVRD_THRESH</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[13]">GTX0:DRP0C[13]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_FIFO_ADDR_MODE" title="GTX0:RX_FIFO_ADDR_MODE">GTX0:RX_FIFO_ADDR_MODE</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[14]">GTX0:DRP0C[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP0C" title="GTX0:DRP0C[15]">GTX0:DRP0C[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_1" title="GTX0:CLK_COR_SEQ_1_1[0]">GTX0:CLK_COR_SEQ_1_1[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[0]">GTX0:DRP0D[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_1" title="GTX0:CLK_COR_SEQ_1_1[1]">GTX0:CLK_COR_SEQ_1_1[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[1]">GTX0:DRP0D[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_1" title="GTX0:CLK_COR_SEQ_1_1[2]">GTX0:CLK_COR_SEQ_1_1[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[2]">GTX0:DRP0D[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_1" title="GTX0:CLK_COR_SEQ_1_1[3]">GTX0:CLK_COR_SEQ_1_1[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[3]">GTX0:DRP0D[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_1" title="GTX0:CLK_COR_SEQ_1_1[4]">GTX0:CLK_COR_SEQ_1_1[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[4]">GTX0:DRP0D[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_1" title="GTX0:CLK_COR_SEQ_1_1[5]">GTX0:CLK_COR_SEQ_1_1[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[5]">GTX0:DRP0D[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_1" title="GTX0:CLK_COR_SEQ_1_1[6]">GTX0:CLK_COR_SEQ_1_1[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[6]">GTX0:DRP0D[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_1" title="GTX0:CLK_COR_SEQ_1_1[7]">GTX0:CLK_COR_SEQ_1_1[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[7]">GTX0:DRP0D[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_1" title="GTX0:CLK_COR_SEQ_1_1[8]">GTX0:CLK_COR_SEQ_1_1[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[8]">GTX0:DRP0D[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_1" title="GTX0:CLK_COR_SEQ_1_1[9]">GTX0:CLK_COR_SEQ_1_1[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[9]">GTX0:DRP0D[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_ENABLE" title="GTX0:CLK_COR_SEQ_1_ENABLE[0]">GTX0:CLK_COR_SEQ_1_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[10]">GTX0:DRP0D[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_ENABLE" title="GTX0:CLK_COR_SEQ_1_ENABLE[1]">GTX0:CLK_COR_SEQ_1_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[11]">GTX0:DRP0D[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_ENABLE" title="GTX0:CLK_COR_SEQ_1_ENABLE[2]">GTX0:CLK_COR_SEQ_1_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[12]">GTX0:DRP0D[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_ENABLE" title="GTX0:CLK_COR_SEQ_1_ENABLE[3]">GTX0:CLK_COR_SEQ_1_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[13]">GTX0:DRP0D[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_CORRECT_USE" title="GTX0:CLK_CORRECT_USE">GTX0:CLK_CORRECT_USE</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[14]">GTX0:DRP0D[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_PRECEDENCE" title="GTX0:CLK_COR_PRECEDENCE">GTX0:CLK_COR_PRECEDENCE</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0D" title="GTX0:DRP0D[15]">GTX0:DRP0D[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_2" title="GTX0:CLK_COR_SEQ_1_2[0]">GTX0:CLK_COR_SEQ_1_2[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[0]">GTX0:DRP0E[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_2" title="GTX0:CLK_COR_SEQ_1_2[1]">GTX0:CLK_COR_SEQ_1_2[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[1]">GTX0:DRP0E[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_2" title="GTX0:CLK_COR_SEQ_1_2[2]">GTX0:CLK_COR_SEQ_1_2[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[2]">GTX0:DRP0E[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_2" title="GTX0:CLK_COR_SEQ_1_2[3]">GTX0:CLK_COR_SEQ_1_2[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[3]">GTX0:DRP0E[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_2" title="GTX0:CLK_COR_SEQ_1_2[4]">GTX0:CLK_COR_SEQ_1_2[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[4]">GTX0:DRP0E[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_2" title="GTX0:CLK_COR_SEQ_1_2[5]">GTX0:CLK_COR_SEQ_1_2[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[5]">GTX0:DRP0E[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_2" title="GTX0:CLK_COR_SEQ_1_2[6]">GTX0:CLK_COR_SEQ_1_2[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[6]">GTX0:DRP0E[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_2" title="GTX0:CLK_COR_SEQ_1_2[7]">GTX0:CLK_COR_SEQ_1_2[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[7]">GTX0:DRP0E[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_2" title="GTX0:CLK_COR_SEQ_1_2[8]">GTX0:CLK_COR_SEQ_1_2[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[8]">GTX0:DRP0E[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_2" title="GTX0:CLK_COR_SEQ_1_2[9]">GTX0:CLK_COR_SEQ_1_2[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[9]">GTX0:DRP0E[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_REPEAT_WAIT" title="GTX0:CLK_COR_REPEAT_WAIT[0]">GTX0:CLK_COR_REPEAT_WAIT[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[10]">GTX0:DRP0E[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_REPEAT_WAIT" title="GTX0:CLK_COR_REPEAT_WAIT[1]">GTX0:CLK_COR_REPEAT_WAIT[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[11]">GTX0:DRP0E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_REPEAT_WAIT" title="GTX0:CLK_COR_REPEAT_WAIT[2]">GTX0:CLK_COR_REPEAT_WAIT[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[12]">GTX0:DRP0E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_REPEAT_WAIT" title="GTX0:CLK_COR_REPEAT_WAIT[3]">GTX0:CLK_COR_REPEAT_WAIT[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[13]">GTX0:DRP0E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_REPEAT_WAIT" title="GTX0:CLK_COR_REPEAT_WAIT[4]">GTX0:CLK_COR_REPEAT_WAIT[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[14]">GTX0:DRP0E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_KEEP_IDLE" title="GTX0:CLK_COR_KEEP_IDLE">GTX0:CLK_COR_KEEP_IDLE</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0E" title="GTX0:DRP0E[15]">GTX0:DRP0E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_3" title="GTX0:CLK_COR_SEQ_1_3[0]">GTX0:CLK_COR_SEQ_1_3[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[0]">GTX0:DRP0F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_3" title="GTX0:CLK_COR_SEQ_1_3[1]">GTX0:CLK_COR_SEQ_1_3[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[1]">GTX0:DRP0F[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_3" title="GTX0:CLK_COR_SEQ_1_3[2]">GTX0:CLK_COR_SEQ_1_3[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[2]">GTX0:DRP0F[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_3" title="GTX0:CLK_COR_SEQ_1_3[3]">GTX0:CLK_COR_SEQ_1_3[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[3]">GTX0:DRP0F[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_3" title="GTX0:CLK_COR_SEQ_1_3[4]">GTX0:CLK_COR_SEQ_1_3[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[4]">GTX0:DRP0F[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_3" title="GTX0:CLK_COR_SEQ_1_3[5]">GTX0:CLK_COR_SEQ_1_3[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[5]">GTX0:DRP0F[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_3" title="GTX0:CLK_COR_SEQ_1_3[6]">GTX0:CLK_COR_SEQ_1_3[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[6]">GTX0:DRP0F[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_3" title="GTX0:CLK_COR_SEQ_1_3[7]">GTX0:CLK_COR_SEQ_1_3[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[7]">GTX0:DRP0F[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_3" title="GTX0:CLK_COR_SEQ_1_3[8]">GTX0:CLK_COR_SEQ_1_3[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[8]">GTX0:DRP0F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_3" title="GTX0:CLK_COR_SEQ_1_3[9]">GTX0:CLK_COR_SEQ_1_3[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[9]">GTX0:DRP0F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_MIN_LAT" title="GTX0:CLK_COR_MIN_LAT[0]">GTX0:CLK_COR_MIN_LAT[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[10]">GTX0:DRP0F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_MIN_LAT" title="GTX0:CLK_COR_MIN_LAT[1]">GTX0:CLK_COR_MIN_LAT[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[11]">GTX0:DRP0F[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_MIN_LAT" title="GTX0:CLK_COR_MIN_LAT[2]">GTX0:CLK_COR_MIN_LAT[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[12]">GTX0:DRP0F[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_MIN_LAT" title="GTX0:CLK_COR_MIN_LAT[3]">GTX0:CLK_COR_MIN_LAT[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[13]">GTX0:DRP0F[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_MIN_LAT" title="GTX0:CLK_COR_MIN_LAT[4]">GTX0:CLK_COR_MIN_LAT[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[14]">GTX0:DRP0F[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_MIN_LAT" title="GTX0:CLK_COR_MIN_LAT[5]">GTX0:CLK_COR_MIN_LAT[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP0F" title="GTX0:DRP0F[15]">GTX0:DRP0F[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 2</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_4" title="GTX0:CLK_COR_SEQ_1_4[0]">GTX0:CLK_COR_SEQ_1_4[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[0]">GTX0:DRP10[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_4" title="GTX0:CLK_COR_SEQ_1_4[1]">GTX0:CLK_COR_SEQ_1_4[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[1]">GTX0:DRP10[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_4" title="GTX0:CLK_COR_SEQ_1_4[2]">GTX0:CLK_COR_SEQ_1_4[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[2]">GTX0:DRP10[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_4" title="GTX0:CLK_COR_SEQ_1_4[3]">GTX0:CLK_COR_SEQ_1_4[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[3]">GTX0:DRP10[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_4" title="GTX0:CLK_COR_SEQ_1_4[4]">GTX0:CLK_COR_SEQ_1_4[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[4]">GTX0:DRP10[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_4" title="GTX0:CLK_COR_SEQ_1_4[5]">GTX0:CLK_COR_SEQ_1_4[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[5]">GTX0:DRP10[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_4" title="GTX0:CLK_COR_SEQ_1_4[6]">GTX0:CLK_COR_SEQ_1_4[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[6]">GTX0:DRP10[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_4" title="GTX0:CLK_COR_SEQ_1_4[7]">GTX0:CLK_COR_SEQ_1_4[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[7]">GTX0:DRP10[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_4" title="GTX0:CLK_COR_SEQ_1_4[8]">GTX0:CLK_COR_SEQ_1_4[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[8]">GTX0:DRP10[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_4" title="GTX0:CLK_COR_SEQ_1_4[9]">GTX0:CLK_COR_SEQ_1_4[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[9]">GTX0:DRP10[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_MAX_LAT" title="GTX0:CLK_COR_MAX_LAT[0]">GTX0:CLK_COR_MAX_LAT[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[10]">GTX0:DRP10[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_MAX_LAT" title="GTX0:CLK_COR_MAX_LAT[1]">GTX0:CLK_COR_MAX_LAT[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[11]">GTX0:DRP10[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_MAX_LAT" title="GTX0:CLK_COR_MAX_LAT[2]">GTX0:CLK_COR_MAX_LAT[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[12]">GTX0:DRP10[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_MAX_LAT" title="GTX0:CLK_COR_MAX_LAT[3]">GTX0:CLK_COR_MAX_LAT[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[13]">GTX0:DRP10[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_MAX_LAT" title="GTX0:CLK_COR_MAX_LAT[4]">GTX0:CLK_COR_MAX_LAT[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[14]">GTX0:DRP10[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_MAX_LAT" title="GTX0:CLK_COR_MAX_LAT[5]">GTX0:CLK_COR_MAX_LAT[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP10" title="GTX0:DRP10[15]">GTX0:DRP10[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_1" title="GTX0:CLK_COR_SEQ_2_1[0]">GTX0:CLK_COR_SEQ_2_1[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[0]">GTX0:DRP11[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_1" title="GTX0:CLK_COR_SEQ_2_1[1]">GTX0:CLK_COR_SEQ_2_1[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[1]">GTX0:DRP11[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_1" title="GTX0:CLK_COR_SEQ_2_1[2]">GTX0:CLK_COR_SEQ_2_1[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[2]">GTX0:DRP11[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_1" title="GTX0:CLK_COR_SEQ_2_1[3]">GTX0:CLK_COR_SEQ_2_1[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[3]">GTX0:DRP11[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_1" title="GTX0:CLK_COR_SEQ_2_1[4]">GTX0:CLK_COR_SEQ_2_1[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[4]">GTX0:DRP11[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_1" title="GTX0:CLK_COR_SEQ_2_1[5]">GTX0:CLK_COR_SEQ_2_1[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[5]">GTX0:DRP11[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_1" title="GTX0:CLK_COR_SEQ_2_1[6]">GTX0:CLK_COR_SEQ_2_1[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[6]">GTX0:DRP11[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_1" title="GTX0:CLK_COR_SEQ_2_1[7]">GTX0:CLK_COR_SEQ_2_1[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[7]">GTX0:DRP11[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_1" title="GTX0:CLK_COR_SEQ_2_1[8]">GTX0:CLK_COR_SEQ_2_1[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[8]">GTX0:DRP11[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_1" title="GTX0:CLK_COR_SEQ_2_1[9]">GTX0:CLK_COR_SEQ_2_1[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[9]">GTX0:DRP11[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_ENABLE" title="GTX0:CLK_COR_SEQ_2_ENABLE[0]">GTX0:CLK_COR_SEQ_2_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[10]">GTX0:DRP11[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_ENABLE" title="GTX0:CLK_COR_SEQ_2_ENABLE[1]">GTX0:CLK_COR_SEQ_2_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[11]">GTX0:DRP11[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_ENABLE" title="GTX0:CLK_COR_SEQ_2_ENABLE[2]">GTX0:CLK_COR_SEQ_2_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[12]">GTX0:DRP11[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_ENABLE" title="GTX0:CLK_COR_SEQ_2_ENABLE[3]">GTX0:CLK_COR_SEQ_2_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[13]">GTX0:DRP11[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_USE" title="GTX0:CLK_COR_SEQ_2_USE">GTX0:CLK_COR_SEQ_2_USE</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[14]">GTX0:DRP11[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_INSERT_IDLE_FLAG" title="GTX0:CLK_COR_INSERT_IDLE_FLAG">GTX0:CLK_COR_INSERT_IDLE_FLAG</a><br><a href="#bits-xc6v-GTX-GTX0:DRP11" title="GTX0:DRP11[15]">GTX0:DRP11[15]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_2" title="GTX0:CLK_COR_SEQ_2_2[0]">GTX0:CLK_COR_SEQ_2_2[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[0]">GTX0:DRP12[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_2" title="GTX0:CLK_COR_SEQ_2_2[1]">GTX0:CLK_COR_SEQ_2_2[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[1]">GTX0:DRP12[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_2" title="GTX0:CLK_COR_SEQ_2_2[2]">GTX0:CLK_COR_SEQ_2_2[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[2]">GTX0:DRP12[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_2" title="GTX0:CLK_COR_SEQ_2_2[3]">GTX0:CLK_COR_SEQ_2_2[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[3]">GTX0:DRP12[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_2" title="GTX0:CLK_COR_SEQ_2_2[4]">GTX0:CLK_COR_SEQ_2_2[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[4]">GTX0:DRP12[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_2" title="GTX0:CLK_COR_SEQ_2_2[5]">GTX0:CLK_COR_SEQ_2_2[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[5]">GTX0:DRP12[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_2" title="GTX0:CLK_COR_SEQ_2_2[6]">GTX0:CLK_COR_SEQ_2_2[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[6]">GTX0:DRP12[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_2" title="GTX0:CLK_COR_SEQ_2_2[7]">GTX0:CLK_COR_SEQ_2_2[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[7]">GTX0:DRP12[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_2" title="GTX0:CLK_COR_SEQ_2_2[8]">GTX0:CLK_COR_SEQ_2_2[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[8]">GTX0:DRP12[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_2" title="GTX0:CLK_COR_SEQ_2_2[9]">GTX0:CLK_COR_SEQ_2_2[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[9]">GTX0:DRP12[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_ADJ_LEN" title="GTX0:CLK_COR_ADJ_LEN[0]">GTX0:CLK_COR_ADJ_LEN[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[10]">GTX0:DRP12[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_ADJ_LEN" title="GTX0:CLK_COR_ADJ_LEN[1]">GTX0:CLK_COR_ADJ_LEN[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[11]">GTX0:DRP12[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[12]">GTX0:DRP12[12]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_SLIDE_MODE" title="GTX0:RX_SLIDE_MODE[0]">GTX0:RX_SLIDE_MODE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[13]">GTX0:DRP12[13]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_SLIDE_MODE" title="GTX0:RX_SLIDE_MODE[1]">GTX0:RX_SLIDE_MODE[1]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[14]">GTX0:DRP12[14]</a><br><a href="#bits-xc6v-GTX-GTX0:SHOW_REALIGN_COMMA" title="GTX0:SHOW_REALIGN_COMMA">GTX0:SHOW_REALIGN_COMMA</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP12" title="GTX0:DRP12[15]">GTX0:DRP12[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_CDR_FORCE_ROTATE" title="GTX0:RX_CDR_FORCE_ROTATE">GTX0:RX_CDR_FORCE_ROTATE</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_3" title="GTX0:CLK_COR_SEQ_2_3[0]">GTX0:CLK_COR_SEQ_2_3[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[0]">GTX0:DRP13[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_3" title="GTX0:CLK_COR_SEQ_2_3[1]">GTX0:CLK_COR_SEQ_2_3[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[1]">GTX0:DRP13[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_3" title="GTX0:CLK_COR_SEQ_2_3[2]">GTX0:CLK_COR_SEQ_2_3[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[2]">GTX0:DRP13[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_3" title="GTX0:CLK_COR_SEQ_2_3[3]">GTX0:CLK_COR_SEQ_2_3[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[3]">GTX0:DRP13[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_3" title="GTX0:CLK_COR_SEQ_2_3[4]">GTX0:CLK_COR_SEQ_2_3[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[4]">GTX0:DRP13[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_3" title="GTX0:CLK_COR_SEQ_2_3[5]">GTX0:CLK_COR_SEQ_2_3[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[5]">GTX0:DRP13[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_3" title="GTX0:CLK_COR_SEQ_2_3[6]">GTX0:CLK_COR_SEQ_2_3[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[6]">GTX0:DRP13[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_3" title="GTX0:CLK_COR_SEQ_2_3[7]">GTX0:CLK_COR_SEQ_2_3[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[7]">GTX0:DRP13[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_3" title="GTX0:CLK_COR_SEQ_2_3[8]">GTX0:CLK_COR_SEQ_2_3[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[8]">GTX0:DRP13[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_3" title="GTX0:CLK_COR_SEQ_2_3[9]">GTX0:CLK_COR_SEQ_2_3[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[9]">GTX0:DRP13[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_DET_LEN" title="GTX0:CLK_COR_DET_LEN[0]">GTX0:CLK_COR_DET_LEN[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[10]">GTX0:DRP13[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_DET_LEN" title="GTX0:CLK_COR_DET_LEN[1]">GTX0:CLK_COR_DET_LEN[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[11]">GTX0:DRP13[11]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[12]">GTX0:DRP13[12]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_SLIDE_AUTO_WAIT" title="GTX0:RX_SLIDE_AUTO_WAIT[0]">GTX0:RX_SLIDE_AUTO_WAIT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[13]">GTX0:DRP13[13]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_SLIDE_AUTO_WAIT" title="GTX0:RX_SLIDE_AUTO_WAIT[1]">GTX0:RX_SLIDE_AUTO_WAIT[1]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[14]">GTX0:DRP13[14]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_SLIDE_AUTO_WAIT" title="GTX0:RX_SLIDE_AUTO_WAIT[2]">GTX0:RX_SLIDE_AUTO_WAIT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP13" title="GTX0:DRP13[15]">GTX0:DRP13[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_SLIDE_AUTO_WAIT" title="GTX0:RX_SLIDE_AUTO_WAIT[3]">GTX0:RX_SLIDE_AUTO_WAIT[3]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_4" title="GTX0:CLK_COR_SEQ_2_4[0]">GTX0:CLK_COR_SEQ_2_4[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[0]">GTX0:DRP14[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_4" title="GTX0:CLK_COR_SEQ_2_4[1]">GTX0:CLK_COR_SEQ_2_4[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[1]">GTX0:DRP14[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_4" title="GTX0:CLK_COR_SEQ_2_4[2]">GTX0:CLK_COR_SEQ_2_4[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[2]">GTX0:DRP14[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_4" title="GTX0:CLK_COR_SEQ_2_4[3]">GTX0:CLK_COR_SEQ_2_4[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[3]">GTX0:DRP14[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_4" title="GTX0:CLK_COR_SEQ_2_4[4]">GTX0:CLK_COR_SEQ_2_4[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[4]">GTX0:DRP14[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_4" title="GTX0:CLK_COR_SEQ_2_4[5]">GTX0:CLK_COR_SEQ_2_4[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[5]">GTX0:DRP14[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_4" title="GTX0:CLK_COR_SEQ_2_4[6]">GTX0:CLK_COR_SEQ_2_4[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[6]">GTX0:DRP14[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_4" title="GTX0:CLK_COR_SEQ_2_4[7]">GTX0:CLK_COR_SEQ_2_4[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[7]">GTX0:DRP14[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_4" title="GTX0:CLK_COR_SEQ_2_4[8]">GTX0:CLK_COR_SEQ_2_4[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[8]">GTX0:DRP14[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_4" title="GTX0:CLK_COR_SEQ_2_4[9]">GTX0:CLK_COR_SEQ_2_4[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[9]">GTX0:DRP14[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DEC_PCOMMA_DETECT" title="GTX0:DEC_PCOMMA_DETECT">GTX0:DEC_PCOMMA_DETECT</a><br><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[10]">GTX0:DRP14[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DEC_MCOMMA_DETECT" title="GTX0:DEC_MCOMMA_DETECT">GTX0:DEC_MCOMMA_DETECT</a><br><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[11]">GTX0:DRP14[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[12]">GTX0:DRP14[12]</a><br><a href="#bits-xc6v-GTX-GTX0:USR_CODE_ERR_CLR" title="GTX0:USR_CODE_ERR_CLR">GTX0:USR_CODE_ERR_CLR</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[13]">GTX0:DRP14[13]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DECODE_SEQ_MATCH" title="GTX0:RX_DECODE_SEQ_MATCH">GTX0:RX_DECODE_SEQ_MATCH</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:ALIGN_COMMA_WORD" title="GTX0:ALIGN_COMMA_WORD">GTX0:ALIGN_COMMA_WORD</a><br><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[14]">GTX0:DRP14[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DEC_VALID_COMMA_ONLY" title="GTX0:DEC_VALID_COMMA_ONLY">GTX0:DEC_VALID_COMMA_ONLY</a><br><a href="#bits-xc6v-GTX-GTX0:DRP14" title="GTX0:DRP14[15]">GTX0:DRP14[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[0]">GTX0:DRP15[0]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[0]">GTX0:PMA_CDR_SCAN[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[1]">GTX0:DRP15[1]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[1]">GTX0:PMA_CDR_SCAN[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[2]">GTX0:DRP15[2]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[2]">GTX0:PMA_CDR_SCAN[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[3]">GTX0:DRP15[3]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[3]">GTX0:PMA_CDR_SCAN[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[4]">GTX0:DRP15[4]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[4]">GTX0:PMA_CDR_SCAN[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[5]">GTX0:DRP15[5]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[5]">GTX0:PMA_CDR_SCAN[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[6]">GTX0:DRP15[6]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[6]">GTX0:PMA_CDR_SCAN[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[7]">GTX0:DRP15[7]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[7]">GTX0:PMA_CDR_SCAN[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[8]">GTX0:DRP15[8]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[8]">GTX0:PMA_CDR_SCAN[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[9]">GTX0:DRP15[9]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[9]">GTX0:PMA_CDR_SCAN[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[10]">GTX0:DRP15[10]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[10]">GTX0:PMA_CDR_SCAN[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[11]">GTX0:DRP15[11]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[11]">GTX0:PMA_CDR_SCAN[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[12]">GTX0:DRP15[12]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[12]">GTX0:PMA_CDR_SCAN[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[13]">GTX0:DRP15[13]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[13]">GTX0:PMA_CDR_SCAN[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[14]">GTX0:DRP15[14]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[14]">GTX0:PMA_CDR_SCAN[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP15" title="GTX0:DRP15[15]">GTX0:DRP15[15]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[15]">GTX0:PMA_CDR_SCAN[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[0]">GTX0:DRP16[0]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[16]">GTX0:PMA_CDR_SCAN[16]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[1]">GTX0:DRP16[1]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[17]">GTX0:PMA_CDR_SCAN[17]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[2]">GTX0:DRP16[2]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[18]">GTX0:PMA_CDR_SCAN[18]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[3]">GTX0:DRP16[3]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[19]">GTX0:PMA_CDR_SCAN[19]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[4]">GTX0:DRP16[4]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[20]">GTX0:PMA_CDR_SCAN[20]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[5]">GTX0:DRP16[5]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[21]">GTX0:PMA_CDR_SCAN[21]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[6]">GTX0:DRP16[6]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[22]">GTX0:PMA_CDR_SCAN[22]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[7]">GTX0:DRP16[7]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[23]">GTX0:PMA_CDR_SCAN[23]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[8]">GTX0:DRP16[8]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[24]">GTX0:PMA_CDR_SCAN[24]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[9]">GTX0:DRP16[9]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[25]">GTX0:PMA_CDR_SCAN[25]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[10]">GTX0:DRP16[10]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CDR_SCAN" title="GTX0:PMA_CDR_SCAN[26]">GTX0:PMA_CDR_SCAN[26]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CDR_PH_ADJ_TIME" title="GTX0:CDR_PH_ADJ_TIME[0]">GTX0:CDR_PH_ADJ_TIME[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[11]">GTX0:DRP16[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CDR_PH_ADJ_TIME" title="GTX0:CDR_PH_ADJ_TIME[1]">GTX0:CDR_PH_ADJ_TIME[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[12]">GTX0:DRP16[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CDR_PH_ADJ_TIME" title="GTX0:CDR_PH_ADJ_TIME[2]">GTX0:CDR_PH_ADJ_TIME[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[13]">GTX0:DRP16[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CDR_PH_ADJ_TIME" title="GTX0:CDR_PH_ADJ_TIME[3]">GTX0:CDR_PH_ADJ_TIME[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[14]">GTX0:DRP16[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CDR_PH_ADJ_TIME" title="GTX0:CDR_PH_ADJ_TIME[4]">GTX0:CDR_PH_ADJ_TIME[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP16" title="GTX0:DRP16[15]">GTX0:DRP16[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[0]">GTX0:DRP17[0]</a><br><a href="#bits-xc6v-GTX-GTX0:OOBDETECT_THRESHOLD" title="GTX0:OOBDETECT_THRESHOLD[0]">GTX0:OOBDETECT_THRESHOLD[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[1]">GTX0:DRP17[1]</a><br><a href="#bits-xc6v-GTX-GTX0:OOBDETECT_THRESHOLD" title="GTX0:OOBDETECT_THRESHOLD[1]">GTX0:OOBDETECT_THRESHOLD[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[2]">GTX0:DRP17[2]</a><br><a href="#bits-xc6v-GTX-GTX0:OOBDETECT_THRESHOLD" title="GTX0:OOBDETECT_THRESHOLD[2]">GTX0:OOBDETECT_THRESHOLD[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[3]">GTX0:DRP17[3]</a><br><a href="#bits-xc6v-GTX-GTX0:GTX_CFG_PWRUP" title="GTX0:GTX_CFG_PWRUP">GTX0:GTX_CFG_PWRUP</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:AC_CAP_DIS" title="GTX0:AC_CAP_DIS">GTX0:AC_CAP_DIS</a><br><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[4]">GTX0:DRP17[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[5]">GTX0:DRP17[5]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_CLK25_DIVIDER" title="GTX0:RX_CLK25_DIVIDER[0]">GTX0:RX_CLK25_DIVIDER[0]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[6]">GTX0:DRP17[6]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_CLK25_DIVIDER" title="GTX0:RX_CLK25_DIVIDER[1]">GTX0:RX_CLK25_DIVIDER[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[7]">GTX0:DRP17[7]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_CLK25_DIVIDER" title="GTX0:RX_CLK25_DIVIDER[2]">GTX0:RX_CLK25_DIVIDER[2]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[8]">GTX0:DRP17[8]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_CLK25_DIVIDER" title="GTX0:RX_CLK25_DIVIDER[3]">GTX0:RX_CLK25_DIVIDER[3]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[9]">GTX0:DRP17[9]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_CLK25_DIVIDER" title="GTX0:RX_CLK25_DIVIDER[4]">GTX0:RX_CLK25_DIVIDER[4]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:BIAS_CFG" title="GTX0:BIAS_CFG[16]">GTX0:BIAS_CFG[16]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[10]">GTX0:DRP17[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_CFG" title="GTX0:CHAN_BOND_SEQ_2_CFG[4]">GTX0:CHAN_BOND_SEQ_2_CFG[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[11]">GTX0:DRP17[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[12]">GTX0:DRP17[12]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DATA_WIDTH" title="GTX0:RX_DATA_WIDTH[0]">GTX0:RX_DATA_WIDTH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[13]">GTX0:DRP17[13]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DATA_WIDTH" title="GTX0:RX_DATA_WIDTH[1]">GTX0:RX_DATA_WIDTH[1]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[14]">GTX0:DRP17[14]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DATA_WIDTH" title="GTX0:RX_DATA_WIDTH[2]">GTX0:RX_DATA_WIDTH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP17" title="GTX0:DRP17[15]">GTX0:DRP17[15]</a><br><a href="#bits-xc6v-GTX-GTX0:GEN_RXUSRCLK" title="GTX0:GEN_RXUSRCLK">GTX0:GEN_RXUSRCLK</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 3</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[0]">GTX0:DRP18[0]</a><br><a href="#bits-xc6v-GTX-GTX0:GEARBOX_ENDEC" title="GTX0:GEARBOX_ENDEC[0]">GTX0:GEARBOX_ENDEC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[1]">GTX0:DRP18[1]</a><br><a href="#bits-xc6v-GTX-GTX0:GEARBOX_ENDEC" title="GTX0:GEARBOX_ENDEC[1]">GTX0:GEARBOX_ENDEC[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[2]">GTX0:DRP18[2]</a><br><a href="#bits-xc6v-GTX-GTX0:GEARBOX_ENDEC" title="GTX0:GEARBOX_ENDEC[2]">GTX0:GEARBOX_ENDEC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[3]">GTX0:DRP18[3]</a><br><a href="#bits-xc6v-GTX-GTX0:RXGEARBOX_USE" title="GTX0:RXGEARBOX_USE">GTX0:RXGEARBOX_USE</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_RXCDRRESET" title="GTX0:A_RXCDRRESET">GTX0:A_RXCDRRESET</a><br><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[4]">GTX0:DRP18[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_GTXTXRESET" title="GTX0:A_GTXTXRESET">GTX0:A_GTXTXRESET</a><br><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[5]">GTX0:DRP18[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_GTXRXRESET" title="GTX0:A_GTXRXRESET">GTX0:A_GTXRXRESET</a><br><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[6]">GTX0:DRP18[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_RXBUFRESET" title="GTX0:A_RXBUFRESET">GTX0:A_RXBUFRESET</a><br><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[7]">GTX0:DRP18[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_RXRESET" title="GTX0:A_RXRESET">GTX0:A_RXRESET</a><br><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[8]">GTX0:DRP18[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXRESET" title="GTX0:A_TXRESET">GTX0:A_TXRESET</a><br><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[9]">GTX0:DRP18[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_RXCDRHOLD" title="GTX0:A_RXCDRHOLD">GTX0:A_RXCDRHOLD</a><br><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[10]">GTX0:DRP18[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_RXCDRFREQRESET" title="GTX0:A_RXCDRFREQRESET">GTX0:A_RXCDRFREQRESET</a><br><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[11]">GTX0:DRP18[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_RXCDRPHASERESET" title="GTX0:A_RXCDRPHASERESET">GTX0:A_RXCDRPHASERESET</a><br><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[12]">GTX0:DRP18[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_RXDFERESET" title="GTX0:A_RXDFERESET">GTX0:A_RXDFERESET</a><br><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[13]">GTX0:DRP18[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[14]">GTX0:DRP18[14]</a><br><a href="#bits-xc6v-GTX-GTX0:RESET_DRP_EN" title="GTX0:RESET_DRP_EN">GTX0:RESET_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP18" title="GTX0:DRP18[15]">GTX0:DRP18[15]</a><br><a href="#bits-xc6v-GTX-GTX0:MASTER_DRP_EN" title="GTX0:MASTER_DRP_EN">GTX0:MASTER_DRP_EN</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[0]">GTX0:DRP19[0]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[0]">GTX0:RXPLL_COM_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[1]">GTX0:DRP19[1]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[1]">GTX0:RXPLL_COM_CFG[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[2]">GTX0:DRP19[2]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[2]">GTX0:RXPLL_COM_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[3]">GTX0:DRP19[3]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[3]">GTX0:RXPLL_COM_CFG[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[4]">GTX0:DRP19[4]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[4]">GTX0:RXPLL_COM_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[5]">GTX0:DRP19[5]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[5]">GTX0:RXPLL_COM_CFG[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[6]">GTX0:DRP19[6]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[6]">GTX0:RXPLL_COM_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[7]">GTX0:DRP19[7]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[7]">GTX0:RXPLL_COM_CFG[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[8]">GTX0:DRP19[8]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[8]">GTX0:RXPLL_COM_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[9]">GTX0:DRP19[9]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[9]">GTX0:RXPLL_COM_CFG[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[10]">GTX0:DRP19[10]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[10]">GTX0:RXPLL_COM_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[11]">GTX0:DRP19[11]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[11]">GTX0:RXPLL_COM_CFG[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[12]">GTX0:DRP19[12]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[12]">GTX0:RXPLL_COM_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[13]">GTX0:DRP19[13]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[13]">GTX0:RXPLL_COM_CFG[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[14]">GTX0:DRP19[14]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[14]">GTX0:RXPLL_COM_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP19" title="GTX0:DRP19[15]">GTX0:DRP19[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[15]">GTX0:RXPLL_COM_CFG[15]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[0]">GTX0:DRP1A[0]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[16]">GTX0:RXPLL_COM_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[1]">GTX0:DRP1A[1]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[17]">GTX0:RXPLL_COM_CFG[17]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[2]">GTX0:DRP1A[2]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[18]">GTX0:RXPLL_COM_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[3]">GTX0:DRP1A[3]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[19]">GTX0:RXPLL_COM_CFG[19]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[4]">GTX0:DRP1A[4]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[20]">GTX0:RXPLL_COM_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[5]">GTX0:DRP1A[5]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[21]">GTX0:RXPLL_COM_CFG[21]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[6]">GTX0:DRP1A[6]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[22]">GTX0:RXPLL_COM_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[7]">GTX0:DRP1A[7]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_COM_CFG" title="GTX0:RXPLL_COM_CFG[23]">GTX0:RXPLL_COM_CFG[23]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[8]">GTX0:DRP1A[8]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_CP_CFG" title="GTX0:RXPLL_CP_CFG[0]">GTX0:RXPLL_CP_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[9]">GTX0:DRP1A[9]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_CP_CFG" title="GTX0:RXPLL_CP_CFG[1]">GTX0:RXPLL_CP_CFG[1]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[10]">GTX0:DRP1A[10]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_CP_CFG" title="GTX0:RXPLL_CP_CFG[2]">GTX0:RXPLL_CP_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[11]">GTX0:DRP1A[11]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_CP_CFG" title="GTX0:RXPLL_CP_CFG[3]">GTX0:RXPLL_CP_CFG[3]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[12]">GTX0:DRP1A[12]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_CP_CFG" title="GTX0:RXPLL_CP_CFG[4]">GTX0:RXPLL_CP_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[13]">GTX0:DRP1A[13]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_CP_CFG" title="GTX0:RXPLL_CP_CFG[5]">GTX0:RXPLL_CP_CFG[5]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[14]">GTX0:DRP1A[14]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_CP_CFG" title="GTX0:RXPLL_CP_CFG[6]">GTX0:RXPLL_CP_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1A" title="GTX0:DRP1A[15]">GTX0:DRP1A[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_CP_CFG" title="GTX0:RXPLL_CP_CFG[7]">GTX0:RXPLL_CP_CFG[7]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[0]">GTX0:DRP1B[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[1]">GTX0:DRP1B[1]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_DIVSEL_FB" title="GTX0:RXPLL_DIVSEL_FB[1]">GTX0:RXPLL_DIVSEL_FB[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[2]">GTX0:DRP1B[2]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_DIVSEL_FB" title="GTX0:RXPLL_DIVSEL_FB[2]">GTX0:RXPLL_DIVSEL_FB[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[3]">GTX0:DRP1B[3]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_DIVSEL_FB" title="GTX0:RXPLL_DIVSEL_FB[3]">GTX0:RXPLL_DIVSEL_FB[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[4]">GTX0:DRP1B[4]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_DIVSEL_FB" title="GTX0:RXPLL_DIVSEL_FB[4]">GTX0:RXPLL_DIVSEL_FB[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[5]">GTX0:DRP1B[5]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_DIVSEL_FB" title="GTX0:RXPLL_DIVSEL_FB[0]">GTX0:RXPLL_DIVSEL_FB[0]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[6]">GTX0:DRP1B[6]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_DIVSEL45_FB" title="GTX0:RXPLL_DIVSEL45_FB">GTX0:RXPLL_DIVSEL45_FB</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[7]">GTX0:DRP1B[7]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_STARTUP_EN" title="GTX0:RXPLL_STARTUP_EN">GTX0:RXPLL_STARTUP_EN</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[8]">GTX0:DRP1B[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_RXPOWERDOWN" title="GTX0:A_RXPOWERDOWN[0]">GTX0:A_RXPOWERDOWN[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[9]">GTX0:DRP1B[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_RXPOWERDOWN" title="GTX0:A_RXPOWERDOWN[1]">GTX0:A_RXPOWERDOWN[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[10]">GTX0:DRP1B[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[11]">GTX0:DRP1B[11]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_LKDET_CFG" title="GTX0:RXPLL_LKDET_CFG[0]">GTX0:RXPLL_LKDET_CFG[0]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[12]">GTX0:DRP1B[12]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_LKDET_CFG" title="GTX0:RXPLL_LKDET_CFG[1]">GTX0:RXPLL_LKDET_CFG[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[13]">GTX0:DRP1B[13]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_LKDET_CFG" title="GTX0:RXPLL_LKDET_CFG[2]">GTX0:RXPLL_LKDET_CFG[2]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[14]">GTX0:DRP1B[14]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_DIVSEL_OUT" title="GTX0:RXPLL_DIVSEL_OUT[0]">GTX0:RXPLL_DIVSEL_OUT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1B" title="GTX0:DRP1B[15]">GTX0:DRP1B[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_DIVSEL_OUT" title="GTX0:RXPLL_DIVSEL_OUT[1]">GTX0:RXPLL_DIVSEL_OUT[1]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[0]">GTX0:DRP1C[0]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLLREFSEL_TESTCLK" title="GTX0:RXPLLREFSEL_TESTCLK">GTX0:RXPLLREFSEL_TESTCLK</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[1]">GTX0:DRP1C[1]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_DIVSEL_REF" title="GTX0:RXPLL_DIVSEL_REF[1]">GTX0:RXPLL_DIVSEL_REF[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[2]">GTX0:DRP1C[2]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_DIVSEL_REF" title="GTX0:RXPLL_DIVSEL_REF[2]">GTX0:RXPLL_DIVSEL_REF[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[3]">GTX0:DRP1C[3]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_DIVSEL_REF" title="GTX0:RXPLL_DIVSEL_REF[3]">GTX0:RXPLL_DIVSEL_REF[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[4]">GTX0:DRP1C[4]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_DIVSEL_REF" title="GTX0:RXPLL_DIVSEL_REF[4]">GTX0:RXPLL_DIVSEL_REF[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[5]">GTX0:DRP1C[5]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLL_DIVSEL_REF" title="GTX0:RXPLL_DIVSEL_REF[0]">GTX0:RXPLL_DIVSEL_REF[0]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[6]">GTX0:DRP1C[6]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLLREFSEL_MODE" title="GTX0:RXPLLREFSEL_MODE">GTX0:RXPLLREFSEL_MODE</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[7]">GTX0:DRP1C[7]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLLREFSEL_STATIC" title="GTX0:RXPLLREFSEL_STATIC[0]">GTX0:RXPLLREFSEL_STATIC[0]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[8]">GTX0:DRP1C[8]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLLREFSEL_STATIC" title="GTX0:RXPLLREFSEL_STATIC[1]">GTX0:RXPLLREFSEL_STATIC[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[9]">GTX0:DRP1C[9]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPLLREFSEL_STATIC" title="GTX0:RXPLLREFSEL_STATIC[2]">GTX0:RXPLLREFSEL_STATIC[2]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_PLLRXRESET" title="GTX0:A_PLLRXRESET">GTX0:A_PLLRXRESET</a><br><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[10]">GTX0:DRP1C[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_RXPLLLKDETEN" title="GTX0:A_RXPLLLKDETEN">GTX0:A_RXPLLLKDETEN</a><br><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[11]">GTX0:DRP1C[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_PLLCLKRXRESET" title="GTX0:A_PLLCLKRXRESET">GTX0:A_PLLCLKRXRESET</a><br><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[12]">GTX0:DRP1C[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[13]">GTX0:DRP1C[13]</a><br><a href="#bits-xc6v-GTX-GTX0:PLL_DRP_EN" title="GTX0:PLL_DRP_EN">GTX0:PLL_DRP_EN</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_RXPLLPOWERDOWN" title="GTX0:A_RXPLLPOWERDOWN">GTX0:A_RXPLLPOWERDOWN</a><br><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[14]">GTX0:DRP1C[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1C" title="GTX0:DRP1C[15]">GTX0:DRP1C[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_OVERSAMPLE_MODE" title="GTX0:RX_OVERSAMPLE_MODE">GTX0:RX_OVERSAMPLE_MODE</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[0]">GTX0:DRP1D[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[0]">GTX0:TXPLL_COM_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[1]">GTX0:DRP1D[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[1]">GTX0:TXPLL_COM_CFG[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[2]">GTX0:DRP1D[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[2]">GTX0:TXPLL_COM_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[3]">GTX0:DRP1D[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[3]">GTX0:TXPLL_COM_CFG[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[4]">GTX0:DRP1D[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[4]">GTX0:TXPLL_COM_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[5]">GTX0:DRP1D[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[5]">GTX0:TXPLL_COM_CFG[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[6]">GTX0:DRP1D[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[6]">GTX0:TXPLL_COM_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[7]">GTX0:DRP1D[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[7]">GTX0:TXPLL_COM_CFG[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[8]">GTX0:DRP1D[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[8]">GTX0:TXPLL_COM_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[9]">GTX0:DRP1D[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[9]">GTX0:TXPLL_COM_CFG[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[10]">GTX0:DRP1D[10]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[10]">GTX0:TXPLL_COM_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[11]">GTX0:DRP1D[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[11]">GTX0:TXPLL_COM_CFG[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[12]">GTX0:DRP1D[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[12]">GTX0:TXPLL_COM_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[13]">GTX0:DRP1D[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[13]">GTX0:TXPLL_COM_CFG[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[14]">GTX0:DRP1D[14]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[14]">GTX0:TXPLL_COM_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1D" title="GTX0:DRP1D[15]">GTX0:DRP1D[15]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[15]">GTX0:TXPLL_COM_CFG[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[0]">GTX0:DRP1E[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[16]">GTX0:TXPLL_COM_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[1]">GTX0:DRP1E[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[17]">GTX0:TXPLL_COM_CFG[17]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[2]">GTX0:DRP1E[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[18]">GTX0:TXPLL_COM_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[3]">GTX0:DRP1E[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[19]">GTX0:TXPLL_COM_CFG[19]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[4]">GTX0:DRP1E[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[20]">GTX0:TXPLL_COM_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[5]">GTX0:DRP1E[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[21]">GTX0:TXPLL_COM_CFG[21]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[6]">GTX0:DRP1E[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[22]">GTX0:TXPLL_COM_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[7]">GTX0:DRP1E[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_COM_CFG" title="GTX0:TXPLL_COM_CFG[23]">GTX0:TXPLL_COM_CFG[23]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[8]">GTX0:DRP1E[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_CP_CFG" title="GTX0:TXPLL_CP_CFG[0]">GTX0:TXPLL_CP_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[9]">GTX0:DRP1E[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_CP_CFG" title="GTX0:TXPLL_CP_CFG[1]">GTX0:TXPLL_CP_CFG[1]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[10]">GTX0:DRP1E[10]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_CP_CFG" title="GTX0:TXPLL_CP_CFG[2]">GTX0:TXPLL_CP_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[11]">GTX0:DRP1E[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_CP_CFG" title="GTX0:TXPLL_CP_CFG[3]">GTX0:TXPLL_CP_CFG[3]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[12]">GTX0:DRP1E[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_CP_CFG" title="GTX0:TXPLL_CP_CFG[4]">GTX0:TXPLL_CP_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[13]">GTX0:DRP1E[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_CP_CFG" title="GTX0:TXPLL_CP_CFG[5]">GTX0:TXPLL_CP_CFG[5]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[14]">GTX0:DRP1E[14]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_CP_CFG" title="GTX0:TXPLL_CP_CFG[6]">GTX0:TXPLL_CP_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1E" title="GTX0:DRP1E[15]">GTX0:DRP1E[15]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_CP_CFG" title="GTX0:TXPLL_CP_CFG[7]">GTX0:TXPLL_CP_CFG[7]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[0]">GTX0:DRP1F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[1]">GTX0:DRP1F[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_DIVSEL_FB" title="GTX0:TXPLL_DIVSEL_FB[1]">GTX0:TXPLL_DIVSEL_FB[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[2]">GTX0:DRP1F[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_DIVSEL_FB" title="GTX0:TXPLL_DIVSEL_FB[2]">GTX0:TXPLL_DIVSEL_FB[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[3]">GTX0:DRP1F[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_DIVSEL_FB" title="GTX0:TXPLL_DIVSEL_FB[3]">GTX0:TXPLL_DIVSEL_FB[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[4]">GTX0:DRP1F[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_DIVSEL_FB" title="GTX0:TXPLL_DIVSEL_FB[4]">GTX0:TXPLL_DIVSEL_FB[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[5]">GTX0:DRP1F[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_DIVSEL_FB" title="GTX0:TXPLL_DIVSEL_FB[0]">GTX0:TXPLL_DIVSEL_FB[0]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[6]">GTX0:DRP1F[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_DIVSEL45_FB" title="GTX0:TXPLL_DIVSEL45_FB">GTX0:TXPLL_DIVSEL45_FB</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[7]">GTX0:DRP1F[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_STARTUP_EN" title="GTX0:TXPLL_STARTUP_EN">GTX0:TXPLL_STARTUP_EN</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[8]">GTX0:DRP1F[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_CLK_SOURCE" title="GTX0:TX_CLK_SOURCE">GTX0:TX_CLK_SOURCE</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPOWERDOWN" title="GTX0:A_TXPOWERDOWN[0]">GTX0:A_TXPOWERDOWN[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[9]">GTX0:DRP1F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPOWERDOWN" title="GTX0:A_TXPOWERDOWN[1]">GTX0:A_TXPOWERDOWN[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[10]">GTX0:DRP1F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[11]">GTX0:DRP1F[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_LKDET_CFG" title="GTX0:TXPLL_LKDET_CFG[0]">GTX0:TXPLL_LKDET_CFG[0]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[12]">GTX0:DRP1F[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_LKDET_CFG" title="GTX0:TXPLL_LKDET_CFG[1]">GTX0:TXPLL_LKDET_CFG[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[13]">GTX0:DRP1F[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_LKDET_CFG" title="GTX0:TXPLL_LKDET_CFG[2]">GTX0:TXPLL_LKDET_CFG[2]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[14]">GTX0:DRP1F[14]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_DIVSEL_OUT" title="GTX0:TXPLL_DIVSEL_OUT[0]">GTX0:TXPLL_DIVSEL_OUT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP1F" title="GTX0:DRP1F[15]">GTX0:DRP1F[15]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_DIVSEL_OUT" title="GTX0:TXPLL_DIVSEL_OUT[1]">GTX0:TXPLL_DIVSEL_OUT[1]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 4</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[0]">GTX0:DRP20[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLLREFSEL_TESTCLK" title="GTX0:TXPLLREFSEL_TESTCLK">GTX0:TXPLLREFSEL_TESTCLK</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[1]">GTX0:DRP20[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_DIVSEL_REF" title="GTX0:TXPLL_DIVSEL_REF[1]">GTX0:TXPLL_DIVSEL_REF[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[2]">GTX0:DRP20[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_DIVSEL_REF" title="GTX0:TXPLL_DIVSEL_REF[2]">GTX0:TXPLL_DIVSEL_REF[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[3]">GTX0:DRP20[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_DIVSEL_REF" title="GTX0:TXPLL_DIVSEL_REF[3]">GTX0:TXPLL_DIVSEL_REF[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[4]">GTX0:DRP20[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_DIVSEL_REF" title="GTX0:TXPLL_DIVSEL_REF[4]">GTX0:TXPLL_DIVSEL_REF[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[5]">GTX0:DRP20[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_DIVSEL_REF" title="GTX0:TXPLL_DIVSEL_REF[0]">GTX0:TXPLL_DIVSEL_REF[0]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[6]">GTX0:DRP20[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLLREFSEL_MODE" title="GTX0:TXPLLREFSEL_MODE">GTX0:TXPLLREFSEL_MODE</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[7]">GTX0:DRP20[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLLREFSEL_STATIC" title="GTX0:TXPLLREFSEL_STATIC[0]">GTX0:TXPLLREFSEL_STATIC[0]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[8]">GTX0:DRP20[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLLREFSEL_STATIC" title="GTX0:TXPLLREFSEL_STATIC[1]">GTX0:TXPLLREFSEL_STATIC[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[9]">GTX0:DRP20[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLLREFSEL_STATIC" title="GTX0:TXPLLREFSEL_STATIC[2]">GTX0:TXPLLREFSEL_STATIC[2]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_PLLTXRESET" title="GTX0:A_PLLTXRESET">GTX0:A_PLLTXRESET</a><br><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[10]">GTX0:DRP20[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPLLLKDETEN" title="GTX0:A_TXPLLLKDETEN">GTX0:A_TXPLLLKDETEN</a><br><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[11]">GTX0:DRP20[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_PLLCLKTXRESET" title="GTX0:A_PLLCLKTXRESET">GTX0:A_PLLCLKTXRESET</a><br><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[12]">GTX0:DRP20[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[13]">GTX0:DRP20[13]</a><br><a href="#bits-xc6v-GTX-GTX0:PDELIDLE_DRP_EN" title="GTX0:PDELIDLE_DRP_EN">GTX0:PDELIDLE_DRP_EN</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPLLPOWERDOWN" title="GTX0:A_TXPLLPOWERDOWN">GTX0:A_TXPLLPOWERDOWN</a><br><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[14]">GTX0:DRP20[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP20" title="GTX0:DRP20[15]">GTX0:DRP20[15]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_OVERSAMPLE_MODE" title="GTX0:TX_OVERSAMPLE_MODE">GTX0:TX_OVERSAMPLE_MODE</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[0]">GTX0:DRP21[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DETECT_RX_CFG" title="GTX0:TX_DETECT_RX_CFG[0]">GTX0:TX_DETECT_RX_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[1]">GTX0:DRP21[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DETECT_RX_CFG" title="GTX0:TX_DETECT_RX_CFG[1]">GTX0:TX_DETECT_RX_CFG[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[2]">GTX0:DRP21[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DETECT_RX_CFG" title="GTX0:TX_DETECT_RX_CFG[2]">GTX0:TX_DETECT_RX_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[3]">GTX0:DRP21[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DETECT_RX_CFG" title="GTX0:TX_DETECT_RX_CFG[3]">GTX0:TX_DETECT_RX_CFG[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[4]">GTX0:DRP21[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DETECT_RX_CFG" title="GTX0:TX_DETECT_RX_CFG[4]">GTX0:TX_DETECT_RX_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[5]">GTX0:DRP21[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DETECT_RX_CFG" title="GTX0:TX_DETECT_RX_CFG[5]">GTX0:TX_DETECT_RX_CFG[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[6]">GTX0:DRP21[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DETECT_RX_CFG" title="GTX0:TX_DETECT_RX_CFG[6]">GTX0:TX_DETECT_RX_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[7]">GTX0:DRP21[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DETECT_RX_CFG" title="GTX0:TX_DETECT_RX_CFG[7]">GTX0:TX_DETECT_RX_CFG[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[8]">GTX0:DRP21[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DETECT_RX_CFG" title="GTX0:TX_DETECT_RX_CFG[8]">GTX0:TX_DETECT_RX_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[9]">GTX0:DRP21[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DETECT_RX_CFG" title="GTX0:TX_DETECT_RX_CFG[9]">GTX0:TX_DETECT_RX_CFG[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[10]">GTX0:DRP21[10]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DETECT_RX_CFG" title="GTX0:TX_DETECT_RX_CFG[10]">GTX0:TX_DETECT_RX_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[11]">GTX0:DRP21[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DETECT_RX_CFG" title="GTX0:TX_DETECT_RX_CFG[11]">GTX0:TX_DETECT_RX_CFG[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[12]">GTX0:DRP21[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DETECT_RX_CFG" title="GTX0:TX_DETECT_RX_CFG[12]">GTX0:TX_DETECT_RX_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[13]">GTX0:DRP21[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DETECT_RX_CFG" title="GTX0:TX_DETECT_RX_CFG[13]">GTX0:TX_DETECT_RX_CFG[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXELECIDLE" title="GTX0:A_TXELECIDLE">GTX0:A_TXELECIDLE</a><br><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[14]">GTX0:DRP21[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP21" title="GTX0:DRP21[15]">GTX0:DRP21[15]</a><br><a href="#bits-xc6v-GTX-GTX0:PCI_EXPRESS_MODE" title="GTX0:PCI_EXPRESS_MODE">GTX0:PCI_EXPRESS_MODE</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[0]">GTX0:DRP22[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[1]">GTX0:DRP22[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[2]">GTX0:DRP22[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[3]">GTX0:DRP22[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[4]">GTX0:DRP22[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[5]">GTX0:DRP22[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[6]">GTX0:DRP22[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[7]">GTX0:DRP22[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[8]">GTX0:DRP22[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[9]">GTX0:DRP22[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[10]">GTX0:DRP22[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[11]">GTX0:DRP22[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[12]">GTX0:DRP22[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[13]">GTX0:DRP22[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[14]">GTX0:DRP22[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP22" title="GTX0:DRP22[15]">GTX0:DRP22[15]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CAS_CLK_EN" title="GTX0:PMA_CAS_CLK_EN">GTX0:PMA_CAS_CLK_EN</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[0]">GTX0:DRP23[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_TO_P2" title="GTX0:TRANS_TIME_TO_P2[0]">GTX0:TRANS_TIME_TO_P2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[1]">GTX0:DRP23[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_TO_P2" title="GTX0:TRANS_TIME_TO_P2[1]">GTX0:TRANS_TIME_TO_P2[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[2]">GTX0:DRP23[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_TO_P2" title="GTX0:TRANS_TIME_TO_P2[2]">GTX0:TRANS_TIME_TO_P2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[3]">GTX0:DRP23[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_TO_P2" title="GTX0:TRANS_TIME_TO_P2[3]">GTX0:TRANS_TIME_TO_P2[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[4]">GTX0:DRP23[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_TO_P2" title="GTX0:TRANS_TIME_TO_P2[4]">GTX0:TRANS_TIME_TO_P2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[5]">GTX0:DRP23[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_TO_P2" title="GTX0:TRANS_TIME_TO_P2[5]">GTX0:TRANS_TIME_TO_P2[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[6]">GTX0:DRP23[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_TO_P2" title="GTX0:TRANS_TIME_TO_P2[6]">GTX0:TRANS_TIME_TO_P2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[7]">GTX0:DRP23[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_TO_P2" title="GTX0:TRANS_TIME_TO_P2[7]">GTX0:TRANS_TIME_TO_P2[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[8]">GTX0:DRP23[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_TO_P2" title="GTX0:TRANS_TIME_TO_P2[8]">GTX0:TRANS_TIME_TO_P2[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[9]">GTX0:DRP23[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_TO_P2" title="GTX0:TRANS_TIME_TO_P2[9]">GTX0:TRANS_TIME_TO_P2[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[10]">GTX0:DRP23[10]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_CLK25_DIVIDER" title="GTX0:TX_CLK25_DIVIDER[0]">GTX0:TX_CLK25_DIVIDER[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[11]">GTX0:DRP23[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_CLK25_DIVIDER" title="GTX0:TX_CLK25_DIVIDER[1]">GTX0:TX_CLK25_DIVIDER[1]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[12]">GTX0:DRP23[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_CLK25_DIVIDER" title="GTX0:TX_CLK25_DIVIDER[2]">GTX0:TX_CLK25_DIVIDER[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[13]">GTX0:DRP23[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_CLK25_DIVIDER" title="GTX0:TX_CLK25_DIVIDER[3]">GTX0:TX_CLK25_DIVIDER[3]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[14]">GTX0:DRP23[14]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_CLK25_DIVIDER" title="GTX0:TX_CLK25_DIVIDER[4]">GTX0:TX_CLK25_DIVIDER[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP23" title="GTX0:DRP23[15]">GTX0:DRP23[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[0]">GTX0:DRP24[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_FROM_P2" title="GTX0:TRANS_TIME_FROM_P2[0]">GTX0:TRANS_TIME_FROM_P2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[1]">GTX0:DRP24[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_FROM_P2" title="GTX0:TRANS_TIME_FROM_P2[1]">GTX0:TRANS_TIME_FROM_P2[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[2]">GTX0:DRP24[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_FROM_P2" title="GTX0:TRANS_TIME_FROM_P2[2]">GTX0:TRANS_TIME_FROM_P2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[3]">GTX0:DRP24[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_FROM_P2" title="GTX0:TRANS_TIME_FROM_P2[3]">GTX0:TRANS_TIME_FROM_P2[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[4]">GTX0:DRP24[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_FROM_P2" title="GTX0:TRANS_TIME_FROM_P2[4]">GTX0:TRANS_TIME_FROM_P2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[5]">GTX0:DRP24[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_FROM_P2" title="GTX0:TRANS_TIME_FROM_P2[5]">GTX0:TRANS_TIME_FROM_P2[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[6]">GTX0:DRP24[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_FROM_P2" title="GTX0:TRANS_TIME_FROM_P2[6]">GTX0:TRANS_TIME_FROM_P2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[7]">GTX0:DRP24[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_FROM_P2" title="GTX0:TRANS_TIME_FROM_P2[7]">GTX0:TRANS_TIME_FROM_P2[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[8]">GTX0:DRP24[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_FROM_P2" title="GTX0:TRANS_TIME_FROM_P2[8]">GTX0:TRANS_TIME_FROM_P2[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[9]">GTX0:DRP24[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_FROM_P2" title="GTX0:TRANS_TIME_FROM_P2[9]">GTX0:TRANS_TIME_FROM_P2[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[10]">GTX0:DRP24[10]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_FROM_P2" title="GTX0:TRANS_TIME_FROM_P2[10]">GTX0:TRANS_TIME_FROM_P2[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[11]">GTX0:DRP24[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_FROM_P2" title="GTX0:TRANS_TIME_FROM_P2[11]">GTX0:TRANS_TIME_FROM_P2[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:COM_BURST_VAL" title="GTX0:COM_BURST_VAL[0]">GTX0:COM_BURST_VAL[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[12]">GTX0:DRP24[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:COM_BURST_VAL" title="GTX0:COM_BURST_VAL[1]">GTX0:COM_BURST_VAL[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[13]">GTX0:DRP24[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:COM_BURST_VAL" title="GTX0:COM_BURST_VAL[2]">GTX0:COM_BURST_VAL[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[14]">GTX0:DRP24[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:COM_BURST_VAL" title="GTX0:COM_BURST_VAL[3]">GTX0:COM_BURST_VAL[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP24" title="GTX0:DRP24[15]">GTX0:DRP24[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[0]">GTX0:DRP25[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_NON_P2" title="GTX0:TRANS_TIME_NON_P2[0]">GTX0:TRANS_TIME_NON_P2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[1]">GTX0:DRP25[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_NON_P2" title="GTX0:TRANS_TIME_NON_P2[1]">GTX0:TRANS_TIME_NON_P2[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[2]">GTX0:DRP25[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_NON_P2" title="GTX0:TRANS_TIME_NON_P2[2]">GTX0:TRANS_TIME_NON_P2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[3]">GTX0:DRP25[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_NON_P2" title="GTX0:TRANS_TIME_NON_P2[3]">GTX0:TRANS_TIME_NON_P2[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[4]">GTX0:DRP25[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_NON_P2" title="GTX0:TRANS_TIME_NON_P2[4]">GTX0:TRANS_TIME_NON_P2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[5]">GTX0:DRP25[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_NON_P2" title="GTX0:TRANS_TIME_NON_P2[5]">GTX0:TRANS_TIME_NON_P2[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[6]">GTX0:DRP25[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_NON_P2" title="GTX0:TRANS_TIME_NON_P2[6]">GTX0:TRANS_TIME_NON_P2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[7]">GTX0:DRP25[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_NON_P2" title="GTX0:TRANS_TIME_NON_P2[7]">GTX0:TRANS_TIME_NON_P2[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:CM_TRIM" title="GTX0:CM_TRIM[0]">GTX0:CM_TRIM[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[8]">GTX0:DRP25[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:CM_TRIM" title="GTX0:CM_TRIM[1]">GTX0:CM_TRIM[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[9]">GTX0:DRP25[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_RXPOLARITY" title="GTX0:A_RXPOLARITY">GTX0:A_RXPOLARITY</a><br><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[10]">GTX0:DRP25[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPOLARITY" title="GTX0:A_TXPOLARITY">GTX0:A_TXPOLARITY</a><br><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[11]">GTX0:DRP25[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[12]">GTX0:DRP25[12]</a><br><a href="#bits-xc6v-GTX-GTX0:POLARITY_DRP_EN" title="GTX0:POLARITY_DRP_EN">GTX0:POLARITY_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_RXPMASETPHASE" title="GTX0:A_RXPMASETPHASE">GTX0:A_RXPMASETPHASE</a><br><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[13]">GTX0:DRP25[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_RXENPMAPHASEALIGN" title="GTX0:A_RXENPMAPHASEALIGN">GTX0:A_RXENPMAPHASEALIGN</a><br><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[14]">GTX0:DRP25[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP25" title="GTX0:DRP25[15]">GTX0:DRP25[15]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_PMADATA_OPT" title="GTX0:TX_PMADATA_OPT">GTX0:TX_PMADATA_OPT</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[0]">GTX0:DRP26[0]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_WAKE" title="GTX0:SATA_MAX_WAKE[0]">GTX0:SATA_MAX_WAKE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[1]">GTX0:DRP26[1]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_WAKE" title="GTX0:SATA_MAX_WAKE[1]">GTX0:SATA_MAX_WAKE[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[2]">GTX0:DRP26[2]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_WAKE" title="GTX0:SATA_MAX_WAKE[2]">GTX0:SATA_MAX_WAKE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[3]">GTX0:DRP26[3]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_WAKE" title="GTX0:SATA_MAX_WAKE[3]">GTX0:SATA_MAX_WAKE[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[4]">GTX0:DRP26[4]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_WAKE" title="GTX0:SATA_MAX_WAKE[4]">GTX0:SATA_MAX_WAKE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[5]">GTX0:DRP26[5]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_WAKE" title="GTX0:SATA_MAX_WAKE[5]">GTX0:SATA_MAX_WAKE[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[6]">GTX0:DRP26[6]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_WAKE" title="GTX0:SATA_MIN_WAKE[0]">GTX0:SATA_MIN_WAKE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[7]">GTX0:DRP26[7]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_WAKE" title="GTX0:SATA_MIN_WAKE[1]">GTX0:SATA_MIN_WAKE[1]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[8]">GTX0:DRP26[8]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_WAKE" title="GTX0:SATA_MIN_WAKE[2]">GTX0:SATA_MIN_WAKE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[9]">GTX0:DRP26[9]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_WAKE" title="GTX0:SATA_MIN_WAKE[3]">GTX0:SATA_MIN_WAKE[3]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[10]">GTX0:DRP26[10]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_WAKE" title="GTX0:SATA_MIN_WAKE[4]">GTX0:SATA_MIN_WAKE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[11]">GTX0:DRP26[11]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_WAKE" title="GTX0:SATA_MIN_WAKE[5]">GTX0:SATA_MIN_WAKE[5]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[12]">GTX0:DRP26[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_SATA" title="GTX0:TXPLL_SATA[0]">GTX0:TXPLL_SATA[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[13]">GTX0:DRP26[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TXPLL_SATA" title="GTX0:TXPLL_SATA[1]">GTX0:TXPLL_SATA[1]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:BGTEST_CFG" title="GTX0:BGTEST_CFG[0]">GTX0:BGTEST_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[14]">GTX0:DRP26[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:BGTEST_CFG" title="GTX0:BGTEST_CFG[1]">GTX0:BGTEST_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP26" title="GTX0:DRP26[15]">GTX0:DRP26[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[0]">GTX0:DRP27[0]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_INIT" title="GTX0:SATA_MAX_INIT[0]">GTX0:SATA_MAX_INIT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[1]">GTX0:DRP27[1]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_INIT" title="GTX0:SATA_MAX_INIT[1]">GTX0:SATA_MAX_INIT[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[2]">GTX0:DRP27[2]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_INIT" title="GTX0:SATA_MAX_INIT[2]">GTX0:SATA_MAX_INIT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[3]">GTX0:DRP27[3]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_INIT" title="GTX0:SATA_MAX_INIT[3]">GTX0:SATA_MAX_INIT[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[4]">GTX0:DRP27[4]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_INIT" title="GTX0:SATA_MAX_INIT[4]">GTX0:SATA_MAX_INIT[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[5]">GTX0:DRP27[5]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_INIT" title="GTX0:SATA_MAX_INIT[5]">GTX0:SATA_MAX_INIT[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[6]">GTX0:DRP27[6]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_INIT" title="GTX0:SATA_MIN_INIT[0]">GTX0:SATA_MIN_INIT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[7]">GTX0:DRP27[7]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_INIT" title="GTX0:SATA_MIN_INIT[1]">GTX0:SATA_MIN_INIT[1]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[8]">GTX0:DRP27[8]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_INIT" title="GTX0:SATA_MIN_INIT[2]">GTX0:SATA_MIN_INIT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[9]">GTX0:DRP27[9]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_INIT" title="GTX0:SATA_MIN_INIT[3]">GTX0:SATA_MIN_INIT[3]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[10]">GTX0:DRP27[10]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_INIT" title="GTX0:SATA_MIN_INIT[4]">GTX0:SATA_MIN_INIT[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[11]">GTX0:DRP27[11]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_INIT" title="GTX0:SATA_MIN_INIT[5]">GTX0:SATA_MIN_INIT[5]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[12]">GTX0:DRP27[12]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_IDLE_VAL" title="GTX0:SATA_IDLE_VAL[0]">GTX0:SATA_IDLE_VAL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[13]">GTX0:DRP27[13]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_IDLE_VAL" title="GTX0:SATA_IDLE_VAL[1]">GTX0:SATA_IDLE_VAL[1]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[14]">GTX0:DRP27[14]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_IDLE_VAL" title="GTX0:SATA_IDLE_VAL[2]">GTX0:SATA_IDLE_VAL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP27" title="GTX0:DRP27[15]">GTX0:DRP27[15]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_EN_RATE_RESET_BUF" title="GTX0:TX_EN_RATE_RESET_BUF">GTX0:TX_EN_RATE_RESET_BUF</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 5</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[0]">GTX0:DRP28[0]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_BURST" title="GTX0:SATA_MAX_BURST[0]">GTX0:SATA_MAX_BURST[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[1]">GTX0:DRP28[1]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_BURST" title="GTX0:SATA_MAX_BURST[1]">GTX0:SATA_MAX_BURST[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[2]">GTX0:DRP28[2]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_BURST" title="GTX0:SATA_MAX_BURST[2]">GTX0:SATA_MAX_BURST[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[3]">GTX0:DRP28[3]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_BURST" title="GTX0:SATA_MAX_BURST[3]">GTX0:SATA_MAX_BURST[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[4]">GTX0:DRP28[4]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_BURST" title="GTX0:SATA_MAX_BURST[4]">GTX0:SATA_MAX_BURST[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[5]">GTX0:DRP28[5]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MAX_BURST" title="GTX0:SATA_MAX_BURST[5]">GTX0:SATA_MAX_BURST[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[6]">GTX0:DRP28[6]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_BURST" title="GTX0:SATA_MIN_BURST[0]">GTX0:SATA_MIN_BURST[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[7]">GTX0:DRP28[7]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_BURST" title="GTX0:SATA_MIN_BURST[1]">GTX0:SATA_MIN_BURST[1]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[8]">GTX0:DRP28[8]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_BURST" title="GTX0:SATA_MIN_BURST[2]">GTX0:SATA_MIN_BURST[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[9]">GTX0:DRP28[9]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_BURST" title="GTX0:SATA_MIN_BURST[3]">GTX0:SATA_MIN_BURST[3]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[10]">GTX0:DRP28[10]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_BURST" title="GTX0:SATA_MIN_BURST[4]">GTX0:SATA_MIN_BURST[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[11]">GTX0:DRP28[11]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_MIN_BURST" title="GTX0:SATA_MIN_BURST[5]">GTX0:SATA_MIN_BURST[5]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[12]">GTX0:DRP28[12]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_BURST_VAL" title="GTX0:SATA_BURST_VAL[0]">GTX0:SATA_BURST_VAL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[13]">GTX0:DRP28[13]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_BURST_VAL" title="GTX0:SATA_BURST_VAL[1]">GTX0:SATA_BURST_VAL[1]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[14]">GTX0:DRP28[14]</a><br><a href="#bits-xc6v-GTX-GTX0:SATA_BURST_VAL" title="GTX0:SATA_BURST_VAL[2]">GTX0:SATA_BURST_VAL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP28" title="GTX0:DRP28[15]">GTX0:DRP28[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[0]">GTX0:DRP29[0]</a><br><a href="#bits-xc6v-GTX-GTX0:SAS_MAX_COMSAS" title="GTX0:SAS_MAX_COMSAS[0]">GTX0:SAS_MAX_COMSAS[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[1]">GTX0:DRP29[1]</a><br><a href="#bits-xc6v-GTX-GTX0:SAS_MAX_COMSAS" title="GTX0:SAS_MAX_COMSAS[1]">GTX0:SAS_MAX_COMSAS[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[2]">GTX0:DRP29[2]</a><br><a href="#bits-xc6v-GTX-GTX0:SAS_MAX_COMSAS" title="GTX0:SAS_MAX_COMSAS[2]">GTX0:SAS_MAX_COMSAS[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[3]">GTX0:DRP29[3]</a><br><a href="#bits-xc6v-GTX-GTX0:SAS_MAX_COMSAS" title="GTX0:SAS_MAX_COMSAS[3]">GTX0:SAS_MAX_COMSAS[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[4]">GTX0:DRP29[4]</a><br><a href="#bits-xc6v-GTX-GTX0:SAS_MAX_COMSAS" title="GTX0:SAS_MAX_COMSAS[4]">GTX0:SAS_MAX_COMSAS[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[5]">GTX0:DRP29[5]</a><br><a href="#bits-xc6v-GTX-GTX0:SAS_MAX_COMSAS" title="GTX0:SAS_MAX_COMSAS[5]">GTX0:SAS_MAX_COMSAS[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[6]">GTX0:DRP29[6]</a><br><a href="#bits-xc6v-GTX-GTX0:SAS_MIN_COMSAS" title="GTX0:SAS_MIN_COMSAS[0]">GTX0:SAS_MIN_COMSAS[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[7]">GTX0:DRP29[7]</a><br><a href="#bits-xc6v-GTX-GTX0:SAS_MIN_COMSAS" title="GTX0:SAS_MIN_COMSAS[1]">GTX0:SAS_MIN_COMSAS[1]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[8]">GTX0:DRP29[8]</a><br><a href="#bits-xc6v-GTX-GTX0:SAS_MIN_COMSAS" title="GTX0:SAS_MIN_COMSAS[2]">GTX0:SAS_MIN_COMSAS[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[9]">GTX0:DRP29[9]</a><br><a href="#bits-xc6v-GTX-GTX0:SAS_MIN_COMSAS" title="GTX0:SAS_MIN_COMSAS[3]">GTX0:SAS_MIN_COMSAS[3]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[10]">GTX0:DRP29[10]</a><br><a href="#bits-xc6v-GTX-GTX0:SAS_MIN_COMSAS" title="GTX0:SAS_MIN_COMSAS[4]">GTX0:SAS_MIN_COMSAS[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[11]">GTX0:DRP29[11]</a><br><a href="#bits-xc6v-GTX-GTX0:SAS_MIN_COMSAS" title="GTX0:SAS_MIN_COMSAS[5]">GTX0:SAS_MIN_COMSAS[5]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPMASETPHASE" title="GTX0:A_TXPMASETPHASE">GTX0:A_TXPMASETPHASE</a><br><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[12]">GTX0:DRP29[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXENPMAPHASEALIGN" title="GTX0:A_TXENPMAPHASEALIGN">GTX0:A_TXENPMAPHASEALIGN</a><br><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[13]">GTX0:DRP29[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_RXENSAMPLEALIGN" title="GTX0:A_RXENSAMPLEALIGN">GTX0:A_RXENSAMPLEALIGN</a><br><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[14]">GTX0:DRP29[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP29" title="GTX0:DRP29[15]">GTX0:DRP29[15]</a><br><a href="#bits-xc6v-GTX-GTX0:PHASEALIGN_DRP_EN" title="GTX0:PHASEALIGN_DRP_EN">GTX0:PHASEALIGN_DRP_EN</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[0]">GTX0:DRP2A[0]</a><br><a href="#bits-xc6v-GTX-GTX0:LOOPBACK_DRP_EN" title="GTX0:LOOPBACK_DRP_EN">GTX0:LOOPBACK_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_LOOPBACK" title="GTX0:A_LOOPBACK[0]">GTX0:A_LOOPBACK[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[1]">GTX0:DRP2A[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_LOOPBACK" title="GTX0:A_LOOPBACK[1]">GTX0:A_LOOPBACK[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[2]">GTX0:DRP2A[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_LOOPBACK" title="GTX0:A_LOOPBACK[2]">GTX0:A_LOOPBACK[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[3]">GTX0:DRP2A[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[4]">GTX0:DRP2A[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_RXENPRBSTST" title="GTX0:A_RXENPRBSTST[0]">GTX0:A_RXENPRBSTST[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[5]">GTX0:DRP2A[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_RXENPRBSTST" title="GTX0:A_RXENPRBSTST[1]">GTX0:A_RXENPRBSTST[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[6]">GTX0:DRP2A[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_RXENPRBSTST" title="GTX0:A_RXENPRBSTST[2]">GTX0:A_RXENPRBSTST[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[7]">GTX0:DRP2A[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[8]">GTX0:DRP2A[8]</a><br><a href="#bits-xc6v-GTX-GTX0:RXPRBSERR_LOOPBACK" title="GTX0:RXPRBSERR_LOOPBACK">GTX0:RXPRBSERR_LOOPBACK</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[9]">GTX0:DRP2A[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPRBSFORCEERR" title="GTX0:A_TXPRBSFORCEERR">GTX0:A_TXPRBSFORCEERR</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[10]">GTX0:DRP2A[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXENPRBSTST" title="GTX0:A_TXENPRBSTST[0]">GTX0:A_TXENPRBSTST[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[11]">GTX0:DRP2A[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXENPRBSTST" title="GTX0:A_TXENPRBSTST[1]">GTX0:A_TXENPRBSTST[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[12]">GTX0:DRP2A[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXENPRBSTST" title="GTX0:A_TXENPRBSTST[2]">GTX0:A_TXENPRBSTST[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[13]">GTX0:DRP2A[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_PRBSCNTRESET" title="GTX0:A_PRBSCNTRESET">GTX0:A_PRBSCNTRESET</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[14]">GTX0:DRP2A[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2A" title="GTX0:DRP2A[15]">GTX0:DRP2A[15]</a><br><a href="#bits-xc6v-GTX-GTX0:PRBS_DRP_EN" title="GTX0:PRBS_DRP_EN">GTX0:PRBS_DRP_EN</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP1" title="GTX0:A_DFETAP1[0]">GTX0:A_DFETAP1[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[0]">GTX0:DRP2B[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP1" title="GTX0:A_DFETAP1[1]">GTX0:A_DFETAP1[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[1]">GTX0:DRP2B[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP1" title="GTX0:A_DFETAP1[2]">GTX0:A_DFETAP1[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[2]">GTX0:DRP2B[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP1" title="GTX0:A_DFETAP1[3]">GTX0:A_DFETAP1[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[3]">GTX0:DRP2B[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP1" title="GTX0:A_DFETAP1[4]">GTX0:A_DFETAP1[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[4]">GTX0:DRP2B[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP3" title="GTX0:A_DFETAP3[0]">GTX0:A_DFETAP3[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[5]">GTX0:DRP2B[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP3" title="GTX0:A_DFETAP3[1]">GTX0:A_DFETAP3[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[6]">GTX0:DRP2B[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP3" title="GTX0:A_DFETAP3[2]">GTX0:A_DFETAP3[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[7]">GTX0:DRP2B[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP3" title="GTX0:A_DFETAP3[3]">GTX0:A_DFETAP3[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[8]">GTX0:DRP2B[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[9]">GTX0:DRP2B[9]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EN_IDLE_HOLD_CDR" title="GTX0:RX_EN_IDLE_HOLD_CDR">GTX0:RX_EN_IDLE_HOLD_CDR</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[10]">GTX0:DRP2B[10]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EN_IDLE_RESET_FR" title="GTX0:RX_EN_IDLE_RESET_FR">GTX0:RX_EN_IDLE_RESET_FR</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[11]">GTX0:DRP2B[11]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EN_IDLE_HOLD_DFE" title="GTX0:RX_EN_IDLE_HOLD_DFE">GTX0:RX_EN_IDLE_HOLD_DFE</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[12]">GTX0:DRP2B[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[13]">GTX0:DRP2B[13]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_DFEDLYOVRD" title="GTX0:A_DFEDLYOVRD">GTX0:A_DFEDLYOVRD</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[14]">GTX0:DRP2B[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAPOVRD" title="GTX0:A_DFETAPOVRD">GTX0:A_DFETAPOVRD</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2B" title="GTX0:DRP2B[15]">GTX0:DRP2B[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP2" title="GTX0:A_DFETAP2[0]">GTX0:A_DFETAP2[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[0]">GTX0:DRP2C[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP2" title="GTX0:A_DFETAP2[1]">GTX0:A_DFETAP2[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[1]">GTX0:DRP2C[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP2" title="GTX0:A_DFETAP2[2]">GTX0:A_DFETAP2[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[2]">GTX0:DRP2C[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP2" title="GTX0:A_DFETAP2[3]">GTX0:A_DFETAP2[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[3]">GTX0:DRP2C[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP2" title="GTX0:A_DFETAP2[4]">GTX0:A_DFETAP2[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[4]">GTX0:DRP2C[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP4" title="GTX0:A_DFETAP4[0]">GTX0:A_DFETAP4[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[5]">GTX0:DRP2C[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP4" title="GTX0:A_DFETAP4[1]">GTX0:A_DFETAP4[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[6]">GTX0:DRP2C[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP4" title="GTX0:A_DFETAP4[2]">GTX0:A_DFETAP4[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[7]">GTX0:DRP2C[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_DFETAP4" title="GTX0:A_DFETAP4[3]">GTX0:A_DFETAP4[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[8]">GTX0:DRP2C[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_DFECLKDLYADJ" title="GTX0:A_DFECLKDLYADJ[0]">GTX0:A_DFECLKDLYADJ[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[9]">GTX0:DRP2C[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_DFECLKDLYADJ" title="GTX0:A_DFECLKDLYADJ[1]">GTX0:A_DFECLKDLYADJ[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[10]">GTX0:DRP2C[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_DFECLKDLYADJ" title="GTX0:A_DFECLKDLYADJ[2]">GTX0:A_DFECLKDLYADJ[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[11]">GTX0:DRP2C[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_DFECLKDLYADJ" title="GTX0:A_DFECLKDLYADJ[3]">GTX0:A_DFECLKDLYADJ[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[12]">GTX0:DRP2C[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_DFECLKDLYADJ" title="GTX0:A_DFECLKDLYADJ[4]">GTX0:A_DFECLKDLYADJ[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[13]">GTX0:DRP2C[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_DFECLKDLYADJ" title="GTX0:A_DFECLKDLYADJ[5]">GTX0:A_DFECLKDLYADJ[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[14]">GTX0:DRP2C[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DFE_DRP_EN" title="GTX0:DFE_DRP_EN">GTX0:DFE_DRP_EN</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2C" title="GTX0:DRP2C[15]">GTX0:DRP2C[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DFE_CFG" title="GTX0:DFE_CFG[0]">GTX0:DFE_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[0]">GTX0:DRP2D[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DFE_CFG" title="GTX0:DFE_CFG[1]">GTX0:DFE_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[1]">GTX0:DRP2D[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DFE_CFG" title="GTX0:DFE_CFG[2]">GTX0:DFE_CFG[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[2]">GTX0:DRP2D[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DFE_CFG" title="GTX0:DFE_CFG[3]">GTX0:DFE_CFG[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[3]">GTX0:DRP2D[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DFE_CFG" title="GTX0:DFE_CFG[4]">GTX0:DFE_CFG[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[4]">GTX0:DRP2D[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DFE_CFG" title="GTX0:DFE_CFG[5]">GTX0:DFE_CFG[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[5]">GTX0:DRP2D[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DFE_CFG" title="GTX0:DFE_CFG[6]">GTX0:DFE_CFG[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[6]">GTX0:DRP2D[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DFE_CFG" title="GTX0:DFE_CFG[7]">GTX0:DFE_CFG[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[7]">GTX0:DRP2D[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[8]">GTX0:DRP2D[8]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EYE_OFFSET" title="GTX0:RX_EYE_OFFSET[0]">GTX0:RX_EYE_OFFSET[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[9]">GTX0:DRP2D[9]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EYE_OFFSET" title="GTX0:RX_EYE_OFFSET[1]">GTX0:RX_EYE_OFFSET[1]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[10]">GTX0:DRP2D[10]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EYE_OFFSET" title="GTX0:RX_EYE_OFFSET[2]">GTX0:RX_EYE_OFFSET[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[11]">GTX0:DRP2D[11]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EYE_OFFSET" title="GTX0:RX_EYE_OFFSET[3]">GTX0:RX_EYE_OFFSET[3]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[12]">GTX0:DRP2D[12]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EYE_OFFSET" title="GTX0:RX_EYE_OFFSET[4]">GTX0:RX_EYE_OFFSET[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[13]">GTX0:DRP2D[13]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EYE_OFFSET" title="GTX0:RX_EYE_OFFSET[5]">GTX0:RX_EYE_OFFSET[5]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[14]">GTX0:DRP2D[14]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EYE_OFFSET" title="GTX0:RX_EYE_OFFSET[6]">GTX0:RX_EYE_OFFSET[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2D" title="GTX0:DRP2D[15]">GTX0:DRP2D[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EYE_OFFSET" title="GTX0:RX_EYE_OFFSET[7]">GTX0:RX_EYE_OFFSET[7]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[0]">GTX0:DRP2E[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TERMINATION_CTRL" title="GTX0:TERMINATION_CTRL[0]">GTX0:TERMINATION_CTRL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[1]">GTX0:DRP2E[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TERMINATION_CTRL" title="GTX0:TERMINATION_CTRL[1]">GTX0:TERMINATION_CTRL[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[2]">GTX0:DRP2E[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TERMINATION_CTRL" title="GTX0:TERMINATION_CTRL[2]">GTX0:TERMINATION_CTRL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[3]">GTX0:DRP2E[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TERMINATION_CTRL" title="GTX0:TERMINATION_CTRL[3]">GTX0:TERMINATION_CTRL[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[4]">GTX0:DRP2E[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TERMINATION_CTRL" title="GTX0:TERMINATION_CTRL[4]">GTX0:TERMINATION_CTRL[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[5]">GTX0:DRP2E[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[6]">GTX0:DRP2E[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TERMINATION_OVRD" title="GTX0:TERMINATION_OVRD">GTX0:TERMINATION_OVRD</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[7]">GTX0:DRP2E[7]</a><br><a href="#bits-xc6v-GTX-GTX0:RCV_TERM_GND" title="GTX0:RCV_TERM_GND">GTX0:RCV_TERM_GND</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[8]">GTX0:DRP2E[8]</a><br><a href="#bits-xc6v-GTX-GTX0:RCV_TERM_VTTRX" title="GTX0:RCV_TERM_VTTRX">GTX0:RCV_TERM_VTTRX</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[9]">GTX0:DRP2E[9]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EYE_SCANMODE" title="GTX0:RX_EYE_SCANMODE[0]">GTX0:RX_EYE_SCANMODE[0]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[10]">GTX0:DRP2E[10]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EYE_SCANMODE" title="GTX0:RX_EYE_SCANMODE[1]">GTX0:RX_EYE_SCANMODE[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DFE_CAL_TIME" title="GTX0:DFE_CAL_TIME[0]">GTX0:DFE_CAL_TIME[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[11]">GTX0:DRP2E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DFE_CAL_TIME" title="GTX0:DFE_CAL_TIME[1]">GTX0:DFE_CAL_TIME[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[12]">GTX0:DRP2E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DFE_CAL_TIME" title="GTX0:DFE_CAL_TIME[2]">GTX0:DFE_CAL_TIME[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[13]">GTX0:DRP2E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DFE_CAL_TIME" title="GTX0:DFE_CAL_TIME[3]">GTX0:DFE_CAL_TIME[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[14]">GTX0:DRP2E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DFE_CAL_TIME" title="GTX0:DFE_CAL_TIME[4]">GTX0:DFE_CAL_TIME[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2E" title="GTX0:DRP2E[15]">GTX0:DRP2E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:COMMA_10B_ENABLE" title="GTX0:COMMA_10B_ENABLE[0]">GTX0:COMMA_10B_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[0]">GTX0:DRP2F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:COMMA_10B_ENABLE" title="GTX0:COMMA_10B_ENABLE[1]">GTX0:COMMA_10B_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[1]">GTX0:DRP2F[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:COMMA_10B_ENABLE" title="GTX0:COMMA_10B_ENABLE[2]">GTX0:COMMA_10B_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[2]">GTX0:DRP2F[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:COMMA_10B_ENABLE" title="GTX0:COMMA_10B_ENABLE[3]">GTX0:COMMA_10B_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[3]">GTX0:DRP2F[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:COMMA_10B_ENABLE" title="GTX0:COMMA_10B_ENABLE[4]">GTX0:COMMA_10B_ENABLE[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[4]">GTX0:DRP2F[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:COMMA_10B_ENABLE" title="GTX0:COMMA_10B_ENABLE[5]">GTX0:COMMA_10B_ENABLE[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[5]">GTX0:DRP2F[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:COMMA_10B_ENABLE" title="GTX0:COMMA_10B_ENABLE[6]">GTX0:COMMA_10B_ENABLE[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[6]">GTX0:DRP2F[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:COMMA_10B_ENABLE" title="GTX0:COMMA_10B_ENABLE[7]">GTX0:COMMA_10B_ENABLE[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[7]">GTX0:DRP2F[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:COMMA_10B_ENABLE" title="GTX0:COMMA_10B_ENABLE[8]">GTX0:COMMA_10B_ENABLE[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[8]">GTX0:DRP2F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:COMMA_10B_ENABLE" title="GTX0:COMMA_10B_ENABLE[9]">GTX0:COMMA_10B_ENABLE[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[9]">GTX0:DRP2F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:COMMA_DOUBLE" title="GTX0:COMMA_DOUBLE">GTX0:COMMA_DOUBLE</a><br><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[10]">GTX0:DRP2F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[11]">GTX0:DRP2F[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_IDLE_ASSERT_DELAY" title="GTX0:TX_IDLE_ASSERT_DELAY[0]">GTX0:TX_IDLE_ASSERT_DELAY[0]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[12]">GTX0:DRP2F[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_IDLE_ASSERT_DELAY" title="GTX0:TX_IDLE_ASSERT_DELAY[1]">GTX0:TX_IDLE_ASSERT_DELAY[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[13]">GTX0:DRP2F[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_IDLE_ASSERT_DELAY" title="GTX0:TX_IDLE_ASSERT_DELAY[2]">GTX0:TX_IDLE_ASSERT_DELAY[2]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[14]">GTX0:DRP2F[14]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_XCLK_SEL" title="GTX0:TX_XCLK_SEL">GTX0:TX_XCLK_SEL</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP2F" title="GTX0:DRP2F[15]">GTX0:DRP2F[15]</a><br><a href="#bits-xc6v-GTX-GTX0:TXGEARBOX_USE" title="GTX0:TXGEARBOX_USE">GTX0:TXGEARBOX_USE</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 6</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[0]">GTX0:DRP30[0]</a><br><a href="#bits-xc6v-GTX-GTX0:MCOMMA_10B_VALUE" title="GTX0:MCOMMA_10B_VALUE[0]">GTX0:MCOMMA_10B_VALUE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[1]">GTX0:DRP30[1]</a><br><a href="#bits-xc6v-GTX-GTX0:MCOMMA_10B_VALUE" title="GTX0:MCOMMA_10B_VALUE[1]">GTX0:MCOMMA_10B_VALUE[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[2]">GTX0:DRP30[2]</a><br><a href="#bits-xc6v-GTX-GTX0:MCOMMA_10B_VALUE" title="GTX0:MCOMMA_10B_VALUE[2]">GTX0:MCOMMA_10B_VALUE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[3]">GTX0:DRP30[3]</a><br><a href="#bits-xc6v-GTX-GTX0:MCOMMA_10B_VALUE" title="GTX0:MCOMMA_10B_VALUE[3]">GTX0:MCOMMA_10B_VALUE[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[4]">GTX0:DRP30[4]</a><br><a href="#bits-xc6v-GTX-GTX0:MCOMMA_10B_VALUE" title="GTX0:MCOMMA_10B_VALUE[4]">GTX0:MCOMMA_10B_VALUE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[5]">GTX0:DRP30[5]</a><br><a href="#bits-xc6v-GTX-GTX0:MCOMMA_10B_VALUE" title="GTX0:MCOMMA_10B_VALUE[5]">GTX0:MCOMMA_10B_VALUE[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[6]">GTX0:DRP30[6]</a><br><a href="#bits-xc6v-GTX-GTX0:MCOMMA_10B_VALUE" title="GTX0:MCOMMA_10B_VALUE[6]">GTX0:MCOMMA_10B_VALUE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[7]">GTX0:DRP30[7]</a><br><a href="#bits-xc6v-GTX-GTX0:MCOMMA_10B_VALUE" title="GTX0:MCOMMA_10B_VALUE[7]">GTX0:MCOMMA_10B_VALUE[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[8]">GTX0:DRP30[8]</a><br><a href="#bits-xc6v-GTX-GTX0:MCOMMA_10B_VALUE" title="GTX0:MCOMMA_10B_VALUE[8]">GTX0:MCOMMA_10B_VALUE[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[9]">GTX0:DRP30[9]</a><br><a href="#bits-xc6v-GTX-GTX0:MCOMMA_10B_VALUE" title="GTX0:MCOMMA_10B_VALUE[9]">GTX0:MCOMMA_10B_VALUE[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[10]">GTX0:DRP30[10]</a><br><a href="#bits-xc6v-GTX-GTX0:MCOMMA_DETECT" title="GTX0:MCOMMA_DETECT">GTX0:MCOMMA_DETECT</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[11]">GTX0:DRP30[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_IDLE_DEASSERT_DELAY" title="GTX0:TX_IDLE_DEASSERT_DELAY[0]">GTX0:TX_IDLE_DEASSERT_DELAY[0]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[12]">GTX0:DRP30[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_IDLE_DEASSERT_DELAY" title="GTX0:TX_IDLE_DEASSERT_DELAY[1]">GTX0:TX_IDLE_DEASSERT_DELAY[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[13]">GTX0:DRP30[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_IDLE_DEASSERT_DELAY" title="GTX0:TX_IDLE_DEASSERT_DELAY[2]">GTX0:TX_IDLE_DEASSERT_DELAY[2]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[14]">GTX0:DRP30[14]</a><br><a href="#bits-xc6v-GTX-GTX0:INV.TXUSRCLK" title="~GTX0:INV.TXUSRCLK">~GTX0:INV.TXUSRCLK</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP30" title="GTX0:DRP30[15]">GTX0:DRP30[15]</a><br><a href="#bits-xc6v-GTX-GTX0:INV.TXUSRCLK2" title="~GTX0:INV.TXUSRCLK2">~GTX0:INV.TXUSRCLK2</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[0]">GTX0:DRP31[0]</a><br><a href="#bits-xc6v-GTX-GTX0:PCOMMA_10B_VALUE" title="GTX0:PCOMMA_10B_VALUE[0]">GTX0:PCOMMA_10B_VALUE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[1]">GTX0:DRP31[1]</a><br><a href="#bits-xc6v-GTX-GTX0:PCOMMA_10B_VALUE" title="GTX0:PCOMMA_10B_VALUE[1]">GTX0:PCOMMA_10B_VALUE[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[2]">GTX0:DRP31[2]</a><br><a href="#bits-xc6v-GTX-GTX0:PCOMMA_10B_VALUE" title="GTX0:PCOMMA_10B_VALUE[2]">GTX0:PCOMMA_10B_VALUE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[3]">GTX0:DRP31[3]</a><br><a href="#bits-xc6v-GTX-GTX0:PCOMMA_10B_VALUE" title="GTX0:PCOMMA_10B_VALUE[3]">GTX0:PCOMMA_10B_VALUE[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[4]">GTX0:DRP31[4]</a><br><a href="#bits-xc6v-GTX-GTX0:PCOMMA_10B_VALUE" title="GTX0:PCOMMA_10B_VALUE[4]">GTX0:PCOMMA_10B_VALUE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[5]">GTX0:DRP31[5]</a><br><a href="#bits-xc6v-GTX-GTX0:PCOMMA_10B_VALUE" title="GTX0:PCOMMA_10B_VALUE[5]">GTX0:PCOMMA_10B_VALUE[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[6]">GTX0:DRP31[6]</a><br><a href="#bits-xc6v-GTX-GTX0:PCOMMA_10B_VALUE" title="GTX0:PCOMMA_10B_VALUE[6]">GTX0:PCOMMA_10B_VALUE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[7]">GTX0:DRP31[7]</a><br><a href="#bits-xc6v-GTX-GTX0:PCOMMA_10B_VALUE" title="GTX0:PCOMMA_10B_VALUE[7]">GTX0:PCOMMA_10B_VALUE[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[8]">GTX0:DRP31[8]</a><br><a href="#bits-xc6v-GTX-GTX0:PCOMMA_10B_VALUE" title="GTX0:PCOMMA_10B_VALUE[8]">GTX0:PCOMMA_10B_VALUE[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[9]">GTX0:DRP31[9]</a><br><a href="#bits-xc6v-GTX-GTX0:PCOMMA_10B_VALUE" title="GTX0:PCOMMA_10B_VALUE[9]">GTX0:PCOMMA_10B_VALUE[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[10]">GTX0:DRP31[10]</a><br><a href="#bits-xc6v-GTX-GTX0:PCOMMA_DETECT" title="GTX0:PCOMMA_DETECT">GTX0:PCOMMA_DETECT</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[11]">GTX0:DRP31[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_BUFFER_USE" title="GTX0:TX_BUFFER_USE">GTX0:TX_BUFFER_USE</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[12]">GTX0:DRP31[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DATA_WIDTH" title="GTX0:TX_DATA_WIDTH[0]">GTX0:TX_DATA_WIDTH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[13]">GTX0:DRP31[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DATA_WIDTH" title="GTX0:TX_DATA_WIDTH[1]">GTX0:TX_DATA_WIDTH[1]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[14]">GTX0:DRP31[14]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DATA_WIDTH" title="GTX0:TX_DATA_WIDTH[2]">GTX0:TX_DATA_WIDTH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP31" title="GTX0:DRP31[15]">GTX0:DRP31[15]</a><br><a href="#bits-xc6v-GTX-GTX0:GEN_TXUSRCLK" title="GTX0:GEN_TXUSRCLK">GTX0:GEN_TXUSRCLK</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[0]">GTX0:DRP32[0]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[0]">GTX0:PMA_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[1]">GTX0:DRP32[1]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[1]">GTX0:PMA_CFG[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[2]">GTX0:DRP32[2]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[2]">GTX0:PMA_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[3]">GTX0:DRP32[3]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[3]">GTX0:PMA_CFG[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[4]">GTX0:DRP32[4]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[4]">GTX0:PMA_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[5]">GTX0:DRP32[5]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[5]">GTX0:PMA_CFG[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[6]">GTX0:DRP32[6]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[6]">GTX0:PMA_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[7]">GTX0:DRP32[7]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[7]">GTX0:PMA_CFG[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[8]">GTX0:DRP32[8]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[8]">GTX0:PMA_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[9]">GTX0:DRP32[9]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[9]">GTX0:PMA_CFG[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[10]">GTX0:DRP32[10]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[10]">GTX0:PMA_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[11]">GTX0:DRP32[11]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[11]">GTX0:PMA_CFG[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[12]">GTX0:DRP32[12]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[12]">GTX0:PMA_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[13]">GTX0:DRP32[13]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[13]">GTX0:PMA_CFG[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[14]">GTX0:DRP32[14]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[14]">GTX0:PMA_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP32" title="GTX0:DRP32[15]">GTX0:DRP32[15]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[15]">GTX0:PMA_CFG[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[0]">GTX0:DRP33[0]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[16]">GTX0:PMA_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[1]">GTX0:DRP33[1]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[17]">GTX0:PMA_CFG[17]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[2]">GTX0:DRP33[2]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[18]">GTX0:PMA_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[3]">GTX0:DRP33[3]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[19]">GTX0:PMA_CFG[19]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[4]">GTX0:DRP33[4]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[20]">GTX0:PMA_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[5]">GTX0:DRP33[5]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[21]">GTX0:PMA_CFG[21]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[6]">GTX0:DRP33[6]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[22]">GTX0:PMA_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[7]">GTX0:DRP33[7]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[23]">GTX0:PMA_CFG[23]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[8]">GTX0:DRP33[8]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[24]">GTX0:PMA_CFG[24]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[9]">GTX0:DRP33[9]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[25]">GTX0:PMA_CFG[25]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[10]">GTX0:DRP33[10]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[26]">GTX0:PMA_CFG[26]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[11]">GTX0:DRP33[11]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[27]">GTX0:PMA_CFG[27]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[12]">GTX0:DRP33[12]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[28]">GTX0:PMA_CFG[28]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[13]">GTX0:DRP33[13]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[29]">GTX0:PMA_CFG[29]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[14]">GTX0:DRP33[14]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[30]">GTX0:PMA_CFG[30]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP33" title="GTX0:DRP33[15]">GTX0:DRP33[15]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[31]">GTX0:PMA_CFG[31]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[0]">GTX0:DRP34[0]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[32]">GTX0:PMA_CFG[32]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[1]">GTX0:DRP34[1]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[33]">GTX0:PMA_CFG[33]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[2]">GTX0:DRP34[2]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[34]">GTX0:PMA_CFG[34]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[3]">GTX0:DRP34[3]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[35]">GTX0:PMA_CFG[35]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[4]">GTX0:DRP34[4]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[36]">GTX0:PMA_CFG[36]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[5]">GTX0:DRP34[5]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[37]">GTX0:PMA_CFG[37]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[6]">GTX0:DRP34[6]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[38]">GTX0:PMA_CFG[38]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[7]">GTX0:DRP34[7]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[39]">GTX0:PMA_CFG[39]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[8]">GTX0:DRP34[8]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[40]">GTX0:PMA_CFG[40]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[9]">GTX0:DRP34[9]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[41]">GTX0:PMA_CFG[41]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[10]">GTX0:DRP34[10]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[42]">GTX0:PMA_CFG[42]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[11]">GTX0:DRP34[11]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[43]">GTX0:PMA_CFG[43]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[12]">GTX0:DRP34[12]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[44]">GTX0:PMA_CFG[44]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[13]">GTX0:DRP34[13]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[45]">GTX0:PMA_CFG[45]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[14]">GTX0:DRP34[14]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[46]">GTX0:PMA_CFG[46]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP34" title="GTX0:DRP34[15]">GTX0:DRP34[15]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[47]">GTX0:PMA_CFG[47]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[0]">GTX0:DRP35[0]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[48]">GTX0:PMA_CFG[48]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[1]">GTX0:DRP35[1]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[49]">GTX0:PMA_CFG[49]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[2]">GTX0:DRP35[2]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[50]">GTX0:PMA_CFG[50]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[3]">GTX0:DRP35[3]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[51]">GTX0:PMA_CFG[51]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[4]">GTX0:DRP35[4]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[52]">GTX0:PMA_CFG[52]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[5]">GTX0:DRP35[5]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[53]">GTX0:PMA_CFG[53]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[6]">GTX0:DRP35[6]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[54]">GTX0:PMA_CFG[54]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[7]">GTX0:DRP35[7]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[55]">GTX0:PMA_CFG[55]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[8]">GTX0:DRP35[8]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[56]">GTX0:PMA_CFG[56]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[9]">GTX0:DRP35[9]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[57]">GTX0:PMA_CFG[57]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[10]">GTX0:DRP35[10]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[58]">GTX0:PMA_CFG[58]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[11]">GTX0:DRP35[11]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[59]">GTX0:PMA_CFG[59]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[12]">GTX0:DRP35[12]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[60]">GTX0:PMA_CFG[60]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[13]">GTX0:DRP35[13]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[61]">GTX0:PMA_CFG[61]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[14]">GTX0:DRP35[14]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[62]">GTX0:PMA_CFG[62]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP35" title="GTX0:DRP35[15]">GTX0:DRP35[15]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[63]">GTX0:PMA_CFG[63]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[0]">GTX0:DRP36[0]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[16]">GTX0:PMA_TX_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[1]">GTX0:DRP36[1]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[17]">GTX0:PMA_TX_CFG[17]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[2]">GTX0:DRP36[2]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[18]">GTX0:PMA_TX_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[3]">GTX0:DRP36[3]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[19]">GTX0:PMA_TX_CFG[19]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[4]">GTX0:DRP36[4]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[64]">GTX0:PMA_CFG[64]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[5]">GTX0:DRP36[5]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[65]">GTX0:PMA_CFG[65]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[6]">GTX0:DRP36[6]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[66]">GTX0:PMA_CFG[66]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[7]">GTX0:DRP36[7]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[67]">GTX0:PMA_CFG[67]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[8]">GTX0:DRP36[8]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[68]">GTX0:PMA_CFG[68]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[9]">GTX0:DRP36[9]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[69]">GTX0:PMA_CFG[69]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[10]">GTX0:DRP36[10]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[70]">GTX0:PMA_CFG[70]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[11]">GTX0:DRP36[11]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[71]">GTX0:PMA_CFG[71]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[12]">GTX0:DRP36[12]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[72]">GTX0:PMA_CFG[72]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[13]">GTX0:DRP36[13]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[73]">GTX0:PMA_CFG[73]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[14]">GTX0:DRP36[14]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[74]">GTX0:PMA_CFG[74]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP36" title="GTX0:DRP36[15]">GTX0:DRP36[15]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_CFG" title="GTX0:PMA_CFG[75]">GTX0:PMA_CFG[75]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[0]">GTX0:DRP37[0]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[0]">GTX0:PMA_TX_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[1]">GTX0:DRP37[1]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[1]">GTX0:PMA_TX_CFG[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[2]">GTX0:DRP37[2]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[2]">GTX0:PMA_TX_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[3]">GTX0:DRP37[3]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[3]">GTX0:PMA_TX_CFG[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[4]">GTX0:DRP37[4]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[4]">GTX0:PMA_TX_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[5]">GTX0:DRP37[5]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[5]">GTX0:PMA_TX_CFG[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[6]">GTX0:DRP37[6]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[6]">GTX0:PMA_TX_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[7]">GTX0:DRP37[7]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[7]">GTX0:PMA_TX_CFG[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[8]">GTX0:DRP37[8]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[8]">GTX0:PMA_TX_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[9]">GTX0:DRP37[9]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[9]">GTX0:PMA_TX_CFG[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[10]">GTX0:DRP37[10]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[10]">GTX0:PMA_TX_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[11]">GTX0:DRP37[11]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[11]">GTX0:PMA_TX_CFG[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[12]">GTX0:DRP37[12]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[12]">GTX0:PMA_TX_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[13]">GTX0:DRP37[13]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[13]">GTX0:PMA_TX_CFG[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[14]">GTX0:DRP37[14]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[14]">GTX0:PMA_TX_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP37" title="GTX0:DRP37[15]">GTX0:DRP37[15]</a><br><a href="#bits-xc6v-GTX-GTX0:PMA_TX_CFG" title="GTX0:PMA_TX_CFG[15]">GTX0:PMA_TX_CFG[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 7</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[0]">GTX0:DRP38[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_0" title="GTX0:TX_MARGIN_LOW_0[0]">GTX0:TX_MARGIN_LOW_0[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[1]">GTX0:DRP38[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_0" title="GTX0:TX_MARGIN_LOW_0[1]">GTX0:TX_MARGIN_LOW_0[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[2]">GTX0:DRP38[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_0" title="GTX0:TX_MARGIN_LOW_0[2]">GTX0:TX_MARGIN_LOW_0[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[3]">GTX0:DRP38[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_0" title="GTX0:TX_MARGIN_LOW_0[3]">GTX0:TX_MARGIN_LOW_0[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[4]">GTX0:DRP38[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_0" title="GTX0:TX_MARGIN_LOW_0[4]">GTX0:TX_MARGIN_LOW_0[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[5]">GTX0:DRP38[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_0" title="GTX0:TX_MARGIN_LOW_0[5]">GTX0:TX_MARGIN_LOW_0[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[6]">GTX0:DRP38[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_0" title="GTX0:TX_MARGIN_LOW_0[6]">GTX0:TX_MARGIN_LOW_0[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[7]">GTX0:DRP38[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_0" title="GTX0:TX_MARGIN_FULL_0[0]">GTX0:TX_MARGIN_FULL_0[0]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[8]">GTX0:DRP38[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_0" title="GTX0:TX_MARGIN_FULL_0[1]">GTX0:TX_MARGIN_FULL_0[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[9]">GTX0:DRP38[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_0" title="GTX0:TX_MARGIN_FULL_0[2]">GTX0:TX_MARGIN_FULL_0[2]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[10]">GTX0:DRP38[10]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_0" title="GTX0:TX_MARGIN_FULL_0[3]">GTX0:TX_MARGIN_FULL_0[3]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[11]">GTX0:DRP38[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_0" title="GTX0:TX_MARGIN_FULL_0[4]">GTX0:TX_MARGIN_FULL_0[4]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[12]">GTX0:DRP38[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_0" title="GTX0:TX_MARGIN_FULL_0[5]">GTX0:TX_MARGIN_FULL_0[5]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[13]">GTX0:DRP38[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_0" title="GTX0:TX_MARGIN_FULL_0[6]">GTX0:TX_MARGIN_FULL_0[6]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[14]">GTX0:DRP38[14]</a><br><a href="#bits-xc6v-GTX-GTX0:TXOUTCLKPCS_SEL" title="GTX0:TXOUTCLKPCS_SEL">GTX0:TXOUTCLKPCS_SEL</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP38" title="GTX0:DRP38[15]">GTX0:DRP38[15]</a><br><a href="#bits-xc6v-GTX-GTX0:INV.DCLK" title="~GTX0:INV.DCLK">~GTX0:INV.DCLK</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[0]">GTX0:DRP39[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_1" title="GTX0:TX_MARGIN_LOW_1[0]">GTX0:TX_MARGIN_LOW_1[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[1]">GTX0:DRP39[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_1" title="GTX0:TX_MARGIN_LOW_1[1]">GTX0:TX_MARGIN_LOW_1[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[2]">GTX0:DRP39[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_1" title="GTX0:TX_MARGIN_LOW_1[2]">GTX0:TX_MARGIN_LOW_1[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[3]">GTX0:DRP39[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_1" title="GTX0:TX_MARGIN_LOW_1[3]">GTX0:TX_MARGIN_LOW_1[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[4]">GTX0:DRP39[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_1" title="GTX0:TX_MARGIN_LOW_1[4]">GTX0:TX_MARGIN_LOW_1[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[5]">GTX0:DRP39[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_1" title="GTX0:TX_MARGIN_LOW_1[5]">GTX0:TX_MARGIN_LOW_1[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[6]">GTX0:DRP39[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_1" title="GTX0:TX_MARGIN_LOW_1[6]">GTX0:TX_MARGIN_LOW_1[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[7]">GTX0:DRP39[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_1" title="GTX0:TX_MARGIN_FULL_1[0]">GTX0:TX_MARGIN_FULL_1[0]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[8]">GTX0:DRP39[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_1" title="GTX0:TX_MARGIN_FULL_1[1]">GTX0:TX_MARGIN_FULL_1[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[9]">GTX0:DRP39[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_1" title="GTX0:TX_MARGIN_FULL_1[2]">GTX0:TX_MARGIN_FULL_1[2]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[10]">GTX0:DRP39[10]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_1" title="GTX0:TX_MARGIN_FULL_1[3]">GTX0:TX_MARGIN_FULL_1[3]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[11]">GTX0:DRP39[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_1" title="GTX0:TX_MARGIN_FULL_1[4]">GTX0:TX_MARGIN_FULL_1[4]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[12]">GTX0:DRP39[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_1" title="GTX0:TX_MARGIN_FULL_1[5]">GTX0:TX_MARGIN_FULL_1[5]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[13]">GTX0:DRP39[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_1" title="GTX0:TX_MARGIN_FULL_1[6]">GTX0:TX_MARGIN_FULL_1[6]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[14]">GTX0:DRP39[14]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_TDCC_CFG" title="GTX0:TX_TDCC_CFG[0]">GTX0:TX_TDCC_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP39" title="GTX0:DRP39[15]">GTX0:DRP39[15]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_TDCC_CFG" title="GTX0:TX_TDCC_CFG[1]">GTX0:TX_TDCC_CFG[1]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[0]">GTX0:DRP3A[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_2" title="GTX0:TX_MARGIN_LOW_2[0]">GTX0:TX_MARGIN_LOW_2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[1]">GTX0:DRP3A[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_2" title="GTX0:TX_MARGIN_LOW_2[1]">GTX0:TX_MARGIN_LOW_2[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[2]">GTX0:DRP3A[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_2" title="GTX0:TX_MARGIN_LOW_2[2]">GTX0:TX_MARGIN_LOW_2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[3]">GTX0:DRP3A[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_2" title="GTX0:TX_MARGIN_LOW_2[3]">GTX0:TX_MARGIN_LOW_2[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[4]">GTX0:DRP3A[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_2" title="GTX0:TX_MARGIN_LOW_2[4]">GTX0:TX_MARGIN_LOW_2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[5]">GTX0:DRP3A[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_2" title="GTX0:TX_MARGIN_LOW_2[5]">GTX0:TX_MARGIN_LOW_2[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[6]">GTX0:DRP3A[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_2" title="GTX0:TX_MARGIN_LOW_2[6]">GTX0:TX_MARGIN_LOW_2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[7]">GTX0:DRP3A[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_2" title="GTX0:TX_MARGIN_FULL_2[0]">GTX0:TX_MARGIN_FULL_2[0]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[8]">GTX0:DRP3A[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_2" title="GTX0:TX_MARGIN_FULL_2[1]">GTX0:TX_MARGIN_FULL_2[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[9]">GTX0:DRP3A[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_2" title="GTX0:TX_MARGIN_FULL_2[2]">GTX0:TX_MARGIN_FULL_2[2]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[10]">GTX0:DRP3A[10]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_2" title="GTX0:TX_MARGIN_FULL_2[3]">GTX0:TX_MARGIN_FULL_2[3]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[11]">GTX0:DRP3A[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_2" title="GTX0:TX_MARGIN_FULL_2[4]">GTX0:TX_MARGIN_FULL_2[4]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[12]">GTX0:DRP3A[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_2" title="GTX0:TX_MARGIN_FULL_2[5]">GTX0:TX_MARGIN_FULL_2[5]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[13]">GTX0:DRP3A[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_2" title="GTX0:TX_MARGIN_FULL_2[6]">GTX0:TX_MARGIN_FULL_2[6]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[14]">GTX0:DRP3A[14]</a><br><a href="#bits-xc6v-GTX-GTX0:TXDRIVE_LOOPBACK_HIZ" title="~GTX0:TXDRIVE_LOOPBACK_HIZ">~GTX0:TXDRIVE_LOOPBACK_HIZ</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3A" title="GTX0:DRP3A[15]">GTX0:DRP3A[15]</a><br><a href="#bits-xc6v-GTX-GTX0:TXDRIVE_LOOPBACK_PD" title="~GTX0:TXDRIVE_LOOPBACK_PD">~GTX0:TXDRIVE_LOOPBACK_PD</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[0]">GTX0:DRP3B[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_3" title="GTX0:TX_MARGIN_LOW_3[0]">GTX0:TX_MARGIN_LOW_3[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[1]">GTX0:DRP3B[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_3" title="GTX0:TX_MARGIN_LOW_3[1]">GTX0:TX_MARGIN_LOW_3[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[2]">GTX0:DRP3B[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_3" title="GTX0:TX_MARGIN_LOW_3[2]">GTX0:TX_MARGIN_LOW_3[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[3]">GTX0:DRP3B[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_3" title="GTX0:TX_MARGIN_LOW_3[3]">GTX0:TX_MARGIN_LOW_3[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[4]">GTX0:DRP3B[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_3" title="GTX0:TX_MARGIN_LOW_3[4]">GTX0:TX_MARGIN_LOW_3[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[5]">GTX0:DRP3B[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_3" title="GTX0:TX_MARGIN_LOW_3[5]">GTX0:TX_MARGIN_LOW_3[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[6]">GTX0:DRP3B[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_3" title="GTX0:TX_MARGIN_LOW_3[6]">GTX0:TX_MARGIN_LOW_3[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[7]">GTX0:DRP3B[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_3" title="GTX0:TX_MARGIN_FULL_3[0]">GTX0:TX_MARGIN_FULL_3[0]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[8]">GTX0:DRP3B[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_3" title="GTX0:TX_MARGIN_FULL_3[1]">GTX0:TX_MARGIN_FULL_3[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[9]">GTX0:DRP3B[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_3" title="GTX0:TX_MARGIN_FULL_3[2]">GTX0:TX_MARGIN_FULL_3[2]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[10]">GTX0:DRP3B[10]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_3" title="GTX0:TX_MARGIN_FULL_3[3]">GTX0:TX_MARGIN_FULL_3[3]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[11]">GTX0:DRP3B[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_3" title="GTX0:TX_MARGIN_FULL_3[4]">GTX0:TX_MARGIN_FULL_3[4]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[12]">GTX0:DRP3B[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_3" title="GTX0:TX_MARGIN_FULL_3[5]">GTX0:TX_MARGIN_FULL_3[5]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[13]">GTX0:DRP3B[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_3" title="GTX0:TX_MARGIN_FULL_3[6]">GTX0:TX_MARGIN_FULL_3[6]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXSWING" title="GTX0:A_TXSWING">GTX0:A_TXSWING</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[14]">GTX0:DRP3B[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXDEEMPH" title="GTX0:A_TXDEEMPH">GTX0:A_TXDEEMPH</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3B" title="GTX0:DRP3B[15]">GTX0:DRP3B[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[0]">GTX0:DRP3C[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_4" title="GTX0:TX_MARGIN_LOW_4[0]">GTX0:TX_MARGIN_LOW_4[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[1]">GTX0:DRP3C[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_4" title="GTX0:TX_MARGIN_LOW_4[1]">GTX0:TX_MARGIN_LOW_4[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[2]">GTX0:DRP3C[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_4" title="GTX0:TX_MARGIN_LOW_4[2]">GTX0:TX_MARGIN_LOW_4[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[3]">GTX0:DRP3C[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_4" title="GTX0:TX_MARGIN_LOW_4[3]">GTX0:TX_MARGIN_LOW_4[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[4]">GTX0:DRP3C[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_4" title="GTX0:TX_MARGIN_LOW_4[4]">GTX0:TX_MARGIN_LOW_4[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[5]">GTX0:DRP3C[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_4" title="GTX0:TX_MARGIN_LOW_4[5]">GTX0:TX_MARGIN_LOW_4[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[6]">GTX0:DRP3C[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_4" title="GTX0:TX_MARGIN_LOW_4[6]">GTX0:TX_MARGIN_LOW_4[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[7]">GTX0:DRP3C[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_4" title="GTX0:TX_MARGIN_FULL_4[0]">GTX0:TX_MARGIN_FULL_4[0]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[8]">GTX0:DRP3C[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_4" title="GTX0:TX_MARGIN_FULL_4[1]">GTX0:TX_MARGIN_FULL_4[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[9]">GTX0:DRP3C[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_4" title="GTX0:TX_MARGIN_FULL_4[2]">GTX0:TX_MARGIN_FULL_4[2]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[10]">GTX0:DRP3C[10]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_4" title="GTX0:TX_MARGIN_FULL_4[3]">GTX0:TX_MARGIN_FULL_4[3]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[11]">GTX0:DRP3C[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_4" title="GTX0:TX_MARGIN_FULL_4[4]">GTX0:TX_MARGIN_FULL_4[4]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[12]">GTX0:DRP3C[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_4" title="GTX0:TX_MARGIN_FULL_4[5]">GTX0:TX_MARGIN_FULL_4[5]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[13]">GTX0:DRP3C[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_4" title="GTX0:TX_MARGIN_FULL_4[6]">GTX0:TX_MARGIN_FULL_4[6]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[14]">GTX0:DRP3C[14]</a><br><a href="#bits-xc6v-GTX-GTX0:TXDRIVE_DRP_EN" title="GTX0:TXDRIVE_DRP_EN">GTX0:TXDRIVE_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3C" title="GTX0:DRP3C[15]">GTX0:DRP3C[15]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DRIVE_MODE" title="GTX0:TX_DRIVE_MODE">GTX0:TX_DRIVE_MODE</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXDIFFCTRL" title="GTX0:A_TXDIFFCTRL[0]">GTX0:A_TXDIFFCTRL[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[0]">GTX0:DRP3D[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXDIFFCTRL" title="GTX0:A_TXDIFFCTRL[1]">GTX0:A_TXDIFFCTRL[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[1]">GTX0:DRP3D[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXDIFFCTRL" title="GTX0:A_TXDIFFCTRL[2]">GTX0:A_TXDIFFCTRL[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[2]">GTX0:DRP3D[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXDIFFCTRL" title="GTX0:A_TXDIFFCTRL[3]">GTX0:A_TXDIFFCTRL[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[3]">GTX0:DRP3D[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXBUFDIFFCTRL" title="GTX0:A_TXBUFDIFFCTRL[0]">GTX0:A_TXBUFDIFFCTRL[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[4]">GTX0:DRP3D[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXBUFDIFFCTRL" title="GTX0:A_TXBUFDIFFCTRL[1]">GTX0:A_TXBUFDIFFCTRL[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[5]">GTX0:DRP3D[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXBUFDIFFCTRL" title="GTX0:A_TXBUFDIFFCTRL[2]">GTX0:A_TXBUFDIFFCTRL[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[6]">GTX0:DRP3D[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPREEMPHASIS" title="GTX0:A_TXPREEMPHASIS[0]">GTX0:A_TXPREEMPHASIS[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[7]">GTX0:DRP3D[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPREEMPHASIS" title="GTX0:A_TXPREEMPHASIS[1]">GTX0:A_TXPREEMPHASIS[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[8]">GTX0:DRP3D[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPREEMPHASIS" title="GTX0:A_TXPREEMPHASIS[2]">GTX0:A_TXPREEMPHASIS[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[9]">GTX0:DRP3D[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPREEMPHASIS" title="GTX0:A_TXPREEMPHASIS[3]">GTX0:A_TXPREEMPHASIS[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[10]">GTX0:DRP3D[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPOSTEMPHASIS" title="GTX0:A_TXPOSTEMPHASIS[0]">GTX0:A_TXPOSTEMPHASIS[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[11]">GTX0:DRP3D[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPOSTEMPHASIS" title="GTX0:A_TXPOSTEMPHASIS[1]">GTX0:A_TXPOSTEMPHASIS[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[12]">GTX0:DRP3D[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPOSTEMPHASIS" title="GTX0:A_TXPOSTEMPHASIS[2]">GTX0:A_TXPOSTEMPHASIS[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[13]">GTX0:DRP3D[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPOSTEMPHASIS" title="GTX0:A_TXPOSTEMPHASIS[3]">GTX0:A_TXPOSTEMPHASIS[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[14]">GTX0:DRP3D[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXPOSTEMPHASIS" title="GTX0:A_TXPOSTEMPHASIS[4]">GTX0:A_TXPOSTEMPHASIS[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3D" title="GTX0:DRP3D[15]">GTX0:DRP3D[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[0]">GTX0:DRP3E[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DEEMPH_0" title="GTX0:TX_DEEMPH_0[0]">GTX0:TX_DEEMPH_0[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[1]">GTX0:DRP3E[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DEEMPH_0" title="GTX0:TX_DEEMPH_0[1]">GTX0:TX_DEEMPH_0[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[2]">GTX0:DRP3E[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DEEMPH_0" title="GTX0:TX_DEEMPH_0[2]">GTX0:TX_DEEMPH_0[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[3]">GTX0:DRP3E[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DEEMPH_0" title="GTX0:TX_DEEMPH_0[3]">GTX0:TX_DEEMPH_0[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[4]">GTX0:DRP3E[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DEEMPH_0" title="GTX0:TX_DEEMPH_0[4]">GTX0:TX_DEEMPH_0[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[5]">GTX0:DRP3E[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DEEMPH_1" title="GTX0:TX_DEEMPH_1[0]">GTX0:TX_DEEMPH_1[0]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[6]">GTX0:DRP3E[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DEEMPH_1" title="GTX0:TX_DEEMPH_1[1]">GTX0:TX_DEEMPH_1[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[7]">GTX0:DRP3E[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DEEMPH_1" title="GTX0:TX_DEEMPH_1[2]">GTX0:TX_DEEMPH_1[2]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[8]">GTX0:DRP3E[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DEEMPH_1" title="GTX0:TX_DEEMPH_1[3]">GTX0:TX_DEEMPH_1[3]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[9]">GTX0:DRP3E[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DEEMPH_1" title="GTX0:TX_DEEMPH_1[4]">GTX0:TX_DEEMPH_1[4]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[10]">GTX0:DRP3E[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[11]">GTX0:DRP3E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[12]">GTX0:DRP3E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXMARGIN" title="GTX0:A_TXMARGIN[0]">GTX0:A_TXMARGIN[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[13]">GTX0:DRP3E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_TXMARGIN" title="GTX0:A_TXMARGIN[1]">GTX0:A_TXMARGIN[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[14]">GTX0:DRP3E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_TXMARGIN" title="GTX0:A_TXMARGIN[2]">GTX0:A_TXMARGIN[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP3E" title="GTX0:DRP3E[15]">GTX0:DRP3E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[0]">GTX0:DRP3F[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_RATE" title="GTX0:TRANS_TIME_RATE[0]">GTX0:TRANS_TIME_RATE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[1]">GTX0:DRP3F[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_RATE" title="GTX0:TRANS_TIME_RATE[1]">GTX0:TRANS_TIME_RATE[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[2]">GTX0:DRP3F[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_RATE" title="GTX0:TRANS_TIME_RATE[2]">GTX0:TRANS_TIME_RATE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[3]">GTX0:DRP3F[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_RATE" title="GTX0:TRANS_TIME_RATE[3]">GTX0:TRANS_TIME_RATE[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[4]">GTX0:DRP3F[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_RATE" title="GTX0:TRANS_TIME_RATE[4]">GTX0:TRANS_TIME_RATE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[5]">GTX0:DRP3F[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_RATE" title="GTX0:TRANS_TIME_RATE[5]">GTX0:TRANS_TIME_RATE[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[6]">GTX0:DRP3F[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_RATE" title="GTX0:TRANS_TIME_RATE[6]">GTX0:TRANS_TIME_RATE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[7]">GTX0:DRP3F[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TRANS_TIME_RATE" title="GTX0:TRANS_TIME_RATE[7]">GTX0:TRANS_TIME_RATE[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[8]">GTX0:DRP3F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[9]">GTX0:DRP3F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[10]">GTX0:DRP3F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[11]">GTX0:DRP3F[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[12]">GTX0:DRP3F[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[13]">GTX0:DRP3F[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[14]">GTX0:DRP3F[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP3F" title="GTX0:DRP3F[15]">GTX0:DRP3F[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 8</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_RXEQMIX" title="GTX0:A_RXEQMIX[0]">GTX0:A_RXEQMIX[0]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[0]">GTX0:DRP40[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_RXEQMIX" title="GTX0:A_RXEQMIX[1]">GTX0:A_RXEQMIX[1]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[1]">GTX0:DRP40[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_RXEQMIX" title="GTX0:A_RXEQMIX[2]">GTX0:A_RXEQMIX[2]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[2]">GTX0:DRP40[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_RXEQMIX" title="GTX0:A_RXEQMIX[3]">GTX0:A_RXEQMIX[3]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[3]">GTX0:DRP40[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_RXEQMIX" title="GTX0:A_RXEQMIX[4]">GTX0:A_RXEQMIX[4]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[4]">GTX0:DRP40[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_RXEQMIX" title="GTX0:A_RXEQMIX[5]">GTX0:A_RXEQMIX[5]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[5]">GTX0:DRP40[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_RXEQMIX" title="GTX0:A_RXEQMIX[6]">GTX0:A_RXEQMIX[6]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[6]">GTX0:DRP40[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_RXEQMIX" title="GTX0:A_RXEQMIX[7]">GTX0:A_RXEQMIX[7]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[7]">GTX0:DRP40[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:A_RXEQMIX" title="GTX0:A_RXEQMIX[8]">GTX0:A_RXEQMIX[8]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[8]">GTX0:DRP40[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:A_RXEQMIX" title="GTX0:A_RXEQMIX[9]">GTX0:A_RXEQMIX[9]</a><br><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[9]">GTX0:DRP40[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[10]">GTX0:DRP40[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[11]">GTX0:DRP40[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[12]">GTX0:DRP40[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[13]">GTX0:DRP40[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[14]">GTX0:DRP40[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP40" title="GTX0:DRP40[15]">GTX0:DRP40[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[0]">GTX0:DRP41[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[16]">GTX0:TST_ATTR[16]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[1]">GTX0:DRP41[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[17]">GTX0:TST_ATTR[17]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[2]">GTX0:DRP41[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[18]">GTX0:TST_ATTR[18]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[3]">GTX0:DRP41[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[19]">GTX0:TST_ATTR[19]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[4]">GTX0:DRP41[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[20]">GTX0:TST_ATTR[20]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[5]">GTX0:DRP41[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[21]">GTX0:TST_ATTR[21]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[6]">GTX0:DRP41[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[22]">GTX0:TST_ATTR[22]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[7]">GTX0:DRP41[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[23]">GTX0:TST_ATTR[23]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[8]">GTX0:DRP41[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[24]">GTX0:TST_ATTR[24]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[9]">GTX0:DRP41[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[25]">GTX0:TST_ATTR[25]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[10]">GTX0:DRP41[10]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[26]">GTX0:TST_ATTR[26]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[11]">GTX0:DRP41[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[27]">GTX0:TST_ATTR[27]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[12]">GTX0:DRP41[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[28]">GTX0:TST_ATTR[28]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[13]">GTX0:DRP41[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[29]">GTX0:TST_ATTR[29]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[14]">GTX0:DRP41[14]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[30]">GTX0:TST_ATTR[30]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP41" title="GTX0:DRP41[15]">GTX0:DRP41[15]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[31]">GTX0:TST_ATTR[31]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[0]">GTX0:DRP42[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[0]">GTX0:TST_ATTR[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[1]">GTX0:DRP42[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[1]">GTX0:TST_ATTR[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[2]">GTX0:DRP42[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[2]">GTX0:TST_ATTR[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[3]">GTX0:DRP42[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[3]">GTX0:TST_ATTR[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[4]">GTX0:DRP42[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[4]">GTX0:TST_ATTR[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[5]">GTX0:DRP42[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[5]">GTX0:TST_ATTR[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[6]">GTX0:DRP42[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[6]">GTX0:TST_ATTR[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[7]">GTX0:DRP42[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[7]">GTX0:TST_ATTR[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[8]">GTX0:DRP42[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[8]">GTX0:TST_ATTR[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[9]">GTX0:DRP42[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[9]">GTX0:TST_ATTR[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[10]">GTX0:DRP42[10]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[10]">GTX0:TST_ATTR[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[11]">GTX0:DRP42[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[11]">GTX0:TST_ATTR[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[12]">GTX0:DRP42[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[12]">GTX0:TST_ATTR[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[13]">GTX0:DRP42[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[13]">GTX0:TST_ATTR[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[14]">GTX0:DRP42[14]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[14]">GTX0:TST_ATTR[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP42" title="GTX0:DRP42[15]">GTX0:DRP42[15]</a><br><a href="#bits-xc6v-GTX-GTX0:TST_ATTR" title="GTX0:TST_ATTR[15]">GTX0:TST_ATTR[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[0]">GTX0:DRP43[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TXOUTCLK_CTRL" title="GTX0:TXOUTCLK_CTRL[2]">GTX0:TXOUTCLK_CTRL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[1]">GTX0:DRP43[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TXOUTCLK_CTRL" title="GTX0:TXOUTCLK_CTRL[1]">GTX0:TXOUTCLK_CTRL[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[2]">GTX0:DRP43[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TXOUTCLK_CTRL" title="GTX0:TXOUTCLK_CTRL[0]">GTX0:TXOUTCLK_CTRL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[3]">GTX0:DRP43[3]</a><br><a href="#bits-xc6v-GTX-GTX0:RXRECCLK_CTRL" title="GTX0:RXRECCLK_CTRL[2]">GTX0:RXRECCLK_CTRL[2]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[4]">GTX0:DRP43[4]</a><br><a href="#bits-xc6v-GTX-GTX0:RXRECCLK_CTRL" title="GTX0:RXRECCLK_CTRL[1]">GTX0:RXRECCLK_CTRL[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[5]">GTX0:DRP43[5]</a><br><a href="#bits-xc6v-GTX-GTX0:RXRECCLK_CTRL" title="GTX0:RXRECCLK_CTRL[0]">GTX0:RXRECCLK_CTRL[0]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[6]">GTX0:DRP43[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[7]">GTX0:DRP43[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[8]">GTX0:DRP43[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[9]">GTX0:DRP43[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[10]">GTX0:DRP43[10]</a><br><a href="#bits-xc6v-GTX-GTX0:INV.TSTCLK0" title="~GTX0:INV.TSTCLK0">~GTX0:INV.TSTCLK0</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[11]">GTX0:DRP43[11]</a><br><a href="#bits-xc6v-GTX-GTX0:INV.TSTCLK1" title="~GTX0:INV.TSTCLK1">~GTX0:INV.TSTCLK1</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[12]">GTX0:DRP43[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[13]">GTX0:DRP43[13]</a><br><a href="#bits-xc6v-GTX-GTX0:INV.SCANCLK" title="~GTX0:INV.SCANCLK">~GTX0:INV.SCANCLK</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[14]">GTX0:DRP43[14]</a><br><a href="#bits-xc6v-GTX-GTX0:INV.GREFCLKTX" title="~GTX0:INV.GREFCLKTX">~GTX0:INV.GREFCLKTX</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP43" title="GTX0:DRP43[15]">GTX0:DRP43[15]</a><br><a href="#bits-xc6v-GTX-GTX0:INV.GREFCLKRX" title="~GTX0:INV.GREFCLKRX">~GTX0:INV.GREFCLKRX</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[0]">GTX0:DRP44[0]</a><br><a href="#bits-xc6v-GTX-GTX0:POWER_SAVE" title="GTX0:POWER_SAVE[0]">GTX0:POWER_SAVE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[1]">GTX0:DRP44[1]</a><br><a href="#bits-xc6v-GTX-GTX0:POWER_SAVE" title="GTX0:POWER_SAVE[1]">GTX0:POWER_SAVE[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[2]">GTX0:DRP44[2]</a><br><a href="#bits-xc6v-GTX-GTX0:POWER_SAVE" title="GTX0:POWER_SAVE[2]">GTX0:POWER_SAVE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[3]">GTX0:DRP44[3]</a><br><a href="#bits-xc6v-GTX-GTX0:POWER_SAVE" title="GTX0:POWER_SAVE[3]">GTX0:POWER_SAVE[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[4]">GTX0:DRP44[4]</a><br><a href="#bits-xc6v-GTX-GTX0:POWER_SAVE" title="GTX0:POWER_SAVE[4]">GTX0:POWER_SAVE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[5]">GTX0:DRP44[5]</a><br><a href="#bits-xc6v-GTX-GTX0:POWER_SAVE" title="GTX0:POWER_SAVE[5]">GTX0:POWER_SAVE[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[6]">GTX0:DRP44[6]</a><br><a href="#bits-xc6v-GTX-GTX0:POWER_SAVE" title="GTX0:POWER_SAVE[6]">GTX0:POWER_SAVE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[7]">GTX0:DRP44[7]</a><br><a href="#bits-xc6v-GTX-GTX0:POWER_SAVE" title="GTX0:POWER_SAVE[7]">GTX0:POWER_SAVE[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[8]">GTX0:DRP44[8]</a><br><a href="#bits-xc6v-GTX-GTX0:POWER_SAVE" title="GTX0:POWER_SAVE[8]">GTX0:POWER_SAVE[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[9]">GTX0:DRP44[9]</a><br><a href="#bits-xc6v-GTX-GTX0:POWER_SAVE" title="GTX0:POWER_SAVE[9]">GTX0:POWER_SAVE[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[10]">GTX0:DRP44[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[11]">GTX0:DRP44[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[12]">GTX0:DRP44[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[13]">GTX0:DRP44[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[14]">GTX0:DRP44[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP44" title="GTX0:DRP44[15]">GTX0:DRP44[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[0]">GTX0:DRP45[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_BYTECLK_CFG" title="GTX0:TX_BYTECLK_CFG[0]">GTX0:TX_BYTECLK_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[1]">GTX0:DRP45[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_BYTECLK_CFG" title="GTX0:TX_BYTECLK_CFG[1]">GTX0:TX_BYTECLK_CFG[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[2]">GTX0:DRP45[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_BYTECLK_CFG" title="GTX0:TX_BYTECLK_CFG[2]">GTX0:TX_BYTECLK_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[3]">GTX0:DRP45[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_BYTECLK_CFG" title="GTX0:TX_BYTECLK_CFG[3]">GTX0:TX_BYTECLK_CFG[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[4]">GTX0:DRP45[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_BYTECLK_CFG" title="GTX0:TX_BYTECLK_CFG[4]">GTX0:TX_BYTECLK_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[5]">GTX0:DRP45[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_BYTECLK_CFG" title="GTX0:TX_BYTECLK_CFG[5]">GTX0:TX_BYTECLK_CFG[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[6]">GTX0:DRP45[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_USRCLK_CFG" title="GTX0:TX_USRCLK_CFG[0]">GTX0:TX_USRCLK_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[7]">GTX0:DRP45[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_USRCLK_CFG" title="GTX0:TX_USRCLK_CFG[1]">GTX0:TX_USRCLK_CFG[1]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[8]">GTX0:DRP45[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_USRCLK_CFG" title="GTX0:TX_USRCLK_CFG[2]">GTX0:TX_USRCLK_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[9]">GTX0:DRP45[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_USRCLK_CFG" title="GTX0:TX_USRCLK_CFG[3]">GTX0:TX_USRCLK_CFG[3]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[10]">GTX0:DRP45[10]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_USRCLK_CFG" title="GTX0:TX_USRCLK_CFG[4]">GTX0:TX_USRCLK_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[11]">GTX0:DRP45[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_USRCLK_CFG" title="GTX0:TX_USRCLK_CFG[5]">GTX0:TX_USRCLK_CFG[5]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[12]">GTX0:DRP45[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[13]">GTX0:DRP45[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[14]">GTX0:DRP45[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP45" title="GTX0:DRP45[15]">GTX0:DRP45[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[0]">GTX0:DRP46[0]</a><br><a href="#bits-xc6v-GTX-GTX0:RXRECCLK_DLY" title="GTX0:RXRECCLK_DLY[0]">GTX0:RXRECCLK_DLY[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[1]">GTX0:DRP46[1]</a><br><a href="#bits-xc6v-GTX-GTX0:RXRECCLK_DLY" title="GTX0:RXRECCLK_DLY[1]">GTX0:RXRECCLK_DLY[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[2]">GTX0:DRP46[2]</a><br><a href="#bits-xc6v-GTX-GTX0:RXRECCLK_DLY" title="GTX0:RXRECCLK_DLY[2]">GTX0:RXRECCLK_DLY[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[3]">GTX0:DRP46[3]</a><br><a href="#bits-xc6v-GTX-GTX0:RXRECCLK_DLY" title="GTX0:RXRECCLK_DLY[3]">GTX0:RXRECCLK_DLY[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[4]">GTX0:DRP46[4]</a><br><a href="#bits-xc6v-GTX-GTX0:RXRECCLK_DLY" title="GTX0:RXRECCLK_DLY[4]">GTX0:RXRECCLK_DLY[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[5]">GTX0:DRP46[5]</a><br><a href="#bits-xc6v-GTX-GTX0:RXRECCLK_DLY" title="GTX0:RXRECCLK_DLY[5]">GTX0:RXRECCLK_DLY[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[6]">GTX0:DRP46[6]</a><br><a href="#bits-xc6v-GTX-GTX0:RXRECCLK_DLY" title="GTX0:RXRECCLK_DLY[6]">GTX0:RXRECCLK_DLY[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[7]">GTX0:DRP46[7]</a><br><a href="#bits-xc6v-GTX-GTX0:RXRECCLK_DLY" title="GTX0:RXRECCLK_DLY[7]">GTX0:RXRECCLK_DLY[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[8]">GTX0:DRP46[8]</a><br><a href="#bits-xc6v-GTX-GTX0:RXRECCLK_DLY" title="GTX0:RXRECCLK_DLY[8]">GTX0:RXRECCLK_DLY[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[9]">GTX0:DRP46[9]</a><br><a href="#bits-xc6v-GTX-GTX0:RXRECCLK_DLY" title="GTX0:RXRECCLK_DLY[9]">GTX0:RXRECCLK_DLY[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[10]">GTX0:DRP46[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[11]">GTX0:DRP46[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[12]">GTX0:DRP46[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[13]">GTX0:DRP46[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[14]">GTX0:DRP46[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP46" title="GTX0:DRP46[15]">GTX0:DRP46[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[0]">GTX0:DRP47[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TXOUTCLK_DLY" title="GTX0:TXOUTCLK_DLY[0]">GTX0:TXOUTCLK_DLY[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[1]">GTX0:DRP47[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TXOUTCLK_DLY" title="GTX0:TXOUTCLK_DLY[1]">GTX0:TXOUTCLK_DLY[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[2]">GTX0:DRP47[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TXOUTCLK_DLY" title="GTX0:TXOUTCLK_DLY[2]">GTX0:TXOUTCLK_DLY[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[3]">GTX0:DRP47[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TXOUTCLK_DLY" title="GTX0:TXOUTCLK_DLY[3]">GTX0:TXOUTCLK_DLY[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[4]">GTX0:DRP47[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TXOUTCLK_DLY" title="GTX0:TXOUTCLK_DLY[4]">GTX0:TXOUTCLK_DLY[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[5]">GTX0:DRP47[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TXOUTCLK_DLY" title="GTX0:TXOUTCLK_DLY[5]">GTX0:TXOUTCLK_DLY[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[6]">GTX0:DRP47[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TXOUTCLK_DLY" title="GTX0:TXOUTCLK_DLY[6]">GTX0:TXOUTCLK_DLY[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[7]">GTX0:DRP47[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TXOUTCLK_DLY" title="GTX0:TXOUTCLK_DLY[7]">GTX0:TXOUTCLK_DLY[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[8]">GTX0:DRP47[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TXOUTCLK_DLY" title="GTX0:TXOUTCLK_DLY[8]">GTX0:TXOUTCLK_DLY[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[9]">GTX0:DRP47[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TXOUTCLK_DLY" title="GTX0:TXOUTCLK_DLY[9]">GTX0:TXOUTCLK_DLY[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[10]">GTX0:DRP47[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[11]">GTX0:DRP47[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[12]">GTX0:DRP47[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[13]">GTX0:DRP47[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[14]">GTX0:DRP47[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP47" title="GTX0:DRP47[15]">GTX0:DRP47[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 9</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[0]">GTX0:DRP48[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[1]">GTX0:DRP48[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[2]">GTX0:DRP48[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[3]">GTX0:DRP48[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[4]">GTX0:DRP48[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[5]">GTX0:DRP48[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[6]">GTX0:DRP48[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[7]">GTX0:DRP48[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[8]">GTX0:DRP48[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[9]">GTX0:DRP48[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[10]">GTX0:DRP48[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[11]">GTX0:DRP48[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[12]">GTX0:DRP48[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[13]">GTX0:DRP48[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[14]">GTX0:DRP48[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP48" title="GTX0:DRP48[15]">GTX0:DRP48[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[0]">GTX0:DRP49[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[1]">GTX0:DRP49[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[2]">GTX0:DRP49[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[3]">GTX0:DRP49[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[4]">GTX0:DRP49[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[5]">GTX0:DRP49[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[6]">GTX0:DRP49[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[7]">GTX0:DRP49[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[8]">GTX0:DRP49[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[9]">GTX0:DRP49[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[10]">GTX0:DRP49[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[11]">GTX0:DRP49[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[12]">GTX0:DRP49[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[13]">GTX0:DRP49[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[14]">GTX0:DRP49[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP49" title="GTX0:DRP49[15]">GTX0:DRP49[15]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[0]">GTX0:DRP4A[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[1]">GTX0:DRP4A[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[2]">GTX0:DRP4A[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[3]">GTX0:DRP4A[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[4]">GTX0:DRP4A[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[5]">GTX0:DRP4A[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[6]">GTX0:DRP4A[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[7]">GTX0:DRP4A[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[8]">GTX0:DRP4A[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[9]">GTX0:DRP4A[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[10]">GTX0:DRP4A[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[11]">GTX0:DRP4A[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[12]">GTX0:DRP4A[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[13]">GTX0:DRP4A[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[14]">GTX0:DRP4A[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4A" title="GTX0:DRP4A[15]">GTX0:DRP4A[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[0]">GTX0:DRP4B[0]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_MONSEL" title="GTX0:RX_DLYALIGN_MONSEL[0]">GTX0:RX_DLYALIGN_MONSEL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[1]">GTX0:DRP4B[1]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_MONSEL" title="GTX0:RX_DLYALIGN_MONSEL[1]">GTX0:RX_DLYALIGN_MONSEL[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[2]">GTX0:DRP4B[2]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_MONSEL" title="GTX0:RX_DLYALIGN_MONSEL[2]">GTX0:RX_DLYALIGN_MONSEL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[3]">GTX0:DRP4B[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_MONSEL" title="GTX0:TX_DLYALIGN_MONSEL[0]">GTX0:TX_DLYALIGN_MONSEL[0]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[4]">GTX0:DRP4B[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_MONSEL" title="GTX0:TX_DLYALIGN_MONSEL[1]">GTX0:TX_DLYALIGN_MONSEL[1]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[5]">GTX0:DRP4B[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_MONSEL" title="GTX0:TX_DLYALIGN_MONSEL[2]">GTX0:TX_DLYALIGN_MONSEL[2]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[6]">GTX0:DRP4B[6]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_EDGESET" title="GTX0:RX_DLYALIGN_EDGESET[0]">GTX0:RX_DLYALIGN_EDGESET[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[7]">GTX0:DRP4B[7]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_EDGESET" title="GTX0:RX_DLYALIGN_EDGESET[1]">GTX0:RX_DLYALIGN_EDGESET[1]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[8]">GTX0:DRP4B[8]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_EDGESET" title="GTX0:RX_DLYALIGN_EDGESET[2]">GTX0:RX_DLYALIGN_EDGESET[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[9]">GTX0:DRP4B[9]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_EDGESET" title="GTX0:RX_DLYALIGN_EDGESET[3]">GTX0:RX_DLYALIGN_EDGESET[3]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[10]">GTX0:DRP4B[10]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_EDGESET" title="GTX0:RX_DLYALIGN_EDGESET[4]">GTX0:RX_DLYALIGN_EDGESET[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[11]">GTX0:DRP4B[11]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[12]">GTX0:DRP4B[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[13]">GTX0:DRP4B[13]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[14]">GTX0:DRP4B[14]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_EN_REALIGN_RESET_BUF2" title="GTX0:RX_EN_REALIGN_RESET_BUF2">GTX0:RX_EN_REALIGN_RESET_BUF2</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4B" title="GTX0:DRP4B[15]">GTX0:DRP4B[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[0]">GTX0:DRP4C[0]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_CTRINC" title="GTX0:TX_DLYALIGN_CTRINC[0]">GTX0:TX_DLYALIGN_CTRINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[1]">GTX0:DRP4C[1]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_CTRINC" title="GTX0:TX_DLYALIGN_CTRINC[1]">GTX0:TX_DLYALIGN_CTRINC[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[2]">GTX0:DRP4C[2]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_CTRINC" title="GTX0:TX_DLYALIGN_CTRINC[2]">GTX0:TX_DLYALIGN_CTRINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[3]">GTX0:DRP4C[3]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_CTRINC" title="GTX0:TX_DLYALIGN_CTRINC[3]">GTX0:TX_DLYALIGN_CTRINC[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[4]">GTX0:DRP4C[4]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_LPFINC" title="GTX0:TX_DLYALIGN_LPFINC[0]">GTX0:TX_DLYALIGN_LPFINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[5]">GTX0:DRP4C[5]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_LPFINC" title="GTX0:TX_DLYALIGN_LPFINC[1]">GTX0:TX_DLYALIGN_LPFINC[1]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[6]">GTX0:DRP4C[6]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_LPFINC" title="GTX0:TX_DLYALIGN_LPFINC[2]">GTX0:TX_DLYALIGN_LPFINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[7]">GTX0:DRP4C[7]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_LPFINC" title="GTX0:TX_DLYALIGN_LPFINC[3]">GTX0:TX_DLYALIGN_LPFINC[3]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[8]">GTX0:DRP4C[8]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_OVRDSETTING" title="GTX0:TX_DLYALIGN_OVRDSETTING[0]">GTX0:TX_DLYALIGN_OVRDSETTING[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[9]">GTX0:DRP4C[9]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_OVRDSETTING" title="GTX0:TX_DLYALIGN_OVRDSETTING[1]">GTX0:TX_DLYALIGN_OVRDSETTING[1]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[10]">GTX0:DRP4C[10]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_OVRDSETTING" title="GTX0:TX_DLYALIGN_OVRDSETTING[2]">GTX0:TX_DLYALIGN_OVRDSETTING[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[11]">GTX0:DRP4C[11]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_OVRDSETTING" title="GTX0:TX_DLYALIGN_OVRDSETTING[3]">GTX0:TX_DLYALIGN_OVRDSETTING[3]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[12]">GTX0:DRP4C[12]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_OVRDSETTING" title="GTX0:TX_DLYALIGN_OVRDSETTING[4]">GTX0:TX_DLYALIGN_OVRDSETTING[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[13]">GTX0:DRP4C[13]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_OVRDSETTING" title="GTX0:TX_DLYALIGN_OVRDSETTING[5]">GTX0:TX_DLYALIGN_OVRDSETTING[5]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[14]">GTX0:DRP4C[14]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_OVRDSETTING" title="GTX0:TX_DLYALIGN_OVRDSETTING[6]">GTX0:TX_DLYALIGN_OVRDSETTING[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4C" title="GTX0:DRP4C[15]">GTX0:DRP4C[15]</a><br><a href="#bits-xc6v-GTX-GTX0:TX_DLYALIGN_OVRDSETTING" title="GTX0:TX_DLYALIGN_OVRDSETTING[7]">GTX0:TX_DLYALIGN_OVRDSETTING[7]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[0]">GTX0:DRP4D[0]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_CTRINC" title="GTX0:RX_DLYALIGN_CTRINC[0]">GTX0:RX_DLYALIGN_CTRINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[1]">GTX0:DRP4D[1]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_CTRINC" title="GTX0:RX_DLYALIGN_CTRINC[1]">GTX0:RX_DLYALIGN_CTRINC[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[2]">GTX0:DRP4D[2]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_CTRINC" title="GTX0:RX_DLYALIGN_CTRINC[2]">GTX0:RX_DLYALIGN_CTRINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[3]">GTX0:DRP4D[3]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_CTRINC" title="GTX0:RX_DLYALIGN_CTRINC[3]">GTX0:RX_DLYALIGN_CTRINC[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[4]">GTX0:DRP4D[4]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_LPFINC" title="GTX0:RX_DLYALIGN_LPFINC[0]">GTX0:RX_DLYALIGN_LPFINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[5]">GTX0:DRP4D[5]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_LPFINC" title="GTX0:RX_DLYALIGN_LPFINC[1]">GTX0:RX_DLYALIGN_LPFINC[1]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[6]">GTX0:DRP4D[6]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_LPFINC" title="GTX0:RX_DLYALIGN_LPFINC[2]">GTX0:RX_DLYALIGN_LPFINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[7]">GTX0:DRP4D[7]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_LPFINC" title="GTX0:RX_DLYALIGN_LPFINC[3]">GTX0:RX_DLYALIGN_LPFINC[3]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[8]">GTX0:DRP4D[8]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_OVRDSETTING" title="GTX0:RX_DLYALIGN_OVRDSETTING[0]">GTX0:RX_DLYALIGN_OVRDSETTING[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[9]">GTX0:DRP4D[9]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_OVRDSETTING" title="GTX0:RX_DLYALIGN_OVRDSETTING[1]">GTX0:RX_DLYALIGN_OVRDSETTING[1]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[10]">GTX0:DRP4D[10]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_OVRDSETTING" title="GTX0:RX_DLYALIGN_OVRDSETTING[2]">GTX0:RX_DLYALIGN_OVRDSETTING[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[11]">GTX0:DRP4D[11]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_OVRDSETTING" title="GTX0:RX_DLYALIGN_OVRDSETTING[3]">GTX0:RX_DLYALIGN_OVRDSETTING[3]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[12]">GTX0:DRP4D[12]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_OVRDSETTING" title="GTX0:RX_DLYALIGN_OVRDSETTING[4]">GTX0:RX_DLYALIGN_OVRDSETTING[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[13]">GTX0:DRP4D[13]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_OVRDSETTING" title="GTX0:RX_DLYALIGN_OVRDSETTING[5]">GTX0:RX_DLYALIGN_OVRDSETTING[5]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[14]">GTX0:DRP4D[14]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_OVRDSETTING" title="GTX0:RX_DLYALIGN_OVRDSETTING[6]">GTX0:RX_DLYALIGN_OVRDSETTING[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4D" title="GTX0:DRP4D[15]">GTX0:DRP4D[15]</a><br><a href="#bits-xc6v-GTX-GTX0:RX_DLYALIGN_OVRDSETTING" title="GTX0:RX_DLYALIGN_OVRDSETTING[7]">GTX0:RX_DLYALIGN_OVRDSETTING[7]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[0]">GTX0:DRP4E[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[1]">GTX0:DRP4E[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[2]">GTX0:DRP4E[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[3]">GTX0:DRP4E[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[4]">GTX0:DRP4E[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[5]">GTX0:DRP4E[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[6]">GTX0:DRP4E[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[7]">GTX0:DRP4E[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[8]">GTX0:DRP4E[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[9]">GTX0:DRP4E[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[10]">GTX0:DRP4E[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[11]">GTX0:DRP4E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[12]">GTX0:DRP4E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[13]">GTX0:DRP4E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[14]">GTX0:DRP4E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4E" title="GTX0:DRP4E[15]">GTX0:DRP4E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[0]">GTX0:DRP4F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[1]">GTX0:DRP4F[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[2]">GTX0:DRP4F[2]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[3]">GTX0:DRP4F[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[4]">GTX0:DRP4F[4]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[5]">GTX0:DRP4F[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[6]">GTX0:DRP4F[6]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[7]">GTX0:DRP4F[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[8]">GTX0:DRP4F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[9]">GTX0:DRP4F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[10]">GTX0:DRP4F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[11]">GTX0:DRP4F[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[12]">GTX0:DRP4F[12]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[13]">GTX0:DRP4F[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[14]">GTX0:DRP4F[14]</a></td><td><a href="#bits-xc6v-GTX-GTX0:DRP4F" title="GTX0:DRP4F[15]">GTX0:DRP4F[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 10</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[0]">GTX1:DRP00[0]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[0]">GTX1:PMA_RX_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[1]">GTX1:DRP00[1]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[1]">GTX1:PMA_RX_CFG[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[2]">GTX1:DRP00[2]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[2]">GTX1:PMA_RX_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[3]">GTX1:DRP00[3]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[3]">GTX1:PMA_RX_CFG[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[4]">GTX1:DRP00[4]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[4]">GTX1:PMA_RX_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[5]">GTX1:DRP00[5]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[5]">GTX1:PMA_RX_CFG[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[6]">GTX1:DRP00[6]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[6]">GTX1:PMA_RX_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[7]">GTX1:DRP00[7]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[7]">GTX1:PMA_RX_CFG[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[8]">GTX1:DRP00[8]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[8]">GTX1:PMA_RX_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[9]">GTX1:DRP00[9]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[9]">GTX1:PMA_RX_CFG[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[10]">GTX1:DRP00[10]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[10]">GTX1:PMA_RX_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[11]">GTX1:DRP00[11]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[11]">GTX1:PMA_RX_CFG[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[12]">GTX1:DRP00[12]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[12]">GTX1:PMA_RX_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[13]">GTX1:DRP00[13]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[13]">GTX1:PMA_RX_CFG[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[14]">GTX1:DRP00[14]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[14]">GTX1:PMA_RX_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP00" title="GTX1:DRP00[15]">GTX1:DRP00[15]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[15]">GTX1:PMA_RX_CFG[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[0]">GTX1:DRP01[0]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[16]">GTX1:PMA_RX_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[1]">GTX1:DRP01[1]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[17]">GTX1:PMA_RX_CFG[17]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[2]">GTX1:DRP01[2]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[18]">GTX1:PMA_RX_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[3]">GTX1:DRP01[3]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[19]">GTX1:PMA_RX_CFG[19]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[4]">GTX1:DRP01[4]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[20]">GTX1:PMA_RX_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[5]">GTX1:DRP01[5]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[21]">GTX1:PMA_RX_CFG[21]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[6]">GTX1:DRP01[6]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[22]">GTX1:PMA_RX_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[7]">GTX1:DRP01[7]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[23]">GTX1:PMA_RX_CFG[23]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[8]">GTX1:DRP01[8]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RX_CFG" title="GTX1:PMA_RX_CFG[24]">GTX1:PMA_RX_CFG[24]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[9]">GTX1:DRP01[9]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RXSYNC_CFG" title="GTX1:PMA_RXSYNC_CFG[0]">GTX1:PMA_RXSYNC_CFG[0]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[10]">GTX1:DRP01[10]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RXSYNC_CFG" title="GTX1:PMA_RXSYNC_CFG[1]">GTX1:PMA_RXSYNC_CFG[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[11]">GTX1:DRP01[11]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RXSYNC_CFG" title="GTX1:PMA_RXSYNC_CFG[2]">GTX1:PMA_RXSYNC_CFG[2]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[12]">GTX1:DRP01[12]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RXSYNC_CFG" title="GTX1:PMA_RXSYNC_CFG[3]">GTX1:PMA_RXSYNC_CFG[3]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[13]">GTX1:DRP01[13]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RXSYNC_CFG" title="GTX1:PMA_RXSYNC_CFG[4]">GTX1:PMA_RXSYNC_CFG[4]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[14]">GTX1:DRP01[14]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RXSYNC_CFG" title="GTX1:PMA_RXSYNC_CFG[5]">GTX1:PMA_RXSYNC_CFG[5]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP01" title="GTX1:DRP01[15]">GTX1:DRP01[15]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_RXSYNC_CFG" title="GTX1:PMA_RXSYNC_CFG[6]">GTX1:PMA_RXSYNC_CFG[6]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[0]">GTX1:DRP02[0]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[0]">GTX1:RXUSRCLK_DLY[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[1]">GTX1:DRP02[1]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[1]">GTX1:RXUSRCLK_DLY[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[2]">GTX1:DRP02[2]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[2]">GTX1:RXUSRCLK_DLY[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[3]">GTX1:DRP02[3]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[3]">GTX1:RXUSRCLK_DLY[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[4]">GTX1:DRP02[4]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[4]">GTX1:RXUSRCLK_DLY[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[5]">GTX1:DRP02[5]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[5]">GTX1:RXUSRCLK_DLY[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[6]">GTX1:DRP02[6]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[6]">GTX1:RXUSRCLK_DLY[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[7]">GTX1:DRP02[7]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[7]">GTX1:RXUSRCLK_DLY[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[8]">GTX1:DRP02[8]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[8]">GTX1:RXUSRCLK_DLY[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[9]">GTX1:DRP02[9]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[9]">GTX1:RXUSRCLK_DLY[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[10]">GTX1:DRP02[10]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[10]">GTX1:RXUSRCLK_DLY[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[11]">GTX1:DRP02[11]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[11]">GTX1:RXUSRCLK_DLY[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[12]">GTX1:DRP02[12]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[12]">GTX1:RXUSRCLK_DLY[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[13]">GTX1:DRP02[13]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[13]">GTX1:RXUSRCLK_DLY[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[14]">GTX1:DRP02[14]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[14]">GTX1:RXUSRCLK_DLY[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP02" title="GTX1:DRP02[15]">GTX1:DRP02[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RXUSRCLK_DLY" title="GTX1:RXUSRCLK_DLY[15]">GTX1:RXUSRCLK_DLY[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[0]">GTX1:BIAS_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[0]">GTX1:DRP03[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[1]">GTX1:BIAS_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[1]">GTX1:DRP03[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[2]">GTX1:BIAS_CFG[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[2]">GTX1:DRP03[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[3]">GTX1:BIAS_CFG[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[3]">GTX1:DRP03[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[4]">GTX1:BIAS_CFG[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[4]">GTX1:DRP03[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[5]">GTX1:BIAS_CFG[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[5]">GTX1:DRP03[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[6]">GTX1:BIAS_CFG[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[6]">GTX1:DRP03[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[7]">GTX1:BIAS_CFG[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[7]">GTX1:DRP03[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[8]">GTX1:BIAS_CFG[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[8]">GTX1:DRP03[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[9]">GTX1:BIAS_CFG[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[9]">GTX1:DRP03[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[10]">GTX1:BIAS_CFG[10]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[10]">GTX1:DRP03[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[11]">GTX1:BIAS_CFG[11]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[11]">GTX1:DRP03[11]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[12]">GTX1:BIAS_CFG[12]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[12]">GTX1:DRP03[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[13]">GTX1:BIAS_CFG[13]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[13]">GTX1:DRP03[13]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[14]">GTX1:BIAS_CFG[14]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[14]">GTX1:DRP03[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[15]">GTX1:BIAS_CFG[15]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP03" title="GTX1:DRP03[15]">GTX1:DRP03[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_1" title="GTX1:CHAN_BOND_SEQ_1_1[0]">GTX1:CHAN_BOND_SEQ_1_1[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[0]">GTX1:DRP04[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_1" title="GTX1:CHAN_BOND_SEQ_1_1[1]">GTX1:CHAN_BOND_SEQ_1_1[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[1]">GTX1:DRP04[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_1" title="GTX1:CHAN_BOND_SEQ_1_1[2]">GTX1:CHAN_BOND_SEQ_1_1[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[2]">GTX1:DRP04[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_1" title="GTX1:CHAN_BOND_SEQ_1_1[3]">GTX1:CHAN_BOND_SEQ_1_1[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[3]">GTX1:DRP04[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_1" title="GTX1:CHAN_BOND_SEQ_1_1[4]">GTX1:CHAN_BOND_SEQ_1_1[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[4]">GTX1:DRP04[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_1" title="GTX1:CHAN_BOND_SEQ_1_1[5]">GTX1:CHAN_BOND_SEQ_1_1[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[5]">GTX1:DRP04[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_1" title="GTX1:CHAN_BOND_SEQ_1_1[6]">GTX1:CHAN_BOND_SEQ_1_1[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[6]">GTX1:DRP04[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_1" title="GTX1:CHAN_BOND_SEQ_1_1[7]">GTX1:CHAN_BOND_SEQ_1_1[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[7]">GTX1:DRP04[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_1" title="GTX1:CHAN_BOND_SEQ_1_1[8]">GTX1:CHAN_BOND_SEQ_1_1[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[8]">GTX1:DRP04[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_1" title="GTX1:CHAN_BOND_SEQ_1_1[9]">GTX1:CHAN_BOND_SEQ_1_1[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[9]">GTX1:DRP04[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_ENABLE" title="GTX1:CHAN_BOND_SEQ_1_ENABLE[0]">GTX1:CHAN_BOND_SEQ_1_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[10]">GTX1:DRP04[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_ENABLE" title="GTX1:CHAN_BOND_SEQ_1_ENABLE[1]">GTX1:CHAN_BOND_SEQ_1_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[11]">GTX1:DRP04[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_ENABLE" title="GTX1:CHAN_BOND_SEQ_1_ENABLE[2]">GTX1:CHAN_BOND_SEQ_1_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[12]">GTX1:DRP04[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_ENABLE" title="GTX1:CHAN_BOND_SEQ_1_ENABLE[3]">GTX1:CHAN_BOND_SEQ_1_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[13]">GTX1:DRP04[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[14]">GTX1:DRP04[14]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_BUFFER_USE" title="GTX1:RX_BUFFER_USE">GTX1:RX_BUFFER_USE</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP04" title="GTX1:DRP04[15]">GTX1:DRP04[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_LOSS_OF_SYNC_FSM" title="GTX1:RX_LOSS_OF_SYNC_FSM">GTX1:RX_LOSS_OF_SYNC_FSM</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_2" title="GTX1:CHAN_BOND_SEQ_1_2[0]">GTX1:CHAN_BOND_SEQ_1_2[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[0]">GTX1:DRP05[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_2" title="GTX1:CHAN_BOND_SEQ_1_2[1]">GTX1:CHAN_BOND_SEQ_1_2[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[1]">GTX1:DRP05[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_2" title="GTX1:CHAN_BOND_SEQ_1_2[2]">GTX1:CHAN_BOND_SEQ_1_2[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[2]">GTX1:DRP05[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_2" title="GTX1:CHAN_BOND_SEQ_1_2[3]">GTX1:CHAN_BOND_SEQ_1_2[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[3]">GTX1:DRP05[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_2" title="GTX1:CHAN_BOND_SEQ_1_2[4]">GTX1:CHAN_BOND_SEQ_1_2[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[4]">GTX1:DRP05[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_2" title="GTX1:CHAN_BOND_SEQ_1_2[5]">GTX1:CHAN_BOND_SEQ_1_2[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[5]">GTX1:DRP05[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_2" title="GTX1:CHAN_BOND_SEQ_1_2[6]">GTX1:CHAN_BOND_SEQ_1_2[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[6]">GTX1:DRP05[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_2" title="GTX1:CHAN_BOND_SEQ_1_2[7]">GTX1:CHAN_BOND_SEQ_1_2[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[7]">GTX1:DRP05[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_2" title="GTX1:CHAN_BOND_SEQ_1_2[8]">GTX1:CHAN_BOND_SEQ_1_2[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[8]">GTX1:DRP05[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_2" title="GTX1:CHAN_BOND_SEQ_1_2[9]">GTX1:CHAN_BOND_SEQ_1_2[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[9]">GTX1:DRP05[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_1_MAX_SKEW" title="GTX1:CHAN_BOND_1_MAX_SKEW[0]">GTX1:CHAN_BOND_1_MAX_SKEW[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[10]">GTX1:DRP05[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_1_MAX_SKEW" title="GTX1:CHAN_BOND_1_MAX_SKEW[1]">GTX1:CHAN_BOND_1_MAX_SKEW[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[11]">GTX1:DRP05[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_1_MAX_SKEW" title="GTX1:CHAN_BOND_1_MAX_SKEW[2]">GTX1:CHAN_BOND_1_MAX_SKEW[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[12]">GTX1:DRP05[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_1_MAX_SKEW" title="GTX1:CHAN_BOND_1_MAX_SKEW[3]">GTX1:CHAN_BOND_1_MAX_SKEW[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[13]">GTX1:DRP05[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[14]">GTX1:DRP05[14]</a><br><a href="#bits-xc6v-GTX-GTX1:INV.RXUSRCLK" title="~GTX1:INV.RXUSRCLK">~GTX1:INV.RXUSRCLK</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP05" title="GTX1:DRP05[15]">GTX1:DRP05[15]</a><br><a href="#bits-xc6v-GTX-GTX1:INV.RXUSRCLK2" title="~GTX1:INV.RXUSRCLK2">~GTX1:INV.RXUSRCLK2</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_3" title="GTX1:CHAN_BOND_SEQ_1_3[0]">GTX1:CHAN_BOND_SEQ_1_3[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[0]">GTX1:DRP06[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_3" title="GTX1:CHAN_BOND_SEQ_1_3[1]">GTX1:CHAN_BOND_SEQ_1_3[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[1]">GTX1:DRP06[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_3" title="GTX1:CHAN_BOND_SEQ_1_3[2]">GTX1:CHAN_BOND_SEQ_1_3[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[2]">GTX1:DRP06[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_3" title="GTX1:CHAN_BOND_SEQ_1_3[3]">GTX1:CHAN_BOND_SEQ_1_3[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[3]">GTX1:DRP06[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_3" title="GTX1:CHAN_BOND_SEQ_1_3[4]">GTX1:CHAN_BOND_SEQ_1_3[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[4]">GTX1:DRP06[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_3" title="GTX1:CHAN_BOND_SEQ_1_3[5]">GTX1:CHAN_BOND_SEQ_1_3[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[5]">GTX1:DRP06[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_3" title="GTX1:CHAN_BOND_SEQ_1_3[6]">GTX1:CHAN_BOND_SEQ_1_3[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[6]">GTX1:DRP06[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_3" title="GTX1:CHAN_BOND_SEQ_1_3[7]">GTX1:CHAN_BOND_SEQ_1_3[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[7]">GTX1:DRP06[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_3" title="GTX1:CHAN_BOND_SEQ_1_3[8]">GTX1:CHAN_BOND_SEQ_1_3[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[8]">GTX1:DRP06[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_3" title="GTX1:CHAN_BOND_SEQ_1_3[9]">GTX1:CHAN_BOND_SEQ_1_3[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[9]">GTX1:DRP06[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[10]">GTX1:DRP06[10]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_LOS_THRESHOLD" title="GTX1:RX_LOS_THRESHOLD[0]">GTX1:RX_LOS_THRESHOLD[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[11]">GTX1:DRP06[11]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_LOS_THRESHOLD" title="GTX1:RX_LOS_THRESHOLD[1]">GTX1:RX_LOS_THRESHOLD[1]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[12]">GTX1:DRP06[12]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_LOS_THRESHOLD" title="GTX1:RX_LOS_THRESHOLD[2]">GTX1:RX_LOS_THRESHOLD[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[13]">GTX1:DRP06[13]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_LOS_INVALID_INCR" title="GTX1:RX_LOS_INVALID_INCR[0]">GTX1:RX_LOS_INVALID_INCR[0]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[14]">GTX1:DRP06[14]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_LOS_INVALID_INCR" title="GTX1:RX_LOS_INVALID_INCR[1]">GTX1:RX_LOS_INVALID_INCR[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP06" title="GTX1:DRP06[15]">GTX1:DRP06[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_LOS_INVALID_INCR" title="GTX1:RX_LOS_INVALID_INCR[2]">GTX1:RX_LOS_INVALID_INCR[2]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_4" title="GTX1:CHAN_BOND_SEQ_1_4[0]">GTX1:CHAN_BOND_SEQ_1_4[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[0]">GTX1:DRP07[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_4" title="GTX1:CHAN_BOND_SEQ_1_4[1]">GTX1:CHAN_BOND_SEQ_1_4[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[1]">GTX1:DRP07[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_4" title="GTX1:CHAN_BOND_SEQ_1_4[2]">GTX1:CHAN_BOND_SEQ_1_4[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[2]">GTX1:DRP07[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_4" title="GTX1:CHAN_BOND_SEQ_1_4[3]">GTX1:CHAN_BOND_SEQ_1_4[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[3]">GTX1:DRP07[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_4" title="GTX1:CHAN_BOND_SEQ_1_4[4]">GTX1:CHAN_BOND_SEQ_1_4[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[4]">GTX1:DRP07[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_4" title="GTX1:CHAN_BOND_SEQ_1_4[5]">GTX1:CHAN_BOND_SEQ_1_4[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[5]">GTX1:DRP07[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_4" title="GTX1:CHAN_BOND_SEQ_1_4[6]">GTX1:CHAN_BOND_SEQ_1_4[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[6]">GTX1:DRP07[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_4" title="GTX1:CHAN_BOND_SEQ_1_4[7]">GTX1:CHAN_BOND_SEQ_1_4[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[7]">GTX1:DRP07[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_4" title="GTX1:CHAN_BOND_SEQ_1_4[8]">GTX1:CHAN_BOND_SEQ_1_4[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[8]">GTX1:DRP07[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_4" title="GTX1:CHAN_BOND_SEQ_1_4[9]">GTX1:CHAN_BOND_SEQ_1_4[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[9]">GTX1:DRP07[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_LEN" title="GTX1:CHAN_BOND_SEQ_LEN[0]">GTX1:CHAN_BOND_SEQ_LEN[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[10]">GTX1:DRP07[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_LEN" title="GTX1:CHAN_BOND_SEQ_LEN[1]">GTX1:CHAN_BOND_SEQ_LEN[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[11]">GTX1:DRP07[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[12]">GTX1:DRP07[12]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_IDLE_LO_CNT" title="GTX1:RX_IDLE_LO_CNT[0]">GTX1:RX_IDLE_LO_CNT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[13]">GTX1:DRP07[13]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_IDLE_LO_CNT" title="GTX1:RX_IDLE_LO_CNT[1]">GTX1:RX_IDLE_LO_CNT[1]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[14]">GTX1:DRP07[14]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_IDLE_LO_CNT" title="GTX1:RX_IDLE_LO_CNT[2]">GTX1:RX_IDLE_LO_CNT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP07" title="GTX1:DRP07[15]">GTX1:DRP07[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_IDLE_LO_CNT" title="GTX1:RX_IDLE_LO_CNT[3]">GTX1:RX_IDLE_LO_CNT[3]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 11</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_1" title="GTX1:CHAN_BOND_SEQ_2_1[0]">GTX1:CHAN_BOND_SEQ_2_1[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[0]">GTX1:DRP08[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_1" title="GTX1:CHAN_BOND_SEQ_2_1[1]">GTX1:CHAN_BOND_SEQ_2_1[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[1]">GTX1:DRP08[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_1" title="GTX1:CHAN_BOND_SEQ_2_1[2]">GTX1:CHAN_BOND_SEQ_2_1[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[2]">GTX1:DRP08[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_1" title="GTX1:CHAN_BOND_SEQ_2_1[3]">GTX1:CHAN_BOND_SEQ_2_1[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[3]">GTX1:DRP08[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_1" title="GTX1:CHAN_BOND_SEQ_2_1[4]">GTX1:CHAN_BOND_SEQ_2_1[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[4]">GTX1:DRP08[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_1" title="GTX1:CHAN_BOND_SEQ_2_1[5]">GTX1:CHAN_BOND_SEQ_2_1[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[5]">GTX1:DRP08[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_1" title="GTX1:CHAN_BOND_SEQ_2_1[6]">GTX1:CHAN_BOND_SEQ_2_1[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[6]">GTX1:DRP08[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_1" title="GTX1:CHAN_BOND_SEQ_2_1[7]">GTX1:CHAN_BOND_SEQ_2_1[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[7]">GTX1:DRP08[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_1" title="GTX1:CHAN_BOND_SEQ_2_1[8]">GTX1:CHAN_BOND_SEQ_2_1[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[8]">GTX1:DRP08[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_1" title="GTX1:CHAN_BOND_SEQ_2_1[9]">GTX1:CHAN_BOND_SEQ_2_1[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[9]">GTX1:DRP08[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_ENABLE" title="GTX1:CHAN_BOND_SEQ_2_ENABLE[0]">GTX1:CHAN_BOND_SEQ_2_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[10]">GTX1:DRP08[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_ENABLE" title="GTX1:CHAN_BOND_SEQ_2_ENABLE[1]">GTX1:CHAN_BOND_SEQ_2_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[11]">GTX1:DRP08[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_ENABLE" title="GTX1:CHAN_BOND_SEQ_2_ENABLE[2]">GTX1:CHAN_BOND_SEQ_2_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[12]">GTX1:DRP08[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_ENABLE" title="GTX1:CHAN_BOND_SEQ_2_ENABLE[3]">GTX1:CHAN_BOND_SEQ_2_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[13]">GTX1:DRP08[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[14]">GTX1:DRP08[14]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EN_REALIGN_RESET_BUF" title="GTX1:RX_EN_REALIGN_RESET_BUF">GTX1:RX_EN_REALIGN_RESET_BUF</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP08" title="GTX1:DRP08[15]">GTX1:DRP08[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EN_RATE_RESET_BUF" title="GTX1:RX_EN_RATE_RESET_BUF">GTX1:RX_EN_RATE_RESET_BUF</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_2" title="GTX1:CHAN_BOND_SEQ_2_2[0]">GTX1:CHAN_BOND_SEQ_2_2[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[0]">GTX1:DRP09[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_2" title="GTX1:CHAN_BOND_SEQ_2_2[1]">GTX1:CHAN_BOND_SEQ_2_2[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[1]">GTX1:DRP09[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_2" title="GTX1:CHAN_BOND_SEQ_2_2[2]">GTX1:CHAN_BOND_SEQ_2_2[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[2]">GTX1:DRP09[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_2" title="GTX1:CHAN_BOND_SEQ_2_2[3]">GTX1:CHAN_BOND_SEQ_2_2[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[3]">GTX1:DRP09[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_2" title="GTX1:CHAN_BOND_SEQ_2_2[4]">GTX1:CHAN_BOND_SEQ_2_2[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[4]">GTX1:DRP09[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_2" title="GTX1:CHAN_BOND_SEQ_2_2[5]">GTX1:CHAN_BOND_SEQ_2_2[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[5]">GTX1:DRP09[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_2" title="GTX1:CHAN_BOND_SEQ_2_2[6]">GTX1:CHAN_BOND_SEQ_2_2[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[6]">GTX1:DRP09[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_2" title="GTX1:CHAN_BOND_SEQ_2_2[7]">GTX1:CHAN_BOND_SEQ_2_2[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[7]">GTX1:DRP09[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_2" title="GTX1:CHAN_BOND_SEQ_2_2[8]">GTX1:CHAN_BOND_SEQ_2_2[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[8]">GTX1:DRP09[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_2" title="GTX1:CHAN_BOND_SEQ_2_2[9]">GTX1:CHAN_BOND_SEQ_2_2[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[9]">GTX1:DRP09[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_2_MAX_SKEW" title="GTX1:CHAN_BOND_2_MAX_SKEW[0]">GTX1:CHAN_BOND_2_MAX_SKEW[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[10]">GTX1:DRP09[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_2_MAX_SKEW" title="GTX1:CHAN_BOND_2_MAX_SKEW[1]">GTX1:CHAN_BOND_2_MAX_SKEW[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[11]">GTX1:DRP09[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_2_MAX_SKEW" title="GTX1:CHAN_BOND_2_MAX_SKEW[2]">GTX1:CHAN_BOND_2_MAX_SKEW[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[12]">GTX1:DRP09[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_2_MAX_SKEW" title="GTX1:CHAN_BOND_2_MAX_SKEW[3]">GTX1:CHAN_BOND_2_MAX_SKEW[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[13]">GTX1:DRP09[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_KEEP_ALIGN" title="GTX1:CHAN_BOND_KEEP_ALIGN">GTX1:CHAN_BOND_KEEP_ALIGN</a><br><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[14]">GTX1:DRP09[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP09" title="GTX1:DRP09[15]">GTX1:DRP09[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EN_MODE_RESET_BUF" title="GTX1:RX_EN_MODE_RESET_BUF">GTX1:RX_EN_MODE_RESET_BUF</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_3" title="GTX1:CHAN_BOND_SEQ_2_3[0]">GTX1:CHAN_BOND_SEQ_2_3[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[0]">GTX1:DRP0A[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_3" title="GTX1:CHAN_BOND_SEQ_2_3[1]">GTX1:CHAN_BOND_SEQ_2_3[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[1]">GTX1:DRP0A[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_3" title="GTX1:CHAN_BOND_SEQ_2_3[2]">GTX1:CHAN_BOND_SEQ_2_3[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[2]">GTX1:DRP0A[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_3" title="GTX1:CHAN_BOND_SEQ_2_3[3]">GTX1:CHAN_BOND_SEQ_2_3[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[3]">GTX1:DRP0A[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_3" title="GTX1:CHAN_BOND_SEQ_2_3[4]">GTX1:CHAN_BOND_SEQ_2_3[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[4]">GTX1:DRP0A[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_3" title="GTX1:CHAN_BOND_SEQ_2_3[5]">GTX1:CHAN_BOND_SEQ_2_3[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[5]">GTX1:DRP0A[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_3" title="GTX1:CHAN_BOND_SEQ_2_3[6]">GTX1:CHAN_BOND_SEQ_2_3[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[6]">GTX1:DRP0A[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_3" title="GTX1:CHAN_BOND_SEQ_2_3[7]">GTX1:CHAN_BOND_SEQ_2_3[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[7]">GTX1:DRP0A[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_3" title="GTX1:CHAN_BOND_SEQ_2_3[8]">GTX1:CHAN_BOND_SEQ_2_3[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[8]">GTX1:DRP0A[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_3" title="GTX1:CHAN_BOND_SEQ_2_3[9]">GTX1:CHAN_BOND_SEQ_2_3[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[9]">GTX1:DRP0A[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_CFG" title="GTX1:CHAN_BOND_SEQ_2_CFG[0]">GTX1:CHAN_BOND_SEQ_2_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[10]">GTX1:DRP0A[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_CFG" title="GTX1:CHAN_BOND_SEQ_2_CFG[1]">GTX1:CHAN_BOND_SEQ_2_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[11]">GTX1:DRP0A[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_CFG" title="GTX1:CHAN_BOND_SEQ_2_CFG[2]">GTX1:CHAN_BOND_SEQ_2_CFG[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[12]">GTX1:DRP0A[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_CFG" title="GTX1:CHAN_BOND_SEQ_2_CFG[3]">GTX1:CHAN_BOND_SEQ_2_CFG[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[13]">GTX1:DRP0A[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_USE" title="GTX1:CHAN_BOND_SEQ_2_USE">GTX1:CHAN_BOND_SEQ_2_USE</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[14]">GTX1:DRP0A[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP0A" title="GTX1:DRP0A[15]">GTX1:DRP0A[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EN_IDLE_RESET_PH" title="GTX1:RX_EN_IDLE_RESET_PH">GTX1:RX_EN_IDLE_RESET_PH</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_4" title="GTX1:CHAN_BOND_SEQ_2_4[0]">GTX1:CHAN_BOND_SEQ_2_4[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[0]">GTX1:DRP0B[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_4" title="GTX1:CHAN_BOND_SEQ_2_4[1]">GTX1:CHAN_BOND_SEQ_2_4[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[1]">GTX1:DRP0B[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_4" title="GTX1:CHAN_BOND_SEQ_2_4[2]">GTX1:CHAN_BOND_SEQ_2_4[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[2]">GTX1:DRP0B[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_4" title="GTX1:CHAN_BOND_SEQ_2_4[3]">GTX1:CHAN_BOND_SEQ_2_4[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[3]">GTX1:DRP0B[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_4" title="GTX1:CHAN_BOND_SEQ_2_4[4]">GTX1:CHAN_BOND_SEQ_2_4[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[4]">GTX1:DRP0B[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_4" title="GTX1:CHAN_BOND_SEQ_2_4[5]">GTX1:CHAN_BOND_SEQ_2_4[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[5]">GTX1:DRP0B[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_4" title="GTX1:CHAN_BOND_SEQ_2_4[6]">GTX1:CHAN_BOND_SEQ_2_4[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[6]">GTX1:DRP0B[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_4" title="GTX1:CHAN_BOND_SEQ_2_4[7]">GTX1:CHAN_BOND_SEQ_2_4[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[7]">GTX1:DRP0B[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_4" title="GTX1:CHAN_BOND_SEQ_2_4[8]">GTX1:CHAN_BOND_SEQ_2_4[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[8]">GTX1:DRP0B[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_4" title="GTX1:CHAN_BOND_SEQ_2_4[9]">GTX1:CHAN_BOND_SEQ_2_4[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[9]">GTX1:DRP0B[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[10]">GTX1:DRP0B[10]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EN_IDLE_RESET_BUF" title="GTX1:RX_EN_IDLE_RESET_BUF">GTX1:RX_EN_IDLE_RESET_BUF</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[11]">GTX1:DRP0B[11]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_XCLK_SEL" title="GTX1:RX_XCLK_SEL">GTX1:RX_XCLK_SEL</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[12]">GTX1:DRP0B[12]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_IDLE_HI_CNT" title="GTX1:RX_IDLE_HI_CNT[0]">GTX1:RX_IDLE_HI_CNT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[13]">GTX1:DRP0B[13]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_IDLE_HI_CNT" title="GTX1:RX_IDLE_HI_CNT[1]">GTX1:RX_IDLE_HI_CNT[1]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[14]">GTX1:DRP0B[14]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_IDLE_HI_CNT" title="GTX1:RX_IDLE_HI_CNT[2]">GTX1:RX_IDLE_HI_CNT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP0B" title="GTX1:DRP0B[15]">GTX1:DRP0B[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_IDLE_HI_CNT" title="GTX1:RX_IDLE_HI_CNT[3]">GTX1:RX_IDLE_HI_CNT[3]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[0]">GTX1:DRP0C[0]</a><br><a href="#bits-xc6v-GTX-GTX1:RXBUF_OVFL_THRESH" title="GTX1:RXBUF_OVFL_THRESH[0]">GTX1:RXBUF_OVFL_THRESH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[1]">GTX1:DRP0C[1]</a><br><a href="#bits-xc6v-GTX-GTX1:RXBUF_OVFL_THRESH" title="GTX1:RXBUF_OVFL_THRESH[1]">GTX1:RXBUF_OVFL_THRESH[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[2]">GTX1:DRP0C[2]</a><br><a href="#bits-xc6v-GTX-GTX1:RXBUF_OVFL_THRESH" title="GTX1:RXBUF_OVFL_THRESH[2]">GTX1:RXBUF_OVFL_THRESH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[3]">GTX1:DRP0C[3]</a><br><a href="#bits-xc6v-GTX-GTX1:RXBUF_OVFL_THRESH" title="GTX1:RXBUF_OVFL_THRESH[3]">GTX1:RXBUF_OVFL_THRESH[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[4]">GTX1:DRP0C[4]</a><br><a href="#bits-xc6v-GTX-GTX1:RXBUF_OVFL_THRESH" title="GTX1:RXBUF_OVFL_THRESH[4]">GTX1:RXBUF_OVFL_THRESH[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[5]">GTX1:DRP0C[5]</a><br><a href="#bits-xc6v-GTX-GTX1:RXBUF_OVFL_THRESH" title="GTX1:RXBUF_OVFL_THRESH[5]">GTX1:RXBUF_OVFL_THRESH[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[6]">GTX1:DRP0C[6]</a><br><a href="#bits-xc6v-GTX-GTX1:RXBUF_UDFL_THRESH" title="GTX1:RXBUF_UDFL_THRESH[0]">GTX1:RXBUF_UDFL_THRESH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[7]">GTX1:DRP0C[7]</a><br><a href="#bits-xc6v-GTX-GTX1:RXBUF_UDFL_THRESH" title="GTX1:RXBUF_UDFL_THRESH[1]">GTX1:RXBUF_UDFL_THRESH[1]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[8]">GTX1:DRP0C[8]</a><br><a href="#bits-xc6v-GTX-GTX1:RXBUF_UDFL_THRESH" title="GTX1:RXBUF_UDFL_THRESH[2]">GTX1:RXBUF_UDFL_THRESH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[9]">GTX1:DRP0C[9]</a><br><a href="#bits-xc6v-GTX-GTX1:RXBUF_UDFL_THRESH" title="GTX1:RXBUF_UDFL_THRESH[3]">GTX1:RXBUF_UDFL_THRESH[3]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[10]">GTX1:DRP0C[10]</a><br><a href="#bits-xc6v-GTX-GTX1:RXBUF_UDFL_THRESH" title="GTX1:RXBUF_UDFL_THRESH[4]">GTX1:RXBUF_UDFL_THRESH[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[11]">GTX1:DRP0C[11]</a><br><a href="#bits-xc6v-GTX-GTX1:RXBUF_UDFL_THRESH" title="GTX1:RXBUF_UDFL_THRESH[5]">GTX1:RXBUF_UDFL_THRESH[5]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[12]">GTX1:DRP0C[12]</a><br><a href="#bits-xc6v-GTX-GTX1:RXBUF_OVRD_THRESH" title="GTX1:RXBUF_OVRD_THRESH">GTX1:RXBUF_OVRD_THRESH</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[13]">GTX1:DRP0C[13]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_FIFO_ADDR_MODE" title="GTX1:RX_FIFO_ADDR_MODE">GTX1:RX_FIFO_ADDR_MODE</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[14]">GTX1:DRP0C[14]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX0:CLKCM_CFG" title="IBUFDS_GTX0:CLKCM_CFG">IBUFDS_GTX0:CLKCM_CFG</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP0C" title="GTX1:DRP0C[15]">GTX1:DRP0C[15]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX1:CLKCM_CFG" title="IBUFDS_GTX1:CLKCM_CFG">IBUFDS_GTX1:CLKCM_CFG</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_1" title="GTX1:CLK_COR_SEQ_1_1[0]">GTX1:CLK_COR_SEQ_1_1[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[0]">GTX1:DRP0D[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_1" title="GTX1:CLK_COR_SEQ_1_1[1]">GTX1:CLK_COR_SEQ_1_1[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[1]">GTX1:DRP0D[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_1" title="GTX1:CLK_COR_SEQ_1_1[2]">GTX1:CLK_COR_SEQ_1_1[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[2]">GTX1:DRP0D[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_1" title="GTX1:CLK_COR_SEQ_1_1[3]">GTX1:CLK_COR_SEQ_1_1[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[3]">GTX1:DRP0D[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_1" title="GTX1:CLK_COR_SEQ_1_1[4]">GTX1:CLK_COR_SEQ_1_1[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[4]">GTX1:DRP0D[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_1" title="GTX1:CLK_COR_SEQ_1_1[5]">GTX1:CLK_COR_SEQ_1_1[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[5]">GTX1:DRP0D[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_1" title="GTX1:CLK_COR_SEQ_1_1[6]">GTX1:CLK_COR_SEQ_1_1[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[6]">GTX1:DRP0D[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_1" title="GTX1:CLK_COR_SEQ_1_1[7]">GTX1:CLK_COR_SEQ_1_1[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[7]">GTX1:DRP0D[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_1" title="GTX1:CLK_COR_SEQ_1_1[8]">GTX1:CLK_COR_SEQ_1_1[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[8]">GTX1:DRP0D[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_1" title="GTX1:CLK_COR_SEQ_1_1[9]">GTX1:CLK_COR_SEQ_1_1[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[9]">GTX1:DRP0D[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_ENABLE" title="GTX1:CLK_COR_SEQ_1_ENABLE[0]">GTX1:CLK_COR_SEQ_1_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[10]">GTX1:DRP0D[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_ENABLE" title="GTX1:CLK_COR_SEQ_1_ENABLE[1]">GTX1:CLK_COR_SEQ_1_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[11]">GTX1:DRP0D[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_ENABLE" title="GTX1:CLK_COR_SEQ_1_ENABLE[2]">GTX1:CLK_COR_SEQ_1_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[12]">GTX1:DRP0D[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_ENABLE" title="GTX1:CLK_COR_SEQ_1_ENABLE[3]">GTX1:CLK_COR_SEQ_1_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[13]">GTX1:DRP0D[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_CORRECT_USE" title="GTX1:CLK_CORRECT_USE">GTX1:CLK_CORRECT_USE</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[14]">GTX1:DRP0D[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_PRECEDENCE" title="GTX1:CLK_COR_PRECEDENCE">GTX1:CLK_COR_PRECEDENCE</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0D" title="GTX1:DRP0D[15]">GTX1:DRP0D[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_2" title="GTX1:CLK_COR_SEQ_1_2[0]">GTX1:CLK_COR_SEQ_1_2[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[0]">GTX1:DRP0E[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_2" title="GTX1:CLK_COR_SEQ_1_2[1]">GTX1:CLK_COR_SEQ_1_2[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[1]">GTX1:DRP0E[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_2" title="GTX1:CLK_COR_SEQ_1_2[2]">GTX1:CLK_COR_SEQ_1_2[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[2]">GTX1:DRP0E[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_2" title="GTX1:CLK_COR_SEQ_1_2[3]">GTX1:CLK_COR_SEQ_1_2[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[3]">GTX1:DRP0E[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_2" title="GTX1:CLK_COR_SEQ_1_2[4]">GTX1:CLK_COR_SEQ_1_2[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[4]">GTX1:DRP0E[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_2" title="GTX1:CLK_COR_SEQ_1_2[5]">GTX1:CLK_COR_SEQ_1_2[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[5]">GTX1:DRP0E[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_2" title="GTX1:CLK_COR_SEQ_1_2[6]">GTX1:CLK_COR_SEQ_1_2[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[6]">GTX1:DRP0E[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_2" title="GTX1:CLK_COR_SEQ_1_2[7]">GTX1:CLK_COR_SEQ_1_2[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[7]">GTX1:DRP0E[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_2" title="GTX1:CLK_COR_SEQ_1_2[8]">GTX1:CLK_COR_SEQ_1_2[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[8]">GTX1:DRP0E[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_2" title="GTX1:CLK_COR_SEQ_1_2[9]">GTX1:CLK_COR_SEQ_1_2[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[9]">GTX1:DRP0E[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_REPEAT_WAIT" title="GTX1:CLK_COR_REPEAT_WAIT[0]">GTX1:CLK_COR_REPEAT_WAIT[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[10]">GTX1:DRP0E[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_REPEAT_WAIT" title="GTX1:CLK_COR_REPEAT_WAIT[1]">GTX1:CLK_COR_REPEAT_WAIT[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[11]">GTX1:DRP0E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_REPEAT_WAIT" title="GTX1:CLK_COR_REPEAT_WAIT[2]">GTX1:CLK_COR_REPEAT_WAIT[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[12]">GTX1:DRP0E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_REPEAT_WAIT" title="GTX1:CLK_COR_REPEAT_WAIT[3]">GTX1:CLK_COR_REPEAT_WAIT[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[13]">GTX1:DRP0E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_REPEAT_WAIT" title="GTX1:CLK_COR_REPEAT_WAIT[4]">GTX1:CLK_COR_REPEAT_WAIT[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[14]">GTX1:DRP0E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_KEEP_IDLE" title="GTX1:CLK_COR_KEEP_IDLE">GTX1:CLK_COR_KEEP_IDLE</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0E" title="GTX1:DRP0E[15]">GTX1:DRP0E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_3" title="GTX1:CLK_COR_SEQ_1_3[0]">GTX1:CLK_COR_SEQ_1_3[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[0]">GTX1:DRP0F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_3" title="GTX1:CLK_COR_SEQ_1_3[1]">GTX1:CLK_COR_SEQ_1_3[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[1]">GTX1:DRP0F[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_3" title="GTX1:CLK_COR_SEQ_1_3[2]">GTX1:CLK_COR_SEQ_1_3[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[2]">GTX1:DRP0F[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_3" title="GTX1:CLK_COR_SEQ_1_3[3]">GTX1:CLK_COR_SEQ_1_3[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[3]">GTX1:DRP0F[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_3" title="GTX1:CLK_COR_SEQ_1_3[4]">GTX1:CLK_COR_SEQ_1_3[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[4]">GTX1:DRP0F[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_3" title="GTX1:CLK_COR_SEQ_1_3[5]">GTX1:CLK_COR_SEQ_1_3[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[5]">GTX1:DRP0F[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_3" title="GTX1:CLK_COR_SEQ_1_3[6]">GTX1:CLK_COR_SEQ_1_3[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[6]">GTX1:DRP0F[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_3" title="GTX1:CLK_COR_SEQ_1_3[7]">GTX1:CLK_COR_SEQ_1_3[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[7]">GTX1:DRP0F[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_3" title="GTX1:CLK_COR_SEQ_1_3[8]">GTX1:CLK_COR_SEQ_1_3[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[8]">GTX1:DRP0F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_3" title="GTX1:CLK_COR_SEQ_1_3[9]">GTX1:CLK_COR_SEQ_1_3[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[9]">GTX1:DRP0F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_MIN_LAT" title="GTX1:CLK_COR_MIN_LAT[0]">GTX1:CLK_COR_MIN_LAT[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[10]">GTX1:DRP0F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_MIN_LAT" title="GTX1:CLK_COR_MIN_LAT[1]">GTX1:CLK_COR_MIN_LAT[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[11]">GTX1:DRP0F[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_MIN_LAT" title="GTX1:CLK_COR_MIN_LAT[2]">GTX1:CLK_COR_MIN_LAT[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[12]">GTX1:DRP0F[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_MIN_LAT" title="GTX1:CLK_COR_MIN_LAT[3]">GTX1:CLK_COR_MIN_LAT[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[13]">GTX1:DRP0F[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_MIN_LAT" title="GTX1:CLK_COR_MIN_LAT[4]">GTX1:CLK_COR_MIN_LAT[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[14]">GTX1:DRP0F[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_MIN_LAT" title="GTX1:CLK_COR_MIN_LAT[5]">GTX1:CLK_COR_MIN_LAT[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP0F" title="GTX1:DRP0F[15]">GTX1:DRP0F[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 12</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_4" title="GTX1:CLK_COR_SEQ_1_4[0]">GTX1:CLK_COR_SEQ_1_4[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[0]">GTX1:DRP10[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_4" title="GTX1:CLK_COR_SEQ_1_4[1]">GTX1:CLK_COR_SEQ_1_4[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[1]">GTX1:DRP10[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_4" title="GTX1:CLK_COR_SEQ_1_4[2]">GTX1:CLK_COR_SEQ_1_4[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[2]">GTX1:DRP10[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_4" title="GTX1:CLK_COR_SEQ_1_4[3]">GTX1:CLK_COR_SEQ_1_4[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[3]">GTX1:DRP10[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_4" title="GTX1:CLK_COR_SEQ_1_4[4]">GTX1:CLK_COR_SEQ_1_4[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[4]">GTX1:DRP10[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_4" title="GTX1:CLK_COR_SEQ_1_4[5]">GTX1:CLK_COR_SEQ_1_4[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[5]">GTX1:DRP10[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_4" title="GTX1:CLK_COR_SEQ_1_4[6]">GTX1:CLK_COR_SEQ_1_4[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[6]">GTX1:DRP10[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_4" title="GTX1:CLK_COR_SEQ_1_4[7]">GTX1:CLK_COR_SEQ_1_4[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[7]">GTX1:DRP10[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_4" title="GTX1:CLK_COR_SEQ_1_4[8]">GTX1:CLK_COR_SEQ_1_4[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[8]">GTX1:DRP10[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_4" title="GTX1:CLK_COR_SEQ_1_4[9]">GTX1:CLK_COR_SEQ_1_4[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[9]">GTX1:DRP10[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_MAX_LAT" title="GTX1:CLK_COR_MAX_LAT[0]">GTX1:CLK_COR_MAX_LAT[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[10]">GTX1:DRP10[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_MAX_LAT" title="GTX1:CLK_COR_MAX_LAT[1]">GTX1:CLK_COR_MAX_LAT[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[11]">GTX1:DRP10[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_MAX_LAT" title="GTX1:CLK_COR_MAX_LAT[2]">GTX1:CLK_COR_MAX_LAT[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[12]">GTX1:DRP10[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_MAX_LAT" title="GTX1:CLK_COR_MAX_LAT[3]">GTX1:CLK_COR_MAX_LAT[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[13]">GTX1:DRP10[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_MAX_LAT" title="GTX1:CLK_COR_MAX_LAT[4]">GTX1:CLK_COR_MAX_LAT[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[14]">GTX1:DRP10[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_MAX_LAT" title="GTX1:CLK_COR_MAX_LAT[5]">GTX1:CLK_COR_MAX_LAT[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP10" title="GTX1:DRP10[15]">GTX1:DRP10[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_1" title="GTX1:CLK_COR_SEQ_2_1[0]">GTX1:CLK_COR_SEQ_2_1[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[0]">GTX1:DRP11[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_1" title="GTX1:CLK_COR_SEQ_2_1[1]">GTX1:CLK_COR_SEQ_2_1[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[1]">GTX1:DRP11[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_1" title="GTX1:CLK_COR_SEQ_2_1[2]">GTX1:CLK_COR_SEQ_2_1[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[2]">GTX1:DRP11[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_1" title="GTX1:CLK_COR_SEQ_2_1[3]">GTX1:CLK_COR_SEQ_2_1[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[3]">GTX1:DRP11[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_1" title="GTX1:CLK_COR_SEQ_2_1[4]">GTX1:CLK_COR_SEQ_2_1[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[4]">GTX1:DRP11[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_1" title="GTX1:CLK_COR_SEQ_2_1[5]">GTX1:CLK_COR_SEQ_2_1[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[5]">GTX1:DRP11[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_1" title="GTX1:CLK_COR_SEQ_2_1[6]">GTX1:CLK_COR_SEQ_2_1[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[6]">GTX1:DRP11[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_1" title="GTX1:CLK_COR_SEQ_2_1[7]">GTX1:CLK_COR_SEQ_2_1[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[7]">GTX1:DRP11[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_1" title="GTX1:CLK_COR_SEQ_2_1[8]">GTX1:CLK_COR_SEQ_2_1[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[8]">GTX1:DRP11[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_1" title="GTX1:CLK_COR_SEQ_2_1[9]">GTX1:CLK_COR_SEQ_2_1[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[9]">GTX1:DRP11[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_ENABLE" title="GTX1:CLK_COR_SEQ_2_ENABLE[0]">GTX1:CLK_COR_SEQ_2_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[10]">GTX1:DRP11[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_ENABLE" title="GTX1:CLK_COR_SEQ_2_ENABLE[1]">GTX1:CLK_COR_SEQ_2_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[11]">GTX1:DRP11[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_ENABLE" title="GTX1:CLK_COR_SEQ_2_ENABLE[2]">GTX1:CLK_COR_SEQ_2_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[12]">GTX1:DRP11[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_ENABLE" title="GTX1:CLK_COR_SEQ_2_ENABLE[3]">GTX1:CLK_COR_SEQ_2_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[13]">GTX1:DRP11[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_USE" title="GTX1:CLK_COR_SEQ_2_USE">GTX1:CLK_COR_SEQ_2_USE</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[14]">GTX1:DRP11[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_INSERT_IDLE_FLAG" title="GTX1:CLK_COR_INSERT_IDLE_FLAG">GTX1:CLK_COR_INSERT_IDLE_FLAG</a><br><a href="#bits-xc6v-GTX-GTX1:DRP11" title="GTX1:DRP11[15]">GTX1:DRP11[15]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_2" title="GTX1:CLK_COR_SEQ_2_2[0]">GTX1:CLK_COR_SEQ_2_2[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[0]">GTX1:DRP12[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_2" title="GTX1:CLK_COR_SEQ_2_2[1]">GTX1:CLK_COR_SEQ_2_2[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[1]">GTX1:DRP12[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_2" title="GTX1:CLK_COR_SEQ_2_2[2]">GTX1:CLK_COR_SEQ_2_2[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[2]">GTX1:DRP12[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_2" title="GTX1:CLK_COR_SEQ_2_2[3]">GTX1:CLK_COR_SEQ_2_2[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[3]">GTX1:DRP12[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_2" title="GTX1:CLK_COR_SEQ_2_2[4]">GTX1:CLK_COR_SEQ_2_2[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[4]">GTX1:DRP12[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_2" title="GTX1:CLK_COR_SEQ_2_2[5]">GTX1:CLK_COR_SEQ_2_2[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[5]">GTX1:DRP12[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_2" title="GTX1:CLK_COR_SEQ_2_2[6]">GTX1:CLK_COR_SEQ_2_2[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[6]">GTX1:DRP12[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_2" title="GTX1:CLK_COR_SEQ_2_2[7]">GTX1:CLK_COR_SEQ_2_2[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[7]">GTX1:DRP12[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_2" title="GTX1:CLK_COR_SEQ_2_2[8]">GTX1:CLK_COR_SEQ_2_2[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[8]">GTX1:DRP12[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_2" title="GTX1:CLK_COR_SEQ_2_2[9]">GTX1:CLK_COR_SEQ_2_2[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[9]">GTX1:DRP12[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_ADJ_LEN" title="GTX1:CLK_COR_ADJ_LEN[0]">GTX1:CLK_COR_ADJ_LEN[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[10]">GTX1:DRP12[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_ADJ_LEN" title="GTX1:CLK_COR_ADJ_LEN[1]">GTX1:CLK_COR_ADJ_LEN[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[11]">GTX1:DRP12[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[12]">GTX1:DRP12[12]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_SLIDE_MODE" title="GTX1:RX_SLIDE_MODE[0]">GTX1:RX_SLIDE_MODE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[13]">GTX1:DRP12[13]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_SLIDE_MODE" title="GTX1:RX_SLIDE_MODE[1]">GTX1:RX_SLIDE_MODE[1]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[14]">GTX1:DRP12[14]</a><br><a href="#bits-xc6v-GTX-GTX1:SHOW_REALIGN_COMMA" title="GTX1:SHOW_REALIGN_COMMA">GTX1:SHOW_REALIGN_COMMA</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP12" title="GTX1:DRP12[15]">GTX1:DRP12[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_CDR_FORCE_ROTATE" title="GTX1:RX_CDR_FORCE_ROTATE">GTX1:RX_CDR_FORCE_ROTATE</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_3" title="GTX1:CLK_COR_SEQ_2_3[0]">GTX1:CLK_COR_SEQ_2_3[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[0]">GTX1:DRP13[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_3" title="GTX1:CLK_COR_SEQ_2_3[1]">GTX1:CLK_COR_SEQ_2_3[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[1]">GTX1:DRP13[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_3" title="GTX1:CLK_COR_SEQ_2_3[2]">GTX1:CLK_COR_SEQ_2_3[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[2]">GTX1:DRP13[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_3" title="GTX1:CLK_COR_SEQ_2_3[3]">GTX1:CLK_COR_SEQ_2_3[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[3]">GTX1:DRP13[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_3" title="GTX1:CLK_COR_SEQ_2_3[4]">GTX1:CLK_COR_SEQ_2_3[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[4]">GTX1:DRP13[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_3" title="GTX1:CLK_COR_SEQ_2_3[5]">GTX1:CLK_COR_SEQ_2_3[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[5]">GTX1:DRP13[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_3" title="GTX1:CLK_COR_SEQ_2_3[6]">GTX1:CLK_COR_SEQ_2_3[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[6]">GTX1:DRP13[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_3" title="GTX1:CLK_COR_SEQ_2_3[7]">GTX1:CLK_COR_SEQ_2_3[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[7]">GTX1:DRP13[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_3" title="GTX1:CLK_COR_SEQ_2_3[8]">GTX1:CLK_COR_SEQ_2_3[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[8]">GTX1:DRP13[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_3" title="GTX1:CLK_COR_SEQ_2_3[9]">GTX1:CLK_COR_SEQ_2_3[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[9]">GTX1:DRP13[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_DET_LEN" title="GTX1:CLK_COR_DET_LEN[0]">GTX1:CLK_COR_DET_LEN[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[10]">GTX1:DRP13[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_DET_LEN" title="GTX1:CLK_COR_DET_LEN[1]">GTX1:CLK_COR_DET_LEN[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[11]">GTX1:DRP13[11]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[12]">GTX1:DRP13[12]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_SLIDE_AUTO_WAIT" title="GTX1:RX_SLIDE_AUTO_WAIT[0]">GTX1:RX_SLIDE_AUTO_WAIT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[13]">GTX1:DRP13[13]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_SLIDE_AUTO_WAIT" title="GTX1:RX_SLIDE_AUTO_WAIT[1]">GTX1:RX_SLIDE_AUTO_WAIT[1]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[14]">GTX1:DRP13[14]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_SLIDE_AUTO_WAIT" title="GTX1:RX_SLIDE_AUTO_WAIT[2]">GTX1:RX_SLIDE_AUTO_WAIT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP13" title="GTX1:DRP13[15]">GTX1:DRP13[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_SLIDE_AUTO_WAIT" title="GTX1:RX_SLIDE_AUTO_WAIT[3]">GTX1:RX_SLIDE_AUTO_WAIT[3]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_4" title="GTX1:CLK_COR_SEQ_2_4[0]">GTX1:CLK_COR_SEQ_2_4[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[0]">GTX1:DRP14[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_4" title="GTX1:CLK_COR_SEQ_2_4[1]">GTX1:CLK_COR_SEQ_2_4[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[1]">GTX1:DRP14[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_4" title="GTX1:CLK_COR_SEQ_2_4[2]">GTX1:CLK_COR_SEQ_2_4[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[2]">GTX1:DRP14[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_4" title="GTX1:CLK_COR_SEQ_2_4[3]">GTX1:CLK_COR_SEQ_2_4[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[3]">GTX1:DRP14[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_4" title="GTX1:CLK_COR_SEQ_2_4[4]">GTX1:CLK_COR_SEQ_2_4[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[4]">GTX1:DRP14[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_4" title="GTX1:CLK_COR_SEQ_2_4[5]">GTX1:CLK_COR_SEQ_2_4[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[5]">GTX1:DRP14[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_4" title="GTX1:CLK_COR_SEQ_2_4[6]">GTX1:CLK_COR_SEQ_2_4[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[6]">GTX1:DRP14[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_4" title="GTX1:CLK_COR_SEQ_2_4[7]">GTX1:CLK_COR_SEQ_2_4[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[7]">GTX1:DRP14[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_4" title="GTX1:CLK_COR_SEQ_2_4[8]">GTX1:CLK_COR_SEQ_2_4[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[8]">GTX1:DRP14[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_4" title="GTX1:CLK_COR_SEQ_2_4[9]">GTX1:CLK_COR_SEQ_2_4[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[9]">GTX1:DRP14[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DEC_PCOMMA_DETECT" title="GTX1:DEC_PCOMMA_DETECT">GTX1:DEC_PCOMMA_DETECT</a><br><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[10]">GTX1:DRP14[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DEC_MCOMMA_DETECT" title="GTX1:DEC_MCOMMA_DETECT">GTX1:DEC_MCOMMA_DETECT</a><br><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[11]">GTX1:DRP14[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[12]">GTX1:DRP14[12]</a><br><a href="#bits-xc6v-GTX-GTX1:USR_CODE_ERR_CLR" title="GTX1:USR_CODE_ERR_CLR">GTX1:USR_CODE_ERR_CLR</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[13]">GTX1:DRP14[13]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DECODE_SEQ_MATCH" title="GTX1:RX_DECODE_SEQ_MATCH">GTX1:RX_DECODE_SEQ_MATCH</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:ALIGN_COMMA_WORD" title="GTX1:ALIGN_COMMA_WORD">GTX1:ALIGN_COMMA_WORD</a><br><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[14]">GTX1:DRP14[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DEC_VALID_COMMA_ONLY" title="GTX1:DEC_VALID_COMMA_ONLY">GTX1:DEC_VALID_COMMA_ONLY</a><br><a href="#bits-xc6v-GTX-GTX1:DRP14" title="GTX1:DRP14[15]">GTX1:DRP14[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[0]">GTX1:DRP15[0]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[0]">GTX1:PMA_CDR_SCAN[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[1]">GTX1:DRP15[1]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[1]">GTX1:PMA_CDR_SCAN[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[2]">GTX1:DRP15[2]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[2]">GTX1:PMA_CDR_SCAN[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[3]">GTX1:DRP15[3]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[3]">GTX1:PMA_CDR_SCAN[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[4]">GTX1:DRP15[4]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[4]">GTX1:PMA_CDR_SCAN[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[5]">GTX1:DRP15[5]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[5]">GTX1:PMA_CDR_SCAN[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[6]">GTX1:DRP15[6]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[6]">GTX1:PMA_CDR_SCAN[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[7]">GTX1:DRP15[7]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[7]">GTX1:PMA_CDR_SCAN[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[8]">GTX1:DRP15[8]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[8]">GTX1:PMA_CDR_SCAN[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[9]">GTX1:DRP15[9]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[9]">GTX1:PMA_CDR_SCAN[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[10]">GTX1:DRP15[10]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[10]">GTX1:PMA_CDR_SCAN[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[11]">GTX1:DRP15[11]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[11]">GTX1:PMA_CDR_SCAN[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[12]">GTX1:DRP15[12]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[12]">GTX1:PMA_CDR_SCAN[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[13]">GTX1:DRP15[13]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[13]">GTX1:PMA_CDR_SCAN[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[14]">GTX1:DRP15[14]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[14]">GTX1:PMA_CDR_SCAN[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP15" title="GTX1:DRP15[15]">GTX1:DRP15[15]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[15]">GTX1:PMA_CDR_SCAN[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[0]">GTX1:DRP16[0]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[16]">GTX1:PMA_CDR_SCAN[16]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[1]">GTX1:DRP16[1]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[17]">GTX1:PMA_CDR_SCAN[17]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[2]">GTX1:DRP16[2]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[18]">GTX1:PMA_CDR_SCAN[18]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[3]">GTX1:DRP16[3]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[19]">GTX1:PMA_CDR_SCAN[19]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[4]">GTX1:DRP16[4]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[20]">GTX1:PMA_CDR_SCAN[20]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[5]">GTX1:DRP16[5]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[21]">GTX1:PMA_CDR_SCAN[21]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[6]">GTX1:DRP16[6]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[22]">GTX1:PMA_CDR_SCAN[22]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[7]">GTX1:DRP16[7]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[23]">GTX1:PMA_CDR_SCAN[23]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[8]">GTX1:DRP16[8]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[24]">GTX1:PMA_CDR_SCAN[24]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[9]">GTX1:DRP16[9]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[25]">GTX1:PMA_CDR_SCAN[25]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[10]">GTX1:DRP16[10]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CDR_SCAN" title="GTX1:PMA_CDR_SCAN[26]">GTX1:PMA_CDR_SCAN[26]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CDR_PH_ADJ_TIME" title="GTX1:CDR_PH_ADJ_TIME[0]">GTX1:CDR_PH_ADJ_TIME[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[11]">GTX1:DRP16[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CDR_PH_ADJ_TIME" title="GTX1:CDR_PH_ADJ_TIME[1]">GTX1:CDR_PH_ADJ_TIME[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[12]">GTX1:DRP16[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CDR_PH_ADJ_TIME" title="GTX1:CDR_PH_ADJ_TIME[2]">GTX1:CDR_PH_ADJ_TIME[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[13]">GTX1:DRP16[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CDR_PH_ADJ_TIME" title="GTX1:CDR_PH_ADJ_TIME[3]">GTX1:CDR_PH_ADJ_TIME[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[14]">GTX1:DRP16[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CDR_PH_ADJ_TIME" title="GTX1:CDR_PH_ADJ_TIME[4]">GTX1:CDR_PH_ADJ_TIME[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP16" title="GTX1:DRP16[15]">GTX1:DRP16[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[0]">GTX1:DRP17[0]</a><br><a href="#bits-xc6v-GTX-GTX1:OOBDETECT_THRESHOLD" title="GTX1:OOBDETECT_THRESHOLD[0]">GTX1:OOBDETECT_THRESHOLD[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[1]">GTX1:DRP17[1]</a><br><a href="#bits-xc6v-GTX-GTX1:OOBDETECT_THRESHOLD" title="GTX1:OOBDETECT_THRESHOLD[1]">GTX1:OOBDETECT_THRESHOLD[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[2]">GTX1:DRP17[2]</a><br><a href="#bits-xc6v-GTX-GTX1:OOBDETECT_THRESHOLD" title="GTX1:OOBDETECT_THRESHOLD[2]">GTX1:OOBDETECT_THRESHOLD[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[3]">GTX1:DRP17[3]</a><br><a href="#bits-xc6v-GTX-GTX1:GTX_CFG_PWRUP" title="GTX1:GTX_CFG_PWRUP">GTX1:GTX_CFG_PWRUP</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:AC_CAP_DIS" title="GTX1:AC_CAP_DIS">GTX1:AC_CAP_DIS</a><br><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[4]">GTX1:DRP17[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[5]">GTX1:DRP17[5]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_CLK25_DIVIDER" title="GTX1:RX_CLK25_DIVIDER[0]">GTX1:RX_CLK25_DIVIDER[0]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[6]">GTX1:DRP17[6]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_CLK25_DIVIDER" title="GTX1:RX_CLK25_DIVIDER[1]">GTX1:RX_CLK25_DIVIDER[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[7]">GTX1:DRP17[7]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_CLK25_DIVIDER" title="GTX1:RX_CLK25_DIVIDER[2]">GTX1:RX_CLK25_DIVIDER[2]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[8]">GTX1:DRP17[8]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_CLK25_DIVIDER" title="GTX1:RX_CLK25_DIVIDER[3]">GTX1:RX_CLK25_DIVIDER[3]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[9]">GTX1:DRP17[9]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_CLK25_DIVIDER" title="GTX1:RX_CLK25_DIVIDER[4]">GTX1:RX_CLK25_DIVIDER[4]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:BIAS_CFG" title="GTX1:BIAS_CFG[16]">GTX1:BIAS_CFG[16]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[10]">GTX1:DRP17[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_CFG" title="GTX1:CHAN_BOND_SEQ_2_CFG[4]">GTX1:CHAN_BOND_SEQ_2_CFG[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[11]">GTX1:DRP17[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[12]">GTX1:DRP17[12]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DATA_WIDTH" title="GTX1:RX_DATA_WIDTH[0]">GTX1:RX_DATA_WIDTH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[13]">GTX1:DRP17[13]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DATA_WIDTH" title="GTX1:RX_DATA_WIDTH[1]">GTX1:RX_DATA_WIDTH[1]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[14]">GTX1:DRP17[14]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DATA_WIDTH" title="GTX1:RX_DATA_WIDTH[2]">GTX1:RX_DATA_WIDTH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP17" title="GTX1:DRP17[15]">GTX1:DRP17[15]</a><br><a href="#bits-xc6v-GTX-GTX1:GEN_RXUSRCLK" title="GTX1:GEN_RXUSRCLK">GTX1:GEN_RXUSRCLK</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 13</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[0]">GTX1:DRP18[0]</a><br><a href="#bits-xc6v-GTX-GTX1:GEARBOX_ENDEC" title="GTX1:GEARBOX_ENDEC[0]">GTX1:GEARBOX_ENDEC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[1]">GTX1:DRP18[1]</a><br><a href="#bits-xc6v-GTX-GTX1:GEARBOX_ENDEC" title="GTX1:GEARBOX_ENDEC[1]">GTX1:GEARBOX_ENDEC[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[2]">GTX1:DRP18[2]</a><br><a href="#bits-xc6v-GTX-GTX1:GEARBOX_ENDEC" title="GTX1:GEARBOX_ENDEC[2]">GTX1:GEARBOX_ENDEC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[3]">GTX1:DRP18[3]</a><br><a href="#bits-xc6v-GTX-GTX1:RXGEARBOX_USE" title="GTX1:RXGEARBOX_USE">GTX1:RXGEARBOX_USE</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_RXCDRRESET" title="GTX1:A_RXCDRRESET">GTX1:A_RXCDRRESET</a><br><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[4]">GTX1:DRP18[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_GTXTXRESET" title="GTX1:A_GTXTXRESET">GTX1:A_GTXTXRESET</a><br><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[5]">GTX1:DRP18[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_GTXRXRESET" title="GTX1:A_GTXRXRESET">GTX1:A_GTXRXRESET</a><br><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[6]">GTX1:DRP18[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_RXBUFRESET" title="GTX1:A_RXBUFRESET">GTX1:A_RXBUFRESET</a><br><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[7]">GTX1:DRP18[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_RXRESET" title="GTX1:A_RXRESET">GTX1:A_RXRESET</a><br><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[8]">GTX1:DRP18[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXRESET" title="GTX1:A_TXRESET">GTX1:A_TXRESET</a><br><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[9]">GTX1:DRP18[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_RXCDRHOLD" title="GTX1:A_RXCDRHOLD">GTX1:A_RXCDRHOLD</a><br><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[10]">GTX1:DRP18[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_RXCDRFREQRESET" title="GTX1:A_RXCDRFREQRESET">GTX1:A_RXCDRFREQRESET</a><br><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[11]">GTX1:DRP18[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_RXCDRPHASERESET" title="GTX1:A_RXCDRPHASERESET">GTX1:A_RXCDRPHASERESET</a><br><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[12]">GTX1:DRP18[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_RXDFERESET" title="GTX1:A_RXDFERESET">GTX1:A_RXDFERESET</a><br><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[13]">GTX1:DRP18[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[14]">GTX1:DRP18[14]</a><br><a href="#bits-xc6v-GTX-GTX1:RESET_DRP_EN" title="GTX1:RESET_DRP_EN">GTX1:RESET_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP18" title="GTX1:DRP18[15]">GTX1:DRP18[15]</a><br><a href="#bits-xc6v-GTX-GTX1:MASTER_DRP_EN" title="GTX1:MASTER_DRP_EN">GTX1:MASTER_DRP_EN</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[0]">GTX1:DRP19[0]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[0]">GTX1:RXPLL_COM_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[1]">GTX1:DRP19[1]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[1]">GTX1:RXPLL_COM_CFG[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[2]">GTX1:DRP19[2]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[2]">GTX1:RXPLL_COM_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[3]">GTX1:DRP19[3]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[3]">GTX1:RXPLL_COM_CFG[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[4]">GTX1:DRP19[4]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[4]">GTX1:RXPLL_COM_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[5]">GTX1:DRP19[5]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[5]">GTX1:RXPLL_COM_CFG[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[6]">GTX1:DRP19[6]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[6]">GTX1:RXPLL_COM_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[7]">GTX1:DRP19[7]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[7]">GTX1:RXPLL_COM_CFG[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[8]">GTX1:DRP19[8]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[8]">GTX1:RXPLL_COM_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[9]">GTX1:DRP19[9]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[9]">GTX1:RXPLL_COM_CFG[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[10]">GTX1:DRP19[10]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[10]">GTX1:RXPLL_COM_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[11]">GTX1:DRP19[11]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[11]">GTX1:RXPLL_COM_CFG[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[12]">GTX1:DRP19[12]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[12]">GTX1:RXPLL_COM_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[13]">GTX1:DRP19[13]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[13]">GTX1:RXPLL_COM_CFG[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[14]">GTX1:DRP19[14]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[14]">GTX1:RXPLL_COM_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP19" title="GTX1:DRP19[15]">GTX1:DRP19[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[15]">GTX1:RXPLL_COM_CFG[15]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[0]">GTX1:DRP1A[0]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[16]">GTX1:RXPLL_COM_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[1]">GTX1:DRP1A[1]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[17]">GTX1:RXPLL_COM_CFG[17]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[2]">GTX1:DRP1A[2]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[18]">GTX1:RXPLL_COM_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[3]">GTX1:DRP1A[3]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[19]">GTX1:RXPLL_COM_CFG[19]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[4]">GTX1:DRP1A[4]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[20]">GTX1:RXPLL_COM_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[5]">GTX1:DRP1A[5]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[21]">GTX1:RXPLL_COM_CFG[21]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[6]">GTX1:DRP1A[6]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[22]">GTX1:RXPLL_COM_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[7]">GTX1:DRP1A[7]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_COM_CFG" title="GTX1:RXPLL_COM_CFG[23]">GTX1:RXPLL_COM_CFG[23]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[8]">GTX1:DRP1A[8]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_CP_CFG" title="GTX1:RXPLL_CP_CFG[0]">GTX1:RXPLL_CP_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[9]">GTX1:DRP1A[9]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_CP_CFG" title="GTX1:RXPLL_CP_CFG[1]">GTX1:RXPLL_CP_CFG[1]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[10]">GTX1:DRP1A[10]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_CP_CFG" title="GTX1:RXPLL_CP_CFG[2]">GTX1:RXPLL_CP_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[11]">GTX1:DRP1A[11]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_CP_CFG" title="GTX1:RXPLL_CP_CFG[3]">GTX1:RXPLL_CP_CFG[3]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[12]">GTX1:DRP1A[12]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_CP_CFG" title="GTX1:RXPLL_CP_CFG[4]">GTX1:RXPLL_CP_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[13]">GTX1:DRP1A[13]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_CP_CFG" title="GTX1:RXPLL_CP_CFG[5]">GTX1:RXPLL_CP_CFG[5]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[14]">GTX1:DRP1A[14]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_CP_CFG" title="GTX1:RXPLL_CP_CFG[6]">GTX1:RXPLL_CP_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1A" title="GTX1:DRP1A[15]">GTX1:DRP1A[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_CP_CFG" title="GTX1:RXPLL_CP_CFG[7]">GTX1:RXPLL_CP_CFG[7]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[0]">GTX1:DRP1B[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[1]">GTX1:DRP1B[1]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_DIVSEL_FB" title="GTX1:RXPLL_DIVSEL_FB[1]">GTX1:RXPLL_DIVSEL_FB[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[2]">GTX1:DRP1B[2]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_DIVSEL_FB" title="GTX1:RXPLL_DIVSEL_FB[2]">GTX1:RXPLL_DIVSEL_FB[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[3]">GTX1:DRP1B[3]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_DIVSEL_FB" title="GTX1:RXPLL_DIVSEL_FB[3]">GTX1:RXPLL_DIVSEL_FB[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[4]">GTX1:DRP1B[4]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_DIVSEL_FB" title="GTX1:RXPLL_DIVSEL_FB[4]">GTX1:RXPLL_DIVSEL_FB[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[5]">GTX1:DRP1B[5]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_DIVSEL_FB" title="GTX1:RXPLL_DIVSEL_FB[0]">GTX1:RXPLL_DIVSEL_FB[0]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[6]">GTX1:DRP1B[6]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_DIVSEL45_FB" title="GTX1:RXPLL_DIVSEL45_FB">GTX1:RXPLL_DIVSEL45_FB</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[7]">GTX1:DRP1B[7]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_STARTUP_EN" title="GTX1:RXPLL_STARTUP_EN">GTX1:RXPLL_STARTUP_EN</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[8]">GTX1:DRP1B[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_RXPOWERDOWN" title="GTX1:A_RXPOWERDOWN[0]">GTX1:A_RXPOWERDOWN[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[9]">GTX1:DRP1B[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_RXPOWERDOWN" title="GTX1:A_RXPOWERDOWN[1]">GTX1:A_RXPOWERDOWN[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[10]">GTX1:DRP1B[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[11]">GTX1:DRP1B[11]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_LKDET_CFG" title="GTX1:RXPLL_LKDET_CFG[0]">GTX1:RXPLL_LKDET_CFG[0]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[12]">GTX1:DRP1B[12]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_LKDET_CFG" title="GTX1:RXPLL_LKDET_CFG[1]">GTX1:RXPLL_LKDET_CFG[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[13]">GTX1:DRP1B[13]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_LKDET_CFG" title="GTX1:RXPLL_LKDET_CFG[2]">GTX1:RXPLL_LKDET_CFG[2]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[14]">GTX1:DRP1B[14]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_DIVSEL_OUT" title="GTX1:RXPLL_DIVSEL_OUT[0]">GTX1:RXPLL_DIVSEL_OUT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1B" title="GTX1:DRP1B[15]">GTX1:DRP1B[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_DIVSEL_OUT" title="GTX1:RXPLL_DIVSEL_OUT[1]">GTX1:RXPLL_DIVSEL_OUT[1]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[0]">GTX1:DRP1C[0]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLLREFSEL_TESTCLK" title="GTX1:RXPLLREFSEL_TESTCLK">GTX1:RXPLLREFSEL_TESTCLK</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[1]">GTX1:DRP1C[1]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_DIVSEL_REF" title="GTX1:RXPLL_DIVSEL_REF[1]">GTX1:RXPLL_DIVSEL_REF[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[2]">GTX1:DRP1C[2]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_DIVSEL_REF" title="GTX1:RXPLL_DIVSEL_REF[2]">GTX1:RXPLL_DIVSEL_REF[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[3]">GTX1:DRP1C[3]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_DIVSEL_REF" title="GTX1:RXPLL_DIVSEL_REF[3]">GTX1:RXPLL_DIVSEL_REF[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[4]">GTX1:DRP1C[4]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_DIVSEL_REF" title="GTX1:RXPLL_DIVSEL_REF[4]">GTX1:RXPLL_DIVSEL_REF[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[5]">GTX1:DRP1C[5]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLL_DIVSEL_REF" title="GTX1:RXPLL_DIVSEL_REF[0]">GTX1:RXPLL_DIVSEL_REF[0]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[6]">GTX1:DRP1C[6]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLLREFSEL_MODE" title="GTX1:RXPLLREFSEL_MODE">GTX1:RXPLLREFSEL_MODE</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[7]">GTX1:DRP1C[7]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLLREFSEL_STATIC" title="GTX1:RXPLLREFSEL_STATIC[0]">GTX1:RXPLLREFSEL_STATIC[0]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[8]">GTX1:DRP1C[8]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLLREFSEL_STATIC" title="GTX1:RXPLLREFSEL_STATIC[1]">GTX1:RXPLLREFSEL_STATIC[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[9]">GTX1:DRP1C[9]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPLLREFSEL_STATIC" title="GTX1:RXPLLREFSEL_STATIC[2]">GTX1:RXPLLREFSEL_STATIC[2]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_PLLRXRESET" title="GTX1:A_PLLRXRESET">GTX1:A_PLLRXRESET</a><br><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[10]">GTX1:DRP1C[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_RXPLLLKDETEN" title="GTX1:A_RXPLLLKDETEN">GTX1:A_RXPLLLKDETEN</a><br><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[11]">GTX1:DRP1C[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_PLLCLKRXRESET" title="GTX1:A_PLLCLKRXRESET">GTX1:A_PLLCLKRXRESET</a><br><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[12]">GTX1:DRP1C[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[13]">GTX1:DRP1C[13]</a><br><a href="#bits-xc6v-GTX-GTX1:PLL_DRP_EN" title="GTX1:PLL_DRP_EN">GTX1:PLL_DRP_EN</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_RXPLLPOWERDOWN" title="GTX1:A_RXPLLPOWERDOWN">GTX1:A_RXPLLPOWERDOWN</a><br><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[14]">GTX1:DRP1C[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1C" title="GTX1:DRP1C[15]">GTX1:DRP1C[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_OVERSAMPLE_MODE" title="GTX1:RX_OVERSAMPLE_MODE">GTX1:RX_OVERSAMPLE_MODE</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[0]">GTX1:DRP1D[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[0]">GTX1:TXPLL_COM_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[1]">GTX1:DRP1D[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[1]">GTX1:TXPLL_COM_CFG[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[2]">GTX1:DRP1D[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[2]">GTX1:TXPLL_COM_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[3]">GTX1:DRP1D[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[3]">GTX1:TXPLL_COM_CFG[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[4]">GTX1:DRP1D[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[4]">GTX1:TXPLL_COM_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[5]">GTX1:DRP1D[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[5]">GTX1:TXPLL_COM_CFG[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[6]">GTX1:DRP1D[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[6]">GTX1:TXPLL_COM_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[7]">GTX1:DRP1D[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[7]">GTX1:TXPLL_COM_CFG[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[8]">GTX1:DRP1D[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[8]">GTX1:TXPLL_COM_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[9]">GTX1:DRP1D[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[9]">GTX1:TXPLL_COM_CFG[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[10]">GTX1:DRP1D[10]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[10]">GTX1:TXPLL_COM_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[11]">GTX1:DRP1D[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[11]">GTX1:TXPLL_COM_CFG[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[12]">GTX1:DRP1D[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[12]">GTX1:TXPLL_COM_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[13]">GTX1:DRP1D[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[13]">GTX1:TXPLL_COM_CFG[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[14]">GTX1:DRP1D[14]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[14]">GTX1:TXPLL_COM_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1D" title="GTX1:DRP1D[15]">GTX1:DRP1D[15]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[15]">GTX1:TXPLL_COM_CFG[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[0]">GTX1:DRP1E[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[16]">GTX1:TXPLL_COM_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[1]">GTX1:DRP1E[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[17]">GTX1:TXPLL_COM_CFG[17]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[2]">GTX1:DRP1E[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[18]">GTX1:TXPLL_COM_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[3]">GTX1:DRP1E[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[19]">GTX1:TXPLL_COM_CFG[19]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[4]">GTX1:DRP1E[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[20]">GTX1:TXPLL_COM_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[5]">GTX1:DRP1E[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[21]">GTX1:TXPLL_COM_CFG[21]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[6]">GTX1:DRP1E[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[22]">GTX1:TXPLL_COM_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[7]">GTX1:DRP1E[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_COM_CFG" title="GTX1:TXPLL_COM_CFG[23]">GTX1:TXPLL_COM_CFG[23]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[8]">GTX1:DRP1E[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_CP_CFG" title="GTX1:TXPLL_CP_CFG[0]">GTX1:TXPLL_CP_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[9]">GTX1:DRP1E[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_CP_CFG" title="GTX1:TXPLL_CP_CFG[1]">GTX1:TXPLL_CP_CFG[1]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[10]">GTX1:DRP1E[10]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_CP_CFG" title="GTX1:TXPLL_CP_CFG[2]">GTX1:TXPLL_CP_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[11]">GTX1:DRP1E[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_CP_CFG" title="GTX1:TXPLL_CP_CFG[3]">GTX1:TXPLL_CP_CFG[3]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[12]">GTX1:DRP1E[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_CP_CFG" title="GTX1:TXPLL_CP_CFG[4]">GTX1:TXPLL_CP_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[13]">GTX1:DRP1E[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_CP_CFG" title="GTX1:TXPLL_CP_CFG[5]">GTX1:TXPLL_CP_CFG[5]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[14]">GTX1:DRP1E[14]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_CP_CFG" title="GTX1:TXPLL_CP_CFG[6]">GTX1:TXPLL_CP_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1E" title="GTX1:DRP1E[15]">GTX1:DRP1E[15]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_CP_CFG" title="GTX1:TXPLL_CP_CFG[7]">GTX1:TXPLL_CP_CFG[7]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[0]">GTX1:DRP1F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[1]">GTX1:DRP1F[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_DIVSEL_FB" title="GTX1:TXPLL_DIVSEL_FB[1]">GTX1:TXPLL_DIVSEL_FB[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[2]">GTX1:DRP1F[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_DIVSEL_FB" title="GTX1:TXPLL_DIVSEL_FB[2]">GTX1:TXPLL_DIVSEL_FB[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[3]">GTX1:DRP1F[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_DIVSEL_FB" title="GTX1:TXPLL_DIVSEL_FB[3]">GTX1:TXPLL_DIVSEL_FB[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[4]">GTX1:DRP1F[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_DIVSEL_FB" title="GTX1:TXPLL_DIVSEL_FB[4]">GTX1:TXPLL_DIVSEL_FB[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[5]">GTX1:DRP1F[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_DIVSEL_FB" title="GTX1:TXPLL_DIVSEL_FB[0]">GTX1:TXPLL_DIVSEL_FB[0]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[6]">GTX1:DRP1F[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_DIVSEL45_FB" title="GTX1:TXPLL_DIVSEL45_FB">GTX1:TXPLL_DIVSEL45_FB</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[7]">GTX1:DRP1F[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_STARTUP_EN" title="GTX1:TXPLL_STARTUP_EN">GTX1:TXPLL_STARTUP_EN</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[8]">GTX1:DRP1F[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_CLK_SOURCE" title="GTX1:TX_CLK_SOURCE">GTX1:TX_CLK_SOURCE</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPOWERDOWN" title="GTX1:A_TXPOWERDOWN[0]">GTX1:A_TXPOWERDOWN[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[9]">GTX1:DRP1F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPOWERDOWN" title="GTX1:A_TXPOWERDOWN[1]">GTX1:A_TXPOWERDOWN[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[10]">GTX1:DRP1F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[11]">GTX1:DRP1F[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_LKDET_CFG" title="GTX1:TXPLL_LKDET_CFG[0]">GTX1:TXPLL_LKDET_CFG[0]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[12]">GTX1:DRP1F[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_LKDET_CFG" title="GTX1:TXPLL_LKDET_CFG[1]">GTX1:TXPLL_LKDET_CFG[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[13]">GTX1:DRP1F[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_LKDET_CFG" title="GTX1:TXPLL_LKDET_CFG[2]">GTX1:TXPLL_LKDET_CFG[2]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[14]">GTX1:DRP1F[14]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_DIVSEL_OUT" title="GTX1:TXPLL_DIVSEL_OUT[0]">GTX1:TXPLL_DIVSEL_OUT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP1F" title="GTX1:DRP1F[15]">GTX1:DRP1F[15]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_DIVSEL_OUT" title="GTX1:TXPLL_DIVSEL_OUT[1]">GTX1:TXPLL_DIVSEL_OUT[1]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 14</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[0]">GTX1:DRP20[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLLREFSEL_TESTCLK" title="GTX1:TXPLLREFSEL_TESTCLK">GTX1:TXPLLREFSEL_TESTCLK</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[1]">GTX1:DRP20[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_DIVSEL_REF" title="GTX1:TXPLL_DIVSEL_REF[1]">GTX1:TXPLL_DIVSEL_REF[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[2]">GTX1:DRP20[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_DIVSEL_REF" title="GTX1:TXPLL_DIVSEL_REF[2]">GTX1:TXPLL_DIVSEL_REF[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[3]">GTX1:DRP20[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_DIVSEL_REF" title="GTX1:TXPLL_DIVSEL_REF[3]">GTX1:TXPLL_DIVSEL_REF[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[4]">GTX1:DRP20[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_DIVSEL_REF" title="GTX1:TXPLL_DIVSEL_REF[4]">GTX1:TXPLL_DIVSEL_REF[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[5]">GTX1:DRP20[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_DIVSEL_REF" title="GTX1:TXPLL_DIVSEL_REF[0]">GTX1:TXPLL_DIVSEL_REF[0]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[6]">GTX1:DRP20[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLLREFSEL_MODE" title="GTX1:TXPLLREFSEL_MODE">GTX1:TXPLLREFSEL_MODE</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[7]">GTX1:DRP20[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLLREFSEL_STATIC" title="GTX1:TXPLLREFSEL_STATIC[0]">GTX1:TXPLLREFSEL_STATIC[0]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[8]">GTX1:DRP20[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLLREFSEL_STATIC" title="GTX1:TXPLLREFSEL_STATIC[1]">GTX1:TXPLLREFSEL_STATIC[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[9]">GTX1:DRP20[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLLREFSEL_STATIC" title="GTX1:TXPLLREFSEL_STATIC[2]">GTX1:TXPLLREFSEL_STATIC[2]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_PLLTXRESET" title="GTX1:A_PLLTXRESET">GTX1:A_PLLTXRESET</a><br><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[10]">GTX1:DRP20[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPLLLKDETEN" title="GTX1:A_TXPLLLKDETEN">GTX1:A_TXPLLLKDETEN</a><br><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[11]">GTX1:DRP20[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_PLLCLKTXRESET" title="GTX1:A_PLLCLKTXRESET">GTX1:A_PLLCLKTXRESET</a><br><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[12]">GTX1:DRP20[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[13]">GTX1:DRP20[13]</a><br><a href="#bits-xc6v-GTX-GTX1:PDELIDLE_DRP_EN" title="GTX1:PDELIDLE_DRP_EN">GTX1:PDELIDLE_DRP_EN</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPLLPOWERDOWN" title="GTX1:A_TXPLLPOWERDOWN">GTX1:A_TXPLLPOWERDOWN</a><br><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[14]">GTX1:DRP20[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP20" title="GTX1:DRP20[15]">GTX1:DRP20[15]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_OVERSAMPLE_MODE" title="GTX1:TX_OVERSAMPLE_MODE">GTX1:TX_OVERSAMPLE_MODE</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[0]">GTX1:DRP21[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DETECT_RX_CFG" title="GTX1:TX_DETECT_RX_CFG[0]">GTX1:TX_DETECT_RX_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[1]">GTX1:DRP21[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DETECT_RX_CFG" title="GTX1:TX_DETECT_RX_CFG[1]">GTX1:TX_DETECT_RX_CFG[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[2]">GTX1:DRP21[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DETECT_RX_CFG" title="GTX1:TX_DETECT_RX_CFG[2]">GTX1:TX_DETECT_RX_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[3]">GTX1:DRP21[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DETECT_RX_CFG" title="GTX1:TX_DETECT_RX_CFG[3]">GTX1:TX_DETECT_RX_CFG[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[4]">GTX1:DRP21[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DETECT_RX_CFG" title="GTX1:TX_DETECT_RX_CFG[4]">GTX1:TX_DETECT_RX_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[5]">GTX1:DRP21[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DETECT_RX_CFG" title="GTX1:TX_DETECT_RX_CFG[5]">GTX1:TX_DETECT_RX_CFG[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[6]">GTX1:DRP21[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DETECT_RX_CFG" title="GTX1:TX_DETECT_RX_CFG[6]">GTX1:TX_DETECT_RX_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[7]">GTX1:DRP21[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DETECT_RX_CFG" title="GTX1:TX_DETECT_RX_CFG[7]">GTX1:TX_DETECT_RX_CFG[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[8]">GTX1:DRP21[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DETECT_RX_CFG" title="GTX1:TX_DETECT_RX_CFG[8]">GTX1:TX_DETECT_RX_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[9]">GTX1:DRP21[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DETECT_RX_CFG" title="GTX1:TX_DETECT_RX_CFG[9]">GTX1:TX_DETECT_RX_CFG[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[10]">GTX1:DRP21[10]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DETECT_RX_CFG" title="GTX1:TX_DETECT_RX_CFG[10]">GTX1:TX_DETECT_RX_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[11]">GTX1:DRP21[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DETECT_RX_CFG" title="GTX1:TX_DETECT_RX_CFG[11]">GTX1:TX_DETECT_RX_CFG[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[12]">GTX1:DRP21[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DETECT_RX_CFG" title="GTX1:TX_DETECT_RX_CFG[12]">GTX1:TX_DETECT_RX_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[13]">GTX1:DRP21[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DETECT_RX_CFG" title="GTX1:TX_DETECT_RX_CFG[13]">GTX1:TX_DETECT_RX_CFG[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXELECIDLE" title="GTX1:A_TXELECIDLE">GTX1:A_TXELECIDLE</a><br><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[14]">GTX1:DRP21[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP21" title="GTX1:DRP21[15]">GTX1:DRP21[15]</a><br><a href="#bits-xc6v-GTX-GTX1:PCI_EXPRESS_MODE" title="GTX1:PCI_EXPRESS_MODE">GTX1:PCI_EXPRESS_MODE</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[0]">GTX1:DRP22[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[1]">GTX1:DRP22[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[2]">GTX1:DRP22[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[3]">GTX1:DRP22[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[4]">GTX1:DRP22[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[5]">GTX1:DRP22[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[6]">GTX1:DRP22[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[7]">GTX1:DRP22[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[8]">GTX1:DRP22[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[9]">GTX1:DRP22[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[10]">GTX1:DRP22[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[11]">GTX1:DRP22[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[12]">GTX1:DRP22[12]</a><br><a href="#bits-xc6v-GTX-HCLK_GTX:MUX.PERFCLK" title="HCLK_GTX:MUX.PERFCLK[1]">HCLK_GTX:MUX.PERFCLK[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[13]">GTX1:DRP22[13]</a><br><a href="#bits-xc6v-GTX-HCLK_GTX:MUX.PERFCLK" title="HCLK_GTX:MUX.PERFCLK[2]">HCLK_GTX:MUX.PERFCLK[2]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[14]">GTX1:DRP22[14]</a><br><a href="#bits-xc6v-GTX-HCLK_GTX:MUX.PERFCLK" title="HCLK_GTX:MUX.PERFCLK[0]">HCLK_GTX:MUX.PERFCLK[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP22" title="GTX1:DRP22[15]">GTX1:DRP22[15]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CAS_CLK_EN" title="GTX1:PMA_CAS_CLK_EN">GTX1:PMA_CAS_CLK_EN</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[0]">GTX1:DRP23[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_TO_P2" title="GTX1:TRANS_TIME_TO_P2[0]">GTX1:TRANS_TIME_TO_P2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[1]">GTX1:DRP23[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_TO_P2" title="GTX1:TRANS_TIME_TO_P2[1]">GTX1:TRANS_TIME_TO_P2[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[2]">GTX1:DRP23[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_TO_P2" title="GTX1:TRANS_TIME_TO_P2[2]">GTX1:TRANS_TIME_TO_P2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[3]">GTX1:DRP23[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_TO_P2" title="GTX1:TRANS_TIME_TO_P2[3]">GTX1:TRANS_TIME_TO_P2[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[4]">GTX1:DRP23[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_TO_P2" title="GTX1:TRANS_TIME_TO_P2[4]">GTX1:TRANS_TIME_TO_P2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[5]">GTX1:DRP23[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_TO_P2" title="GTX1:TRANS_TIME_TO_P2[5]">GTX1:TRANS_TIME_TO_P2[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[6]">GTX1:DRP23[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_TO_P2" title="GTX1:TRANS_TIME_TO_P2[6]">GTX1:TRANS_TIME_TO_P2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[7]">GTX1:DRP23[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_TO_P2" title="GTX1:TRANS_TIME_TO_P2[7]">GTX1:TRANS_TIME_TO_P2[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[8]">GTX1:DRP23[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_TO_P2" title="GTX1:TRANS_TIME_TO_P2[8]">GTX1:TRANS_TIME_TO_P2[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[9]">GTX1:DRP23[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_TO_P2" title="GTX1:TRANS_TIME_TO_P2[9]">GTX1:TRANS_TIME_TO_P2[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[10]">GTX1:DRP23[10]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_CLK25_DIVIDER" title="GTX1:TX_CLK25_DIVIDER[0]">GTX1:TX_CLK25_DIVIDER[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[11]">GTX1:DRP23[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_CLK25_DIVIDER" title="GTX1:TX_CLK25_DIVIDER[1]">GTX1:TX_CLK25_DIVIDER[1]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[12]">GTX1:DRP23[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_CLK25_DIVIDER" title="GTX1:TX_CLK25_DIVIDER[2]">GTX1:TX_CLK25_DIVIDER[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[13]">GTX1:DRP23[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_CLK25_DIVIDER" title="GTX1:TX_CLK25_DIVIDER[3]">GTX1:TX_CLK25_DIVIDER[3]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[14]">GTX1:DRP23[14]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_CLK25_DIVIDER" title="GTX1:TX_CLK25_DIVIDER[4]">GTX1:TX_CLK25_DIVIDER[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP23" title="GTX1:DRP23[15]">GTX1:DRP23[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[0]">GTX1:DRP24[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_FROM_P2" title="GTX1:TRANS_TIME_FROM_P2[0]">GTX1:TRANS_TIME_FROM_P2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[1]">GTX1:DRP24[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_FROM_P2" title="GTX1:TRANS_TIME_FROM_P2[1]">GTX1:TRANS_TIME_FROM_P2[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[2]">GTX1:DRP24[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_FROM_P2" title="GTX1:TRANS_TIME_FROM_P2[2]">GTX1:TRANS_TIME_FROM_P2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[3]">GTX1:DRP24[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_FROM_P2" title="GTX1:TRANS_TIME_FROM_P2[3]">GTX1:TRANS_TIME_FROM_P2[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[4]">GTX1:DRP24[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_FROM_P2" title="GTX1:TRANS_TIME_FROM_P2[4]">GTX1:TRANS_TIME_FROM_P2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[5]">GTX1:DRP24[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_FROM_P2" title="GTX1:TRANS_TIME_FROM_P2[5]">GTX1:TRANS_TIME_FROM_P2[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[6]">GTX1:DRP24[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_FROM_P2" title="GTX1:TRANS_TIME_FROM_P2[6]">GTX1:TRANS_TIME_FROM_P2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[7]">GTX1:DRP24[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_FROM_P2" title="GTX1:TRANS_TIME_FROM_P2[7]">GTX1:TRANS_TIME_FROM_P2[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[8]">GTX1:DRP24[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_FROM_P2" title="GTX1:TRANS_TIME_FROM_P2[8]">GTX1:TRANS_TIME_FROM_P2[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[9]">GTX1:DRP24[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_FROM_P2" title="GTX1:TRANS_TIME_FROM_P2[9]">GTX1:TRANS_TIME_FROM_P2[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[10]">GTX1:DRP24[10]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_FROM_P2" title="GTX1:TRANS_TIME_FROM_P2[10]">GTX1:TRANS_TIME_FROM_P2[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[11]">GTX1:DRP24[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_FROM_P2" title="GTX1:TRANS_TIME_FROM_P2[11]">GTX1:TRANS_TIME_FROM_P2[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:COM_BURST_VAL" title="GTX1:COM_BURST_VAL[0]">GTX1:COM_BURST_VAL[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[12]">GTX1:DRP24[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:COM_BURST_VAL" title="GTX1:COM_BURST_VAL[1]">GTX1:COM_BURST_VAL[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[13]">GTX1:DRP24[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:COM_BURST_VAL" title="GTX1:COM_BURST_VAL[2]">GTX1:COM_BURST_VAL[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[14]">GTX1:DRP24[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:COM_BURST_VAL" title="GTX1:COM_BURST_VAL[3]">GTX1:COM_BURST_VAL[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP24" title="GTX1:DRP24[15]">GTX1:DRP24[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[0]">GTX1:DRP25[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_NON_P2" title="GTX1:TRANS_TIME_NON_P2[0]">GTX1:TRANS_TIME_NON_P2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[1]">GTX1:DRP25[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_NON_P2" title="GTX1:TRANS_TIME_NON_P2[1]">GTX1:TRANS_TIME_NON_P2[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[2]">GTX1:DRP25[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_NON_P2" title="GTX1:TRANS_TIME_NON_P2[2]">GTX1:TRANS_TIME_NON_P2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[3]">GTX1:DRP25[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_NON_P2" title="GTX1:TRANS_TIME_NON_P2[3]">GTX1:TRANS_TIME_NON_P2[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[4]">GTX1:DRP25[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_NON_P2" title="GTX1:TRANS_TIME_NON_P2[4]">GTX1:TRANS_TIME_NON_P2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[5]">GTX1:DRP25[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_NON_P2" title="GTX1:TRANS_TIME_NON_P2[5]">GTX1:TRANS_TIME_NON_P2[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[6]">GTX1:DRP25[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_NON_P2" title="GTX1:TRANS_TIME_NON_P2[6]">GTX1:TRANS_TIME_NON_P2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[7]">GTX1:DRP25[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_NON_P2" title="GTX1:TRANS_TIME_NON_P2[7]">GTX1:TRANS_TIME_NON_P2[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:CM_TRIM" title="GTX1:CM_TRIM[0]">GTX1:CM_TRIM[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[8]">GTX1:DRP25[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:CM_TRIM" title="GTX1:CM_TRIM[1]">GTX1:CM_TRIM[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[9]">GTX1:DRP25[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_RXPOLARITY" title="GTX1:A_RXPOLARITY">GTX1:A_RXPOLARITY</a><br><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[10]">GTX1:DRP25[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPOLARITY" title="GTX1:A_TXPOLARITY">GTX1:A_TXPOLARITY</a><br><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[11]">GTX1:DRP25[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[12]">GTX1:DRP25[12]</a><br><a href="#bits-xc6v-GTX-GTX1:POLARITY_DRP_EN" title="GTX1:POLARITY_DRP_EN">GTX1:POLARITY_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_RXPMASETPHASE" title="GTX1:A_RXPMASETPHASE">GTX1:A_RXPMASETPHASE</a><br><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[13]">GTX1:DRP25[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_RXENPMAPHASEALIGN" title="GTX1:A_RXENPMAPHASEALIGN">GTX1:A_RXENPMAPHASEALIGN</a><br><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[14]">GTX1:DRP25[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP25" title="GTX1:DRP25[15]">GTX1:DRP25[15]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_PMADATA_OPT" title="GTX1:TX_PMADATA_OPT">GTX1:TX_PMADATA_OPT</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[0]">GTX1:DRP26[0]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_WAKE" title="GTX1:SATA_MAX_WAKE[0]">GTX1:SATA_MAX_WAKE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[1]">GTX1:DRP26[1]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_WAKE" title="GTX1:SATA_MAX_WAKE[1]">GTX1:SATA_MAX_WAKE[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[2]">GTX1:DRP26[2]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_WAKE" title="GTX1:SATA_MAX_WAKE[2]">GTX1:SATA_MAX_WAKE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[3]">GTX1:DRP26[3]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_WAKE" title="GTX1:SATA_MAX_WAKE[3]">GTX1:SATA_MAX_WAKE[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[4]">GTX1:DRP26[4]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_WAKE" title="GTX1:SATA_MAX_WAKE[4]">GTX1:SATA_MAX_WAKE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[5]">GTX1:DRP26[5]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_WAKE" title="GTX1:SATA_MAX_WAKE[5]">GTX1:SATA_MAX_WAKE[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[6]">GTX1:DRP26[6]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_WAKE" title="GTX1:SATA_MIN_WAKE[0]">GTX1:SATA_MIN_WAKE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[7]">GTX1:DRP26[7]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_WAKE" title="GTX1:SATA_MIN_WAKE[1]">GTX1:SATA_MIN_WAKE[1]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[8]">GTX1:DRP26[8]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_WAKE" title="GTX1:SATA_MIN_WAKE[2]">GTX1:SATA_MIN_WAKE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[9]">GTX1:DRP26[9]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_WAKE" title="GTX1:SATA_MIN_WAKE[3]">GTX1:SATA_MIN_WAKE[3]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[10]">GTX1:DRP26[10]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_WAKE" title="GTX1:SATA_MIN_WAKE[4]">GTX1:SATA_MIN_WAKE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[11]">GTX1:DRP26[11]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_WAKE" title="GTX1:SATA_MIN_WAKE[5]">GTX1:SATA_MIN_WAKE[5]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[12]">GTX1:DRP26[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_SATA" title="GTX1:TXPLL_SATA[0]">GTX1:TXPLL_SATA[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[13]">GTX1:DRP26[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TXPLL_SATA" title="GTX1:TXPLL_SATA[1]">GTX1:TXPLL_SATA[1]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:BGTEST_CFG" title="GTX1:BGTEST_CFG[0]">GTX1:BGTEST_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[14]">GTX1:DRP26[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:BGTEST_CFG" title="GTX1:BGTEST_CFG[1]">GTX1:BGTEST_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP26" title="GTX1:DRP26[15]">GTX1:DRP26[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[0]">GTX1:DRP27[0]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_INIT" title="GTX1:SATA_MAX_INIT[0]">GTX1:SATA_MAX_INIT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[1]">GTX1:DRP27[1]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_INIT" title="GTX1:SATA_MAX_INIT[1]">GTX1:SATA_MAX_INIT[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[2]">GTX1:DRP27[2]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_INIT" title="GTX1:SATA_MAX_INIT[2]">GTX1:SATA_MAX_INIT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[3]">GTX1:DRP27[3]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_INIT" title="GTX1:SATA_MAX_INIT[3]">GTX1:SATA_MAX_INIT[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[4]">GTX1:DRP27[4]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_INIT" title="GTX1:SATA_MAX_INIT[4]">GTX1:SATA_MAX_INIT[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[5]">GTX1:DRP27[5]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_INIT" title="GTX1:SATA_MAX_INIT[5]">GTX1:SATA_MAX_INIT[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[6]">GTX1:DRP27[6]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_INIT" title="GTX1:SATA_MIN_INIT[0]">GTX1:SATA_MIN_INIT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[7]">GTX1:DRP27[7]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_INIT" title="GTX1:SATA_MIN_INIT[1]">GTX1:SATA_MIN_INIT[1]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[8]">GTX1:DRP27[8]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_INIT" title="GTX1:SATA_MIN_INIT[2]">GTX1:SATA_MIN_INIT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[9]">GTX1:DRP27[9]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_INIT" title="GTX1:SATA_MIN_INIT[3]">GTX1:SATA_MIN_INIT[3]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[10]">GTX1:DRP27[10]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_INIT" title="GTX1:SATA_MIN_INIT[4]">GTX1:SATA_MIN_INIT[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[11]">GTX1:DRP27[11]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_INIT" title="GTX1:SATA_MIN_INIT[5]">GTX1:SATA_MIN_INIT[5]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[12]">GTX1:DRP27[12]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_IDLE_VAL" title="GTX1:SATA_IDLE_VAL[0]">GTX1:SATA_IDLE_VAL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[13]">GTX1:DRP27[13]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_IDLE_VAL" title="GTX1:SATA_IDLE_VAL[1]">GTX1:SATA_IDLE_VAL[1]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[14]">GTX1:DRP27[14]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_IDLE_VAL" title="GTX1:SATA_IDLE_VAL[2]">GTX1:SATA_IDLE_VAL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP27" title="GTX1:DRP27[15]">GTX1:DRP27[15]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_EN_RATE_RESET_BUF" title="GTX1:TX_EN_RATE_RESET_BUF">GTX1:TX_EN_RATE_RESET_BUF</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 15</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[0]">GTX1:DRP28[0]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_BURST" title="GTX1:SATA_MAX_BURST[0]">GTX1:SATA_MAX_BURST[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[1]">GTX1:DRP28[1]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_BURST" title="GTX1:SATA_MAX_BURST[1]">GTX1:SATA_MAX_BURST[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[2]">GTX1:DRP28[2]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_BURST" title="GTX1:SATA_MAX_BURST[2]">GTX1:SATA_MAX_BURST[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[3]">GTX1:DRP28[3]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_BURST" title="GTX1:SATA_MAX_BURST[3]">GTX1:SATA_MAX_BURST[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[4]">GTX1:DRP28[4]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_BURST" title="GTX1:SATA_MAX_BURST[4]">GTX1:SATA_MAX_BURST[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[5]">GTX1:DRP28[5]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MAX_BURST" title="GTX1:SATA_MAX_BURST[5]">GTX1:SATA_MAX_BURST[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[6]">GTX1:DRP28[6]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_BURST" title="GTX1:SATA_MIN_BURST[0]">GTX1:SATA_MIN_BURST[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[7]">GTX1:DRP28[7]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_BURST" title="GTX1:SATA_MIN_BURST[1]">GTX1:SATA_MIN_BURST[1]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[8]">GTX1:DRP28[8]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_BURST" title="GTX1:SATA_MIN_BURST[2]">GTX1:SATA_MIN_BURST[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[9]">GTX1:DRP28[9]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_BURST" title="GTX1:SATA_MIN_BURST[3]">GTX1:SATA_MIN_BURST[3]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[10]">GTX1:DRP28[10]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_BURST" title="GTX1:SATA_MIN_BURST[4]">GTX1:SATA_MIN_BURST[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[11]">GTX1:DRP28[11]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_MIN_BURST" title="GTX1:SATA_MIN_BURST[5]">GTX1:SATA_MIN_BURST[5]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[12]">GTX1:DRP28[12]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_BURST_VAL" title="GTX1:SATA_BURST_VAL[0]">GTX1:SATA_BURST_VAL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[13]">GTX1:DRP28[13]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_BURST_VAL" title="GTX1:SATA_BURST_VAL[1]">GTX1:SATA_BURST_VAL[1]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[14]">GTX1:DRP28[14]</a><br><a href="#bits-xc6v-GTX-GTX1:SATA_BURST_VAL" title="GTX1:SATA_BURST_VAL[2]">GTX1:SATA_BURST_VAL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP28" title="GTX1:DRP28[15]">GTX1:DRP28[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[0]">GTX1:DRP29[0]</a><br><a href="#bits-xc6v-GTX-GTX1:SAS_MAX_COMSAS" title="GTX1:SAS_MAX_COMSAS[0]">GTX1:SAS_MAX_COMSAS[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[1]">GTX1:DRP29[1]</a><br><a href="#bits-xc6v-GTX-GTX1:SAS_MAX_COMSAS" title="GTX1:SAS_MAX_COMSAS[1]">GTX1:SAS_MAX_COMSAS[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[2]">GTX1:DRP29[2]</a><br><a href="#bits-xc6v-GTX-GTX1:SAS_MAX_COMSAS" title="GTX1:SAS_MAX_COMSAS[2]">GTX1:SAS_MAX_COMSAS[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[3]">GTX1:DRP29[3]</a><br><a href="#bits-xc6v-GTX-GTX1:SAS_MAX_COMSAS" title="GTX1:SAS_MAX_COMSAS[3]">GTX1:SAS_MAX_COMSAS[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[4]">GTX1:DRP29[4]</a><br><a href="#bits-xc6v-GTX-GTX1:SAS_MAX_COMSAS" title="GTX1:SAS_MAX_COMSAS[4]">GTX1:SAS_MAX_COMSAS[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[5]">GTX1:DRP29[5]</a><br><a href="#bits-xc6v-GTX-GTX1:SAS_MAX_COMSAS" title="GTX1:SAS_MAX_COMSAS[5]">GTX1:SAS_MAX_COMSAS[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[6]">GTX1:DRP29[6]</a><br><a href="#bits-xc6v-GTX-GTX1:SAS_MIN_COMSAS" title="GTX1:SAS_MIN_COMSAS[0]">GTX1:SAS_MIN_COMSAS[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[7]">GTX1:DRP29[7]</a><br><a href="#bits-xc6v-GTX-GTX1:SAS_MIN_COMSAS" title="GTX1:SAS_MIN_COMSAS[1]">GTX1:SAS_MIN_COMSAS[1]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[8]">GTX1:DRP29[8]</a><br><a href="#bits-xc6v-GTX-GTX1:SAS_MIN_COMSAS" title="GTX1:SAS_MIN_COMSAS[2]">GTX1:SAS_MIN_COMSAS[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[9]">GTX1:DRP29[9]</a><br><a href="#bits-xc6v-GTX-GTX1:SAS_MIN_COMSAS" title="GTX1:SAS_MIN_COMSAS[3]">GTX1:SAS_MIN_COMSAS[3]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[10]">GTX1:DRP29[10]</a><br><a href="#bits-xc6v-GTX-GTX1:SAS_MIN_COMSAS" title="GTX1:SAS_MIN_COMSAS[4]">GTX1:SAS_MIN_COMSAS[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[11]">GTX1:DRP29[11]</a><br><a href="#bits-xc6v-GTX-GTX1:SAS_MIN_COMSAS" title="GTX1:SAS_MIN_COMSAS[5]">GTX1:SAS_MIN_COMSAS[5]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPMASETPHASE" title="GTX1:A_TXPMASETPHASE">GTX1:A_TXPMASETPHASE</a><br><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[12]">GTX1:DRP29[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXENPMAPHASEALIGN" title="GTX1:A_TXENPMAPHASEALIGN">GTX1:A_TXENPMAPHASEALIGN</a><br><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[13]">GTX1:DRP29[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_RXENSAMPLEALIGN" title="GTX1:A_RXENSAMPLEALIGN">GTX1:A_RXENSAMPLEALIGN</a><br><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[14]">GTX1:DRP29[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP29" title="GTX1:DRP29[15]">GTX1:DRP29[15]</a><br><a href="#bits-xc6v-GTX-GTX1:PHASEALIGN_DRP_EN" title="GTX1:PHASEALIGN_DRP_EN">GTX1:PHASEALIGN_DRP_EN</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[0]">GTX1:DRP2A[0]</a><br><a href="#bits-xc6v-GTX-GTX1:LOOPBACK_DRP_EN" title="GTX1:LOOPBACK_DRP_EN">GTX1:LOOPBACK_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_LOOPBACK" title="GTX1:A_LOOPBACK[0]">GTX1:A_LOOPBACK[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[1]">GTX1:DRP2A[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_LOOPBACK" title="GTX1:A_LOOPBACK[1]">GTX1:A_LOOPBACK[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[2]">GTX1:DRP2A[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_LOOPBACK" title="GTX1:A_LOOPBACK[2]">GTX1:A_LOOPBACK[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[3]">GTX1:DRP2A[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[4]">GTX1:DRP2A[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_RXENPRBSTST" title="GTX1:A_RXENPRBSTST[0]">GTX1:A_RXENPRBSTST[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[5]">GTX1:DRP2A[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_RXENPRBSTST" title="GTX1:A_RXENPRBSTST[1]">GTX1:A_RXENPRBSTST[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[6]">GTX1:DRP2A[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_RXENPRBSTST" title="GTX1:A_RXENPRBSTST[2]">GTX1:A_RXENPRBSTST[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[7]">GTX1:DRP2A[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[8]">GTX1:DRP2A[8]</a><br><a href="#bits-xc6v-GTX-GTX1:RXPRBSERR_LOOPBACK" title="GTX1:RXPRBSERR_LOOPBACK">GTX1:RXPRBSERR_LOOPBACK</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[9]">GTX1:DRP2A[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPRBSFORCEERR" title="GTX1:A_TXPRBSFORCEERR">GTX1:A_TXPRBSFORCEERR</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[10]">GTX1:DRP2A[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXENPRBSTST" title="GTX1:A_TXENPRBSTST[0]">GTX1:A_TXENPRBSTST[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[11]">GTX1:DRP2A[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXENPRBSTST" title="GTX1:A_TXENPRBSTST[1]">GTX1:A_TXENPRBSTST[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[12]">GTX1:DRP2A[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXENPRBSTST" title="GTX1:A_TXENPRBSTST[2]">GTX1:A_TXENPRBSTST[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[13]">GTX1:DRP2A[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_PRBSCNTRESET" title="GTX1:A_PRBSCNTRESET">GTX1:A_PRBSCNTRESET</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[14]">GTX1:DRP2A[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2A" title="GTX1:DRP2A[15]">GTX1:DRP2A[15]</a><br><a href="#bits-xc6v-GTX-GTX1:PRBS_DRP_EN" title="GTX1:PRBS_DRP_EN">GTX1:PRBS_DRP_EN</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP1" title="GTX1:A_DFETAP1[0]">GTX1:A_DFETAP1[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[0]">GTX1:DRP2B[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP1" title="GTX1:A_DFETAP1[1]">GTX1:A_DFETAP1[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[1]">GTX1:DRP2B[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP1" title="GTX1:A_DFETAP1[2]">GTX1:A_DFETAP1[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[2]">GTX1:DRP2B[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP1" title="GTX1:A_DFETAP1[3]">GTX1:A_DFETAP1[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[3]">GTX1:DRP2B[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP1" title="GTX1:A_DFETAP1[4]">GTX1:A_DFETAP1[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[4]">GTX1:DRP2B[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP3" title="GTX1:A_DFETAP3[0]">GTX1:A_DFETAP3[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[5]">GTX1:DRP2B[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP3" title="GTX1:A_DFETAP3[1]">GTX1:A_DFETAP3[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[6]">GTX1:DRP2B[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP3" title="GTX1:A_DFETAP3[2]">GTX1:A_DFETAP3[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[7]">GTX1:DRP2B[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP3" title="GTX1:A_DFETAP3[3]">GTX1:A_DFETAP3[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[8]">GTX1:DRP2B[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[9]">GTX1:DRP2B[9]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EN_IDLE_HOLD_CDR" title="GTX1:RX_EN_IDLE_HOLD_CDR">GTX1:RX_EN_IDLE_HOLD_CDR</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[10]">GTX1:DRP2B[10]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EN_IDLE_RESET_FR" title="GTX1:RX_EN_IDLE_RESET_FR">GTX1:RX_EN_IDLE_RESET_FR</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[11]">GTX1:DRP2B[11]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EN_IDLE_HOLD_DFE" title="GTX1:RX_EN_IDLE_HOLD_DFE">GTX1:RX_EN_IDLE_HOLD_DFE</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[12]">GTX1:DRP2B[12]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX0:CLKRCV_TRST" title="IBUFDS_GTX0:CLKRCV_TRST">IBUFDS_GTX0:CLKRCV_TRST</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[13]">GTX1:DRP2B[13]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX1:CLKRCV_TRST" title="IBUFDS_GTX1:CLKRCV_TRST">IBUFDS_GTX1:CLKRCV_TRST</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_DFEDLYOVRD" title="GTX1:A_DFEDLYOVRD">GTX1:A_DFEDLYOVRD</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[14]">GTX1:DRP2B[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAPOVRD" title="GTX1:A_DFETAPOVRD">GTX1:A_DFETAPOVRD</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2B" title="GTX1:DRP2B[15]">GTX1:DRP2B[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP2" title="GTX1:A_DFETAP2[0]">GTX1:A_DFETAP2[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[0]">GTX1:DRP2C[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP2" title="GTX1:A_DFETAP2[1]">GTX1:A_DFETAP2[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[1]">GTX1:DRP2C[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP2" title="GTX1:A_DFETAP2[2]">GTX1:A_DFETAP2[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[2]">GTX1:DRP2C[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP2" title="GTX1:A_DFETAP2[3]">GTX1:A_DFETAP2[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[3]">GTX1:DRP2C[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP2" title="GTX1:A_DFETAP2[4]">GTX1:A_DFETAP2[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[4]">GTX1:DRP2C[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP4" title="GTX1:A_DFETAP4[0]">GTX1:A_DFETAP4[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[5]">GTX1:DRP2C[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP4" title="GTX1:A_DFETAP4[1]">GTX1:A_DFETAP4[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[6]">GTX1:DRP2C[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP4" title="GTX1:A_DFETAP4[2]">GTX1:A_DFETAP4[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[7]">GTX1:DRP2C[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_DFETAP4" title="GTX1:A_DFETAP4[3]">GTX1:A_DFETAP4[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[8]">GTX1:DRP2C[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_DFECLKDLYADJ" title="GTX1:A_DFECLKDLYADJ[0]">GTX1:A_DFECLKDLYADJ[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[9]">GTX1:DRP2C[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_DFECLKDLYADJ" title="GTX1:A_DFECLKDLYADJ[1]">GTX1:A_DFECLKDLYADJ[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[10]">GTX1:DRP2C[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_DFECLKDLYADJ" title="GTX1:A_DFECLKDLYADJ[2]">GTX1:A_DFECLKDLYADJ[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[11]">GTX1:DRP2C[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_DFECLKDLYADJ" title="GTX1:A_DFECLKDLYADJ[3]">GTX1:A_DFECLKDLYADJ[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[12]">GTX1:DRP2C[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_DFECLKDLYADJ" title="GTX1:A_DFECLKDLYADJ[4]">GTX1:A_DFECLKDLYADJ[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[13]">GTX1:DRP2C[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_DFECLKDLYADJ" title="GTX1:A_DFECLKDLYADJ[5]">GTX1:A_DFECLKDLYADJ[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[14]">GTX1:DRP2C[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DFE_DRP_EN" title="GTX1:DFE_DRP_EN">GTX1:DFE_DRP_EN</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2C" title="GTX1:DRP2C[15]">GTX1:DRP2C[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DFE_CFG" title="GTX1:DFE_CFG[0]">GTX1:DFE_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[0]">GTX1:DRP2D[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DFE_CFG" title="GTX1:DFE_CFG[1]">GTX1:DFE_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[1]">GTX1:DRP2D[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DFE_CFG" title="GTX1:DFE_CFG[2]">GTX1:DFE_CFG[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[2]">GTX1:DRP2D[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DFE_CFG" title="GTX1:DFE_CFG[3]">GTX1:DFE_CFG[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[3]">GTX1:DRP2D[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DFE_CFG" title="GTX1:DFE_CFG[4]">GTX1:DFE_CFG[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[4]">GTX1:DRP2D[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DFE_CFG" title="GTX1:DFE_CFG[5]">GTX1:DFE_CFG[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[5]">GTX1:DRP2D[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DFE_CFG" title="GTX1:DFE_CFG[6]">GTX1:DFE_CFG[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[6]">GTX1:DRP2D[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DFE_CFG" title="GTX1:DFE_CFG[7]">GTX1:DFE_CFG[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[7]">GTX1:DRP2D[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[8]">GTX1:DRP2D[8]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EYE_OFFSET" title="GTX1:RX_EYE_OFFSET[0]">GTX1:RX_EYE_OFFSET[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[9]">GTX1:DRP2D[9]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EYE_OFFSET" title="GTX1:RX_EYE_OFFSET[1]">GTX1:RX_EYE_OFFSET[1]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[10]">GTX1:DRP2D[10]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EYE_OFFSET" title="GTX1:RX_EYE_OFFSET[2]">GTX1:RX_EYE_OFFSET[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[11]">GTX1:DRP2D[11]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EYE_OFFSET" title="GTX1:RX_EYE_OFFSET[3]">GTX1:RX_EYE_OFFSET[3]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[12]">GTX1:DRP2D[12]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EYE_OFFSET" title="GTX1:RX_EYE_OFFSET[4]">GTX1:RX_EYE_OFFSET[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[13]">GTX1:DRP2D[13]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EYE_OFFSET" title="GTX1:RX_EYE_OFFSET[5]">GTX1:RX_EYE_OFFSET[5]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[14]">GTX1:DRP2D[14]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EYE_OFFSET" title="GTX1:RX_EYE_OFFSET[6]">GTX1:RX_EYE_OFFSET[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2D" title="GTX1:DRP2D[15]">GTX1:DRP2D[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EYE_OFFSET" title="GTX1:RX_EYE_OFFSET[7]">GTX1:RX_EYE_OFFSET[7]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[0]">GTX1:DRP2E[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TERMINATION_CTRL" title="GTX1:TERMINATION_CTRL[0]">GTX1:TERMINATION_CTRL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[1]">GTX1:DRP2E[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TERMINATION_CTRL" title="GTX1:TERMINATION_CTRL[1]">GTX1:TERMINATION_CTRL[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[2]">GTX1:DRP2E[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TERMINATION_CTRL" title="GTX1:TERMINATION_CTRL[2]">GTX1:TERMINATION_CTRL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[3]">GTX1:DRP2E[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TERMINATION_CTRL" title="GTX1:TERMINATION_CTRL[3]">GTX1:TERMINATION_CTRL[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[4]">GTX1:DRP2E[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TERMINATION_CTRL" title="GTX1:TERMINATION_CTRL[4]">GTX1:TERMINATION_CTRL[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[5]">GTX1:DRP2E[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[6]">GTX1:DRP2E[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TERMINATION_OVRD" title="GTX1:TERMINATION_OVRD">GTX1:TERMINATION_OVRD</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[7]">GTX1:DRP2E[7]</a><br><a href="#bits-xc6v-GTX-GTX1:RCV_TERM_GND" title="GTX1:RCV_TERM_GND">GTX1:RCV_TERM_GND</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[8]">GTX1:DRP2E[8]</a><br><a href="#bits-xc6v-GTX-GTX1:RCV_TERM_VTTRX" title="GTX1:RCV_TERM_VTTRX">GTX1:RCV_TERM_VTTRX</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[9]">GTX1:DRP2E[9]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EYE_SCANMODE" title="GTX1:RX_EYE_SCANMODE[0]">GTX1:RX_EYE_SCANMODE[0]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[10]">GTX1:DRP2E[10]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EYE_SCANMODE" title="GTX1:RX_EYE_SCANMODE[1]">GTX1:RX_EYE_SCANMODE[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DFE_CAL_TIME" title="GTX1:DFE_CAL_TIME[0]">GTX1:DFE_CAL_TIME[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[11]">GTX1:DRP2E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DFE_CAL_TIME" title="GTX1:DFE_CAL_TIME[1]">GTX1:DFE_CAL_TIME[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[12]">GTX1:DRP2E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DFE_CAL_TIME" title="GTX1:DFE_CAL_TIME[2]">GTX1:DFE_CAL_TIME[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[13]">GTX1:DRP2E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DFE_CAL_TIME" title="GTX1:DFE_CAL_TIME[3]">GTX1:DFE_CAL_TIME[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[14]">GTX1:DRP2E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DFE_CAL_TIME" title="GTX1:DFE_CAL_TIME[4]">GTX1:DFE_CAL_TIME[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2E" title="GTX1:DRP2E[15]">GTX1:DRP2E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:COMMA_10B_ENABLE" title="GTX1:COMMA_10B_ENABLE[0]">GTX1:COMMA_10B_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[0]">GTX1:DRP2F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:COMMA_10B_ENABLE" title="GTX1:COMMA_10B_ENABLE[1]">GTX1:COMMA_10B_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[1]">GTX1:DRP2F[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:COMMA_10B_ENABLE" title="GTX1:COMMA_10B_ENABLE[2]">GTX1:COMMA_10B_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[2]">GTX1:DRP2F[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:COMMA_10B_ENABLE" title="GTX1:COMMA_10B_ENABLE[3]">GTX1:COMMA_10B_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[3]">GTX1:DRP2F[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:COMMA_10B_ENABLE" title="GTX1:COMMA_10B_ENABLE[4]">GTX1:COMMA_10B_ENABLE[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[4]">GTX1:DRP2F[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:COMMA_10B_ENABLE" title="GTX1:COMMA_10B_ENABLE[5]">GTX1:COMMA_10B_ENABLE[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[5]">GTX1:DRP2F[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:COMMA_10B_ENABLE" title="GTX1:COMMA_10B_ENABLE[6]">GTX1:COMMA_10B_ENABLE[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[6]">GTX1:DRP2F[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:COMMA_10B_ENABLE" title="GTX1:COMMA_10B_ENABLE[7]">GTX1:COMMA_10B_ENABLE[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[7]">GTX1:DRP2F[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:COMMA_10B_ENABLE" title="GTX1:COMMA_10B_ENABLE[8]">GTX1:COMMA_10B_ENABLE[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[8]">GTX1:DRP2F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:COMMA_10B_ENABLE" title="GTX1:COMMA_10B_ENABLE[9]">GTX1:COMMA_10B_ENABLE[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[9]">GTX1:DRP2F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:COMMA_DOUBLE" title="GTX1:COMMA_DOUBLE">GTX1:COMMA_DOUBLE</a><br><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[10]">GTX1:DRP2F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[11]">GTX1:DRP2F[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_IDLE_ASSERT_DELAY" title="GTX1:TX_IDLE_ASSERT_DELAY[0]">GTX1:TX_IDLE_ASSERT_DELAY[0]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[12]">GTX1:DRP2F[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_IDLE_ASSERT_DELAY" title="GTX1:TX_IDLE_ASSERT_DELAY[1]">GTX1:TX_IDLE_ASSERT_DELAY[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[13]">GTX1:DRP2F[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_IDLE_ASSERT_DELAY" title="GTX1:TX_IDLE_ASSERT_DELAY[2]">GTX1:TX_IDLE_ASSERT_DELAY[2]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[14]">GTX1:DRP2F[14]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_XCLK_SEL" title="GTX1:TX_XCLK_SEL">GTX1:TX_XCLK_SEL</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP2F" title="GTX1:DRP2F[15]">GTX1:DRP2F[15]</a><br><a href="#bits-xc6v-GTX-GTX1:TXGEARBOX_USE" title="GTX1:TXGEARBOX_USE">GTX1:TXGEARBOX_USE</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 16</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[0]">GTX1:DRP30[0]</a><br><a href="#bits-xc6v-GTX-GTX1:MCOMMA_10B_VALUE" title="GTX1:MCOMMA_10B_VALUE[0]">GTX1:MCOMMA_10B_VALUE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[1]">GTX1:DRP30[1]</a><br><a href="#bits-xc6v-GTX-GTX1:MCOMMA_10B_VALUE" title="GTX1:MCOMMA_10B_VALUE[1]">GTX1:MCOMMA_10B_VALUE[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[2]">GTX1:DRP30[2]</a><br><a href="#bits-xc6v-GTX-GTX1:MCOMMA_10B_VALUE" title="GTX1:MCOMMA_10B_VALUE[2]">GTX1:MCOMMA_10B_VALUE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[3]">GTX1:DRP30[3]</a><br><a href="#bits-xc6v-GTX-GTX1:MCOMMA_10B_VALUE" title="GTX1:MCOMMA_10B_VALUE[3]">GTX1:MCOMMA_10B_VALUE[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[4]">GTX1:DRP30[4]</a><br><a href="#bits-xc6v-GTX-GTX1:MCOMMA_10B_VALUE" title="GTX1:MCOMMA_10B_VALUE[4]">GTX1:MCOMMA_10B_VALUE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[5]">GTX1:DRP30[5]</a><br><a href="#bits-xc6v-GTX-GTX1:MCOMMA_10B_VALUE" title="GTX1:MCOMMA_10B_VALUE[5]">GTX1:MCOMMA_10B_VALUE[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[6]">GTX1:DRP30[6]</a><br><a href="#bits-xc6v-GTX-GTX1:MCOMMA_10B_VALUE" title="GTX1:MCOMMA_10B_VALUE[6]">GTX1:MCOMMA_10B_VALUE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[7]">GTX1:DRP30[7]</a><br><a href="#bits-xc6v-GTX-GTX1:MCOMMA_10B_VALUE" title="GTX1:MCOMMA_10B_VALUE[7]">GTX1:MCOMMA_10B_VALUE[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[8]">GTX1:DRP30[8]</a><br><a href="#bits-xc6v-GTX-GTX1:MCOMMA_10B_VALUE" title="GTX1:MCOMMA_10B_VALUE[8]">GTX1:MCOMMA_10B_VALUE[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[9]">GTX1:DRP30[9]</a><br><a href="#bits-xc6v-GTX-GTX1:MCOMMA_10B_VALUE" title="GTX1:MCOMMA_10B_VALUE[9]">GTX1:MCOMMA_10B_VALUE[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[10]">GTX1:DRP30[10]</a><br><a href="#bits-xc6v-GTX-GTX1:MCOMMA_DETECT" title="GTX1:MCOMMA_DETECT">GTX1:MCOMMA_DETECT</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[11]">GTX1:DRP30[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_IDLE_DEASSERT_DELAY" title="GTX1:TX_IDLE_DEASSERT_DELAY[0]">GTX1:TX_IDLE_DEASSERT_DELAY[0]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[12]">GTX1:DRP30[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_IDLE_DEASSERT_DELAY" title="GTX1:TX_IDLE_DEASSERT_DELAY[1]">GTX1:TX_IDLE_DEASSERT_DELAY[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[13]">GTX1:DRP30[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_IDLE_DEASSERT_DELAY" title="GTX1:TX_IDLE_DEASSERT_DELAY[2]">GTX1:TX_IDLE_DEASSERT_DELAY[2]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[14]">GTX1:DRP30[14]</a><br><a href="#bits-xc6v-GTX-GTX1:INV.TXUSRCLK" title="~GTX1:INV.TXUSRCLK">~GTX1:INV.TXUSRCLK</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP30" title="GTX1:DRP30[15]">GTX1:DRP30[15]</a><br><a href="#bits-xc6v-GTX-GTX1:INV.TXUSRCLK2" title="~GTX1:INV.TXUSRCLK2">~GTX1:INV.TXUSRCLK2</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[0]">GTX1:DRP31[0]</a><br><a href="#bits-xc6v-GTX-GTX1:PCOMMA_10B_VALUE" title="GTX1:PCOMMA_10B_VALUE[0]">GTX1:PCOMMA_10B_VALUE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[1]">GTX1:DRP31[1]</a><br><a href="#bits-xc6v-GTX-GTX1:PCOMMA_10B_VALUE" title="GTX1:PCOMMA_10B_VALUE[1]">GTX1:PCOMMA_10B_VALUE[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[2]">GTX1:DRP31[2]</a><br><a href="#bits-xc6v-GTX-GTX1:PCOMMA_10B_VALUE" title="GTX1:PCOMMA_10B_VALUE[2]">GTX1:PCOMMA_10B_VALUE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[3]">GTX1:DRP31[3]</a><br><a href="#bits-xc6v-GTX-GTX1:PCOMMA_10B_VALUE" title="GTX1:PCOMMA_10B_VALUE[3]">GTX1:PCOMMA_10B_VALUE[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[4]">GTX1:DRP31[4]</a><br><a href="#bits-xc6v-GTX-GTX1:PCOMMA_10B_VALUE" title="GTX1:PCOMMA_10B_VALUE[4]">GTX1:PCOMMA_10B_VALUE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[5]">GTX1:DRP31[5]</a><br><a href="#bits-xc6v-GTX-GTX1:PCOMMA_10B_VALUE" title="GTX1:PCOMMA_10B_VALUE[5]">GTX1:PCOMMA_10B_VALUE[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[6]">GTX1:DRP31[6]</a><br><a href="#bits-xc6v-GTX-GTX1:PCOMMA_10B_VALUE" title="GTX1:PCOMMA_10B_VALUE[6]">GTX1:PCOMMA_10B_VALUE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[7]">GTX1:DRP31[7]</a><br><a href="#bits-xc6v-GTX-GTX1:PCOMMA_10B_VALUE" title="GTX1:PCOMMA_10B_VALUE[7]">GTX1:PCOMMA_10B_VALUE[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[8]">GTX1:DRP31[8]</a><br><a href="#bits-xc6v-GTX-GTX1:PCOMMA_10B_VALUE" title="GTX1:PCOMMA_10B_VALUE[8]">GTX1:PCOMMA_10B_VALUE[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[9]">GTX1:DRP31[9]</a><br><a href="#bits-xc6v-GTX-GTX1:PCOMMA_10B_VALUE" title="GTX1:PCOMMA_10B_VALUE[9]">GTX1:PCOMMA_10B_VALUE[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[10]">GTX1:DRP31[10]</a><br><a href="#bits-xc6v-GTX-GTX1:PCOMMA_DETECT" title="GTX1:PCOMMA_DETECT">GTX1:PCOMMA_DETECT</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[11]">GTX1:DRP31[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_BUFFER_USE" title="GTX1:TX_BUFFER_USE">GTX1:TX_BUFFER_USE</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[12]">GTX1:DRP31[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DATA_WIDTH" title="GTX1:TX_DATA_WIDTH[0]">GTX1:TX_DATA_WIDTH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[13]">GTX1:DRP31[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DATA_WIDTH" title="GTX1:TX_DATA_WIDTH[1]">GTX1:TX_DATA_WIDTH[1]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[14]">GTX1:DRP31[14]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DATA_WIDTH" title="GTX1:TX_DATA_WIDTH[2]">GTX1:TX_DATA_WIDTH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP31" title="GTX1:DRP31[15]">GTX1:DRP31[15]</a><br><a href="#bits-xc6v-GTX-GTX1:GEN_TXUSRCLK" title="GTX1:GEN_TXUSRCLK">GTX1:GEN_TXUSRCLK</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[0]">GTX1:DRP32[0]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[0]">GTX1:PMA_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[1]">GTX1:DRP32[1]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[1]">GTX1:PMA_CFG[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[2]">GTX1:DRP32[2]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[2]">GTX1:PMA_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[3]">GTX1:DRP32[3]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[3]">GTX1:PMA_CFG[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[4]">GTX1:DRP32[4]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[4]">GTX1:PMA_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[5]">GTX1:DRP32[5]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[5]">GTX1:PMA_CFG[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[6]">GTX1:DRP32[6]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[6]">GTX1:PMA_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[7]">GTX1:DRP32[7]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[7]">GTX1:PMA_CFG[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[8]">GTX1:DRP32[8]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[8]">GTX1:PMA_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[9]">GTX1:DRP32[9]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[9]">GTX1:PMA_CFG[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[10]">GTX1:DRP32[10]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[10]">GTX1:PMA_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[11]">GTX1:DRP32[11]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[11]">GTX1:PMA_CFG[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[12]">GTX1:DRP32[12]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[12]">GTX1:PMA_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[13]">GTX1:DRP32[13]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[13]">GTX1:PMA_CFG[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[14]">GTX1:DRP32[14]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[14]">GTX1:PMA_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP32" title="GTX1:DRP32[15]">GTX1:DRP32[15]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[15]">GTX1:PMA_CFG[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[0]">GTX1:DRP33[0]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[16]">GTX1:PMA_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[1]">GTX1:DRP33[1]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[17]">GTX1:PMA_CFG[17]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[2]">GTX1:DRP33[2]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[18]">GTX1:PMA_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[3]">GTX1:DRP33[3]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[19]">GTX1:PMA_CFG[19]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[4]">GTX1:DRP33[4]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[20]">GTX1:PMA_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[5]">GTX1:DRP33[5]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[21]">GTX1:PMA_CFG[21]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[6]">GTX1:DRP33[6]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[22]">GTX1:PMA_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[7]">GTX1:DRP33[7]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[23]">GTX1:PMA_CFG[23]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[8]">GTX1:DRP33[8]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[24]">GTX1:PMA_CFG[24]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[9]">GTX1:DRP33[9]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[25]">GTX1:PMA_CFG[25]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[10]">GTX1:DRP33[10]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[26]">GTX1:PMA_CFG[26]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[11]">GTX1:DRP33[11]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[27]">GTX1:PMA_CFG[27]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[12]">GTX1:DRP33[12]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[28]">GTX1:PMA_CFG[28]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[13]">GTX1:DRP33[13]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[29]">GTX1:PMA_CFG[29]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[14]">GTX1:DRP33[14]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[30]">GTX1:PMA_CFG[30]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP33" title="GTX1:DRP33[15]">GTX1:DRP33[15]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[31]">GTX1:PMA_CFG[31]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[0]">GTX1:DRP34[0]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[32]">GTX1:PMA_CFG[32]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[1]">GTX1:DRP34[1]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[33]">GTX1:PMA_CFG[33]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[2]">GTX1:DRP34[2]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[34]">GTX1:PMA_CFG[34]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[3]">GTX1:DRP34[3]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[35]">GTX1:PMA_CFG[35]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[4]">GTX1:DRP34[4]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[36]">GTX1:PMA_CFG[36]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[5]">GTX1:DRP34[5]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[37]">GTX1:PMA_CFG[37]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[6]">GTX1:DRP34[6]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[38]">GTX1:PMA_CFG[38]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[7]">GTX1:DRP34[7]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[39]">GTX1:PMA_CFG[39]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[8]">GTX1:DRP34[8]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[40]">GTX1:PMA_CFG[40]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[9]">GTX1:DRP34[9]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[41]">GTX1:PMA_CFG[41]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[10]">GTX1:DRP34[10]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[42]">GTX1:PMA_CFG[42]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[11]">GTX1:DRP34[11]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[43]">GTX1:PMA_CFG[43]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[12]">GTX1:DRP34[12]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[44]">GTX1:PMA_CFG[44]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[13]">GTX1:DRP34[13]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[45]">GTX1:PMA_CFG[45]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[14]">GTX1:DRP34[14]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[46]">GTX1:PMA_CFG[46]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP34" title="GTX1:DRP34[15]">GTX1:DRP34[15]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[47]">GTX1:PMA_CFG[47]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[0]">GTX1:DRP35[0]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[48]">GTX1:PMA_CFG[48]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[1]">GTX1:DRP35[1]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[49]">GTX1:PMA_CFG[49]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[2]">GTX1:DRP35[2]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[50]">GTX1:PMA_CFG[50]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[3]">GTX1:DRP35[3]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[51]">GTX1:PMA_CFG[51]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[4]">GTX1:DRP35[4]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[52]">GTX1:PMA_CFG[52]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[5]">GTX1:DRP35[5]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[53]">GTX1:PMA_CFG[53]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[6]">GTX1:DRP35[6]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[54]">GTX1:PMA_CFG[54]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[7]">GTX1:DRP35[7]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[55]">GTX1:PMA_CFG[55]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[8]">GTX1:DRP35[8]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[56]">GTX1:PMA_CFG[56]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[9]">GTX1:DRP35[9]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[57]">GTX1:PMA_CFG[57]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[10]">GTX1:DRP35[10]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[58]">GTX1:PMA_CFG[58]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[11]">GTX1:DRP35[11]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[59]">GTX1:PMA_CFG[59]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[12]">GTX1:DRP35[12]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[60]">GTX1:PMA_CFG[60]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[13]">GTX1:DRP35[13]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[61]">GTX1:PMA_CFG[61]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[14]">GTX1:DRP35[14]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[62]">GTX1:PMA_CFG[62]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP35" title="GTX1:DRP35[15]">GTX1:DRP35[15]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[63]">GTX1:PMA_CFG[63]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[0]">GTX1:DRP36[0]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[16]">GTX1:PMA_TX_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[1]">GTX1:DRP36[1]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[17]">GTX1:PMA_TX_CFG[17]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[2]">GTX1:DRP36[2]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[18]">GTX1:PMA_TX_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[3]">GTX1:DRP36[3]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[19]">GTX1:PMA_TX_CFG[19]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[4]">GTX1:DRP36[4]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[64]">GTX1:PMA_CFG[64]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[5]">GTX1:DRP36[5]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[65]">GTX1:PMA_CFG[65]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[6]">GTX1:DRP36[6]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[66]">GTX1:PMA_CFG[66]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[7]">GTX1:DRP36[7]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[67]">GTX1:PMA_CFG[67]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[8]">GTX1:DRP36[8]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[68]">GTX1:PMA_CFG[68]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[9]">GTX1:DRP36[9]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[69]">GTX1:PMA_CFG[69]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[10]">GTX1:DRP36[10]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[70]">GTX1:PMA_CFG[70]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[11]">GTX1:DRP36[11]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[71]">GTX1:PMA_CFG[71]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[12]">GTX1:DRP36[12]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[72]">GTX1:PMA_CFG[72]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[13]">GTX1:DRP36[13]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[73]">GTX1:PMA_CFG[73]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[14]">GTX1:DRP36[14]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[74]">GTX1:PMA_CFG[74]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP36" title="GTX1:DRP36[15]">GTX1:DRP36[15]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_CFG" title="GTX1:PMA_CFG[75]">GTX1:PMA_CFG[75]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[0]">GTX1:DRP37[0]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[0]">GTX1:PMA_TX_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[1]">GTX1:DRP37[1]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[1]">GTX1:PMA_TX_CFG[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[2]">GTX1:DRP37[2]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[2]">GTX1:PMA_TX_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[3]">GTX1:DRP37[3]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[3]">GTX1:PMA_TX_CFG[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[4]">GTX1:DRP37[4]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[4]">GTX1:PMA_TX_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[5]">GTX1:DRP37[5]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[5]">GTX1:PMA_TX_CFG[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[6]">GTX1:DRP37[6]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[6]">GTX1:PMA_TX_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[7]">GTX1:DRP37[7]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[7]">GTX1:PMA_TX_CFG[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[8]">GTX1:DRP37[8]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[8]">GTX1:PMA_TX_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[9]">GTX1:DRP37[9]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[9]">GTX1:PMA_TX_CFG[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[10]">GTX1:DRP37[10]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[10]">GTX1:PMA_TX_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[11]">GTX1:DRP37[11]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[11]">GTX1:PMA_TX_CFG[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[12]">GTX1:DRP37[12]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[12]">GTX1:PMA_TX_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[13]">GTX1:DRP37[13]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[13]">GTX1:PMA_TX_CFG[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[14]">GTX1:DRP37[14]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[14]">GTX1:PMA_TX_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP37" title="GTX1:DRP37[15]">GTX1:DRP37[15]</a><br><a href="#bits-xc6v-GTX-GTX1:PMA_TX_CFG" title="GTX1:PMA_TX_CFG[15]">GTX1:PMA_TX_CFG[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 17</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[0]">GTX1:DRP38[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_0" title="GTX1:TX_MARGIN_LOW_0[0]">GTX1:TX_MARGIN_LOW_0[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[1]">GTX1:DRP38[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_0" title="GTX1:TX_MARGIN_LOW_0[1]">GTX1:TX_MARGIN_LOW_0[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[2]">GTX1:DRP38[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_0" title="GTX1:TX_MARGIN_LOW_0[2]">GTX1:TX_MARGIN_LOW_0[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[3]">GTX1:DRP38[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_0" title="GTX1:TX_MARGIN_LOW_0[3]">GTX1:TX_MARGIN_LOW_0[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[4]">GTX1:DRP38[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_0" title="GTX1:TX_MARGIN_LOW_0[4]">GTX1:TX_MARGIN_LOW_0[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[5]">GTX1:DRP38[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_0" title="GTX1:TX_MARGIN_LOW_0[5]">GTX1:TX_MARGIN_LOW_0[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[6]">GTX1:DRP38[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_0" title="GTX1:TX_MARGIN_LOW_0[6]">GTX1:TX_MARGIN_LOW_0[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[7]">GTX1:DRP38[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_0" title="GTX1:TX_MARGIN_FULL_0[0]">GTX1:TX_MARGIN_FULL_0[0]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[8]">GTX1:DRP38[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_0" title="GTX1:TX_MARGIN_FULL_0[1]">GTX1:TX_MARGIN_FULL_0[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[9]">GTX1:DRP38[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_0" title="GTX1:TX_MARGIN_FULL_0[2]">GTX1:TX_MARGIN_FULL_0[2]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[10]">GTX1:DRP38[10]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_0" title="GTX1:TX_MARGIN_FULL_0[3]">GTX1:TX_MARGIN_FULL_0[3]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[11]">GTX1:DRP38[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_0" title="GTX1:TX_MARGIN_FULL_0[4]">GTX1:TX_MARGIN_FULL_0[4]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[12]">GTX1:DRP38[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_0" title="GTX1:TX_MARGIN_FULL_0[5]">GTX1:TX_MARGIN_FULL_0[5]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[13]">GTX1:DRP38[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_0" title="GTX1:TX_MARGIN_FULL_0[6]">GTX1:TX_MARGIN_FULL_0[6]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[14]">GTX1:DRP38[14]</a><br><a href="#bits-xc6v-GTX-GTX1:TXOUTCLKPCS_SEL" title="GTX1:TXOUTCLKPCS_SEL">GTX1:TXOUTCLKPCS_SEL</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP38" title="GTX1:DRP38[15]">GTX1:DRP38[15]</a><br><a href="#bits-xc6v-GTX-GTX1:INV.DCLK" title="~GTX1:INV.DCLK">~GTX1:INV.DCLK</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[0]">GTX1:DRP39[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_1" title="GTX1:TX_MARGIN_LOW_1[0]">GTX1:TX_MARGIN_LOW_1[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[1]">GTX1:DRP39[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_1" title="GTX1:TX_MARGIN_LOW_1[1]">GTX1:TX_MARGIN_LOW_1[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[2]">GTX1:DRP39[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_1" title="GTX1:TX_MARGIN_LOW_1[2]">GTX1:TX_MARGIN_LOW_1[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[3]">GTX1:DRP39[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_1" title="GTX1:TX_MARGIN_LOW_1[3]">GTX1:TX_MARGIN_LOW_1[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[4]">GTX1:DRP39[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_1" title="GTX1:TX_MARGIN_LOW_1[4]">GTX1:TX_MARGIN_LOW_1[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[5]">GTX1:DRP39[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_1" title="GTX1:TX_MARGIN_LOW_1[5]">GTX1:TX_MARGIN_LOW_1[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[6]">GTX1:DRP39[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_1" title="GTX1:TX_MARGIN_LOW_1[6]">GTX1:TX_MARGIN_LOW_1[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[7]">GTX1:DRP39[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_1" title="GTX1:TX_MARGIN_FULL_1[0]">GTX1:TX_MARGIN_FULL_1[0]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[8]">GTX1:DRP39[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_1" title="GTX1:TX_MARGIN_FULL_1[1]">GTX1:TX_MARGIN_FULL_1[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[9]">GTX1:DRP39[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_1" title="GTX1:TX_MARGIN_FULL_1[2]">GTX1:TX_MARGIN_FULL_1[2]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[10]">GTX1:DRP39[10]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_1" title="GTX1:TX_MARGIN_FULL_1[3]">GTX1:TX_MARGIN_FULL_1[3]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[11]">GTX1:DRP39[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_1" title="GTX1:TX_MARGIN_FULL_1[4]">GTX1:TX_MARGIN_FULL_1[4]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[12]">GTX1:DRP39[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_1" title="GTX1:TX_MARGIN_FULL_1[5]">GTX1:TX_MARGIN_FULL_1[5]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[13]">GTX1:DRP39[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_1" title="GTX1:TX_MARGIN_FULL_1[6]">GTX1:TX_MARGIN_FULL_1[6]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[14]">GTX1:DRP39[14]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_TDCC_CFG" title="GTX1:TX_TDCC_CFG[0]">GTX1:TX_TDCC_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP39" title="GTX1:DRP39[15]">GTX1:DRP39[15]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_TDCC_CFG" title="GTX1:TX_TDCC_CFG[1]">GTX1:TX_TDCC_CFG[1]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[0]">GTX1:DRP3A[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_2" title="GTX1:TX_MARGIN_LOW_2[0]">GTX1:TX_MARGIN_LOW_2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[1]">GTX1:DRP3A[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_2" title="GTX1:TX_MARGIN_LOW_2[1]">GTX1:TX_MARGIN_LOW_2[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[2]">GTX1:DRP3A[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_2" title="GTX1:TX_MARGIN_LOW_2[2]">GTX1:TX_MARGIN_LOW_2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[3]">GTX1:DRP3A[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_2" title="GTX1:TX_MARGIN_LOW_2[3]">GTX1:TX_MARGIN_LOW_2[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[4]">GTX1:DRP3A[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_2" title="GTX1:TX_MARGIN_LOW_2[4]">GTX1:TX_MARGIN_LOW_2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[5]">GTX1:DRP3A[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_2" title="GTX1:TX_MARGIN_LOW_2[5]">GTX1:TX_MARGIN_LOW_2[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[6]">GTX1:DRP3A[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_2" title="GTX1:TX_MARGIN_LOW_2[6]">GTX1:TX_MARGIN_LOW_2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[7]">GTX1:DRP3A[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_2" title="GTX1:TX_MARGIN_FULL_2[0]">GTX1:TX_MARGIN_FULL_2[0]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[8]">GTX1:DRP3A[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_2" title="GTX1:TX_MARGIN_FULL_2[1]">GTX1:TX_MARGIN_FULL_2[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[9]">GTX1:DRP3A[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_2" title="GTX1:TX_MARGIN_FULL_2[2]">GTX1:TX_MARGIN_FULL_2[2]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[10]">GTX1:DRP3A[10]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_2" title="GTX1:TX_MARGIN_FULL_2[3]">GTX1:TX_MARGIN_FULL_2[3]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[11]">GTX1:DRP3A[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_2" title="GTX1:TX_MARGIN_FULL_2[4]">GTX1:TX_MARGIN_FULL_2[4]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[12]">GTX1:DRP3A[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_2" title="GTX1:TX_MARGIN_FULL_2[5]">GTX1:TX_MARGIN_FULL_2[5]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[13]">GTX1:DRP3A[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_2" title="GTX1:TX_MARGIN_FULL_2[6]">GTX1:TX_MARGIN_FULL_2[6]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[14]">GTX1:DRP3A[14]</a><br><a href="#bits-xc6v-GTX-GTX1:TXDRIVE_LOOPBACK_HIZ" title="~GTX1:TXDRIVE_LOOPBACK_HIZ">~GTX1:TXDRIVE_LOOPBACK_HIZ</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3A" title="GTX1:DRP3A[15]">GTX1:DRP3A[15]</a><br><a href="#bits-xc6v-GTX-GTX1:TXDRIVE_LOOPBACK_PD" title="~GTX1:TXDRIVE_LOOPBACK_PD">~GTX1:TXDRIVE_LOOPBACK_PD</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[0]">GTX1:DRP3B[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_3" title="GTX1:TX_MARGIN_LOW_3[0]">GTX1:TX_MARGIN_LOW_3[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[1]">GTX1:DRP3B[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_3" title="GTX1:TX_MARGIN_LOW_3[1]">GTX1:TX_MARGIN_LOW_3[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[2]">GTX1:DRP3B[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_3" title="GTX1:TX_MARGIN_LOW_3[2]">GTX1:TX_MARGIN_LOW_3[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[3]">GTX1:DRP3B[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_3" title="GTX1:TX_MARGIN_LOW_3[3]">GTX1:TX_MARGIN_LOW_3[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[4]">GTX1:DRP3B[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_3" title="GTX1:TX_MARGIN_LOW_3[4]">GTX1:TX_MARGIN_LOW_3[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[5]">GTX1:DRP3B[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_3" title="GTX1:TX_MARGIN_LOW_3[5]">GTX1:TX_MARGIN_LOW_3[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[6]">GTX1:DRP3B[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_3" title="GTX1:TX_MARGIN_LOW_3[6]">GTX1:TX_MARGIN_LOW_3[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[7]">GTX1:DRP3B[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_3" title="GTX1:TX_MARGIN_FULL_3[0]">GTX1:TX_MARGIN_FULL_3[0]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[8]">GTX1:DRP3B[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_3" title="GTX1:TX_MARGIN_FULL_3[1]">GTX1:TX_MARGIN_FULL_3[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[9]">GTX1:DRP3B[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_3" title="GTX1:TX_MARGIN_FULL_3[2]">GTX1:TX_MARGIN_FULL_3[2]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[10]">GTX1:DRP3B[10]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_3" title="GTX1:TX_MARGIN_FULL_3[3]">GTX1:TX_MARGIN_FULL_3[3]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[11]">GTX1:DRP3B[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_3" title="GTX1:TX_MARGIN_FULL_3[4]">GTX1:TX_MARGIN_FULL_3[4]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[12]">GTX1:DRP3B[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_3" title="GTX1:TX_MARGIN_FULL_3[5]">GTX1:TX_MARGIN_FULL_3[5]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[13]">GTX1:DRP3B[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_3" title="GTX1:TX_MARGIN_FULL_3[6]">GTX1:TX_MARGIN_FULL_3[6]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXSWING" title="GTX1:A_TXSWING">GTX1:A_TXSWING</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[14]">GTX1:DRP3B[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXDEEMPH" title="GTX1:A_TXDEEMPH">GTX1:A_TXDEEMPH</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3B" title="GTX1:DRP3B[15]">GTX1:DRP3B[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[0]">GTX1:DRP3C[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_4" title="GTX1:TX_MARGIN_LOW_4[0]">GTX1:TX_MARGIN_LOW_4[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[1]">GTX1:DRP3C[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_4" title="GTX1:TX_MARGIN_LOW_4[1]">GTX1:TX_MARGIN_LOW_4[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[2]">GTX1:DRP3C[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_4" title="GTX1:TX_MARGIN_LOW_4[2]">GTX1:TX_MARGIN_LOW_4[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[3]">GTX1:DRP3C[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_4" title="GTX1:TX_MARGIN_LOW_4[3]">GTX1:TX_MARGIN_LOW_4[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[4]">GTX1:DRP3C[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_4" title="GTX1:TX_MARGIN_LOW_4[4]">GTX1:TX_MARGIN_LOW_4[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[5]">GTX1:DRP3C[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_4" title="GTX1:TX_MARGIN_LOW_4[5]">GTX1:TX_MARGIN_LOW_4[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[6]">GTX1:DRP3C[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_4" title="GTX1:TX_MARGIN_LOW_4[6]">GTX1:TX_MARGIN_LOW_4[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[7]">GTX1:DRP3C[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_4" title="GTX1:TX_MARGIN_FULL_4[0]">GTX1:TX_MARGIN_FULL_4[0]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[8]">GTX1:DRP3C[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_4" title="GTX1:TX_MARGIN_FULL_4[1]">GTX1:TX_MARGIN_FULL_4[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[9]">GTX1:DRP3C[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_4" title="GTX1:TX_MARGIN_FULL_4[2]">GTX1:TX_MARGIN_FULL_4[2]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[10]">GTX1:DRP3C[10]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_4" title="GTX1:TX_MARGIN_FULL_4[3]">GTX1:TX_MARGIN_FULL_4[3]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[11]">GTX1:DRP3C[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_4" title="GTX1:TX_MARGIN_FULL_4[4]">GTX1:TX_MARGIN_FULL_4[4]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[12]">GTX1:DRP3C[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_4" title="GTX1:TX_MARGIN_FULL_4[5]">GTX1:TX_MARGIN_FULL_4[5]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[13]">GTX1:DRP3C[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_4" title="GTX1:TX_MARGIN_FULL_4[6]">GTX1:TX_MARGIN_FULL_4[6]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[14]">GTX1:DRP3C[14]</a><br><a href="#bits-xc6v-GTX-GTX1:TXDRIVE_DRP_EN" title="GTX1:TXDRIVE_DRP_EN">GTX1:TXDRIVE_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3C" title="GTX1:DRP3C[15]">GTX1:DRP3C[15]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DRIVE_MODE" title="GTX1:TX_DRIVE_MODE">GTX1:TX_DRIVE_MODE</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXDIFFCTRL" title="GTX1:A_TXDIFFCTRL[0]">GTX1:A_TXDIFFCTRL[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[0]">GTX1:DRP3D[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXDIFFCTRL" title="GTX1:A_TXDIFFCTRL[1]">GTX1:A_TXDIFFCTRL[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[1]">GTX1:DRP3D[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXDIFFCTRL" title="GTX1:A_TXDIFFCTRL[2]">GTX1:A_TXDIFFCTRL[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[2]">GTX1:DRP3D[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXDIFFCTRL" title="GTX1:A_TXDIFFCTRL[3]">GTX1:A_TXDIFFCTRL[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[3]">GTX1:DRP3D[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXBUFDIFFCTRL" title="GTX1:A_TXBUFDIFFCTRL[0]">GTX1:A_TXBUFDIFFCTRL[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[4]">GTX1:DRP3D[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXBUFDIFFCTRL" title="GTX1:A_TXBUFDIFFCTRL[1]">GTX1:A_TXBUFDIFFCTRL[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[5]">GTX1:DRP3D[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXBUFDIFFCTRL" title="GTX1:A_TXBUFDIFFCTRL[2]">GTX1:A_TXBUFDIFFCTRL[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[6]">GTX1:DRP3D[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPREEMPHASIS" title="GTX1:A_TXPREEMPHASIS[0]">GTX1:A_TXPREEMPHASIS[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[7]">GTX1:DRP3D[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPREEMPHASIS" title="GTX1:A_TXPREEMPHASIS[1]">GTX1:A_TXPREEMPHASIS[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[8]">GTX1:DRP3D[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPREEMPHASIS" title="GTX1:A_TXPREEMPHASIS[2]">GTX1:A_TXPREEMPHASIS[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[9]">GTX1:DRP3D[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPREEMPHASIS" title="GTX1:A_TXPREEMPHASIS[3]">GTX1:A_TXPREEMPHASIS[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[10]">GTX1:DRP3D[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPOSTEMPHASIS" title="GTX1:A_TXPOSTEMPHASIS[0]">GTX1:A_TXPOSTEMPHASIS[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[11]">GTX1:DRP3D[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPOSTEMPHASIS" title="GTX1:A_TXPOSTEMPHASIS[1]">GTX1:A_TXPOSTEMPHASIS[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[12]">GTX1:DRP3D[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPOSTEMPHASIS" title="GTX1:A_TXPOSTEMPHASIS[2]">GTX1:A_TXPOSTEMPHASIS[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[13]">GTX1:DRP3D[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPOSTEMPHASIS" title="GTX1:A_TXPOSTEMPHASIS[3]">GTX1:A_TXPOSTEMPHASIS[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[14]">GTX1:DRP3D[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXPOSTEMPHASIS" title="GTX1:A_TXPOSTEMPHASIS[4]">GTX1:A_TXPOSTEMPHASIS[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3D" title="GTX1:DRP3D[15]">GTX1:DRP3D[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[0]">GTX1:DRP3E[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DEEMPH_0" title="GTX1:TX_DEEMPH_0[0]">GTX1:TX_DEEMPH_0[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[1]">GTX1:DRP3E[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DEEMPH_0" title="GTX1:TX_DEEMPH_0[1]">GTX1:TX_DEEMPH_0[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[2]">GTX1:DRP3E[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DEEMPH_0" title="GTX1:TX_DEEMPH_0[2]">GTX1:TX_DEEMPH_0[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[3]">GTX1:DRP3E[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DEEMPH_0" title="GTX1:TX_DEEMPH_0[3]">GTX1:TX_DEEMPH_0[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[4]">GTX1:DRP3E[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DEEMPH_0" title="GTX1:TX_DEEMPH_0[4]">GTX1:TX_DEEMPH_0[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[5]">GTX1:DRP3E[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DEEMPH_1" title="GTX1:TX_DEEMPH_1[0]">GTX1:TX_DEEMPH_1[0]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[6]">GTX1:DRP3E[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DEEMPH_1" title="GTX1:TX_DEEMPH_1[1]">GTX1:TX_DEEMPH_1[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[7]">GTX1:DRP3E[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DEEMPH_1" title="GTX1:TX_DEEMPH_1[2]">GTX1:TX_DEEMPH_1[2]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[8]">GTX1:DRP3E[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DEEMPH_1" title="GTX1:TX_DEEMPH_1[3]">GTX1:TX_DEEMPH_1[3]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[9]">GTX1:DRP3E[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DEEMPH_1" title="GTX1:TX_DEEMPH_1[4]">GTX1:TX_DEEMPH_1[4]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[10]">GTX1:DRP3E[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[11]">GTX1:DRP3E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[12]">GTX1:DRP3E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXMARGIN" title="GTX1:A_TXMARGIN[0]">GTX1:A_TXMARGIN[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[13]">GTX1:DRP3E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_TXMARGIN" title="GTX1:A_TXMARGIN[1]">GTX1:A_TXMARGIN[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[14]">GTX1:DRP3E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_TXMARGIN" title="GTX1:A_TXMARGIN[2]">GTX1:A_TXMARGIN[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP3E" title="GTX1:DRP3E[15]">GTX1:DRP3E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[0]">GTX1:DRP3F[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_RATE" title="GTX1:TRANS_TIME_RATE[0]">GTX1:TRANS_TIME_RATE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[1]">GTX1:DRP3F[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_RATE" title="GTX1:TRANS_TIME_RATE[1]">GTX1:TRANS_TIME_RATE[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[2]">GTX1:DRP3F[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_RATE" title="GTX1:TRANS_TIME_RATE[2]">GTX1:TRANS_TIME_RATE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[3]">GTX1:DRP3F[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_RATE" title="GTX1:TRANS_TIME_RATE[3]">GTX1:TRANS_TIME_RATE[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[4]">GTX1:DRP3F[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_RATE" title="GTX1:TRANS_TIME_RATE[4]">GTX1:TRANS_TIME_RATE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[5]">GTX1:DRP3F[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_RATE" title="GTX1:TRANS_TIME_RATE[5]">GTX1:TRANS_TIME_RATE[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[6]">GTX1:DRP3F[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_RATE" title="GTX1:TRANS_TIME_RATE[6]">GTX1:TRANS_TIME_RATE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[7]">GTX1:DRP3F[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TRANS_TIME_RATE" title="GTX1:TRANS_TIME_RATE[7]">GTX1:TRANS_TIME_RATE[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[8]">GTX1:DRP3F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[9]">GTX1:DRP3F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[10]">GTX1:DRP3F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[11]">GTX1:DRP3F[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[12]">GTX1:DRP3F[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[13]">GTX1:DRP3F[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[14]">GTX1:DRP3F[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP3F" title="GTX1:DRP3F[15]">GTX1:DRP3F[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 18</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_RXEQMIX" title="GTX1:A_RXEQMIX[0]">GTX1:A_RXEQMIX[0]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[0]">GTX1:DRP40[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_RXEQMIX" title="GTX1:A_RXEQMIX[1]">GTX1:A_RXEQMIX[1]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[1]">GTX1:DRP40[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_RXEQMIX" title="GTX1:A_RXEQMIX[2]">GTX1:A_RXEQMIX[2]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[2]">GTX1:DRP40[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_RXEQMIX" title="GTX1:A_RXEQMIX[3]">GTX1:A_RXEQMIX[3]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[3]">GTX1:DRP40[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_RXEQMIX" title="GTX1:A_RXEQMIX[4]">GTX1:A_RXEQMIX[4]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[4]">GTX1:DRP40[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_RXEQMIX" title="GTX1:A_RXEQMIX[5]">GTX1:A_RXEQMIX[5]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[5]">GTX1:DRP40[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_RXEQMIX" title="GTX1:A_RXEQMIX[6]">GTX1:A_RXEQMIX[6]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[6]">GTX1:DRP40[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_RXEQMIX" title="GTX1:A_RXEQMIX[7]">GTX1:A_RXEQMIX[7]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[7]">GTX1:DRP40[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:A_RXEQMIX" title="GTX1:A_RXEQMIX[8]">GTX1:A_RXEQMIX[8]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[8]">GTX1:DRP40[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:A_RXEQMIX" title="GTX1:A_RXEQMIX[9]">GTX1:A_RXEQMIX[9]</a><br><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[9]">GTX1:DRP40[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[10]">GTX1:DRP40[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[11]">GTX1:DRP40[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[12]">GTX1:DRP40[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[13]">GTX1:DRP40[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[14]">GTX1:DRP40[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP40" title="GTX1:DRP40[15]">GTX1:DRP40[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[0]">GTX1:DRP41[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[16]">GTX1:TST_ATTR[16]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[1]">GTX1:DRP41[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[17]">GTX1:TST_ATTR[17]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[2]">GTX1:DRP41[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[18]">GTX1:TST_ATTR[18]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[3]">GTX1:DRP41[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[19]">GTX1:TST_ATTR[19]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[4]">GTX1:DRP41[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[20]">GTX1:TST_ATTR[20]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[5]">GTX1:DRP41[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[21]">GTX1:TST_ATTR[21]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[6]">GTX1:DRP41[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[22]">GTX1:TST_ATTR[22]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[7]">GTX1:DRP41[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[23]">GTX1:TST_ATTR[23]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[8]">GTX1:DRP41[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[24]">GTX1:TST_ATTR[24]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[9]">GTX1:DRP41[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[25]">GTX1:TST_ATTR[25]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[10]">GTX1:DRP41[10]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[26]">GTX1:TST_ATTR[26]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[11]">GTX1:DRP41[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[27]">GTX1:TST_ATTR[27]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[12]">GTX1:DRP41[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[28]">GTX1:TST_ATTR[28]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[13]">GTX1:DRP41[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[29]">GTX1:TST_ATTR[29]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[14]">GTX1:DRP41[14]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[30]">GTX1:TST_ATTR[30]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP41" title="GTX1:DRP41[15]">GTX1:DRP41[15]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[31]">GTX1:TST_ATTR[31]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[0]">GTX1:DRP42[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[0]">GTX1:TST_ATTR[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[1]">GTX1:DRP42[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[1]">GTX1:TST_ATTR[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[2]">GTX1:DRP42[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[2]">GTX1:TST_ATTR[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[3]">GTX1:DRP42[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[3]">GTX1:TST_ATTR[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[4]">GTX1:DRP42[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[4]">GTX1:TST_ATTR[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[5]">GTX1:DRP42[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[5]">GTX1:TST_ATTR[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[6]">GTX1:DRP42[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[6]">GTX1:TST_ATTR[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[7]">GTX1:DRP42[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[7]">GTX1:TST_ATTR[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[8]">GTX1:DRP42[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[8]">GTX1:TST_ATTR[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[9]">GTX1:DRP42[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[9]">GTX1:TST_ATTR[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[10]">GTX1:DRP42[10]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[10]">GTX1:TST_ATTR[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[11]">GTX1:DRP42[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[11]">GTX1:TST_ATTR[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[12]">GTX1:DRP42[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[12]">GTX1:TST_ATTR[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[13]">GTX1:DRP42[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[13]">GTX1:TST_ATTR[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[14]">GTX1:DRP42[14]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[14]">GTX1:TST_ATTR[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP42" title="GTX1:DRP42[15]">GTX1:DRP42[15]</a><br><a href="#bits-xc6v-GTX-GTX1:TST_ATTR" title="GTX1:TST_ATTR[15]">GTX1:TST_ATTR[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[0]">GTX1:DRP43[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TXOUTCLK_CTRL" title="GTX1:TXOUTCLK_CTRL[2]">GTX1:TXOUTCLK_CTRL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[1]">GTX1:DRP43[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TXOUTCLK_CTRL" title="GTX1:TXOUTCLK_CTRL[1]">GTX1:TXOUTCLK_CTRL[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[2]">GTX1:DRP43[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TXOUTCLK_CTRL" title="GTX1:TXOUTCLK_CTRL[0]">GTX1:TXOUTCLK_CTRL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[3]">GTX1:DRP43[3]</a><br><a href="#bits-xc6v-GTX-GTX1:RXRECCLK_CTRL" title="GTX1:RXRECCLK_CTRL[2]">GTX1:RXRECCLK_CTRL[2]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[4]">GTX1:DRP43[4]</a><br><a href="#bits-xc6v-GTX-GTX1:RXRECCLK_CTRL" title="GTX1:RXRECCLK_CTRL[1]">GTX1:RXRECCLK_CTRL[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[5]">GTX1:DRP43[5]</a><br><a href="#bits-xc6v-GTX-GTX1:RXRECCLK_CTRL" title="GTX1:RXRECCLK_CTRL[0]">GTX1:RXRECCLK_CTRL[0]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[6]">GTX1:DRP43[6]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX0:MUX.HCLK_OUT" title="IBUFDS_GTX0:MUX.HCLK_OUT[1]">IBUFDS_GTX0:MUX.HCLK_OUT[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[7]">GTX1:DRP43[7]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX0:MUX.HCLK_OUT" title="IBUFDS_GTX0:MUX.HCLK_OUT[0]">IBUFDS_GTX0:MUX.HCLK_OUT[0]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[8]">GTX1:DRP43[8]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX1:MUX.HCLK_OUT" title="IBUFDS_GTX1:MUX.HCLK_OUT[1]">IBUFDS_GTX1:MUX.HCLK_OUT[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[9]">GTX1:DRP43[9]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX1:MUX.HCLK_OUT" title="IBUFDS_GTX1:MUX.HCLK_OUT[0]">IBUFDS_GTX1:MUX.HCLK_OUT[0]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[10]">GTX1:DRP43[10]</a><br><a href="#bits-xc6v-GTX-GTX1:INV.TSTCLK0" title="~GTX1:INV.TSTCLK0">~GTX1:INV.TSTCLK0</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[11]">GTX1:DRP43[11]</a><br><a href="#bits-xc6v-GTX-GTX1:INV.TSTCLK1" title="~GTX1:INV.TSTCLK1">~GTX1:INV.TSTCLK1</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[12]">GTX1:DRP43[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[13]">GTX1:DRP43[13]</a><br><a href="#bits-xc6v-GTX-GTX1:INV.SCANCLK" title="~GTX1:INV.SCANCLK">~GTX1:INV.SCANCLK</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[14]">GTX1:DRP43[14]</a><br><a href="#bits-xc6v-GTX-GTX1:INV.GREFCLKTX" title="~GTX1:INV.GREFCLKTX">~GTX1:INV.GREFCLKTX</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP43" title="GTX1:DRP43[15]">GTX1:DRP43[15]</a><br><a href="#bits-xc6v-GTX-GTX1:INV.GREFCLKRX" title="~GTX1:INV.GREFCLKRX">~GTX1:INV.GREFCLKRX</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[0]">GTX1:DRP44[0]</a><br><a href="#bits-xc6v-GTX-GTX1:POWER_SAVE" title="GTX1:POWER_SAVE[0]">GTX1:POWER_SAVE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[1]">GTX1:DRP44[1]</a><br><a href="#bits-xc6v-GTX-GTX1:POWER_SAVE" title="GTX1:POWER_SAVE[1]">GTX1:POWER_SAVE[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[2]">GTX1:DRP44[2]</a><br><a href="#bits-xc6v-GTX-GTX1:POWER_SAVE" title="GTX1:POWER_SAVE[2]">GTX1:POWER_SAVE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[3]">GTX1:DRP44[3]</a><br><a href="#bits-xc6v-GTX-GTX1:POWER_SAVE" title="GTX1:POWER_SAVE[3]">GTX1:POWER_SAVE[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[4]">GTX1:DRP44[4]</a><br><a href="#bits-xc6v-GTX-GTX1:POWER_SAVE" title="GTX1:POWER_SAVE[4]">GTX1:POWER_SAVE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[5]">GTX1:DRP44[5]</a><br><a href="#bits-xc6v-GTX-GTX1:POWER_SAVE" title="GTX1:POWER_SAVE[5]">GTX1:POWER_SAVE[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[6]">GTX1:DRP44[6]</a><br><a href="#bits-xc6v-GTX-GTX1:POWER_SAVE" title="GTX1:POWER_SAVE[6]">GTX1:POWER_SAVE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[7]">GTX1:DRP44[7]</a><br><a href="#bits-xc6v-GTX-GTX1:POWER_SAVE" title="GTX1:POWER_SAVE[7]">GTX1:POWER_SAVE[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[8]">GTX1:DRP44[8]</a><br><a href="#bits-xc6v-GTX-GTX1:POWER_SAVE" title="GTX1:POWER_SAVE[8]">GTX1:POWER_SAVE[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[9]">GTX1:DRP44[9]</a><br><a href="#bits-xc6v-GTX-GTX1:POWER_SAVE" title="GTX1:POWER_SAVE[9]">GTX1:POWER_SAVE[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[10]">GTX1:DRP44[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[11]">GTX1:DRP44[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[12]">GTX1:DRP44[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[13]">GTX1:DRP44[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[14]">GTX1:DRP44[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP44" title="GTX1:DRP44[15]">GTX1:DRP44[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[0]">GTX1:DRP45[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_BYTECLK_CFG" title="GTX1:TX_BYTECLK_CFG[0]">GTX1:TX_BYTECLK_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[1]">GTX1:DRP45[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_BYTECLK_CFG" title="GTX1:TX_BYTECLK_CFG[1]">GTX1:TX_BYTECLK_CFG[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[2]">GTX1:DRP45[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_BYTECLK_CFG" title="GTX1:TX_BYTECLK_CFG[2]">GTX1:TX_BYTECLK_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[3]">GTX1:DRP45[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_BYTECLK_CFG" title="GTX1:TX_BYTECLK_CFG[3]">GTX1:TX_BYTECLK_CFG[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[4]">GTX1:DRP45[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_BYTECLK_CFG" title="GTX1:TX_BYTECLK_CFG[4]">GTX1:TX_BYTECLK_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[5]">GTX1:DRP45[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_BYTECLK_CFG" title="GTX1:TX_BYTECLK_CFG[5]">GTX1:TX_BYTECLK_CFG[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[6]">GTX1:DRP45[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_USRCLK_CFG" title="GTX1:TX_USRCLK_CFG[0]">GTX1:TX_USRCLK_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[7]">GTX1:DRP45[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_USRCLK_CFG" title="GTX1:TX_USRCLK_CFG[1]">GTX1:TX_USRCLK_CFG[1]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[8]">GTX1:DRP45[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_USRCLK_CFG" title="GTX1:TX_USRCLK_CFG[2]">GTX1:TX_USRCLK_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[9]">GTX1:DRP45[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_USRCLK_CFG" title="GTX1:TX_USRCLK_CFG[3]">GTX1:TX_USRCLK_CFG[3]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[10]">GTX1:DRP45[10]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_USRCLK_CFG" title="GTX1:TX_USRCLK_CFG[4]">GTX1:TX_USRCLK_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[11]">GTX1:DRP45[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_USRCLK_CFG" title="GTX1:TX_USRCLK_CFG[5]">GTX1:TX_USRCLK_CFG[5]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[12]">GTX1:DRP45[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[13]">GTX1:DRP45[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[14]">GTX1:DRP45[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP45" title="GTX1:DRP45[15]">GTX1:DRP45[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[0]">GTX1:DRP46[0]</a><br><a href="#bits-xc6v-GTX-GTX1:RXRECCLK_DLY" title="GTX1:RXRECCLK_DLY[0]">GTX1:RXRECCLK_DLY[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[1]">GTX1:DRP46[1]</a><br><a href="#bits-xc6v-GTX-GTX1:RXRECCLK_DLY" title="GTX1:RXRECCLK_DLY[1]">GTX1:RXRECCLK_DLY[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[2]">GTX1:DRP46[2]</a><br><a href="#bits-xc6v-GTX-GTX1:RXRECCLK_DLY" title="GTX1:RXRECCLK_DLY[2]">GTX1:RXRECCLK_DLY[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[3]">GTX1:DRP46[3]</a><br><a href="#bits-xc6v-GTX-GTX1:RXRECCLK_DLY" title="GTX1:RXRECCLK_DLY[3]">GTX1:RXRECCLK_DLY[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[4]">GTX1:DRP46[4]</a><br><a href="#bits-xc6v-GTX-GTX1:RXRECCLK_DLY" title="GTX1:RXRECCLK_DLY[4]">GTX1:RXRECCLK_DLY[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[5]">GTX1:DRP46[5]</a><br><a href="#bits-xc6v-GTX-GTX1:RXRECCLK_DLY" title="GTX1:RXRECCLK_DLY[5]">GTX1:RXRECCLK_DLY[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[6]">GTX1:DRP46[6]</a><br><a href="#bits-xc6v-GTX-GTX1:RXRECCLK_DLY" title="GTX1:RXRECCLK_DLY[6]">GTX1:RXRECCLK_DLY[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[7]">GTX1:DRP46[7]</a><br><a href="#bits-xc6v-GTX-GTX1:RXRECCLK_DLY" title="GTX1:RXRECCLK_DLY[7]">GTX1:RXRECCLK_DLY[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[8]">GTX1:DRP46[8]</a><br><a href="#bits-xc6v-GTX-GTX1:RXRECCLK_DLY" title="GTX1:RXRECCLK_DLY[8]">GTX1:RXRECCLK_DLY[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[9]">GTX1:DRP46[9]</a><br><a href="#bits-xc6v-GTX-GTX1:RXRECCLK_DLY" title="GTX1:RXRECCLK_DLY[9]">GTX1:RXRECCLK_DLY[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[10]">GTX1:DRP46[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[11]">GTX1:DRP46[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[12]">GTX1:DRP46[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[13]">GTX1:DRP46[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[14]">GTX1:DRP46[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP46" title="GTX1:DRP46[15]">GTX1:DRP46[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[0]">GTX1:DRP47[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TXOUTCLK_DLY" title="GTX1:TXOUTCLK_DLY[0]">GTX1:TXOUTCLK_DLY[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[1]">GTX1:DRP47[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TXOUTCLK_DLY" title="GTX1:TXOUTCLK_DLY[1]">GTX1:TXOUTCLK_DLY[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[2]">GTX1:DRP47[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TXOUTCLK_DLY" title="GTX1:TXOUTCLK_DLY[2]">GTX1:TXOUTCLK_DLY[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[3]">GTX1:DRP47[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TXOUTCLK_DLY" title="GTX1:TXOUTCLK_DLY[3]">GTX1:TXOUTCLK_DLY[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[4]">GTX1:DRP47[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TXOUTCLK_DLY" title="GTX1:TXOUTCLK_DLY[4]">GTX1:TXOUTCLK_DLY[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[5]">GTX1:DRP47[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TXOUTCLK_DLY" title="GTX1:TXOUTCLK_DLY[5]">GTX1:TXOUTCLK_DLY[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[6]">GTX1:DRP47[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TXOUTCLK_DLY" title="GTX1:TXOUTCLK_DLY[6]">GTX1:TXOUTCLK_DLY[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[7]">GTX1:DRP47[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TXOUTCLK_DLY" title="GTX1:TXOUTCLK_DLY[7]">GTX1:TXOUTCLK_DLY[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[8]">GTX1:DRP47[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TXOUTCLK_DLY" title="GTX1:TXOUTCLK_DLY[8]">GTX1:TXOUTCLK_DLY[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[9]">GTX1:DRP47[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TXOUTCLK_DLY" title="GTX1:TXOUTCLK_DLY[9]">GTX1:TXOUTCLK_DLY[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[10]">GTX1:DRP47[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[11]">GTX1:DRP47[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[12]">GTX1:DRP47[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[13]">GTX1:DRP47[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[14]">GTX1:DRP47[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP47" title="GTX1:DRP47[15]">GTX1:DRP47[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 19</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[0]">GTX1:DRP48[0]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX0:REFCLKOUT_DLY" title="IBUFDS_GTX0:REFCLKOUT_DLY[0]">IBUFDS_GTX0:REFCLKOUT_DLY[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[1]">GTX1:DRP48[1]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX0:REFCLKOUT_DLY" title="IBUFDS_GTX0:REFCLKOUT_DLY[1]">IBUFDS_GTX0:REFCLKOUT_DLY[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[2]">GTX1:DRP48[2]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX0:REFCLKOUT_DLY" title="IBUFDS_GTX0:REFCLKOUT_DLY[2]">IBUFDS_GTX0:REFCLKOUT_DLY[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[3]">GTX1:DRP48[3]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX0:REFCLKOUT_DLY" title="IBUFDS_GTX0:REFCLKOUT_DLY[3]">IBUFDS_GTX0:REFCLKOUT_DLY[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[4]">GTX1:DRP48[4]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX0:REFCLKOUT_DLY" title="IBUFDS_GTX0:REFCLKOUT_DLY[4]">IBUFDS_GTX0:REFCLKOUT_DLY[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[5]">GTX1:DRP48[5]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX0:REFCLKOUT_DLY" title="IBUFDS_GTX0:REFCLKOUT_DLY[5]">IBUFDS_GTX0:REFCLKOUT_DLY[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[6]">GTX1:DRP48[6]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX0:REFCLKOUT_DLY" title="IBUFDS_GTX0:REFCLKOUT_DLY[6]">IBUFDS_GTX0:REFCLKOUT_DLY[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[7]">GTX1:DRP48[7]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX0:REFCLKOUT_DLY" title="IBUFDS_GTX0:REFCLKOUT_DLY[7]">IBUFDS_GTX0:REFCLKOUT_DLY[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[8]">GTX1:DRP48[8]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX0:REFCLKOUT_DLY" title="IBUFDS_GTX0:REFCLKOUT_DLY[8]">IBUFDS_GTX0:REFCLKOUT_DLY[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[9]">GTX1:DRP48[9]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX0:REFCLKOUT_DLY" title="IBUFDS_GTX0:REFCLKOUT_DLY[9]">IBUFDS_GTX0:REFCLKOUT_DLY[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[10]">GTX1:DRP48[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[11]">GTX1:DRP48[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[12]">GTX1:DRP48[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[13]">GTX1:DRP48[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[14]">GTX1:DRP48[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP48" title="GTX1:DRP48[15]">GTX1:DRP48[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[0]">GTX1:DRP49[0]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX1:REFCLKOUT_DLY" title="IBUFDS_GTX1:REFCLKOUT_DLY[0]">IBUFDS_GTX1:REFCLKOUT_DLY[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[1]">GTX1:DRP49[1]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX1:REFCLKOUT_DLY" title="IBUFDS_GTX1:REFCLKOUT_DLY[1]">IBUFDS_GTX1:REFCLKOUT_DLY[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[2]">GTX1:DRP49[2]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX1:REFCLKOUT_DLY" title="IBUFDS_GTX1:REFCLKOUT_DLY[2]">IBUFDS_GTX1:REFCLKOUT_DLY[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[3]">GTX1:DRP49[3]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX1:REFCLKOUT_DLY" title="IBUFDS_GTX1:REFCLKOUT_DLY[3]">IBUFDS_GTX1:REFCLKOUT_DLY[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[4]">GTX1:DRP49[4]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX1:REFCLKOUT_DLY" title="IBUFDS_GTX1:REFCLKOUT_DLY[4]">IBUFDS_GTX1:REFCLKOUT_DLY[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[5]">GTX1:DRP49[5]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX1:REFCLKOUT_DLY" title="IBUFDS_GTX1:REFCLKOUT_DLY[5]">IBUFDS_GTX1:REFCLKOUT_DLY[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[6]">GTX1:DRP49[6]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX1:REFCLKOUT_DLY" title="IBUFDS_GTX1:REFCLKOUT_DLY[6]">IBUFDS_GTX1:REFCLKOUT_DLY[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[7]">GTX1:DRP49[7]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX1:REFCLKOUT_DLY" title="IBUFDS_GTX1:REFCLKOUT_DLY[7]">IBUFDS_GTX1:REFCLKOUT_DLY[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[8]">GTX1:DRP49[8]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX1:REFCLKOUT_DLY" title="IBUFDS_GTX1:REFCLKOUT_DLY[8]">IBUFDS_GTX1:REFCLKOUT_DLY[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[9]">GTX1:DRP49[9]</a><br><a href="#bits-xc6v-GTX-IBUFDS_GTX1:REFCLKOUT_DLY" title="IBUFDS_GTX1:REFCLKOUT_DLY[9]">IBUFDS_GTX1:REFCLKOUT_DLY[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[10]">GTX1:DRP49[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[11]">GTX1:DRP49[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[12]">GTX1:DRP49[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[13]">GTX1:DRP49[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[14]">GTX1:DRP49[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP49" title="GTX1:DRP49[15]">GTX1:DRP49[15]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[0]">GTX1:DRP4A[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[1]">GTX1:DRP4A[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[2]">GTX1:DRP4A[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[3]">GTX1:DRP4A[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[4]">GTX1:DRP4A[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[5]">GTX1:DRP4A[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[6]">GTX1:DRP4A[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[7]">GTX1:DRP4A[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[8]">GTX1:DRP4A[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[9]">GTX1:DRP4A[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[10]">GTX1:DRP4A[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[11]">GTX1:DRP4A[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[12]">GTX1:DRP4A[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[13]">GTX1:DRP4A[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[14]">GTX1:DRP4A[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4A" title="GTX1:DRP4A[15]">GTX1:DRP4A[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[0]">GTX1:DRP4B[0]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_MONSEL" title="GTX1:RX_DLYALIGN_MONSEL[0]">GTX1:RX_DLYALIGN_MONSEL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[1]">GTX1:DRP4B[1]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_MONSEL" title="GTX1:RX_DLYALIGN_MONSEL[1]">GTX1:RX_DLYALIGN_MONSEL[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[2]">GTX1:DRP4B[2]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_MONSEL" title="GTX1:RX_DLYALIGN_MONSEL[2]">GTX1:RX_DLYALIGN_MONSEL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[3]">GTX1:DRP4B[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_MONSEL" title="GTX1:TX_DLYALIGN_MONSEL[0]">GTX1:TX_DLYALIGN_MONSEL[0]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[4]">GTX1:DRP4B[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_MONSEL" title="GTX1:TX_DLYALIGN_MONSEL[1]">GTX1:TX_DLYALIGN_MONSEL[1]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[5]">GTX1:DRP4B[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_MONSEL" title="GTX1:TX_DLYALIGN_MONSEL[2]">GTX1:TX_DLYALIGN_MONSEL[2]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[6]">GTX1:DRP4B[6]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_EDGESET" title="GTX1:RX_DLYALIGN_EDGESET[0]">GTX1:RX_DLYALIGN_EDGESET[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[7]">GTX1:DRP4B[7]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_EDGESET" title="GTX1:RX_DLYALIGN_EDGESET[1]">GTX1:RX_DLYALIGN_EDGESET[1]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[8]">GTX1:DRP4B[8]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_EDGESET" title="GTX1:RX_DLYALIGN_EDGESET[2]">GTX1:RX_DLYALIGN_EDGESET[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[9]">GTX1:DRP4B[9]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_EDGESET" title="GTX1:RX_DLYALIGN_EDGESET[3]">GTX1:RX_DLYALIGN_EDGESET[3]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[10]">GTX1:DRP4B[10]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_EDGESET" title="GTX1:RX_DLYALIGN_EDGESET[4]">GTX1:RX_DLYALIGN_EDGESET[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[11]">GTX1:DRP4B[11]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[12]">GTX1:DRP4B[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[13]">GTX1:DRP4B[13]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[14]">GTX1:DRP4B[14]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_EN_REALIGN_RESET_BUF2" title="GTX1:RX_EN_REALIGN_RESET_BUF2">GTX1:RX_EN_REALIGN_RESET_BUF2</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4B" title="GTX1:DRP4B[15]">GTX1:DRP4B[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[0]">GTX1:DRP4C[0]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_CTRINC" title="GTX1:TX_DLYALIGN_CTRINC[0]">GTX1:TX_DLYALIGN_CTRINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[1]">GTX1:DRP4C[1]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_CTRINC" title="GTX1:TX_DLYALIGN_CTRINC[1]">GTX1:TX_DLYALIGN_CTRINC[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[2]">GTX1:DRP4C[2]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_CTRINC" title="GTX1:TX_DLYALIGN_CTRINC[2]">GTX1:TX_DLYALIGN_CTRINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[3]">GTX1:DRP4C[3]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_CTRINC" title="GTX1:TX_DLYALIGN_CTRINC[3]">GTX1:TX_DLYALIGN_CTRINC[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[4]">GTX1:DRP4C[4]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_LPFINC" title="GTX1:TX_DLYALIGN_LPFINC[0]">GTX1:TX_DLYALIGN_LPFINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[5]">GTX1:DRP4C[5]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_LPFINC" title="GTX1:TX_DLYALIGN_LPFINC[1]">GTX1:TX_DLYALIGN_LPFINC[1]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[6]">GTX1:DRP4C[6]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_LPFINC" title="GTX1:TX_DLYALIGN_LPFINC[2]">GTX1:TX_DLYALIGN_LPFINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[7]">GTX1:DRP4C[7]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_LPFINC" title="GTX1:TX_DLYALIGN_LPFINC[3]">GTX1:TX_DLYALIGN_LPFINC[3]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[8]">GTX1:DRP4C[8]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_OVRDSETTING" title="GTX1:TX_DLYALIGN_OVRDSETTING[0]">GTX1:TX_DLYALIGN_OVRDSETTING[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[9]">GTX1:DRP4C[9]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_OVRDSETTING" title="GTX1:TX_DLYALIGN_OVRDSETTING[1]">GTX1:TX_DLYALIGN_OVRDSETTING[1]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[10]">GTX1:DRP4C[10]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_OVRDSETTING" title="GTX1:TX_DLYALIGN_OVRDSETTING[2]">GTX1:TX_DLYALIGN_OVRDSETTING[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[11]">GTX1:DRP4C[11]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_OVRDSETTING" title="GTX1:TX_DLYALIGN_OVRDSETTING[3]">GTX1:TX_DLYALIGN_OVRDSETTING[3]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[12]">GTX1:DRP4C[12]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_OVRDSETTING" title="GTX1:TX_DLYALIGN_OVRDSETTING[4]">GTX1:TX_DLYALIGN_OVRDSETTING[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[13]">GTX1:DRP4C[13]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_OVRDSETTING" title="GTX1:TX_DLYALIGN_OVRDSETTING[5]">GTX1:TX_DLYALIGN_OVRDSETTING[5]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[14]">GTX1:DRP4C[14]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_OVRDSETTING" title="GTX1:TX_DLYALIGN_OVRDSETTING[6]">GTX1:TX_DLYALIGN_OVRDSETTING[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4C" title="GTX1:DRP4C[15]">GTX1:DRP4C[15]</a><br><a href="#bits-xc6v-GTX-GTX1:TX_DLYALIGN_OVRDSETTING" title="GTX1:TX_DLYALIGN_OVRDSETTING[7]">GTX1:TX_DLYALIGN_OVRDSETTING[7]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[0]">GTX1:DRP4D[0]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_CTRINC" title="GTX1:RX_DLYALIGN_CTRINC[0]">GTX1:RX_DLYALIGN_CTRINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[1]">GTX1:DRP4D[1]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_CTRINC" title="GTX1:RX_DLYALIGN_CTRINC[1]">GTX1:RX_DLYALIGN_CTRINC[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[2]">GTX1:DRP4D[2]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_CTRINC" title="GTX1:RX_DLYALIGN_CTRINC[2]">GTX1:RX_DLYALIGN_CTRINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[3]">GTX1:DRP4D[3]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_CTRINC" title="GTX1:RX_DLYALIGN_CTRINC[3]">GTX1:RX_DLYALIGN_CTRINC[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[4]">GTX1:DRP4D[4]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_LPFINC" title="GTX1:RX_DLYALIGN_LPFINC[0]">GTX1:RX_DLYALIGN_LPFINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[5]">GTX1:DRP4D[5]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_LPFINC" title="GTX1:RX_DLYALIGN_LPFINC[1]">GTX1:RX_DLYALIGN_LPFINC[1]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[6]">GTX1:DRP4D[6]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_LPFINC" title="GTX1:RX_DLYALIGN_LPFINC[2]">GTX1:RX_DLYALIGN_LPFINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[7]">GTX1:DRP4D[7]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_LPFINC" title="GTX1:RX_DLYALIGN_LPFINC[3]">GTX1:RX_DLYALIGN_LPFINC[3]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[8]">GTX1:DRP4D[8]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_OVRDSETTING" title="GTX1:RX_DLYALIGN_OVRDSETTING[0]">GTX1:RX_DLYALIGN_OVRDSETTING[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[9]">GTX1:DRP4D[9]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_OVRDSETTING" title="GTX1:RX_DLYALIGN_OVRDSETTING[1]">GTX1:RX_DLYALIGN_OVRDSETTING[1]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[10]">GTX1:DRP4D[10]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_OVRDSETTING" title="GTX1:RX_DLYALIGN_OVRDSETTING[2]">GTX1:RX_DLYALIGN_OVRDSETTING[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[11]">GTX1:DRP4D[11]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_OVRDSETTING" title="GTX1:RX_DLYALIGN_OVRDSETTING[3]">GTX1:RX_DLYALIGN_OVRDSETTING[3]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[12]">GTX1:DRP4D[12]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_OVRDSETTING" title="GTX1:RX_DLYALIGN_OVRDSETTING[4]">GTX1:RX_DLYALIGN_OVRDSETTING[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[13]">GTX1:DRP4D[13]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_OVRDSETTING" title="GTX1:RX_DLYALIGN_OVRDSETTING[5]">GTX1:RX_DLYALIGN_OVRDSETTING[5]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[14]">GTX1:DRP4D[14]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_OVRDSETTING" title="GTX1:RX_DLYALIGN_OVRDSETTING[6]">GTX1:RX_DLYALIGN_OVRDSETTING[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4D" title="GTX1:DRP4D[15]">GTX1:DRP4D[15]</a><br><a href="#bits-xc6v-GTX-GTX1:RX_DLYALIGN_OVRDSETTING" title="GTX1:RX_DLYALIGN_OVRDSETTING[7]">GTX1:RX_DLYALIGN_OVRDSETTING[7]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[0]">GTX1:DRP4E[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[1]">GTX1:DRP4E[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[2]">GTX1:DRP4E[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[3]">GTX1:DRP4E[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[4]">GTX1:DRP4E[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[5]">GTX1:DRP4E[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[6]">GTX1:DRP4E[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[7]">GTX1:DRP4E[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[8]">GTX1:DRP4E[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[9]">GTX1:DRP4E[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[10]">GTX1:DRP4E[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[11]">GTX1:DRP4E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[12]">GTX1:DRP4E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[13]">GTX1:DRP4E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[14]">GTX1:DRP4E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4E" title="GTX1:DRP4E[15]">GTX1:DRP4E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[0]">GTX1:DRP4F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[1]">GTX1:DRP4F[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[2]">GTX1:DRP4F[2]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[3]">GTX1:DRP4F[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[4]">GTX1:DRP4F[4]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[5]">GTX1:DRP4F[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[6]">GTX1:DRP4F[6]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[7]">GTX1:DRP4F[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[8]">GTX1:DRP4F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[9]">GTX1:DRP4F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[10]">GTX1:DRP4F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[11]">GTX1:DRP4F[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[12]">GTX1:DRP4F[12]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[13]">GTX1:DRP4F[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[14]">GTX1:DRP4F[14]</a></td><td><a href="#bits-xc6v-GTX-GTX1:DRP4F" title="GTX1:DRP4F[15]">GTX1:DRP4F[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 20</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[0]">GTX2:DRP00[0]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[0]">GTX2:PMA_RX_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[1]">GTX2:DRP00[1]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[1]">GTX2:PMA_RX_CFG[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[2]">GTX2:DRP00[2]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[2]">GTX2:PMA_RX_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[3]">GTX2:DRP00[3]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[3]">GTX2:PMA_RX_CFG[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[4]">GTX2:DRP00[4]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[4]">GTX2:PMA_RX_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[5]">GTX2:DRP00[5]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[5]">GTX2:PMA_RX_CFG[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[6]">GTX2:DRP00[6]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[6]">GTX2:PMA_RX_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[7]">GTX2:DRP00[7]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[7]">GTX2:PMA_RX_CFG[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[8]">GTX2:DRP00[8]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[8]">GTX2:PMA_RX_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[9]">GTX2:DRP00[9]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[9]">GTX2:PMA_RX_CFG[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[10]">GTX2:DRP00[10]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[10]">GTX2:PMA_RX_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[11]">GTX2:DRP00[11]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[11]">GTX2:PMA_RX_CFG[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[12]">GTX2:DRP00[12]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[12]">GTX2:PMA_RX_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[13]">GTX2:DRP00[13]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[13]">GTX2:PMA_RX_CFG[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[14]">GTX2:DRP00[14]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[14]">GTX2:PMA_RX_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP00" title="GTX2:DRP00[15]">GTX2:DRP00[15]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[15]">GTX2:PMA_RX_CFG[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[0]">GTX2:DRP01[0]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[16]">GTX2:PMA_RX_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[1]">GTX2:DRP01[1]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[17]">GTX2:PMA_RX_CFG[17]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[2]">GTX2:DRP01[2]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[18]">GTX2:PMA_RX_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[3]">GTX2:DRP01[3]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[19]">GTX2:PMA_RX_CFG[19]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[4]">GTX2:DRP01[4]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[20]">GTX2:PMA_RX_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[5]">GTX2:DRP01[5]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[21]">GTX2:PMA_RX_CFG[21]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[6]">GTX2:DRP01[6]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[22]">GTX2:PMA_RX_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[7]">GTX2:DRP01[7]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[23]">GTX2:PMA_RX_CFG[23]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[8]">GTX2:DRP01[8]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RX_CFG" title="GTX2:PMA_RX_CFG[24]">GTX2:PMA_RX_CFG[24]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[9]">GTX2:DRP01[9]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RXSYNC_CFG" title="GTX2:PMA_RXSYNC_CFG[0]">GTX2:PMA_RXSYNC_CFG[0]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[10]">GTX2:DRP01[10]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RXSYNC_CFG" title="GTX2:PMA_RXSYNC_CFG[1]">GTX2:PMA_RXSYNC_CFG[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[11]">GTX2:DRP01[11]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RXSYNC_CFG" title="GTX2:PMA_RXSYNC_CFG[2]">GTX2:PMA_RXSYNC_CFG[2]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[12]">GTX2:DRP01[12]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RXSYNC_CFG" title="GTX2:PMA_RXSYNC_CFG[3]">GTX2:PMA_RXSYNC_CFG[3]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[13]">GTX2:DRP01[13]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RXSYNC_CFG" title="GTX2:PMA_RXSYNC_CFG[4]">GTX2:PMA_RXSYNC_CFG[4]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[14]">GTX2:DRP01[14]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RXSYNC_CFG" title="GTX2:PMA_RXSYNC_CFG[5]">GTX2:PMA_RXSYNC_CFG[5]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP01" title="GTX2:DRP01[15]">GTX2:DRP01[15]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_RXSYNC_CFG" title="GTX2:PMA_RXSYNC_CFG[6]">GTX2:PMA_RXSYNC_CFG[6]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[0]">GTX2:DRP02[0]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[0]">GTX2:RXUSRCLK_DLY[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[1]">GTX2:DRP02[1]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[1]">GTX2:RXUSRCLK_DLY[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[2]">GTX2:DRP02[2]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[2]">GTX2:RXUSRCLK_DLY[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[3]">GTX2:DRP02[3]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[3]">GTX2:RXUSRCLK_DLY[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[4]">GTX2:DRP02[4]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[4]">GTX2:RXUSRCLK_DLY[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[5]">GTX2:DRP02[5]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[5]">GTX2:RXUSRCLK_DLY[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[6]">GTX2:DRP02[6]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[6]">GTX2:RXUSRCLK_DLY[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[7]">GTX2:DRP02[7]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[7]">GTX2:RXUSRCLK_DLY[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[8]">GTX2:DRP02[8]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[8]">GTX2:RXUSRCLK_DLY[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[9]">GTX2:DRP02[9]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[9]">GTX2:RXUSRCLK_DLY[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[10]">GTX2:DRP02[10]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[10]">GTX2:RXUSRCLK_DLY[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[11]">GTX2:DRP02[11]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[11]">GTX2:RXUSRCLK_DLY[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[12]">GTX2:DRP02[12]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[12]">GTX2:RXUSRCLK_DLY[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[13]">GTX2:DRP02[13]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[13]">GTX2:RXUSRCLK_DLY[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[14]">GTX2:DRP02[14]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[14]">GTX2:RXUSRCLK_DLY[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP02" title="GTX2:DRP02[15]">GTX2:DRP02[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RXUSRCLK_DLY" title="GTX2:RXUSRCLK_DLY[15]">GTX2:RXUSRCLK_DLY[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[0]">GTX2:BIAS_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[0]">GTX2:DRP03[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[1]">GTX2:BIAS_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[1]">GTX2:DRP03[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[2]">GTX2:BIAS_CFG[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[2]">GTX2:DRP03[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[3]">GTX2:BIAS_CFG[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[3]">GTX2:DRP03[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[4]">GTX2:BIAS_CFG[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[4]">GTX2:DRP03[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[5]">GTX2:BIAS_CFG[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[5]">GTX2:DRP03[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[6]">GTX2:BIAS_CFG[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[6]">GTX2:DRP03[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[7]">GTX2:BIAS_CFG[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[7]">GTX2:DRP03[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[8]">GTX2:BIAS_CFG[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[8]">GTX2:DRP03[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[9]">GTX2:BIAS_CFG[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[9]">GTX2:DRP03[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[10]">GTX2:BIAS_CFG[10]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[10]">GTX2:DRP03[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[11]">GTX2:BIAS_CFG[11]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[11]">GTX2:DRP03[11]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[12]">GTX2:BIAS_CFG[12]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[12]">GTX2:DRP03[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[13]">GTX2:BIAS_CFG[13]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[13]">GTX2:DRP03[13]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[14]">GTX2:BIAS_CFG[14]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[14]">GTX2:DRP03[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[15]">GTX2:BIAS_CFG[15]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP03" title="GTX2:DRP03[15]">GTX2:DRP03[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_1" title="GTX2:CHAN_BOND_SEQ_1_1[0]">GTX2:CHAN_BOND_SEQ_1_1[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[0]">GTX2:DRP04[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_1" title="GTX2:CHAN_BOND_SEQ_1_1[1]">GTX2:CHAN_BOND_SEQ_1_1[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[1]">GTX2:DRP04[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_1" title="GTX2:CHAN_BOND_SEQ_1_1[2]">GTX2:CHAN_BOND_SEQ_1_1[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[2]">GTX2:DRP04[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_1" title="GTX2:CHAN_BOND_SEQ_1_1[3]">GTX2:CHAN_BOND_SEQ_1_1[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[3]">GTX2:DRP04[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_1" title="GTX2:CHAN_BOND_SEQ_1_1[4]">GTX2:CHAN_BOND_SEQ_1_1[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[4]">GTX2:DRP04[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_1" title="GTX2:CHAN_BOND_SEQ_1_1[5]">GTX2:CHAN_BOND_SEQ_1_1[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[5]">GTX2:DRP04[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_1" title="GTX2:CHAN_BOND_SEQ_1_1[6]">GTX2:CHAN_BOND_SEQ_1_1[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[6]">GTX2:DRP04[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_1" title="GTX2:CHAN_BOND_SEQ_1_1[7]">GTX2:CHAN_BOND_SEQ_1_1[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[7]">GTX2:DRP04[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_1" title="GTX2:CHAN_BOND_SEQ_1_1[8]">GTX2:CHAN_BOND_SEQ_1_1[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[8]">GTX2:DRP04[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_1" title="GTX2:CHAN_BOND_SEQ_1_1[9]">GTX2:CHAN_BOND_SEQ_1_1[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[9]">GTX2:DRP04[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_ENABLE" title="GTX2:CHAN_BOND_SEQ_1_ENABLE[0]">GTX2:CHAN_BOND_SEQ_1_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[10]">GTX2:DRP04[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_ENABLE" title="GTX2:CHAN_BOND_SEQ_1_ENABLE[1]">GTX2:CHAN_BOND_SEQ_1_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[11]">GTX2:DRP04[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_ENABLE" title="GTX2:CHAN_BOND_SEQ_1_ENABLE[2]">GTX2:CHAN_BOND_SEQ_1_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[12]">GTX2:DRP04[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_ENABLE" title="GTX2:CHAN_BOND_SEQ_1_ENABLE[3]">GTX2:CHAN_BOND_SEQ_1_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[13]">GTX2:DRP04[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[14]">GTX2:DRP04[14]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_BUFFER_USE" title="GTX2:RX_BUFFER_USE">GTX2:RX_BUFFER_USE</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP04" title="GTX2:DRP04[15]">GTX2:DRP04[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_LOSS_OF_SYNC_FSM" title="GTX2:RX_LOSS_OF_SYNC_FSM">GTX2:RX_LOSS_OF_SYNC_FSM</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_2" title="GTX2:CHAN_BOND_SEQ_1_2[0]">GTX2:CHAN_BOND_SEQ_1_2[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[0]">GTX2:DRP05[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_2" title="GTX2:CHAN_BOND_SEQ_1_2[1]">GTX2:CHAN_BOND_SEQ_1_2[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[1]">GTX2:DRP05[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_2" title="GTX2:CHAN_BOND_SEQ_1_2[2]">GTX2:CHAN_BOND_SEQ_1_2[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[2]">GTX2:DRP05[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_2" title="GTX2:CHAN_BOND_SEQ_1_2[3]">GTX2:CHAN_BOND_SEQ_1_2[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[3]">GTX2:DRP05[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_2" title="GTX2:CHAN_BOND_SEQ_1_2[4]">GTX2:CHAN_BOND_SEQ_1_2[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[4]">GTX2:DRP05[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_2" title="GTX2:CHAN_BOND_SEQ_1_2[5]">GTX2:CHAN_BOND_SEQ_1_2[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[5]">GTX2:DRP05[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_2" title="GTX2:CHAN_BOND_SEQ_1_2[6]">GTX2:CHAN_BOND_SEQ_1_2[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[6]">GTX2:DRP05[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_2" title="GTX2:CHAN_BOND_SEQ_1_2[7]">GTX2:CHAN_BOND_SEQ_1_2[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[7]">GTX2:DRP05[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_2" title="GTX2:CHAN_BOND_SEQ_1_2[8]">GTX2:CHAN_BOND_SEQ_1_2[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[8]">GTX2:DRP05[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_2" title="GTX2:CHAN_BOND_SEQ_1_2[9]">GTX2:CHAN_BOND_SEQ_1_2[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[9]">GTX2:DRP05[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_1_MAX_SKEW" title="GTX2:CHAN_BOND_1_MAX_SKEW[0]">GTX2:CHAN_BOND_1_MAX_SKEW[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[10]">GTX2:DRP05[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_1_MAX_SKEW" title="GTX2:CHAN_BOND_1_MAX_SKEW[1]">GTX2:CHAN_BOND_1_MAX_SKEW[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[11]">GTX2:DRP05[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_1_MAX_SKEW" title="GTX2:CHAN_BOND_1_MAX_SKEW[2]">GTX2:CHAN_BOND_1_MAX_SKEW[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[12]">GTX2:DRP05[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_1_MAX_SKEW" title="GTX2:CHAN_BOND_1_MAX_SKEW[3]">GTX2:CHAN_BOND_1_MAX_SKEW[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[13]">GTX2:DRP05[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[14]">GTX2:DRP05[14]</a><br><a href="#bits-xc6v-GTX-GTX2:INV.RXUSRCLK" title="~GTX2:INV.RXUSRCLK">~GTX2:INV.RXUSRCLK</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP05" title="GTX2:DRP05[15]">GTX2:DRP05[15]</a><br><a href="#bits-xc6v-GTX-GTX2:INV.RXUSRCLK2" title="~GTX2:INV.RXUSRCLK2">~GTX2:INV.RXUSRCLK2</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_3" title="GTX2:CHAN_BOND_SEQ_1_3[0]">GTX2:CHAN_BOND_SEQ_1_3[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[0]">GTX2:DRP06[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_3" title="GTX2:CHAN_BOND_SEQ_1_3[1]">GTX2:CHAN_BOND_SEQ_1_3[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[1]">GTX2:DRP06[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_3" title="GTX2:CHAN_BOND_SEQ_1_3[2]">GTX2:CHAN_BOND_SEQ_1_3[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[2]">GTX2:DRP06[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_3" title="GTX2:CHAN_BOND_SEQ_1_3[3]">GTX2:CHAN_BOND_SEQ_1_3[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[3]">GTX2:DRP06[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_3" title="GTX2:CHAN_BOND_SEQ_1_3[4]">GTX2:CHAN_BOND_SEQ_1_3[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[4]">GTX2:DRP06[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_3" title="GTX2:CHAN_BOND_SEQ_1_3[5]">GTX2:CHAN_BOND_SEQ_1_3[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[5]">GTX2:DRP06[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_3" title="GTX2:CHAN_BOND_SEQ_1_3[6]">GTX2:CHAN_BOND_SEQ_1_3[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[6]">GTX2:DRP06[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_3" title="GTX2:CHAN_BOND_SEQ_1_3[7]">GTX2:CHAN_BOND_SEQ_1_3[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[7]">GTX2:DRP06[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_3" title="GTX2:CHAN_BOND_SEQ_1_3[8]">GTX2:CHAN_BOND_SEQ_1_3[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[8]">GTX2:DRP06[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_3" title="GTX2:CHAN_BOND_SEQ_1_3[9]">GTX2:CHAN_BOND_SEQ_1_3[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[9]">GTX2:DRP06[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[10]">GTX2:DRP06[10]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_LOS_THRESHOLD" title="GTX2:RX_LOS_THRESHOLD[0]">GTX2:RX_LOS_THRESHOLD[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[11]">GTX2:DRP06[11]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_LOS_THRESHOLD" title="GTX2:RX_LOS_THRESHOLD[1]">GTX2:RX_LOS_THRESHOLD[1]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[12]">GTX2:DRP06[12]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_LOS_THRESHOLD" title="GTX2:RX_LOS_THRESHOLD[2]">GTX2:RX_LOS_THRESHOLD[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[13]">GTX2:DRP06[13]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_LOS_INVALID_INCR" title="GTX2:RX_LOS_INVALID_INCR[0]">GTX2:RX_LOS_INVALID_INCR[0]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[14]">GTX2:DRP06[14]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_LOS_INVALID_INCR" title="GTX2:RX_LOS_INVALID_INCR[1]">GTX2:RX_LOS_INVALID_INCR[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP06" title="GTX2:DRP06[15]">GTX2:DRP06[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_LOS_INVALID_INCR" title="GTX2:RX_LOS_INVALID_INCR[2]">GTX2:RX_LOS_INVALID_INCR[2]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_4" title="GTX2:CHAN_BOND_SEQ_1_4[0]">GTX2:CHAN_BOND_SEQ_1_4[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[0]">GTX2:DRP07[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_4" title="GTX2:CHAN_BOND_SEQ_1_4[1]">GTX2:CHAN_BOND_SEQ_1_4[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[1]">GTX2:DRP07[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_4" title="GTX2:CHAN_BOND_SEQ_1_4[2]">GTX2:CHAN_BOND_SEQ_1_4[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[2]">GTX2:DRP07[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_4" title="GTX2:CHAN_BOND_SEQ_1_4[3]">GTX2:CHAN_BOND_SEQ_1_4[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[3]">GTX2:DRP07[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_4" title="GTX2:CHAN_BOND_SEQ_1_4[4]">GTX2:CHAN_BOND_SEQ_1_4[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[4]">GTX2:DRP07[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_4" title="GTX2:CHAN_BOND_SEQ_1_4[5]">GTX2:CHAN_BOND_SEQ_1_4[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[5]">GTX2:DRP07[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_4" title="GTX2:CHAN_BOND_SEQ_1_4[6]">GTX2:CHAN_BOND_SEQ_1_4[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[6]">GTX2:DRP07[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_4" title="GTX2:CHAN_BOND_SEQ_1_4[7]">GTX2:CHAN_BOND_SEQ_1_4[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[7]">GTX2:DRP07[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_4" title="GTX2:CHAN_BOND_SEQ_1_4[8]">GTX2:CHAN_BOND_SEQ_1_4[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[8]">GTX2:DRP07[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_4" title="GTX2:CHAN_BOND_SEQ_1_4[9]">GTX2:CHAN_BOND_SEQ_1_4[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[9]">GTX2:DRP07[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_LEN" title="GTX2:CHAN_BOND_SEQ_LEN[0]">GTX2:CHAN_BOND_SEQ_LEN[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[10]">GTX2:DRP07[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_LEN" title="GTX2:CHAN_BOND_SEQ_LEN[1]">GTX2:CHAN_BOND_SEQ_LEN[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[11]">GTX2:DRP07[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[12]">GTX2:DRP07[12]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_IDLE_LO_CNT" title="GTX2:RX_IDLE_LO_CNT[0]">GTX2:RX_IDLE_LO_CNT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[13]">GTX2:DRP07[13]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_IDLE_LO_CNT" title="GTX2:RX_IDLE_LO_CNT[1]">GTX2:RX_IDLE_LO_CNT[1]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[14]">GTX2:DRP07[14]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_IDLE_LO_CNT" title="GTX2:RX_IDLE_LO_CNT[2]">GTX2:RX_IDLE_LO_CNT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP07" title="GTX2:DRP07[15]">GTX2:DRP07[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_IDLE_LO_CNT" title="GTX2:RX_IDLE_LO_CNT[3]">GTX2:RX_IDLE_LO_CNT[3]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 21</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_1" title="GTX2:CHAN_BOND_SEQ_2_1[0]">GTX2:CHAN_BOND_SEQ_2_1[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[0]">GTX2:DRP08[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_1" title="GTX2:CHAN_BOND_SEQ_2_1[1]">GTX2:CHAN_BOND_SEQ_2_1[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[1]">GTX2:DRP08[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_1" title="GTX2:CHAN_BOND_SEQ_2_1[2]">GTX2:CHAN_BOND_SEQ_2_1[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[2]">GTX2:DRP08[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_1" title="GTX2:CHAN_BOND_SEQ_2_1[3]">GTX2:CHAN_BOND_SEQ_2_1[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[3]">GTX2:DRP08[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_1" title="GTX2:CHAN_BOND_SEQ_2_1[4]">GTX2:CHAN_BOND_SEQ_2_1[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[4]">GTX2:DRP08[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_1" title="GTX2:CHAN_BOND_SEQ_2_1[5]">GTX2:CHAN_BOND_SEQ_2_1[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[5]">GTX2:DRP08[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_1" title="GTX2:CHAN_BOND_SEQ_2_1[6]">GTX2:CHAN_BOND_SEQ_2_1[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[6]">GTX2:DRP08[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_1" title="GTX2:CHAN_BOND_SEQ_2_1[7]">GTX2:CHAN_BOND_SEQ_2_1[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[7]">GTX2:DRP08[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_1" title="GTX2:CHAN_BOND_SEQ_2_1[8]">GTX2:CHAN_BOND_SEQ_2_1[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[8]">GTX2:DRP08[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_1" title="GTX2:CHAN_BOND_SEQ_2_1[9]">GTX2:CHAN_BOND_SEQ_2_1[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[9]">GTX2:DRP08[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_ENABLE" title="GTX2:CHAN_BOND_SEQ_2_ENABLE[0]">GTX2:CHAN_BOND_SEQ_2_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[10]">GTX2:DRP08[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_ENABLE" title="GTX2:CHAN_BOND_SEQ_2_ENABLE[1]">GTX2:CHAN_BOND_SEQ_2_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[11]">GTX2:DRP08[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_ENABLE" title="GTX2:CHAN_BOND_SEQ_2_ENABLE[2]">GTX2:CHAN_BOND_SEQ_2_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[12]">GTX2:DRP08[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_ENABLE" title="GTX2:CHAN_BOND_SEQ_2_ENABLE[3]">GTX2:CHAN_BOND_SEQ_2_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[13]">GTX2:DRP08[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[14]">GTX2:DRP08[14]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EN_REALIGN_RESET_BUF" title="GTX2:RX_EN_REALIGN_RESET_BUF">GTX2:RX_EN_REALIGN_RESET_BUF</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP08" title="GTX2:DRP08[15]">GTX2:DRP08[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EN_RATE_RESET_BUF" title="GTX2:RX_EN_RATE_RESET_BUF">GTX2:RX_EN_RATE_RESET_BUF</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_2" title="GTX2:CHAN_BOND_SEQ_2_2[0]">GTX2:CHAN_BOND_SEQ_2_2[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[0]">GTX2:DRP09[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_2" title="GTX2:CHAN_BOND_SEQ_2_2[1]">GTX2:CHAN_BOND_SEQ_2_2[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[1]">GTX2:DRP09[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_2" title="GTX2:CHAN_BOND_SEQ_2_2[2]">GTX2:CHAN_BOND_SEQ_2_2[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[2]">GTX2:DRP09[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_2" title="GTX2:CHAN_BOND_SEQ_2_2[3]">GTX2:CHAN_BOND_SEQ_2_2[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[3]">GTX2:DRP09[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_2" title="GTX2:CHAN_BOND_SEQ_2_2[4]">GTX2:CHAN_BOND_SEQ_2_2[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[4]">GTX2:DRP09[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_2" title="GTX2:CHAN_BOND_SEQ_2_2[5]">GTX2:CHAN_BOND_SEQ_2_2[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[5]">GTX2:DRP09[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_2" title="GTX2:CHAN_BOND_SEQ_2_2[6]">GTX2:CHAN_BOND_SEQ_2_2[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[6]">GTX2:DRP09[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_2" title="GTX2:CHAN_BOND_SEQ_2_2[7]">GTX2:CHAN_BOND_SEQ_2_2[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[7]">GTX2:DRP09[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_2" title="GTX2:CHAN_BOND_SEQ_2_2[8]">GTX2:CHAN_BOND_SEQ_2_2[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[8]">GTX2:DRP09[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_2" title="GTX2:CHAN_BOND_SEQ_2_2[9]">GTX2:CHAN_BOND_SEQ_2_2[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[9]">GTX2:DRP09[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_2_MAX_SKEW" title="GTX2:CHAN_BOND_2_MAX_SKEW[0]">GTX2:CHAN_BOND_2_MAX_SKEW[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[10]">GTX2:DRP09[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_2_MAX_SKEW" title="GTX2:CHAN_BOND_2_MAX_SKEW[1]">GTX2:CHAN_BOND_2_MAX_SKEW[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[11]">GTX2:DRP09[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_2_MAX_SKEW" title="GTX2:CHAN_BOND_2_MAX_SKEW[2]">GTX2:CHAN_BOND_2_MAX_SKEW[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[12]">GTX2:DRP09[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_2_MAX_SKEW" title="GTX2:CHAN_BOND_2_MAX_SKEW[3]">GTX2:CHAN_BOND_2_MAX_SKEW[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[13]">GTX2:DRP09[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_KEEP_ALIGN" title="GTX2:CHAN_BOND_KEEP_ALIGN">GTX2:CHAN_BOND_KEEP_ALIGN</a><br><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[14]">GTX2:DRP09[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP09" title="GTX2:DRP09[15]">GTX2:DRP09[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EN_MODE_RESET_BUF" title="GTX2:RX_EN_MODE_RESET_BUF">GTX2:RX_EN_MODE_RESET_BUF</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_3" title="GTX2:CHAN_BOND_SEQ_2_3[0]">GTX2:CHAN_BOND_SEQ_2_3[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[0]">GTX2:DRP0A[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_3" title="GTX2:CHAN_BOND_SEQ_2_3[1]">GTX2:CHAN_BOND_SEQ_2_3[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[1]">GTX2:DRP0A[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_3" title="GTX2:CHAN_BOND_SEQ_2_3[2]">GTX2:CHAN_BOND_SEQ_2_3[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[2]">GTX2:DRP0A[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_3" title="GTX2:CHAN_BOND_SEQ_2_3[3]">GTX2:CHAN_BOND_SEQ_2_3[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[3]">GTX2:DRP0A[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_3" title="GTX2:CHAN_BOND_SEQ_2_3[4]">GTX2:CHAN_BOND_SEQ_2_3[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[4]">GTX2:DRP0A[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_3" title="GTX2:CHAN_BOND_SEQ_2_3[5]">GTX2:CHAN_BOND_SEQ_2_3[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[5]">GTX2:DRP0A[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_3" title="GTX2:CHAN_BOND_SEQ_2_3[6]">GTX2:CHAN_BOND_SEQ_2_3[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[6]">GTX2:DRP0A[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_3" title="GTX2:CHAN_BOND_SEQ_2_3[7]">GTX2:CHAN_BOND_SEQ_2_3[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[7]">GTX2:DRP0A[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_3" title="GTX2:CHAN_BOND_SEQ_2_3[8]">GTX2:CHAN_BOND_SEQ_2_3[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[8]">GTX2:DRP0A[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_3" title="GTX2:CHAN_BOND_SEQ_2_3[9]">GTX2:CHAN_BOND_SEQ_2_3[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[9]">GTX2:DRP0A[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_CFG" title="GTX2:CHAN_BOND_SEQ_2_CFG[0]">GTX2:CHAN_BOND_SEQ_2_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[10]">GTX2:DRP0A[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_CFG" title="GTX2:CHAN_BOND_SEQ_2_CFG[1]">GTX2:CHAN_BOND_SEQ_2_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[11]">GTX2:DRP0A[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_CFG" title="GTX2:CHAN_BOND_SEQ_2_CFG[2]">GTX2:CHAN_BOND_SEQ_2_CFG[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[12]">GTX2:DRP0A[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_CFG" title="GTX2:CHAN_BOND_SEQ_2_CFG[3]">GTX2:CHAN_BOND_SEQ_2_CFG[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[13]">GTX2:DRP0A[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_USE" title="GTX2:CHAN_BOND_SEQ_2_USE">GTX2:CHAN_BOND_SEQ_2_USE</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[14]">GTX2:DRP0A[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP0A" title="GTX2:DRP0A[15]">GTX2:DRP0A[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EN_IDLE_RESET_PH" title="GTX2:RX_EN_IDLE_RESET_PH">GTX2:RX_EN_IDLE_RESET_PH</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_4" title="GTX2:CHAN_BOND_SEQ_2_4[0]">GTX2:CHAN_BOND_SEQ_2_4[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[0]">GTX2:DRP0B[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_4" title="GTX2:CHAN_BOND_SEQ_2_4[1]">GTX2:CHAN_BOND_SEQ_2_4[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[1]">GTX2:DRP0B[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_4" title="GTX2:CHAN_BOND_SEQ_2_4[2]">GTX2:CHAN_BOND_SEQ_2_4[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[2]">GTX2:DRP0B[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_4" title="GTX2:CHAN_BOND_SEQ_2_4[3]">GTX2:CHAN_BOND_SEQ_2_4[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[3]">GTX2:DRP0B[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_4" title="GTX2:CHAN_BOND_SEQ_2_4[4]">GTX2:CHAN_BOND_SEQ_2_4[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[4]">GTX2:DRP0B[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_4" title="GTX2:CHAN_BOND_SEQ_2_4[5]">GTX2:CHAN_BOND_SEQ_2_4[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[5]">GTX2:DRP0B[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_4" title="GTX2:CHAN_BOND_SEQ_2_4[6]">GTX2:CHAN_BOND_SEQ_2_4[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[6]">GTX2:DRP0B[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_4" title="GTX2:CHAN_BOND_SEQ_2_4[7]">GTX2:CHAN_BOND_SEQ_2_4[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[7]">GTX2:DRP0B[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_4" title="GTX2:CHAN_BOND_SEQ_2_4[8]">GTX2:CHAN_BOND_SEQ_2_4[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[8]">GTX2:DRP0B[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_4" title="GTX2:CHAN_BOND_SEQ_2_4[9]">GTX2:CHAN_BOND_SEQ_2_4[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[9]">GTX2:DRP0B[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[10]">GTX2:DRP0B[10]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EN_IDLE_RESET_BUF" title="GTX2:RX_EN_IDLE_RESET_BUF">GTX2:RX_EN_IDLE_RESET_BUF</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[11]">GTX2:DRP0B[11]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_XCLK_SEL" title="GTX2:RX_XCLK_SEL">GTX2:RX_XCLK_SEL</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[12]">GTX2:DRP0B[12]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_IDLE_HI_CNT" title="GTX2:RX_IDLE_HI_CNT[0]">GTX2:RX_IDLE_HI_CNT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[13]">GTX2:DRP0B[13]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_IDLE_HI_CNT" title="GTX2:RX_IDLE_HI_CNT[1]">GTX2:RX_IDLE_HI_CNT[1]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[14]">GTX2:DRP0B[14]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_IDLE_HI_CNT" title="GTX2:RX_IDLE_HI_CNT[2]">GTX2:RX_IDLE_HI_CNT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP0B" title="GTX2:DRP0B[15]">GTX2:DRP0B[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_IDLE_HI_CNT" title="GTX2:RX_IDLE_HI_CNT[3]">GTX2:RX_IDLE_HI_CNT[3]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[0]">GTX2:DRP0C[0]</a><br><a href="#bits-xc6v-GTX-GTX2:RXBUF_OVFL_THRESH" title="GTX2:RXBUF_OVFL_THRESH[0]">GTX2:RXBUF_OVFL_THRESH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[1]">GTX2:DRP0C[1]</a><br><a href="#bits-xc6v-GTX-GTX2:RXBUF_OVFL_THRESH" title="GTX2:RXBUF_OVFL_THRESH[1]">GTX2:RXBUF_OVFL_THRESH[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[2]">GTX2:DRP0C[2]</a><br><a href="#bits-xc6v-GTX-GTX2:RXBUF_OVFL_THRESH" title="GTX2:RXBUF_OVFL_THRESH[2]">GTX2:RXBUF_OVFL_THRESH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[3]">GTX2:DRP0C[3]</a><br><a href="#bits-xc6v-GTX-GTX2:RXBUF_OVFL_THRESH" title="GTX2:RXBUF_OVFL_THRESH[3]">GTX2:RXBUF_OVFL_THRESH[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[4]">GTX2:DRP0C[4]</a><br><a href="#bits-xc6v-GTX-GTX2:RXBUF_OVFL_THRESH" title="GTX2:RXBUF_OVFL_THRESH[4]">GTX2:RXBUF_OVFL_THRESH[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[5]">GTX2:DRP0C[5]</a><br><a href="#bits-xc6v-GTX-GTX2:RXBUF_OVFL_THRESH" title="GTX2:RXBUF_OVFL_THRESH[5]">GTX2:RXBUF_OVFL_THRESH[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[6]">GTX2:DRP0C[6]</a><br><a href="#bits-xc6v-GTX-GTX2:RXBUF_UDFL_THRESH" title="GTX2:RXBUF_UDFL_THRESH[0]">GTX2:RXBUF_UDFL_THRESH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[7]">GTX2:DRP0C[7]</a><br><a href="#bits-xc6v-GTX-GTX2:RXBUF_UDFL_THRESH" title="GTX2:RXBUF_UDFL_THRESH[1]">GTX2:RXBUF_UDFL_THRESH[1]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[8]">GTX2:DRP0C[8]</a><br><a href="#bits-xc6v-GTX-GTX2:RXBUF_UDFL_THRESH" title="GTX2:RXBUF_UDFL_THRESH[2]">GTX2:RXBUF_UDFL_THRESH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[9]">GTX2:DRP0C[9]</a><br><a href="#bits-xc6v-GTX-GTX2:RXBUF_UDFL_THRESH" title="GTX2:RXBUF_UDFL_THRESH[3]">GTX2:RXBUF_UDFL_THRESH[3]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[10]">GTX2:DRP0C[10]</a><br><a href="#bits-xc6v-GTX-GTX2:RXBUF_UDFL_THRESH" title="GTX2:RXBUF_UDFL_THRESH[4]">GTX2:RXBUF_UDFL_THRESH[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[11]">GTX2:DRP0C[11]</a><br><a href="#bits-xc6v-GTX-GTX2:RXBUF_UDFL_THRESH" title="GTX2:RXBUF_UDFL_THRESH[5]">GTX2:RXBUF_UDFL_THRESH[5]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[12]">GTX2:DRP0C[12]</a><br><a href="#bits-xc6v-GTX-GTX2:RXBUF_OVRD_THRESH" title="GTX2:RXBUF_OVRD_THRESH">GTX2:RXBUF_OVRD_THRESH</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[13]">GTX2:DRP0C[13]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_FIFO_ADDR_MODE" title="GTX2:RX_FIFO_ADDR_MODE">GTX2:RX_FIFO_ADDR_MODE</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[14]">GTX2:DRP0C[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP0C" title="GTX2:DRP0C[15]">GTX2:DRP0C[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_1" title="GTX2:CLK_COR_SEQ_1_1[0]">GTX2:CLK_COR_SEQ_1_1[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[0]">GTX2:DRP0D[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_1" title="GTX2:CLK_COR_SEQ_1_1[1]">GTX2:CLK_COR_SEQ_1_1[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[1]">GTX2:DRP0D[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_1" title="GTX2:CLK_COR_SEQ_1_1[2]">GTX2:CLK_COR_SEQ_1_1[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[2]">GTX2:DRP0D[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_1" title="GTX2:CLK_COR_SEQ_1_1[3]">GTX2:CLK_COR_SEQ_1_1[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[3]">GTX2:DRP0D[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_1" title="GTX2:CLK_COR_SEQ_1_1[4]">GTX2:CLK_COR_SEQ_1_1[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[4]">GTX2:DRP0D[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_1" title="GTX2:CLK_COR_SEQ_1_1[5]">GTX2:CLK_COR_SEQ_1_1[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[5]">GTX2:DRP0D[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_1" title="GTX2:CLK_COR_SEQ_1_1[6]">GTX2:CLK_COR_SEQ_1_1[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[6]">GTX2:DRP0D[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_1" title="GTX2:CLK_COR_SEQ_1_1[7]">GTX2:CLK_COR_SEQ_1_1[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[7]">GTX2:DRP0D[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_1" title="GTX2:CLK_COR_SEQ_1_1[8]">GTX2:CLK_COR_SEQ_1_1[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[8]">GTX2:DRP0D[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_1" title="GTX2:CLK_COR_SEQ_1_1[9]">GTX2:CLK_COR_SEQ_1_1[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[9]">GTX2:DRP0D[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_ENABLE" title="GTX2:CLK_COR_SEQ_1_ENABLE[0]">GTX2:CLK_COR_SEQ_1_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[10]">GTX2:DRP0D[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_ENABLE" title="GTX2:CLK_COR_SEQ_1_ENABLE[1]">GTX2:CLK_COR_SEQ_1_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[11]">GTX2:DRP0D[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_ENABLE" title="GTX2:CLK_COR_SEQ_1_ENABLE[2]">GTX2:CLK_COR_SEQ_1_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[12]">GTX2:DRP0D[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_ENABLE" title="GTX2:CLK_COR_SEQ_1_ENABLE[3]">GTX2:CLK_COR_SEQ_1_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[13]">GTX2:DRP0D[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_CORRECT_USE" title="GTX2:CLK_CORRECT_USE">GTX2:CLK_CORRECT_USE</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[14]">GTX2:DRP0D[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_PRECEDENCE" title="GTX2:CLK_COR_PRECEDENCE">GTX2:CLK_COR_PRECEDENCE</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0D" title="GTX2:DRP0D[15]">GTX2:DRP0D[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_2" title="GTX2:CLK_COR_SEQ_1_2[0]">GTX2:CLK_COR_SEQ_1_2[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[0]">GTX2:DRP0E[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_2" title="GTX2:CLK_COR_SEQ_1_2[1]">GTX2:CLK_COR_SEQ_1_2[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[1]">GTX2:DRP0E[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_2" title="GTX2:CLK_COR_SEQ_1_2[2]">GTX2:CLK_COR_SEQ_1_2[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[2]">GTX2:DRP0E[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_2" title="GTX2:CLK_COR_SEQ_1_2[3]">GTX2:CLK_COR_SEQ_1_2[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[3]">GTX2:DRP0E[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_2" title="GTX2:CLK_COR_SEQ_1_2[4]">GTX2:CLK_COR_SEQ_1_2[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[4]">GTX2:DRP0E[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_2" title="GTX2:CLK_COR_SEQ_1_2[5]">GTX2:CLK_COR_SEQ_1_2[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[5]">GTX2:DRP0E[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_2" title="GTX2:CLK_COR_SEQ_1_2[6]">GTX2:CLK_COR_SEQ_1_2[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[6]">GTX2:DRP0E[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_2" title="GTX2:CLK_COR_SEQ_1_2[7]">GTX2:CLK_COR_SEQ_1_2[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[7]">GTX2:DRP0E[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_2" title="GTX2:CLK_COR_SEQ_1_2[8]">GTX2:CLK_COR_SEQ_1_2[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[8]">GTX2:DRP0E[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_2" title="GTX2:CLK_COR_SEQ_1_2[9]">GTX2:CLK_COR_SEQ_1_2[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[9]">GTX2:DRP0E[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_REPEAT_WAIT" title="GTX2:CLK_COR_REPEAT_WAIT[0]">GTX2:CLK_COR_REPEAT_WAIT[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[10]">GTX2:DRP0E[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_REPEAT_WAIT" title="GTX2:CLK_COR_REPEAT_WAIT[1]">GTX2:CLK_COR_REPEAT_WAIT[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[11]">GTX2:DRP0E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_REPEAT_WAIT" title="GTX2:CLK_COR_REPEAT_WAIT[2]">GTX2:CLK_COR_REPEAT_WAIT[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[12]">GTX2:DRP0E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_REPEAT_WAIT" title="GTX2:CLK_COR_REPEAT_WAIT[3]">GTX2:CLK_COR_REPEAT_WAIT[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[13]">GTX2:DRP0E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_REPEAT_WAIT" title="GTX2:CLK_COR_REPEAT_WAIT[4]">GTX2:CLK_COR_REPEAT_WAIT[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[14]">GTX2:DRP0E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_KEEP_IDLE" title="GTX2:CLK_COR_KEEP_IDLE">GTX2:CLK_COR_KEEP_IDLE</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0E" title="GTX2:DRP0E[15]">GTX2:DRP0E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_3" title="GTX2:CLK_COR_SEQ_1_3[0]">GTX2:CLK_COR_SEQ_1_3[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[0]">GTX2:DRP0F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_3" title="GTX2:CLK_COR_SEQ_1_3[1]">GTX2:CLK_COR_SEQ_1_3[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[1]">GTX2:DRP0F[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_3" title="GTX2:CLK_COR_SEQ_1_3[2]">GTX2:CLK_COR_SEQ_1_3[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[2]">GTX2:DRP0F[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_3" title="GTX2:CLK_COR_SEQ_1_3[3]">GTX2:CLK_COR_SEQ_1_3[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[3]">GTX2:DRP0F[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_3" title="GTX2:CLK_COR_SEQ_1_3[4]">GTX2:CLK_COR_SEQ_1_3[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[4]">GTX2:DRP0F[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_3" title="GTX2:CLK_COR_SEQ_1_3[5]">GTX2:CLK_COR_SEQ_1_3[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[5]">GTX2:DRP0F[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_3" title="GTX2:CLK_COR_SEQ_1_3[6]">GTX2:CLK_COR_SEQ_1_3[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[6]">GTX2:DRP0F[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_3" title="GTX2:CLK_COR_SEQ_1_3[7]">GTX2:CLK_COR_SEQ_1_3[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[7]">GTX2:DRP0F[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_3" title="GTX2:CLK_COR_SEQ_1_3[8]">GTX2:CLK_COR_SEQ_1_3[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[8]">GTX2:DRP0F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_3" title="GTX2:CLK_COR_SEQ_1_3[9]">GTX2:CLK_COR_SEQ_1_3[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[9]">GTX2:DRP0F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_MIN_LAT" title="GTX2:CLK_COR_MIN_LAT[0]">GTX2:CLK_COR_MIN_LAT[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[10]">GTX2:DRP0F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_MIN_LAT" title="GTX2:CLK_COR_MIN_LAT[1]">GTX2:CLK_COR_MIN_LAT[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[11]">GTX2:DRP0F[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_MIN_LAT" title="GTX2:CLK_COR_MIN_LAT[2]">GTX2:CLK_COR_MIN_LAT[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[12]">GTX2:DRP0F[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_MIN_LAT" title="GTX2:CLK_COR_MIN_LAT[3]">GTX2:CLK_COR_MIN_LAT[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[13]">GTX2:DRP0F[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_MIN_LAT" title="GTX2:CLK_COR_MIN_LAT[4]">GTX2:CLK_COR_MIN_LAT[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[14]">GTX2:DRP0F[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_MIN_LAT" title="GTX2:CLK_COR_MIN_LAT[5]">GTX2:CLK_COR_MIN_LAT[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP0F" title="GTX2:DRP0F[15]">GTX2:DRP0F[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 22</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_4" title="GTX2:CLK_COR_SEQ_1_4[0]">GTX2:CLK_COR_SEQ_1_4[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[0]">GTX2:DRP10[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_4" title="GTX2:CLK_COR_SEQ_1_4[1]">GTX2:CLK_COR_SEQ_1_4[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[1]">GTX2:DRP10[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_4" title="GTX2:CLK_COR_SEQ_1_4[2]">GTX2:CLK_COR_SEQ_1_4[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[2]">GTX2:DRP10[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_4" title="GTX2:CLK_COR_SEQ_1_4[3]">GTX2:CLK_COR_SEQ_1_4[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[3]">GTX2:DRP10[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_4" title="GTX2:CLK_COR_SEQ_1_4[4]">GTX2:CLK_COR_SEQ_1_4[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[4]">GTX2:DRP10[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_4" title="GTX2:CLK_COR_SEQ_1_4[5]">GTX2:CLK_COR_SEQ_1_4[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[5]">GTX2:DRP10[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_4" title="GTX2:CLK_COR_SEQ_1_4[6]">GTX2:CLK_COR_SEQ_1_4[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[6]">GTX2:DRP10[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_4" title="GTX2:CLK_COR_SEQ_1_4[7]">GTX2:CLK_COR_SEQ_1_4[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[7]">GTX2:DRP10[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_4" title="GTX2:CLK_COR_SEQ_1_4[8]">GTX2:CLK_COR_SEQ_1_4[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[8]">GTX2:DRP10[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_4" title="GTX2:CLK_COR_SEQ_1_4[9]">GTX2:CLK_COR_SEQ_1_4[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[9]">GTX2:DRP10[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_MAX_LAT" title="GTX2:CLK_COR_MAX_LAT[0]">GTX2:CLK_COR_MAX_LAT[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[10]">GTX2:DRP10[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_MAX_LAT" title="GTX2:CLK_COR_MAX_LAT[1]">GTX2:CLK_COR_MAX_LAT[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[11]">GTX2:DRP10[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_MAX_LAT" title="GTX2:CLK_COR_MAX_LAT[2]">GTX2:CLK_COR_MAX_LAT[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[12]">GTX2:DRP10[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_MAX_LAT" title="GTX2:CLK_COR_MAX_LAT[3]">GTX2:CLK_COR_MAX_LAT[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[13]">GTX2:DRP10[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_MAX_LAT" title="GTX2:CLK_COR_MAX_LAT[4]">GTX2:CLK_COR_MAX_LAT[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[14]">GTX2:DRP10[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_MAX_LAT" title="GTX2:CLK_COR_MAX_LAT[5]">GTX2:CLK_COR_MAX_LAT[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP10" title="GTX2:DRP10[15]">GTX2:DRP10[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_1" title="GTX2:CLK_COR_SEQ_2_1[0]">GTX2:CLK_COR_SEQ_2_1[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[0]">GTX2:DRP11[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_1" title="GTX2:CLK_COR_SEQ_2_1[1]">GTX2:CLK_COR_SEQ_2_1[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[1]">GTX2:DRP11[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_1" title="GTX2:CLK_COR_SEQ_2_1[2]">GTX2:CLK_COR_SEQ_2_1[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[2]">GTX2:DRP11[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_1" title="GTX2:CLK_COR_SEQ_2_1[3]">GTX2:CLK_COR_SEQ_2_1[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[3]">GTX2:DRP11[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_1" title="GTX2:CLK_COR_SEQ_2_1[4]">GTX2:CLK_COR_SEQ_2_1[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[4]">GTX2:DRP11[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_1" title="GTX2:CLK_COR_SEQ_2_1[5]">GTX2:CLK_COR_SEQ_2_1[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[5]">GTX2:DRP11[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_1" title="GTX2:CLK_COR_SEQ_2_1[6]">GTX2:CLK_COR_SEQ_2_1[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[6]">GTX2:DRP11[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_1" title="GTX2:CLK_COR_SEQ_2_1[7]">GTX2:CLK_COR_SEQ_2_1[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[7]">GTX2:DRP11[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_1" title="GTX2:CLK_COR_SEQ_2_1[8]">GTX2:CLK_COR_SEQ_2_1[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[8]">GTX2:DRP11[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_1" title="GTX2:CLK_COR_SEQ_2_1[9]">GTX2:CLK_COR_SEQ_2_1[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[9]">GTX2:DRP11[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_ENABLE" title="GTX2:CLK_COR_SEQ_2_ENABLE[0]">GTX2:CLK_COR_SEQ_2_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[10]">GTX2:DRP11[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_ENABLE" title="GTX2:CLK_COR_SEQ_2_ENABLE[1]">GTX2:CLK_COR_SEQ_2_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[11]">GTX2:DRP11[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_ENABLE" title="GTX2:CLK_COR_SEQ_2_ENABLE[2]">GTX2:CLK_COR_SEQ_2_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[12]">GTX2:DRP11[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_ENABLE" title="GTX2:CLK_COR_SEQ_2_ENABLE[3]">GTX2:CLK_COR_SEQ_2_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[13]">GTX2:DRP11[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_USE" title="GTX2:CLK_COR_SEQ_2_USE">GTX2:CLK_COR_SEQ_2_USE</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[14]">GTX2:DRP11[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_INSERT_IDLE_FLAG" title="GTX2:CLK_COR_INSERT_IDLE_FLAG">GTX2:CLK_COR_INSERT_IDLE_FLAG</a><br><a href="#bits-xc6v-GTX-GTX2:DRP11" title="GTX2:DRP11[15]">GTX2:DRP11[15]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_2" title="GTX2:CLK_COR_SEQ_2_2[0]">GTX2:CLK_COR_SEQ_2_2[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[0]">GTX2:DRP12[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_2" title="GTX2:CLK_COR_SEQ_2_2[1]">GTX2:CLK_COR_SEQ_2_2[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[1]">GTX2:DRP12[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_2" title="GTX2:CLK_COR_SEQ_2_2[2]">GTX2:CLK_COR_SEQ_2_2[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[2]">GTX2:DRP12[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_2" title="GTX2:CLK_COR_SEQ_2_2[3]">GTX2:CLK_COR_SEQ_2_2[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[3]">GTX2:DRP12[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_2" title="GTX2:CLK_COR_SEQ_2_2[4]">GTX2:CLK_COR_SEQ_2_2[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[4]">GTX2:DRP12[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_2" title="GTX2:CLK_COR_SEQ_2_2[5]">GTX2:CLK_COR_SEQ_2_2[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[5]">GTX2:DRP12[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_2" title="GTX2:CLK_COR_SEQ_2_2[6]">GTX2:CLK_COR_SEQ_2_2[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[6]">GTX2:DRP12[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_2" title="GTX2:CLK_COR_SEQ_2_2[7]">GTX2:CLK_COR_SEQ_2_2[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[7]">GTX2:DRP12[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_2" title="GTX2:CLK_COR_SEQ_2_2[8]">GTX2:CLK_COR_SEQ_2_2[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[8]">GTX2:DRP12[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_2" title="GTX2:CLK_COR_SEQ_2_2[9]">GTX2:CLK_COR_SEQ_2_2[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[9]">GTX2:DRP12[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_ADJ_LEN" title="GTX2:CLK_COR_ADJ_LEN[0]">GTX2:CLK_COR_ADJ_LEN[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[10]">GTX2:DRP12[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_ADJ_LEN" title="GTX2:CLK_COR_ADJ_LEN[1]">GTX2:CLK_COR_ADJ_LEN[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[11]">GTX2:DRP12[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[12]">GTX2:DRP12[12]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_SLIDE_MODE" title="GTX2:RX_SLIDE_MODE[0]">GTX2:RX_SLIDE_MODE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[13]">GTX2:DRP12[13]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_SLIDE_MODE" title="GTX2:RX_SLIDE_MODE[1]">GTX2:RX_SLIDE_MODE[1]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[14]">GTX2:DRP12[14]</a><br><a href="#bits-xc6v-GTX-GTX2:SHOW_REALIGN_COMMA" title="GTX2:SHOW_REALIGN_COMMA">GTX2:SHOW_REALIGN_COMMA</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP12" title="GTX2:DRP12[15]">GTX2:DRP12[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_CDR_FORCE_ROTATE" title="GTX2:RX_CDR_FORCE_ROTATE">GTX2:RX_CDR_FORCE_ROTATE</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_3" title="GTX2:CLK_COR_SEQ_2_3[0]">GTX2:CLK_COR_SEQ_2_3[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[0]">GTX2:DRP13[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_3" title="GTX2:CLK_COR_SEQ_2_3[1]">GTX2:CLK_COR_SEQ_2_3[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[1]">GTX2:DRP13[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_3" title="GTX2:CLK_COR_SEQ_2_3[2]">GTX2:CLK_COR_SEQ_2_3[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[2]">GTX2:DRP13[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_3" title="GTX2:CLK_COR_SEQ_2_3[3]">GTX2:CLK_COR_SEQ_2_3[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[3]">GTX2:DRP13[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_3" title="GTX2:CLK_COR_SEQ_2_3[4]">GTX2:CLK_COR_SEQ_2_3[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[4]">GTX2:DRP13[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_3" title="GTX2:CLK_COR_SEQ_2_3[5]">GTX2:CLK_COR_SEQ_2_3[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[5]">GTX2:DRP13[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_3" title="GTX2:CLK_COR_SEQ_2_3[6]">GTX2:CLK_COR_SEQ_2_3[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[6]">GTX2:DRP13[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_3" title="GTX2:CLK_COR_SEQ_2_3[7]">GTX2:CLK_COR_SEQ_2_3[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[7]">GTX2:DRP13[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_3" title="GTX2:CLK_COR_SEQ_2_3[8]">GTX2:CLK_COR_SEQ_2_3[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[8]">GTX2:DRP13[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_3" title="GTX2:CLK_COR_SEQ_2_3[9]">GTX2:CLK_COR_SEQ_2_3[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[9]">GTX2:DRP13[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_DET_LEN" title="GTX2:CLK_COR_DET_LEN[0]">GTX2:CLK_COR_DET_LEN[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[10]">GTX2:DRP13[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_DET_LEN" title="GTX2:CLK_COR_DET_LEN[1]">GTX2:CLK_COR_DET_LEN[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[11]">GTX2:DRP13[11]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[12]">GTX2:DRP13[12]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_SLIDE_AUTO_WAIT" title="GTX2:RX_SLIDE_AUTO_WAIT[0]">GTX2:RX_SLIDE_AUTO_WAIT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[13]">GTX2:DRP13[13]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_SLIDE_AUTO_WAIT" title="GTX2:RX_SLIDE_AUTO_WAIT[1]">GTX2:RX_SLIDE_AUTO_WAIT[1]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[14]">GTX2:DRP13[14]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_SLIDE_AUTO_WAIT" title="GTX2:RX_SLIDE_AUTO_WAIT[2]">GTX2:RX_SLIDE_AUTO_WAIT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP13" title="GTX2:DRP13[15]">GTX2:DRP13[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_SLIDE_AUTO_WAIT" title="GTX2:RX_SLIDE_AUTO_WAIT[3]">GTX2:RX_SLIDE_AUTO_WAIT[3]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_4" title="GTX2:CLK_COR_SEQ_2_4[0]">GTX2:CLK_COR_SEQ_2_4[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[0]">GTX2:DRP14[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_4" title="GTX2:CLK_COR_SEQ_2_4[1]">GTX2:CLK_COR_SEQ_2_4[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[1]">GTX2:DRP14[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_4" title="GTX2:CLK_COR_SEQ_2_4[2]">GTX2:CLK_COR_SEQ_2_4[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[2]">GTX2:DRP14[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_4" title="GTX2:CLK_COR_SEQ_2_4[3]">GTX2:CLK_COR_SEQ_2_4[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[3]">GTX2:DRP14[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_4" title="GTX2:CLK_COR_SEQ_2_4[4]">GTX2:CLK_COR_SEQ_2_4[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[4]">GTX2:DRP14[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_4" title="GTX2:CLK_COR_SEQ_2_4[5]">GTX2:CLK_COR_SEQ_2_4[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[5]">GTX2:DRP14[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_4" title="GTX2:CLK_COR_SEQ_2_4[6]">GTX2:CLK_COR_SEQ_2_4[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[6]">GTX2:DRP14[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_4" title="GTX2:CLK_COR_SEQ_2_4[7]">GTX2:CLK_COR_SEQ_2_4[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[7]">GTX2:DRP14[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_4" title="GTX2:CLK_COR_SEQ_2_4[8]">GTX2:CLK_COR_SEQ_2_4[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[8]">GTX2:DRP14[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_4" title="GTX2:CLK_COR_SEQ_2_4[9]">GTX2:CLK_COR_SEQ_2_4[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[9]">GTX2:DRP14[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DEC_PCOMMA_DETECT" title="GTX2:DEC_PCOMMA_DETECT">GTX2:DEC_PCOMMA_DETECT</a><br><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[10]">GTX2:DRP14[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DEC_MCOMMA_DETECT" title="GTX2:DEC_MCOMMA_DETECT">GTX2:DEC_MCOMMA_DETECT</a><br><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[11]">GTX2:DRP14[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[12]">GTX2:DRP14[12]</a><br><a href="#bits-xc6v-GTX-GTX2:USR_CODE_ERR_CLR" title="GTX2:USR_CODE_ERR_CLR">GTX2:USR_CODE_ERR_CLR</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[13]">GTX2:DRP14[13]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DECODE_SEQ_MATCH" title="GTX2:RX_DECODE_SEQ_MATCH">GTX2:RX_DECODE_SEQ_MATCH</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:ALIGN_COMMA_WORD" title="GTX2:ALIGN_COMMA_WORD">GTX2:ALIGN_COMMA_WORD</a><br><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[14]">GTX2:DRP14[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DEC_VALID_COMMA_ONLY" title="GTX2:DEC_VALID_COMMA_ONLY">GTX2:DEC_VALID_COMMA_ONLY</a><br><a href="#bits-xc6v-GTX-GTX2:DRP14" title="GTX2:DRP14[15]">GTX2:DRP14[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[0]">GTX2:DRP15[0]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[0]">GTX2:PMA_CDR_SCAN[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[1]">GTX2:DRP15[1]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[1]">GTX2:PMA_CDR_SCAN[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[2]">GTX2:DRP15[2]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[2]">GTX2:PMA_CDR_SCAN[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[3]">GTX2:DRP15[3]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[3]">GTX2:PMA_CDR_SCAN[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[4]">GTX2:DRP15[4]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[4]">GTX2:PMA_CDR_SCAN[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[5]">GTX2:DRP15[5]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[5]">GTX2:PMA_CDR_SCAN[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[6]">GTX2:DRP15[6]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[6]">GTX2:PMA_CDR_SCAN[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[7]">GTX2:DRP15[7]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[7]">GTX2:PMA_CDR_SCAN[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[8]">GTX2:DRP15[8]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[8]">GTX2:PMA_CDR_SCAN[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[9]">GTX2:DRP15[9]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[9]">GTX2:PMA_CDR_SCAN[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[10]">GTX2:DRP15[10]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[10]">GTX2:PMA_CDR_SCAN[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[11]">GTX2:DRP15[11]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[11]">GTX2:PMA_CDR_SCAN[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[12]">GTX2:DRP15[12]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[12]">GTX2:PMA_CDR_SCAN[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[13]">GTX2:DRP15[13]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[13]">GTX2:PMA_CDR_SCAN[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[14]">GTX2:DRP15[14]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[14]">GTX2:PMA_CDR_SCAN[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP15" title="GTX2:DRP15[15]">GTX2:DRP15[15]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[15]">GTX2:PMA_CDR_SCAN[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[0]">GTX2:DRP16[0]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[16]">GTX2:PMA_CDR_SCAN[16]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[1]">GTX2:DRP16[1]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[17]">GTX2:PMA_CDR_SCAN[17]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[2]">GTX2:DRP16[2]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[18]">GTX2:PMA_CDR_SCAN[18]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[3]">GTX2:DRP16[3]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[19]">GTX2:PMA_CDR_SCAN[19]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[4]">GTX2:DRP16[4]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[20]">GTX2:PMA_CDR_SCAN[20]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[5]">GTX2:DRP16[5]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[21]">GTX2:PMA_CDR_SCAN[21]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[6]">GTX2:DRP16[6]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[22]">GTX2:PMA_CDR_SCAN[22]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[7]">GTX2:DRP16[7]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[23]">GTX2:PMA_CDR_SCAN[23]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[8]">GTX2:DRP16[8]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[24]">GTX2:PMA_CDR_SCAN[24]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[9]">GTX2:DRP16[9]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[25]">GTX2:PMA_CDR_SCAN[25]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[10]">GTX2:DRP16[10]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CDR_SCAN" title="GTX2:PMA_CDR_SCAN[26]">GTX2:PMA_CDR_SCAN[26]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CDR_PH_ADJ_TIME" title="GTX2:CDR_PH_ADJ_TIME[0]">GTX2:CDR_PH_ADJ_TIME[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[11]">GTX2:DRP16[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CDR_PH_ADJ_TIME" title="GTX2:CDR_PH_ADJ_TIME[1]">GTX2:CDR_PH_ADJ_TIME[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[12]">GTX2:DRP16[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CDR_PH_ADJ_TIME" title="GTX2:CDR_PH_ADJ_TIME[2]">GTX2:CDR_PH_ADJ_TIME[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[13]">GTX2:DRP16[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CDR_PH_ADJ_TIME" title="GTX2:CDR_PH_ADJ_TIME[3]">GTX2:CDR_PH_ADJ_TIME[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[14]">GTX2:DRP16[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CDR_PH_ADJ_TIME" title="GTX2:CDR_PH_ADJ_TIME[4]">GTX2:CDR_PH_ADJ_TIME[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP16" title="GTX2:DRP16[15]">GTX2:DRP16[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[0]">GTX2:DRP17[0]</a><br><a href="#bits-xc6v-GTX-GTX2:OOBDETECT_THRESHOLD" title="GTX2:OOBDETECT_THRESHOLD[0]">GTX2:OOBDETECT_THRESHOLD[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[1]">GTX2:DRP17[1]</a><br><a href="#bits-xc6v-GTX-GTX2:OOBDETECT_THRESHOLD" title="GTX2:OOBDETECT_THRESHOLD[1]">GTX2:OOBDETECT_THRESHOLD[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[2]">GTX2:DRP17[2]</a><br><a href="#bits-xc6v-GTX-GTX2:OOBDETECT_THRESHOLD" title="GTX2:OOBDETECT_THRESHOLD[2]">GTX2:OOBDETECT_THRESHOLD[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[3]">GTX2:DRP17[3]</a><br><a href="#bits-xc6v-GTX-GTX2:GTX_CFG_PWRUP" title="GTX2:GTX_CFG_PWRUP">GTX2:GTX_CFG_PWRUP</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:AC_CAP_DIS" title="GTX2:AC_CAP_DIS">GTX2:AC_CAP_DIS</a><br><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[4]">GTX2:DRP17[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[5]">GTX2:DRP17[5]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_CLK25_DIVIDER" title="GTX2:RX_CLK25_DIVIDER[0]">GTX2:RX_CLK25_DIVIDER[0]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[6]">GTX2:DRP17[6]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_CLK25_DIVIDER" title="GTX2:RX_CLK25_DIVIDER[1]">GTX2:RX_CLK25_DIVIDER[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[7]">GTX2:DRP17[7]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_CLK25_DIVIDER" title="GTX2:RX_CLK25_DIVIDER[2]">GTX2:RX_CLK25_DIVIDER[2]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[8]">GTX2:DRP17[8]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_CLK25_DIVIDER" title="GTX2:RX_CLK25_DIVIDER[3]">GTX2:RX_CLK25_DIVIDER[3]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[9]">GTX2:DRP17[9]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_CLK25_DIVIDER" title="GTX2:RX_CLK25_DIVIDER[4]">GTX2:RX_CLK25_DIVIDER[4]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:BIAS_CFG" title="GTX2:BIAS_CFG[16]">GTX2:BIAS_CFG[16]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[10]">GTX2:DRP17[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_CFG" title="GTX2:CHAN_BOND_SEQ_2_CFG[4]">GTX2:CHAN_BOND_SEQ_2_CFG[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[11]">GTX2:DRP17[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[12]">GTX2:DRP17[12]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DATA_WIDTH" title="GTX2:RX_DATA_WIDTH[0]">GTX2:RX_DATA_WIDTH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[13]">GTX2:DRP17[13]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DATA_WIDTH" title="GTX2:RX_DATA_WIDTH[1]">GTX2:RX_DATA_WIDTH[1]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[14]">GTX2:DRP17[14]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DATA_WIDTH" title="GTX2:RX_DATA_WIDTH[2]">GTX2:RX_DATA_WIDTH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP17" title="GTX2:DRP17[15]">GTX2:DRP17[15]</a><br><a href="#bits-xc6v-GTX-GTX2:GEN_RXUSRCLK" title="GTX2:GEN_RXUSRCLK">GTX2:GEN_RXUSRCLK</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 23</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[0]">GTX2:DRP18[0]</a><br><a href="#bits-xc6v-GTX-GTX2:GEARBOX_ENDEC" title="GTX2:GEARBOX_ENDEC[0]">GTX2:GEARBOX_ENDEC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[1]">GTX2:DRP18[1]</a><br><a href="#bits-xc6v-GTX-GTX2:GEARBOX_ENDEC" title="GTX2:GEARBOX_ENDEC[1]">GTX2:GEARBOX_ENDEC[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[2]">GTX2:DRP18[2]</a><br><a href="#bits-xc6v-GTX-GTX2:GEARBOX_ENDEC" title="GTX2:GEARBOX_ENDEC[2]">GTX2:GEARBOX_ENDEC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[3]">GTX2:DRP18[3]</a><br><a href="#bits-xc6v-GTX-GTX2:RXGEARBOX_USE" title="GTX2:RXGEARBOX_USE">GTX2:RXGEARBOX_USE</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_RXCDRRESET" title="GTX2:A_RXCDRRESET">GTX2:A_RXCDRRESET</a><br><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[4]">GTX2:DRP18[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_GTXTXRESET" title="GTX2:A_GTXTXRESET">GTX2:A_GTXTXRESET</a><br><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[5]">GTX2:DRP18[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_GTXRXRESET" title="GTX2:A_GTXRXRESET">GTX2:A_GTXRXRESET</a><br><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[6]">GTX2:DRP18[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_RXBUFRESET" title="GTX2:A_RXBUFRESET">GTX2:A_RXBUFRESET</a><br><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[7]">GTX2:DRP18[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_RXRESET" title="GTX2:A_RXRESET">GTX2:A_RXRESET</a><br><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[8]">GTX2:DRP18[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXRESET" title="GTX2:A_TXRESET">GTX2:A_TXRESET</a><br><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[9]">GTX2:DRP18[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_RXCDRHOLD" title="GTX2:A_RXCDRHOLD">GTX2:A_RXCDRHOLD</a><br><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[10]">GTX2:DRP18[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_RXCDRFREQRESET" title="GTX2:A_RXCDRFREQRESET">GTX2:A_RXCDRFREQRESET</a><br><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[11]">GTX2:DRP18[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_RXCDRPHASERESET" title="GTX2:A_RXCDRPHASERESET">GTX2:A_RXCDRPHASERESET</a><br><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[12]">GTX2:DRP18[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_RXDFERESET" title="GTX2:A_RXDFERESET">GTX2:A_RXDFERESET</a><br><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[13]">GTX2:DRP18[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[14]">GTX2:DRP18[14]</a><br><a href="#bits-xc6v-GTX-GTX2:RESET_DRP_EN" title="GTX2:RESET_DRP_EN">GTX2:RESET_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP18" title="GTX2:DRP18[15]">GTX2:DRP18[15]</a><br><a href="#bits-xc6v-GTX-GTX2:MASTER_DRP_EN" title="GTX2:MASTER_DRP_EN">GTX2:MASTER_DRP_EN</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[0]">GTX2:DRP19[0]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[0]">GTX2:RXPLL_COM_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[1]">GTX2:DRP19[1]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[1]">GTX2:RXPLL_COM_CFG[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[2]">GTX2:DRP19[2]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[2]">GTX2:RXPLL_COM_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[3]">GTX2:DRP19[3]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[3]">GTX2:RXPLL_COM_CFG[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[4]">GTX2:DRP19[4]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[4]">GTX2:RXPLL_COM_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[5]">GTX2:DRP19[5]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[5]">GTX2:RXPLL_COM_CFG[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[6]">GTX2:DRP19[6]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[6]">GTX2:RXPLL_COM_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[7]">GTX2:DRP19[7]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[7]">GTX2:RXPLL_COM_CFG[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[8]">GTX2:DRP19[8]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[8]">GTX2:RXPLL_COM_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[9]">GTX2:DRP19[9]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[9]">GTX2:RXPLL_COM_CFG[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[10]">GTX2:DRP19[10]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[10]">GTX2:RXPLL_COM_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[11]">GTX2:DRP19[11]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[11]">GTX2:RXPLL_COM_CFG[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[12]">GTX2:DRP19[12]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[12]">GTX2:RXPLL_COM_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[13]">GTX2:DRP19[13]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[13]">GTX2:RXPLL_COM_CFG[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[14]">GTX2:DRP19[14]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[14]">GTX2:RXPLL_COM_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP19" title="GTX2:DRP19[15]">GTX2:DRP19[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[15]">GTX2:RXPLL_COM_CFG[15]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[0]">GTX2:DRP1A[0]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[16]">GTX2:RXPLL_COM_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[1]">GTX2:DRP1A[1]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[17]">GTX2:RXPLL_COM_CFG[17]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[2]">GTX2:DRP1A[2]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[18]">GTX2:RXPLL_COM_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[3]">GTX2:DRP1A[3]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[19]">GTX2:RXPLL_COM_CFG[19]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[4]">GTX2:DRP1A[4]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[20]">GTX2:RXPLL_COM_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[5]">GTX2:DRP1A[5]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[21]">GTX2:RXPLL_COM_CFG[21]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[6]">GTX2:DRP1A[6]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[22]">GTX2:RXPLL_COM_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[7]">GTX2:DRP1A[7]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_COM_CFG" title="GTX2:RXPLL_COM_CFG[23]">GTX2:RXPLL_COM_CFG[23]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[8]">GTX2:DRP1A[8]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_CP_CFG" title="GTX2:RXPLL_CP_CFG[0]">GTX2:RXPLL_CP_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[9]">GTX2:DRP1A[9]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_CP_CFG" title="GTX2:RXPLL_CP_CFG[1]">GTX2:RXPLL_CP_CFG[1]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[10]">GTX2:DRP1A[10]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_CP_CFG" title="GTX2:RXPLL_CP_CFG[2]">GTX2:RXPLL_CP_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[11]">GTX2:DRP1A[11]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_CP_CFG" title="GTX2:RXPLL_CP_CFG[3]">GTX2:RXPLL_CP_CFG[3]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[12]">GTX2:DRP1A[12]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_CP_CFG" title="GTX2:RXPLL_CP_CFG[4]">GTX2:RXPLL_CP_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[13]">GTX2:DRP1A[13]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_CP_CFG" title="GTX2:RXPLL_CP_CFG[5]">GTX2:RXPLL_CP_CFG[5]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[14]">GTX2:DRP1A[14]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_CP_CFG" title="GTX2:RXPLL_CP_CFG[6]">GTX2:RXPLL_CP_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1A" title="GTX2:DRP1A[15]">GTX2:DRP1A[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_CP_CFG" title="GTX2:RXPLL_CP_CFG[7]">GTX2:RXPLL_CP_CFG[7]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[0]">GTX2:DRP1B[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[1]">GTX2:DRP1B[1]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_DIVSEL_FB" title="GTX2:RXPLL_DIVSEL_FB[1]">GTX2:RXPLL_DIVSEL_FB[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[2]">GTX2:DRP1B[2]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_DIVSEL_FB" title="GTX2:RXPLL_DIVSEL_FB[2]">GTX2:RXPLL_DIVSEL_FB[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[3]">GTX2:DRP1B[3]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_DIVSEL_FB" title="GTX2:RXPLL_DIVSEL_FB[3]">GTX2:RXPLL_DIVSEL_FB[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[4]">GTX2:DRP1B[4]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_DIVSEL_FB" title="GTX2:RXPLL_DIVSEL_FB[4]">GTX2:RXPLL_DIVSEL_FB[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[5]">GTX2:DRP1B[5]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_DIVSEL_FB" title="GTX2:RXPLL_DIVSEL_FB[0]">GTX2:RXPLL_DIVSEL_FB[0]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[6]">GTX2:DRP1B[6]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_DIVSEL45_FB" title="GTX2:RXPLL_DIVSEL45_FB">GTX2:RXPLL_DIVSEL45_FB</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[7]">GTX2:DRP1B[7]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_STARTUP_EN" title="GTX2:RXPLL_STARTUP_EN">GTX2:RXPLL_STARTUP_EN</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[8]">GTX2:DRP1B[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_RXPOWERDOWN" title="GTX2:A_RXPOWERDOWN[0]">GTX2:A_RXPOWERDOWN[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[9]">GTX2:DRP1B[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_RXPOWERDOWN" title="GTX2:A_RXPOWERDOWN[1]">GTX2:A_RXPOWERDOWN[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[10]">GTX2:DRP1B[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[11]">GTX2:DRP1B[11]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_LKDET_CFG" title="GTX2:RXPLL_LKDET_CFG[0]">GTX2:RXPLL_LKDET_CFG[0]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[12]">GTX2:DRP1B[12]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_LKDET_CFG" title="GTX2:RXPLL_LKDET_CFG[1]">GTX2:RXPLL_LKDET_CFG[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[13]">GTX2:DRP1B[13]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_LKDET_CFG" title="GTX2:RXPLL_LKDET_CFG[2]">GTX2:RXPLL_LKDET_CFG[2]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[14]">GTX2:DRP1B[14]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_DIVSEL_OUT" title="GTX2:RXPLL_DIVSEL_OUT[0]">GTX2:RXPLL_DIVSEL_OUT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1B" title="GTX2:DRP1B[15]">GTX2:DRP1B[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_DIVSEL_OUT" title="GTX2:RXPLL_DIVSEL_OUT[1]">GTX2:RXPLL_DIVSEL_OUT[1]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[0]">GTX2:DRP1C[0]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLLREFSEL_TESTCLK" title="GTX2:RXPLLREFSEL_TESTCLK">GTX2:RXPLLREFSEL_TESTCLK</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[1]">GTX2:DRP1C[1]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_DIVSEL_REF" title="GTX2:RXPLL_DIVSEL_REF[1]">GTX2:RXPLL_DIVSEL_REF[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[2]">GTX2:DRP1C[2]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_DIVSEL_REF" title="GTX2:RXPLL_DIVSEL_REF[2]">GTX2:RXPLL_DIVSEL_REF[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[3]">GTX2:DRP1C[3]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_DIVSEL_REF" title="GTX2:RXPLL_DIVSEL_REF[3]">GTX2:RXPLL_DIVSEL_REF[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[4]">GTX2:DRP1C[4]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_DIVSEL_REF" title="GTX2:RXPLL_DIVSEL_REF[4]">GTX2:RXPLL_DIVSEL_REF[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[5]">GTX2:DRP1C[5]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLL_DIVSEL_REF" title="GTX2:RXPLL_DIVSEL_REF[0]">GTX2:RXPLL_DIVSEL_REF[0]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[6]">GTX2:DRP1C[6]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLLREFSEL_MODE" title="GTX2:RXPLLREFSEL_MODE">GTX2:RXPLLREFSEL_MODE</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[7]">GTX2:DRP1C[7]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLLREFSEL_STATIC" title="GTX2:RXPLLREFSEL_STATIC[0]">GTX2:RXPLLREFSEL_STATIC[0]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[8]">GTX2:DRP1C[8]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLLREFSEL_STATIC" title="GTX2:RXPLLREFSEL_STATIC[1]">GTX2:RXPLLREFSEL_STATIC[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[9]">GTX2:DRP1C[9]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPLLREFSEL_STATIC" title="GTX2:RXPLLREFSEL_STATIC[2]">GTX2:RXPLLREFSEL_STATIC[2]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_PLLRXRESET" title="GTX2:A_PLLRXRESET">GTX2:A_PLLRXRESET</a><br><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[10]">GTX2:DRP1C[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_RXPLLLKDETEN" title="GTX2:A_RXPLLLKDETEN">GTX2:A_RXPLLLKDETEN</a><br><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[11]">GTX2:DRP1C[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_PLLCLKRXRESET" title="GTX2:A_PLLCLKRXRESET">GTX2:A_PLLCLKRXRESET</a><br><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[12]">GTX2:DRP1C[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[13]">GTX2:DRP1C[13]</a><br><a href="#bits-xc6v-GTX-GTX2:PLL_DRP_EN" title="GTX2:PLL_DRP_EN">GTX2:PLL_DRP_EN</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_RXPLLPOWERDOWN" title="GTX2:A_RXPLLPOWERDOWN">GTX2:A_RXPLLPOWERDOWN</a><br><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[14]">GTX2:DRP1C[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1C" title="GTX2:DRP1C[15]">GTX2:DRP1C[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_OVERSAMPLE_MODE" title="GTX2:RX_OVERSAMPLE_MODE">GTX2:RX_OVERSAMPLE_MODE</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[0]">GTX2:DRP1D[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[0]">GTX2:TXPLL_COM_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[1]">GTX2:DRP1D[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[1]">GTX2:TXPLL_COM_CFG[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[2]">GTX2:DRP1D[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[2]">GTX2:TXPLL_COM_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[3]">GTX2:DRP1D[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[3]">GTX2:TXPLL_COM_CFG[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[4]">GTX2:DRP1D[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[4]">GTX2:TXPLL_COM_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[5]">GTX2:DRP1D[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[5]">GTX2:TXPLL_COM_CFG[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[6]">GTX2:DRP1D[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[6]">GTX2:TXPLL_COM_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[7]">GTX2:DRP1D[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[7]">GTX2:TXPLL_COM_CFG[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[8]">GTX2:DRP1D[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[8]">GTX2:TXPLL_COM_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[9]">GTX2:DRP1D[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[9]">GTX2:TXPLL_COM_CFG[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[10]">GTX2:DRP1D[10]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[10]">GTX2:TXPLL_COM_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[11]">GTX2:DRP1D[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[11]">GTX2:TXPLL_COM_CFG[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[12]">GTX2:DRP1D[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[12]">GTX2:TXPLL_COM_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[13]">GTX2:DRP1D[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[13]">GTX2:TXPLL_COM_CFG[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[14]">GTX2:DRP1D[14]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[14]">GTX2:TXPLL_COM_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1D" title="GTX2:DRP1D[15]">GTX2:DRP1D[15]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[15]">GTX2:TXPLL_COM_CFG[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[0]">GTX2:DRP1E[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[16]">GTX2:TXPLL_COM_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[1]">GTX2:DRP1E[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[17]">GTX2:TXPLL_COM_CFG[17]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[2]">GTX2:DRP1E[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[18]">GTX2:TXPLL_COM_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[3]">GTX2:DRP1E[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[19]">GTX2:TXPLL_COM_CFG[19]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[4]">GTX2:DRP1E[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[20]">GTX2:TXPLL_COM_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[5]">GTX2:DRP1E[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[21]">GTX2:TXPLL_COM_CFG[21]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[6]">GTX2:DRP1E[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[22]">GTX2:TXPLL_COM_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[7]">GTX2:DRP1E[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_COM_CFG" title="GTX2:TXPLL_COM_CFG[23]">GTX2:TXPLL_COM_CFG[23]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[8]">GTX2:DRP1E[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_CP_CFG" title="GTX2:TXPLL_CP_CFG[0]">GTX2:TXPLL_CP_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[9]">GTX2:DRP1E[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_CP_CFG" title="GTX2:TXPLL_CP_CFG[1]">GTX2:TXPLL_CP_CFG[1]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[10]">GTX2:DRP1E[10]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_CP_CFG" title="GTX2:TXPLL_CP_CFG[2]">GTX2:TXPLL_CP_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[11]">GTX2:DRP1E[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_CP_CFG" title="GTX2:TXPLL_CP_CFG[3]">GTX2:TXPLL_CP_CFG[3]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[12]">GTX2:DRP1E[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_CP_CFG" title="GTX2:TXPLL_CP_CFG[4]">GTX2:TXPLL_CP_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[13]">GTX2:DRP1E[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_CP_CFG" title="GTX2:TXPLL_CP_CFG[5]">GTX2:TXPLL_CP_CFG[5]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[14]">GTX2:DRP1E[14]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_CP_CFG" title="GTX2:TXPLL_CP_CFG[6]">GTX2:TXPLL_CP_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1E" title="GTX2:DRP1E[15]">GTX2:DRP1E[15]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_CP_CFG" title="GTX2:TXPLL_CP_CFG[7]">GTX2:TXPLL_CP_CFG[7]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[0]">GTX2:DRP1F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[1]">GTX2:DRP1F[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_DIVSEL_FB" title="GTX2:TXPLL_DIVSEL_FB[1]">GTX2:TXPLL_DIVSEL_FB[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[2]">GTX2:DRP1F[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_DIVSEL_FB" title="GTX2:TXPLL_DIVSEL_FB[2]">GTX2:TXPLL_DIVSEL_FB[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[3]">GTX2:DRP1F[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_DIVSEL_FB" title="GTX2:TXPLL_DIVSEL_FB[3]">GTX2:TXPLL_DIVSEL_FB[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[4]">GTX2:DRP1F[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_DIVSEL_FB" title="GTX2:TXPLL_DIVSEL_FB[4]">GTX2:TXPLL_DIVSEL_FB[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[5]">GTX2:DRP1F[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_DIVSEL_FB" title="GTX2:TXPLL_DIVSEL_FB[0]">GTX2:TXPLL_DIVSEL_FB[0]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[6]">GTX2:DRP1F[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_DIVSEL45_FB" title="GTX2:TXPLL_DIVSEL45_FB">GTX2:TXPLL_DIVSEL45_FB</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[7]">GTX2:DRP1F[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_STARTUP_EN" title="GTX2:TXPLL_STARTUP_EN">GTX2:TXPLL_STARTUP_EN</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[8]">GTX2:DRP1F[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_CLK_SOURCE" title="GTX2:TX_CLK_SOURCE">GTX2:TX_CLK_SOURCE</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPOWERDOWN" title="GTX2:A_TXPOWERDOWN[0]">GTX2:A_TXPOWERDOWN[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[9]">GTX2:DRP1F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPOWERDOWN" title="GTX2:A_TXPOWERDOWN[1]">GTX2:A_TXPOWERDOWN[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[10]">GTX2:DRP1F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[11]">GTX2:DRP1F[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_LKDET_CFG" title="GTX2:TXPLL_LKDET_CFG[0]">GTX2:TXPLL_LKDET_CFG[0]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[12]">GTX2:DRP1F[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_LKDET_CFG" title="GTX2:TXPLL_LKDET_CFG[1]">GTX2:TXPLL_LKDET_CFG[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[13]">GTX2:DRP1F[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_LKDET_CFG" title="GTX2:TXPLL_LKDET_CFG[2]">GTX2:TXPLL_LKDET_CFG[2]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[14]">GTX2:DRP1F[14]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_DIVSEL_OUT" title="GTX2:TXPLL_DIVSEL_OUT[0]">GTX2:TXPLL_DIVSEL_OUT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP1F" title="GTX2:DRP1F[15]">GTX2:DRP1F[15]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_DIVSEL_OUT" title="GTX2:TXPLL_DIVSEL_OUT[1]">GTX2:TXPLL_DIVSEL_OUT[1]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 24</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[0]">GTX2:DRP20[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLLREFSEL_TESTCLK" title="GTX2:TXPLLREFSEL_TESTCLK">GTX2:TXPLLREFSEL_TESTCLK</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[1]">GTX2:DRP20[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_DIVSEL_REF" title="GTX2:TXPLL_DIVSEL_REF[1]">GTX2:TXPLL_DIVSEL_REF[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[2]">GTX2:DRP20[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_DIVSEL_REF" title="GTX2:TXPLL_DIVSEL_REF[2]">GTX2:TXPLL_DIVSEL_REF[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[3]">GTX2:DRP20[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_DIVSEL_REF" title="GTX2:TXPLL_DIVSEL_REF[3]">GTX2:TXPLL_DIVSEL_REF[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[4]">GTX2:DRP20[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_DIVSEL_REF" title="GTX2:TXPLL_DIVSEL_REF[4]">GTX2:TXPLL_DIVSEL_REF[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[5]">GTX2:DRP20[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_DIVSEL_REF" title="GTX2:TXPLL_DIVSEL_REF[0]">GTX2:TXPLL_DIVSEL_REF[0]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[6]">GTX2:DRP20[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLLREFSEL_MODE" title="GTX2:TXPLLREFSEL_MODE">GTX2:TXPLLREFSEL_MODE</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[7]">GTX2:DRP20[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLLREFSEL_STATIC" title="GTX2:TXPLLREFSEL_STATIC[0]">GTX2:TXPLLREFSEL_STATIC[0]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[8]">GTX2:DRP20[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLLREFSEL_STATIC" title="GTX2:TXPLLREFSEL_STATIC[1]">GTX2:TXPLLREFSEL_STATIC[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[9]">GTX2:DRP20[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLLREFSEL_STATIC" title="GTX2:TXPLLREFSEL_STATIC[2]">GTX2:TXPLLREFSEL_STATIC[2]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_PLLTXRESET" title="GTX2:A_PLLTXRESET">GTX2:A_PLLTXRESET</a><br><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[10]">GTX2:DRP20[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPLLLKDETEN" title="GTX2:A_TXPLLLKDETEN">GTX2:A_TXPLLLKDETEN</a><br><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[11]">GTX2:DRP20[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_PLLCLKTXRESET" title="GTX2:A_PLLCLKTXRESET">GTX2:A_PLLCLKTXRESET</a><br><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[12]">GTX2:DRP20[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[13]">GTX2:DRP20[13]</a><br><a href="#bits-xc6v-GTX-GTX2:PDELIDLE_DRP_EN" title="GTX2:PDELIDLE_DRP_EN">GTX2:PDELIDLE_DRP_EN</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPLLPOWERDOWN" title="GTX2:A_TXPLLPOWERDOWN">GTX2:A_TXPLLPOWERDOWN</a><br><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[14]">GTX2:DRP20[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP20" title="GTX2:DRP20[15]">GTX2:DRP20[15]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_OVERSAMPLE_MODE" title="GTX2:TX_OVERSAMPLE_MODE">GTX2:TX_OVERSAMPLE_MODE</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[0]">GTX2:DRP21[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DETECT_RX_CFG" title="GTX2:TX_DETECT_RX_CFG[0]">GTX2:TX_DETECT_RX_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[1]">GTX2:DRP21[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DETECT_RX_CFG" title="GTX2:TX_DETECT_RX_CFG[1]">GTX2:TX_DETECT_RX_CFG[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[2]">GTX2:DRP21[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DETECT_RX_CFG" title="GTX2:TX_DETECT_RX_CFG[2]">GTX2:TX_DETECT_RX_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[3]">GTX2:DRP21[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DETECT_RX_CFG" title="GTX2:TX_DETECT_RX_CFG[3]">GTX2:TX_DETECT_RX_CFG[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[4]">GTX2:DRP21[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DETECT_RX_CFG" title="GTX2:TX_DETECT_RX_CFG[4]">GTX2:TX_DETECT_RX_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[5]">GTX2:DRP21[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DETECT_RX_CFG" title="GTX2:TX_DETECT_RX_CFG[5]">GTX2:TX_DETECT_RX_CFG[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[6]">GTX2:DRP21[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DETECT_RX_CFG" title="GTX2:TX_DETECT_RX_CFG[6]">GTX2:TX_DETECT_RX_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[7]">GTX2:DRP21[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DETECT_RX_CFG" title="GTX2:TX_DETECT_RX_CFG[7]">GTX2:TX_DETECT_RX_CFG[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[8]">GTX2:DRP21[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DETECT_RX_CFG" title="GTX2:TX_DETECT_RX_CFG[8]">GTX2:TX_DETECT_RX_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[9]">GTX2:DRP21[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DETECT_RX_CFG" title="GTX2:TX_DETECT_RX_CFG[9]">GTX2:TX_DETECT_RX_CFG[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[10]">GTX2:DRP21[10]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DETECT_RX_CFG" title="GTX2:TX_DETECT_RX_CFG[10]">GTX2:TX_DETECT_RX_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[11]">GTX2:DRP21[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DETECT_RX_CFG" title="GTX2:TX_DETECT_RX_CFG[11]">GTX2:TX_DETECT_RX_CFG[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[12]">GTX2:DRP21[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DETECT_RX_CFG" title="GTX2:TX_DETECT_RX_CFG[12]">GTX2:TX_DETECT_RX_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[13]">GTX2:DRP21[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DETECT_RX_CFG" title="GTX2:TX_DETECT_RX_CFG[13]">GTX2:TX_DETECT_RX_CFG[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXELECIDLE" title="GTX2:A_TXELECIDLE">GTX2:A_TXELECIDLE</a><br><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[14]">GTX2:DRP21[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP21" title="GTX2:DRP21[15]">GTX2:DRP21[15]</a><br><a href="#bits-xc6v-GTX-GTX2:PCI_EXPRESS_MODE" title="GTX2:PCI_EXPRESS_MODE">GTX2:PCI_EXPRESS_MODE</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[0]">GTX2:DRP22[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[1]">GTX2:DRP22[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[2]">GTX2:DRP22[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[3]">GTX2:DRP22[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[4]">GTX2:DRP22[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[5]">GTX2:DRP22[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[6]">GTX2:DRP22[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[7]">GTX2:DRP22[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[8]">GTX2:DRP22[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[9]">GTX2:DRP22[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[10]">GTX2:DRP22[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[11]">GTX2:DRP22[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[12]">GTX2:DRP22[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[13]">GTX2:DRP22[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[14]">GTX2:DRP22[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP22" title="GTX2:DRP22[15]">GTX2:DRP22[15]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CAS_CLK_EN" title="GTX2:PMA_CAS_CLK_EN">GTX2:PMA_CAS_CLK_EN</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[0]">GTX2:DRP23[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_TO_P2" title="GTX2:TRANS_TIME_TO_P2[0]">GTX2:TRANS_TIME_TO_P2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[1]">GTX2:DRP23[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_TO_P2" title="GTX2:TRANS_TIME_TO_P2[1]">GTX2:TRANS_TIME_TO_P2[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[2]">GTX2:DRP23[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_TO_P2" title="GTX2:TRANS_TIME_TO_P2[2]">GTX2:TRANS_TIME_TO_P2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[3]">GTX2:DRP23[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_TO_P2" title="GTX2:TRANS_TIME_TO_P2[3]">GTX2:TRANS_TIME_TO_P2[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[4]">GTX2:DRP23[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_TO_P2" title="GTX2:TRANS_TIME_TO_P2[4]">GTX2:TRANS_TIME_TO_P2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[5]">GTX2:DRP23[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_TO_P2" title="GTX2:TRANS_TIME_TO_P2[5]">GTX2:TRANS_TIME_TO_P2[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[6]">GTX2:DRP23[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_TO_P2" title="GTX2:TRANS_TIME_TO_P2[6]">GTX2:TRANS_TIME_TO_P2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[7]">GTX2:DRP23[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_TO_P2" title="GTX2:TRANS_TIME_TO_P2[7]">GTX2:TRANS_TIME_TO_P2[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[8]">GTX2:DRP23[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_TO_P2" title="GTX2:TRANS_TIME_TO_P2[8]">GTX2:TRANS_TIME_TO_P2[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[9]">GTX2:DRP23[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_TO_P2" title="GTX2:TRANS_TIME_TO_P2[9]">GTX2:TRANS_TIME_TO_P2[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[10]">GTX2:DRP23[10]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_CLK25_DIVIDER" title="GTX2:TX_CLK25_DIVIDER[0]">GTX2:TX_CLK25_DIVIDER[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[11]">GTX2:DRP23[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_CLK25_DIVIDER" title="GTX2:TX_CLK25_DIVIDER[1]">GTX2:TX_CLK25_DIVIDER[1]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[12]">GTX2:DRP23[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_CLK25_DIVIDER" title="GTX2:TX_CLK25_DIVIDER[2]">GTX2:TX_CLK25_DIVIDER[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[13]">GTX2:DRP23[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_CLK25_DIVIDER" title="GTX2:TX_CLK25_DIVIDER[3]">GTX2:TX_CLK25_DIVIDER[3]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[14]">GTX2:DRP23[14]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_CLK25_DIVIDER" title="GTX2:TX_CLK25_DIVIDER[4]">GTX2:TX_CLK25_DIVIDER[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP23" title="GTX2:DRP23[15]">GTX2:DRP23[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[0]">GTX2:DRP24[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_FROM_P2" title="GTX2:TRANS_TIME_FROM_P2[0]">GTX2:TRANS_TIME_FROM_P2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[1]">GTX2:DRP24[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_FROM_P2" title="GTX2:TRANS_TIME_FROM_P2[1]">GTX2:TRANS_TIME_FROM_P2[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[2]">GTX2:DRP24[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_FROM_P2" title="GTX2:TRANS_TIME_FROM_P2[2]">GTX2:TRANS_TIME_FROM_P2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[3]">GTX2:DRP24[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_FROM_P2" title="GTX2:TRANS_TIME_FROM_P2[3]">GTX2:TRANS_TIME_FROM_P2[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[4]">GTX2:DRP24[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_FROM_P2" title="GTX2:TRANS_TIME_FROM_P2[4]">GTX2:TRANS_TIME_FROM_P2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[5]">GTX2:DRP24[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_FROM_P2" title="GTX2:TRANS_TIME_FROM_P2[5]">GTX2:TRANS_TIME_FROM_P2[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[6]">GTX2:DRP24[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_FROM_P2" title="GTX2:TRANS_TIME_FROM_P2[6]">GTX2:TRANS_TIME_FROM_P2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[7]">GTX2:DRP24[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_FROM_P2" title="GTX2:TRANS_TIME_FROM_P2[7]">GTX2:TRANS_TIME_FROM_P2[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[8]">GTX2:DRP24[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_FROM_P2" title="GTX2:TRANS_TIME_FROM_P2[8]">GTX2:TRANS_TIME_FROM_P2[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[9]">GTX2:DRP24[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_FROM_P2" title="GTX2:TRANS_TIME_FROM_P2[9]">GTX2:TRANS_TIME_FROM_P2[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[10]">GTX2:DRP24[10]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_FROM_P2" title="GTX2:TRANS_TIME_FROM_P2[10]">GTX2:TRANS_TIME_FROM_P2[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[11]">GTX2:DRP24[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_FROM_P2" title="GTX2:TRANS_TIME_FROM_P2[11]">GTX2:TRANS_TIME_FROM_P2[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:COM_BURST_VAL" title="GTX2:COM_BURST_VAL[0]">GTX2:COM_BURST_VAL[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[12]">GTX2:DRP24[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:COM_BURST_VAL" title="GTX2:COM_BURST_VAL[1]">GTX2:COM_BURST_VAL[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[13]">GTX2:DRP24[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:COM_BURST_VAL" title="GTX2:COM_BURST_VAL[2]">GTX2:COM_BURST_VAL[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[14]">GTX2:DRP24[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:COM_BURST_VAL" title="GTX2:COM_BURST_VAL[3]">GTX2:COM_BURST_VAL[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP24" title="GTX2:DRP24[15]">GTX2:DRP24[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[0]">GTX2:DRP25[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_NON_P2" title="GTX2:TRANS_TIME_NON_P2[0]">GTX2:TRANS_TIME_NON_P2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[1]">GTX2:DRP25[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_NON_P2" title="GTX2:TRANS_TIME_NON_P2[1]">GTX2:TRANS_TIME_NON_P2[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[2]">GTX2:DRP25[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_NON_P2" title="GTX2:TRANS_TIME_NON_P2[2]">GTX2:TRANS_TIME_NON_P2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[3]">GTX2:DRP25[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_NON_P2" title="GTX2:TRANS_TIME_NON_P2[3]">GTX2:TRANS_TIME_NON_P2[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[4]">GTX2:DRP25[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_NON_P2" title="GTX2:TRANS_TIME_NON_P2[4]">GTX2:TRANS_TIME_NON_P2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[5]">GTX2:DRP25[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_NON_P2" title="GTX2:TRANS_TIME_NON_P2[5]">GTX2:TRANS_TIME_NON_P2[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[6]">GTX2:DRP25[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_NON_P2" title="GTX2:TRANS_TIME_NON_P2[6]">GTX2:TRANS_TIME_NON_P2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[7]">GTX2:DRP25[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_NON_P2" title="GTX2:TRANS_TIME_NON_P2[7]">GTX2:TRANS_TIME_NON_P2[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:CM_TRIM" title="GTX2:CM_TRIM[0]">GTX2:CM_TRIM[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[8]">GTX2:DRP25[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:CM_TRIM" title="GTX2:CM_TRIM[1]">GTX2:CM_TRIM[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[9]">GTX2:DRP25[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_RXPOLARITY" title="GTX2:A_RXPOLARITY">GTX2:A_RXPOLARITY</a><br><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[10]">GTX2:DRP25[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPOLARITY" title="GTX2:A_TXPOLARITY">GTX2:A_TXPOLARITY</a><br><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[11]">GTX2:DRP25[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[12]">GTX2:DRP25[12]</a><br><a href="#bits-xc6v-GTX-GTX2:POLARITY_DRP_EN" title="GTX2:POLARITY_DRP_EN">GTX2:POLARITY_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_RXPMASETPHASE" title="GTX2:A_RXPMASETPHASE">GTX2:A_RXPMASETPHASE</a><br><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[13]">GTX2:DRP25[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_RXENPMAPHASEALIGN" title="GTX2:A_RXENPMAPHASEALIGN">GTX2:A_RXENPMAPHASEALIGN</a><br><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[14]">GTX2:DRP25[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP25" title="GTX2:DRP25[15]">GTX2:DRP25[15]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_PMADATA_OPT" title="GTX2:TX_PMADATA_OPT">GTX2:TX_PMADATA_OPT</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[0]">GTX2:DRP26[0]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_WAKE" title="GTX2:SATA_MAX_WAKE[0]">GTX2:SATA_MAX_WAKE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[1]">GTX2:DRP26[1]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_WAKE" title="GTX2:SATA_MAX_WAKE[1]">GTX2:SATA_MAX_WAKE[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[2]">GTX2:DRP26[2]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_WAKE" title="GTX2:SATA_MAX_WAKE[2]">GTX2:SATA_MAX_WAKE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[3]">GTX2:DRP26[3]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_WAKE" title="GTX2:SATA_MAX_WAKE[3]">GTX2:SATA_MAX_WAKE[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[4]">GTX2:DRP26[4]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_WAKE" title="GTX2:SATA_MAX_WAKE[4]">GTX2:SATA_MAX_WAKE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[5]">GTX2:DRP26[5]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_WAKE" title="GTX2:SATA_MAX_WAKE[5]">GTX2:SATA_MAX_WAKE[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[6]">GTX2:DRP26[6]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_WAKE" title="GTX2:SATA_MIN_WAKE[0]">GTX2:SATA_MIN_WAKE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[7]">GTX2:DRP26[7]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_WAKE" title="GTX2:SATA_MIN_WAKE[1]">GTX2:SATA_MIN_WAKE[1]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[8]">GTX2:DRP26[8]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_WAKE" title="GTX2:SATA_MIN_WAKE[2]">GTX2:SATA_MIN_WAKE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[9]">GTX2:DRP26[9]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_WAKE" title="GTX2:SATA_MIN_WAKE[3]">GTX2:SATA_MIN_WAKE[3]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[10]">GTX2:DRP26[10]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_WAKE" title="GTX2:SATA_MIN_WAKE[4]">GTX2:SATA_MIN_WAKE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[11]">GTX2:DRP26[11]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_WAKE" title="GTX2:SATA_MIN_WAKE[5]">GTX2:SATA_MIN_WAKE[5]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[12]">GTX2:DRP26[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_SATA" title="GTX2:TXPLL_SATA[0]">GTX2:TXPLL_SATA[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[13]">GTX2:DRP26[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TXPLL_SATA" title="GTX2:TXPLL_SATA[1]">GTX2:TXPLL_SATA[1]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:BGTEST_CFG" title="GTX2:BGTEST_CFG[0]">GTX2:BGTEST_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[14]">GTX2:DRP26[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:BGTEST_CFG" title="GTX2:BGTEST_CFG[1]">GTX2:BGTEST_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP26" title="GTX2:DRP26[15]">GTX2:DRP26[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[0]">GTX2:DRP27[0]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_INIT" title="GTX2:SATA_MAX_INIT[0]">GTX2:SATA_MAX_INIT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[1]">GTX2:DRP27[1]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_INIT" title="GTX2:SATA_MAX_INIT[1]">GTX2:SATA_MAX_INIT[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[2]">GTX2:DRP27[2]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_INIT" title="GTX2:SATA_MAX_INIT[2]">GTX2:SATA_MAX_INIT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[3]">GTX2:DRP27[3]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_INIT" title="GTX2:SATA_MAX_INIT[3]">GTX2:SATA_MAX_INIT[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[4]">GTX2:DRP27[4]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_INIT" title="GTX2:SATA_MAX_INIT[4]">GTX2:SATA_MAX_INIT[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[5]">GTX2:DRP27[5]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_INIT" title="GTX2:SATA_MAX_INIT[5]">GTX2:SATA_MAX_INIT[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[6]">GTX2:DRP27[6]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_INIT" title="GTX2:SATA_MIN_INIT[0]">GTX2:SATA_MIN_INIT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[7]">GTX2:DRP27[7]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_INIT" title="GTX2:SATA_MIN_INIT[1]">GTX2:SATA_MIN_INIT[1]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[8]">GTX2:DRP27[8]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_INIT" title="GTX2:SATA_MIN_INIT[2]">GTX2:SATA_MIN_INIT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[9]">GTX2:DRP27[9]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_INIT" title="GTX2:SATA_MIN_INIT[3]">GTX2:SATA_MIN_INIT[3]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[10]">GTX2:DRP27[10]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_INIT" title="GTX2:SATA_MIN_INIT[4]">GTX2:SATA_MIN_INIT[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[11]">GTX2:DRP27[11]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_INIT" title="GTX2:SATA_MIN_INIT[5]">GTX2:SATA_MIN_INIT[5]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[12]">GTX2:DRP27[12]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_IDLE_VAL" title="GTX2:SATA_IDLE_VAL[0]">GTX2:SATA_IDLE_VAL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[13]">GTX2:DRP27[13]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_IDLE_VAL" title="GTX2:SATA_IDLE_VAL[1]">GTX2:SATA_IDLE_VAL[1]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[14]">GTX2:DRP27[14]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_IDLE_VAL" title="GTX2:SATA_IDLE_VAL[2]">GTX2:SATA_IDLE_VAL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP27" title="GTX2:DRP27[15]">GTX2:DRP27[15]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_EN_RATE_RESET_BUF" title="GTX2:TX_EN_RATE_RESET_BUF">GTX2:TX_EN_RATE_RESET_BUF</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 25</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[0]">GTX2:DRP28[0]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_BURST" title="GTX2:SATA_MAX_BURST[0]">GTX2:SATA_MAX_BURST[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[1]">GTX2:DRP28[1]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_BURST" title="GTX2:SATA_MAX_BURST[1]">GTX2:SATA_MAX_BURST[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[2]">GTX2:DRP28[2]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_BURST" title="GTX2:SATA_MAX_BURST[2]">GTX2:SATA_MAX_BURST[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[3]">GTX2:DRP28[3]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_BURST" title="GTX2:SATA_MAX_BURST[3]">GTX2:SATA_MAX_BURST[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[4]">GTX2:DRP28[4]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_BURST" title="GTX2:SATA_MAX_BURST[4]">GTX2:SATA_MAX_BURST[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[5]">GTX2:DRP28[5]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MAX_BURST" title="GTX2:SATA_MAX_BURST[5]">GTX2:SATA_MAX_BURST[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[6]">GTX2:DRP28[6]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_BURST" title="GTX2:SATA_MIN_BURST[0]">GTX2:SATA_MIN_BURST[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[7]">GTX2:DRP28[7]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_BURST" title="GTX2:SATA_MIN_BURST[1]">GTX2:SATA_MIN_BURST[1]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[8]">GTX2:DRP28[8]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_BURST" title="GTX2:SATA_MIN_BURST[2]">GTX2:SATA_MIN_BURST[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[9]">GTX2:DRP28[9]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_BURST" title="GTX2:SATA_MIN_BURST[3]">GTX2:SATA_MIN_BURST[3]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[10]">GTX2:DRP28[10]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_BURST" title="GTX2:SATA_MIN_BURST[4]">GTX2:SATA_MIN_BURST[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[11]">GTX2:DRP28[11]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_MIN_BURST" title="GTX2:SATA_MIN_BURST[5]">GTX2:SATA_MIN_BURST[5]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[12]">GTX2:DRP28[12]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_BURST_VAL" title="GTX2:SATA_BURST_VAL[0]">GTX2:SATA_BURST_VAL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[13]">GTX2:DRP28[13]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_BURST_VAL" title="GTX2:SATA_BURST_VAL[1]">GTX2:SATA_BURST_VAL[1]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[14]">GTX2:DRP28[14]</a><br><a href="#bits-xc6v-GTX-GTX2:SATA_BURST_VAL" title="GTX2:SATA_BURST_VAL[2]">GTX2:SATA_BURST_VAL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP28" title="GTX2:DRP28[15]">GTX2:DRP28[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[0]">GTX2:DRP29[0]</a><br><a href="#bits-xc6v-GTX-GTX2:SAS_MAX_COMSAS" title="GTX2:SAS_MAX_COMSAS[0]">GTX2:SAS_MAX_COMSAS[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[1]">GTX2:DRP29[1]</a><br><a href="#bits-xc6v-GTX-GTX2:SAS_MAX_COMSAS" title="GTX2:SAS_MAX_COMSAS[1]">GTX2:SAS_MAX_COMSAS[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[2]">GTX2:DRP29[2]</a><br><a href="#bits-xc6v-GTX-GTX2:SAS_MAX_COMSAS" title="GTX2:SAS_MAX_COMSAS[2]">GTX2:SAS_MAX_COMSAS[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[3]">GTX2:DRP29[3]</a><br><a href="#bits-xc6v-GTX-GTX2:SAS_MAX_COMSAS" title="GTX2:SAS_MAX_COMSAS[3]">GTX2:SAS_MAX_COMSAS[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[4]">GTX2:DRP29[4]</a><br><a href="#bits-xc6v-GTX-GTX2:SAS_MAX_COMSAS" title="GTX2:SAS_MAX_COMSAS[4]">GTX2:SAS_MAX_COMSAS[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[5]">GTX2:DRP29[5]</a><br><a href="#bits-xc6v-GTX-GTX2:SAS_MAX_COMSAS" title="GTX2:SAS_MAX_COMSAS[5]">GTX2:SAS_MAX_COMSAS[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[6]">GTX2:DRP29[6]</a><br><a href="#bits-xc6v-GTX-GTX2:SAS_MIN_COMSAS" title="GTX2:SAS_MIN_COMSAS[0]">GTX2:SAS_MIN_COMSAS[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[7]">GTX2:DRP29[7]</a><br><a href="#bits-xc6v-GTX-GTX2:SAS_MIN_COMSAS" title="GTX2:SAS_MIN_COMSAS[1]">GTX2:SAS_MIN_COMSAS[1]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[8]">GTX2:DRP29[8]</a><br><a href="#bits-xc6v-GTX-GTX2:SAS_MIN_COMSAS" title="GTX2:SAS_MIN_COMSAS[2]">GTX2:SAS_MIN_COMSAS[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[9]">GTX2:DRP29[9]</a><br><a href="#bits-xc6v-GTX-GTX2:SAS_MIN_COMSAS" title="GTX2:SAS_MIN_COMSAS[3]">GTX2:SAS_MIN_COMSAS[3]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[10]">GTX2:DRP29[10]</a><br><a href="#bits-xc6v-GTX-GTX2:SAS_MIN_COMSAS" title="GTX2:SAS_MIN_COMSAS[4]">GTX2:SAS_MIN_COMSAS[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[11]">GTX2:DRP29[11]</a><br><a href="#bits-xc6v-GTX-GTX2:SAS_MIN_COMSAS" title="GTX2:SAS_MIN_COMSAS[5]">GTX2:SAS_MIN_COMSAS[5]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPMASETPHASE" title="GTX2:A_TXPMASETPHASE">GTX2:A_TXPMASETPHASE</a><br><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[12]">GTX2:DRP29[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXENPMAPHASEALIGN" title="GTX2:A_TXENPMAPHASEALIGN">GTX2:A_TXENPMAPHASEALIGN</a><br><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[13]">GTX2:DRP29[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_RXENSAMPLEALIGN" title="GTX2:A_RXENSAMPLEALIGN">GTX2:A_RXENSAMPLEALIGN</a><br><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[14]">GTX2:DRP29[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP29" title="GTX2:DRP29[15]">GTX2:DRP29[15]</a><br><a href="#bits-xc6v-GTX-GTX2:PHASEALIGN_DRP_EN" title="GTX2:PHASEALIGN_DRP_EN">GTX2:PHASEALIGN_DRP_EN</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[0]">GTX2:DRP2A[0]</a><br><a href="#bits-xc6v-GTX-GTX2:LOOPBACK_DRP_EN" title="GTX2:LOOPBACK_DRP_EN">GTX2:LOOPBACK_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_LOOPBACK" title="GTX2:A_LOOPBACK[0]">GTX2:A_LOOPBACK[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[1]">GTX2:DRP2A[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_LOOPBACK" title="GTX2:A_LOOPBACK[1]">GTX2:A_LOOPBACK[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[2]">GTX2:DRP2A[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_LOOPBACK" title="GTX2:A_LOOPBACK[2]">GTX2:A_LOOPBACK[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[3]">GTX2:DRP2A[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[4]">GTX2:DRP2A[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_RXENPRBSTST" title="GTX2:A_RXENPRBSTST[0]">GTX2:A_RXENPRBSTST[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[5]">GTX2:DRP2A[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_RXENPRBSTST" title="GTX2:A_RXENPRBSTST[1]">GTX2:A_RXENPRBSTST[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[6]">GTX2:DRP2A[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_RXENPRBSTST" title="GTX2:A_RXENPRBSTST[2]">GTX2:A_RXENPRBSTST[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[7]">GTX2:DRP2A[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[8]">GTX2:DRP2A[8]</a><br><a href="#bits-xc6v-GTX-GTX2:RXPRBSERR_LOOPBACK" title="GTX2:RXPRBSERR_LOOPBACK">GTX2:RXPRBSERR_LOOPBACK</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[9]">GTX2:DRP2A[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPRBSFORCEERR" title="GTX2:A_TXPRBSFORCEERR">GTX2:A_TXPRBSFORCEERR</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[10]">GTX2:DRP2A[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXENPRBSTST" title="GTX2:A_TXENPRBSTST[0]">GTX2:A_TXENPRBSTST[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[11]">GTX2:DRP2A[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXENPRBSTST" title="GTX2:A_TXENPRBSTST[1]">GTX2:A_TXENPRBSTST[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[12]">GTX2:DRP2A[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXENPRBSTST" title="GTX2:A_TXENPRBSTST[2]">GTX2:A_TXENPRBSTST[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[13]">GTX2:DRP2A[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_PRBSCNTRESET" title="GTX2:A_PRBSCNTRESET">GTX2:A_PRBSCNTRESET</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[14]">GTX2:DRP2A[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2A" title="GTX2:DRP2A[15]">GTX2:DRP2A[15]</a><br><a href="#bits-xc6v-GTX-GTX2:PRBS_DRP_EN" title="GTX2:PRBS_DRP_EN">GTX2:PRBS_DRP_EN</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP1" title="GTX2:A_DFETAP1[0]">GTX2:A_DFETAP1[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[0]">GTX2:DRP2B[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP1" title="GTX2:A_DFETAP1[1]">GTX2:A_DFETAP1[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[1]">GTX2:DRP2B[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP1" title="GTX2:A_DFETAP1[2]">GTX2:A_DFETAP1[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[2]">GTX2:DRP2B[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP1" title="GTX2:A_DFETAP1[3]">GTX2:A_DFETAP1[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[3]">GTX2:DRP2B[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP1" title="GTX2:A_DFETAP1[4]">GTX2:A_DFETAP1[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[4]">GTX2:DRP2B[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP3" title="GTX2:A_DFETAP3[0]">GTX2:A_DFETAP3[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[5]">GTX2:DRP2B[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP3" title="GTX2:A_DFETAP3[1]">GTX2:A_DFETAP3[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[6]">GTX2:DRP2B[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP3" title="GTX2:A_DFETAP3[2]">GTX2:A_DFETAP3[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[7]">GTX2:DRP2B[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP3" title="GTX2:A_DFETAP3[3]">GTX2:A_DFETAP3[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[8]">GTX2:DRP2B[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[9]">GTX2:DRP2B[9]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EN_IDLE_HOLD_CDR" title="GTX2:RX_EN_IDLE_HOLD_CDR">GTX2:RX_EN_IDLE_HOLD_CDR</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[10]">GTX2:DRP2B[10]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EN_IDLE_RESET_FR" title="GTX2:RX_EN_IDLE_RESET_FR">GTX2:RX_EN_IDLE_RESET_FR</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[11]">GTX2:DRP2B[11]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EN_IDLE_HOLD_DFE" title="GTX2:RX_EN_IDLE_HOLD_DFE">GTX2:RX_EN_IDLE_HOLD_DFE</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[12]">GTX2:DRP2B[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[13]">GTX2:DRP2B[13]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_DFEDLYOVRD" title="GTX2:A_DFEDLYOVRD">GTX2:A_DFEDLYOVRD</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[14]">GTX2:DRP2B[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAPOVRD" title="GTX2:A_DFETAPOVRD">GTX2:A_DFETAPOVRD</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2B" title="GTX2:DRP2B[15]">GTX2:DRP2B[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP2" title="GTX2:A_DFETAP2[0]">GTX2:A_DFETAP2[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[0]">GTX2:DRP2C[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP2" title="GTX2:A_DFETAP2[1]">GTX2:A_DFETAP2[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[1]">GTX2:DRP2C[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP2" title="GTX2:A_DFETAP2[2]">GTX2:A_DFETAP2[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[2]">GTX2:DRP2C[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP2" title="GTX2:A_DFETAP2[3]">GTX2:A_DFETAP2[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[3]">GTX2:DRP2C[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP2" title="GTX2:A_DFETAP2[4]">GTX2:A_DFETAP2[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[4]">GTX2:DRP2C[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP4" title="GTX2:A_DFETAP4[0]">GTX2:A_DFETAP4[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[5]">GTX2:DRP2C[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP4" title="GTX2:A_DFETAP4[1]">GTX2:A_DFETAP4[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[6]">GTX2:DRP2C[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP4" title="GTX2:A_DFETAP4[2]">GTX2:A_DFETAP4[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[7]">GTX2:DRP2C[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_DFETAP4" title="GTX2:A_DFETAP4[3]">GTX2:A_DFETAP4[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[8]">GTX2:DRP2C[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_DFECLKDLYADJ" title="GTX2:A_DFECLKDLYADJ[0]">GTX2:A_DFECLKDLYADJ[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[9]">GTX2:DRP2C[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_DFECLKDLYADJ" title="GTX2:A_DFECLKDLYADJ[1]">GTX2:A_DFECLKDLYADJ[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[10]">GTX2:DRP2C[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_DFECLKDLYADJ" title="GTX2:A_DFECLKDLYADJ[2]">GTX2:A_DFECLKDLYADJ[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[11]">GTX2:DRP2C[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_DFECLKDLYADJ" title="GTX2:A_DFECLKDLYADJ[3]">GTX2:A_DFECLKDLYADJ[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[12]">GTX2:DRP2C[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_DFECLKDLYADJ" title="GTX2:A_DFECLKDLYADJ[4]">GTX2:A_DFECLKDLYADJ[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[13]">GTX2:DRP2C[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_DFECLKDLYADJ" title="GTX2:A_DFECLKDLYADJ[5]">GTX2:A_DFECLKDLYADJ[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[14]">GTX2:DRP2C[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DFE_DRP_EN" title="GTX2:DFE_DRP_EN">GTX2:DFE_DRP_EN</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2C" title="GTX2:DRP2C[15]">GTX2:DRP2C[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DFE_CFG" title="GTX2:DFE_CFG[0]">GTX2:DFE_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[0]">GTX2:DRP2D[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DFE_CFG" title="GTX2:DFE_CFG[1]">GTX2:DFE_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[1]">GTX2:DRP2D[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DFE_CFG" title="GTX2:DFE_CFG[2]">GTX2:DFE_CFG[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[2]">GTX2:DRP2D[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DFE_CFG" title="GTX2:DFE_CFG[3]">GTX2:DFE_CFG[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[3]">GTX2:DRP2D[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DFE_CFG" title="GTX2:DFE_CFG[4]">GTX2:DFE_CFG[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[4]">GTX2:DRP2D[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DFE_CFG" title="GTX2:DFE_CFG[5]">GTX2:DFE_CFG[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[5]">GTX2:DRP2D[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DFE_CFG" title="GTX2:DFE_CFG[6]">GTX2:DFE_CFG[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[6]">GTX2:DRP2D[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DFE_CFG" title="GTX2:DFE_CFG[7]">GTX2:DFE_CFG[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[7]">GTX2:DRP2D[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[8]">GTX2:DRP2D[8]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EYE_OFFSET" title="GTX2:RX_EYE_OFFSET[0]">GTX2:RX_EYE_OFFSET[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[9]">GTX2:DRP2D[9]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EYE_OFFSET" title="GTX2:RX_EYE_OFFSET[1]">GTX2:RX_EYE_OFFSET[1]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[10]">GTX2:DRP2D[10]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EYE_OFFSET" title="GTX2:RX_EYE_OFFSET[2]">GTX2:RX_EYE_OFFSET[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[11]">GTX2:DRP2D[11]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EYE_OFFSET" title="GTX2:RX_EYE_OFFSET[3]">GTX2:RX_EYE_OFFSET[3]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[12]">GTX2:DRP2D[12]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EYE_OFFSET" title="GTX2:RX_EYE_OFFSET[4]">GTX2:RX_EYE_OFFSET[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[13]">GTX2:DRP2D[13]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EYE_OFFSET" title="GTX2:RX_EYE_OFFSET[5]">GTX2:RX_EYE_OFFSET[5]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[14]">GTX2:DRP2D[14]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EYE_OFFSET" title="GTX2:RX_EYE_OFFSET[6]">GTX2:RX_EYE_OFFSET[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2D" title="GTX2:DRP2D[15]">GTX2:DRP2D[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EYE_OFFSET" title="GTX2:RX_EYE_OFFSET[7]">GTX2:RX_EYE_OFFSET[7]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[0]">GTX2:DRP2E[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TERMINATION_CTRL" title="GTX2:TERMINATION_CTRL[0]">GTX2:TERMINATION_CTRL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[1]">GTX2:DRP2E[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TERMINATION_CTRL" title="GTX2:TERMINATION_CTRL[1]">GTX2:TERMINATION_CTRL[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[2]">GTX2:DRP2E[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TERMINATION_CTRL" title="GTX2:TERMINATION_CTRL[2]">GTX2:TERMINATION_CTRL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[3]">GTX2:DRP2E[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TERMINATION_CTRL" title="GTX2:TERMINATION_CTRL[3]">GTX2:TERMINATION_CTRL[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[4]">GTX2:DRP2E[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TERMINATION_CTRL" title="GTX2:TERMINATION_CTRL[4]">GTX2:TERMINATION_CTRL[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[5]">GTX2:DRP2E[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[6]">GTX2:DRP2E[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TERMINATION_OVRD" title="GTX2:TERMINATION_OVRD">GTX2:TERMINATION_OVRD</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[7]">GTX2:DRP2E[7]</a><br><a href="#bits-xc6v-GTX-GTX2:RCV_TERM_GND" title="GTX2:RCV_TERM_GND">GTX2:RCV_TERM_GND</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[8]">GTX2:DRP2E[8]</a><br><a href="#bits-xc6v-GTX-GTX2:RCV_TERM_VTTRX" title="GTX2:RCV_TERM_VTTRX">GTX2:RCV_TERM_VTTRX</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[9]">GTX2:DRP2E[9]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EYE_SCANMODE" title="GTX2:RX_EYE_SCANMODE[0]">GTX2:RX_EYE_SCANMODE[0]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[10]">GTX2:DRP2E[10]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EYE_SCANMODE" title="GTX2:RX_EYE_SCANMODE[1]">GTX2:RX_EYE_SCANMODE[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DFE_CAL_TIME" title="GTX2:DFE_CAL_TIME[0]">GTX2:DFE_CAL_TIME[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[11]">GTX2:DRP2E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DFE_CAL_TIME" title="GTX2:DFE_CAL_TIME[1]">GTX2:DFE_CAL_TIME[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[12]">GTX2:DRP2E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DFE_CAL_TIME" title="GTX2:DFE_CAL_TIME[2]">GTX2:DFE_CAL_TIME[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[13]">GTX2:DRP2E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DFE_CAL_TIME" title="GTX2:DFE_CAL_TIME[3]">GTX2:DFE_CAL_TIME[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[14]">GTX2:DRP2E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DFE_CAL_TIME" title="GTX2:DFE_CAL_TIME[4]">GTX2:DFE_CAL_TIME[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2E" title="GTX2:DRP2E[15]">GTX2:DRP2E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:COMMA_10B_ENABLE" title="GTX2:COMMA_10B_ENABLE[0]">GTX2:COMMA_10B_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[0]">GTX2:DRP2F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:COMMA_10B_ENABLE" title="GTX2:COMMA_10B_ENABLE[1]">GTX2:COMMA_10B_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[1]">GTX2:DRP2F[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:COMMA_10B_ENABLE" title="GTX2:COMMA_10B_ENABLE[2]">GTX2:COMMA_10B_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[2]">GTX2:DRP2F[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:COMMA_10B_ENABLE" title="GTX2:COMMA_10B_ENABLE[3]">GTX2:COMMA_10B_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[3]">GTX2:DRP2F[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:COMMA_10B_ENABLE" title="GTX2:COMMA_10B_ENABLE[4]">GTX2:COMMA_10B_ENABLE[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[4]">GTX2:DRP2F[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:COMMA_10B_ENABLE" title="GTX2:COMMA_10B_ENABLE[5]">GTX2:COMMA_10B_ENABLE[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[5]">GTX2:DRP2F[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:COMMA_10B_ENABLE" title="GTX2:COMMA_10B_ENABLE[6]">GTX2:COMMA_10B_ENABLE[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[6]">GTX2:DRP2F[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:COMMA_10B_ENABLE" title="GTX2:COMMA_10B_ENABLE[7]">GTX2:COMMA_10B_ENABLE[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[7]">GTX2:DRP2F[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:COMMA_10B_ENABLE" title="GTX2:COMMA_10B_ENABLE[8]">GTX2:COMMA_10B_ENABLE[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[8]">GTX2:DRP2F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:COMMA_10B_ENABLE" title="GTX2:COMMA_10B_ENABLE[9]">GTX2:COMMA_10B_ENABLE[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[9]">GTX2:DRP2F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:COMMA_DOUBLE" title="GTX2:COMMA_DOUBLE">GTX2:COMMA_DOUBLE</a><br><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[10]">GTX2:DRP2F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[11]">GTX2:DRP2F[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_IDLE_ASSERT_DELAY" title="GTX2:TX_IDLE_ASSERT_DELAY[0]">GTX2:TX_IDLE_ASSERT_DELAY[0]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[12]">GTX2:DRP2F[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_IDLE_ASSERT_DELAY" title="GTX2:TX_IDLE_ASSERT_DELAY[1]">GTX2:TX_IDLE_ASSERT_DELAY[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[13]">GTX2:DRP2F[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_IDLE_ASSERT_DELAY" title="GTX2:TX_IDLE_ASSERT_DELAY[2]">GTX2:TX_IDLE_ASSERT_DELAY[2]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[14]">GTX2:DRP2F[14]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_XCLK_SEL" title="GTX2:TX_XCLK_SEL">GTX2:TX_XCLK_SEL</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP2F" title="GTX2:DRP2F[15]">GTX2:DRP2F[15]</a><br><a href="#bits-xc6v-GTX-GTX2:TXGEARBOX_USE" title="GTX2:TXGEARBOX_USE">GTX2:TXGEARBOX_USE</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 26</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[0]">GTX2:DRP30[0]</a><br><a href="#bits-xc6v-GTX-GTX2:MCOMMA_10B_VALUE" title="GTX2:MCOMMA_10B_VALUE[0]">GTX2:MCOMMA_10B_VALUE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[1]">GTX2:DRP30[1]</a><br><a href="#bits-xc6v-GTX-GTX2:MCOMMA_10B_VALUE" title="GTX2:MCOMMA_10B_VALUE[1]">GTX2:MCOMMA_10B_VALUE[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[2]">GTX2:DRP30[2]</a><br><a href="#bits-xc6v-GTX-GTX2:MCOMMA_10B_VALUE" title="GTX2:MCOMMA_10B_VALUE[2]">GTX2:MCOMMA_10B_VALUE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[3]">GTX2:DRP30[3]</a><br><a href="#bits-xc6v-GTX-GTX2:MCOMMA_10B_VALUE" title="GTX2:MCOMMA_10B_VALUE[3]">GTX2:MCOMMA_10B_VALUE[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[4]">GTX2:DRP30[4]</a><br><a href="#bits-xc6v-GTX-GTX2:MCOMMA_10B_VALUE" title="GTX2:MCOMMA_10B_VALUE[4]">GTX2:MCOMMA_10B_VALUE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[5]">GTX2:DRP30[5]</a><br><a href="#bits-xc6v-GTX-GTX2:MCOMMA_10B_VALUE" title="GTX2:MCOMMA_10B_VALUE[5]">GTX2:MCOMMA_10B_VALUE[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[6]">GTX2:DRP30[6]</a><br><a href="#bits-xc6v-GTX-GTX2:MCOMMA_10B_VALUE" title="GTX2:MCOMMA_10B_VALUE[6]">GTX2:MCOMMA_10B_VALUE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[7]">GTX2:DRP30[7]</a><br><a href="#bits-xc6v-GTX-GTX2:MCOMMA_10B_VALUE" title="GTX2:MCOMMA_10B_VALUE[7]">GTX2:MCOMMA_10B_VALUE[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[8]">GTX2:DRP30[8]</a><br><a href="#bits-xc6v-GTX-GTX2:MCOMMA_10B_VALUE" title="GTX2:MCOMMA_10B_VALUE[8]">GTX2:MCOMMA_10B_VALUE[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[9]">GTX2:DRP30[9]</a><br><a href="#bits-xc6v-GTX-GTX2:MCOMMA_10B_VALUE" title="GTX2:MCOMMA_10B_VALUE[9]">GTX2:MCOMMA_10B_VALUE[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[10]">GTX2:DRP30[10]</a><br><a href="#bits-xc6v-GTX-GTX2:MCOMMA_DETECT" title="GTX2:MCOMMA_DETECT">GTX2:MCOMMA_DETECT</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[11]">GTX2:DRP30[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_IDLE_DEASSERT_DELAY" title="GTX2:TX_IDLE_DEASSERT_DELAY[0]">GTX2:TX_IDLE_DEASSERT_DELAY[0]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[12]">GTX2:DRP30[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_IDLE_DEASSERT_DELAY" title="GTX2:TX_IDLE_DEASSERT_DELAY[1]">GTX2:TX_IDLE_DEASSERT_DELAY[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[13]">GTX2:DRP30[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_IDLE_DEASSERT_DELAY" title="GTX2:TX_IDLE_DEASSERT_DELAY[2]">GTX2:TX_IDLE_DEASSERT_DELAY[2]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[14]">GTX2:DRP30[14]</a><br><a href="#bits-xc6v-GTX-GTX2:INV.TXUSRCLK" title="~GTX2:INV.TXUSRCLK">~GTX2:INV.TXUSRCLK</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP30" title="GTX2:DRP30[15]">GTX2:DRP30[15]</a><br><a href="#bits-xc6v-GTX-GTX2:INV.TXUSRCLK2" title="~GTX2:INV.TXUSRCLK2">~GTX2:INV.TXUSRCLK2</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[0]">GTX2:DRP31[0]</a><br><a href="#bits-xc6v-GTX-GTX2:PCOMMA_10B_VALUE" title="GTX2:PCOMMA_10B_VALUE[0]">GTX2:PCOMMA_10B_VALUE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[1]">GTX2:DRP31[1]</a><br><a href="#bits-xc6v-GTX-GTX2:PCOMMA_10B_VALUE" title="GTX2:PCOMMA_10B_VALUE[1]">GTX2:PCOMMA_10B_VALUE[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[2]">GTX2:DRP31[2]</a><br><a href="#bits-xc6v-GTX-GTX2:PCOMMA_10B_VALUE" title="GTX2:PCOMMA_10B_VALUE[2]">GTX2:PCOMMA_10B_VALUE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[3]">GTX2:DRP31[3]</a><br><a href="#bits-xc6v-GTX-GTX2:PCOMMA_10B_VALUE" title="GTX2:PCOMMA_10B_VALUE[3]">GTX2:PCOMMA_10B_VALUE[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[4]">GTX2:DRP31[4]</a><br><a href="#bits-xc6v-GTX-GTX2:PCOMMA_10B_VALUE" title="GTX2:PCOMMA_10B_VALUE[4]">GTX2:PCOMMA_10B_VALUE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[5]">GTX2:DRP31[5]</a><br><a href="#bits-xc6v-GTX-GTX2:PCOMMA_10B_VALUE" title="GTX2:PCOMMA_10B_VALUE[5]">GTX2:PCOMMA_10B_VALUE[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[6]">GTX2:DRP31[6]</a><br><a href="#bits-xc6v-GTX-GTX2:PCOMMA_10B_VALUE" title="GTX2:PCOMMA_10B_VALUE[6]">GTX2:PCOMMA_10B_VALUE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[7]">GTX2:DRP31[7]</a><br><a href="#bits-xc6v-GTX-GTX2:PCOMMA_10B_VALUE" title="GTX2:PCOMMA_10B_VALUE[7]">GTX2:PCOMMA_10B_VALUE[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[8]">GTX2:DRP31[8]</a><br><a href="#bits-xc6v-GTX-GTX2:PCOMMA_10B_VALUE" title="GTX2:PCOMMA_10B_VALUE[8]">GTX2:PCOMMA_10B_VALUE[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[9]">GTX2:DRP31[9]</a><br><a href="#bits-xc6v-GTX-GTX2:PCOMMA_10B_VALUE" title="GTX2:PCOMMA_10B_VALUE[9]">GTX2:PCOMMA_10B_VALUE[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[10]">GTX2:DRP31[10]</a><br><a href="#bits-xc6v-GTX-GTX2:PCOMMA_DETECT" title="GTX2:PCOMMA_DETECT">GTX2:PCOMMA_DETECT</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[11]">GTX2:DRP31[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_BUFFER_USE" title="GTX2:TX_BUFFER_USE">GTX2:TX_BUFFER_USE</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[12]">GTX2:DRP31[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DATA_WIDTH" title="GTX2:TX_DATA_WIDTH[0]">GTX2:TX_DATA_WIDTH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[13]">GTX2:DRP31[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DATA_WIDTH" title="GTX2:TX_DATA_WIDTH[1]">GTX2:TX_DATA_WIDTH[1]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[14]">GTX2:DRP31[14]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DATA_WIDTH" title="GTX2:TX_DATA_WIDTH[2]">GTX2:TX_DATA_WIDTH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP31" title="GTX2:DRP31[15]">GTX2:DRP31[15]</a><br><a href="#bits-xc6v-GTX-GTX2:GEN_TXUSRCLK" title="GTX2:GEN_TXUSRCLK">GTX2:GEN_TXUSRCLK</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[0]">GTX2:DRP32[0]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[0]">GTX2:PMA_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[1]">GTX2:DRP32[1]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[1]">GTX2:PMA_CFG[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[2]">GTX2:DRP32[2]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[2]">GTX2:PMA_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[3]">GTX2:DRP32[3]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[3]">GTX2:PMA_CFG[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[4]">GTX2:DRP32[4]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[4]">GTX2:PMA_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[5]">GTX2:DRP32[5]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[5]">GTX2:PMA_CFG[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[6]">GTX2:DRP32[6]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[6]">GTX2:PMA_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[7]">GTX2:DRP32[7]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[7]">GTX2:PMA_CFG[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[8]">GTX2:DRP32[8]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[8]">GTX2:PMA_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[9]">GTX2:DRP32[9]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[9]">GTX2:PMA_CFG[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[10]">GTX2:DRP32[10]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[10]">GTX2:PMA_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[11]">GTX2:DRP32[11]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[11]">GTX2:PMA_CFG[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[12]">GTX2:DRP32[12]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[12]">GTX2:PMA_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[13]">GTX2:DRP32[13]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[13]">GTX2:PMA_CFG[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[14]">GTX2:DRP32[14]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[14]">GTX2:PMA_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP32" title="GTX2:DRP32[15]">GTX2:DRP32[15]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[15]">GTX2:PMA_CFG[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[0]">GTX2:DRP33[0]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[16]">GTX2:PMA_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[1]">GTX2:DRP33[1]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[17]">GTX2:PMA_CFG[17]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[2]">GTX2:DRP33[2]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[18]">GTX2:PMA_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[3]">GTX2:DRP33[3]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[19]">GTX2:PMA_CFG[19]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[4]">GTX2:DRP33[4]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[20]">GTX2:PMA_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[5]">GTX2:DRP33[5]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[21]">GTX2:PMA_CFG[21]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[6]">GTX2:DRP33[6]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[22]">GTX2:PMA_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[7]">GTX2:DRP33[7]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[23]">GTX2:PMA_CFG[23]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[8]">GTX2:DRP33[8]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[24]">GTX2:PMA_CFG[24]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[9]">GTX2:DRP33[9]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[25]">GTX2:PMA_CFG[25]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[10]">GTX2:DRP33[10]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[26]">GTX2:PMA_CFG[26]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[11]">GTX2:DRP33[11]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[27]">GTX2:PMA_CFG[27]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[12]">GTX2:DRP33[12]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[28]">GTX2:PMA_CFG[28]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[13]">GTX2:DRP33[13]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[29]">GTX2:PMA_CFG[29]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[14]">GTX2:DRP33[14]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[30]">GTX2:PMA_CFG[30]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP33" title="GTX2:DRP33[15]">GTX2:DRP33[15]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[31]">GTX2:PMA_CFG[31]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[0]">GTX2:DRP34[0]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[32]">GTX2:PMA_CFG[32]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[1]">GTX2:DRP34[1]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[33]">GTX2:PMA_CFG[33]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[2]">GTX2:DRP34[2]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[34]">GTX2:PMA_CFG[34]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[3]">GTX2:DRP34[3]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[35]">GTX2:PMA_CFG[35]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[4]">GTX2:DRP34[4]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[36]">GTX2:PMA_CFG[36]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[5]">GTX2:DRP34[5]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[37]">GTX2:PMA_CFG[37]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[6]">GTX2:DRP34[6]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[38]">GTX2:PMA_CFG[38]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[7]">GTX2:DRP34[7]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[39]">GTX2:PMA_CFG[39]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[8]">GTX2:DRP34[8]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[40]">GTX2:PMA_CFG[40]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[9]">GTX2:DRP34[9]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[41]">GTX2:PMA_CFG[41]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[10]">GTX2:DRP34[10]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[42]">GTX2:PMA_CFG[42]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[11]">GTX2:DRP34[11]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[43]">GTX2:PMA_CFG[43]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[12]">GTX2:DRP34[12]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[44]">GTX2:PMA_CFG[44]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[13]">GTX2:DRP34[13]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[45]">GTX2:PMA_CFG[45]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[14]">GTX2:DRP34[14]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[46]">GTX2:PMA_CFG[46]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP34" title="GTX2:DRP34[15]">GTX2:DRP34[15]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[47]">GTX2:PMA_CFG[47]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[0]">GTX2:DRP35[0]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[48]">GTX2:PMA_CFG[48]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[1]">GTX2:DRP35[1]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[49]">GTX2:PMA_CFG[49]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[2]">GTX2:DRP35[2]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[50]">GTX2:PMA_CFG[50]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[3]">GTX2:DRP35[3]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[51]">GTX2:PMA_CFG[51]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[4]">GTX2:DRP35[4]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[52]">GTX2:PMA_CFG[52]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[5]">GTX2:DRP35[5]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[53]">GTX2:PMA_CFG[53]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[6]">GTX2:DRP35[6]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[54]">GTX2:PMA_CFG[54]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[7]">GTX2:DRP35[7]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[55]">GTX2:PMA_CFG[55]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[8]">GTX2:DRP35[8]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[56]">GTX2:PMA_CFG[56]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[9]">GTX2:DRP35[9]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[57]">GTX2:PMA_CFG[57]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[10]">GTX2:DRP35[10]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[58]">GTX2:PMA_CFG[58]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[11]">GTX2:DRP35[11]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[59]">GTX2:PMA_CFG[59]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[12]">GTX2:DRP35[12]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[60]">GTX2:PMA_CFG[60]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[13]">GTX2:DRP35[13]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[61]">GTX2:PMA_CFG[61]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[14]">GTX2:DRP35[14]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[62]">GTX2:PMA_CFG[62]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP35" title="GTX2:DRP35[15]">GTX2:DRP35[15]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[63]">GTX2:PMA_CFG[63]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[0]">GTX2:DRP36[0]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[16]">GTX2:PMA_TX_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[1]">GTX2:DRP36[1]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[17]">GTX2:PMA_TX_CFG[17]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[2]">GTX2:DRP36[2]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[18]">GTX2:PMA_TX_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[3]">GTX2:DRP36[3]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[19]">GTX2:PMA_TX_CFG[19]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[4]">GTX2:DRP36[4]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[64]">GTX2:PMA_CFG[64]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[5]">GTX2:DRP36[5]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[65]">GTX2:PMA_CFG[65]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[6]">GTX2:DRP36[6]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[66]">GTX2:PMA_CFG[66]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[7]">GTX2:DRP36[7]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[67]">GTX2:PMA_CFG[67]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[8]">GTX2:DRP36[8]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[68]">GTX2:PMA_CFG[68]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[9]">GTX2:DRP36[9]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[69]">GTX2:PMA_CFG[69]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[10]">GTX2:DRP36[10]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[70]">GTX2:PMA_CFG[70]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[11]">GTX2:DRP36[11]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[71]">GTX2:PMA_CFG[71]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[12]">GTX2:DRP36[12]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[72]">GTX2:PMA_CFG[72]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[13]">GTX2:DRP36[13]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[73]">GTX2:PMA_CFG[73]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[14]">GTX2:DRP36[14]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[74]">GTX2:PMA_CFG[74]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP36" title="GTX2:DRP36[15]">GTX2:DRP36[15]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_CFG" title="GTX2:PMA_CFG[75]">GTX2:PMA_CFG[75]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[0]">GTX2:DRP37[0]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[0]">GTX2:PMA_TX_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[1]">GTX2:DRP37[1]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[1]">GTX2:PMA_TX_CFG[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[2]">GTX2:DRP37[2]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[2]">GTX2:PMA_TX_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[3]">GTX2:DRP37[3]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[3]">GTX2:PMA_TX_CFG[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[4]">GTX2:DRP37[4]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[4]">GTX2:PMA_TX_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[5]">GTX2:DRP37[5]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[5]">GTX2:PMA_TX_CFG[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[6]">GTX2:DRP37[6]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[6]">GTX2:PMA_TX_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[7]">GTX2:DRP37[7]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[7]">GTX2:PMA_TX_CFG[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[8]">GTX2:DRP37[8]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[8]">GTX2:PMA_TX_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[9]">GTX2:DRP37[9]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[9]">GTX2:PMA_TX_CFG[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[10]">GTX2:DRP37[10]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[10]">GTX2:PMA_TX_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[11]">GTX2:DRP37[11]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[11]">GTX2:PMA_TX_CFG[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[12]">GTX2:DRP37[12]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[12]">GTX2:PMA_TX_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[13]">GTX2:DRP37[13]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[13]">GTX2:PMA_TX_CFG[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[14]">GTX2:DRP37[14]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[14]">GTX2:PMA_TX_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP37" title="GTX2:DRP37[15]">GTX2:DRP37[15]</a><br><a href="#bits-xc6v-GTX-GTX2:PMA_TX_CFG" title="GTX2:PMA_TX_CFG[15]">GTX2:PMA_TX_CFG[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 27</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[0]">GTX2:DRP38[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_0" title="GTX2:TX_MARGIN_LOW_0[0]">GTX2:TX_MARGIN_LOW_0[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[1]">GTX2:DRP38[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_0" title="GTX2:TX_MARGIN_LOW_0[1]">GTX2:TX_MARGIN_LOW_0[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[2]">GTX2:DRP38[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_0" title="GTX2:TX_MARGIN_LOW_0[2]">GTX2:TX_MARGIN_LOW_0[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[3]">GTX2:DRP38[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_0" title="GTX2:TX_MARGIN_LOW_0[3]">GTX2:TX_MARGIN_LOW_0[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[4]">GTX2:DRP38[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_0" title="GTX2:TX_MARGIN_LOW_0[4]">GTX2:TX_MARGIN_LOW_0[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[5]">GTX2:DRP38[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_0" title="GTX2:TX_MARGIN_LOW_0[5]">GTX2:TX_MARGIN_LOW_0[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[6]">GTX2:DRP38[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_0" title="GTX2:TX_MARGIN_LOW_0[6]">GTX2:TX_MARGIN_LOW_0[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[7]">GTX2:DRP38[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_0" title="GTX2:TX_MARGIN_FULL_0[0]">GTX2:TX_MARGIN_FULL_0[0]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[8]">GTX2:DRP38[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_0" title="GTX2:TX_MARGIN_FULL_0[1]">GTX2:TX_MARGIN_FULL_0[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[9]">GTX2:DRP38[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_0" title="GTX2:TX_MARGIN_FULL_0[2]">GTX2:TX_MARGIN_FULL_0[2]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[10]">GTX2:DRP38[10]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_0" title="GTX2:TX_MARGIN_FULL_0[3]">GTX2:TX_MARGIN_FULL_0[3]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[11]">GTX2:DRP38[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_0" title="GTX2:TX_MARGIN_FULL_0[4]">GTX2:TX_MARGIN_FULL_0[4]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[12]">GTX2:DRP38[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_0" title="GTX2:TX_MARGIN_FULL_0[5]">GTX2:TX_MARGIN_FULL_0[5]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[13]">GTX2:DRP38[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_0" title="GTX2:TX_MARGIN_FULL_0[6]">GTX2:TX_MARGIN_FULL_0[6]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[14]">GTX2:DRP38[14]</a><br><a href="#bits-xc6v-GTX-GTX2:TXOUTCLKPCS_SEL" title="GTX2:TXOUTCLKPCS_SEL">GTX2:TXOUTCLKPCS_SEL</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP38" title="GTX2:DRP38[15]">GTX2:DRP38[15]</a><br><a href="#bits-xc6v-GTX-GTX2:INV.DCLK" title="~GTX2:INV.DCLK">~GTX2:INV.DCLK</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[0]">GTX2:DRP39[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_1" title="GTX2:TX_MARGIN_LOW_1[0]">GTX2:TX_MARGIN_LOW_1[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[1]">GTX2:DRP39[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_1" title="GTX2:TX_MARGIN_LOW_1[1]">GTX2:TX_MARGIN_LOW_1[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[2]">GTX2:DRP39[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_1" title="GTX2:TX_MARGIN_LOW_1[2]">GTX2:TX_MARGIN_LOW_1[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[3]">GTX2:DRP39[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_1" title="GTX2:TX_MARGIN_LOW_1[3]">GTX2:TX_MARGIN_LOW_1[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[4]">GTX2:DRP39[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_1" title="GTX2:TX_MARGIN_LOW_1[4]">GTX2:TX_MARGIN_LOW_1[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[5]">GTX2:DRP39[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_1" title="GTX2:TX_MARGIN_LOW_1[5]">GTX2:TX_MARGIN_LOW_1[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[6]">GTX2:DRP39[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_1" title="GTX2:TX_MARGIN_LOW_1[6]">GTX2:TX_MARGIN_LOW_1[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[7]">GTX2:DRP39[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_1" title="GTX2:TX_MARGIN_FULL_1[0]">GTX2:TX_MARGIN_FULL_1[0]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[8]">GTX2:DRP39[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_1" title="GTX2:TX_MARGIN_FULL_1[1]">GTX2:TX_MARGIN_FULL_1[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[9]">GTX2:DRP39[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_1" title="GTX2:TX_MARGIN_FULL_1[2]">GTX2:TX_MARGIN_FULL_1[2]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[10]">GTX2:DRP39[10]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_1" title="GTX2:TX_MARGIN_FULL_1[3]">GTX2:TX_MARGIN_FULL_1[3]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[11]">GTX2:DRP39[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_1" title="GTX2:TX_MARGIN_FULL_1[4]">GTX2:TX_MARGIN_FULL_1[4]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[12]">GTX2:DRP39[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_1" title="GTX2:TX_MARGIN_FULL_1[5]">GTX2:TX_MARGIN_FULL_1[5]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[13]">GTX2:DRP39[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_1" title="GTX2:TX_MARGIN_FULL_1[6]">GTX2:TX_MARGIN_FULL_1[6]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[14]">GTX2:DRP39[14]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_TDCC_CFG" title="GTX2:TX_TDCC_CFG[0]">GTX2:TX_TDCC_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP39" title="GTX2:DRP39[15]">GTX2:DRP39[15]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_TDCC_CFG" title="GTX2:TX_TDCC_CFG[1]">GTX2:TX_TDCC_CFG[1]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[0]">GTX2:DRP3A[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_2" title="GTX2:TX_MARGIN_LOW_2[0]">GTX2:TX_MARGIN_LOW_2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[1]">GTX2:DRP3A[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_2" title="GTX2:TX_MARGIN_LOW_2[1]">GTX2:TX_MARGIN_LOW_2[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[2]">GTX2:DRP3A[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_2" title="GTX2:TX_MARGIN_LOW_2[2]">GTX2:TX_MARGIN_LOW_2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[3]">GTX2:DRP3A[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_2" title="GTX2:TX_MARGIN_LOW_2[3]">GTX2:TX_MARGIN_LOW_2[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[4]">GTX2:DRP3A[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_2" title="GTX2:TX_MARGIN_LOW_2[4]">GTX2:TX_MARGIN_LOW_2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[5]">GTX2:DRP3A[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_2" title="GTX2:TX_MARGIN_LOW_2[5]">GTX2:TX_MARGIN_LOW_2[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[6]">GTX2:DRP3A[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_2" title="GTX2:TX_MARGIN_LOW_2[6]">GTX2:TX_MARGIN_LOW_2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[7]">GTX2:DRP3A[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_2" title="GTX2:TX_MARGIN_FULL_2[0]">GTX2:TX_MARGIN_FULL_2[0]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[8]">GTX2:DRP3A[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_2" title="GTX2:TX_MARGIN_FULL_2[1]">GTX2:TX_MARGIN_FULL_2[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[9]">GTX2:DRP3A[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_2" title="GTX2:TX_MARGIN_FULL_2[2]">GTX2:TX_MARGIN_FULL_2[2]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[10]">GTX2:DRP3A[10]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_2" title="GTX2:TX_MARGIN_FULL_2[3]">GTX2:TX_MARGIN_FULL_2[3]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[11]">GTX2:DRP3A[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_2" title="GTX2:TX_MARGIN_FULL_2[4]">GTX2:TX_MARGIN_FULL_2[4]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[12]">GTX2:DRP3A[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_2" title="GTX2:TX_MARGIN_FULL_2[5]">GTX2:TX_MARGIN_FULL_2[5]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[13]">GTX2:DRP3A[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_2" title="GTX2:TX_MARGIN_FULL_2[6]">GTX2:TX_MARGIN_FULL_2[6]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[14]">GTX2:DRP3A[14]</a><br><a href="#bits-xc6v-GTX-GTX2:TXDRIVE_LOOPBACK_HIZ" title="~GTX2:TXDRIVE_LOOPBACK_HIZ">~GTX2:TXDRIVE_LOOPBACK_HIZ</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3A" title="GTX2:DRP3A[15]">GTX2:DRP3A[15]</a><br><a href="#bits-xc6v-GTX-GTX2:TXDRIVE_LOOPBACK_PD" title="~GTX2:TXDRIVE_LOOPBACK_PD">~GTX2:TXDRIVE_LOOPBACK_PD</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[0]">GTX2:DRP3B[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_3" title="GTX2:TX_MARGIN_LOW_3[0]">GTX2:TX_MARGIN_LOW_3[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[1]">GTX2:DRP3B[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_3" title="GTX2:TX_MARGIN_LOW_3[1]">GTX2:TX_MARGIN_LOW_3[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[2]">GTX2:DRP3B[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_3" title="GTX2:TX_MARGIN_LOW_3[2]">GTX2:TX_MARGIN_LOW_3[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[3]">GTX2:DRP3B[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_3" title="GTX2:TX_MARGIN_LOW_3[3]">GTX2:TX_MARGIN_LOW_3[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[4]">GTX2:DRP3B[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_3" title="GTX2:TX_MARGIN_LOW_3[4]">GTX2:TX_MARGIN_LOW_3[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[5]">GTX2:DRP3B[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_3" title="GTX2:TX_MARGIN_LOW_3[5]">GTX2:TX_MARGIN_LOW_3[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[6]">GTX2:DRP3B[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_3" title="GTX2:TX_MARGIN_LOW_3[6]">GTX2:TX_MARGIN_LOW_3[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[7]">GTX2:DRP3B[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_3" title="GTX2:TX_MARGIN_FULL_3[0]">GTX2:TX_MARGIN_FULL_3[0]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[8]">GTX2:DRP3B[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_3" title="GTX2:TX_MARGIN_FULL_3[1]">GTX2:TX_MARGIN_FULL_3[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[9]">GTX2:DRP3B[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_3" title="GTX2:TX_MARGIN_FULL_3[2]">GTX2:TX_MARGIN_FULL_3[2]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[10]">GTX2:DRP3B[10]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_3" title="GTX2:TX_MARGIN_FULL_3[3]">GTX2:TX_MARGIN_FULL_3[3]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[11]">GTX2:DRP3B[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_3" title="GTX2:TX_MARGIN_FULL_3[4]">GTX2:TX_MARGIN_FULL_3[4]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[12]">GTX2:DRP3B[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_3" title="GTX2:TX_MARGIN_FULL_3[5]">GTX2:TX_MARGIN_FULL_3[5]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[13]">GTX2:DRP3B[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_3" title="GTX2:TX_MARGIN_FULL_3[6]">GTX2:TX_MARGIN_FULL_3[6]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXSWING" title="GTX2:A_TXSWING">GTX2:A_TXSWING</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[14]">GTX2:DRP3B[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXDEEMPH" title="GTX2:A_TXDEEMPH">GTX2:A_TXDEEMPH</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3B" title="GTX2:DRP3B[15]">GTX2:DRP3B[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[0]">GTX2:DRP3C[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_4" title="GTX2:TX_MARGIN_LOW_4[0]">GTX2:TX_MARGIN_LOW_4[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[1]">GTX2:DRP3C[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_4" title="GTX2:TX_MARGIN_LOW_4[1]">GTX2:TX_MARGIN_LOW_4[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[2]">GTX2:DRP3C[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_4" title="GTX2:TX_MARGIN_LOW_4[2]">GTX2:TX_MARGIN_LOW_4[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[3]">GTX2:DRP3C[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_4" title="GTX2:TX_MARGIN_LOW_4[3]">GTX2:TX_MARGIN_LOW_4[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[4]">GTX2:DRP3C[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_4" title="GTX2:TX_MARGIN_LOW_4[4]">GTX2:TX_MARGIN_LOW_4[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[5]">GTX2:DRP3C[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_4" title="GTX2:TX_MARGIN_LOW_4[5]">GTX2:TX_MARGIN_LOW_4[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[6]">GTX2:DRP3C[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_4" title="GTX2:TX_MARGIN_LOW_4[6]">GTX2:TX_MARGIN_LOW_4[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[7]">GTX2:DRP3C[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_4" title="GTX2:TX_MARGIN_FULL_4[0]">GTX2:TX_MARGIN_FULL_4[0]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[8]">GTX2:DRP3C[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_4" title="GTX2:TX_MARGIN_FULL_4[1]">GTX2:TX_MARGIN_FULL_4[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[9]">GTX2:DRP3C[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_4" title="GTX2:TX_MARGIN_FULL_4[2]">GTX2:TX_MARGIN_FULL_4[2]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[10]">GTX2:DRP3C[10]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_4" title="GTX2:TX_MARGIN_FULL_4[3]">GTX2:TX_MARGIN_FULL_4[3]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[11]">GTX2:DRP3C[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_4" title="GTX2:TX_MARGIN_FULL_4[4]">GTX2:TX_MARGIN_FULL_4[4]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[12]">GTX2:DRP3C[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_4" title="GTX2:TX_MARGIN_FULL_4[5]">GTX2:TX_MARGIN_FULL_4[5]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[13]">GTX2:DRP3C[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_4" title="GTX2:TX_MARGIN_FULL_4[6]">GTX2:TX_MARGIN_FULL_4[6]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[14]">GTX2:DRP3C[14]</a><br><a href="#bits-xc6v-GTX-GTX2:TXDRIVE_DRP_EN" title="GTX2:TXDRIVE_DRP_EN">GTX2:TXDRIVE_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3C" title="GTX2:DRP3C[15]">GTX2:DRP3C[15]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DRIVE_MODE" title="GTX2:TX_DRIVE_MODE">GTX2:TX_DRIVE_MODE</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXDIFFCTRL" title="GTX2:A_TXDIFFCTRL[0]">GTX2:A_TXDIFFCTRL[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[0]">GTX2:DRP3D[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXDIFFCTRL" title="GTX2:A_TXDIFFCTRL[1]">GTX2:A_TXDIFFCTRL[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[1]">GTX2:DRP3D[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXDIFFCTRL" title="GTX2:A_TXDIFFCTRL[2]">GTX2:A_TXDIFFCTRL[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[2]">GTX2:DRP3D[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXDIFFCTRL" title="GTX2:A_TXDIFFCTRL[3]">GTX2:A_TXDIFFCTRL[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[3]">GTX2:DRP3D[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXBUFDIFFCTRL" title="GTX2:A_TXBUFDIFFCTRL[0]">GTX2:A_TXBUFDIFFCTRL[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[4]">GTX2:DRP3D[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXBUFDIFFCTRL" title="GTX2:A_TXBUFDIFFCTRL[1]">GTX2:A_TXBUFDIFFCTRL[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[5]">GTX2:DRP3D[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXBUFDIFFCTRL" title="GTX2:A_TXBUFDIFFCTRL[2]">GTX2:A_TXBUFDIFFCTRL[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[6]">GTX2:DRP3D[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPREEMPHASIS" title="GTX2:A_TXPREEMPHASIS[0]">GTX2:A_TXPREEMPHASIS[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[7]">GTX2:DRP3D[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPREEMPHASIS" title="GTX2:A_TXPREEMPHASIS[1]">GTX2:A_TXPREEMPHASIS[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[8]">GTX2:DRP3D[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPREEMPHASIS" title="GTX2:A_TXPREEMPHASIS[2]">GTX2:A_TXPREEMPHASIS[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[9]">GTX2:DRP3D[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPREEMPHASIS" title="GTX2:A_TXPREEMPHASIS[3]">GTX2:A_TXPREEMPHASIS[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[10]">GTX2:DRP3D[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPOSTEMPHASIS" title="GTX2:A_TXPOSTEMPHASIS[0]">GTX2:A_TXPOSTEMPHASIS[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[11]">GTX2:DRP3D[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPOSTEMPHASIS" title="GTX2:A_TXPOSTEMPHASIS[1]">GTX2:A_TXPOSTEMPHASIS[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[12]">GTX2:DRP3D[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPOSTEMPHASIS" title="GTX2:A_TXPOSTEMPHASIS[2]">GTX2:A_TXPOSTEMPHASIS[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[13]">GTX2:DRP3D[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPOSTEMPHASIS" title="GTX2:A_TXPOSTEMPHASIS[3]">GTX2:A_TXPOSTEMPHASIS[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[14]">GTX2:DRP3D[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXPOSTEMPHASIS" title="GTX2:A_TXPOSTEMPHASIS[4]">GTX2:A_TXPOSTEMPHASIS[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3D" title="GTX2:DRP3D[15]">GTX2:DRP3D[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[0]">GTX2:DRP3E[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DEEMPH_0" title="GTX2:TX_DEEMPH_0[0]">GTX2:TX_DEEMPH_0[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[1]">GTX2:DRP3E[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DEEMPH_0" title="GTX2:TX_DEEMPH_0[1]">GTX2:TX_DEEMPH_0[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[2]">GTX2:DRP3E[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DEEMPH_0" title="GTX2:TX_DEEMPH_0[2]">GTX2:TX_DEEMPH_0[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[3]">GTX2:DRP3E[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DEEMPH_0" title="GTX2:TX_DEEMPH_0[3]">GTX2:TX_DEEMPH_0[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[4]">GTX2:DRP3E[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DEEMPH_0" title="GTX2:TX_DEEMPH_0[4]">GTX2:TX_DEEMPH_0[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[5]">GTX2:DRP3E[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DEEMPH_1" title="GTX2:TX_DEEMPH_1[0]">GTX2:TX_DEEMPH_1[0]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[6]">GTX2:DRP3E[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DEEMPH_1" title="GTX2:TX_DEEMPH_1[1]">GTX2:TX_DEEMPH_1[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[7]">GTX2:DRP3E[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DEEMPH_1" title="GTX2:TX_DEEMPH_1[2]">GTX2:TX_DEEMPH_1[2]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[8]">GTX2:DRP3E[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DEEMPH_1" title="GTX2:TX_DEEMPH_1[3]">GTX2:TX_DEEMPH_1[3]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[9]">GTX2:DRP3E[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DEEMPH_1" title="GTX2:TX_DEEMPH_1[4]">GTX2:TX_DEEMPH_1[4]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[10]">GTX2:DRP3E[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[11]">GTX2:DRP3E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[12]">GTX2:DRP3E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXMARGIN" title="GTX2:A_TXMARGIN[0]">GTX2:A_TXMARGIN[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[13]">GTX2:DRP3E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_TXMARGIN" title="GTX2:A_TXMARGIN[1]">GTX2:A_TXMARGIN[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[14]">GTX2:DRP3E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_TXMARGIN" title="GTX2:A_TXMARGIN[2]">GTX2:A_TXMARGIN[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP3E" title="GTX2:DRP3E[15]">GTX2:DRP3E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[0]">GTX2:DRP3F[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_RATE" title="GTX2:TRANS_TIME_RATE[0]">GTX2:TRANS_TIME_RATE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[1]">GTX2:DRP3F[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_RATE" title="GTX2:TRANS_TIME_RATE[1]">GTX2:TRANS_TIME_RATE[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[2]">GTX2:DRP3F[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_RATE" title="GTX2:TRANS_TIME_RATE[2]">GTX2:TRANS_TIME_RATE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[3]">GTX2:DRP3F[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_RATE" title="GTX2:TRANS_TIME_RATE[3]">GTX2:TRANS_TIME_RATE[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[4]">GTX2:DRP3F[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_RATE" title="GTX2:TRANS_TIME_RATE[4]">GTX2:TRANS_TIME_RATE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[5]">GTX2:DRP3F[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_RATE" title="GTX2:TRANS_TIME_RATE[5]">GTX2:TRANS_TIME_RATE[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[6]">GTX2:DRP3F[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_RATE" title="GTX2:TRANS_TIME_RATE[6]">GTX2:TRANS_TIME_RATE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[7]">GTX2:DRP3F[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TRANS_TIME_RATE" title="GTX2:TRANS_TIME_RATE[7]">GTX2:TRANS_TIME_RATE[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[8]">GTX2:DRP3F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[9]">GTX2:DRP3F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[10]">GTX2:DRP3F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[11]">GTX2:DRP3F[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[12]">GTX2:DRP3F[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[13]">GTX2:DRP3F[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[14]">GTX2:DRP3F[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP3F" title="GTX2:DRP3F[15]">GTX2:DRP3F[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 28</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_RXEQMIX" title="GTX2:A_RXEQMIX[0]">GTX2:A_RXEQMIX[0]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[0]">GTX2:DRP40[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_RXEQMIX" title="GTX2:A_RXEQMIX[1]">GTX2:A_RXEQMIX[1]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[1]">GTX2:DRP40[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_RXEQMIX" title="GTX2:A_RXEQMIX[2]">GTX2:A_RXEQMIX[2]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[2]">GTX2:DRP40[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_RXEQMIX" title="GTX2:A_RXEQMIX[3]">GTX2:A_RXEQMIX[3]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[3]">GTX2:DRP40[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_RXEQMIX" title="GTX2:A_RXEQMIX[4]">GTX2:A_RXEQMIX[4]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[4]">GTX2:DRP40[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_RXEQMIX" title="GTX2:A_RXEQMIX[5]">GTX2:A_RXEQMIX[5]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[5]">GTX2:DRP40[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_RXEQMIX" title="GTX2:A_RXEQMIX[6]">GTX2:A_RXEQMIX[6]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[6]">GTX2:DRP40[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_RXEQMIX" title="GTX2:A_RXEQMIX[7]">GTX2:A_RXEQMIX[7]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[7]">GTX2:DRP40[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:A_RXEQMIX" title="GTX2:A_RXEQMIX[8]">GTX2:A_RXEQMIX[8]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[8]">GTX2:DRP40[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:A_RXEQMIX" title="GTX2:A_RXEQMIX[9]">GTX2:A_RXEQMIX[9]</a><br><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[9]">GTX2:DRP40[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[10]">GTX2:DRP40[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[11]">GTX2:DRP40[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[12]">GTX2:DRP40[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[13]">GTX2:DRP40[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[14]">GTX2:DRP40[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP40" title="GTX2:DRP40[15]">GTX2:DRP40[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[0]">GTX2:DRP41[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[16]">GTX2:TST_ATTR[16]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[1]">GTX2:DRP41[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[17]">GTX2:TST_ATTR[17]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[2]">GTX2:DRP41[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[18]">GTX2:TST_ATTR[18]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[3]">GTX2:DRP41[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[19]">GTX2:TST_ATTR[19]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[4]">GTX2:DRP41[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[20]">GTX2:TST_ATTR[20]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[5]">GTX2:DRP41[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[21]">GTX2:TST_ATTR[21]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[6]">GTX2:DRP41[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[22]">GTX2:TST_ATTR[22]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[7]">GTX2:DRP41[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[23]">GTX2:TST_ATTR[23]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[8]">GTX2:DRP41[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[24]">GTX2:TST_ATTR[24]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[9]">GTX2:DRP41[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[25]">GTX2:TST_ATTR[25]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[10]">GTX2:DRP41[10]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[26]">GTX2:TST_ATTR[26]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[11]">GTX2:DRP41[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[27]">GTX2:TST_ATTR[27]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[12]">GTX2:DRP41[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[28]">GTX2:TST_ATTR[28]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[13]">GTX2:DRP41[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[29]">GTX2:TST_ATTR[29]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[14]">GTX2:DRP41[14]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[30]">GTX2:TST_ATTR[30]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP41" title="GTX2:DRP41[15]">GTX2:DRP41[15]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[31]">GTX2:TST_ATTR[31]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[0]">GTX2:DRP42[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[0]">GTX2:TST_ATTR[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[1]">GTX2:DRP42[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[1]">GTX2:TST_ATTR[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[2]">GTX2:DRP42[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[2]">GTX2:TST_ATTR[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[3]">GTX2:DRP42[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[3]">GTX2:TST_ATTR[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[4]">GTX2:DRP42[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[4]">GTX2:TST_ATTR[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[5]">GTX2:DRP42[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[5]">GTX2:TST_ATTR[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[6]">GTX2:DRP42[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[6]">GTX2:TST_ATTR[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[7]">GTX2:DRP42[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[7]">GTX2:TST_ATTR[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[8]">GTX2:DRP42[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[8]">GTX2:TST_ATTR[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[9]">GTX2:DRP42[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[9]">GTX2:TST_ATTR[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[10]">GTX2:DRP42[10]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[10]">GTX2:TST_ATTR[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[11]">GTX2:DRP42[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[11]">GTX2:TST_ATTR[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[12]">GTX2:DRP42[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[12]">GTX2:TST_ATTR[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[13]">GTX2:DRP42[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[13]">GTX2:TST_ATTR[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[14]">GTX2:DRP42[14]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[14]">GTX2:TST_ATTR[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP42" title="GTX2:DRP42[15]">GTX2:DRP42[15]</a><br><a href="#bits-xc6v-GTX-GTX2:TST_ATTR" title="GTX2:TST_ATTR[15]">GTX2:TST_ATTR[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[0]">GTX2:DRP43[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TXOUTCLK_CTRL" title="GTX2:TXOUTCLK_CTRL[2]">GTX2:TXOUTCLK_CTRL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[1]">GTX2:DRP43[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TXOUTCLK_CTRL" title="GTX2:TXOUTCLK_CTRL[1]">GTX2:TXOUTCLK_CTRL[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[2]">GTX2:DRP43[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TXOUTCLK_CTRL" title="GTX2:TXOUTCLK_CTRL[0]">GTX2:TXOUTCLK_CTRL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[3]">GTX2:DRP43[3]</a><br><a href="#bits-xc6v-GTX-GTX2:RXRECCLK_CTRL" title="GTX2:RXRECCLK_CTRL[2]">GTX2:RXRECCLK_CTRL[2]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[4]">GTX2:DRP43[4]</a><br><a href="#bits-xc6v-GTX-GTX2:RXRECCLK_CTRL" title="GTX2:RXRECCLK_CTRL[1]">GTX2:RXRECCLK_CTRL[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[5]">GTX2:DRP43[5]</a><br><a href="#bits-xc6v-GTX-GTX2:RXRECCLK_CTRL" title="GTX2:RXRECCLK_CTRL[0]">GTX2:RXRECCLK_CTRL[0]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[6]">GTX2:DRP43[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[7]">GTX2:DRP43[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[8]">GTX2:DRP43[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[9]">GTX2:DRP43[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[10]">GTX2:DRP43[10]</a><br><a href="#bits-xc6v-GTX-GTX2:INV.TSTCLK0" title="~GTX2:INV.TSTCLK0">~GTX2:INV.TSTCLK0</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[11]">GTX2:DRP43[11]</a><br><a href="#bits-xc6v-GTX-GTX2:INV.TSTCLK1" title="~GTX2:INV.TSTCLK1">~GTX2:INV.TSTCLK1</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[12]">GTX2:DRP43[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[13]">GTX2:DRP43[13]</a><br><a href="#bits-xc6v-GTX-GTX2:INV.SCANCLK" title="~GTX2:INV.SCANCLK">~GTX2:INV.SCANCLK</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[14]">GTX2:DRP43[14]</a><br><a href="#bits-xc6v-GTX-GTX2:INV.GREFCLKTX" title="~GTX2:INV.GREFCLKTX">~GTX2:INV.GREFCLKTX</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP43" title="GTX2:DRP43[15]">GTX2:DRP43[15]</a><br><a href="#bits-xc6v-GTX-GTX2:INV.GREFCLKRX" title="~GTX2:INV.GREFCLKRX">~GTX2:INV.GREFCLKRX</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[0]">GTX2:DRP44[0]</a><br><a href="#bits-xc6v-GTX-GTX2:POWER_SAVE" title="GTX2:POWER_SAVE[0]">GTX2:POWER_SAVE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[1]">GTX2:DRP44[1]</a><br><a href="#bits-xc6v-GTX-GTX2:POWER_SAVE" title="GTX2:POWER_SAVE[1]">GTX2:POWER_SAVE[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[2]">GTX2:DRP44[2]</a><br><a href="#bits-xc6v-GTX-GTX2:POWER_SAVE" title="GTX2:POWER_SAVE[2]">GTX2:POWER_SAVE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[3]">GTX2:DRP44[3]</a><br><a href="#bits-xc6v-GTX-GTX2:POWER_SAVE" title="GTX2:POWER_SAVE[3]">GTX2:POWER_SAVE[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[4]">GTX2:DRP44[4]</a><br><a href="#bits-xc6v-GTX-GTX2:POWER_SAVE" title="GTX2:POWER_SAVE[4]">GTX2:POWER_SAVE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[5]">GTX2:DRP44[5]</a><br><a href="#bits-xc6v-GTX-GTX2:POWER_SAVE" title="GTX2:POWER_SAVE[5]">GTX2:POWER_SAVE[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[6]">GTX2:DRP44[6]</a><br><a href="#bits-xc6v-GTX-GTX2:POWER_SAVE" title="GTX2:POWER_SAVE[6]">GTX2:POWER_SAVE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[7]">GTX2:DRP44[7]</a><br><a href="#bits-xc6v-GTX-GTX2:POWER_SAVE" title="GTX2:POWER_SAVE[7]">GTX2:POWER_SAVE[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[8]">GTX2:DRP44[8]</a><br><a href="#bits-xc6v-GTX-GTX2:POWER_SAVE" title="GTX2:POWER_SAVE[8]">GTX2:POWER_SAVE[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[9]">GTX2:DRP44[9]</a><br><a href="#bits-xc6v-GTX-GTX2:POWER_SAVE" title="GTX2:POWER_SAVE[9]">GTX2:POWER_SAVE[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[10]">GTX2:DRP44[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[11]">GTX2:DRP44[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[12]">GTX2:DRP44[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[13]">GTX2:DRP44[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[14]">GTX2:DRP44[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP44" title="GTX2:DRP44[15]">GTX2:DRP44[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[0]">GTX2:DRP45[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_BYTECLK_CFG" title="GTX2:TX_BYTECLK_CFG[0]">GTX2:TX_BYTECLK_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[1]">GTX2:DRP45[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_BYTECLK_CFG" title="GTX2:TX_BYTECLK_CFG[1]">GTX2:TX_BYTECLK_CFG[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[2]">GTX2:DRP45[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_BYTECLK_CFG" title="GTX2:TX_BYTECLK_CFG[2]">GTX2:TX_BYTECLK_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[3]">GTX2:DRP45[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_BYTECLK_CFG" title="GTX2:TX_BYTECLK_CFG[3]">GTX2:TX_BYTECLK_CFG[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[4]">GTX2:DRP45[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_BYTECLK_CFG" title="GTX2:TX_BYTECLK_CFG[4]">GTX2:TX_BYTECLK_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[5]">GTX2:DRP45[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_BYTECLK_CFG" title="GTX2:TX_BYTECLK_CFG[5]">GTX2:TX_BYTECLK_CFG[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[6]">GTX2:DRP45[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_USRCLK_CFG" title="GTX2:TX_USRCLK_CFG[0]">GTX2:TX_USRCLK_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[7]">GTX2:DRP45[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_USRCLK_CFG" title="GTX2:TX_USRCLK_CFG[1]">GTX2:TX_USRCLK_CFG[1]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[8]">GTX2:DRP45[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_USRCLK_CFG" title="GTX2:TX_USRCLK_CFG[2]">GTX2:TX_USRCLK_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[9]">GTX2:DRP45[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_USRCLK_CFG" title="GTX2:TX_USRCLK_CFG[3]">GTX2:TX_USRCLK_CFG[3]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[10]">GTX2:DRP45[10]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_USRCLK_CFG" title="GTX2:TX_USRCLK_CFG[4]">GTX2:TX_USRCLK_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[11]">GTX2:DRP45[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_USRCLK_CFG" title="GTX2:TX_USRCLK_CFG[5]">GTX2:TX_USRCLK_CFG[5]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[12]">GTX2:DRP45[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[13]">GTX2:DRP45[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[14]">GTX2:DRP45[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP45" title="GTX2:DRP45[15]">GTX2:DRP45[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[0]">GTX2:DRP46[0]</a><br><a href="#bits-xc6v-GTX-GTX2:RXRECCLK_DLY" title="GTX2:RXRECCLK_DLY[0]">GTX2:RXRECCLK_DLY[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[1]">GTX2:DRP46[1]</a><br><a href="#bits-xc6v-GTX-GTX2:RXRECCLK_DLY" title="GTX2:RXRECCLK_DLY[1]">GTX2:RXRECCLK_DLY[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[2]">GTX2:DRP46[2]</a><br><a href="#bits-xc6v-GTX-GTX2:RXRECCLK_DLY" title="GTX2:RXRECCLK_DLY[2]">GTX2:RXRECCLK_DLY[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[3]">GTX2:DRP46[3]</a><br><a href="#bits-xc6v-GTX-GTX2:RXRECCLK_DLY" title="GTX2:RXRECCLK_DLY[3]">GTX2:RXRECCLK_DLY[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[4]">GTX2:DRP46[4]</a><br><a href="#bits-xc6v-GTX-GTX2:RXRECCLK_DLY" title="GTX2:RXRECCLK_DLY[4]">GTX2:RXRECCLK_DLY[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[5]">GTX2:DRP46[5]</a><br><a href="#bits-xc6v-GTX-GTX2:RXRECCLK_DLY" title="GTX2:RXRECCLK_DLY[5]">GTX2:RXRECCLK_DLY[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[6]">GTX2:DRP46[6]</a><br><a href="#bits-xc6v-GTX-GTX2:RXRECCLK_DLY" title="GTX2:RXRECCLK_DLY[6]">GTX2:RXRECCLK_DLY[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[7]">GTX2:DRP46[7]</a><br><a href="#bits-xc6v-GTX-GTX2:RXRECCLK_DLY" title="GTX2:RXRECCLK_DLY[7]">GTX2:RXRECCLK_DLY[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[8]">GTX2:DRP46[8]</a><br><a href="#bits-xc6v-GTX-GTX2:RXRECCLK_DLY" title="GTX2:RXRECCLK_DLY[8]">GTX2:RXRECCLK_DLY[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[9]">GTX2:DRP46[9]</a><br><a href="#bits-xc6v-GTX-GTX2:RXRECCLK_DLY" title="GTX2:RXRECCLK_DLY[9]">GTX2:RXRECCLK_DLY[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[10]">GTX2:DRP46[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[11]">GTX2:DRP46[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[12]">GTX2:DRP46[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[13]">GTX2:DRP46[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[14]">GTX2:DRP46[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP46" title="GTX2:DRP46[15]">GTX2:DRP46[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[0]">GTX2:DRP47[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TXOUTCLK_DLY" title="GTX2:TXOUTCLK_DLY[0]">GTX2:TXOUTCLK_DLY[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[1]">GTX2:DRP47[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TXOUTCLK_DLY" title="GTX2:TXOUTCLK_DLY[1]">GTX2:TXOUTCLK_DLY[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[2]">GTX2:DRP47[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TXOUTCLK_DLY" title="GTX2:TXOUTCLK_DLY[2]">GTX2:TXOUTCLK_DLY[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[3]">GTX2:DRP47[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TXOUTCLK_DLY" title="GTX2:TXOUTCLK_DLY[3]">GTX2:TXOUTCLK_DLY[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[4]">GTX2:DRP47[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TXOUTCLK_DLY" title="GTX2:TXOUTCLK_DLY[4]">GTX2:TXOUTCLK_DLY[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[5]">GTX2:DRP47[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TXOUTCLK_DLY" title="GTX2:TXOUTCLK_DLY[5]">GTX2:TXOUTCLK_DLY[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[6]">GTX2:DRP47[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TXOUTCLK_DLY" title="GTX2:TXOUTCLK_DLY[6]">GTX2:TXOUTCLK_DLY[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[7]">GTX2:DRP47[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TXOUTCLK_DLY" title="GTX2:TXOUTCLK_DLY[7]">GTX2:TXOUTCLK_DLY[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[8]">GTX2:DRP47[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TXOUTCLK_DLY" title="GTX2:TXOUTCLK_DLY[8]">GTX2:TXOUTCLK_DLY[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[9]">GTX2:DRP47[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TXOUTCLK_DLY" title="GTX2:TXOUTCLK_DLY[9]">GTX2:TXOUTCLK_DLY[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[10]">GTX2:DRP47[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[11]">GTX2:DRP47[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[12]">GTX2:DRP47[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[13]">GTX2:DRP47[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[14]">GTX2:DRP47[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP47" title="GTX2:DRP47[15]">GTX2:DRP47[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 29</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[0]">GTX2:DRP48[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[1]">GTX2:DRP48[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[2]">GTX2:DRP48[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[3]">GTX2:DRP48[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[4]">GTX2:DRP48[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[5]">GTX2:DRP48[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[6]">GTX2:DRP48[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[7]">GTX2:DRP48[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[8]">GTX2:DRP48[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[9]">GTX2:DRP48[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[10]">GTX2:DRP48[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[11]">GTX2:DRP48[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[12]">GTX2:DRP48[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[13]">GTX2:DRP48[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[14]">GTX2:DRP48[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP48" title="GTX2:DRP48[15]">GTX2:DRP48[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[0]">GTX2:DRP49[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[1]">GTX2:DRP49[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[2]">GTX2:DRP49[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[3]">GTX2:DRP49[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[4]">GTX2:DRP49[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[5]">GTX2:DRP49[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[6]">GTX2:DRP49[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[7]">GTX2:DRP49[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[8]">GTX2:DRP49[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[9]">GTX2:DRP49[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[10]">GTX2:DRP49[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[11]">GTX2:DRP49[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[12]">GTX2:DRP49[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[13]">GTX2:DRP49[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[14]">GTX2:DRP49[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP49" title="GTX2:DRP49[15]">GTX2:DRP49[15]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[0]">GTX2:DRP4A[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[1]">GTX2:DRP4A[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[2]">GTX2:DRP4A[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[3]">GTX2:DRP4A[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[4]">GTX2:DRP4A[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[5]">GTX2:DRP4A[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[6]">GTX2:DRP4A[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[7]">GTX2:DRP4A[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[8]">GTX2:DRP4A[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[9]">GTX2:DRP4A[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[10]">GTX2:DRP4A[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[11]">GTX2:DRP4A[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[12]">GTX2:DRP4A[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[13]">GTX2:DRP4A[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[14]">GTX2:DRP4A[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4A" title="GTX2:DRP4A[15]">GTX2:DRP4A[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[0]">GTX2:DRP4B[0]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_MONSEL" title="GTX2:RX_DLYALIGN_MONSEL[0]">GTX2:RX_DLYALIGN_MONSEL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[1]">GTX2:DRP4B[1]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_MONSEL" title="GTX2:RX_DLYALIGN_MONSEL[1]">GTX2:RX_DLYALIGN_MONSEL[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[2]">GTX2:DRP4B[2]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_MONSEL" title="GTX2:RX_DLYALIGN_MONSEL[2]">GTX2:RX_DLYALIGN_MONSEL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[3]">GTX2:DRP4B[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_MONSEL" title="GTX2:TX_DLYALIGN_MONSEL[0]">GTX2:TX_DLYALIGN_MONSEL[0]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[4]">GTX2:DRP4B[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_MONSEL" title="GTX2:TX_DLYALIGN_MONSEL[1]">GTX2:TX_DLYALIGN_MONSEL[1]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[5]">GTX2:DRP4B[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_MONSEL" title="GTX2:TX_DLYALIGN_MONSEL[2]">GTX2:TX_DLYALIGN_MONSEL[2]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[6]">GTX2:DRP4B[6]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_EDGESET" title="GTX2:RX_DLYALIGN_EDGESET[0]">GTX2:RX_DLYALIGN_EDGESET[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[7]">GTX2:DRP4B[7]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_EDGESET" title="GTX2:RX_DLYALIGN_EDGESET[1]">GTX2:RX_DLYALIGN_EDGESET[1]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[8]">GTX2:DRP4B[8]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_EDGESET" title="GTX2:RX_DLYALIGN_EDGESET[2]">GTX2:RX_DLYALIGN_EDGESET[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[9]">GTX2:DRP4B[9]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_EDGESET" title="GTX2:RX_DLYALIGN_EDGESET[3]">GTX2:RX_DLYALIGN_EDGESET[3]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[10]">GTX2:DRP4B[10]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_EDGESET" title="GTX2:RX_DLYALIGN_EDGESET[4]">GTX2:RX_DLYALIGN_EDGESET[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[11]">GTX2:DRP4B[11]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[12]">GTX2:DRP4B[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[13]">GTX2:DRP4B[13]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[14]">GTX2:DRP4B[14]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_EN_REALIGN_RESET_BUF2" title="GTX2:RX_EN_REALIGN_RESET_BUF2">GTX2:RX_EN_REALIGN_RESET_BUF2</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4B" title="GTX2:DRP4B[15]">GTX2:DRP4B[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[0]">GTX2:DRP4C[0]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_CTRINC" title="GTX2:TX_DLYALIGN_CTRINC[0]">GTX2:TX_DLYALIGN_CTRINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[1]">GTX2:DRP4C[1]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_CTRINC" title="GTX2:TX_DLYALIGN_CTRINC[1]">GTX2:TX_DLYALIGN_CTRINC[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[2]">GTX2:DRP4C[2]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_CTRINC" title="GTX2:TX_DLYALIGN_CTRINC[2]">GTX2:TX_DLYALIGN_CTRINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[3]">GTX2:DRP4C[3]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_CTRINC" title="GTX2:TX_DLYALIGN_CTRINC[3]">GTX2:TX_DLYALIGN_CTRINC[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[4]">GTX2:DRP4C[4]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_LPFINC" title="GTX2:TX_DLYALIGN_LPFINC[0]">GTX2:TX_DLYALIGN_LPFINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[5]">GTX2:DRP4C[5]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_LPFINC" title="GTX2:TX_DLYALIGN_LPFINC[1]">GTX2:TX_DLYALIGN_LPFINC[1]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[6]">GTX2:DRP4C[6]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_LPFINC" title="GTX2:TX_DLYALIGN_LPFINC[2]">GTX2:TX_DLYALIGN_LPFINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[7]">GTX2:DRP4C[7]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_LPFINC" title="GTX2:TX_DLYALIGN_LPFINC[3]">GTX2:TX_DLYALIGN_LPFINC[3]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[8]">GTX2:DRP4C[8]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_OVRDSETTING" title="GTX2:TX_DLYALIGN_OVRDSETTING[0]">GTX2:TX_DLYALIGN_OVRDSETTING[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[9]">GTX2:DRP4C[9]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_OVRDSETTING" title="GTX2:TX_DLYALIGN_OVRDSETTING[1]">GTX2:TX_DLYALIGN_OVRDSETTING[1]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[10]">GTX2:DRP4C[10]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_OVRDSETTING" title="GTX2:TX_DLYALIGN_OVRDSETTING[2]">GTX2:TX_DLYALIGN_OVRDSETTING[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[11]">GTX2:DRP4C[11]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_OVRDSETTING" title="GTX2:TX_DLYALIGN_OVRDSETTING[3]">GTX2:TX_DLYALIGN_OVRDSETTING[3]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[12]">GTX2:DRP4C[12]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_OVRDSETTING" title="GTX2:TX_DLYALIGN_OVRDSETTING[4]">GTX2:TX_DLYALIGN_OVRDSETTING[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[13]">GTX2:DRP4C[13]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_OVRDSETTING" title="GTX2:TX_DLYALIGN_OVRDSETTING[5]">GTX2:TX_DLYALIGN_OVRDSETTING[5]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[14]">GTX2:DRP4C[14]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_OVRDSETTING" title="GTX2:TX_DLYALIGN_OVRDSETTING[6]">GTX2:TX_DLYALIGN_OVRDSETTING[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4C" title="GTX2:DRP4C[15]">GTX2:DRP4C[15]</a><br><a href="#bits-xc6v-GTX-GTX2:TX_DLYALIGN_OVRDSETTING" title="GTX2:TX_DLYALIGN_OVRDSETTING[7]">GTX2:TX_DLYALIGN_OVRDSETTING[7]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[0]">GTX2:DRP4D[0]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_CTRINC" title="GTX2:RX_DLYALIGN_CTRINC[0]">GTX2:RX_DLYALIGN_CTRINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[1]">GTX2:DRP4D[1]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_CTRINC" title="GTX2:RX_DLYALIGN_CTRINC[1]">GTX2:RX_DLYALIGN_CTRINC[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[2]">GTX2:DRP4D[2]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_CTRINC" title="GTX2:RX_DLYALIGN_CTRINC[2]">GTX2:RX_DLYALIGN_CTRINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[3]">GTX2:DRP4D[3]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_CTRINC" title="GTX2:RX_DLYALIGN_CTRINC[3]">GTX2:RX_DLYALIGN_CTRINC[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[4]">GTX2:DRP4D[4]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_LPFINC" title="GTX2:RX_DLYALIGN_LPFINC[0]">GTX2:RX_DLYALIGN_LPFINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[5]">GTX2:DRP4D[5]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_LPFINC" title="GTX2:RX_DLYALIGN_LPFINC[1]">GTX2:RX_DLYALIGN_LPFINC[1]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[6]">GTX2:DRP4D[6]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_LPFINC" title="GTX2:RX_DLYALIGN_LPFINC[2]">GTX2:RX_DLYALIGN_LPFINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[7]">GTX2:DRP4D[7]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_LPFINC" title="GTX2:RX_DLYALIGN_LPFINC[3]">GTX2:RX_DLYALIGN_LPFINC[3]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[8]">GTX2:DRP4D[8]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_OVRDSETTING" title="GTX2:RX_DLYALIGN_OVRDSETTING[0]">GTX2:RX_DLYALIGN_OVRDSETTING[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[9]">GTX2:DRP4D[9]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_OVRDSETTING" title="GTX2:RX_DLYALIGN_OVRDSETTING[1]">GTX2:RX_DLYALIGN_OVRDSETTING[1]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[10]">GTX2:DRP4D[10]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_OVRDSETTING" title="GTX2:RX_DLYALIGN_OVRDSETTING[2]">GTX2:RX_DLYALIGN_OVRDSETTING[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[11]">GTX2:DRP4D[11]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_OVRDSETTING" title="GTX2:RX_DLYALIGN_OVRDSETTING[3]">GTX2:RX_DLYALIGN_OVRDSETTING[3]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[12]">GTX2:DRP4D[12]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_OVRDSETTING" title="GTX2:RX_DLYALIGN_OVRDSETTING[4]">GTX2:RX_DLYALIGN_OVRDSETTING[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[13]">GTX2:DRP4D[13]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_OVRDSETTING" title="GTX2:RX_DLYALIGN_OVRDSETTING[5]">GTX2:RX_DLYALIGN_OVRDSETTING[5]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[14]">GTX2:DRP4D[14]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_OVRDSETTING" title="GTX2:RX_DLYALIGN_OVRDSETTING[6]">GTX2:RX_DLYALIGN_OVRDSETTING[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4D" title="GTX2:DRP4D[15]">GTX2:DRP4D[15]</a><br><a href="#bits-xc6v-GTX-GTX2:RX_DLYALIGN_OVRDSETTING" title="GTX2:RX_DLYALIGN_OVRDSETTING[7]">GTX2:RX_DLYALIGN_OVRDSETTING[7]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[0]">GTX2:DRP4E[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[1]">GTX2:DRP4E[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[2]">GTX2:DRP4E[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[3]">GTX2:DRP4E[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[4]">GTX2:DRP4E[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[5]">GTX2:DRP4E[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[6]">GTX2:DRP4E[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[7]">GTX2:DRP4E[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[8]">GTX2:DRP4E[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[9]">GTX2:DRP4E[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[10]">GTX2:DRP4E[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[11]">GTX2:DRP4E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[12]">GTX2:DRP4E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[13]">GTX2:DRP4E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[14]">GTX2:DRP4E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4E" title="GTX2:DRP4E[15]">GTX2:DRP4E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[0]">GTX2:DRP4F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[1]">GTX2:DRP4F[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[2]">GTX2:DRP4F[2]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[3]">GTX2:DRP4F[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[4]">GTX2:DRP4F[4]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[5]">GTX2:DRP4F[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[6]">GTX2:DRP4F[6]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[7]">GTX2:DRP4F[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[8]">GTX2:DRP4F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[9]">GTX2:DRP4F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[10]">GTX2:DRP4F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[11]">GTX2:DRP4F[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[12]">GTX2:DRP4F[12]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[13]">GTX2:DRP4F[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[14]">GTX2:DRP4F[14]</a></td><td><a href="#bits-xc6v-GTX-GTX2:DRP4F" title="GTX2:DRP4F[15]">GTX2:DRP4F[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 30</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[0]">GTX3:DRP00[0]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[0]">GTX3:PMA_RX_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[1]">GTX3:DRP00[1]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[1]">GTX3:PMA_RX_CFG[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[2]">GTX3:DRP00[2]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[2]">GTX3:PMA_RX_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[3]">GTX3:DRP00[3]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[3]">GTX3:PMA_RX_CFG[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[4]">GTX3:DRP00[4]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[4]">GTX3:PMA_RX_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[5]">GTX3:DRP00[5]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[5]">GTX3:PMA_RX_CFG[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[6]">GTX3:DRP00[6]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[6]">GTX3:PMA_RX_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[7]">GTX3:DRP00[7]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[7]">GTX3:PMA_RX_CFG[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[8]">GTX3:DRP00[8]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[8]">GTX3:PMA_RX_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[9]">GTX3:DRP00[9]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[9]">GTX3:PMA_RX_CFG[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[10]">GTX3:DRP00[10]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[10]">GTX3:PMA_RX_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[11]">GTX3:DRP00[11]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[11]">GTX3:PMA_RX_CFG[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[12]">GTX3:DRP00[12]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[12]">GTX3:PMA_RX_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[13]">GTX3:DRP00[13]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[13]">GTX3:PMA_RX_CFG[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[14]">GTX3:DRP00[14]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[14]">GTX3:PMA_RX_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP00" title="GTX3:DRP00[15]">GTX3:DRP00[15]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[15]">GTX3:PMA_RX_CFG[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[0]">GTX3:DRP01[0]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[16]">GTX3:PMA_RX_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[1]">GTX3:DRP01[1]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[17]">GTX3:PMA_RX_CFG[17]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[2]">GTX3:DRP01[2]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[18]">GTX3:PMA_RX_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[3]">GTX3:DRP01[3]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[19]">GTX3:PMA_RX_CFG[19]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[4]">GTX3:DRP01[4]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[20]">GTX3:PMA_RX_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[5]">GTX3:DRP01[5]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[21]">GTX3:PMA_RX_CFG[21]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[6]">GTX3:DRP01[6]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[22]">GTX3:PMA_RX_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[7]">GTX3:DRP01[7]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[23]">GTX3:PMA_RX_CFG[23]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[8]">GTX3:DRP01[8]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RX_CFG" title="GTX3:PMA_RX_CFG[24]">GTX3:PMA_RX_CFG[24]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[9]">GTX3:DRP01[9]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RXSYNC_CFG" title="GTX3:PMA_RXSYNC_CFG[0]">GTX3:PMA_RXSYNC_CFG[0]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[10]">GTX3:DRP01[10]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RXSYNC_CFG" title="GTX3:PMA_RXSYNC_CFG[1]">GTX3:PMA_RXSYNC_CFG[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[11]">GTX3:DRP01[11]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RXSYNC_CFG" title="GTX3:PMA_RXSYNC_CFG[2]">GTX3:PMA_RXSYNC_CFG[2]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[12]">GTX3:DRP01[12]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RXSYNC_CFG" title="GTX3:PMA_RXSYNC_CFG[3]">GTX3:PMA_RXSYNC_CFG[3]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[13]">GTX3:DRP01[13]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RXSYNC_CFG" title="GTX3:PMA_RXSYNC_CFG[4]">GTX3:PMA_RXSYNC_CFG[4]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[14]">GTX3:DRP01[14]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RXSYNC_CFG" title="GTX3:PMA_RXSYNC_CFG[5]">GTX3:PMA_RXSYNC_CFG[5]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP01" title="GTX3:DRP01[15]">GTX3:DRP01[15]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_RXSYNC_CFG" title="GTX3:PMA_RXSYNC_CFG[6]">GTX3:PMA_RXSYNC_CFG[6]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[0]">GTX3:DRP02[0]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[0]">GTX3:RXUSRCLK_DLY[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[1]">GTX3:DRP02[1]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[1]">GTX3:RXUSRCLK_DLY[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[2]">GTX3:DRP02[2]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[2]">GTX3:RXUSRCLK_DLY[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[3]">GTX3:DRP02[3]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[3]">GTX3:RXUSRCLK_DLY[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[4]">GTX3:DRP02[4]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[4]">GTX3:RXUSRCLK_DLY[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[5]">GTX3:DRP02[5]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[5]">GTX3:RXUSRCLK_DLY[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[6]">GTX3:DRP02[6]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[6]">GTX3:RXUSRCLK_DLY[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[7]">GTX3:DRP02[7]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[7]">GTX3:RXUSRCLK_DLY[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[8]">GTX3:DRP02[8]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[8]">GTX3:RXUSRCLK_DLY[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[9]">GTX3:DRP02[9]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[9]">GTX3:RXUSRCLK_DLY[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[10]">GTX3:DRP02[10]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[10]">GTX3:RXUSRCLK_DLY[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[11]">GTX3:DRP02[11]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[11]">GTX3:RXUSRCLK_DLY[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[12]">GTX3:DRP02[12]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[12]">GTX3:RXUSRCLK_DLY[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[13]">GTX3:DRP02[13]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[13]">GTX3:RXUSRCLK_DLY[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[14]">GTX3:DRP02[14]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[14]">GTX3:RXUSRCLK_DLY[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP02" title="GTX3:DRP02[15]">GTX3:DRP02[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RXUSRCLK_DLY" title="GTX3:RXUSRCLK_DLY[15]">GTX3:RXUSRCLK_DLY[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[0]">GTX3:BIAS_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[0]">GTX3:DRP03[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[1]">GTX3:BIAS_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[1]">GTX3:DRP03[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[2]">GTX3:BIAS_CFG[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[2]">GTX3:DRP03[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[3]">GTX3:BIAS_CFG[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[3]">GTX3:DRP03[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[4]">GTX3:BIAS_CFG[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[4]">GTX3:DRP03[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[5]">GTX3:BIAS_CFG[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[5]">GTX3:DRP03[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[6]">GTX3:BIAS_CFG[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[6]">GTX3:DRP03[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[7]">GTX3:BIAS_CFG[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[7]">GTX3:DRP03[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[8]">GTX3:BIAS_CFG[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[8]">GTX3:DRP03[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[9]">GTX3:BIAS_CFG[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[9]">GTX3:DRP03[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[10]">GTX3:BIAS_CFG[10]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[10]">GTX3:DRP03[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[11]">GTX3:BIAS_CFG[11]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[11]">GTX3:DRP03[11]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[12]">GTX3:BIAS_CFG[12]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[12]">GTX3:DRP03[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[13]">GTX3:BIAS_CFG[13]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[13]">GTX3:DRP03[13]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[14]">GTX3:BIAS_CFG[14]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[14]">GTX3:DRP03[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[15]">GTX3:BIAS_CFG[15]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP03" title="GTX3:DRP03[15]">GTX3:DRP03[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_1" title="GTX3:CHAN_BOND_SEQ_1_1[0]">GTX3:CHAN_BOND_SEQ_1_1[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[0]">GTX3:DRP04[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_1" title="GTX3:CHAN_BOND_SEQ_1_1[1]">GTX3:CHAN_BOND_SEQ_1_1[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[1]">GTX3:DRP04[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_1" title="GTX3:CHAN_BOND_SEQ_1_1[2]">GTX3:CHAN_BOND_SEQ_1_1[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[2]">GTX3:DRP04[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_1" title="GTX3:CHAN_BOND_SEQ_1_1[3]">GTX3:CHAN_BOND_SEQ_1_1[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[3]">GTX3:DRP04[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_1" title="GTX3:CHAN_BOND_SEQ_1_1[4]">GTX3:CHAN_BOND_SEQ_1_1[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[4]">GTX3:DRP04[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_1" title="GTX3:CHAN_BOND_SEQ_1_1[5]">GTX3:CHAN_BOND_SEQ_1_1[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[5]">GTX3:DRP04[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_1" title="GTX3:CHAN_BOND_SEQ_1_1[6]">GTX3:CHAN_BOND_SEQ_1_1[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[6]">GTX3:DRP04[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_1" title="GTX3:CHAN_BOND_SEQ_1_1[7]">GTX3:CHAN_BOND_SEQ_1_1[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[7]">GTX3:DRP04[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_1" title="GTX3:CHAN_BOND_SEQ_1_1[8]">GTX3:CHAN_BOND_SEQ_1_1[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[8]">GTX3:DRP04[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_1" title="GTX3:CHAN_BOND_SEQ_1_1[9]">GTX3:CHAN_BOND_SEQ_1_1[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[9]">GTX3:DRP04[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_ENABLE" title="GTX3:CHAN_BOND_SEQ_1_ENABLE[0]">GTX3:CHAN_BOND_SEQ_1_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[10]">GTX3:DRP04[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_ENABLE" title="GTX3:CHAN_BOND_SEQ_1_ENABLE[1]">GTX3:CHAN_BOND_SEQ_1_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[11]">GTX3:DRP04[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_ENABLE" title="GTX3:CHAN_BOND_SEQ_1_ENABLE[2]">GTX3:CHAN_BOND_SEQ_1_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[12]">GTX3:DRP04[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_ENABLE" title="GTX3:CHAN_BOND_SEQ_1_ENABLE[3]">GTX3:CHAN_BOND_SEQ_1_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[13]">GTX3:DRP04[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[14]">GTX3:DRP04[14]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_BUFFER_USE" title="GTX3:RX_BUFFER_USE">GTX3:RX_BUFFER_USE</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP04" title="GTX3:DRP04[15]">GTX3:DRP04[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_LOSS_OF_SYNC_FSM" title="GTX3:RX_LOSS_OF_SYNC_FSM">GTX3:RX_LOSS_OF_SYNC_FSM</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_2" title="GTX3:CHAN_BOND_SEQ_1_2[0]">GTX3:CHAN_BOND_SEQ_1_2[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[0]">GTX3:DRP05[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_2" title="GTX3:CHAN_BOND_SEQ_1_2[1]">GTX3:CHAN_BOND_SEQ_1_2[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[1]">GTX3:DRP05[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_2" title="GTX3:CHAN_BOND_SEQ_1_2[2]">GTX3:CHAN_BOND_SEQ_1_2[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[2]">GTX3:DRP05[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_2" title="GTX3:CHAN_BOND_SEQ_1_2[3]">GTX3:CHAN_BOND_SEQ_1_2[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[3]">GTX3:DRP05[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_2" title="GTX3:CHAN_BOND_SEQ_1_2[4]">GTX3:CHAN_BOND_SEQ_1_2[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[4]">GTX3:DRP05[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_2" title="GTX3:CHAN_BOND_SEQ_1_2[5]">GTX3:CHAN_BOND_SEQ_1_2[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[5]">GTX3:DRP05[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_2" title="GTX3:CHAN_BOND_SEQ_1_2[6]">GTX3:CHAN_BOND_SEQ_1_2[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[6]">GTX3:DRP05[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_2" title="GTX3:CHAN_BOND_SEQ_1_2[7]">GTX3:CHAN_BOND_SEQ_1_2[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[7]">GTX3:DRP05[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_2" title="GTX3:CHAN_BOND_SEQ_1_2[8]">GTX3:CHAN_BOND_SEQ_1_2[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[8]">GTX3:DRP05[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_2" title="GTX3:CHAN_BOND_SEQ_1_2[9]">GTX3:CHAN_BOND_SEQ_1_2[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[9]">GTX3:DRP05[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_1_MAX_SKEW" title="GTX3:CHAN_BOND_1_MAX_SKEW[0]">GTX3:CHAN_BOND_1_MAX_SKEW[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[10]">GTX3:DRP05[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_1_MAX_SKEW" title="GTX3:CHAN_BOND_1_MAX_SKEW[1]">GTX3:CHAN_BOND_1_MAX_SKEW[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[11]">GTX3:DRP05[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_1_MAX_SKEW" title="GTX3:CHAN_BOND_1_MAX_SKEW[2]">GTX3:CHAN_BOND_1_MAX_SKEW[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[12]">GTX3:DRP05[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_1_MAX_SKEW" title="GTX3:CHAN_BOND_1_MAX_SKEW[3]">GTX3:CHAN_BOND_1_MAX_SKEW[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[13]">GTX3:DRP05[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[14]">GTX3:DRP05[14]</a><br><a href="#bits-xc6v-GTX-GTX3:INV.RXUSRCLK" title="~GTX3:INV.RXUSRCLK">~GTX3:INV.RXUSRCLK</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP05" title="GTX3:DRP05[15]">GTX3:DRP05[15]</a><br><a href="#bits-xc6v-GTX-GTX3:INV.RXUSRCLK2" title="~GTX3:INV.RXUSRCLK2">~GTX3:INV.RXUSRCLK2</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_3" title="GTX3:CHAN_BOND_SEQ_1_3[0]">GTX3:CHAN_BOND_SEQ_1_3[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[0]">GTX3:DRP06[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_3" title="GTX3:CHAN_BOND_SEQ_1_3[1]">GTX3:CHAN_BOND_SEQ_1_3[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[1]">GTX3:DRP06[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_3" title="GTX3:CHAN_BOND_SEQ_1_3[2]">GTX3:CHAN_BOND_SEQ_1_3[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[2]">GTX3:DRP06[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_3" title="GTX3:CHAN_BOND_SEQ_1_3[3]">GTX3:CHAN_BOND_SEQ_1_3[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[3]">GTX3:DRP06[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_3" title="GTX3:CHAN_BOND_SEQ_1_3[4]">GTX3:CHAN_BOND_SEQ_1_3[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[4]">GTX3:DRP06[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_3" title="GTX3:CHAN_BOND_SEQ_1_3[5]">GTX3:CHAN_BOND_SEQ_1_3[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[5]">GTX3:DRP06[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_3" title="GTX3:CHAN_BOND_SEQ_1_3[6]">GTX3:CHAN_BOND_SEQ_1_3[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[6]">GTX3:DRP06[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_3" title="GTX3:CHAN_BOND_SEQ_1_3[7]">GTX3:CHAN_BOND_SEQ_1_3[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[7]">GTX3:DRP06[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_3" title="GTX3:CHAN_BOND_SEQ_1_3[8]">GTX3:CHAN_BOND_SEQ_1_3[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[8]">GTX3:DRP06[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_3" title="GTX3:CHAN_BOND_SEQ_1_3[9]">GTX3:CHAN_BOND_SEQ_1_3[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[9]">GTX3:DRP06[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[10]">GTX3:DRP06[10]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_LOS_THRESHOLD" title="GTX3:RX_LOS_THRESHOLD[0]">GTX3:RX_LOS_THRESHOLD[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[11]">GTX3:DRP06[11]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_LOS_THRESHOLD" title="GTX3:RX_LOS_THRESHOLD[1]">GTX3:RX_LOS_THRESHOLD[1]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[12]">GTX3:DRP06[12]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_LOS_THRESHOLD" title="GTX3:RX_LOS_THRESHOLD[2]">GTX3:RX_LOS_THRESHOLD[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[13]">GTX3:DRP06[13]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_LOS_INVALID_INCR" title="GTX3:RX_LOS_INVALID_INCR[0]">GTX3:RX_LOS_INVALID_INCR[0]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[14]">GTX3:DRP06[14]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_LOS_INVALID_INCR" title="GTX3:RX_LOS_INVALID_INCR[1]">GTX3:RX_LOS_INVALID_INCR[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP06" title="GTX3:DRP06[15]">GTX3:DRP06[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_LOS_INVALID_INCR" title="GTX3:RX_LOS_INVALID_INCR[2]">GTX3:RX_LOS_INVALID_INCR[2]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_4" title="GTX3:CHAN_BOND_SEQ_1_4[0]">GTX3:CHAN_BOND_SEQ_1_4[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[0]">GTX3:DRP07[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_4" title="GTX3:CHAN_BOND_SEQ_1_4[1]">GTX3:CHAN_BOND_SEQ_1_4[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[1]">GTX3:DRP07[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_4" title="GTX3:CHAN_BOND_SEQ_1_4[2]">GTX3:CHAN_BOND_SEQ_1_4[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[2]">GTX3:DRP07[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_4" title="GTX3:CHAN_BOND_SEQ_1_4[3]">GTX3:CHAN_BOND_SEQ_1_4[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[3]">GTX3:DRP07[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_4" title="GTX3:CHAN_BOND_SEQ_1_4[4]">GTX3:CHAN_BOND_SEQ_1_4[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[4]">GTX3:DRP07[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_4" title="GTX3:CHAN_BOND_SEQ_1_4[5]">GTX3:CHAN_BOND_SEQ_1_4[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[5]">GTX3:DRP07[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_4" title="GTX3:CHAN_BOND_SEQ_1_4[6]">GTX3:CHAN_BOND_SEQ_1_4[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[6]">GTX3:DRP07[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_4" title="GTX3:CHAN_BOND_SEQ_1_4[7]">GTX3:CHAN_BOND_SEQ_1_4[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[7]">GTX3:DRP07[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_4" title="GTX3:CHAN_BOND_SEQ_1_4[8]">GTX3:CHAN_BOND_SEQ_1_4[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[8]">GTX3:DRP07[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_4" title="GTX3:CHAN_BOND_SEQ_1_4[9]">GTX3:CHAN_BOND_SEQ_1_4[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[9]">GTX3:DRP07[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_LEN" title="GTX3:CHAN_BOND_SEQ_LEN[0]">GTX3:CHAN_BOND_SEQ_LEN[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[10]">GTX3:DRP07[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_LEN" title="GTX3:CHAN_BOND_SEQ_LEN[1]">GTX3:CHAN_BOND_SEQ_LEN[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[11]">GTX3:DRP07[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[12]">GTX3:DRP07[12]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_IDLE_LO_CNT" title="GTX3:RX_IDLE_LO_CNT[0]">GTX3:RX_IDLE_LO_CNT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[13]">GTX3:DRP07[13]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_IDLE_LO_CNT" title="GTX3:RX_IDLE_LO_CNT[1]">GTX3:RX_IDLE_LO_CNT[1]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[14]">GTX3:DRP07[14]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_IDLE_LO_CNT" title="GTX3:RX_IDLE_LO_CNT[2]">GTX3:RX_IDLE_LO_CNT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP07" title="GTX3:DRP07[15]">GTX3:DRP07[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_IDLE_LO_CNT" title="GTX3:RX_IDLE_LO_CNT[3]">GTX3:RX_IDLE_LO_CNT[3]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 31</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_1" title="GTX3:CHAN_BOND_SEQ_2_1[0]">GTX3:CHAN_BOND_SEQ_2_1[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[0]">GTX3:DRP08[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_1" title="GTX3:CHAN_BOND_SEQ_2_1[1]">GTX3:CHAN_BOND_SEQ_2_1[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[1]">GTX3:DRP08[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_1" title="GTX3:CHAN_BOND_SEQ_2_1[2]">GTX3:CHAN_BOND_SEQ_2_1[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[2]">GTX3:DRP08[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_1" title="GTX3:CHAN_BOND_SEQ_2_1[3]">GTX3:CHAN_BOND_SEQ_2_1[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[3]">GTX3:DRP08[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_1" title="GTX3:CHAN_BOND_SEQ_2_1[4]">GTX3:CHAN_BOND_SEQ_2_1[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[4]">GTX3:DRP08[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_1" title="GTX3:CHAN_BOND_SEQ_2_1[5]">GTX3:CHAN_BOND_SEQ_2_1[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[5]">GTX3:DRP08[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_1" title="GTX3:CHAN_BOND_SEQ_2_1[6]">GTX3:CHAN_BOND_SEQ_2_1[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[6]">GTX3:DRP08[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_1" title="GTX3:CHAN_BOND_SEQ_2_1[7]">GTX3:CHAN_BOND_SEQ_2_1[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[7]">GTX3:DRP08[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_1" title="GTX3:CHAN_BOND_SEQ_2_1[8]">GTX3:CHAN_BOND_SEQ_2_1[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[8]">GTX3:DRP08[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_1" title="GTX3:CHAN_BOND_SEQ_2_1[9]">GTX3:CHAN_BOND_SEQ_2_1[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[9]">GTX3:DRP08[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_ENABLE" title="GTX3:CHAN_BOND_SEQ_2_ENABLE[0]">GTX3:CHAN_BOND_SEQ_2_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[10]">GTX3:DRP08[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_ENABLE" title="GTX3:CHAN_BOND_SEQ_2_ENABLE[1]">GTX3:CHAN_BOND_SEQ_2_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[11]">GTX3:DRP08[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_ENABLE" title="GTX3:CHAN_BOND_SEQ_2_ENABLE[2]">GTX3:CHAN_BOND_SEQ_2_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[12]">GTX3:DRP08[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_ENABLE" title="GTX3:CHAN_BOND_SEQ_2_ENABLE[3]">GTX3:CHAN_BOND_SEQ_2_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[13]">GTX3:DRP08[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[14]">GTX3:DRP08[14]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EN_REALIGN_RESET_BUF" title="GTX3:RX_EN_REALIGN_RESET_BUF">GTX3:RX_EN_REALIGN_RESET_BUF</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP08" title="GTX3:DRP08[15]">GTX3:DRP08[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EN_RATE_RESET_BUF" title="GTX3:RX_EN_RATE_RESET_BUF">GTX3:RX_EN_RATE_RESET_BUF</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_2" title="GTX3:CHAN_BOND_SEQ_2_2[0]">GTX3:CHAN_BOND_SEQ_2_2[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[0]">GTX3:DRP09[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_2" title="GTX3:CHAN_BOND_SEQ_2_2[1]">GTX3:CHAN_BOND_SEQ_2_2[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[1]">GTX3:DRP09[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_2" title="GTX3:CHAN_BOND_SEQ_2_2[2]">GTX3:CHAN_BOND_SEQ_2_2[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[2]">GTX3:DRP09[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_2" title="GTX3:CHAN_BOND_SEQ_2_2[3]">GTX3:CHAN_BOND_SEQ_2_2[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[3]">GTX3:DRP09[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_2" title="GTX3:CHAN_BOND_SEQ_2_2[4]">GTX3:CHAN_BOND_SEQ_2_2[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[4]">GTX3:DRP09[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_2" title="GTX3:CHAN_BOND_SEQ_2_2[5]">GTX3:CHAN_BOND_SEQ_2_2[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[5]">GTX3:DRP09[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_2" title="GTX3:CHAN_BOND_SEQ_2_2[6]">GTX3:CHAN_BOND_SEQ_2_2[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[6]">GTX3:DRP09[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_2" title="GTX3:CHAN_BOND_SEQ_2_2[7]">GTX3:CHAN_BOND_SEQ_2_2[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[7]">GTX3:DRP09[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_2" title="GTX3:CHAN_BOND_SEQ_2_2[8]">GTX3:CHAN_BOND_SEQ_2_2[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[8]">GTX3:DRP09[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_2" title="GTX3:CHAN_BOND_SEQ_2_2[9]">GTX3:CHAN_BOND_SEQ_2_2[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[9]">GTX3:DRP09[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_2_MAX_SKEW" title="GTX3:CHAN_BOND_2_MAX_SKEW[0]">GTX3:CHAN_BOND_2_MAX_SKEW[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[10]">GTX3:DRP09[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_2_MAX_SKEW" title="GTX3:CHAN_BOND_2_MAX_SKEW[1]">GTX3:CHAN_BOND_2_MAX_SKEW[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[11]">GTX3:DRP09[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_2_MAX_SKEW" title="GTX3:CHAN_BOND_2_MAX_SKEW[2]">GTX3:CHAN_BOND_2_MAX_SKEW[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[12]">GTX3:DRP09[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_2_MAX_SKEW" title="GTX3:CHAN_BOND_2_MAX_SKEW[3]">GTX3:CHAN_BOND_2_MAX_SKEW[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[13]">GTX3:DRP09[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_KEEP_ALIGN" title="GTX3:CHAN_BOND_KEEP_ALIGN">GTX3:CHAN_BOND_KEEP_ALIGN</a><br><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[14]">GTX3:DRP09[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP09" title="GTX3:DRP09[15]">GTX3:DRP09[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EN_MODE_RESET_BUF" title="GTX3:RX_EN_MODE_RESET_BUF">GTX3:RX_EN_MODE_RESET_BUF</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_3" title="GTX3:CHAN_BOND_SEQ_2_3[0]">GTX3:CHAN_BOND_SEQ_2_3[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[0]">GTX3:DRP0A[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_3" title="GTX3:CHAN_BOND_SEQ_2_3[1]">GTX3:CHAN_BOND_SEQ_2_3[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[1]">GTX3:DRP0A[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_3" title="GTX3:CHAN_BOND_SEQ_2_3[2]">GTX3:CHAN_BOND_SEQ_2_3[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[2]">GTX3:DRP0A[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_3" title="GTX3:CHAN_BOND_SEQ_2_3[3]">GTX3:CHAN_BOND_SEQ_2_3[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[3]">GTX3:DRP0A[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_3" title="GTX3:CHAN_BOND_SEQ_2_3[4]">GTX3:CHAN_BOND_SEQ_2_3[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[4]">GTX3:DRP0A[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_3" title="GTX3:CHAN_BOND_SEQ_2_3[5]">GTX3:CHAN_BOND_SEQ_2_3[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[5]">GTX3:DRP0A[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_3" title="GTX3:CHAN_BOND_SEQ_2_3[6]">GTX3:CHAN_BOND_SEQ_2_3[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[6]">GTX3:DRP0A[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_3" title="GTX3:CHAN_BOND_SEQ_2_3[7]">GTX3:CHAN_BOND_SEQ_2_3[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[7]">GTX3:DRP0A[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_3" title="GTX3:CHAN_BOND_SEQ_2_3[8]">GTX3:CHAN_BOND_SEQ_2_3[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[8]">GTX3:DRP0A[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_3" title="GTX3:CHAN_BOND_SEQ_2_3[9]">GTX3:CHAN_BOND_SEQ_2_3[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[9]">GTX3:DRP0A[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_CFG" title="GTX3:CHAN_BOND_SEQ_2_CFG[0]">GTX3:CHAN_BOND_SEQ_2_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[10]">GTX3:DRP0A[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_CFG" title="GTX3:CHAN_BOND_SEQ_2_CFG[1]">GTX3:CHAN_BOND_SEQ_2_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[11]">GTX3:DRP0A[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_CFG" title="GTX3:CHAN_BOND_SEQ_2_CFG[2]">GTX3:CHAN_BOND_SEQ_2_CFG[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[12]">GTX3:DRP0A[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_CFG" title="GTX3:CHAN_BOND_SEQ_2_CFG[3]">GTX3:CHAN_BOND_SEQ_2_CFG[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[13]">GTX3:DRP0A[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_USE" title="GTX3:CHAN_BOND_SEQ_2_USE">GTX3:CHAN_BOND_SEQ_2_USE</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[14]">GTX3:DRP0A[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP0A" title="GTX3:DRP0A[15]">GTX3:DRP0A[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EN_IDLE_RESET_PH" title="GTX3:RX_EN_IDLE_RESET_PH">GTX3:RX_EN_IDLE_RESET_PH</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_4" title="GTX3:CHAN_BOND_SEQ_2_4[0]">GTX3:CHAN_BOND_SEQ_2_4[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[0]">GTX3:DRP0B[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_4" title="GTX3:CHAN_BOND_SEQ_2_4[1]">GTX3:CHAN_BOND_SEQ_2_4[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[1]">GTX3:DRP0B[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_4" title="GTX3:CHAN_BOND_SEQ_2_4[2]">GTX3:CHAN_BOND_SEQ_2_4[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[2]">GTX3:DRP0B[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_4" title="GTX3:CHAN_BOND_SEQ_2_4[3]">GTX3:CHAN_BOND_SEQ_2_4[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[3]">GTX3:DRP0B[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_4" title="GTX3:CHAN_BOND_SEQ_2_4[4]">GTX3:CHAN_BOND_SEQ_2_4[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[4]">GTX3:DRP0B[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_4" title="GTX3:CHAN_BOND_SEQ_2_4[5]">GTX3:CHAN_BOND_SEQ_2_4[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[5]">GTX3:DRP0B[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_4" title="GTX3:CHAN_BOND_SEQ_2_4[6]">GTX3:CHAN_BOND_SEQ_2_4[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[6]">GTX3:DRP0B[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_4" title="GTX3:CHAN_BOND_SEQ_2_4[7]">GTX3:CHAN_BOND_SEQ_2_4[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[7]">GTX3:DRP0B[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_4" title="GTX3:CHAN_BOND_SEQ_2_4[8]">GTX3:CHAN_BOND_SEQ_2_4[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[8]">GTX3:DRP0B[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_4" title="GTX3:CHAN_BOND_SEQ_2_4[9]">GTX3:CHAN_BOND_SEQ_2_4[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[9]">GTX3:DRP0B[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[10]">GTX3:DRP0B[10]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EN_IDLE_RESET_BUF" title="GTX3:RX_EN_IDLE_RESET_BUF">GTX3:RX_EN_IDLE_RESET_BUF</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[11]">GTX3:DRP0B[11]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_XCLK_SEL" title="GTX3:RX_XCLK_SEL">GTX3:RX_XCLK_SEL</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[12]">GTX3:DRP0B[12]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_IDLE_HI_CNT" title="GTX3:RX_IDLE_HI_CNT[0]">GTX3:RX_IDLE_HI_CNT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[13]">GTX3:DRP0B[13]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_IDLE_HI_CNT" title="GTX3:RX_IDLE_HI_CNT[1]">GTX3:RX_IDLE_HI_CNT[1]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[14]">GTX3:DRP0B[14]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_IDLE_HI_CNT" title="GTX3:RX_IDLE_HI_CNT[2]">GTX3:RX_IDLE_HI_CNT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP0B" title="GTX3:DRP0B[15]">GTX3:DRP0B[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_IDLE_HI_CNT" title="GTX3:RX_IDLE_HI_CNT[3]">GTX3:RX_IDLE_HI_CNT[3]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[0]">GTX3:DRP0C[0]</a><br><a href="#bits-xc6v-GTX-GTX3:RXBUF_OVFL_THRESH" title="GTX3:RXBUF_OVFL_THRESH[0]">GTX3:RXBUF_OVFL_THRESH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[1]">GTX3:DRP0C[1]</a><br><a href="#bits-xc6v-GTX-GTX3:RXBUF_OVFL_THRESH" title="GTX3:RXBUF_OVFL_THRESH[1]">GTX3:RXBUF_OVFL_THRESH[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[2]">GTX3:DRP0C[2]</a><br><a href="#bits-xc6v-GTX-GTX3:RXBUF_OVFL_THRESH" title="GTX3:RXBUF_OVFL_THRESH[2]">GTX3:RXBUF_OVFL_THRESH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[3]">GTX3:DRP0C[3]</a><br><a href="#bits-xc6v-GTX-GTX3:RXBUF_OVFL_THRESH" title="GTX3:RXBUF_OVFL_THRESH[3]">GTX3:RXBUF_OVFL_THRESH[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[4]">GTX3:DRP0C[4]</a><br><a href="#bits-xc6v-GTX-GTX3:RXBUF_OVFL_THRESH" title="GTX3:RXBUF_OVFL_THRESH[4]">GTX3:RXBUF_OVFL_THRESH[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[5]">GTX3:DRP0C[5]</a><br><a href="#bits-xc6v-GTX-GTX3:RXBUF_OVFL_THRESH" title="GTX3:RXBUF_OVFL_THRESH[5]">GTX3:RXBUF_OVFL_THRESH[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[6]">GTX3:DRP0C[6]</a><br><a href="#bits-xc6v-GTX-GTX3:RXBUF_UDFL_THRESH" title="GTX3:RXBUF_UDFL_THRESH[0]">GTX3:RXBUF_UDFL_THRESH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[7]">GTX3:DRP0C[7]</a><br><a href="#bits-xc6v-GTX-GTX3:RXBUF_UDFL_THRESH" title="GTX3:RXBUF_UDFL_THRESH[1]">GTX3:RXBUF_UDFL_THRESH[1]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[8]">GTX3:DRP0C[8]</a><br><a href="#bits-xc6v-GTX-GTX3:RXBUF_UDFL_THRESH" title="GTX3:RXBUF_UDFL_THRESH[2]">GTX3:RXBUF_UDFL_THRESH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[9]">GTX3:DRP0C[9]</a><br><a href="#bits-xc6v-GTX-GTX3:RXBUF_UDFL_THRESH" title="GTX3:RXBUF_UDFL_THRESH[3]">GTX3:RXBUF_UDFL_THRESH[3]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[10]">GTX3:DRP0C[10]</a><br><a href="#bits-xc6v-GTX-GTX3:RXBUF_UDFL_THRESH" title="GTX3:RXBUF_UDFL_THRESH[4]">GTX3:RXBUF_UDFL_THRESH[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[11]">GTX3:DRP0C[11]</a><br><a href="#bits-xc6v-GTX-GTX3:RXBUF_UDFL_THRESH" title="GTX3:RXBUF_UDFL_THRESH[5]">GTX3:RXBUF_UDFL_THRESH[5]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[12]">GTX3:DRP0C[12]</a><br><a href="#bits-xc6v-GTX-GTX3:RXBUF_OVRD_THRESH" title="GTX3:RXBUF_OVRD_THRESH">GTX3:RXBUF_OVRD_THRESH</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[13]">GTX3:DRP0C[13]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_FIFO_ADDR_MODE" title="GTX3:RX_FIFO_ADDR_MODE">GTX3:RX_FIFO_ADDR_MODE</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[14]">GTX3:DRP0C[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP0C" title="GTX3:DRP0C[15]">GTX3:DRP0C[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_1" title="GTX3:CLK_COR_SEQ_1_1[0]">GTX3:CLK_COR_SEQ_1_1[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[0]">GTX3:DRP0D[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_1" title="GTX3:CLK_COR_SEQ_1_1[1]">GTX3:CLK_COR_SEQ_1_1[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[1]">GTX3:DRP0D[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_1" title="GTX3:CLK_COR_SEQ_1_1[2]">GTX3:CLK_COR_SEQ_1_1[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[2]">GTX3:DRP0D[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_1" title="GTX3:CLK_COR_SEQ_1_1[3]">GTX3:CLK_COR_SEQ_1_1[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[3]">GTX3:DRP0D[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_1" title="GTX3:CLK_COR_SEQ_1_1[4]">GTX3:CLK_COR_SEQ_1_1[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[4]">GTX3:DRP0D[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_1" title="GTX3:CLK_COR_SEQ_1_1[5]">GTX3:CLK_COR_SEQ_1_1[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[5]">GTX3:DRP0D[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_1" title="GTX3:CLK_COR_SEQ_1_1[6]">GTX3:CLK_COR_SEQ_1_1[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[6]">GTX3:DRP0D[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_1" title="GTX3:CLK_COR_SEQ_1_1[7]">GTX3:CLK_COR_SEQ_1_1[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[7]">GTX3:DRP0D[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_1" title="GTX3:CLK_COR_SEQ_1_1[8]">GTX3:CLK_COR_SEQ_1_1[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[8]">GTX3:DRP0D[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_1" title="GTX3:CLK_COR_SEQ_1_1[9]">GTX3:CLK_COR_SEQ_1_1[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[9]">GTX3:DRP0D[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_ENABLE" title="GTX3:CLK_COR_SEQ_1_ENABLE[0]">GTX3:CLK_COR_SEQ_1_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[10]">GTX3:DRP0D[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_ENABLE" title="GTX3:CLK_COR_SEQ_1_ENABLE[1]">GTX3:CLK_COR_SEQ_1_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[11]">GTX3:DRP0D[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_ENABLE" title="GTX3:CLK_COR_SEQ_1_ENABLE[2]">GTX3:CLK_COR_SEQ_1_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[12]">GTX3:DRP0D[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_ENABLE" title="GTX3:CLK_COR_SEQ_1_ENABLE[3]">GTX3:CLK_COR_SEQ_1_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[13]">GTX3:DRP0D[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_CORRECT_USE" title="GTX3:CLK_CORRECT_USE">GTX3:CLK_CORRECT_USE</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[14]">GTX3:DRP0D[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_PRECEDENCE" title="GTX3:CLK_COR_PRECEDENCE">GTX3:CLK_COR_PRECEDENCE</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0D" title="GTX3:DRP0D[15]">GTX3:DRP0D[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_2" title="GTX3:CLK_COR_SEQ_1_2[0]">GTX3:CLK_COR_SEQ_1_2[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[0]">GTX3:DRP0E[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_2" title="GTX3:CLK_COR_SEQ_1_2[1]">GTX3:CLK_COR_SEQ_1_2[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[1]">GTX3:DRP0E[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_2" title="GTX3:CLK_COR_SEQ_1_2[2]">GTX3:CLK_COR_SEQ_1_2[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[2]">GTX3:DRP0E[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_2" title="GTX3:CLK_COR_SEQ_1_2[3]">GTX3:CLK_COR_SEQ_1_2[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[3]">GTX3:DRP0E[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_2" title="GTX3:CLK_COR_SEQ_1_2[4]">GTX3:CLK_COR_SEQ_1_2[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[4]">GTX3:DRP0E[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_2" title="GTX3:CLK_COR_SEQ_1_2[5]">GTX3:CLK_COR_SEQ_1_2[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[5]">GTX3:DRP0E[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_2" title="GTX3:CLK_COR_SEQ_1_2[6]">GTX3:CLK_COR_SEQ_1_2[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[6]">GTX3:DRP0E[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_2" title="GTX3:CLK_COR_SEQ_1_2[7]">GTX3:CLK_COR_SEQ_1_2[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[7]">GTX3:DRP0E[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_2" title="GTX3:CLK_COR_SEQ_1_2[8]">GTX3:CLK_COR_SEQ_1_2[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[8]">GTX3:DRP0E[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_2" title="GTX3:CLK_COR_SEQ_1_2[9]">GTX3:CLK_COR_SEQ_1_2[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[9]">GTX3:DRP0E[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_REPEAT_WAIT" title="GTX3:CLK_COR_REPEAT_WAIT[0]">GTX3:CLK_COR_REPEAT_WAIT[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[10]">GTX3:DRP0E[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_REPEAT_WAIT" title="GTX3:CLK_COR_REPEAT_WAIT[1]">GTX3:CLK_COR_REPEAT_WAIT[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[11]">GTX3:DRP0E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_REPEAT_WAIT" title="GTX3:CLK_COR_REPEAT_WAIT[2]">GTX3:CLK_COR_REPEAT_WAIT[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[12]">GTX3:DRP0E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_REPEAT_WAIT" title="GTX3:CLK_COR_REPEAT_WAIT[3]">GTX3:CLK_COR_REPEAT_WAIT[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[13]">GTX3:DRP0E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_REPEAT_WAIT" title="GTX3:CLK_COR_REPEAT_WAIT[4]">GTX3:CLK_COR_REPEAT_WAIT[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[14]">GTX3:DRP0E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_KEEP_IDLE" title="GTX3:CLK_COR_KEEP_IDLE">GTX3:CLK_COR_KEEP_IDLE</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0E" title="GTX3:DRP0E[15]">GTX3:DRP0E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_3" title="GTX3:CLK_COR_SEQ_1_3[0]">GTX3:CLK_COR_SEQ_1_3[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[0]">GTX3:DRP0F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_3" title="GTX3:CLK_COR_SEQ_1_3[1]">GTX3:CLK_COR_SEQ_1_3[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[1]">GTX3:DRP0F[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_3" title="GTX3:CLK_COR_SEQ_1_3[2]">GTX3:CLK_COR_SEQ_1_3[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[2]">GTX3:DRP0F[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_3" title="GTX3:CLK_COR_SEQ_1_3[3]">GTX3:CLK_COR_SEQ_1_3[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[3]">GTX3:DRP0F[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_3" title="GTX3:CLK_COR_SEQ_1_3[4]">GTX3:CLK_COR_SEQ_1_3[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[4]">GTX3:DRP0F[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_3" title="GTX3:CLK_COR_SEQ_1_3[5]">GTX3:CLK_COR_SEQ_1_3[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[5]">GTX3:DRP0F[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_3" title="GTX3:CLK_COR_SEQ_1_3[6]">GTX3:CLK_COR_SEQ_1_3[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[6]">GTX3:DRP0F[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_3" title="GTX3:CLK_COR_SEQ_1_3[7]">GTX3:CLK_COR_SEQ_1_3[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[7]">GTX3:DRP0F[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_3" title="GTX3:CLK_COR_SEQ_1_3[8]">GTX3:CLK_COR_SEQ_1_3[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[8]">GTX3:DRP0F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_3" title="GTX3:CLK_COR_SEQ_1_3[9]">GTX3:CLK_COR_SEQ_1_3[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[9]">GTX3:DRP0F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_MIN_LAT" title="GTX3:CLK_COR_MIN_LAT[0]">GTX3:CLK_COR_MIN_LAT[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[10]">GTX3:DRP0F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_MIN_LAT" title="GTX3:CLK_COR_MIN_LAT[1]">GTX3:CLK_COR_MIN_LAT[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[11]">GTX3:DRP0F[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_MIN_LAT" title="GTX3:CLK_COR_MIN_LAT[2]">GTX3:CLK_COR_MIN_LAT[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[12]">GTX3:DRP0F[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_MIN_LAT" title="GTX3:CLK_COR_MIN_LAT[3]">GTX3:CLK_COR_MIN_LAT[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[13]">GTX3:DRP0F[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_MIN_LAT" title="GTX3:CLK_COR_MIN_LAT[4]">GTX3:CLK_COR_MIN_LAT[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[14]">GTX3:DRP0F[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_MIN_LAT" title="GTX3:CLK_COR_MIN_LAT[5]">GTX3:CLK_COR_MIN_LAT[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP0F" title="GTX3:DRP0F[15]">GTX3:DRP0F[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 32</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_4" title="GTX3:CLK_COR_SEQ_1_4[0]">GTX3:CLK_COR_SEQ_1_4[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[0]">GTX3:DRP10[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_4" title="GTX3:CLK_COR_SEQ_1_4[1]">GTX3:CLK_COR_SEQ_1_4[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[1]">GTX3:DRP10[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_4" title="GTX3:CLK_COR_SEQ_1_4[2]">GTX3:CLK_COR_SEQ_1_4[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[2]">GTX3:DRP10[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_4" title="GTX3:CLK_COR_SEQ_1_4[3]">GTX3:CLK_COR_SEQ_1_4[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[3]">GTX3:DRP10[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_4" title="GTX3:CLK_COR_SEQ_1_4[4]">GTX3:CLK_COR_SEQ_1_4[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[4]">GTX3:DRP10[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_4" title="GTX3:CLK_COR_SEQ_1_4[5]">GTX3:CLK_COR_SEQ_1_4[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[5]">GTX3:DRP10[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_4" title="GTX3:CLK_COR_SEQ_1_4[6]">GTX3:CLK_COR_SEQ_1_4[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[6]">GTX3:DRP10[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_4" title="GTX3:CLK_COR_SEQ_1_4[7]">GTX3:CLK_COR_SEQ_1_4[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[7]">GTX3:DRP10[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_4" title="GTX3:CLK_COR_SEQ_1_4[8]">GTX3:CLK_COR_SEQ_1_4[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[8]">GTX3:DRP10[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_4" title="GTX3:CLK_COR_SEQ_1_4[9]">GTX3:CLK_COR_SEQ_1_4[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[9]">GTX3:DRP10[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_MAX_LAT" title="GTX3:CLK_COR_MAX_LAT[0]">GTX3:CLK_COR_MAX_LAT[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[10]">GTX3:DRP10[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_MAX_LAT" title="GTX3:CLK_COR_MAX_LAT[1]">GTX3:CLK_COR_MAX_LAT[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[11]">GTX3:DRP10[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_MAX_LAT" title="GTX3:CLK_COR_MAX_LAT[2]">GTX3:CLK_COR_MAX_LAT[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[12]">GTX3:DRP10[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_MAX_LAT" title="GTX3:CLK_COR_MAX_LAT[3]">GTX3:CLK_COR_MAX_LAT[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[13]">GTX3:DRP10[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_MAX_LAT" title="GTX3:CLK_COR_MAX_LAT[4]">GTX3:CLK_COR_MAX_LAT[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[14]">GTX3:DRP10[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_MAX_LAT" title="GTX3:CLK_COR_MAX_LAT[5]">GTX3:CLK_COR_MAX_LAT[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP10" title="GTX3:DRP10[15]">GTX3:DRP10[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_1" title="GTX3:CLK_COR_SEQ_2_1[0]">GTX3:CLK_COR_SEQ_2_1[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[0]">GTX3:DRP11[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_1" title="GTX3:CLK_COR_SEQ_2_1[1]">GTX3:CLK_COR_SEQ_2_1[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[1]">GTX3:DRP11[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_1" title="GTX3:CLK_COR_SEQ_2_1[2]">GTX3:CLK_COR_SEQ_2_1[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[2]">GTX3:DRP11[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_1" title="GTX3:CLK_COR_SEQ_2_1[3]">GTX3:CLK_COR_SEQ_2_1[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[3]">GTX3:DRP11[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_1" title="GTX3:CLK_COR_SEQ_2_1[4]">GTX3:CLK_COR_SEQ_2_1[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[4]">GTX3:DRP11[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_1" title="GTX3:CLK_COR_SEQ_2_1[5]">GTX3:CLK_COR_SEQ_2_1[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[5]">GTX3:DRP11[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_1" title="GTX3:CLK_COR_SEQ_2_1[6]">GTX3:CLK_COR_SEQ_2_1[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[6]">GTX3:DRP11[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_1" title="GTX3:CLK_COR_SEQ_2_1[7]">GTX3:CLK_COR_SEQ_2_1[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[7]">GTX3:DRP11[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_1" title="GTX3:CLK_COR_SEQ_2_1[8]">GTX3:CLK_COR_SEQ_2_1[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[8]">GTX3:DRP11[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_1" title="GTX3:CLK_COR_SEQ_2_1[9]">GTX3:CLK_COR_SEQ_2_1[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[9]">GTX3:DRP11[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_ENABLE" title="GTX3:CLK_COR_SEQ_2_ENABLE[0]">GTX3:CLK_COR_SEQ_2_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[10]">GTX3:DRP11[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_ENABLE" title="GTX3:CLK_COR_SEQ_2_ENABLE[1]">GTX3:CLK_COR_SEQ_2_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[11]">GTX3:DRP11[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_ENABLE" title="GTX3:CLK_COR_SEQ_2_ENABLE[2]">GTX3:CLK_COR_SEQ_2_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[12]">GTX3:DRP11[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_ENABLE" title="GTX3:CLK_COR_SEQ_2_ENABLE[3]">GTX3:CLK_COR_SEQ_2_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[13]">GTX3:DRP11[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_USE" title="GTX3:CLK_COR_SEQ_2_USE">GTX3:CLK_COR_SEQ_2_USE</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[14]">GTX3:DRP11[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_INSERT_IDLE_FLAG" title="GTX3:CLK_COR_INSERT_IDLE_FLAG">GTX3:CLK_COR_INSERT_IDLE_FLAG</a><br><a href="#bits-xc6v-GTX-GTX3:DRP11" title="GTX3:DRP11[15]">GTX3:DRP11[15]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_2" title="GTX3:CLK_COR_SEQ_2_2[0]">GTX3:CLK_COR_SEQ_2_2[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[0]">GTX3:DRP12[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_2" title="GTX3:CLK_COR_SEQ_2_2[1]">GTX3:CLK_COR_SEQ_2_2[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[1]">GTX3:DRP12[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_2" title="GTX3:CLK_COR_SEQ_2_2[2]">GTX3:CLK_COR_SEQ_2_2[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[2]">GTX3:DRP12[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_2" title="GTX3:CLK_COR_SEQ_2_2[3]">GTX3:CLK_COR_SEQ_2_2[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[3]">GTX3:DRP12[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_2" title="GTX3:CLK_COR_SEQ_2_2[4]">GTX3:CLK_COR_SEQ_2_2[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[4]">GTX3:DRP12[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_2" title="GTX3:CLK_COR_SEQ_2_2[5]">GTX3:CLK_COR_SEQ_2_2[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[5]">GTX3:DRP12[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_2" title="GTX3:CLK_COR_SEQ_2_2[6]">GTX3:CLK_COR_SEQ_2_2[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[6]">GTX3:DRP12[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_2" title="GTX3:CLK_COR_SEQ_2_2[7]">GTX3:CLK_COR_SEQ_2_2[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[7]">GTX3:DRP12[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_2" title="GTX3:CLK_COR_SEQ_2_2[8]">GTX3:CLK_COR_SEQ_2_2[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[8]">GTX3:DRP12[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_2" title="GTX3:CLK_COR_SEQ_2_2[9]">GTX3:CLK_COR_SEQ_2_2[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[9]">GTX3:DRP12[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_ADJ_LEN" title="GTX3:CLK_COR_ADJ_LEN[0]">GTX3:CLK_COR_ADJ_LEN[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[10]">GTX3:DRP12[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_ADJ_LEN" title="GTX3:CLK_COR_ADJ_LEN[1]">GTX3:CLK_COR_ADJ_LEN[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[11]">GTX3:DRP12[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[12]">GTX3:DRP12[12]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_SLIDE_MODE" title="GTX3:RX_SLIDE_MODE[0]">GTX3:RX_SLIDE_MODE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[13]">GTX3:DRP12[13]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_SLIDE_MODE" title="GTX3:RX_SLIDE_MODE[1]">GTX3:RX_SLIDE_MODE[1]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[14]">GTX3:DRP12[14]</a><br><a href="#bits-xc6v-GTX-GTX3:SHOW_REALIGN_COMMA" title="GTX3:SHOW_REALIGN_COMMA">GTX3:SHOW_REALIGN_COMMA</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP12" title="GTX3:DRP12[15]">GTX3:DRP12[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_CDR_FORCE_ROTATE" title="GTX3:RX_CDR_FORCE_ROTATE">GTX3:RX_CDR_FORCE_ROTATE</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_3" title="GTX3:CLK_COR_SEQ_2_3[0]">GTX3:CLK_COR_SEQ_2_3[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[0]">GTX3:DRP13[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_3" title="GTX3:CLK_COR_SEQ_2_3[1]">GTX3:CLK_COR_SEQ_2_3[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[1]">GTX3:DRP13[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_3" title="GTX3:CLK_COR_SEQ_2_3[2]">GTX3:CLK_COR_SEQ_2_3[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[2]">GTX3:DRP13[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_3" title="GTX3:CLK_COR_SEQ_2_3[3]">GTX3:CLK_COR_SEQ_2_3[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[3]">GTX3:DRP13[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_3" title="GTX3:CLK_COR_SEQ_2_3[4]">GTX3:CLK_COR_SEQ_2_3[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[4]">GTX3:DRP13[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_3" title="GTX3:CLK_COR_SEQ_2_3[5]">GTX3:CLK_COR_SEQ_2_3[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[5]">GTX3:DRP13[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_3" title="GTX3:CLK_COR_SEQ_2_3[6]">GTX3:CLK_COR_SEQ_2_3[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[6]">GTX3:DRP13[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_3" title="GTX3:CLK_COR_SEQ_2_3[7]">GTX3:CLK_COR_SEQ_2_3[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[7]">GTX3:DRP13[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_3" title="GTX3:CLK_COR_SEQ_2_3[8]">GTX3:CLK_COR_SEQ_2_3[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[8]">GTX3:DRP13[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_3" title="GTX3:CLK_COR_SEQ_2_3[9]">GTX3:CLK_COR_SEQ_2_3[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[9]">GTX3:DRP13[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_DET_LEN" title="GTX3:CLK_COR_DET_LEN[0]">GTX3:CLK_COR_DET_LEN[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[10]">GTX3:DRP13[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_DET_LEN" title="GTX3:CLK_COR_DET_LEN[1]">GTX3:CLK_COR_DET_LEN[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[11]">GTX3:DRP13[11]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[12]">GTX3:DRP13[12]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_SLIDE_AUTO_WAIT" title="GTX3:RX_SLIDE_AUTO_WAIT[0]">GTX3:RX_SLIDE_AUTO_WAIT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[13]">GTX3:DRP13[13]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_SLIDE_AUTO_WAIT" title="GTX3:RX_SLIDE_AUTO_WAIT[1]">GTX3:RX_SLIDE_AUTO_WAIT[1]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[14]">GTX3:DRP13[14]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_SLIDE_AUTO_WAIT" title="GTX3:RX_SLIDE_AUTO_WAIT[2]">GTX3:RX_SLIDE_AUTO_WAIT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP13" title="GTX3:DRP13[15]">GTX3:DRP13[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_SLIDE_AUTO_WAIT" title="GTX3:RX_SLIDE_AUTO_WAIT[3]">GTX3:RX_SLIDE_AUTO_WAIT[3]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_4" title="GTX3:CLK_COR_SEQ_2_4[0]">GTX3:CLK_COR_SEQ_2_4[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[0]">GTX3:DRP14[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_4" title="GTX3:CLK_COR_SEQ_2_4[1]">GTX3:CLK_COR_SEQ_2_4[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[1]">GTX3:DRP14[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_4" title="GTX3:CLK_COR_SEQ_2_4[2]">GTX3:CLK_COR_SEQ_2_4[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[2]">GTX3:DRP14[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_4" title="GTX3:CLK_COR_SEQ_2_4[3]">GTX3:CLK_COR_SEQ_2_4[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[3]">GTX3:DRP14[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_4" title="GTX3:CLK_COR_SEQ_2_4[4]">GTX3:CLK_COR_SEQ_2_4[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[4]">GTX3:DRP14[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_4" title="GTX3:CLK_COR_SEQ_2_4[5]">GTX3:CLK_COR_SEQ_2_4[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[5]">GTX3:DRP14[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_4" title="GTX3:CLK_COR_SEQ_2_4[6]">GTX3:CLK_COR_SEQ_2_4[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[6]">GTX3:DRP14[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_4" title="GTX3:CLK_COR_SEQ_2_4[7]">GTX3:CLK_COR_SEQ_2_4[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[7]">GTX3:DRP14[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_4" title="GTX3:CLK_COR_SEQ_2_4[8]">GTX3:CLK_COR_SEQ_2_4[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[8]">GTX3:DRP14[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_4" title="GTX3:CLK_COR_SEQ_2_4[9]">GTX3:CLK_COR_SEQ_2_4[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[9]">GTX3:DRP14[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DEC_PCOMMA_DETECT" title="GTX3:DEC_PCOMMA_DETECT">GTX3:DEC_PCOMMA_DETECT</a><br><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[10]">GTX3:DRP14[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DEC_MCOMMA_DETECT" title="GTX3:DEC_MCOMMA_DETECT">GTX3:DEC_MCOMMA_DETECT</a><br><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[11]">GTX3:DRP14[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[12]">GTX3:DRP14[12]</a><br><a href="#bits-xc6v-GTX-GTX3:USR_CODE_ERR_CLR" title="GTX3:USR_CODE_ERR_CLR">GTX3:USR_CODE_ERR_CLR</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[13]">GTX3:DRP14[13]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DECODE_SEQ_MATCH" title="GTX3:RX_DECODE_SEQ_MATCH">GTX3:RX_DECODE_SEQ_MATCH</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:ALIGN_COMMA_WORD" title="GTX3:ALIGN_COMMA_WORD">GTX3:ALIGN_COMMA_WORD</a><br><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[14]">GTX3:DRP14[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DEC_VALID_COMMA_ONLY" title="GTX3:DEC_VALID_COMMA_ONLY">GTX3:DEC_VALID_COMMA_ONLY</a><br><a href="#bits-xc6v-GTX-GTX3:DRP14" title="GTX3:DRP14[15]">GTX3:DRP14[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[0]">GTX3:DRP15[0]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[0]">GTX3:PMA_CDR_SCAN[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[1]">GTX3:DRP15[1]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[1]">GTX3:PMA_CDR_SCAN[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[2]">GTX3:DRP15[2]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[2]">GTX3:PMA_CDR_SCAN[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[3]">GTX3:DRP15[3]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[3]">GTX3:PMA_CDR_SCAN[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[4]">GTX3:DRP15[4]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[4]">GTX3:PMA_CDR_SCAN[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[5]">GTX3:DRP15[5]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[5]">GTX3:PMA_CDR_SCAN[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[6]">GTX3:DRP15[6]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[6]">GTX3:PMA_CDR_SCAN[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[7]">GTX3:DRP15[7]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[7]">GTX3:PMA_CDR_SCAN[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[8]">GTX3:DRP15[8]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[8]">GTX3:PMA_CDR_SCAN[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[9]">GTX3:DRP15[9]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[9]">GTX3:PMA_CDR_SCAN[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[10]">GTX3:DRP15[10]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[10]">GTX3:PMA_CDR_SCAN[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[11]">GTX3:DRP15[11]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[11]">GTX3:PMA_CDR_SCAN[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[12]">GTX3:DRP15[12]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[12]">GTX3:PMA_CDR_SCAN[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[13]">GTX3:DRP15[13]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[13]">GTX3:PMA_CDR_SCAN[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[14]">GTX3:DRP15[14]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[14]">GTX3:PMA_CDR_SCAN[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP15" title="GTX3:DRP15[15]">GTX3:DRP15[15]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[15]">GTX3:PMA_CDR_SCAN[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[0]">GTX3:DRP16[0]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[16]">GTX3:PMA_CDR_SCAN[16]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[1]">GTX3:DRP16[1]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[17]">GTX3:PMA_CDR_SCAN[17]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[2]">GTX3:DRP16[2]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[18]">GTX3:PMA_CDR_SCAN[18]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[3]">GTX3:DRP16[3]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[19]">GTX3:PMA_CDR_SCAN[19]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[4]">GTX3:DRP16[4]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[20]">GTX3:PMA_CDR_SCAN[20]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[5]">GTX3:DRP16[5]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[21]">GTX3:PMA_CDR_SCAN[21]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[6]">GTX3:DRP16[6]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[22]">GTX3:PMA_CDR_SCAN[22]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[7]">GTX3:DRP16[7]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[23]">GTX3:PMA_CDR_SCAN[23]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[8]">GTX3:DRP16[8]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[24]">GTX3:PMA_CDR_SCAN[24]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[9]">GTX3:DRP16[9]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[25]">GTX3:PMA_CDR_SCAN[25]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[10]">GTX3:DRP16[10]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CDR_SCAN" title="GTX3:PMA_CDR_SCAN[26]">GTX3:PMA_CDR_SCAN[26]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CDR_PH_ADJ_TIME" title="GTX3:CDR_PH_ADJ_TIME[0]">GTX3:CDR_PH_ADJ_TIME[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[11]">GTX3:DRP16[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CDR_PH_ADJ_TIME" title="GTX3:CDR_PH_ADJ_TIME[1]">GTX3:CDR_PH_ADJ_TIME[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[12]">GTX3:DRP16[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CDR_PH_ADJ_TIME" title="GTX3:CDR_PH_ADJ_TIME[2]">GTX3:CDR_PH_ADJ_TIME[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[13]">GTX3:DRP16[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CDR_PH_ADJ_TIME" title="GTX3:CDR_PH_ADJ_TIME[3]">GTX3:CDR_PH_ADJ_TIME[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[14]">GTX3:DRP16[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CDR_PH_ADJ_TIME" title="GTX3:CDR_PH_ADJ_TIME[4]">GTX3:CDR_PH_ADJ_TIME[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP16" title="GTX3:DRP16[15]">GTX3:DRP16[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[0]">GTX3:DRP17[0]</a><br><a href="#bits-xc6v-GTX-GTX3:OOBDETECT_THRESHOLD" title="GTX3:OOBDETECT_THRESHOLD[0]">GTX3:OOBDETECT_THRESHOLD[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[1]">GTX3:DRP17[1]</a><br><a href="#bits-xc6v-GTX-GTX3:OOBDETECT_THRESHOLD" title="GTX3:OOBDETECT_THRESHOLD[1]">GTX3:OOBDETECT_THRESHOLD[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[2]">GTX3:DRP17[2]</a><br><a href="#bits-xc6v-GTX-GTX3:OOBDETECT_THRESHOLD" title="GTX3:OOBDETECT_THRESHOLD[2]">GTX3:OOBDETECT_THRESHOLD[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[3]">GTX3:DRP17[3]</a><br><a href="#bits-xc6v-GTX-GTX3:GTX_CFG_PWRUP" title="GTX3:GTX_CFG_PWRUP">GTX3:GTX_CFG_PWRUP</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:AC_CAP_DIS" title="GTX3:AC_CAP_DIS">GTX3:AC_CAP_DIS</a><br><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[4]">GTX3:DRP17[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[5]">GTX3:DRP17[5]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_CLK25_DIVIDER" title="GTX3:RX_CLK25_DIVIDER[0]">GTX3:RX_CLK25_DIVIDER[0]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[6]">GTX3:DRP17[6]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_CLK25_DIVIDER" title="GTX3:RX_CLK25_DIVIDER[1]">GTX3:RX_CLK25_DIVIDER[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[7]">GTX3:DRP17[7]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_CLK25_DIVIDER" title="GTX3:RX_CLK25_DIVIDER[2]">GTX3:RX_CLK25_DIVIDER[2]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[8]">GTX3:DRP17[8]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_CLK25_DIVIDER" title="GTX3:RX_CLK25_DIVIDER[3]">GTX3:RX_CLK25_DIVIDER[3]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[9]">GTX3:DRP17[9]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_CLK25_DIVIDER" title="GTX3:RX_CLK25_DIVIDER[4]">GTX3:RX_CLK25_DIVIDER[4]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:BIAS_CFG" title="GTX3:BIAS_CFG[16]">GTX3:BIAS_CFG[16]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[10]">GTX3:DRP17[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_CFG" title="GTX3:CHAN_BOND_SEQ_2_CFG[4]">GTX3:CHAN_BOND_SEQ_2_CFG[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[11]">GTX3:DRP17[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[12]">GTX3:DRP17[12]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DATA_WIDTH" title="GTX3:RX_DATA_WIDTH[0]">GTX3:RX_DATA_WIDTH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[13]">GTX3:DRP17[13]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DATA_WIDTH" title="GTX3:RX_DATA_WIDTH[1]">GTX3:RX_DATA_WIDTH[1]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[14]">GTX3:DRP17[14]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DATA_WIDTH" title="GTX3:RX_DATA_WIDTH[2]">GTX3:RX_DATA_WIDTH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP17" title="GTX3:DRP17[15]">GTX3:DRP17[15]</a><br><a href="#bits-xc6v-GTX-GTX3:GEN_RXUSRCLK" title="GTX3:GEN_RXUSRCLK">GTX3:GEN_RXUSRCLK</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 33</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[0]">GTX3:DRP18[0]</a><br><a href="#bits-xc6v-GTX-GTX3:GEARBOX_ENDEC" title="GTX3:GEARBOX_ENDEC[0]">GTX3:GEARBOX_ENDEC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[1]">GTX3:DRP18[1]</a><br><a href="#bits-xc6v-GTX-GTX3:GEARBOX_ENDEC" title="GTX3:GEARBOX_ENDEC[1]">GTX3:GEARBOX_ENDEC[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[2]">GTX3:DRP18[2]</a><br><a href="#bits-xc6v-GTX-GTX3:GEARBOX_ENDEC" title="GTX3:GEARBOX_ENDEC[2]">GTX3:GEARBOX_ENDEC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[3]">GTX3:DRP18[3]</a><br><a href="#bits-xc6v-GTX-GTX3:RXGEARBOX_USE" title="GTX3:RXGEARBOX_USE">GTX3:RXGEARBOX_USE</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_RXCDRRESET" title="GTX3:A_RXCDRRESET">GTX3:A_RXCDRRESET</a><br><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[4]">GTX3:DRP18[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_GTXTXRESET" title="GTX3:A_GTXTXRESET">GTX3:A_GTXTXRESET</a><br><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[5]">GTX3:DRP18[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_GTXRXRESET" title="GTX3:A_GTXRXRESET">GTX3:A_GTXRXRESET</a><br><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[6]">GTX3:DRP18[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_RXBUFRESET" title="GTX3:A_RXBUFRESET">GTX3:A_RXBUFRESET</a><br><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[7]">GTX3:DRP18[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_RXRESET" title="GTX3:A_RXRESET">GTX3:A_RXRESET</a><br><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[8]">GTX3:DRP18[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXRESET" title="GTX3:A_TXRESET">GTX3:A_TXRESET</a><br><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[9]">GTX3:DRP18[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_RXCDRHOLD" title="GTX3:A_RXCDRHOLD">GTX3:A_RXCDRHOLD</a><br><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[10]">GTX3:DRP18[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_RXCDRFREQRESET" title="GTX3:A_RXCDRFREQRESET">GTX3:A_RXCDRFREQRESET</a><br><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[11]">GTX3:DRP18[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_RXCDRPHASERESET" title="GTX3:A_RXCDRPHASERESET">GTX3:A_RXCDRPHASERESET</a><br><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[12]">GTX3:DRP18[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_RXDFERESET" title="GTX3:A_RXDFERESET">GTX3:A_RXDFERESET</a><br><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[13]">GTX3:DRP18[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[14]">GTX3:DRP18[14]</a><br><a href="#bits-xc6v-GTX-GTX3:RESET_DRP_EN" title="GTX3:RESET_DRP_EN">GTX3:RESET_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP18" title="GTX3:DRP18[15]">GTX3:DRP18[15]</a><br><a href="#bits-xc6v-GTX-GTX3:MASTER_DRP_EN" title="GTX3:MASTER_DRP_EN">GTX3:MASTER_DRP_EN</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[0]">GTX3:DRP19[0]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[0]">GTX3:RXPLL_COM_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[1]">GTX3:DRP19[1]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[1]">GTX3:RXPLL_COM_CFG[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[2]">GTX3:DRP19[2]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[2]">GTX3:RXPLL_COM_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[3]">GTX3:DRP19[3]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[3]">GTX3:RXPLL_COM_CFG[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[4]">GTX3:DRP19[4]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[4]">GTX3:RXPLL_COM_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[5]">GTX3:DRP19[5]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[5]">GTX3:RXPLL_COM_CFG[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[6]">GTX3:DRP19[6]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[6]">GTX3:RXPLL_COM_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[7]">GTX3:DRP19[7]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[7]">GTX3:RXPLL_COM_CFG[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[8]">GTX3:DRP19[8]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[8]">GTX3:RXPLL_COM_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[9]">GTX3:DRP19[9]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[9]">GTX3:RXPLL_COM_CFG[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[10]">GTX3:DRP19[10]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[10]">GTX3:RXPLL_COM_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[11]">GTX3:DRP19[11]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[11]">GTX3:RXPLL_COM_CFG[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[12]">GTX3:DRP19[12]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[12]">GTX3:RXPLL_COM_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[13]">GTX3:DRP19[13]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[13]">GTX3:RXPLL_COM_CFG[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[14]">GTX3:DRP19[14]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[14]">GTX3:RXPLL_COM_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP19" title="GTX3:DRP19[15]">GTX3:DRP19[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[15]">GTX3:RXPLL_COM_CFG[15]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[0]">GTX3:DRP1A[0]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[16]">GTX3:RXPLL_COM_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[1]">GTX3:DRP1A[1]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[17]">GTX3:RXPLL_COM_CFG[17]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[2]">GTX3:DRP1A[2]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[18]">GTX3:RXPLL_COM_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[3]">GTX3:DRP1A[3]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[19]">GTX3:RXPLL_COM_CFG[19]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[4]">GTX3:DRP1A[4]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[20]">GTX3:RXPLL_COM_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[5]">GTX3:DRP1A[5]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[21]">GTX3:RXPLL_COM_CFG[21]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[6]">GTX3:DRP1A[6]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[22]">GTX3:RXPLL_COM_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[7]">GTX3:DRP1A[7]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_COM_CFG" title="GTX3:RXPLL_COM_CFG[23]">GTX3:RXPLL_COM_CFG[23]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[8]">GTX3:DRP1A[8]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_CP_CFG" title="GTX3:RXPLL_CP_CFG[0]">GTX3:RXPLL_CP_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[9]">GTX3:DRP1A[9]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_CP_CFG" title="GTX3:RXPLL_CP_CFG[1]">GTX3:RXPLL_CP_CFG[1]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[10]">GTX3:DRP1A[10]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_CP_CFG" title="GTX3:RXPLL_CP_CFG[2]">GTX3:RXPLL_CP_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[11]">GTX3:DRP1A[11]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_CP_CFG" title="GTX3:RXPLL_CP_CFG[3]">GTX3:RXPLL_CP_CFG[3]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[12]">GTX3:DRP1A[12]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_CP_CFG" title="GTX3:RXPLL_CP_CFG[4]">GTX3:RXPLL_CP_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[13]">GTX3:DRP1A[13]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_CP_CFG" title="GTX3:RXPLL_CP_CFG[5]">GTX3:RXPLL_CP_CFG[5]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[14]">GTX3:DRP1A[14]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_CP_CFG" title="GTX3:RXPLL_CP_CFG[6]">GTX3:RXPLL_CP_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1A" title="GTX3:DRP1A[15]">GTX3:DRP1A[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_CP_CFG" title="GTX3:RXPLL_CP_CFG[7]">GTX3:RXPLL_CP_CFG[7]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[0]">GTX3:DRP1B[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[1]">GTX3:DRP1B[1]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_DIVSEL_FB" title="GTX3:RXPLL_DIVSEL_FB[1]">GTX3:RXPLL_DIVSEL_FB[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[2]">GTX3:DRP1B[2]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_DIVSEL_FB" title="GTX3:RXPLL_DIVSEL_FB[2]">GTX3:RXPLL_DIVSEL_FB[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[3]">GTX3:DRP1B[3]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_DIVSEL_FB" title="GTX3:RXPLL_DIVSEL_FB[3]">GTX3:RXPLL_DIVSEL_FB[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[4]">GTX3:DRP1B[4]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_DIVSEL_FB" title="GTX3:RXPLL_DIVSEL_FB[4]">GTX3:RXPLL_DIVSEL_FB[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[5]">GTX3:DRP1B[5]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_DIVSEL_FB" title="GTX3:RXPLL_DIVSEL_FB[0]">GTX3:RXPLL_DIVSEL_FB[0]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[6]">GTX3:DRP1B[6]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_DIVSEL45_FB" title="GTX3:RXPLL_DIVSEL45_FB">GTX3:RXPLL_DIVSEL45_FB</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[7]">GTX3:DRP1B[7]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_STARTUP_EN" title="GTX3:RXPLL_STARTUP_EN">GTX3:RXPLL_STARTUP_EN</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[8]">GTX3:DRP1B[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_RXPOWERDOWN" title="GTX3:A_RXPOWERDOWN[0]">GTX3:A_RXPOWERDOWN[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[9]">GTX3:DRP1B[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_RXPOWERDOWN" title="GTX3:A_RXPOWERDOWN[1]">GTX3:A_RXPOWERDOWN[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[10]">GTX3:DRP1B[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[11]">GTX3:DRP1B[11]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_LKDET_CFG" title="GTX3:RXPLL_LKDET_CFG[0]">GTX3:RXPLL_LKDET_CFG[0]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[12]">GTX3:DRP1B[12]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_LKDET_CFG" title="GTX3:RXPLL_LKDET_CFG[1]">GTX3:RXPLL_LKDET_CFG[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[13]">GTX3:DRP1B[13]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_LKDET_CFG" title="GTX3:RXPLL_LKDET_CFG[2]">GTX3:RXPLL_LKDET_CFG[2]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[14]">GTX3:DRP1B[14]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_DIVSEL_OUT" title="GTX3:RXPLL_DIVSEL_OUT[0]">GTX3:RXPLL_DIVSEL_OUT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1B" title="GTX3:DRP1B[15]">GTX3:DRP1B[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_DIVSEL_OUT" title="GTX3:RXPLL_DIVSEL_OUT[1]">GTX3:RXPLL_DIVSEL_OUT[1]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[0]">GTX3:DRP1C[0]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLLREFSEL_TESTCLK" title="GTX3:RXPLLREFSEL_TESTCLK">GTX3:RXPLLREFSEL_TESTCLK</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[1]">GTX3:DRP1C[1]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_DIVSEL_REF" title="GTX3:RXPLL_DIVSEL_REF[1]">GTX3:RXPLL_DIVSEL_REF[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[2]">GTX3:DRP1C[2]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_DIVSEL_REF" title="GTX3:RXPLL_DIVSEL_REF[2]">GTX3:RXPLL_DIVSEL_REF[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[3]">GTX3:DRP1C[3]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_DIVSEL_REF" title="GTX3:RXPLL_DIVSEL_REF[3]">GTX3:RXPLL_DIVSEL_REF[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[4]">GTX3:DRP1C[4]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_DIVSEL_REF" title="GTX3:RXPLL_DIVSEL_REF[4]">GTX3:RXPLL_DIVSEL_REF[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[5]">GTX3:DRP1C[5]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLL_DIVSEL_REF" title="GTX3:RXPLL_DIVSEL_REF[0]">GTX3:RXPLL_DIVSEL_REF[0]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[6]">GTX3:DRP1C[6]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLLREFSEL_MODE" title="GTX3:RXPLLREFSEL_MODE">GTX3:RXPLLREFSEL_MODE</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[7]">GTX3:DRP1C[7]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLLREFSEL_STATIC" title="GTX3:RXPLLREFSEL_STATIC[0]">GTX3:RXPLLREFSEL_STATIC[0]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[8]">GTX3:DRP1C[8]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLLREFSEL_STATIC" title="GTX3:RXPLLREFSEL_STATIC[1]">GTX3:RXPLLREFSEL_STATIC[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[9]">GTX3:DRP1C[9]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPLLREFSEL_STATIC" title="GTX3:RXPLLREFSEL_STATIC[2]">GTX3:RXPLLREFSEL_STATIC[2]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_PLLRXRESET" title="GTX3:A_PLLRXRESET">GTX3:A_PLLRXRESET</a><br><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[10]">GTX3:DRP1C[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_RXPLLLKDETEN" title="GTX3:A_RXPLLLKDETEN">GTX3:A_RXPLLLKDETEN</a><br><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[11]">GTX3:DRP1C[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_PLLCLKRXRESET" title="GTX3:A_PLLCLKRXRESET">GTX3:A_PLLCLKRXRESET</a><br><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[12]">GTX3:DRP1C[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[13]">GTX3:DRP1C[13]</a><br><a href="#bits-xc6v-GTX-GTX3:PLL_DRP_EN" title="GTX3:PLL_DRP_EN">GTX3:PLL_DRP_EN</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_RXPLLPOWERDOWN" title="GTX3:A_RXPLLPOWERDOWN">GTX3:A_RXPLLPOWERDOWN</a><br><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[14]">GTX3:DRP1C[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1C" title="GTX3:DRP1C[15]">GTX3:DRP1C[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_OVERSAMPLE_MODE" title="GTX3:RX_OVERSAMPLE_MODE">GTX3:RX_OVERSAMPLE_MODE</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[0]">GTX3:DRP1D[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[0]">GTX3:TXPLL_COM_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[1]">GTX3:DRP1D[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[1]">GTX3:TXPLL_COM_CFG[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[2]">GTX3:DRP1D[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[2]">GTX3:TXPLL_COM_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[3]">GTX3:DRP1D[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[3]">GTX3:TXPLL_COM_CFG[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[4]">GTX3:DRP1D[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[4]">GTX3:TXPLL_COM_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[5]">GTX3:DRP1D[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[5]">GTX3:TXPLL_COM_CFG[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[6]">GTX3:DRP1D[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[6]">GTX3:TXPLL_COM_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[7]">GTX3:DRP1D[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[7]">GTX3:TXPLL_COM_CFG[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[8]">GTX3:DRP1D[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[8]">GTX3:TXPLL_COM_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[9]">GTX3:DRP1D[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[9]">GTX3:TXPLL_COM_CFG[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[10]">GTX3:DRP1D[10]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[10]">GTX3:TXPLL_COM_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[11]">GTX3:DRP1D[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[11]">GTX3:TXPLL_COM_CFG[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[12]">GTX3:DRP1D[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[12]">GTX3:TXPLL_COM_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[13]">GTX3:DRP1D[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[13]">GTX3:TXPLL_COM_CFG[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[14]">GTX3:DRP1D[14]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[14]">GTX3:TXPLL_COM_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1D" title="GTX3:DRP1D[15]">GTX3:DRP1D[15]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[15]">GTX3:TXPLL_COM_CFG[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[0]">GTX3:DRP1E[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[16]">GTX3:TXPLL_COM_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[1]">GTX3:DRP1E[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[17]">GTX3:TXPLL_COM_CFG[17]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[2]">GTX3:DRP1E[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[18]">GTX3:TXPLL_COM_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[3]">GTX3:DRP1E[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[19]">GTX3:TXPLL_COM_CFG[19]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[4]">GTX3:DRP1E[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[20]">GTX3:TXPLL_COM_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[5]">GTX3:DRP1E[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[21]">GTX3:TXPLL_COM_CFG[21]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[6]">GTX3:DRP1E[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[22]">GTX3:TXPLL_COM_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[7]">GTX3:DRP1E[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_COM_CFG" title="GTX3:TXPLL_COM_CFG[23]">GTX3:TXPLL_COM_CFG[23]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[8]">GTX3:DRP1E[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_CP_CFG" title="GTX3:TXPLL_CP_CFG[0]">GTX3:TXPLL_CP_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[9]">GTX3:DRP1E[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_CP_CFG" title="GTX3:TXPLL_CP_CFG[1]">GTX3:TXPLL_CP_CFG[1]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[10]">GTX3:DRP1E[10]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_CP_CFG" title="GTX3:TXPLL_CP_CFG[2]">GTX3:TXPLL_CP_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[11]">GTX3:DRP1E[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_CP_CFG" title="GTX3:TXPLL_CP_CFG[3]">GTX3:TXPLL_CP_CFG[3]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[12]">GTX3:DRP1E[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_CP_CFG" title="GTX3:TXPLL_CP_CFG[4]">GTX3:TXPLL_CP_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[13]">GTX3:DRP1E[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_CP_CFG" title="GTX3:TXPLL_CP_CFG[5]">GTX3:TXPLL_CP_CFG[5]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[14]">GTX3:DRP1E[14]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_CP_CFG" title="GTX3:TXPLL_CP_CFG[6]">GTX3:TXPLL_CP_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1E" title="GTX3:DRP1E[15]">GTX3:DRP1E[15]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_CP_CFG" title="GTX3:TXPLL_CP_CFG[7]">GTX3:TXPLL_CP_CFG[7]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[0]">GTX3:DRP1F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[1]">GTX3:DRP1F[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_DIVSEL_FB" title="GTX3:TXPLL_DIVSEL_FB[1]">GTX3:TXPLL_DIVSEL_FB[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[2]">GTX3:DRP1F[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_DIVSEL_FB" title="GTX3:TXPLL_DIVSEL_FB[2]">GTX3:TXPLL_DIVSEL_FB[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[3]">GTX3:DRP1F[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_DIVSEL_FB" title="GTX3:TXPLL_DIVSEL_FB[3]">GTX3:TXPLL_DIVSEL_FB[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[4]">GTX3:DRP1F[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_DIVSEL_FB" title="GTX3:TXPLL_DIVSEL_FB[4]">GTX3:TXPLL_DIVSEL_FB[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[5]">GTX3:DRP1F[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_DIVSEL_FB" title="GTX3:TXPLL_DIVSEL_FB[0]">GTX3:TXPLL_DIVSEL_FB[0]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[6]">GTX3:DRP1F[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_DIVSEL45_FB" title="GTX3:TXPLL_DIVSEL45_FB">GTX3:TXPLL_DIVSEL45_FB</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[7]">GTX3:DRP1F[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_STARTUP_EN" title="GTX3:TXPLL_STARTUP_EN">GTX3:TXPLL_STARTUP_EN</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[8]">GTX3:DRP1F[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_CLK_SOURCE" title="GTX3:TX_CLK_SOURCE">GTX3:TX_CLK_SOURCE</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPOWERDOWN" title="GTX3:A_TXPOWERDOWN[0]">GTX3:A_TXPOWERDOWN[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[9]">GTX3:DRP1F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPOWERDOWN" title="GTX3:A_TXPOWERDOWN[1]">GTX3:A_TXPOWERDOWN[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[10]">GTX3:DRP1F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[11]">GTX3:DRP1F[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_LKDET_CFG" title="GTX3:TXPLL_LKDET_CFG[0]">GTX3:TXPLL_LKDET_CFG[0]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[12]">GTX3:DRP1F[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_LKDET_CFG" title="GTX3:TXPLL_LKDET_CFG[1]">GTX3:TXPLL_LKDET_CFG[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[13]">GTX3:DRP1F[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_LKDET_CFG" title="GTX3:TXPLL_LKDET_CFG[2]">GTX3:TXPLL_LKDET_CFG[2]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[14]">GTX3:DRP1F[14]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_DIVSEL_OUT" title="GTX3:TXPLL_DIVSEL_OUT[0]">GTX3:TXPLL_DIVSEL_OUT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP1F" title="GTX3:DRP1F[15]">GTX3:DRP1F[15]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_DIVSEL_OUT" title="GTX3:TXPLL_DIVSEL_OUT[1]">GTX3:TXPLL_DIVSEL_OUT[1]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 34</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[0]">GTX3:DRP20[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLLREFSEL_TESTCLK" title="GTX3:TXPLLREFSEL_TESTCLK">GTX3:TXPLLREFSEL_TESTCLK</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[1]">GTX3:DRP20[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_DIVSEL_REF" title="GTX3:TXPLL_DIVSEL_REF[1]">GTX3:TXPLL_DIVSEL_REF[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[2]">GTX3:DRP20[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_DIVSEL_REF" title="GTX3:TXPLL_DIVSEL_REF[2]">GTX3:TXPLL_DIVSEL_REF[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[3]">GTX3:DRP20[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_DIVSEL_REF" title="GTX3:TXPLL_DIVSEL_REF[3]">GTX3:TXPLL_DIVSEL_REF[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[4]">GTX3:DRP20[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_DIVSEL_REF" title="GTX3:TXPLL_DIVSEL_REF[4]">GTX3:TXPLL_DIVSEL_REF[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[5]">GTX3:DRP20[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_DIVSEL_REF" title="GTX3:TXPLL_DIVSEL_REF[0]">GTX3:TXPLL_DIVSEL_REF[0]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[6]">GTX3:DRP20[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLLREFSEL_MODE" title="GTX3:TXPLLREFSEL_MODE">GTX3:TXPLLREFSEL_MODE</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[7]">GTX3:DRP20[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLLREFSEL_STATIC" title="GTX3:TXPLLREFSEL_STATIC[0]">GTX3:TXPLLREFSEL_STATIC[0]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[8]">GTX3:DRP20[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLLREFSEL_STATIC" title="GTX3:TXPLLREFSEL_STATIC[1]">GTX3:TXPLLREFSEL_STATIC[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[9]">GTX3:DRP20[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLLREFSEL_STATIC" title="GTX3:TXPLLREFSEL_STATIC[2]">GTX3:TXPLLREFSEL_STATIC[2]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_PLLTXRESET" title="GTX3:A_PLLTXRESET">GTX3:A_PLLTXRESET</a><br><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[10]">GTX3:DRP20[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPLLLKDETEN" title="GTX3:A_TXPLLLKDETEN">GTX3:A_TXPLLLKDETEN</a><br><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[11]">GTX3:DRP20[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_PLLCLKTXRESET" title="GTX3:A_PLLCLKTXRESET">GTX3:A_PLLCLKTXRESET</a><br><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[12]">GTX3:DRP20[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[13]">GTX3:DRP20[13]</a><br><a href="#bits-xc6v-GTX-GTX3:PDELIDLE_DRP_EN" title="GTX3:PDELIDLE_DRP_EN">GTX3:PDELIDLE_DRP_EN</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPLLPOWERDOWN" title="GTX3:A_TXPLLPOWERDOWN">GTX3:A_TXPLLPOWERDOWN</a><br><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[14]">GTX3:DRP20[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP20" title="GTX3:DRP20[15]">GTX3:DRP20[15]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_OVERSAMPLE_MODE" title="GTX3:TX_OVERSAMPLE_MODE">GTX3:TX_OVERSAMPLE_MODE</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[0]">GTX3:DRP21[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DETECT_RX_CFG" title="GTX3:TX_DETECT_RX_CFG[0]">GTX3:TX_DETECT_RX_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[1]">GTX3:DRP21[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DETECT_RX_CFG" title="GTX3:TX_DETECT_RX_CFG[1]">GTX3:TX_DETECT_RX_CFG[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[2]">GTX3:DRP21[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DETECT_RX_CFG" title="GTX3:TX_DETECT_RX_CFG[2]">GTX3:TX_DETECT_RX_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[3]">GTX3:DRP21[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DETECT_RX_CFG" title="GTX3:TX_DETECT_RX_CFG[3]">GTX3:TX_DETECT_RX_CFG[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[4]">GTX3:DRP21[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DETECT_RX_CFG" title="GTX3:TX_DETECT_RX_CFG[4]">GTX3:TX_DETECT_RX_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[5]">GTX3:DRP21[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DETECT_RX_CFG" title="GTX3:TX_DETECT_RX_CFG[5]">GTX3:TX_DETECT_RX_CFG[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[6]">GTX3:DRP21[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DETECT_RX_CFG" title="GTX3:TX_DETECT_RX_CFG[6]">GTX3:TX_DETECT_RX_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[7]">GTX3:DRP21[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DETECT_RX_CFG" title="GTX3:TX_DETECT_RX_CFG[7]">GTX3:TX_DETECT_RX_CFG[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[8]">GTX3:DRP21[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DETECT_RX_CFG" title="GTX3:TX_DETECT_RX_CFG[8]">GTX3:TX_DETECT_RX_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[9]">GTX3:DRP21[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DETECT_RX_CFG" title="GTX3:TX_DETECT_RX_CFG[9]">GTX3:TX_DETECT_RX_CFG[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[10]">GTX3:DRP21[10]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DETECT_RX_CFG" title="GTX3:TX_DETECT_RX_CFG[10]">GTX3:TX_DETECT_RX_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[11]">GTX3:DRP21[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DETECT_RX_CFG" title="GTX3:TX_DETECT_RX_CFG[11]">GTX3:TX_DETECT_RX_CFG[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[12]">GTX3:DRP21[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DETECT_RX_CFG" title="GTX3:TX_DETECT_RX_CFG[12]">GTX3:TX_DETECT_RX_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[13]">GTX3:DRP21[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DETECT_RX_CFG" title="GTX3:TX_DETECT_RX_CFG[13]">GTX3:TX_DETECT_RX_CFG[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXELECIDLE" title="GTX3:A_TXELECIDLE">GTX3:A_TXELECIDLE</a><br><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[14]">GTX3:DRP21[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP21" title="GTX3:DRP21[15]">GTX3:DRP21[15]</a><br><a href="#bits-xc6v-GTX-GTX3:PCI_EXPRESS_MODE" title="GTX3:PCI_EXPRESS_MODE">GTX3:PCI_EXPRESS_MODE</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[0]">GTX3:DRP22[0]</a><br><a href="#bits-xc6v-GTX-HCLK_GTX:MUX.NORTHREFCLKOUT0" title="HCLK_GTX:MUX.NORTHREFCLKOUT0[0]">HCLK_GTX:MUX.NORTHREFCLKOUT0[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[1]">GTX3:DRP22[1]</a><br><a href="#bits-xc6v-GTX-HCLK_GTX:MUX.NORTHREFCLKOUT0" title="HCLK_GTX:MUX.NORTHREFCLKOUT0[1]">HCLK_GTX:MUX.NORTHREFCLKOUT0[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[2]">GTX3:DRP22[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[3]">GTX3:DRP22[3]</a><br><a href="#bits-xc6v-GTX-HCLK_GTX:MUX.NORTHREFCLKOUT1" title="HCLK_GTX:MUX.NORTHREFCLKOUT1[0]">HCLK_GTX:MUX.NORTHREFCLKOUT1[0]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[4]">GTX3:DRP22[4]</a><br><a href="#bits-xc6v-GTX-HCLK_GTX:MUX.NORTHREFCLKOUT1" title="HCLK_GTX:MUX.NORTHREFCLKOUT1[1]">HCLK_GTX:MUX.NORTHREFCLKOUT1[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[5]">GTX3:DRP22[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[6]">GTX3:DRP22[6]</a><br><a href="#bits-xc6v-GTX-HCLK_GTX:MUX.SOUTHREFCLKOUT0" title="HCLK_GTX:MUX.SOUTHREFCLKOUT0[0]">HCLK_GTX:MUX.SOUTHREFCLKOUT0[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[7]">GTX3:DRP22[7]</a><br><a href="#bits-xc6v-GTX-HCLK_GTX:MUX.SOUTHREFCLKOUT0" title="HCLK_GTX:MUX.SOUTHREFCLKOUT0[1]">HCLK_GTX:MUX.SOUTHREFCLKOUT0[1]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[8]">GTX3:DRP22[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[9]">GTX3:DRP22[9]</a><br><a href="#bits-xc6v-GTX-HCLK_GTX:MUX.SOUTHREFCLKOUT1" title="HCLK_GTX:MUX.SOUTHREFCLKOUT1[0]">HCLK_GTX:MUX.SOUTHREFCLKOUT1[0]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[10]">GTX3:DRP22[10]</a><br><a href="#bits-xc6v-GTX-HCLK_GTX:MUX.SOUTHREFCLKOUT1" title="HCLK_GTX:MUX.SOUTHREFCLKOUT1[1]">HCLK_GTX:MUX.SOUTHREFCLKOUT1[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[11]">GTX3:DRP22[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[12]">GTX3:DRP22[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[13]">GTX3:DRP22[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[14]">GTX3:DRP22[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP22" title="GTX3:DRP22[15]">GTX3:DRP22[15]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CAS_CLK_EN" title="GTX3:PMA_CAS_CLK_EN">GTX3:PMA_CAS_CLK_EN</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[0]">GTX3:DRP23[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_TO_P2" title="GTX3:TRANS_TIME_TO_P2[0]">GTX3:TRANS_TIME_TO_P2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[1]">GTX3:DRP23[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_TO_P2" title="GTX3:TRANS_TIME_TO_P2[1]">GTX3:TRANS_TIME_TO_P2[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[2]">GTX3:DRP23[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_TO_P2" title="GTX3:TRANS_TIME_TO_P2[2]">GTX3:TRANS_TIME_TO_P2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[3]">GTX3:DRP23[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_TO_P2" title="GTX3:TRANS_TIME_TO_P2[3]">GTX3:TRANS_TIME_TO_P2[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[4]">GTX3:DRP23[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_TO_P2" title="GTX3:TRANS_TIME_TO_P2[4]">GTX3:TRANS_TIME_TO_P2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[5]">GTX3:DRP23[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_TO_P2" title="GTX3:TRANS_TIME_TO_P2[5]">GTX3:TRANS_TIME_TO_P2[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[6]">GTX3:DRP23[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_TO_P2" title="GTX3:TRANS_TIME_TO_P2[6]">GTX3:TRANS_TIME_TO_P2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[7]">GTX3:DRP23[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_TO_P2" title="GTX3:TRANS_TIME_TO_P2[7]">GTX3:TRANS_TIME_TO_P2[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[8]">GTX3:DRP23[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_TO_P2" title="GTX3:TRANS_TIME_TO_P2[8]">GTX3:TRANS_TIME_TO_P2[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[9]">GTX3:DRP23[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_TO_P2" title="GTX3:TRANS_TIME_TO_P2[9]">GTX3:TRANS_TIME_TO_P2[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[10]">GTX3:DRP23[10]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_CLK25_DIVIDER" title="GTX3:TX_CLK25_DIVIDER[0]">GTX3:TX_CLK25_DIVIDER[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[11]">GTX3:DRP23[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_CLK25_DIVIDER" title="GTX3:TX_CLK25_DIVIDER[1]">GTX3:TX_CLK25_DIVIDER[1]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[12]">GTX3:DRP23[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_CLK25_DIVIDER" title="GTX3:TX_CLK25_DIVIDER[2]">GTX3:TX_CLK25_DIVIDER[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[13]">GTX3:DRP23[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_CLK25_DIVIDER" title="GTX3:TX_CLK25_DIVIDER[3]">GTX3:TX_CLK25_DIVIDER[3]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[14]">GTX3:DRP23[14]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_CLK25_DIVIDER" title="GTX3:TX_CLK25_DIVIDER[4]">GTX3:TX_CLK25_DIVIDER[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP23" title="GTX3:DRP23[15]">GTX3:DRP23[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[0]">GTX3:DRP24[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_FROM_P2" title="GTX3:TRANS_TIME_FROM_P2[0]">GTX3:TRANS_TIME_FROM_P2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[1]">GTX3:DRP24[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_FROM_P2" title="GTX3:TRANS_TIME_FROM_P2[1]">GTX3:TRANS_TIME_FROM_P2[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[2]">GTX3:DRP24[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_FROM_P2" title="GTX3:TRANS_TIME_FROM_P2[2]">GTX3:TRANS_TIME_FROM_P2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[3]">GTX3:DRP24[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_FROM_P2" title="GTX3:TRANS_TIME_FROM_P2[3]">GTX3:TRANS_TIME_FROM_P2[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[4]">GTX3:DRP24[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_FROM_P2" title="GTX3:TRANS_TIME_FROM_P2[4]">GTX3:TRANS_TIME_FROM_P2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[5]">GTX3:DRP24[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_FROM_P2" title="GTX3:TRANS_TIME_FROM_P2[5]">GTX3:TRANS_TIME_FROM_P2[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[6]">GTX3:DRP24[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_FROM_P2" title="GTX3:TRANS_TIME_FROM_P2[6]">GTX3:TRANS_TIME_FROM_P2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[7]">GTX3:DRP24[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_FROM_P2" title="GTX3:TRANS_TIME_FROM_P2[7]">GTX3:TRANS_TIME_FROM_P2[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[8]">GTX3:DRP24[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_FROM_P2" title="GTX3:TRANS_TIME_FROM_P2[8]">GTX3:TRANS_TIME_FROM_P2[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[9]">GTX3:DRP24[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_FROM_P2" title="GTX3:TRANS_TIME_FROM_P2[9]">GTX3:TRANS_TIME_FROM_P2[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[10]">GTX3:DRP24[10]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_FROM_P2" title="GTX3:TRANS_TIME_FROM_P2[10]">GTX3:TRANS_TIME_FROM_P2[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[11]">GTX3:DRP24[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_FROM_P2" title="GTX3:TRANS_TIME_FROM_P2[11]">GTX3:TRANS_TIME_FROM_P2[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:COM_BURST_VAL" title="GTX3:COM_BURST_VAL[0]">GTX3:COM_BURST_VAL[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[12]">GTX3:DRP24[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:COM_BURST_VAL" title="GTX3:COM_BURST_VAL[1]">GTX3:COM_BURST_VAL[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[13]">GTX3:DRP24[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:COM_BURST_VAL" title="GTX3:COM_BURST_VAL[2]">GTX3:COM_BURST_VAL[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[14]">GTX3:DRP24[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:COM_BURST_VAL" title="GTX3:COM_BURST_VAL[3]">GTX3:COM_BURST_VAL[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP24" title="GTX3:DRP24[15]">GTX3:DRP24[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[0]">GTX3:DRP25[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_NON_P2" title="GTX3:TRANS_TIME_NON_P2[0]">GTX3:TRANS_TIME_NON_P2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[1]">GTX3:DRP25[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_NON_P2" title="GTX3:TRANS_TIME_NON_P2[1]">GTX3:TRANS_TIME_NON_P2[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[2]">GTX3:DRP25[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_NON_P2" title="GTX3:TRANS_TIME_NON_P2[2]">GTX3:TRANS_TIME_NON_P2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[3]">GTX3:DRP25[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_NON_P2" title="GTX3:TRANS_TIME_NON_P2[3]">GTX3:TRANS_TIME_NON_P2[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[4]">GTX3:DRP25[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_NON_P2" title="GTX3:TRANS_TIME_NON_P2[4]">GTX3:TRANS_TIME_NON_P2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[5]">GTX3:DRP25[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_NON_P2" title="GTX3:TRANS_TIME_NON_P2[5]">GTX3:TRANS_TIME_NON_P2[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[6]">GTX3:DRP25[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_NON_P2" title="GTX3:TRANS_TIME_NON_P2[6]">GTX3:TRANS_TIME_NON_P2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[7]">GTX3:DRP25[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_NON_P2" title="GTX3:TRANS_TIME_NON_P2[7]">GTX3:TRANS_TIME_NON_P2[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:CM_TRIM" title="GTX3:CM_TRIM[0]">GTX3:CM_TRIM[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[8]">GTX3:DRP25[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:CM_TRIM" title="GTX3:CM_TRIM[1]">GTX3:CM_TRIM[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[9]">GTX3:DRP25[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_RXPOLARITY" title="GTX3:A_RXPOLARITY">GTX3:A_RXPOLARITY</a><br><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[10]">GTX3:DRP25[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPOLARITY" title="GTX3:A_TXPOLARITY">GTX3:A_TXPOLARITY</a><br><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[11]">GTX3:DRP25[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[12]">GTX3:DRP25[12]</a><br><a href="#bits-xc6v-GTX-GTX3:POLARITY_DRP_EN" title="GTX3:POLARITY_DRP_EN">GTX3:POLARITY_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_RXPMASETPHASE" title="GTX3:A_RXPMASETPHASE">GTX3:A_RXPMASETPHASE</a><br><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[13]">GTX3:DRP25[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_RXENPMAPHASEALIGN" title="GTX3:A_RXENPMAPHASEALIGN">GTX3:A_RXENPMAPHASEALIGN</a><br><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[14]">GTX3:DRP25[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP25" title="GTX3:DRP25[15]">GTX3:DRP25[15]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_PMADATA_OPT" title="GTX3:TX_PMADATA_OPT">GTX3:TX_PMADATA_OPT</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[0]">GTX3:DRP26[0]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_WAKE" title="GTX3:SATA_MAX_WAKE[0]">GTX3:SATA_MAX_WAKE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[1]">GTX3:DRP26[1]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_WAKE" title="GTX3:SATA_MAX_WAKE[1]">GTX3:SATA_MAX_WAKE[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[2]">GTX3:DRP26[2]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_WAKE" title="GTX3:SATA_MAX_WAKE[2]">GTX3:SATA_MAX_WAKE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[3]">GTX3:DRP26[3]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_WAKE" title="GTX3:SATA_MAX_WAKE[3]">GTX3:SATA_MAX_WAKE[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[4]">GTX3:DRP26[4]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_WAKE" title="GTX3:SATA_MAX_WAKE[4]">GTX3:SATA_MAX_WAKE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[5]">GTX3:DRP26[5]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_WAKE" title="GTX3:SATA_MAX_WAKE[5]">GTX3:SATA_MAX_WAKE[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[6]">GTX3:DRP26[6]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_WAKE" title="GTX3:SATA_MIN_WAKE[0]">GTX3:SATA_MIN_WAKE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[7]">GTX3:DRP26[7]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_WAKE" title="GTX3:SATA_MIN_WAKE[1]">GTX3:SATA_MIN_WAKE[1]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[8]">GTX3:DRP26[8]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_WAKE" title="GTX3:SATA_MIN_WAKE[2]">GTX3:SATA_MIN_WAKE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[9]">GTX3:DRP26[9]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_WAKE" title="GTX3:SATA_MIN_WAKE[3]">GTX3:SATA_MIN_WAKE[3]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[10]">GTX3:DRP26[10]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_WAKE" title="GTX3:SATA_MIN_WAKE[4]">GTX3:SATA_MIN_WAKE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[11]">GTX3:DRP26[11]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_WAKE" title="GTX3:SATA_MIN_WAKE[5]">GTX3:SATA_MIN_WAKE[5]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[12]">GTX3:DRP26[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_SATA" title="GTX3:TXPLL_SATA[0]">GTX3:TXPLL_SATA[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[13]">GTX3:DRP26[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TXPLL_SATA" title="GTX3:TXPLL_SATA[1]">GTX3:TXPLL_SATA[1]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:BGTEST_CFG" title="GTX3:BGTEST_CFG[0]">GTX3:BGTEST_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[14]">GTX3:DRP26[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:BGTEST_CFG" title="GTX3:BGTEST_CFG[1]">GTX3:BGTEST_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP26" title="GTX3:DRP26[15]">GTX3:DRP26[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[0]">GTX3:DRP27[0]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_INIT" title="GTX3:SATA_MAX_INIT[0]">GTX3:SATA_MAX_INIT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[1]">GTX3:DRP27[1]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_INIT" title="GTX3:SATA_MAX_INIT[1]">GTX3:SATA_MAX_INIT[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[2]">GTX3:DRP27[2]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_INIT" title="GTX3:SATA_MAX_INIT[2]">GTX3:SATA_MAX_INIT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[3]">GTX3:DRP27[3]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_INIT" title="GTX3:SATA_MAX_INIT[3]">GTX3:SATA_MAX_INIT[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[4]">GTX3:DRP27[4]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_INIT" title="GTX3:SATA_MAX_INIT[4]">GTX3:SATA_MAX_INIT[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[5]">GTX3:DRP27[5]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_INIT" title="GTX3:SATA_MAX_INIT[5]">GTX3:SATA_MAX_INIT[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[6]">GTX3:DRP27[6]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_INIT" title="GTX3:SATA_MIN_INIT[0]">GTX3:SATA_MIN_INIT[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[7]">GTX3:DRP27[7]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_INIT" title="GTX3:SATA_MIN_INIT[1]">GTX3:SATA_MIN_INIT[1]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[8]">GTX3:DRP27[8]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_INIT" title="GTX3:SATA_MIN_INIT[2]">GTX3:SATA_MIN_INIT[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[9]">GTX3:DRP27[9]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_INIT" title="GTX3:SATA_MIN_INIT[3]">GTX3:SATA_MIN_INIT[3]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[10]">GTX3:DRP27[10]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_INIT" title="GTX3:SATA_MIN_INIT[4]">GTX3:SATA_MIN_INIT[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[11]">GTX3:DRP27[11]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_INIT" title="GTX3:SATA_MIN_INIT[5]">GTX3:SATA_MIN_INIT[5]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[12]">GTX3:DRP27[12]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_IDLE_VAL" title="GTX3:SATA_IDLE_VAL[0]">GTX3:SATA_IDLE_VAL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[13]">GTX3:DRP27[13]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_IDLE_VAL" title="GTX3:SATA_IDLE_VAL[1]">GTX3:SATA_IDLE_VAL[1]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[14]">GTX3:DRP27[14]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_IDLE_VAL" title="GTX3:SATA_IDLE_VAL[2]">GTX3:SATA_IDLE_VAL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP27" title="GTX3:DRP27[15]">GTX3:DRP27[15]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_EN_RATE_RESET_BUF" title="GTX3:TX_EN_RATE_RESET_BUF">GTX3:TX_EN_RATE_RESET_BUF</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 35</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[0]">GTX3:DRP28[0]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_BURST" title="GTX3:SATA_MAX_BURST[0]">GTX3:SATA_MAX_BURST[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[1]">GTX3:DRP28[1]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_BURST" title="GTX3:SATA_MAX_BURST[1]">GTX3:SATA_MAX_BURST[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[2]">GTX3:DRP28[2]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_BURST" title="GTX3:SATA_MAX_BURST[2]">GTX3:SATA_MAX_BURST[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[3]">GTX3:DRP28[3]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_BURST" title="GTX3:SATA_MAX_BURST[3]">GTX3:SATA_MAX_BURST[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[4]">GTX3:DRP28[4]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_BURST" title="GTX3:SATA_MAX_BURST[4]">GTX3:SATA_MAX_BURST[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[5]">GTX3:DRP28[5]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MAX_BURST" title="GTX3:SATA_MAX_BURST[5]">GTX3:SATA_MAX_BURST[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[6]">GTX3:DRP28[6]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_BURST" title="GTX3:SATA_MIN_BURST[0]">GTX3:SATA_MIN_BURST[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[7]">GTX3:DRP28[7]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_BURST" title="GTX3:SATA_MIN_BURST[1]">GTX3:SATA_MIN_BURST[1]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[8]">GTX3:DRP28[8]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_BURST" title="GTX3:SATA_MIN_BURST[2]">GTX3:SATA_MIN_BURST[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[9]">GTX3:DRP28[9]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_BURST" title="GTX3:SATA_MIN_BURST[3]">GTX3:SATA_MIN_BURST[3]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[10]">GTX3:DRP28[10]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_BURST" title="GTX3:SATA_MIN_BURST[4]">GTX3:SATA_MIN_BURST[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[11]">GTX3:DRP28[11]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_MIN_BURST" title="GTX3:SATA_MIN_BURST[5]">GTX3:SATA_MIN_BURST[5]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[12]">GTX3:DRP28[12]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_BURST_VAL" title="GTX3:SATA_BURST_VAL[0]">GTX3:SATA_BURST_VAL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[13]">GTX3:DRP28[13]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_BURST_VAL" title="GTX3:SATA_BURST_VAL[1]">GTX3:SATA_BURST_VAL[1]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[14]">GTX3:DRP28[14]</a><br><a href="#bits-xc6v-GTX-GTX3:SATA_BURST_VAL" title="GTX3:SATA_BURST_VAL[2]">GTX3:SATA_BURST_VAL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP28" title="GTX3:DRP28[15]">GTX3:DRP28[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[0]">GTX3:DRP29[0]</a><br><a href="#bits-xc6v-GTX-GTX3:SAS_MAX_COMSAS" title="GTX3:SAS_MAX_COMSAS[0]">GTX3:SAS_MAX_COMSAS[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[1]">GTX3:DRP29[1]</a><br><a href="#bits-xc6v-GTX-GTX3:SAS_MAX_COMSAS" title="GTX3:SAS_MAX_COMSAS[1]">GTX3:SAS_MAX_COMSAS[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[2]">GTX3:DRP29[2]</a><br><a href="#bits-xc6v-GTX-GTX3:SAS_MAX_COMSAS" title="GTX3:SAS_MAX_COMSAS[2]">GTX3:SAS_MAX_COMSAS[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[3]">GTX3:DRP29[3]</a><br><a href="#bits-xc6v-GTX-GTX3:SAS_MAX_COMSAS" title="GTX3:SAS_MAX_COMSAS[3]">GTX3:SAS_MAX_COMSAS[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[4]">GTX3:DRP29[4]</a><br><a href="#bits-xc6v-GTX-GTX3:SAS_MAX_COMSAS" title="GTX3:SAS_MAX_COMSAS[4]">GTX3:SAS_MAX_COMSAS[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[5]">GTX3:DRP29[5]</a><br><a href="#bits-xc6v-GTX-GTX3:SAS_MAX_COMSAS" title="GTX3:SAS_MAX_COMSAS[5]">GTX3:SAS_MAX_COMSAS[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[6]">GTX3:DRP29[6]</a><br><a href="#bits-xc6v-GTX-GTX3:SAS_MIN_COMSAS" title="GTX3:SAS_MIN_COMSAS[0]">GTX3:SAS_MIN_COMSAS[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[7]">GTX3:DRP29[7]</a><br><a href="#bits-xc6v-GTX-GTX3:SAS_MIN_COMSAS" title="GTX3:SAS_MIN_COMSAS[1]">GTX3:SAS_MIN_COMSAS[1]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[8]">GTX3:DRP29[8]</a><br><a href="#bits-xc6v-GTX-GTX3:SAS_MIN_COMSAS" title="GTX3:SAS_MIN_COMSAS[2]">GTX3:SAS_MIN_COMSAS[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[9]">GTX3:DRP29[9]</a><br><a href="#bits-xc6v-GTX-GTX3:SAS_MIN_COMSAS" title="GTX3:SAS_MIN_COMSAS[3]">GTX3:SAS_MIN_COMSAS[3]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[10]">GTX3:DRP29[10]</a><br><a href="#bits-xc6v-GTX-GTX3:SAS_MIN_COMSAS" title="GTX3:SAS_MIN_COMSAS[4]">GTX3:SAS_MIN_COMSAS[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[11]">GTX3:DRP29[11]</a><br><a href="#bits-xc6v-GTX-GTX3:SAS_MIN_COMSAS" title="GTX3:SAS_MIN_COMSAS[5]">GTX3:SAS_MIN_COMSAS[5]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPMASETPHASE" title="GTX3:A_TXPMASETPHASE">GTX3:A_TXPMASETPHASE</a><br><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[12]">GTX3:DRP29[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXENPMAPHASEALIGN" title="GTX3:A_TXENPMAPHASEALIGN">GTX3:A_TXENPMAPHASEALIGN</a><br><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[13]">GTX3:DRP29[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_RXENSAMPLEALIGN" title="GTX3:A_RXENSAMPLEALIGN">GTX3:A_RXENSAMPLEALIGN</a><br><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[14]">GTX3:DRP29[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP29" title="GTX3:DRP29[15]">GTX3:DRP29[15]</a><br><a href="#bits-xc6v-GTX-GTX3:PHASEALIGN_DRP_EN" title="GTX3:PHASEALIGN_DRP_EN">GTX3:PHASEALIGN_DRP_EN</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[0]">GTX3:DRP2A[0]</a><br><a href="#bits-xc6v-GTX-GTX3:LOOPBACK_DRP_EN" title="GTX3:LOOPBACK_DRP_EN">GTX3:LOOPBACK_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_LOOPBACK" title="GTX3:A_LOOPBACK[0]">GTX3:A_LOOPBACK[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[1]">GTX3:DRP2A[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_LOOPBACK" title="GTX3:A_LOOPBACK[1]">GTX3:A_LOOPBACK[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[2]">GTX3:DRP2A[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_LOOPBACK" title="GTX3:A_LOOPBACK[2]">GTX3:A_LOOPBACK[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[3]">GTX3:DRP2A[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[4]">GTX3:DRP2A[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_RXENPRBSTST" title="GTX3:A_RXENPRBSTST[0]">GTX3:A_RXENPRBSTST[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[5]">GTX3:DRP2A[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_RXENPRBSTST" title="GTX3:A_RXENPRBSTST[1]">GTX3:A_RXENPRBSTST[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[6]">GTX3:DRP2A[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_RXENPRBSTST" title="GTX3:A_RXENPRBSTST[2]">GTX3:A_RXENPRBSTST[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[7]">GTX3:DRP2A[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[8]">GTX3:DRP2A[8]</a><br><a href="#bits-xc6v-GTX-GTX3:RXPRBSERR_LOOPBACK" title="GTX3:RXPRBSERR_LOOPBACK">GTX3:RXPRBSERR_LOOPBACK</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[9]">GTX3:DRP2A[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPRBSFORCEERR" title="GTX3:A_TXPRBSFORCEERR">GTX3:A_TXPRBSFORCEERR</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[10]">GTX3:DRP2A[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXENPRBSTST" title="GTX3:A_TXENPRBSTST[0]">GTX3:A_TXENPRBSTST[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[11]">GTX3:DRP2A[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXENPRBSTST" title="GTX3:A_TXENPRBSTST[1]">GTX3:A_TXENPRBSTST[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[12]">GTX3:DRP2A[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXENPRBSTST" title="GTX3:A_TXENPRBSTST[2]">GTX3:A_TXENPRBSTST[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[13]">GTX3:DRP2A[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_PRBSCNTRESET" title="GTX3:A_PRBSCNTRESET">GTX3:A_PRBSCNTRESET</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[14]">GTX3:DRP2A[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2A" title="GTX3:DRP2A[15]">GTX3:DRP2A[15]</a><br><a href="#bits-xc6v-GTX-GTX3:PRBS_DRP_EN" title="GTX3:PRBS_DRP_EN">GTX3:PRBS_DRP_EN</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP1" title="GTX3:A_DFETAP1[0]">GTX3:A_DFETAP1[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[0]">GTX3:DRP2B[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP1" title="GTX3:A_DFETAP1[1]">GTX3:A_DFETAP1[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[1]">GTX3:DRP2B[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP1" title="GTX3:A_DFETAP1[2]">GTX3:A_DFETAP1[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[2]">GTX3:DRP2B[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP1" title="GTX3:A_DFETAP1[3]">GTX3:A_DFETAP1[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[3]">GTX3:DRP2B[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP1" title="GTX3:A_DFETAP1[4]">GTX3:A_DFETAP1[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[4]">GTX3:DRP2B[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP3" title="GTX3:A_DFETAP3[0]">GTX3:A_DFETAP3[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[5]">GTX3:DRP2B[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP3" title="GTX3:A_DFETAP3[1]">GTX3:A_DFETAP3[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[6]">GTX3:DRP2B[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP3" title="GTX3:A_DFETAP3[2]">GTX3:A_DFETAP3[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[7]">GTX3:DRP2B[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP3" title="GTX3:A_DFETAP3[3]">GTX3:A_DFETAP3[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[8]">GTX3:DRP2B[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[9]">GTX3:DRP2B[9]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EN_IDLE_HOLD_CDR" title="GTX3:RX_EN_IDLE_HOLD_CDR">GTX3:RX_EN_IDLE_HOLD_CDR</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[10]">GTX3:DRP2B[10]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EN_IDLE_RESET_FR" title="GTX3:RX_EN_IDLE_RESET_FR">GTX3:RX_EN_IDLE_RESET_FR</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[11]">GTX3:DRP2B[11]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EN_IDLE_HOLD_DFE" title="GTX3:RX_EN_IDLE_HOLD_DFE">GTX3:RX_EN_IDLE_HOLD_DFE</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[12]">GTX3:DRP2B[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[13]">GTX3:DRP2B[13]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_DFEDLYOVRD" title="GTX3:A_DFEDLYOVRD">GTX3:A_DFEDLYOVRD</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[14]">GTX3:DRP2B[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAPOVRD" title="GTX3:A_DFETAPOVRD">GTX3:A_DFETAPOVRD</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2B" title="GTX3:DRP2B[15]">GTX3:DRP2B[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP2" title="GTX3:A_DFETAP2[0]">GTX3:A_DFETAP2[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[0]">GTX3:DRP2C[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP2" title="GTX3:A_DFETAP2[1]">GTX3:A_DFETAP2[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[1]">GTX3:DRP2C[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP2" title="GTX3:A_DFETAP2[2]">GTX3:A_DFETAP2[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[2]">GTX3:DRP2C[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP2" title="GTX3:A_DFETAP2[3]">GTX3:A_DFETAP2[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[3]">GTX3:DRP2C[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP2" title="GTX3:A_DFETAP2[4]">GTX3:A_DFETAP2[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[4]">GTX3:DRP2C[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP4" title="GTX3:A_DFETAP4[0]">GTX3:A_DFETAP4[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[5]">GTX3:DRP2C[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP4" title="GTX3:A_DFETAP4[1]">GTX3:A_DFETAP4[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[6]">GTX3:DRP2C[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP4" title="GTX3:A_DFETAP4[2]">GTX3:A_DFETAP4[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[7]">GTX3:DRP2C[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_DFETAP4" title="GTX3:A_DFETAP4[3]">GTX3:A_DFETAP4[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[8]">GTX3:DRP2C[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_DFECLKDLYADJ" title="GTX3:A_DFECLKDLYADJ[0]">GTX3:A_DFECLKDLYADJ[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[9]">GTX3:DRP2C[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_DFECLKDLYADJ" title="GTX3:A_DFECLKDLYADJ[1]">GTX3:A_DFECLKDLYADJ[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[10]">GTX3:DRP2C[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_DFECLKDLYADJ" title="GTX3:A_DFECLKDLYADJ[2]">GTX3:A_DFECLKDLYADJ[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[11]">GTX3:DRP2C[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_DFECLKDLYADJ" title="GTX3:A_DFECLKDLYADJ[3]">GTX3:A_DFECLKDLYADJ[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[12]">GTX3:DRP2C[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_DFECLKDLYADJ" title="GTX3:A_DFECLKDLYADJ[4]">GTX3:A_DFECLKDLYADJ[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[13]">GTX3:DRP2C[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_DFECLKDLYADJ" title="GTX3:A_DFECLKDLYADJ[5]">GTX3:A_DFECLKDLYADJ[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[14]">GTX3:DRP2C[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DFE_DRP_EN" title="GTX3:DFE_DRP_EN">GTX3:DFE_DRP_EN</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2C" title="GTX3:DRP2C[15]">GTX3:DRP2C[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DFE_CFG" title="GTX3:DFE_CFG[0]">GTX3:DFE_CFG[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[0]">GTX3:DRP2D[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DFE_CFG" title="GTX3:DFE_CFG[1]">GTX3:DFE_CFG[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[1]">GTX3:DRP2D[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DFE_CFG" title="GTX3:DFE_CFG[2]">GTX3:DFE_CFG[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[2]">GTX3:DRP2D[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DFE_CFG" title="GTX3:DFE_CFG[3]">GTX3:DFE_CFG[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[3]">GTX3:DRP2D[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DFE_CFG" title="GTX3:DFE_CFG[4]">GTX3:DFE_CFG[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[4]">GTX3:DRP2D[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DFE_CFG" title="GTX3:DFE_CFG[5]">GTX3:DFE_CFG[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[5]">GTX3:DRP2D[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DFE_CFG" title="GTX3:DFE_CFG[6]">GTX3:DFE_CFG[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[6]">GTX3:DRP2D[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DFE_CFG" title="GTX3:DFE_CFG[7]">GTX3:DFE_CFG[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[7]">GTX3:DRP2D[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[8]">GTX3:DRP2D[8]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EYE_OFFSET" title="GTX3:RX_EYE_OFFSET[0]">GTX3:RX_EYE_OFFSET[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[9]">GTX3:DRP2D[9]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EYE_OFFSET" title="GTX3:RX_EYE_OFFSET[1]">GTX3:RX_EYE_OFFSET[1]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[10]">GTX3:DRP2D[10]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EYE_OFFSET" title="GTX3:RX_EYE_OFFSET[2]">GTX3:RX_EYE_OFFSET[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[11]">GTX3:DRP2D[11]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EYE_OFFSET" title="GTX3:RX_EYE_OFFSET[3]">GTX3:RX_EYE_OFFSET[3]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[12]">GTX3:DRP2D[12]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EYE_OFFSET" title="GTX3:RX_EYE_OFFSET[4]">GTX3:RX_EYE_OFFSET[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[13]">GTX3:DRP2D[13]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EYE_OFFSET" title="GTX3:RX_EYE_OFFSET[5]">GTX3:RX_EYE_OFFSET[5]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[14]">GTX3:DRP2D[14]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EYE_OFFSET" title="GTX3:RX_EYE_OFFSET[6]">GTX3:RX_EYE_OFFSET[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2D" title="GTX3:DRP2D[15]">GTX3:DRP2D[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EYE_OFFSET" title="GTX3:RX_EYE_OFFSET[7]">GTX3:RX_EYE_OFFSET[7]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[0]">GTX3:DRP2E[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TERMINATION_CTRL" title="GTX3:TERMINATION_CTRL[0]">GTX3:TERMINATION_CTRL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[1]">GTX3:DRP2E[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TERMINATION_CTRL" title="GTX3:TERMINATION_CTRL[1]">GTX3:TERMINATION_CTRL[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[2]">GTX3:DRP2E[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TERMINATION_CTRL" title="GTX3:TERMINATION_CTRL[2]">GTX3:TERMINATION_CTRL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[3]">GTX3:DRP2E[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TERMINATION_CTRL" title="GTX3:TERMINATION_CTRL[3]">GTX3:TERMINATION_CTRL[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[4]">GTX3:DRP2E[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TERMINATION_CTRL" title="GTX3:TERMINATION_CTRL[4]">GTX3:TERMINATION_CTRL[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[5]">GTX3:DRP2E[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[6]">GTX3:DRP2E[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TERMINATION_OVRD" title="GTX3:TERMINATION_OVRD">GTX3:TERMINATION_OVRD</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[7]">GTX3:DRP2E[7]</a><br><a href="#bits-xc6v-GTX-GTX3:RCV_TERM_GND" title="GTX3:RCV_TERM_GND">GTX3:RCV_TERM_GND</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[8]">GTX3:DRP2E[8]</a><br><a href="#bits-xc6v-GTX-GTX3:RCV_TERM_VTTRX" title="GTX3:RCV_TERM_VTTRX">GTX3:RCV_TERM_VTTRX</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[9]">GTX3:DRP2E[9]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EYE_SCANMODE" title="GTX3:RX_EYE_SCANMODE[0]">GTX3:RX_EYE_SCANMODE[0]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[10]">GTX3:DRP2E[10]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EYE_SCANMODE" title="GTX3:RX_EYE_SCANMODE[1]">GTX3:RX_EYE_SCANMODE[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DFE_CAL_TIME" title="GTX3:DFE_CAL_TIME[0]">GTX3:DFE_CAL_TIME[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[11]">GTX3:DRP2E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DFE_CAL_TIME" title="GTX3:DFE_CAL_TIME[1]">GTX3:DFE_CAL_TIME[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[12]">GTX3:DRP2E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DFE_CAL_TIME" title="GTX3:DFE_CAL_TIME[2]">GTX3:DFE_CAL_TIME[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[13]">GTX3:DRP2E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DFE_CAL_TIME" title="GTX3:DFE_CAL_TIME[3]">GTX3:DFE_CAL_TIME[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[14]">GTX3:DRP2E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DFE_CAL_TIME" title="GTX3:DFE_CAL_TIME[4]">GTX3:DFE_CAL_TIME[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2E" title="GTX3:DRP2E[15]">GTX3:DRP2E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:COMMA_10B_ENABLE" title="GTX3:COMMA_10B_ENABLE[0]">GTX3:COMMA_10B_ENABLE[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[0]">GTX3:DRP2F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:COMMA_10B_ENABLE" title="GTX3:COMMA_10B_ENABLE[1]">GTX3:COMMA_10B_ENABLE[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[1]">GTX3:DRP2F[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:COMMA_10B_ENABLE" title="GTX3:COMMA_10B_ENABLE[2]">GTX3:COMMA_10B_ENABLE[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[2]">GTX3:DRP2F[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:COMMA_10B_ENABLE" title="GTX3:COMMA_10B_ENABLE[3]">GTX3:COMMA_10B_ENABLE[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[3]">GTX3:DRP2F[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:COMMA_10B_ENABLE" title="GTX3:COMMA_10B_ENABLE[4]">GTX3:COMMA_10B_ENABLE[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[4]">GTX3:DRP2F[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:COMMA_10B_ENABLE" title="GTX3:COMMA_10B_ENABLE[5]">GTX3:COMMA_10B_ENABLE[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[5]">GTX3:DRP2F[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:COMMA_10B_ENABLE" title="GTX3:COMMA_10B_ENABLE[6]">GTX3:COMMA_10B_ENABLE[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[6]">GTX3:DRP2F[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:COMMA_10B_ENABLE" title="GTX3:COMMA_10B_ENABLE[7]">GTX3:COMMA_10B_ENABLE[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[7]">GTX3:DRP2F[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:COMMA_10B_ENABLE" title="GTX3:COMMA_10B_ENABLE[8]">GTX3:COMMA_10B_ENABLE[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[8]">GTX3:DRP2F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:COMMA_10B_ENABLE" title="GTX3:COMMA_10B_ENABLE[9]">GTX3:COMMA_10B_ENABLE[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[9]">GTX3:DRP2F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:COMMA_DOUBLE" title="GTX3:COMMA_DOUBLE">GTX3:COMMA_DOUBLE</a><br><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[10]">GTX3:DRP2F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[11]">GTX3:DRP2F[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_IDLE_ASSERT_DELAY" title="GTX3:TX_IDLE_ASSERT_DELAY[0]">GTX3:TX_IDLE_ASSERT_DELAY[0]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[12]">GTX3:DRP2F[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_IDLE_ASSERT_DELAY" title="GTX3:TX_IDLE_ASSERT_DELAY[1]">GTX3:TX_IDLE_ASSERT_DELAY[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[13]">GTX3:DRP2F[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_IDLE_ASSERT_DELAY" title="GTX3:TX_IDLE_ASSERT_DELAY[2]">GTX3:TX_IDLE_ASSERT_DELAY[2]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[14]">GTX3:DRP2F[14]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_XCLK_SEL" title="GTX3:TX_XCLK_SEL">GTX3:TX_XCLK_SEL</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP2F" title="GTX3:DRP2F[15]">GTX3:DRP2F[15]</a><br><a href="#bits-xc6v-GTX-GTX3:TXGEARBOX_USE" title="GTX3:TXGEARBOX_USE">GTX3:TXGEARBOX_USE</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 36</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[0]">GTX3:DRP30[0]</a><br><a href="#bits-xc6v-GTX-GTX3:MCOMMA_10B_VALUE" title="GTX3:MCOMMA_10B_VALUE[0]">GTX3:MCOMMA_10B_VALUE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[1]">GTX3:DRP30[1]</a><br><a href="#bits-xc6v-GTX-GTX3:MCOMMA_10B_VALUE" title="GTX3:MCOMMA_10B_VALUE[1]">GTX3:MCOMMA_10B_VALUE[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[2]">GTX3:DRP30[2]</a><br><a href="#bits-xc6v-GTX-GTX3:MCOMMA_10B_VALUE" title="GTX3:MCOMMA_10B_VALUE[2]">GTX3:MCOMMA_10B_VALUE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[3]">GTX3:DRP30[3]</a><br><a href="#bits-xc6v-GTX-GTX3:MCOMMA_10B_VALUE" title="GTX3:MCOMMA_10B_VALUE[3]">GTX3:MCOMMA_10B_VALUE[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[4]">GTX3:DRP30[4]</a><br><a href="#bits-xc6v-GTX-GTX3:MCOMMA_10B_VALUE" title="GTX3:MCOMMA_10B_VALUE[4]">GTX3:MCOMMA_10B_VALUE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[5]">GTX3:DRP30[5]</a><br><a href="#bits-xc6v-GTX-GTX3:MCOMMA_10B_VALUE" title="GTX3:MCOMMA_10B_VALUE[5]">GTX3:MCOMMA_10B_VALUE[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[6]">GTX3:DRP30[6]</a><br><a href="#bits-xc6v-GTX-GTX3:MCOMMA_10B_VALUE" title="GTX3:MCOMMA_10B_VALUE[6]">GTX3:MCOMMA_10B_VALUE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[7]">GTX3:DRP30[7]</a><br><a href="#bits-xc6v-GTX-GTX3:MCOMMA_10B_VALUE" title="GTX3:MCOMMA_10B_VALUE[7]">GTX3:MCOMMA_10B_VALUE[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[8]">GTX3:DRP30[8]</a><br><a href="#bits-xc6v-GTX-GTX3:MCOMMA_10B_VALUE" title="GTX3:MCOMMA_10B_VALUE[8]">GTX3:MCOMMA_10B_VALUE[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[9]">GTX3:DRP30[9]</a><br><a href="#bits-xc6v-GTX-GTX3:MCOMMA_10B_VALUE" title="GTX3:MCOMMA_10B_VALUE[9]">GTX3:MCOMMA_10B_VALUE[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[10]">GTX3:DRP30[10]</a><br><a href="#bits-xc6v-GTX-GTX3:MCOMMA_DETECT" title="GTX3:MCOMMA_DETECT">GTX3:MCOMMA_DETECT</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[11]">GTX3:DRP30[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_IDLE_DEASSERT_DELAY" title="GTX3:TX_IDLE_DEASSERT_DELAY[0]">GTX3:TX_IDLE_DEASSERT_DELAY[0]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[12]">GTX3:DRP30[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_IDLE_DEASSERT_DELAY" title="GTX3:TX_IDLE_DEASSERT_DELAY[1]">GTX3:TX_IDLE_DEASSERT_DELAY[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[13]">GTX3:DRP30[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_IDLE_DEASSERT_DELAY" title="GTX3:TX_IDLE_DEASSERT_DELAY[2]">GTX3:TX_IDLE_DEASSERT_DELAY[2]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[14]">GTX3:DRP30[14]</a><br><a href="#bits-xc6v-GTX-GTX3:INV.TXUSRCLK" title="~GTX3:INV.TXUSRCLK">~GTX3:INV.TXUSRCLK</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP30" title="GTX3:DRP30[15]">GTX3:DRP30[15]</a><br><a href="#bits-xc6v-GTX-GTX3:INV.TXUSRCLK2" title="~GTX3:INV.TXUSRCLK2">~GTX3:INV.TXUSRCLK2</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[0]">GTX3:DRP31[0]</a><br><a href="#bits-xc6v-GTX-GTX3:PCOMMA_10B_VALUE" title="GTX3:PCOMMA_10B_VALUE[0]">GTX3:PCOMMA_10B_VALUE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[1]">GTX3:DRP31[1]</a><br><a href="#bits-xc6v-GTX-GTX3:PCOMMA_10B_VALUE" title="GTX3:PCOMMA_10B_VALUE[1]">GTX3:PCOMMA_10B_VALUE[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[2]">GTX3:DRP31[2]</a><br><a href="#bits-xc6v-GTX-GTX3:PCOMMA_10B_VALUE" title="GTX3:PCOMMA_10B_VALUE[2]">GTX3:PCOMMA_10B_VALUE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[3]">GTX3:DRP31[3]</a><br><a href="#bits-xc6v-GTX-GTX3:PCOMMA_10B_VALUE" title="GTX3:PCOMMA_10B_VALUE[3]">GTX3:PCOMMA_10B_VALUE[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[4]">GTX3:DRP31[4]</a><br><a href="#bits-xc6v-GTX-GTX3:PCOMMA_10B_VALUE" title="GTX3:PCOMMA_10B_VALUE[4]">GTX3:PCOMMA_10B_VALUE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[5]">GTX3:DRP31[5]</a><br><a href="#bits-xc6v-GTX-GTX3:PCOMMA_10B_VALUE" title="GTX3:PCOMMA_10B_VALUE[5]">GTX3:PCOMMA_10B_VALUE[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[6]">GTX3:DRP31[6]</a><br><a href="#bits-xc6v-GTX-GTX3:PCOMMA_10B_VALUE" title="GTX3:PCOMMA_10B_VALUE[6]">GTX3:PCOMMA_10B_VALUE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[7]">GTX3:DRP31[7]</a><br><a href="#bits-xc6v-GTX-GTX3:PCOMMA_10B_VALUE" title="GTX3:PCOMMA_10B_VALUE[7]">GTX3:PCOMMA_10B_VALUE[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[8]">GTX3:DRP31[8]</a><br><a href="#bits-xc6v-GTX-GTX3:PCOMMA_10B_VALUE" title="GTX3:PCOMMA_10B_VALUE[8]">GTX3:PCOMMA_10B_VALUE[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[9]">GTX3:DRP31[9]</a><br><a href="#bits-xc6v-GTX-GTX3:PCOMMA_10B_VALUE" title="GTX3:PCOMMA_10B_VALUE[9]">GTX3:PCOMMA_10B_VALUE[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[10]">GTX3:DRP31[10]</a><br><a href="#bits-xc6v-GTX-GTX3:PCOMMA_DETECT" title="GTX3:PCOMMA_DETECT">GTX3:PCOMMA_DETECT</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[11]">GTX3:DRP31[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_BUFFER_USE" title="GTX3:TX_BUFFER_USE">GTX3:TX_BUFFER_USE</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[12]">GTX3:DRP31[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DATA_WIDTH" title="GTX3:TX_DATA_WIDTH[0]">GTX3:TX_DATA_WIDTH[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[13]">GTX3:DRP31[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DATA_WIDTH" title="GTX3:TX_DATA_WIDTH[1]">GTX3:TX_DATA_WIDTH[1]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[14]">GTX3:DRP31[14]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DATA_WIDTH" title="GTX3:TX_DATA_WIDTH[2]">GTX3:TX_DATA_WIDTH[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP31" title="GTX3:DRP31[15]">GTX3:DRP31[15]</a><br><a href="#bits-xc6v-GTX-GTX3:GEN_TXUSRCLK" title="GTX3:GEN_TXUSRCLK">GTX3:GEN_TXUSRCLK</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[0]">GTX3:DRP32[0]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[0]">GTX3:PMA_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[1]">GTX3:DRP32[1]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[1]">GTX3:PMA_CFG[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[2]">GTX3:DRP32[2]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[2]">GTX3:PMA_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[3]">GTX3:DRP32[3]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[3]">GTX3:PMA_CFG[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[4]">GTX3:DRP32[4]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[4]">GTX3:PMA_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[5]">GTX3:DRP32[5]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[5]">GTX3:PMA_CFG[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[6]">GTX3:DRP32[6]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[6]">GTX3:PMA_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[7]">GTX3:DRP32[7]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[7]">GTX3:PMA_CFG[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[8]">GTX3:DRP32[8]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[8]">GTX3:PMA_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[9]">GTX3:DRP32[9]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[9]">GTX3:PMA_CFG[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[10]">GTX3:DRP32[10]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[10]">GTX3:PMA_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[11]">GTX3:DRP32[11]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[11]">GTX3:PMA_CFG[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[12]">GTX3:DRP32[12]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[12]">GTX3:PMA_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[13]">GTX3:DRP32[13]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[13]">GTX3:PMA_CFG[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[14]">GTX3:DRP32[14]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[14]">GTX3:PMA_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP32" title="GTX3:DRP32[15]">GTX3:DRP32[15]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[15]">GTX3:PMA_CFG[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[0]">GTX3:DRP33[0]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[16]">GTX3:PMA_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[1]">GTX3:DRP33[1]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[17]">GTX3:PMA_CFG[17]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[2]">GTX3:DRP33[2]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[18]">GTX3:PMA_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[3]">GTX3:DRP33[3]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[19]">GTX3:PMA_CFG[19]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[4]">GTX3:DRP33[4]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[20]">GTX3:PMA_CFG[20]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[5]">GTX3:DRP33[5]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[21]">GTX3:PMA_CFG[21]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[6]">GTX3:DRP33[6]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[22]">GTX3:PMA_CFG[22]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[7]">GTX3:DRP33[7]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[23]">GTX3:PMA_CFG[23]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[8]">GTX3:DRP33[8]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[24]">GTX3:PMA_CFG[24]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[9]">GTX3:DRP33[9]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[25]">GTX3:PMA_CFG[25]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[10]">GTX3:DRP33[10]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[26]">GTX3:PMA_CFG[26]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[11]">GTX3:DRP33[11]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[27]">GTX3:PMA_CFG[27]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[12]">GTX3:DRP33[12]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[28]">GTX3:PMA_CFG[28]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[13]">GTX3:DRP33[13]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[29]">GTX3:PMA_CFG[29]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[14]">GTX3:DRP33[14]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[30]">GTX3:PMA_CFG[30]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP33" title="GTX3:DRP33[15]">GTX3:DRP33[15]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[31]">GTX3:PMA_CFG[31]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[0]">GTX3:DRP34[0]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[32]">GTX3:PMA_CFG[32]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[1]">GTX3:DRP34[1]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[33]">GTX3:PMA_CFG[33]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[2]">GTX3:DRP34[2]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[34]">GTX3:PMA_CFG[34]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[3]">GTX3:DRP34[3]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[35]">GTX3:PMA_CFG[35]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[4]">GTX3:DRP34[4]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[36]">GTX3:PMA_CFG[36]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[5]">GTX3:DRP34[5]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[37]">GTX3:PMA_CFG[37]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[6]">GTX3:DRP34[6]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[38]">GTX3:PMA_CFG[38]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[7]">GTX3:DRP34[7]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[39]">GTX3:PMA_CFG[39]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[8]">GTX3:DRP34[8]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[40]">GTX3:PMA_CFG[40]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[9]">GTX3:DRP34[9]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[41]">GTX3:PMA_CFG[41]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[10]">GTX3:DRP34[10]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[42]">GTX3:PMA_CFG[42]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[11]">GTX3:DRP34[11]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[43]">GTX3:PMA_CFG[43]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[12]">GTX3:DRP34[12]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[44]">GTX3:PMA_CFG[44]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[13]">GTX3:DRP34[13]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[45]">GTX3:PMA_CFG[45]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[14]">GTX3:DRP34[14]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[46]">GTX3:PMA_CFG[46]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP34" title="GTX3:DRP34[15]">GTX3:DRP34[15]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[47]">GTX3:PMA_CFG[47]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[0]">GTX3:DRP35[0]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[48]">GTX3:PMA_CFG[48]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[1]">GTX3:DRP35[1]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[49]">GTX3:PMA_CFG[49]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[2]">GTX3:DRP35[2]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[50]">GTX3:PMA_CFG[50]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[3]">GTX3:DRP35[3]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[51]">GTX3:PMA_CFG[51]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[4]">GTX3:DRP35[4]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[52]">GTX3:PMA_CFG[52]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[5]">GTX3:DRP35[5]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[53]">GTX3:PMA_CFG[53]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[6]">GTX3:DRP35[6]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[54]">GTX3:PMA_CFG[54]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[7]">GTX3:DRP35[7]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[55]">GTX3:PMA_CFG[55]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[8]">GTX3:DRP35[8]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[56]">GTX3:PMA_CFG[56]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[9]">GTX3:DRP35[9]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[57]">GTX3:PMA_CFG[57]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[10]">GTX3:DRP35[10]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[58]">GTX3:PMA_CFG[58]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[11]">GTX3:DRP35[11]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[59]">GTX3:PMA_CFG[59]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[12]">GTX3:DRP35[12]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[60]">GTX3:PMA_CFG[60]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[13]">GTX3:DRP35[13]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[61]">GTX3:PMA_CFG[61]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[14]">GTX3:DRP35[14]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[62]">GTX3:PMA_CFG[62]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP35" title="GTX3:DRP35[15]">GTX3:DRP35[15]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[63]">GTX3:PMA_CFG[63]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[0]">GTX3:DRP36[0]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[16]">GTX3:PMA_TX_CFG[16]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[1]">GTX3:DRP36[1]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[17]">GTX3:PMA_TX_CFG[17]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[2]">GTX3:DRP36[2]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[18]">GTX3:PMA_TX_CFG[18]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[3]">GTX3:DRP36[3]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[19]">GTX3:PMA_TX_CFG[19]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[4]">GTX3:DRP36[4]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[64]">GTX3:PMA_CFG[64]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[5]">GTX3:DRP36[5]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[65]">GTX3:PMA_CFG[65]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[6]">GTX3:DRP36[6]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[66]">GTX3:PMA_CFG[66]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[7]">GTX3:DRP36[7]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[67]">GTX3:PMA_CFG[67]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[8]">GTX3:DRP36[8]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[68]">GTX3:PMA_CFG[68]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[9]">GTX3:DRP36[9]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[69]">GTX3:PMA_CFG[69]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[10]">GTX3:DRP36[10]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[70]">GTX3:PMA_CFG[70]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[11]">GTX3:DRP36[11]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[71]">GTX3:PMA_CFG[71]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[12]">GTX3:DRP36[12]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[72]">GTX3:PMA_CFG[72]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[13]">GTX3:DRP36[13]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[73]">GTX3:PMA_CFG[73]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[14]">GTX3:DRP36[14]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[74]">GTX3:PMA_CFG[74]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP36" title="GTX3:DRP36[15]">GTX3:DRP36[15]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_CFG" title="GTX3:PMA_CFG[75]">GTX3:PMA_CFG[75]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[0]">GTX3:DRP37[0]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[0]">GTX3:PMA_TX_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[1]">GTX3:DRP37[1]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[1]">GTX3:PMA_TX_CFG[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[2]">GTX3:DRP37[2]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[2]">GTX3:PMA_TX_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[3]">GTX3:DRP37[3]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[3]">GTX3:PMA_TX_CFG[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[4]">GTX3:DRP37[4]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[4]">GTX3:PMA_TX_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[5]">GTX3:DRP37[5]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[5]">GTX3:PMA_TX_CFG[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[6]">GTX3:DRP37[6]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[6]">GTX3:PMA_TX_CFG[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[7]">GTX3:DRP37[7]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[7]">GTX3:PMA_TX_CFG[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[8]">GTX3:DRP37[8]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[8]">GTX3:PMA_TX_CFG[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[9]">GTX3:DRP37[9]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[9]">GTX3:PMA_TX_CFG[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[10]">GTX3:DRP37[10]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[10]">GTX3:PMA_TX_CFG[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[11]">GTX3:DRP37[11]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[11]">GTX3:PMA_TX_CFG[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[12]">GTX3:DRP37[12]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[12]">GTX3:PMA_TX_CFG[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[13]">GTX3:DRP37[13]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[13]">GTX3:PMA_TX_CFG[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[14]">GTX3:DRP37[14]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[14]">GTX3:PMA_TX_CFG[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP37" title="GTX3:DRP37[15]">GTX3:DRP37[15]</a><br><a href="#bits-xc6v-GTX-GTX3:PMA_TX_CFG" title="GTX3:PMA_TX_CFG[15]">GTX3:PMA_TX_CFG[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 37</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[0]">GTX3:DRP38[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_0" title="GTX3:TX_MARGIN_LOW_0[0]">GTX3:TX_MARGIN_LOW_0[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[1]">GTX3:DRP38[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_0" title="GTX3:TX_MARGIN_LOW_0[1]">GTX3:TX_MARGIN_LOW_0[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[2]">GTX3:DRP38[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_0" title="GTX3:TX_MARGIN_LOW_0[2]">GTX3:TX_MARGIN_LOW_0[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[3]">GTX3:DRP38[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_0" title="GTX3:TX_MARGIN_LOW_0[3]">GTX3:TX_MARGIN_LOW_0[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[4]">GTX3:DRP38[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_0" title="GTX3:TX_MARGIN_LOW_0[4]">GTX3:TX_MARGIN_LOW_0[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[5]">GTX3:DRP38[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_0" title="GTX3:TX_MARGIN_LOW_0[5]">GTX3:TX_MARGIN_LOW_0[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[6]">GTX3:DRP38[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_0" title="GTX3:TX_MARGIN_LOW_0[6]">GTX3:TX_MARGIN_LOW_0[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[7]">GTX3:DRP38[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_0" title="GTX3:TX_MARGIN_FULL_0[0]">GTX3:TX_MARGIN_FULL_0[0]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[8]">GTX3:DRP38[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_0" title="GTX3:TX_MARGIN_FULL_0[1]">GTX3:TX_MARGIN_FULL_0[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[9]">GTX3:DRP38[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_0" title="GTX3:TX_MARGIN_FULL_0[2]">GTX3:TX_MARGIN_FULL_0[2]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[10]">GTX3:DRP38[10]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_0" title="GTX3:TX_MARGIN_FULL_0[3]">GTX3:TX_MARGIN_FULL_0[3]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[11]">GTX3:DRP38[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_0" title="GTX3:TX_MARGIN_FULL_0[4]">GTX3:TX_MARGIN_FULL_0[4]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[12]">GTX3:DRP38[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_0" title="GTX3:TX_MARGIN_FULL_0[5]">GTX3:TX_MARGIN_FULL_0[5]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[13]">GTX3:DRP38[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_0" title="GTX3:TX_MARGIN_FULL_0[6]">GTX3:TX_MARGIN_FULL_0[6]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[14]">GTX3:DRP38[14]</a><br><a href="#bits-xc6v-GTX-GTX3:TXOUTCLKPCS_SEL" title="GTX3:TXOUTCLKPCS_SEL">GTX3:TXOUTCLKPCS_SEL</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP38" title="GTX3:DRP38[15]">GTX3:DRP38[15]</a><br><a href="#bits-xc6v-GTX-GTX3:INV.DCLK" title="~GTX3:INV.DCLK">~GTX3:INV.DCLK</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[0]">GTX3:DRP39[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_1" title="GTX3:TX_MARGIN_LOW_1[0]">GTX3:TX_MARGIN_LOW_1[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[1]">GTX3:DRP39[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_1" title="GTX3:TX_MARGIN_LOW_1[1]">GTX3:TX_MARGIN_LOW_1[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[2]">GTX3:DRP39[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_1" title="GTX3:TX_MARGIN_LOW_1[2]">GTX3:TX_MARGIN_LOW_1[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[3]">GTX3:DRP39[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_1" title="GTX3:TX_MARGIN_LOW_1[3]">GTX3:TX_MARGIN_LOW_1[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[4]">GTX3:DRP39[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_1" title="GTX3:TX_MARGIN_LOW_1[4]">GTX3:TX_MARGIN_LOW_1[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[5]">GTX3:DRP39[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_1" title="GTX3:TX_MARGIN_LOW_1[5]">GTX3:TX_MARGIN_LOW_1[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[6]">GTX3:DRP39[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_1" title="GTX3:TX_MARGIN_LOW_1[6]">GTX3:TX_MARGIN_LOW_1[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[7]">GTX3:DRP39[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_1" title="GTX3:TX_MARGIN_FULL_1[0]">GTX3:TX_MARGIN_FULL_1[0]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[8]">GTX3:DRP39[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_1" title="GTX3:TX_MARGIN_FULL_1[1]">GTX3:TX_MARGIN_FULL_1[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[9]">GTX3:DRP39[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_1" title="GTX3:TX_MARGIN_FULL_1[2]">GTX3:TX_MARGIN_FULL_1[2]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[10]">GTX3:DRP39[10]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_1" title="GTX3:TX_MARGIN_FULL_1[3]">GTX3:TX_MARGIN_FULL_1[3]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[11]">GTX3:DRP39[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_1" title="GTX3:TX_MARGIN_FULL_1[4]">GTX3:TX_MARGIN_FULL_1[4]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[12]">GTX3:DRP39[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_1" title="GTX3:TX_MARGIN_FULL_1[5]">GTX3:TX_MARGIN_FULL_1[5]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[13]">GTX3:DRP39[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_1" title="GTX3:TX_MARGIN_FULL_1[6]">GTX3:TX_MARGIN_FULL_1[6]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[14]">GTX3:DRP39[14]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_TDCC_CFG" title="GTX3:TX_TDCC_CFG[0]">GTX3:TX_TDCC_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP39" title="GTX3:DRP39[15]">GTX3:DRP39[15]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_TDCC_CFG" title="GTX3:TX_TDCC_CFG[1]">GTX3:TX_TDCC_CFG[1]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[0]">GTX3:DRP3A[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_2" title="GTX3:TX_MARGIN_LOW_2[0]">GTX3:TX_MARGIN_LOW_2[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[1]">GTX3:DRP3A[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_2" title="GTX3:TX_MARGIN_LOW_2[1]">GTX3:TX_MARGIN_LOW_2[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[2]">GTX3:DRP3A[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_2" title="GTX3:TX_MARGIN_LOW_2[2]">GTX3:TX_MARGIN_LOW_2[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[3]">GTX3:DRP3A[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_2" title="GTX3:TX_MARGIN_LOW_2[3]">GTX3:TX_MARGIN_LOW_2[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[4]">GTX3:DRP3A[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_2" title="GTX3:TX_MARGIN_LOW_2[4]">GTX3:TX_MARGIN_LOW_2[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[5]">GTX3:DRP3A[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_2" title="GTX3:TX_MARGIN_LOW_2[5]">GTX3:TX_MARGIN_LOW_2[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[6]">GTX3:DRP3A[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_2" title="GTX3:TX_MARGIN_LOW_2[6]">GTX3:TX_MARGIN_LOW_2[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[7]">GTX3:DRP3A[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_2" title="GTX3:TX_MARGIN_FULL_2[0]">GTX3:TX_MARGIN_FULL_2[0]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[8]">GTX3:DRP3A[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_2" title="GTX3:TX_MARGIN_FULL_2[1]">GTX3:TX_MARGIN_FULL_2[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[9]">GTX3:DRP3A[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_2" title="GTX3:TX_MARGIN_FULL_2[2]">GTX3:TX_MARGIN_FULL_2[2]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[10]">GTX3:DRP3A[10]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_2" title="GTX3:TX_MARGIN_FULL_2[3]">GTX3:TX_MARGIN_FULL_2[3]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[11]">GTX3:DRP3A[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_2" title="GTX3:TX_MARGIN_FULL_2[4]">GTX3:TX_MARGIN_FULL_2[4]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[12]">GTX3:DRP3A[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_2" title="GTX3:TX_MARGIN_FULL_2[5]">GTX3:TX_MARGIN_FULL_2[5]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[13]">GTX3:DRP3A[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_2" title="GTX3:TX_MARGIN_FULL_2[6]">GTX3:TX_MARGIN_FULL_2[6]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[14]">GTX3:DRP3A[14]</a><br><a href="#bits-xc6v-GTX-GTX3:TXDRIVE_LOOPBACK_HIZ" title="~GTX3:TXDRIVE_LOOPBACK_HIZ">~GTX3:TXDRIVE_LOOPBACK_HIZ</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3A" title="GTX3:DRP3A[15]">GTX3:DRP3A[15]</a><br><a href="#bits-xc6v-GTX-GTX3:TXDRIVE_LOOPBACK_PD" title="~GTX3:TXDRIVE_LOOPBACK_PD">~GTX3:TXDRIVE_LOOPBACK_PD</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[0]">GTX3:DRP3B[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_3" title="GTX3:TX_MARGIN_LOW_3[0]">GTX3:TX_MARGIN_LOW_3[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[1]">GTX3:DRP3B[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_3" title="GTX3:TX_MARGIN_LOW_3[1]">GTX3:TX_MARGIN_LOW_3[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[2]">GTX3:DRP3B[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_3" title="GTX3:TX_MARGIN_LOW_3[2]">GTX3:TX_MARGIN_LOW_3[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[3]">GTX3:DRP3B[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_3" title="GTX3:TX_MARGIN_LOW_3[3]">GTX3:TX_MARGIN_LOW_3[3]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[4]">GTX3:DRP3B[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_3" title="GTX3:TX_MARGIN_LOW_3[4]">GTX3:TX_MARGIN_LOW_3[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[5]">GTX3:DRP3B[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_3" title="GTX3:TX_MARGIN_LOW_3[5]">GTX3:TX_MARGIN_LOW_3[5]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[6]">GTX3:DRP3B[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_3" title="GTX3:TX_MARGIN_LOW_3[6]">GTX3:TX_MARGIN_LOW_3[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[7]">GTX3:DRP3B[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_3" title="GTX3:TX_MARGIN_FULL_3[0]">GTX3:TX_MARGIN_FULL_3[0]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[8]">GTX3:DRP3B[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_3" title="GTX3:TX_MARGIN_FULL_3[1]">GTX3:TX_MARGIN_FULL_3[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[9]">GTX3:DRP3B[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_3" title="GTX3:TX_MARGIN_FULL_3[2]">GTX3:TX_MARGIN_FULL_3[2]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[10]">GTX3:DRP3B[10]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_3" title="GTX3:TX_MARGIN_FULL_3[3]">GTX3:TX_MARGIN_FULL_3[3]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[11]">GTX3:DRP3B[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_3" title="GTX3:TX_MARGIN_FULL_3[4]">GTX3:TX_MARGIN_FULL_3[4]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[12]">GTX3:DRP3B[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_3" title="GTX3:TX_MARGIN_FULL_3[5]">GTX3:TX_MARGIN_FULL_3[5]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[13]">GTX3:DRP3B[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_3" title="GTX3:TX_MARGIN_FULL_3[6]">GTX3:TX_MARGIN_FULL_3[6]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXSWING" title="GTX3:A_TXSWING">GTX3:A_TXSWING</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[14]">GTX3:DRP3B[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXDEEMPH" title="GTX3:A_TXDEEMPH">GTX3:A_TXDEEMPH</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3B" title="GTX3:DRP3B[15]">GTX3:DRP3B[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[0]">GTX3:DRP3C[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_4" title="GTX3:TX_MARGIN_LOW_4[0]">GTX3:TX_MARGIN_LOW_4[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[1]">GTX3:DRP3C[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_4" title="GTX3:TX_MARGIN_LOW_4[1]">GTX3:TX_MARGIN_LOW_4[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[2]">GTX3:DRP3C[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_4" title="GTX3:TX_MARGIN_LOW_4[2]">GTX3:TX_MARGIN_LOW_4[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[3]">GTX3:DRP3C[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_4" title="GTX3:TX_MARGIN_LOW_4[3]">GTX3:TX_MARGIN_LOW_4[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[4]">GTX3:DRP3C[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_4" title="GTX3:TX_MARGIN_LOW_4[4]">GTX3:TX_MARGIN_LOW_4[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[5]">GTX3:DRP3C[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_4" title="GTX3:TX_MARGIN_LOW_4[5]">GTX3:TX_MARGIN_LOW_4[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[6]">GTX3:DRP3C[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_4" title="GTX3:TX_MARGIN_LOW_4[6]">GTX3:TX_MARGIN_LOW_4[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[7]">GTX3:DRP3C[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_4" title="GTX3:TX_MARGIN_FULL_4[0]">GTX3:TX_MARGIN_FULL_4[0]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[8]">GTX3:DRP3C[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_4" title="GTX3:TX_MARGIN_FULL_4[1]">GTX3:TX_MARGIN_FULL_4[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[9]">GTX3:DRP3C[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_4" title="GTX3:TX_MARGIN_FULL_4[2]">GTX3:TX_MARGIN_FULL_4[2]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[10]">GTX3:DRP3C[10]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_4" title="GTX3:TX_MARGIN_FULL_4[3]">GTX3:TX_MARGIN_FULL_4[3]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[11]">GTX3:DRP3C[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_4" title="GTX3:TX_MARGIN_FULL_4[4]">GTX3:TX_MARGIN_FULL_4[4]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[12]">GTX3:DRP3C[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_4" title="GTX3:TX_MARGIN_FULL_4[5]">GTX3:TX_MARGIN_FULL_4[5]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[13]">GTX3:DRP3C[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_4" title="GTX3:TX_MARGIN_FULL_4[6]">GTX3:TX_MARGIN_FULL_4[6]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[14]">GTX3:DRP3C[14]</a><br><a href="#bits-xc6v-GTX-GTX3:TXDRIVE_DRP_EN" title="GTX3:TXDRIVE_DRP_EN">GTX3:TXDRIVE_DRP_EN</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3C" title="GTX3:DRP3C[15]">GTX3:DRP3C[15]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DRIVE_MODE" title="GTX3:TX_DRIVE_MODE">GTX3:TX_DRIVE_MODE</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXDIFFCTRL" title="GTX3:A_TXDIFFCTRL[0]">GTX3:A_TXDIFFCTRL[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[0]">GTX3:DRP3D[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXDIFFCTRL" title="GTX3:A_TXDIFFCTRL[1]">GTX3:A_TXDIFFCTRL[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[1]">GTX3:DRP3D[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXDIFFCTRL" title="GTX3:A_TXDIFFCTRL[2]">GTX3:A_TXDIFFCTRL[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[2]">GTX3:DRP3D[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXDIFFCTRL" title="GTX3:A_TXDIFFCTRL[3]">GTX3:A_TXDIFFCTRL[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[3]">GTX3:DRP3D[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXBUFDIFFCTRL" title="GTX3:A_TXBUFDIFFCTRL[0]">GTX3:A_TXBUFDIFFCTRL[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[4]">GTX3:DRP3D[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXBUFDIFFCTRL" title="GTX3:A_TXBUFDIFFCTRL[1]">GTX3:A_TXBUFDIFFCTRL[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[5]">GTX3:DRP3D[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXBUFDIFFCTRL" title="GTX3:A_TXBUFDIFFCTRL[2]">GTX3:A_TXBUFDIFFCTRL[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[6]">GTX3:DRP3D[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPREEMPHASIS" title="GTX3:A_TXPREEMPHASIS[0]">GTX3:A_TXPREEMPHASIS[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[7]">GTX3:DRP3D[7]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPREEMPHASIS" title="GTX3:A_TXPREEMPHASIS[1]">GTX3:A_TXPREEMPHASIS[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[8]">GTX3:DRP3D[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPREEMPHASIS" title="GTX3:A_TXPREEMPHASIS[2]">GTX3:A_TXPREEMPHASIS[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[9]">GTX3:DRP3D[9]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPREEMPHASIS" title="GTX3:A_TXPREEMPHASIS[3]">GTX3:A_TXPREEMPHASIS[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[10]">GTX3:DRP3D[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPOSTEMPHASIS" title="GTX3:A_TXPOSTEMPHASIS[0]">GTX3:A_TXPOSTEMPHASIS[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[11]">GTX3:DRP3D[11]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPOSTEMPHASIS" title="GTX3:A_TXPOSTEMPHASIS[1]">GTX3:A_TXPOSTEMPHASIS[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[12]">GTX3:DRP3D[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPOSTEMPHASIS" title="GTX3:A_TXPOSTEMPHASIS[2]">GTX3:A_TXPOSTEMPHASIS[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[13]">GTX3:DRP3D[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPOSTEMPHASIS" title="GTX3:A_TXPOSTEMPHASIS[3]">GTX3:A_TXPOSTEMPHASIS[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[14]">GTX3:DRP3D[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXPOSTEMPHASIS" title="GTX3:A_TXPOSTEMPHASIS[4]">GTX3:A_TXPOSTEMPHASIS[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3D" title="GTX3:DRP3D[15]">GTX3:DRP3D[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[0]">GTX3:DRP3E[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DEEMPH_0" title="GTX3:TX_DEEMPH_0[0]">GTX3:TX_DEEMPH_0[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[1]">GTX3:DRP3E[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DEEMPH_0" title="GTX3:TX_DEEMPH_0[1]">GTX3:TX_DEEMPH_0[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[2]">GTX3:DRP3E[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DEEMPH_0" title="GTX3:TX_DEEMPH_0[2]">GTX3:TX_DEEMPH_0[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[3]">GTX3:DRP3E[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DEEMPH_0" title="GTX3:TX_DEEMPH_0[3]">GTX3:TX_DEEMPH_0[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[4]">GTX3:DRP3E[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DEEMPH_0" title="GTX3:TX_DEEMPH_0[4]">GTX3:TX_DEEMPH_0[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[5]">GTX3:DRP3E[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DEEMPH_1" title="GTX3:TX_DEEMPH_1[0]">GTX3:TX_DEEMPH_1[0]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[6]">GTX3:DRP3E[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DEEMPH_1" title="GTX3:TX_DEEMPH_1[1]">GTX3:TX_DEEMPH_1[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[7]">GTX3:DRP3E[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DEEMPH_1" title="GTX3:TX_DEEMPH_1[2]">GTX3:TX_DEEMPH_1[2]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[8]">GTX3:DRP3E[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DEEMPH_1" title="GTX3:TX_DEEMPH_1[3]">GTX3:TX_DEEMPH_1[3]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[9]">GTX3:DRP3E[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DEEMPH_1" title="GTX3:TX_DEEMPH_1[4]">GTX3:TX_DEEMPH_1[4]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[10]">GTX3:DRP3E[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[11]">GTX3:DRP3E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[12]">GTX3:DRP3E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXMARGIN" title="GTX3:A_TXMARGIN[0]">GTX3:A_TXMARGIN[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[13]">GTX3:DRP3E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_TXMARGIN" title="GTX3:A_TXMARGIN[1]">GTX3:A_TXMARGIN[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[14]">GTX3:DRP3E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_TXMARGIN" title="GTX3:A_TXMARGIN[2]">GTX3:A_TXMARGIN[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP3E" title="GTX3:DRP3E[15]">GTX3:DRP3E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[0]">GTX3:DRP3F[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_RATE" title="GTX3:TRANS_TIME_RATE[0]">GTX3:TRANS_TIME_RATE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[1]">GTX3:DRP3F[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_RATE" title="GTX3:TRANS_TIME_RATE[1]">GTX3:TRANS_TIME_RATE[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[2]">GTX3:DRP3F[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_RATE" title="GTX3:TRANS_TIME_RATE[2]">GTX3:TRANS_TIME_RATE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[3]">GTX3:DRP3F[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_RATE" title="GTX3:TRANS_TIME_RATE[3]">GTX3:TRANS_TIME_RATE[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[4]">GTX3:DRP3F[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_RATE" title="GTX3:TRANS_TIME_RATE[4]">GTX3:TRANS_TIME_RATE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[5]">GTX3:DRP3F[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_RATE" title="GTX3:TRANS_TIME_RATE[5]">GTX3:TRANS_TIME_RATE[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[6]">GTX3:DRP3F[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_RATE" title="GTX3:TRANS_TIME_RATE[6]">GTX3:TRANS_TIME_RATE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[7]">GTX3:DRP3F[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TRANS_TIME_RATE" title="GTX3:TRANS_TIME_RATE[7]">GTX3:TRANS_TIME_RATE[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[8]">GTX3:DRP3F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[9]">GTX3:DRP3F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[10]">GTX3:DRP3F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[11]">GTX3:DRP3F[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[12]">GTX3:DRP3F[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[13]">GTX3:DRP3F[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[14]">GTX3:DRP3F[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP3F" title="GTX3:DRP3F[15]">GTX3:DRP3F[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 38</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_RXEQMIX" title="GTX3:A_RXEQMIX[0]">GTX3:A_RXEQMIX[0]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[0]">GTX3:DRP40[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_RXEQMIX" title="GTX3:A_RXEQMIX[1]">GTX3:A_RXEQMIX[1]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[1]">GTX3:DRP40[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_RXEQMIX" title="GTX3:A_RXEQMIX[2]">GTX3:A_RXEQMIX[2]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[2]">GTX3:DRP40[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_RXEQMIX" title="GTX3:A_RXEQMIX[3]">GTX3:A_RXEQMIX[3]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[3]">GTX3:DRP40[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_RXEQMIX" title="GTX3:A_RXEQMIX[4]">GTX3:A_RXEQMIX[4]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[4]">GTX3:DRP40[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_RXEQMIX" title="GTX3:A_RXEQMIX[5]">GTX3:A_RXEQMIX[5]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[5]">GTX3:DRP40[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_RXEQMIX" title="GTX3:A_RXEQMIX[6]">GTX3:A_RXEQMIX[6]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[6]">GTX3:DRP40[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_RXEQMIX" title="GTX3:A_RXEQMIX[7]">GTX3:A_RXEQMIX[7]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[7]">GTX3:DRP40[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:A_RXEQMIX" title="GTX3:A_RXEQMIX[8]">GTX3:A_RXEQMIX[8]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[8]">GTX3:DRP40[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:A_RXEQMIX" title="GTX3:A_RXEQMIX[9]">GTX3:A_RXEQMIX[9]</a><br><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[9]">GTX3:DRP40[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[10]">GTX3:DRP40[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[11]">GTX3:DRP40[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[12]">GTX3:DRP40[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[13]">GTX3:DRP40[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[14]">GTX3:DRP40[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP40" title="GTX3:DRP40[15]">GTX3:DRP40[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[0]">GTX3:DRP41[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[16]">GTX3:TST_ATTR[16]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[1]">GTX3:DRP41[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[17]">GTX3:TST_ATTR[17]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[2]">GTX3:DRP41[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[18]">GTX3:TST_ATTR[18]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[3]">GTX3:DRP41[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[19]">GTX3:TST_ATTR[19]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[4]">GTX3:DRP41[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[20]">GTX3:TST_ATTR[20]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[5]">GTX3:DRP41[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[21]">GTX3:TST_ATTR[21]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[6]">GTX3:DRP41[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[22]">GTX3:TST_ATTR[22]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[7]">GTX3:DRP41[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[23]">GTX3:TST_ATTR[23]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[8]">GTX3:DRP41[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[24]">GTX3:TST_ATTR[24]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[9]">GTX3:DRP41[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[25]">GTX3:TST_ATTR[25]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[10]">GTX3:DRP41[10]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[26]">GTX3:TST_ATTR[26]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[11]">GTX3:DRP41[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[27]">GTX3:TST_ATTR[27]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[12]">GTX3:DRP41[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[28]">GTX3:TST_ATTR[28]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[13]">GTX3:DRP41[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[29]">GTX3:TST_ATTR[29]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[14]">GTX3:DRP41[14]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[30]">GTX3:TST_ATTR[30]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP41" title="GTX3:DRP41[15]">GTX3:DRP41[15]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[31]">GTX3:TST_ATTR[31]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[0]">GTX3:DRP42[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[0]">GTX3:TST_ATTR[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[1]">GTX3:DRP42[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[1]">GTX3:TST_ATTR[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[2]">GTX3:DRP42[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[2]">GTX3:TST_ATTR[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[3]">GTX3:DRP42[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[3]">GTX3:TST_ATTR[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[4]">GTX3:DRP42[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[4]">GTX3:TST_ATTR[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[5]">GTX3:DRP42[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[5]">GTX3:TST_ATTR[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[6]">GTX3:DRP42[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[6]">GTX3:TST_ATTR[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[7]">GTX3:DRP42[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[7]">GTX3:TST_ATTR[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[8]">GTX3:DRP42[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[8]">GTX3:TST_ATTR[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[9]">GTX3:DRP42[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[9]">GTX3:TST_ATTR[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[10]">GTX3:DRP42[10]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[10]">GTX3:TST_ATTR[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[11]">GTX3:DRP42[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[11]">GTX3:TST_ATTR[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[12]">GTX3:DRP42[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[12]">GTX3:TST_ATTR[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[13]">GTX3:DRP42[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[13]">GTX3:TST_ATTR[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[14]">GTX3:DRP42[14]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[14]">GTX3:TST_ATTR[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP42" title="GTX3:DRP42[15]">GTX3:DRP42[15]</a><br><a href="#bits-xc6v-GTX-GTX3:TST_ATTR" title="GTX3:TST_ATTR[15]">GTX3:TST_ATTR[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[0]">GTX3:DRP43[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TXOUTCLK_CTRL" title="GTX3:TXOUTCLK_CTRL[2]">GTX3:TXOUTCLK_CTRL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[1]">GTX3:DRP43[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TXOUTCLK_CTRL" title="GTX3:TXOUTCLK_CTRL[1]">GTX3:TXOUTCLK_CTRL[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[2]">GTX3:DRP43[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TXOUTCLK_CTRL" title="GTX3:TXOUTCLK_CTRL[0]">GTX3:TXOUTCLK_CTRL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[3]">GTX3:DRP43[3]</a><br><a href="#bits-xc6v-GTX-GTX3:RXRECCLK_CTRL" title="GTX3:RXRECCLK_CTRL[2]">GTX3:RXRECCLK_CTRL[2]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[4]">GTX3:DRP43[4]</a><br><a href="#bits-xc6v-GTX-GTX3:RXRECCLK_CTRL" title="GTX3:RXRECCLK_CTRL[1]">GTX3:RXRECCLK_CTRL[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[5]">GTX3:DRP43[5]</a><br><a href="#bits-xc6v-GTX-GTX3:RXRECCLK_CTRL" title="GTX3:RXRECCLK_CTRL[0]">GTX3:RXRECCLK_CTRL[0]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[6]">GTX3:DRP43[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[7]">GTX3:DRP43[7]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[8]">GTX3:DRP43[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[9]">GTX3:DRP43[9]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[10]">GTX3:DRP43[10]</a><br><a href="#bits-xc6v-GTX-GTX3:INV.TSTCLK0" title="~GTX3:INV.TSTCLK0">~GTX3:INV.TSTCLK0</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[11]">GTX3:DRP43[11]</a><br><a href="#bits-xc6v-GTX-GTX3:INV.TSTCLK1" title="~GTX3:INV.TSTCLK1">~GTX3:INV.TSTCLK1</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[12]">GTX3:DRP43[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[13]">GTX3:DRP43[13]</a><br><a href="#bits-xc6v-GTX-GTX3:INV.SCANCLK" title="~GTX3:INV.SCANCLK">~GTX3:INV.SCANCLK</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[14]">GTX3:DRP43[14]</a><br><a href="#bits-xc6v-GTX-GTX3:INV.GREFCLKTX" title="~GTX3:INV.GREFCLKTX">~GTX3:INV.GREFCLKTX</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP43" title="GTX3:DRP43[15]">GTX3:DRP43[15]</a><br><a href="#bits-xc6v-GTX-GTX3:INV.GREFCLKRX" title="~GTX3:INV.GREFCLKRX">~GTX3:INV.GREFCLKRX</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[0]">GTX3:DRP44[0]</a><br><a href="#bits-xc6v-GTX-GTX3:POWER_SAVE" title="GTX3:POWER_SAVE[0]">GTX3:POWER_SAVE[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[1]">GTX3:DRP44[1]</a><br><a href="#bits-xc6v-GTX-GTX3:POWER_SAVE" title="GTX3:POWER_SAVE[1]">GTX3:POWER_SAVE[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[2]">GTX3:DRP44[2]</a><br><a href="#bits-xc6v-GTX-GTX3:POWER_SAVE" title="GTX3:POWER_SAVE[2]">GTX3:POWER_SAVE[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[3]">GTX3:DRP44[3]</a><br><a href="#bits-xc6v-GTX-GTX3:POWER_SAVE" title="GTX3:POWER_SAVE[3]">GTX3:POWER_SAVE[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[4]">GTX3:DRP44[4]</a><br><a href="#bits-xc6v-GTX-GTX3:POWER_SAVE" title="GTX3:POWER_SAVE[4]">GTX3:POWER_SAVE[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[5]">GTX3:DRP44[5]</a><br><a href="#bits-xc6v-GTX-GTX3:POWER_SAVE" title="GTX3:POWER_SAVE[5]">GTX3:POWER_SAVE[5]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[6]">GTX3:DRP44[6]</a><br><a href="#bits-xc6v-GTX-GTX3:POWER_SAVE" title="GTX3:POWER_SAVE[6]">GTX3:POWER_SAVE[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[7]">GTX3:DRP44[7]</a><br><a href="#bits-xc6v-GTX-GTX3:POWER_SAVE" title="GTX3:POWER_SAVE[7]">GTX3:POWER_SAVE[7]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[8]">GTX3:DRP44[8]</a><br><a href="#bits-xc6v-GTX-GTX3:POWER_SAVE" title="GTX3:POWER_SAVE[8]">GTX3:POWER_SAVE[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[9]">GTX3:DRP44[9]</a><br><a href="#bits-xc6v-GTX-GTX3:POWER_SAVE" title="GTX3:POWER_SAVE[9]">GTX3:POWER_SAVE[9]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[10]">GTX3:DRP44[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[11]">GTX3:DRP44[11]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[12]">GTX3:DRP44[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[13]">GTX3:DRP44[13]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[14]">GTX3:DRP44[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP44" title="GTX3:DRP44[15]">GTX3:DRP44[15]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[0]">GTX3:DRP45[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_BYTECLK_CFG" title="GTX3:TX_BYTECLK_CFG[0]">GTX3:TX_BYTECLK_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[1]">GTX3:DRP45[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_BYTECLK_CFG" title="GTX3:TX_BYTECLK_CFG[1]">GTX3:TX_BYTECLK_CFG[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[2]">GTX3:DRP45[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_BYTECLK_CFG" title="GTX3:TX_BYTECLK_CFG[2]">GTX3:TX_BYTECLK_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[3]">GTX3:DRP45[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_BYTECLK_CFG" title="GTX3:TX_BYTECLK_CFG[3]">GTX3:TX_BYTECLK_CFG[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[4]">GTX3:DRP45[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_BYTECLK_CFG" title="GTX3:TX_BYTECLK_CFG[4]">GTX3:TX_BYTECLK_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[5]">GTX3:DRP45[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_BYTECLK_CFG" title="GTX3:TX_BYTECLK_CFG[5]">GTX3:TX_BYTECLK_CFG[5]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[6]">GTX3:DRP45[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_USRCLK_CFG" title="GTX3:TX_USRCLK_CFG[0]">GTX3:TX_USRCLK_CFG[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[7]">GTX3:DRP45[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_USRCLK_CFG" title="GTX3:TX_USRCLK_CFG[1]">GTX3:TX_USRCLK_CFG[1]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[8]">GTX3:DRP45[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_USRCLK_CFG" title="GTX3:TX_USRCLK_CFG[2]">GTX3:TX_USRCLK_CFG[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[9]">GTX3:DRP45[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_USRCLK_CFG" title="GTX3:TX_USRCLK_CFG[3]">GTX3:TX_USRCLK_CFG[3]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[10]">GTX3:DRP45[10]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_USRCLK_CFG" title="GTX3:TX_USRCLK_CFG[4]">GTX3:TX_USRCLK_CFG[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[11]">GTX3:DRP45[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_USRCLK_CFG" title="GTX3:TX_USRCLK_CFG[5]">GTX3:TX_USRCLK_CFG[5]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[12]">GTX3:DRP45[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[13]">GTX3:DRP45[13]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[14]">GTX3:DRP45[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP45" title="GTX3:DRP45[15]">GTX3:DRP45[15]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[0]">GTX3:DRP46[0]</a><br><a href="#bits-xc6v-GTX-GTX3:RXRECCLK_DLY" title="GTX3:RXRECCLK_DLY[0]">GTX3:RXRECCLK_DLY[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[1]">GTX3:DRP46[1]</a><br><a href="#bits-xc6v-GTX-GTX3:RXRECCLK_DLY" title="GTX3:RXRECCLK_DLY[1]">GTX3:RXRECCLK_DLY[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[2]">GTX3:DRP46[2]</a><br><a href="#bits-xc6v-GTX-GTX3:RXRECCLK_DLY" title="GTX3:RXRECCLK_DLY[2]">GTX3:RXRECCLK_DLY[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[3]">GTX3:DRP46[3]</a><br><a href="#bits-xc6v-GTX-GTX3:RXRECCLK_DLY" title="GTX3:RXRECCLK_DLY[3]">GTX3:RXRECCLK_DLY[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[4]">GTX3:DRP46[4]</a><br><a href="#bits-xc6v-GTX-GTX3:RXRECCLK_DLY" title="GTX3:RXRECCLK_DLY[4]">GTX3:RXRECCLK_DLY[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[5]">GTX3:DRP46[5]</a><br><a href="#bits-xc6v-GTX-GTX3:RXRECCLK_DLY" title="GTX3:RXRECCLK_DLY[5]">GTX3:RXRECCLK_DLY[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[6]">GTX3:DRP46[6]</a><br><a href="#bits-xc6v-GTX-GTX3:RXRECCLK_DLY" title="GTX3:RXRECCLK_DLY[6]">GTX3:RXRECCLK_DLY[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[7]">GTX3:DRP46[7]</a><br><a href="#bits-xc6v-GTX-GTX3:RXRECCLK_DLY" title="GTX3:RXRECCLK_DLY[7]">GTX3:RXRECCLK_DLY[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[8]">GTX3:DRP46[8]</a><br><a href="#bits-xc6v-GTX-GTX3:RXRECCLK_DLY" title="GTX3:RXRECCLK_DLY[8]">GTX3:RXRECCLK_DLY[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[9]">GTX3:DRP46[9]</a><br><a href="#bits-xc6v-GTX-GTX3:RXRECCLK_DLY" title="GTX3:RXRECCLK_DLY[9]">GTX3:RXRECCLK_DLY[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[10]">GTX3:DRP46[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[11]">GTX3:DRP46[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[12]">GTX3:DRP46[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[13]">GTX3:DRP46[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[14]">GTX3:DRP46[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP46" title="GTX3:DRP46[15]">GTX3:DRP46[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[0]">GTX3:DRP47[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TXOUTCLK_DLY" title="GTX3:TXOUTCLK_DLY[0]">GTX3:TXOUTCLK_DLY[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[1]">GTX3:DRP47[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TXOUTCLK_DLY" title="GTX3:TXOUTCLK_DLY[1]">GTX3:TXOUTCLK_DLY[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[2]">GTX3:DRP47[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TXOUTCLK_DLY" title="GTX3:TXOUTCLK_DLY[2]">GTX3:TXOUTCLK_DLY[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[3]">GTX3:DRP47[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TXOUTCLK_DLY" title="GTX3:TXOUTCLK_DLY[3]">GTX3:TXOUTCLK_DLY[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[4]">GTX3:DRP47[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TXOUTCLK_DLY" title="GTX3:TXOUTCLK_DLY[4]">GTX3:TXOUTCLK_DLY[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[5]">GTX3:DRP47[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TXOUTCLK_DLY" title="GTX3:TXOUTCLK_DLY[5]">GTX3:TXOUTCLK_DLY[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[6]">GTX3:DRP47[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TXOUTCLK_DLY" title="GTX3:TXOUTCLK_DLY[6]">GTX3:TXOUTCLK_DLY[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[7]">GTX3:DRP47[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TXOUTCLK_DLY" title="GTX3:TXOUTCLK_DLY[7]">GTX3:TXOUTCLK_DLY[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[8]">GTX3:DRP47[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TXOUTCLK_DLY" title="GTX3:TXOUTCLK_DLY[8]">GTX3:TXOUTCLK_DLY[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[9]">GTX3:DRP47[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TXOUTCLK_DLY" title="GTX3:TXOUTCLK_DLY[9]">GTX3:TXOUTCLK_DLY[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[10]">GTX3:DRP47[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[11]">GTX3:DRP47[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[12]">GTX3:DRP47[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[13]">GTX3:DRP47[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[14]">GTX3:DRP47[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP47" title="GTX3:DRP47[15]">GTX3:DRP47[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="31">GTX bittile 39</th></tr><tr><th rowspan="2">Row</th><th colspan="30">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th><th>28</th><th>29</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[0]">GTX3:DRP48[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[1]">GTX3:DRP48[1]</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[2]">GTX3:DRP48[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[3]">GTX3:DRP48[3]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[4]">GTX3:DRP48[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[5]">GTX3:DRP48[5]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[6]">GTX3:DRP48[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[7]">GTX3:DRP48[7]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[8]">GTX3:DRP48[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[9]">GTX3:DRP48[9]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[10]">GTX3:DRP48[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[11]">GTX3:DRP48[11]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[12]">GTX3:DRP48[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[13]">GTX3:DRP48[13]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[14]">GTX3:DRP48[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP48" title="GTX3:DRP48[15]">GTX3:DRP48[15]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[0]">GTX3:DRP49[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[1]">GTX3:DRP49[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[2]">GTX3:DRP49[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[3]">GTX3:DRP49[3]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[4]">GTX3:DRP49[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[5]">GTX3:DRP49[5]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[6]">GTX3:DRP49[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[7]">GTX3:DRP49[7]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[8]">GTX3:DRP49[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[9]">GTX3:DRP49[9]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[10]">GTX3:DRP49[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[11]">GTX3:DRP49[11]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[12]">GTX3:DRP49[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[13]">GTX3:DRP49[13]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[14]">GTX3:DRP49[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP49" title="GTX3:DRP49[15]">GTX3:DRP49[15]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[0]">GTX3:DRP4A[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[1]">GTX3:DRP4A[1]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[2]">GTX3:DRP4A[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[3]">GTX3:DRP4A[3]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[4]">GTX3:DRP4A[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[5]">GTX3:DRP4A[5]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[6]">GTX3:DRP4A[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[7]">GTX3:DRP4A[7]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[8]">GTX3:DRP4A[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[9]">GTX3:DRP4A[9]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[10]">GTX3:DRP4A[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[11]">GTX3:DRP4A[11]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[12]">GTX3:DRP4A[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[13]">GTX3:DRP4A[13]</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[14]">GTX3:DRP4A[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4A" title="GTX3:DRP4A[15]">GTX3:DRP4A[15]</a></td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[0]">GTX3:DRP4B[0]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_MONSEL" title="GTX3:RX_DLYALIGN_MONSEL[0]">GTX3:RX_DLYALIGN_MONSEL[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[1]">GTX3:DRP4B[1]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_MONSEL" title="GTX3:RX_DLYALIGN_MONSEL[1]">GTX3:RX_DLYALIGN_MONSEL[1]</a></td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[2]">GTX3:DRP4B[2]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_MONSEL" title="GTX3:RX_DLYALIGN_MONSEL[2]">GTX3:RX_DLYALIGN_MONSEL[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[3]">GTX3:DRP4B[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_MONSEL" title="GTX3:TX_DLYALIGN_MONSEL[0]">GTX3:TX_DLYALIGN_MONSEL[0]</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[4]">GTX3:DRP4B[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_MONSEL" title="GTX3:TX_DLYALIGN_MONSEL[1]">GTX3:TX_DLYALIGN_MONSEL[1]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[5]">GTX3:DRP4B[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_MONSEL" title="GTX3:TX_DLYALIGN_MONSEL[2]">GTX3:TX_DLYALIGN_MONSEL[2]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[6]">GTX3:DRP4B[6]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_EDGESET" title="GTX3:RX_DLYALIGN_EDGESET[0]">GTX3:RX_DLYALIGN_EDGESET[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[7]">GTX3:DRP4B[7]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_EDGESET" title="GTX3:RX_DLYALIGN_EDGESET[1]">GTX3:RX_DLYALIGN_EDGESET[1]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[8]">GTX3:DRP4B[8]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_EDGESET" title="GTX3:RX_DLYALIGN_EDGESET[2]">GTX3:RX_DLYALIGN_EDGESET[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[9]">GTX3:DRP4B[9]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_EDGESET" title="GTX3:RX_DLYALIGN_EDGESET[3]">GTX3:RX_DLYALIGN_EDGESET[3]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[10]">GTX3:DRP4B[10]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_EDGESET" title="GTX3:RX_DLYALIGN_EDGESET[4]">GTX3:RX_DLYALIGN_EDGESET[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[11]">GTX3:DRP4B[11]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[12]">GTX3:DRP4B[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[13]">GTX3:DRP4B[13]</a></td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[14]">GTX3:DRP4B[14]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_EN_REALIGN_RESET_BUF2" title="GTX3:RX_EN_REALIGN_RESET_BUF2">GTX3:RX_EN_REALIGN_RESET_BUF2</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4B" title="GTX3:DRP4B[15]">GTX3:DRP4B[15]</a></td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[0]">GTX3:DRP4C[0]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_CTRINC" title="GTX3:TX_DLYALIGN_CTRINC[0]">GTX3:TX_DLYALIGN_CTRINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[1]">GTX3:DRP4C[1]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_CTRINC" title="GTX3:TX_DLYALIGN_CTRINC[1]">GTX3:TX_DLYALIGN_CTRINC[1]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[2]">GTX3:DRP4C[2]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_CTRINC" title="GTX3:TX_DLYALIGN_CTRINC[2]">GTX3:TX_DLYALIGN_CTRINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[3]">GTX3:DRP4C[3]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_CTRINC" title="GTX3:TX_DLYALIGN_CTRINC[3]">GTX3:TX_DLYALIGN_CTRINC[3]</a></td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[4]">GTX3:DRP4C[4]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_LPFINC" title="GTX3:TX_DLYALIGN_LPFINC[0]">GTX3:TX_DLYALIGN_LPFINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[5]">GTX3:DRP4C[5]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_LPFINC" title="GTX3:TX_DLYALIGN_LPFINC[1]">GTX3:TX_DLYALIGN_LPFINC[1]</a></td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[6]">GTX3:DRP4C[6]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_LPFINC" title="GTX3:TX_DLYALIGN_LPFINC[2]">GTX3:TX_DLYALIGN_LPFINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[7]">GTX3:DRP4C[7]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_LPFINC" title="GTX3:TX_DLYALIGN_LPFINC[3]">GTX3:TX_DLYALIGN_LPFINC[3]</a></td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[8]">GTX3:DRP4C[8]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_OVRDSETTING" title="GTX3:TX_DLYALIGN_OVRDSETTING[0]">GTX3:TX_DLYALIGN_OVRDSETTING[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[9]">GTX3:DRP4C[9]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_OVRDSETTING" title="GTX3:TX_DLYALIGN_OVRDSETTING[1]">GTX3:TX_DLYALIGN_OVRDSETTING[1]</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[10]">GTX3:DRP4C[10]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_OVRDSETTING" title="GTX3:TX_DLYALIGN_OVRDSETTING[2]">GTX3:TX_DLYALIGN_OVRDSETTING[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[11]">GTX3:DRP4C[11]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_OVRDSETTING" title="GTX3:TX_DLYALIGN_OVRDSETTING[3]">GTX3:TX_DLYALIGN_OVRDSETTING[3]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[12]">GTX3:DRP4C[12]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_OVRDSETTING" title="GTX3:TX_DLYALIGN_OVRDSETTING[4]">GTX3:TX_DLYALIGN_OVRDSETTING[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[13]">GTX3:DRP4C[13]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_OVRDSETTING" title="GTX3:TX_DLYALIGN_OVRDSETTING[5]">GTX3:TX_DLYALIGN_OVRDSETTING[5]</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[14]">GTX3:DRP4C[14]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_OVRDSETTING" title="GTX3:TX_DLYALIGN_OVRDSETTING[6]">GTX3:TX_DLYALIGN_OVRDSETTING[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4C" title="GTX3:DRP4C[15]">GTX3:DRP4C[15]</a><br><a href="#bits-xc6v-GTX-GTX3:TX_DLYALIGN_OVRDSETTING" title="GTX3:TX_DLYALIGN_OVRDSETTING[7]">GTX3:TX_DLYALIGN_OVRDSETTING[7]</a></td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[0]">GTX3:DRP4D[0]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_CTRINC" title="GTX3:RX_DLYALIGN_CTRINC[0]">GTX3:RX_DLYALIGN_CTRINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[1]">GTX3:DRP4D[1]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_CTRINC" title="GTX3:RX_DLYALIGN_CTRINC[1]">GTX3:RX_DLYALIGN_CTRINC[1]</a></td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[2]">GTX3:DRP4D[2]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_CTRINC" title="GTX3:RX_DLYALIGN_CTRINC[2]">GTX3:RX_DLYALIGN_CTRINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[3]">GTX3:DRP4D[3]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_CTRINC" title="GTX3:RX_DLYALIGN_CTRINC[3]">GTX3:RX_DLYALIGN_CTRINC[3]</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[4]">GTX3:DRP4D[4]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_LPFINC" title="GTX3:RX_DLYALIGN_LPFINC[0]">GTX3:RX_DLYALIGN_LPFINC[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[5]">GTX3:DRP4D[5]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_LPFINC" title="GTX3:RX_DLYALIGN_LPFINC[1]">GTX3:RX_DLYALIGN_LPFINC[1]</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[6]">GTX3:DRP4D[6]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_LPFINC" title="GTX3:RX_DLYALIGN_LPFINC[2]">GTX3:RX_DLYALIGN_LPFINC[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[7]">GTX3:DRP4D[7]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_LPFINC" title="GTX3:RX_DLYALIGN_LPFINC[3]">GTX3:RX_DLYALIGN_LPFINC[3]</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[8]">GTX3:DRP4D[8]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_OVRDSETTING" title="GTX3:RX_DLYALIGN_OVRDSETTING[0]">GTX3:RX_DLYALIGN_OVRDSETTING[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[9]">GTX3:DRP4D[9]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_OVRDSETTING" title="GTX3:RX_DLYALIGN_OVRDSETTING[1]">GTX3:RX_DLYALIGN_OVRDSETTING[1]</a></td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[10]">GTX3:DRP4D[10]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_OVRDSETTING" title="GTX3:RX_DLYALIGN_OVRDSETTING[2]">GTX3:RX_DLYALIGN_OVRDSETTING[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[11]">GTX3:DRP4D[11]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_OVRDSETTING" title="GTX3:RX_DLYALIGN_OVRDSETTING[3]">GTX3:RX_DLYALIGN_OVRDSETTING[3]</a></td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[12]">GTX3:DRP4D[12]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_OVRDSETTING" title="GTX3:RX_DLYALIGN_OVRDSETTING[4]">GTX3:RX_DLYALIGN_OVRDSETTING[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[13]">GTX3:DRP4D[13]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_OVRDSETTING" title="GTX3:RX_DLYALIGN_OVRDSETTING[5]">GTX3:RX_DLYALIGN_OVRDSETTING[5]</a></td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[14]">GTX3:DRP4D[14]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_OVRDSETTING" title="GTX3:RX_DLYALIGN_OVRDSETTING[6]">GTX3:RX_DLYALIGN_OVRDSETTING[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4D" title="GTX3:DRP4D[15]">GTX3:DRP4D[15]</a><br><a href="#bits-xc6v-GTX-GTX3:RX_DLYALIGN_OVRDSETTING" title="GTX3:RX_DLYALIGN_OVRDSETTING[7]">GTX3:RX_DLYALIGN_OVRDSETTING[7]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[0]">GTX3:DRP4E[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[1]">GTX3:DRP4E[1]</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[2]">GTX3:DRP4E[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[3]">GTX3:DRP4E[3]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[4]">GTX3:DRP4E[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[5]">GTX3:DRP4E[5]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[6]">GTX3:DRP4E[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[7]">GTX3:DRP4E[7]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[8]">GTX3:DRP4E[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[9]">GTX3:DRP4E[9]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[10]">GTX3:DRP4E[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[11]">GTX3:DRP4E[11]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[12]">GTX3:DRP4E[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[13]">GTX3:DRP4E[13]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[14]">GTX3:DRP4E[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4E" title="GTX3:DRP4E[15]">GTX3:DRP4E[15]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[0]">GTX3:DRP4F[0]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[1]">GTX3:DRP4F[1]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[2]">GTX3:DRP4F[2]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[3]">GTX3:DRP4F[3]</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[4]">GTX3:DRP4F[4]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[5]">GTX3:DRP4F[5]</a></td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[6]">GTX3:DRP4F[6]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[7]">GTX3:DRP4F[7]</a></td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[8]">GTX3:DRP4F[8]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[9]">GTX3:DRP4F[9]</a></td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[10]">GTX3:DRP4F[10]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[11]">GTX3:DRP4F[11]</a></td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[12]">GTX3:DRP4F[12]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[13]">GTX3:DRP4F[13]</a></td></tr>
+<tr><td>63</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[14]">GTX3:DRP4F[14]</a></td><td><a href="#bits-xc6v-GTX-GTX3:DRP4F" title="GTX3:DRP4F[15]">GTX3:DRP4F[15]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th colspan="27">GTX bittile 40</th></tr><tr><th rowspan="2">Row</th><th colspan="26">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc6v-GTX-HCLK_GTX:DRPMASK_S" title="HCLK_GTX:DRPMASK_S">HCLK_GTX:DRPMASK_S</a></td><td><a href="#bits-xc6v-GTX-HCLK_GTX:DRPMASK_N" title="HCLK_GTX:DRPMASK_N">HCLK_GTX:DRPMASK_N</a></td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:DRP00"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP01"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP02"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP03"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP04"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP05"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP06"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP07"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP08"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP09"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP0A"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP0B"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP0C"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP0D"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP0E"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP0F"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP10"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP11"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP12"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP13"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP14"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP15"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP16"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP17"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP18"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP19"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP1A"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP1B"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP1C"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP1D"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP1E"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP1F"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP20"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP21"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP22"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP23"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP24"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP25"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP26"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP27"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP28"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP29"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP2A"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP2B"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP2C"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP2D"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP2E"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP2F"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP30"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP31"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP32"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP33"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP34"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP35"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP36"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP37"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP38"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP39"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP3A"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP3B"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP3C"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP3D"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP3E"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP3F"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP40"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP41"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP42"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP43"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP44"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP45"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP46"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP47"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP48"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP49"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP4A"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP4B"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP4C"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP4D"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP4E"></div>
+<div id="bits-xc6v-GTX-GTX0:DRP4F"></div>
+<div id="bits-xc6v-GTX-GTX0:RXUSRCLK_DLY"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP00"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP01"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP02"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP03"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP04"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP05"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP06"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP07"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP08"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP09"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP0A"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP0B"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP0C"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP0D"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP0E"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP0F"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP10"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP11"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP12"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP13"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP14"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP15"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP16"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP17"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP18"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP19"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP1A"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP1B"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP1C"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP1D"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP1E"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP1F"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP20"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP21"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP22"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP23"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP24"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP25"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP26"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP27"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP28"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP29"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP2A"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP2B"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP2C"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP2D"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP2E"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP2F"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP30"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP31"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP32"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP33"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP34"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP35"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP36"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP37"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP38"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP39"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP3A"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP3B"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP3C"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP3D"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP3E"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP3F"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP40"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP41"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP42"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP43"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP44"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP45"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP46"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP47"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP48"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP49"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP4A"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP4B"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP4C"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP4D"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP4E"></div>
+<div id="bits-xc6v-GTX-GTX1:DRP4F"></div>
+<div id="bits-xc6v-GTX-GTX1:RXUSRCLK_DLY"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP00"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP01"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP02"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP03"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP04"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP05"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP06"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP07"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP08"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP09"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP0A"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP0B"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP0C"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP0D"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP0E"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP0F"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP10"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP11"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP12"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP13"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP14"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP15"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP16"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP17"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP18"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP19"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP1A"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP1B"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP1C"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP1D"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP1E"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP1F"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP20"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP21"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP22"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP23"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP24"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP25"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP26"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP27"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP28"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP29"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP2A"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP2B"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP2C"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP2D"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP2E"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP2F"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP30"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP31"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP32"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP33"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP34"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP35"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP36"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP37"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP38"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP39"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP3A"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP3B"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP3C"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP3D"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP3E"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP3F"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP40"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP41"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP42"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP43"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP44"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP45"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP46"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP47"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP48"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP49"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP4A"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP4B"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP4C"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP4D"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP4E"></div>
+<div id="bits-xc6v-GTX-GTX2:DRP4F"></div>
+<div id="bits-xc6v-GTX-GTX2:RXUSRCLK_DLY"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP00"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP01"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP02"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP03"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP04"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP05"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP06"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP07"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP08"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP09"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP0A"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP0B"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP0C"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP0D"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP0E"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP0F"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP10"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP11"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP12"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP13"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP14"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP15"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP16"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP17"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP18"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP19"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP1A"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP1B"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP1C"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP1D"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP1E"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP1F"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP20"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP21"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP22"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP23"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP24"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP25"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP26"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP27"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP28"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP29"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP2A"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP2B"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP2C"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP2D"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP2E"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP2F"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP30"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP31"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP32"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP33"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP34"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP35"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP36"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP37"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP38"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP39"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP3A"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP3B"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP3C"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP3D"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP3E"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP3F"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP40"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP41"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP42"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP43"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP44"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP45"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP46"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP47"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP48"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP49"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP4A"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP4B"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP4C"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP4D"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP4E"></div>
+<div id="bits-xc6v-GTX-GTX3:DRP4F"></div>
+<div id="bits-xc6v-GTX-GTX3:RXUSRCLK_DLY"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:DRP00</th><th>[0, 29, 7]</th><th>[0, 28, 7]</th><th>[0, 29, 6]</th><th>[0, 28, 6]</th><th>[0, 29, 5]</th><th>[0, 28, 5]</th><th>[0, 29, 4]</th><th>[0, 28, 4]</th><th>[0, 29, 3]</th><th>[0, 28, 3]</th><th>[0, 29, 2]</th><th>[0, 28, 2]</th><th>[0, 29, 1]</th><th>[0, 28, 1]</th><th>[0, 29, 0]</th><th>[0, 28, 0]</th></tr>
+<tr><th>GTX0:DRP01</th><th>[0, 29, 15]</th><th>[0, 28, 15]</th><th>[0, 29, 14]</th><th>[0, 28, 14]</th><th>[0, 29, 13]</th><th>[0, 28, 13]</th><th>[0, 29, 12]</th><th>[0, 28, 12]</th><th>[0, 29, 11]</th><th>[0, 28, 11]</th><th>[0, 29, 10]</th><th>[0, 28, 10]</th><th>[0, 29, 9]</th><th>[0, 28, 9]</th><th>[0, 29, 8]</th><th>[0, 28, 8]</th></tr>
+<tr><th>GTX0:DRP02</th><th>[0, 29, 23]</th><th>[0, 28, 23]</th><th>[0, 29, 22]</th><th>[0, 28, 22]</th><th>[0, 29, 21]</th><th>[0, 28, 21]</th><th>[0, 29, 20]</th><th>[0, 28, 20]</th><th>[0, 29, 19]</th><th>[0, 28, 19]</th><th>[0, 29, 18]</th><th>[0, 28, 18]</th><th>[0, 29, 17]</th><th>[0, 28, 17]</th><th>[0, 29, 16]</th><th>[0, 28, 16]</th></tr>
+<tr><th>GTX0:DRP03</th><th>[0, 29, 31]</th><th>[0, 28, 31]</th><th>[0, 29, 30]</th><th>[0, 28, 30]</th><th>[0, 29, 29]</th><th>[0, 28, 29]</th><th>[0, 29, 28]</th><th>[0, 28, 28]</th><th>[0, 29, 27]</th><th>[0, 28, 27]</th><th>[0, 29, 26]</th><th>[0, 28, 26]</th><th>[0, 29, 25]</th><th>[0, 28, 25]</th><th>[0, 29, 24]</th><th>[0, 28, 24]</th></tr>
+<tr><th>GTX0:DRP04</th><th>[0, 29, 39]</th><th>[0, 28, 39]</th><th>[0, 29, 38]</th><th>[0, 28, 38]</th><th>[0, 29, 37]</th><th>[0, 28, 37]</th><th>[0, 29, 36]</th><th>[0, 28, 36]</th><th>[0, 29, 35]</th><th>[0, 28, 35]</th><th>[0, 29, 34]</th><th>[0, 28, 34]</th><th>[0, 29, 33]</th><th>[0, 28, 33]</th><th>[0, 29, 32]</th><th>[0, 28, 32]</th></tr>
+<tr><th>GTX0:DRP05</th><th>[0, 29, 47]</th><th>[0, 28, 47]</th><th>[0, 29, 46]</th><th>[0, 28, 46]</th><th>[0, 29, 45]</th><th>[0, 28, 45]</th><th>[0, 29, 44]</th><th>[0, 28, 44]</th><th>[0, 29, 43]</th><th>[0, 28, 43]</th><th>[0, 29, 42]</th><th>[0, 28, 42]</th><th>[0, 29, 41]</th><th>[0, 28, 41]</th><th>[0, 29, 40]</th><th>[0, 28, 40]</th></tr>
+<tr><th>GTX0:DRP06</th><th>[0, 29, 55]</th><th>[0, 28, 55]</th><th>[0, 29, 54]</th><th>[0, 28, 54]</th><th>[0, 29, 53]</th><th>[0, 28, 53]</th><th>[0, 29, 52]</th><th>[0, 28, 52]</th><th>[0, 29, 51]</th><th>[0, 28, 51]</th><th>[0, 29, 50]</th><th>[0, 28, 50]</th><th>[0, 29, 49]</th><th>[0, 28, 49]</th><th>[0, 29, 48]</th><th>[0, 28, 48]</th></tr>
+<tr><th>GTX0:DRP07</th><th>[0, 29, 63]</th><th>[0, 28, 63]</th><th>[0, 29, 62]</th><th>[0, 28, 62]</th><th>[0, 29, 61]</th><th>[0, 28, 61]</th><th>[0, 29, 60]</th><th>[0, 28, 60]</th><th>[0, 29, 59]</th><th>[0, 28, 59]</th><th>[0, 29, 58]</th><th>[0, 28, 58]</th><th>[0, 29, 57]</th><th>[0, 28, 57]</th><th>[0, 29, 56]</th><th>[0, 28, 56]</th></tr>
+<tr><th>GTX0:DRP08</th><th>[1, 29, 7]</th><th>[1, 28, 7]</th><th>[1, 29, 6]</th><th>[1, 28, 6]</th><th>[1, 29, 5]</th><th>[1, 28, 5]</th><th>[1, 29, 4]</th><th>[1, 28, 4]</th><th>[1, 29, 3]</th><th>[1, 28, 3]</th><th>[1, 29, 2]</th><th>[1, 28, 2]</th><th>[1, 29, 1]</th><th>[1, 28, 1]</th><th>[1, 29, 0]</th><th>[1, 28, 0]</th></tr>
+<tr><th>GTX0:DRP09</th><th>[1, 29, 15]</th><th>[1, 28, 15]</th><th>[1, 29, 14]</th><th>[1, 28, 14]</th><th>[1, 29, 13]</th><th>[1, 28, 13]</th><th>[1, 29, 12]</th><th>[1, 28, 12]</th><th>[1, 29, 11]</th><th>[1, 28, 11]</th><th>[1, 29, 10]</th><th>[1, 28, 10]</th><th>[1, 29, 9]</th><th>[1, 28, 9]</th><th>[1, 29, 8]</th><th>[1, 28, 8]</th></tr>
+<tr><th>GTX0:DRP0A</th><th>[1, 29, 23]</th><th>[1, 28, 23]</th><th>[1, 29, 22]</th><th>[1, 28, 22]</th><th>[1, 29, 21]</th><th>[1, 28, 21]</th><th>[1, 29, 20]</th><th>[1, 28, 20]</th><th>[1, 29, 19]</th><th>[1, 28, 19]</th><th>[1, 29, 18]</th><th>[1, 28, 18]</th><th>[1, 29, 17]</th><th>[1, 28, 17]</th><th>[1, 29, 16]</th><th>[1, 28, 16]</th></tr>
+<tr><th>GTX0:DRP0B</th><th>[1, 29, 31]</th><th>[1, 28, 31]</th><th>[1, 29, 30]</th><th>[1, 28, 30]</th><th>[1, 29, 29]</th><th>[1, 28, 29]</th><th>[1, 29, 28]</th><th>[1, 28, 28]</th><th>[1, 29, 27]</th><th>[1, 28, 27]</th><th>[1, 29, 26]</th><th>[1, 28, 26]</th><th>[1, 29, 25]</th><th>[1, 28, 25]</th><th>[1, 29, 24]</th><th>[1, 28, 24]</th></tr>
+<tr><th>GTX0:DRP0C</th><th>[1, 29, 39]</th><th>[1, 28, 39]</th><th>[1, 29, 38]</th><th>[1, 28, 38]</th><th>[1, 29, 37]</th><th>[1, 28, 37]</th><th>[1, 29, 36]</th><th>[1, 28, 36]</th><th>[1, 29, 35]</th><th>[1, 28, 35]</th><th>[1, 29, 34]</th><th>[1, 28, 34]</th><th>[1, 29, 33]</th><th>[1, 28, 33]</th><th>[1, 29, 32]</th><th>[1, 28, 32]</th></tr>
+<tr><th>GTX0:DRP0D</th><th>[1, 29, 47]</th><th>[1, 28, 47]</th><th>[1, 29, 46]</th><th>[1, 28, 46]</th><th>[1, 29, 45]</th><th>[1, 28, 45]</th><th>[1, 29, 44]</th><th>[1, 28, 44]</th><th>[1, 29, 43]</th><th>[1, 28, 43]</th><th>[1, 29, 42]</th><th>[1, 28, 42]</th><th>[1, 29, 41]</th><th>[1, 28, 41]</th><th>[1, 29, 40]</th><th>[1, 28, 40]</th></tr>
+<tr><th>GTX0:DRP0E</th><th>[1, 29, 55]</th><th>[1, 28, 55]</th><th>[1, 29, 54]</th><th>[1, 28, 54]</th><th>[1, 29, 53]</th><th>[1, 28, 53]</th><th>[1, 29, 52]</th><th>[1, 28, 52]</th><th>[1, 29, 51]</th><th>[1, 28, 51]</th><th>[1, 29, 50]</th><th>[1, 28, 50]</th><th>[1, 29, 49]</th><th>[1, 28, 49]</th><th>[1, 29, 48]</th><th>[1, 28, 48]</th></tr>
+<tr><th>GTX0:DRP0F</th><th>[1, 29, 63]</th><th>[1, 28, 63]</th><th>[1, 29, 62]</th><th>[1, 28, 62]</th><th>[1, 29, 61]</th><th>[1, 28, 61]</th><th>[1, 29, 60]</th><th>[1, 28, 60]</th><th>[1, 29, 59]</th><th>[1, 28, 59]</th><th>[1, 29, 58]</th><th>[1, 28, 58]</th><th>[1, 29, 57]</th><th>[1, 28, 57]</th><th>[1, 29, 56]</th><th>[1, 28, 56]</th></tr>
+<tr><th>GTX0:DRP10</th><th>[2, 29, 7]</th><th>[2, 28, 7]</th><th>[2, 29, 6]</th><th>[2, 28, 6]</th><th>[2, 29, 5]</th><th>[2, 28, 5]</th><th>[2, 29, 4]</th><th>[2, 28, 4]</th><th>[2, 29, 3]</th><th>[2, 28, 3]</th><th>[2, 29, 2]</th><th>[2, 28, 2]</th><th>[2, 29, 1]</th><th>[2, 28, 1]</th><th>[2, 29, 0]</th><th>[2, 28, 0]</th></tr>
+<tr><th>GTX0:DRP11</th><th>[2, 29, 15]</th><th>[2, 28, 15]</th><th>[2, 29, 14]</th><th>[2, 28, 14]</th><th>[2, 29, 13]</th><th>[2, 28, 13]</th><th>[2, 29, 12]</th><th>[2, 28, 12]</th><th>[2, 29, 11]</th><th>[2, 28, 11]</th><th>[2, 29, 10]</th><th>[2, 28, 10]</th><th>[2, 29, 9]</th><th>[2, 28, 9]</th><th>[2, 29, 8]</th><th>[2, 28, 8]</th></tr>
+<tr><th>GTX0:DRP12</th><th>[2, 29, 23]</th><th>[2, 28, 23]</th><th>[2, 29, 22]</th><th>[2, 28, 22]</th><th>[2, 29, 21]</th><th>[2, 28, 21]</th><th>[2, 29, 20]</th><th>[2, 28, 20]</th><th>[2, 29, 19]</th><th>[2, 28, 19]</th><th>[2, 29, 18]</th><th>[2, 28, 18]</th><th>[2, 29, 17]</th><th>[2, 28, 17]</th><th>[2, 29, 16]</th><th>[2, 28, 16]</th></tr>
+<tr><th>GTX0:DRP13</th><th>[2, 29, 31]</th><th>[2, 28, 31]</th><th>[2, 29, 30]</th><th>[2, 28, 30]</th><th>[2, 29, 29]</th><th>[2, 28, 29]</th><th>[2, 29, 28]</th><th>[2, 28, 28]</th><th>[2, 29, 27]</th><th>[2, 28, 27]</th><th>[2, 29, 26]</th><th>[2, 28, 26]</th><th>[2, 29, 25]</th><th>[2, 28, 25]</th><th>[2, 29, 24]</th><th>[2, 28, 24]</th></tr>
+<tr><th>GTX0:DRP14</th><th>[2, 29, 39]</th><th>[2, 28, 39]</th><th>[2, 29, 38]</th><th>[2, 28, 38]</th><th>[2, 29, 37]</th><th>[2, 28, 37]</th><th>[2, 29, 36]</th><th>[2, 28, 36]</th><th>[2, 29, 35]</th><th>[2, 28, 35]</th><th>[2, 29, 34]</th><th>[2, 28, 34]</th><th>[2, 29, 33]</th><th>[2, 28, 33]</th><th>[2, 29, 32]</th><th>[2, 28, 32]</th></tr>
+<tr><th>GTX0:DRP15</th><th>[2, 29, 47]</th><th>[2, 28, 47]</th><th>[2, 29, 46]</th><th>[2, 28, 46]</th><th>[2, 29, 45]</th><th>[2, 28, 45]</th><th>[2, 29, 44]</th><th>[2, 28, 44]</th><th>[2, 29, 43]</th><th>[2, 28, 43]</th><th>[2, 29, 42]</th><th>[2, 28, 42]</th><th>[2, 29, 41]</th><th>[2, 28, 41]</th><th>[2, 29, 40]</th><th>[2, 28, 40]</th></tr>
+<tr><th>GTX0:DRP16</th><th>[2, 29, 55]</th><th>[2, 28, 55]</th><th>[2, 29, 54]</th><th>[2, 28, 54]</th><th>[2, 29, 53]</th><th>[2, 28, 53]</th><th>[2, 29, 52]</th><th>[2, 28, 52]</th><th>[2, 29, 51]</th><th>[2, 28, 51]</th><th>[2, 29, 50]</th><th>[2, 28, 50]</th><th>[2, 29, 49]</th><th>[2, 28, 49]</th><th>[2, 29, 48]</th><th>[2, 28, 48]</th></tr>
+<tr><th>GTX0:DRP17</th><th>[2, 29, 63]</th><th>[2, 28, 63]</th><th>[2, 29, 62]</th><th>[2, 28, 62]</th><th>[2, 29, 61]</th><th>[2, 28, 61]</th><th>[2, 29, 60]</th><th>[2, 28, 60]</th><th>[2, 29, 59]</th><th>[2, 28, 59]</th><th>[2, 29, 58]</th><th>[2, 28, 58]</th><th>[2, 29, 57]</th><th>[2, 28, 57]</th><th>[2, 29, 56]</th><th>[2, 28, 56]</th></tr>
+<tr><th>GTX0:DRP18</th><th>[3, 29, 7]</th><th>[3, 28, 7]</th><th>[3, 29, 6]</th><th>[3, 28, 6]</th><th>[3, 29, 5]</th><th>[3, 28, 5]</th><th>[3, 29, 4]</th><th>[3, 28, 4]</th><th>[3, 29, 3]</th><th>[3, 28, 3]</th><th>[3, 29, 2]</th><th>[3, 28, 2]</th><th>[3, 29, 1]</th><th>[3, 28, 1]</th><th>[3, 29, 0]</th><th>[3, 28, 0]</th></tr>
+<tr><th>GTX0:DRP19</th><th>[3, 29, 15]</th><th>[3, 28, 15]</th><th>[3, 29, 14]</th><th>[3, 28, 14]</th><th>[3, 29, 13]</th><th>[3, 28, 13]</th><th>[3, 29, 12]</th><th>[3, 28, 12]</th><th>[3, 29, 11]</th><th>[3, 28, 11]</th><th>[3, 29, 10]</th><th>[3, 28, 10]</th><th>[3, 29, 9]</th><th>[3, 28, 9]</th><th>[3, 29, 8]</th><th>[3, 28, 8]</th></tr>
+<tr><th>GTX0:DRP1A</th><th>[3, 29, 23]</th><th>[3, 28, 23]</th><th>[3, 29, 22]</th><th>[3, 28, 22]</th><th>[3, 29, 21]</th><th>[3, 28, 21]</th><th>[3, 29, 20]</th><th>[3, 28, 20]</th><th>[3, 29, 19]</th><th>[3, 28, 19]</th><th>[3, 29, 18]</th><th>[3, 28, 18]</th><th>[3, 29, 17]</th><th>[3, 28, 17]</th><th>[3, 29, 16]</th><th>[3, 28, 16]</th></tr>
+<tr><th>GTX0:DRP1B</th><th>[3, 29, 31]</th><th>[3, 28, 31]</th><th>[3, 29, 30]</th><th>[3, 28, 30]</th><th>[3, 29, 29]</th><th>[3, 28, 29]</th><th>[3, 29, 28]</th><th>[3, 28, 28]</th><th>[3, 29, 27]</th><th>[3, 28, 27]</th><th>[3, 29, 26]</th><th>[3, 28, 26]</th><th>[3, 29, 25]</th><th>[3, 28, 25]</th><th>[3, 29, 24]</th><th>[3, 28, 24]</th></tr>
+<tr><th>GTX0:DRP1C</th><th>[3, 29, 39]</th><th>[3, 28, 39]</th><th>[3, 29, 38]</th><th>[3, 28, 38]</th><th>[3, 29, 37]</th><th>[3, 28, 37]</th><th>[3, 29, 36]</th><th>[3, 28, 36]</th><th>[3, 29, 35]</th><th>[3, 28, 35]</th><th>[3, 29, 34]</th><th>[3, 28, 34]</th><th>[3, 29, 33]</th><th>[3, 28, 33]</th><th>[3, 29, 32]</th><th>[3, 28, 32]</th></tr>
+<tr><th>GTX0:DRP1D</th><th>[3, 29, 47]</th><th>[3, 28, 47]</th><th>[3, 29, 46]</th><th>[3, 28, 46]</th><th>[3, 29, 45]</th><th>[3, 28, 45]</th><th>[3, 29, 44]</th><th>[3, 28, 44]</th><th>[3, 29, 43]</th><th>[3, 28, 43]</th><th>[3, 29, 42]</th><th>[3, 28, 42]</th><th>[3, 29, 41]</th><th>[3, 28, 41]</th><th>[3, 29, 40]</th><th>[3, 28, 40]</th></tr>
+<tr><th>GTX0:DRP1E</th><th>[3, 29, 55]</th><th>[3, 28, 55]</th><th>[3, 29, 54]</th><th>[3, 28, 54]</th><th>[3, 29, 53]</th><th>[3, 28, 53]</th><th>[3, 29, 52]</th><th>[3, 28, 52]</th><th>[3, 29, 51]</th><th>[3, 28, 51]</th><th>[3, 29, 50]</th><th>[3, 28, 50]</th><th>[3, 29, 49]</th><th>[3, 28, 49]</th><th>[3, 29, 48]</th><th>[3, 28, 48]</th></tr>
+<tr><th>GTX0:DRP1F</th><th>[3, 29, 63]</th><th>[3, 28, 63]</th><th>[3, 29, 62]</th><th>[3, 28, 62]</th><th>[3, 29, 61]</th><th>[3, 28, 61]</th><th>[3, 29, 60]</th><th>[3, 28, 60]</th><th>[3, 29, 59]</th><th>[3, 28, 59]</th><th>[3, 29, 58]</th><th>[3, 28, 58]</th><th>[3, 29, 57]</th><th>[3, 28, 57]</th><th>[3, 29, 56]</th><th>[3, 28, 56]</th></tr>
+<tr><th>GTX0:DRP20</th><th>[4, 29, 7]</th><th>[4, 28, 7]</th><th>[4, 29, 6]</th><th>[4, 28, 6]</th><th>[4, 29, 5]</th><th>[4, 28, 5]</th><th>[4, 29, 4]</th><th>[4, 28, 4]</th><th>[4, 29, 3]</th><th>[4, 28, 3]</th><th>[4, 29, 2]</th><th>[4, 28, 2]</th><th>[4, 29, 1]</th><th>[4, 28, 1]</th><th>[4, 29, 0]</th><th>[4, 28, 0]</th></tr>
+<tr><th>GTX0:DRP21</th><th>[4, 29, 15]</th><th>[4, 28, 15]</th><th>[4, 29, 14]</th><th>[4, 28, 14]</th><th>[4, 29, 13]</th><th>[4, 28, 13]</th><th>[4, 29, 12]</th><th>[4, 28, 12]</th><th>[4, 29, 11]</th><th>[4, 28, 11]</th><th>[4, 29, 10]</th><th>[4, 28, 10]</th><th>[4, 29, 9]</th><th>[4, 28, 9]</th><th>[4, 29, 8]</th><th>[4, 28, 8]</th></tr>
+<tr><th>GTX0:DRP22</th><th>[4, 29, 23]</th><th>[4, 28, 23]</th><th>[4, 29, 22]</th><th>[4, 28, 22]</th><th>[4, 29, 21]</th><th>[4, 28, 21]</th><th>[4, 29, 20]</th><th>[4, 28, 20]</th><th>[4, 29, 19]</th><th>[4, 28, 19]</th><th>[4, 29, 18]</th><th>[4, 28, 18]</th><th>[4, 29, 17]</th><th>[4, 28, 17]</th><th>[4, 29, 16]</th><th>[4, 28, 16]</th></tr>
+<tr><th>GTX0:DRP23</th><th>[4, 29, 31]</th><th>[4, 28, 31]</th><th>[4, 29, 30]</th><th>[4, 28, 30]</th><th>[4, 29, 29]</th><th>[4, 28, 29]</th><th>[4, 29, 28]</th><th>[4, 28, 28]</th><th>[4, 29, 27]</th><th>[4, 28, 27]</th><th>[4, 29, 26]</th><th>[4, 28, 26]</th><th>[4, 29, 25]</th><th>[4, 28, 25]</th><th>[4, 29, 24]</th><th>[4, 28, 24]</th></tr>
+<tr><th>GTX0:DRP24</th><th>[4, 29, 39]</th><th>[4, 28, 39]</th><th>[4, 29, 38]</th><th>[4, 28, 38]</th><th>[4, 29, 37]</th><th>[4, 28, 37]</th><th>[4, 29, 36]</th><th>[4, 28, 36]</th><th>[4, 29, 35]</th><th>[4, 28, 35]</th><th>[4, 29, 34]</th><th>[4, 28, 34]</th><th>[4, 29, 33]</th><th>[4, 28, 33]</th><th>[4, 29, 32]</th><th>[4, 28, 32]</th></tr>
+<tr><th>GTX0:DRP25</th><th>[4, 29, 47]</th><th>[4, 28, 47]</th><th>[4, 29, 46]</th><th>[4, 28, 46]</th><th>[4, 29, 45]</th><th>[4, 28, 45]</th><th>[4, 29, 44]</th><th>[4, 28, 44]</th><th>[4, 29, 43]</th><th>[4, 28, 43]</th><th>[4, 29, 42]</th><th>[4, 28, 42]</th><th>[4, 29, 41]</th><th>[4, 28, 41]</th><th>[4, 29, 40]</th><th>[4, 28, 40]</th></tr>
+<tr><th>GTX0:DRP26</th><th>[4, 29, 55]</th><th>[4, 28, 55]</th><th>[4, 29, 54]</th><th>[4, 28, 54]</th><th>[4, 29, 53]</th><th>[4, 28, 53]</th><th>[4, 29, 52]</th><th>[4, 28, 52]</th><th>[4, 29, 51]</th><th>[4, 28, 51]</th><th>[4, 29, 50]</th><th>[4, 28, 50]</th><th>[4, 29, 49]</th><th>[4, 28, 49]</th><th>[4, 29, 48]</th><th>[4, 28, 48]</th></tr>
+<tr><th>GTX0:DRP27</th><th>[4, 29, 63]</th><th>[4, 28, 63]</th><th>[4, 29, 62]</th><th>[4, 28, 62]</th><th>[4, 29, 61]</th><th>[4, 28, 61]</th><th>[4, 29, 60]</th><th>[4, 28, 60]</th><th>[4, 29, 59]</th><th>[4, 28, 59]</th><th>[4, 29, 58]</th><th>[4, 28, 58]</th><th>[4, 29, 57]</th><th>[4, 28, 57]</th><th>[4, 29, 56]</th><th>[4, 28, 56]</th></tr>
+<tr><th>GTX0:DRP28</th><th>[5, 29, 7]</th><th>[5, 28, 7]</th><th>[5, 29, 6]</th><th>[5, 28, 6]</th><th>[5, 29, 5]</th><th>[5, 28, 5]</th><th>[5, 29, 4]</th><th>[5, 28, 4]</th><th>[5, 29, 3]</th><th>[5, 28, 3]</th><th>[5, 29, 2]</th><th>[5, 28, 2]</th><th>[5, 29, 1]</th><th>[5, 28, 1]</th><th>[5, 29, 0]</th><th>[5, 28, 0]</th></tr>
+<tr><th>GTX0:DRP29</th><th>[5, 29, 15]</th><th>[5, 28, 15]</th><th>[5, 29, 14]</th><th>[5, 28, 14]</th><th>[5, 29, 13]</th><th>[5, 28, 13]</th><th>[5, 29, 12]</th><th>[5, 28, 12]</th><th>[5, 29, 11]</th><th>[5, 28, 11]</th><th>[5, 29, 10]</th><th>[5, 28, 10]</th><th>[5, 29, 9]</th><th>[5, 28, 9]</th><th>[5, 29, 8]</th><th>[5, 28, 8]</th></tr>
+<tr><th>GTX0:DRP2A</th><th>[5, 29, 23]</th><th>[5, 28, 23]</th><th>[5, 29, 22]</th><th>[5, 28, 22]</th><th>[5, 29, 21]</th><th>[5, 28, 21]</th><th>[5, 29, 20]</th><th>[5, 28, 20]</th><th>[5, 29, 19]</th><th>[5, 28, 19]</th><th>[5, 29, 18]</th><th>[5, 28, 18]</th><th>[5, 29, 17]</th><th>[5, 28, 17]</th><th>[5, 29, 16]</th><th>[5, 28, 16]</th></tr>
+<tr><th>GTX0:DRP2B</th><th>[5, 29, 31]</th><th>[5, 28, 31]</th><th>[5, 29, 30]</th><th>[5, 28, 30]</th><th>[5, 29, 29]</th><th>[5, 28, 29]</th><th>[5, 29, 28]</th><th>[5, 28, 28]</th><th>[5, 29, 27]</th><th>[5, 28, 27]</th><th>[5, 29, 26]</th><th>[5, 28, 26]</th><th>[5, 29, 25]</th><th>[5, 28, 25]</th><th>[5, 29, 24]</th><th>[5, 28, 24]</th></tr>
+<tr><th>GTX0:DRP2C</th><th>[5, 29, 39]</th><th>[5, 28, 39]</th><th>[5, 29, 38]</th><th>[5, 28, 38]</th><th>[5, 29, 37]</th><th>[5, 28, 37]</th><th>[5, 29, 36]</th><th>[5, 28, 36]</th><th>[5, 29, 35]</th><th>[5, 28, 35]</th><th>[5, 29, 34]</th><th>[5, 28, 34]</th><th>[5, 29, 33]</th><th>[5, 28, 33]</th><th>[5, 29, 32]</th><th>[5, 28, 32]</th></tr>
+<tr><th>GTX0:DRP2D</th><th>[5, 29, 47]</th><th>[5, 28, 47]</th><th>[5, 29, 46]</th><th>[5, 28, 46]</th><th>[5, 29, 45]</th><th>[5, 28, 45]</th><th>[5, 29, 44]</th><th>[5, 28, 44]</th><th>[5, 29, 43]</th><th>[5, 28, 43]</th><th>[5, 29, 42]</th><th>[5, 28, 42]</th><th>[5, 29, 41]</th><th>[5, 28, 41]</th><th>[5, 29, 40]</th><th>[5, 28, 40]</th></tr>
+<tr><th>GTX0:DRP2E</th><th>[5, 29, 55]</th><th>[5, 28, 55]</th><th>[5, 29, 54]</th><th>[5, 28, 54]</th><th>[5, 29, 53]</th><th>[5, 28, 53]</th><th>[5, 29, 52]</th><th>[5, 28, 52]</th><th>[5, 29, 51]</th><th>[5, 28, 51]</th><th>[5, 29, 50]</th><th>[5, 28, 50]</th><th>[5, 29, 49]</th><th>[5, 28, 49]</th><th>[5, 29, 48]</th><th>[5, 28, 48]</th></tr>
+<tr><th>GTX0:DRP2F</th><th>[5, 29, 63]</th><th>[5, 28, 63]</th><th>[5, 29, 62]</th><th>[5, 28, 62]</th><th>[5, 29, 61]</th><th>[5, 28, 61]</th><th>[5, 29, 60]</th><th>[5, 28, 60]</th><th>[5, 29, 59]</th><th>[5, 28, 59]</th><th>[5, 29, 58]</th><th>[5, 28, 58]</th><th>[5, 29, 57]</th><th>[5, 28, 57]</th><th>[5, 29, 56]</th><th>[5, 28, 56]</th></tr>
+<tr><th>GTX0:DRP30</th><th>[6, 29, 7]</th><th>[6, 28, 7]</th><th>[6, 29, 6]</th><th>[6, 28, 6]</th><th>[6, 29, 5]</th><th>[6, 28, 5]</th><th>[6, 29, 4]</th><th>[6, 28, 4]</th><th>[6, 29, 3]</th><th>[6, 28, 3]</th><th>[6, 29, 2]</th><th>[6, 28, 2]</th><th>[6, 29, 1]</th><th>[6, 28, 1]</th><th>[6, 29, 0]</th><th>[6, 28, 0]</th></tr>
+<tr><th>GTX0:DRP31</th><th>[6, 29, 15]</th><th>[6, 28, 15]</th><th>[6, 29, 14]</th><th>[6, 28, 14]</th><th>[6, 29, 13]</th><th>[6, 28, 13]</th><th>[6, 29, 12]</th><th>[6, 28, 12]</th><th>[6, 29, 11]</th><th>[6, 28, 11]</th><th>[6, 29, 10]</th><th>[6, 28, 10]</th><th>[6, 29, 9]</th><th>[6, 28, 9]</th><th>[6, 29, 8]</th><th>[6, 28, 8]</th></tr>
+<tr><th>GTX0:DRP32</th><th>[6, 29, 23]</th><th>[6, 28, 23]</th><th>[6, 29, 22]</th><th>[6, 28, 22]</th><th>[6, 29, 21]</th><th>[6, 28, 21]</th><th>[6, 29, 20]</th><th>[6, 28, 20]</th><th>[6, 29, 19]</th><th>[6, 28, 19]</th><th>[6, 29, 18]</th><th>[6, 28, 18]</th><th>[6, 29, 17]</th><th>[6, 28, 17]</th><th>[6, 29, 16]</th><th>[6, 28, 16]</th></tr>
+<tr><th>GTX0:DRP33</th><th>[6, 29, 31]</th><th>[6, 28, 31]</th><th>[6, 29, 30]</th><th>[6, 28, 30]</th><th>[6, 29, 29]</th><th>[6, 28, 29]</th><th>[6, 29, 28]</th><th>[6, 28, 28]</th><th>[6, 29, 27]</th><th>[6, 28, 27]</th><th>[6, 29, 26]</th><th>[6, 28, 26]</th><th>[6, 29, 25]</th><th>[6, 28, 25]</th><th>[6, 29, 24]</th><th>[6, 28, 24]</th></tr>
+<tr><th>GTX0:DRP34</th><th>[6, 29, 39]</th><th>[6, 28, 39]</th><th>[6, 29, 38]</th><th>[6, 28, 38]</th><th>[6, 29, 37]</th><th>[6, 28, 37]</th><th>[6, 29, 36]</th><th>[6, 28, 36]</th><th>[6, 29, 35]</th><th>[6, 28, 35]</th><th>[6, 29, 34]</th><th>[6, 28, 34]</th><th>[6, 29, 33]</th><th>[6, 28, 33]</th><th>[6, 29, 32]</th><th>[6, 28, 32]</th></tr>
+<tr><th>GTX0:DRP35</th><th>[6, 29, 47]</th><th>[6, 28, 47]</th><th>[6, 29, 46]</th><th>[6, 28, 46]</th><th>[6, 29, 45]</th><th>[6, 28, 45]</th><th>[6, 29, 44]</th><th>[6, 28, 44]</th><th>[6, 29, 43]</th><th>[6, 28, 43]</th><th>[6, 29, 42]</th><th>[6, 28, 42]</th><th>[6, 29, 41]</th><th>[6, 28, 41]</th><th>[6, 29, 40]</th><th>[6, 28, 40]</th></tr>
+<tr><th>GTX0:DRP36</th><th>[6, 29, 55]</th><th>[6, 28, 55]</th><th>[6, 29, 54]</th><th>[6, 28, 54]</th><th>[6, 29, 53]</th><th>[6, 28, 53]</th><th>[6, 29, 52]</th><th>[6, 28, 52]</th><th>[6, 29, 51]</th><th>[6, 28, 51]</th><th>[6, 29, 50]</th><th>[6, 28, 50]</th><th>[6, 29, 49]</th><th>[6, 28, 49]</th><th>[6, 29, 48]</th><th>[6, 28, 48]</th></tr>
+<tr><th>GTX0:DRP37</th><th>[6, 29, 63]</th><th>[6, 28, 63]</th><th>[6, 29, 62]</th><th>[6, 28, 62]</th><th>[6, 29, 61]</th><th>[6, 28, 61]</th><th>[6, 29, 60]</th><th>[6, 28, 60]</th><th>[6, 29, 59]</th><th>[6, 28, 59]</th><th>[6, 29, 58]</th><th>[6, 28, 58]</th><th>[6, 29, 57]</th><th>[6, 28, 57]</th><th>[6, 29, 56]</th><th>[6, 28, 56]</th></tr>
+<tr><th>GTX0:DRP38</th><th>[7, 29, 7]</th><th>[7, 28, 7]</th><th>[7, 29, 6]</th><th>[7, 28, 6]</th><th>[7, 29, 5]</th><th>[7, 28, 5]</th><th>[7, 29, 4]</th><th>[7, 28, 4]</th><th>[7, 29, 3]</th><th>[7, 28, 3]</th><th>[7, 29, 2]</th><th>[7, 28, 2]</th><th>[7, 29, 1]</th><th>[7, 28, 1]</th><th>[7, 29, 0]</th><th>[7, 28, 0]</th></tr>
+<tr><th>GTX0:DRP39</th><th>[7, 29, 15]</th><th>[7, 28, 15]</th><th>[7, 29, 14]</th><th>[7, 28, 14]</th><th>[7, 29, 13]</th><th>[7, 28, 13]</th><th>[7, 29, 12]</th><th>[7, 28, 12]</th><th>[7, 29, 11]</th><th>[7, 28, 11]</th><th>[7, 29, 10]</th><th>[7, 28, 10]</th><th>[7, 29, 9]</th><th>[7, 28, 9]</th><th>[7, 29, 8]</th><th>[7, 28, 8]</th></tr>
+<tr><th>GTX0:DRP3A</th><th>[7, 29, 23]</th><th>[7, 28, 23]</th><th>[7, 29, 22]</th><th>[7, 28, 22]</th><th>[7, 29, 21]</th><th>[7, 28, 21]</th><th>[7, 29, 20]</th><th>[7, 28, 20]</th><th>[7, 29, 19]</th><th>[7, 28, 19]</th><th>[7, 29, 18]</th><th>[7, 28, 18]</th><th>[7, 29, 17]</th><th>[7, 28, 17]</th><th>[7, 29, 16]</th><th>[7, 28, 16]</th></tr>
+<tr><th>GTX0:DRP3B</th><th>[7, 29, 31]</th><th>[7, 28, 31]</th><th>[7, 29, 30]</th><th>[7, 28, 30]</th><th>[7, 29, 29]</th><th>[7, 28, 29]</th><th>[7, 29, 28]</th><th>[7, 28, 28]</th><th>[7, 29, 27]</th><th>[7, 28, 27]</th><th>[7, 29, 26]</th><th>[7, 28, 26]</th><th>[7, 29, 25]</th><th>[7, 28, 25]</th><th>[7, 29, 24]</th><th>[7, 28, 24]</th></tr>
+<tr><th>GTX0:DRP3C</th><th>[7, 29, 39]</th><th>[7, 28, 39]</th><th>[7, 29, 38]</th><th>[7, 28, 38]</th><th>[7, 29, 37]</th><th>[7, 28, 37]</th><th>[7, 29, 36]</th><th>[7, 28, 36]</th><th>[7, 29, 35]</th><th>[7, 28, 35]</th><th>[7, 29, 34]</th><th>[7, 28, 34]</th><th>[7, 29, 33]</th><th>[7, 28, 33]</th><th>[7, 29, 32]</th><th>[7, 28, 32]</th></tr>
+<tr><th>GTX0:DRP3D</th><th>[7, 29, 47]</th><th>[7, 28, 47]</th><th>[7, 29, 46]</th><th>[7, 28, 46]</th><th>[7, 29, 45]</th><th>[7, 28, 45]</th><th>[7, 29, 44]</th><th>[7, 28, 44]</th><th>[7, 29, 43]</th><th>[7, 28, 43]</th><th>[7, 29, 42]</th><th>[7, 28, 42]</th><th>[7, 29, 41]</th><th>[7, 28, 41]</th><th>[7, 29, 40]</th><th>[7, 28, 40]</th></tr>
+<tr><th>GTX0:DRP3E</th><th>[7, 29, 55]</th><th>[7, 28, 55]</th><th>[7, 29, 54]</th><th>[7, 28, 54]</th><th>[7, 29, 53]</th><th>[7, 28, 53]</th><th>[7, 29, 52]</th><th>[7, 28, 52]</th><th>[7, 29, 51]</th><th>[7, 28, 51]</th><th>[7, 29, 50]</th><th>[7, 28, 50]</th><th>[7, 29, 49]</th><th>[7, 28, 49]</th><th>[7, 29, 48]</th><th>[7, 28, 48]</th></tr>
+<tr><th>GTX0:DRP3F</th><th>[7, 29, 63]</th><th>[7, 28, 63]</th><th>[7, 29, 62]</th><th>[7, 28, 62]</th><th>[7, 29, 61]</th><th>[7, 28, 61]</th><th>[7, 29, 60]</th><th>[7, 28, 60]</th><th>[7, 29, 59]</th><th>[7, 28, 59]</th><th>[7, 29, 58]</th><th>[7, 28, 58]</th><th>[7, 29, 57]</th><th>[7, 28, 57]</th><th>[7, 29, 56]</th><th>[7, 28, 56]</th></tr>
+<tr><th>GTX0:DRP40</th><th>[8, 29, 7]</th><th>[8, 28, 7]</th><th>[8, 29, 6]</th><th>[8, 28, 6]</th><th>[8, 29, 5]</th><th>[8, 28, 5]</th><th>[8, 29, 4]</th><th>[8, 28, 4]</th><th>[8, 29, 3]</th><th>[8, 28, 3]</th><th>[8, 29, 2]</th><th>[8, 28, 2]</th><th>[8, 29, 1]</th><th>[8, 28, 1]</th><th>[8, 29, 0]</th><th>[8, 28, 0]</th></tr>
+<tr><th>GTX0:DRP41</th><th>[8, 29, 15]</th><th>[8, 28, 15]</th><th>[8, 29, 14]</th><th>[8, 28, 14]</th><th>[8, 29, 13]</th><th>[8, 28, 13]</th><th>[8, 29, 12]</th><th>[8, 28, 12]</th><th>[8, 29, 11]</th><th>[8, 28, 11]</th><th>[8, 29, 10]</th><th>[8, 28, 10]</th><th>[8, 29, 9]</th><th>[8, 28, 9]</th><th>[8, 29, 8]</th><th>[8, 28, 8]</th></tr>
+<tr><th>GTX0:DRP42</th><th>[8, 29, 23]</th><th>[8, 28, 23]</th><th>[8, 29, 22]</th><th>[8, 28, 22]</th><th>[8, 29, 21]</th><th>[8, 28, 21]</th><th>[8, 29, 20]</th><th>[8, 28, 20]</th><th>[8, 29, 19]</th><th>[8, 28, 19]</th><th>[8, 29, 18]</th><th>[8, 28, 18]</th><th>[8, 29, 17]</th><th>[8, 28, 17]</th><th>[8, 29, 16]</th><th>[8, 28, 16]</th></tr>
+<tr><th>GTX0:DRP43</th><th>[8, 29, 31]</th><th>[8, 28, 31]</th><th>[8, 29, 30]</th><th>[8, 28, 30]</th><th>[8, 29, 29]</th><th>[8, 28, 29]</th><th>[8, 29, 28]</th><th>[8, 28, 28]</th><th>[8, 29, 27]</th><th>[8, 28, 27]</th><th>[8, 29, 26]</th><th>[8, 28, 26]</th><th>[8, 29, 25]</th><th>[8, 28, 25]</th><th>[8, 29, 24]</th><th>[8, 28, 24]</th></tr>
+<tr><th>GTX0:DRP44</th><th>[8, 29, 39]</th><th>[8, 28, 39]</th><th>[8, 29, 38]</th><th>[8, 28, 38]</th><th>[8, 29, 37]</th><th>[8, 28, 37]</th><th>[8, 29, 36]</th><th>[8, 28, 36]</th><th>[8, 29, 35]</th><th>[8, 28, 35]</th><th>[8, 29, 34]</th><th>[8, 28, 34]</th><th>[8, 29, 33]</th><th>[8, 28, 33]</th><th>[8, 29, 32]</th><th>[8, 28, 32]</th></tr>
+<tr><th>GTX0:DRP45</th><th>[8, 29, 47]</th><th>[8, 28, 47]</th><th>[8, 29, 46]</th><th>[8, 28, 46]</th><th>[8, 29, 45]</th><th>[8, 28, 45]</th><th>[8, 29, 44]</th><th>[8, 28, 44]</th><th>[8, 29, 43]</th><th>[8, 28, 43]</th><th>[8, 29, 42]</th><th>[8, 28, 42]</th><th>[8, 29, 41]</th><th>[8, 28, 41]</th><th>[8, 29, 40]</th><th>[8, 28, 40]</th></tr>
+<tr><th>GTX0:DRP46</th><th>[8, 29, 55]</th><th>[8, 28, 55]</th><th>[8, 29, 54]</th><th>[8, 28, 54]</th><th>[8, 29, 53]</th><th>[8, 28, 53]</th><th>[8, 29, 52]</th><th>[8, 28, 52]</th><th>[8, 29, 51]</th><th>[8, 28, 51]</th><th>[8, 29, 50]</th><th>[8, 28, 50]</th><th>[8, 29, 49]</th><th>[8, 28, 49]</th><th>[8, 29, 48]</th><th>[8, 28, 48]</th></tr>
+<tr><th>GTX0:DRP47</th><th>[8, 29, 63]</th><th>[8, 28, 63]</th><th>[8, 29, 62]</th><th>[8, 28, 62]</th><th>[8, 29, 61]</th><th>[8, 28, 61]</th><th>[8, 29, 60]</th><th>[8, 28, 60]</th><th>[8, 29, 59]</th><th>[8, 28, 59]</th><th>[8, 29, 58]</th><th>[8, 28, 58]</th><th>[8, 29, 57]</th><th>[8, 28, 57]</th><th>[8, 29, 56]</th><th>[8, 28, 56]</th></tr>
+<tr><th>GTX0:DRP48</th><th>[9, 29, 7]</th><th>[9, 28, 7]</th><th>[9, 29, 6]</th><th>[9, 28, 6]</th><th>[9, 29, 5]</th><th>[9, 28, 5]</th><th>[9, 29, 4]</th><th>[9, 28, 4]</th><th>[9, 29, 3]</th><th>[9, 28, 3]</th><th>[9, 29, 2]</th><th>[9, 28, 2]</th><th>[9, 29, 1]</th><th>[9, 28, 1]</th><th>[9, 29, 0]</th><th>[9, 28, 0]</th></tr>
+<tr><th>GTX0:DRP49</th><th>[9, 29, 15]</th><th>[9, 28, 15]</th><th>[9, 29, 14]</th><th>[9, 28, 14]</th><th>[9, 29, 13]</th><th>[9, 28, 13]</th><th>[9, 29, 12]</th><th>[9, 28, 12]</th><th>[9, 29, 11]</th><th>[9, 28, 11]</th><th>[9, 29, 10]</th><th>[9, 28, 10]</th><th>[9, 29, 9]</th><th>[9, 28, 9]</th><th>[9, 29, 8]</th><th>[9, 28, 8]</th></tr>
+<tr><th>GTX0:DRP4A</th><th>[9, 29, 23]</th><th>[9, 28, 23]</th><th>[9, 29, 22]</th><th>[9, 28, 22]</th><th>[9, 29, 21]</th><th>[9, 28, 21]</th><th>[9, 29, 20]</th><th>[9, 28, 20]</th><th>[9, 29, 19]</th><th>[9, 28, 19]</th><th>[9, 29, 18]</th><th>[9, 28, 18]</th><th>[9, 29, 17]</th><th>[9, 28, 17]</th><th>[9, 29, 16]</th><th>[9, 28, 16]</th></tr>
+<tr><th>GTX0:DRP4B</th><th>[9, 29, 31]</th><th>[9, 28, 31]</th><th>[9, 29, 30]</th><th>[9, 28, 30]</th><th>[9, 29, 29]</th><th>[9, 28, 29]</th><th>[9, 29, 28]</th><th>[9, 28, 28]</th><th>[9, 29, 27]</th><th>[9, 28, 27]</th><th>[9, 29, 26]</th><th>[9, 28, 26]</th><th>[9, 29, 25]</th><th>[9, 28, 25]</th><th>[9, 29, 24]</th><th>[9, 28, 24]</th></tr>
+<tr><th>GTX0:DRP4C</th><th>[9, 29, 39]</th><th>[9, 28, 39]</th><th>[9, 29, 38]</th><th>[9, 28, 38]</th><th>[9, 29, 37]</th><th>[9, 28, 37]</th><th>[9, 29, 36]</th><th>[9, 28, 36]</th><th>[9, 29, 35]</th><th>[9, 28, 35]</th><th>[9, 29, 34]</th><th>[9, 28, 34]</th><th>[9, 29, 33]</th><th>[9, 28, 33]</th><th>[9, 29, 32]</th><th>[9, 28, 32]</th></tr>
+<tr><th>GTX0:DRP4D</th><th>[9, 29, 47]</th><th>[9, 28, 47]</th><th>[9, 29, 46]</th><th>[9, 28, 46]</th><th>[9, 29, 45]</th><th>[9, 28, 45]</th><th>[9, 29, 44]</th><th>[9, 28, 44]</th><th>[9, 29, 43]</th><th>[9, 28, 43]</th><th>[9, 29, 42]</th><th>[9, 28, 42]</th><th>[9, 29, 41]</th><th>[9, 28, 41]</th><th>[9, 29, 40]</th><th>[9, 28, 40]</th></tr>
+<tr><th>GTX0:DRP4E</th><th>[9, 29, 55]</th><th>[9, 28, 55]</th><th>[9, 29, 54]</th><th>[9, 28, 54]</th><th>[9, 29, 53]</th><th>[9, 28, 53]</th><th>[9, 29, 52]</th><th>[9, 28, 52]</th><th>[9, 29, 51]</th><th>[9, 28, 51]</th><th>[9, 29, 50]</th><th>[9, 28, 50]</th><th>[9, 29, 49]</th><th>[9, 28, 49]</th><th>[9, 29, 48]</th><th>[9, 28, 48]</th></tr>
+<tr><th>GTX0:DRP4F</th><th>[9, 29, 63]</th><th>[9, 28, 63]</th><th>[9, 29, 62]</th><th>[9, 28, 62]</th><th>[9, 29, 61]</th><th>[9, 28, 61]</th><th>[9, 29, 60]</th><th>[9, 28, 60]</th><th>[9, 29, 59]</th><th>[9, 28, 59]</th><th>[9, 29, 58]</th><th>[9, 28, 58]</th><th>[9, 29, 57]</th><th>[9, 28, 57]</th><th>[9, 29, 56]</th><th>[9, 28, 56]</th></tr>
+<tr><th>GTX0:RXUSRCLK_DLY</th><th>[0, 29, 23]</th><th>[0, 28, 23]</th><th>[0, 29, 22]</th><th>[0, 28, 22]</th><th>[0, 29, 21]</th><th>[0, 28, 21]</th><th>[0, 29, 20]</th><th>[0, 28, 20]</th><th>[0, 29, 19]</th><th>[0, 28, 19]</th><th>[0, 29, 18]</th><th>[0, 28, 18]</th><th>[0, 29, 17]</th><th>[0, 28, 17]</th><th>[0, 29, 16]</th><th>[0, 28, 16]</th></tr>
+<tr><th>GTX1:DRP00</th><th>[10, 29, 7]</th><th>[10, 28, 7]</th><th>[10, 29, 6]</th><th>[10, 28, 6]</th><th>[10, 29, 5]</th><th>[10, 28, 5]</th><th>[10, 29, 4]</th><th>[10, 28, 4]</th><th>[10, 29, 3]</th><th>[10, 28, 3]</th><th>[10, 29, 2]</th><th>[10, 28, 2]</th><th>[10, 29, 1]</th><th>[10, 28, 1]</th><th>[10, 29, 0]</th><th>[10, 28, 0]</th></tr>
+<tr><th>GTX1:DRP01</th><th>[10, 29, 15]</th><th>[10, 28, 15]</th><th>[10, 29, 14]</th><th>[10, 28, 14]</th><th>[10, 29, 13]</th><th>[10, 28, 13]</th><th>[10, 29, 12]</th><th>[10, 28, 12]</th><th>[10, 29, 11]</th><th>[10, 28, 11]</th><th>[10, 29, 10]</th><th>[10, 28, 10]</th><th>[10, 29, 9]</th><th>[10, 28, 9]</th><th>[10, 29, 8]</th><th>[10, 28, 8]</th></tr>
+<tr><th>GTX1:DRP02</th><th>[10, 29, 23]</th><th>[10, 28, 23]</th><th>[10, 29, 22]</th><th>[10, 28, 22]</th><th>[10, 29, 21]</th><th>[10, 28, 21]</th><th>[10, 29, 20]</th><th>[10, 28, 20]</th><th>[10, 29, 19]</th><th>[10, 28, 19]</th><th>[10, 29, 18]</th><th>[10, 28, 18]</th><th>[10, 29, 17]</th><th>[10, 28, 17]</th><th>[10, 29, 16]</th><th>[10, 28, 16]</th></tr>
+<tr><th>GTX1:DRP03</th><th>[10, 29, 31]</th><th>[10, 28, 31]</th><th>[10, 29, 30]</th><th>[10, 28, 30]</th><th>[10, 29, 29]</th><th>[10, 28, 29]</th><th>[10, 29, 28]</th><th>[10, 28, 28]</th><th>[10, 29, 27]</th><th>[10, 28, 27]</th><th>[10, 29, 26]</th><th>[10, 28, 26]</th><th>[10, 29, 25]</th><th>[10, 28, 25]</th><th>[10, 29, 24]</th><th>[10, 28, 24]</th></tr>
+<tr><th>GTX1:DRP04</th><th>[10, 29, 39]</th><th>[10, 28, 39]</th><th>[10, 29, 38]</th><th>[10, 28, 38]</th><th>[10, 29, 37]</th><th>[10, 28, 37]</th><th>[10, 29, 36]</th><th>[10, 28, 36]</th><th>[10, 29, 35]</th><th>[10, 28, 35]</th><th>[10, 29, 34]</th><th>[10, 28, 34]</th><th>[10, 29, 33]</th><th>[10, 28, 33]</th><th>[10, 29, 32]</th><th>[10, 28, 32]</th></tr>
+<tr><th>GTX1:DRP05</th><th>[10, 29, 47]</th><th>[10, 28, 47]</th><th>[10, 29, 46]</th><th>[10, 28, 46]</th><th>[10, 29, 45]</th><th>[10, 28, 45]</th><th>[10, 29, 44]</th><th>[10, 28, 44]</th><th>[10, 29, 43]</th><th>[10, 28, 43]</th><th>[10, 29, 42]</th><th>[10, 28, 42]</th><th>[10, 29, 41]</th><th>[10, 28, 41]</th><th>[10, 29, 40]</th><th>[10, 28, 40]</th></tr>
+<tr><th>GTX1:DRP06</th><th>[10, 29, 55]</th><th>[10, 28, 55]</th><th>[10, 29, 54]</th><th>[10, 28, 54]</th><th>[10, 29, 53]</th><th>[10, 28, 53]</th><th>[10, 29, 52]</th><th>[10, 28, 52]</th><th>[10, 29, 51]</th><th>[10, 28, 51]</th><th>[10, 29, 50]</th><th>[10, 28, 50]</th><th>[10, 29, 49]</th><th>[10, 28, 49]</th><th>[10, 29, 48]</th><th>[10, 28, 48]</th></tr>
+<tr><th>GTX1:DRP07</th><th>[10, 29, 63]</th><th>[10, 28, 63]</th><th>[10, 29, 62]</th><th>[10, 28, 62]</th><th>[10, 29, 61]</th><th>[10, 28, 61]</th><th>[10, 29, 60]</th><th>[10, 28, 60]</th><th>[10, 29, 59]</th><th>[10, 28, 59]</th><th>[10, 29, 58]</th><th>[10, 28, 58]</th><th>[10, 29, 57]</th><th>[10, 28, 57]</th><th>[10, 29, 56]</th><th>[10, 28, 56]</th></tr>
+<tr><th>GTX1:DRP08</th><th>[11, 29, 7]</th><th>[11, 28, 7]</th><th>[11, 29, 6]</th><th>[11, 28, 6]</th><th>[11, 29, 5]</th><th>[11, 28, 5]</th><th>[11, 29, 4]</th><th>[11, 28, 4]</th><th>[11, 29, 3]</th><th>[11, 28, 3]</th><th>[11, 29, 2]</th><th>[11, 28, 2]</th><th>[11, 29, 1]</th><th>[11, 28, 1]</th><th>[11, 29, 0]</th><th>[11, 28, 0]</th></tr>
+<tr><th>GTX1:DRP09</th><th>[11, 29, 15]</th><th>[11, 28, 15]</th><th>[11, 29, 14]</th><th>[11, 28, 14]</th><th>[11, 29, 13]</th><th>[11, 28, 13]</th><th>[11, 29, 12]</th><th>[11, 28, 12]</th><th>[11, 29, 11]</th><th>[11, 28, 11]</th><th>[11, 29, 10]</th><th>[11, 28, 10]</th><th>[11, 29, 9]</th><th>[11, 28, 9]</th><th>[11, 29, 8]</th><th>[11, 28, 8]</th></tr>
+<tr><th>GTX1:DRP0A</th><th>[11, 29, 23]</th><th>[11, 28, 23]</th><th>[11, 29, 22]</th><th>[11, 28, 22]</th><th>[11, 29, 21]</th><th>[11, 28, 21]</th><th>[11, 29, 20]</th><th>[11, 28, 20]</th><th>[11, 29, 19]</th><th>[11, 28, 19]</th><th>[11, 29, 18]</th><th>[11, 28, 18]</th><th>[11, 29, 17]</th><th>[11, 28, 17]</th><th>[11, 29, 16]</th><th>[11, 28, 16]</th></tr>
+<tr><th>GTX1:DRP0B</th><th>[11, 29, 31]</th><th>[11, 28, 31]</th><th>[11, 29, 30]</th><th>[11, 28, 30]</th><th>[11, 29, 29]</th><th>[11, 28, 29]</th><th>[11, 29, 28]</th><th>[11, 28, 28]</th><th>[11, 29, 27]</th><th>[11, 28, 27]</th><th>[11, 29, 26]</th><th>[11, 28, 26]</th><th>[11, 29, 25]</th><th>[11, 28, 25]</th><th>[11, 29, 24]</th><th>[11, 28, 24]</th></tr>
+<tr><th>GTX1:DRP0C</th><th>[11, 29, 39]</th><th>[11, 28, 39]</th><th>[11, 29, 38]</th><th>[11, 28, 38]</th><th>[11, 29, 37]</th><th>[11, 28, 37]</th><th>[11, 29, 36]</th><th>[11, 28, 36]</th><th>[11, 29, 35]</th><th>[11, 28, 35]</th><th>[11, 29, 34]</th><th>[11, 28, 34]</th><th>[11, 29, 33]</th><th>[11, 28, 33]</th><th>[11, 29, 32]</th><th>[11, 28, 32]</th></tr>
+<tr><th>GTX1:DRP0D</th><th>[11, 29, 47]</th><th>[11, 28, 47]</th><th>[11, 29, 46]</th><th>[11, 28, 46]</th><th>[11, 29, 45]</th><th>[11, 28, 45]</th><th>[11, 29, 44]</th><th>[11, 28, 44]</th><th>[11, 29, 43]</th><th>[11, 28, 43]</th><th>[11, 29, 42]</th><th>[11, 28, 42]</th><th>[11, 29, 41]</th><th>[11, 28, 41]</th><th>[11, 29, 40]</th><th>[11, 28, 40]</th></tr>
+<tr><th>GTX1:DRP0E</th><th>[11, 29, 55]</th><th>[11, 28, 55]</th><th>[11, 29, 54]</th><th>[11, 28, 54]</th><th>[11, 29, 53]</th><th>[11, 28, 53]</th><th>[11, 29, 52]</th><th>[11, 28, 52]</th><th>[11, 29, 51]</th><th>[11, 28, 51]</th><th>[11, 29, 50]</th><th>[11, 28, 50]</th><th>[11, 29, 49]</th><th>[11, 28, 49]</th><th>[11, 29, 48]</th><th>[11, 28, 48]</th></tr>
+<tr><th>GTX1:DRP0F</th><th>[11, 29, 63]</th><th>[11, 28, 63]</th><th>[11, 29, 62]</th><th>[11, 28, 62]</th><th>[11, 29, 61]</th><th>[11, 28, 61]</th><th>[11, 29, 60]</th><th>[11, 28, 60]</th><th>[11, 29, 59]</th><th>[11, 28, 59]</th><th>[11, 29, 58]</th><th>[11, 28, 58]</th><th>[11, 29, 57]</th><th>[11, 28, 57]</th><th>[11, 29, 56]</th><th>[11, 28, 56]</th></tr>
+<tr><th>GTX1:DRP10</th><th>[12, 29, 7]</th><th>[12, 28, 7]</th><th>[12, 29, 6]</th><th>[12, 28, 6]</th><th>[12, 29, 5]</th><th>[12, 28, 5]</th><th>[12, 29, 4]</th><th>[12, 28, 4]</th><th>[12, 29, 3]</th><th>[12, 28, 3]</th><th>[12, 29, 2]</th><th>[12, 28, 2]</th><th>[12, 29, 1]</th><th>[12, 28, 1]</th><th>[12, 29, 0]</th><th>[12, 28, 0]</th></tr>
+<tr><th>GTX1:DRP11</th><th>[12, 29, 15]</th><th>[12, 28, 15]</th><th>[12, 29, 14]</th><th>[12, 28, 14]</th><th>[12, 29, 13]</th><th>[12, 28, 13]</th><th>[12, 29, 12]</th><th>[12, 28, 12]</th><th>[12, 29, 11]</th><th>[12, 28, 11]</th><th>[12, 29, 10]</th><th>[12, 28, 10]</th><th>[12, 29, 9]</th><th>[12, 28, 9]</th><th>[12, 29, 8]</th><th>[12, 28, 8]</th></tr>
+<tr><th>GTX1:DRP12</th><th>[12, 29, 23]</th><th>[12, 28, 23]</th><th>[12, 29, 22]</th><th>[12, 28, 22]</th><th>[12, 29, 21]</th><th>[12, 28, 21]</th><th>[12, 29, 20]</th><th>[12, 28, 20]</th><th>[12, 29, 19]</th><th>[12, 28, 19]</th><th>[12, 29, 18]</th><th>[12, 28, 18]</th><th>[12, 29, 17]</th><th>[12, 28, 17]</th><th>[12, 29, 16]</th><th>[12, 28, 16]</th></tr>
+<tr><th>GTX1:DRP13</th><th>[12, 29, 31]</th><th>[12, 28, 31]</th><th>[12, 29, 30]</th><th>[12, 28, 30]</th><th>[12, 29, 29]</th><th>[12, 28, 29]</th><th>[12, 29, 28]</th><th>[12, 28, 28]</th><th>[12, 29, 27]</th><th>[12, 28, 27]</th><th>[12, 29, 26]</th><th>[12, 28, 26]</th><th>[12, 29, 25]</th><th>[12, 28, 25]</th><th>[12, 29, 24]</th><th>[12, 28, 24]</th></tr>
+<tr><th>GTX1:DRP14</th><th>[12, 29, 39]</th><th>[12, 28, 39]</th><th>[12, 29, 38]</th><th>[12, 28, 38]</th><th>[12, 29, 37]</th><th>[12, 28, 37]</th><th>[12, 29, 36]</th><th>[12, 28, 36]</th><th>[12, 29, 35]</th><th>[12, 28, 35]</th><th>[12, 29, 34]</th><th>[12, 28, 34]</th><th>[12, 29, 33]</th><th>[12, 28, 33]</th><th>[12, 29, 32]</th><th>[12, 28, 32]</th></tr>
+<tr><th>GTX1:DRP15</th><th>[12, 29, 47]</th><th>[12, 28, 47]</th><th>[12, 29, 46]</th><th>[12, 28, 46]</th><th>[12, 29, 45]</th><th>[12, 28, 45]</th><th>[12, 29, 44]</th><th>[12, 28, 44]</th><th>[12, 29, 43]</th><th>[12, 28, 43]</th><th>[12, 29, 42]</th><th>[12, 28, 42]</th><th>[12, 29, 41]</th><th>[12, 28, 41]</th><th>[12, 29, 40]</th><th>[12, 28, 40]</th></tr>
+<tr><th>GTX1:DRP16</th><th>[12, 29, 55]</th><th>[12, 28, 55]</th><th>[12, 29, 54]</th><th>[12, 28, 54]</th><th>[12, 29, 53]</th><th>[12, 28, 53]</th><th>[12, 29, 52]</th><th>[12, 28, 52]</th><th>[12, 29, 51]</th><th>[12, 28, 51]</th><th>[12, 29, 50]</th><th>[12, 28, 50]</th><th>[12, 29, 49]</th><th>[12, 28, 49]</th><th>[12, 29, 48]</th><th>[12, 28, 48]</th></tr>
+<tr><th>GTX1:DRP17</th><th>[12, 29, 63]</th><th>[12, 28, 63]</th><th>[12, 29, 62]</th><th>[12, 28, 62]</th><th>[12, 29, 61]</th><th>[12, 28, 61]</th><th>[12, 29, 60]</th><th>[12, 28, 60]</th><th>[12, 29, 59]</th><th>[12, 28, 59]</th><th>[12, 29, 58]</th><th>[12, 28, 58]</th><th>[12, 29, 57]</th><th>[12, 28, 57]</th><th>[12, 29, 56]</th><th>[12, 28, 56]</th></tr>
+<tr><th>GTX1:DRP18</th><th>[13, 29, 7]</th><th>[13, 28, 7]</th><th>[13, 29, 6]</th><th>[13, 28, 6]</th><th>[13, 29, 5]</th><th>[13, 28, 5]</th><th>[13, 29, 4]</th><th>[13, 28, 4]</th><th>[13, 29, 3]</th><th>[13, 28, 3]</th><th>[13, 29, 2]</th><th>[13, 28, 2]</th><th>[13, 29, 1]</th><th>[13, 28, 1]</th><th>[13, 29, 0]</th><th>[13, 28, 0]</th></tr>
+<tr><th>GTX1:DRP19</th><th>[13, 29, 15]</th><th>[13, 28, 15]</th><th>[13, 29, 14]</th><th>[13, 28, 14]</th><th>[13, 29, 13]</th><th>[13, 28, 13]</th><th>[13, 29, 12]</th><th>[13, 28, 12]</th><th>[13, 29, 11]</th><th>[13, 28, 11]</th><th>[13, 29, 10]</th><th>[13, 28, 10]</th><th>[13, 29, 9]</th><th>[13, 28, 9]</th><th>[13, 29, 8]</th><th>[13, 28, 8]</th></tr>
+<tr><th>GTX1:DRP1A</th><th>[13, 29, 23]</th><th>[13, 28, 23]</th><th>[13, 29, 22]</th><th>[13, 28, 22]</th><th>[13, 29, 21]</th><th>[13, 28, 21]</th><th>[13, 29, 20]</th><th>[13, 28, 20]</th><th>[13, 29, 19]</th><th>[13, 28, 19]</th><th>[13, 29, 18]</th><th>[13, 28, 18]</th><th>[13, 29, 17]</th><th>[13, 28, 17]</th><th>[13, 29, 16]</th><th>[13, 28, 16]</th></tr>
+<tr><th>GTX1:DRP1B</th><th>[13, 29, 31]</th><th>[13, 28, 31]</th><th>[13, 29, 30]</th><th>[13, 28, 30]</th><th>[13, 29, 29]</th><th>[13, 28, 29]</th><th>[13, 29, 28]</th><th>[13, 28, 28]</th><th>[13, 29, 27]</th><th>[13, 28, 27]</th><th>[13, 29, 26]</th><th>[13, 28, 26]</th><th>[13, 29, 25]</th><th>[13, 28, 25]</th><th>[13, 29, 24]</th><th>[13, 28, 24]</th></tr>
+<tr><th>GTX1:DRP1C</th><th>[13, 29, 39]</th><th>[13, 28, 39]</th><th>[13, 29, 38]</th><th>[13, 28, 38]</th><th>[13, 29, 37]</th><th>[13, 28, 37]</th><th>[13, 29, 36]</th><th>[13, 28, 36]</th><th>[13, 29, 35]</th><th>[13, 28, 35]</th><th>[13, 29, 34]</th><th>[13, 28, 34]</th><th>[13, 29, 33]</th><th>[13, 28, 33]</th><th>[13, 29, 32]</th><th>[13, 28, 32]</th></tr>
+<tr><th>GTX1:DRP1D</th><th>[13, 29, 47]</th><th>[13, 28, 47]</th><th>[13, 29, 46]</th><th>[13, 28, 46]</th><th>[13, 29, 45]</th><th>[13, 28, 45]</th><th>[13, 29, 44]</th><th>[13, 28, 44]</th><th>[13, 29, 43]</th><th>[13, 28, 43]</th><th>[13, 29, 42]</th><th>[13, 28, 42]</th><th>[13, 29, 41]</th><th>[13, 28, 41]</th><th>[13, 29, 40]</th><th>[13, 28, 40]</th></tr>
+<tr><th>GTX1:DRP1E</th><th>[13, 29, 55]</th><th>[13, 28, 55]</th><th>[13, 29, 54]</th><th>[13, 28, 54]</th><th>[13, 29, 53]</th><th>[13, 28, 53]</th><th>[13, 29, 52]</th><th>[13, 28, 52]</th><th>[13, 29, 51]</th><th>[13, 28, 51]</th><th>[13, 29, 50]</th><th>[13, 28, 50]</th><th>[13, 29, 49]</th><th>[13, 28, 49]</th><th>[13, 29, 48]</th><th>[13, 28, 48]</th></tr>
+<tr><th>GTX1:DRP1F</th><th>[13, 29, 63]</th><th>[13, 28, 63]</th><th>[13, 29, 62]</th><th>[13, 28, 62]</th><th>[13, 29, 61]</th><th>[13, 28, 61]</th><th>[13, 29, 60]</th><th>[13, 28, 60]</th><th>[13, 29, 59]</th><th>[13, 28, 59]</th><th>[13, 29, 58]</th><th>[13, 28, 58]</th><th>[13, 29, 57]</th><th>[13, 28, 57]</th><th>[13, 29, 56]</th><th>[13, 28, 56]</th></tr>
+<tr><th>GTX1:DRP20</th><th>[14, 29, 7]</th><th>[14, 28, 7]</th><th>[14, 29, 6]</th><th>[14, 28, 6]</th><th>[14, 29, 5]</th><th>[14, 28, 5]</th><th>[14, 29, 4]</th><th>[14, 28, 4]</th><th>[14, 29, 3]</th><th>[14, 28, 3]</th><th>[14, 29, 2]</th><th>[14, 28, 2]</th><th>[14, 29, 1]</th><th>[14, 28, 1]</th><th>[14, 29, 0]</th><th>[14, 28, 0]</th></tr>
+<tr><th>GTX1:DRP21</th><th>[14, 29, 15]</th><th>[14, 28, 15]</th><th>[14, 29, 14]</th><th>[14, 28, 14]</th><th>[14, 29, 13]</th><th>[14, 28, 13]</th><th>[14, 29, 12]</th><th>[14, 28, 12]</th><th>[14, 29, 11]</th><th>[14, 28, 11]</th><th>[14, 29, 10]</th><th>[14, 28, 10]</th><th>[14, 29, 9]</th><th>[14, 28, 9]</th><th>[14, 29, 8]</th><th>[14, 28, 8]</th></tr>
+<tr><th>GTX1:DRP22</th><th>[14, 29, 23]</th><th>[14, 28, 23]</th><th>[14, 29, 22]</th><th>[14, 28, 22]</th><th>[14, 29, 21]</th><th>[14, 28, 21]</th><th>[14, 29, 20]</th><th>[14, 28, 20]</th><th>[14, 29, 19]</th><th>[14, 28, 19]</th><th>[14, 29, 18]</th><th>[14, 28, 18]</th><th>[14, 29, 17]</th><th>[14, 28, 17]</th><th>[14, 29, 16]</th><th>[14, 28, 16]</th></tr>
+<tr><th>GTX1:DRP23</th><th>[14, 29, 31]</th><th>[14, 28, 31]</th><th>[14, 29, 30]</th><th>[14, 28, 30]</th><th>[14, 29, 29]</th><th>[14, 28, 29]</th><th>[14, 29, 28]</th><th>[14, 28, 28]</th><th>[14, 29, 27]</th><th>[14, 28, 27]</th><th>[14, 29, 26]</th><th>[14, 28, 26]</th><th>[14, 29, 25]</th><th>[14, 28, 25]</th><th>[14, 29, 24]</th><th>[14, 28, 24]</th></tr>
+<tr><th>GTX1:DRP24</th><th>[14, 29, 39]</th><th>[14, 28, 39]</th><th>[14, 29, 38]</th><th>[14, 28, 38]</th><th>[14, 29, 37]</th><th>[14, 28, 37]</th><th>[14, 29, 36]</th><th>[14, 28, 36]</th><th>[14, 29, 35]</th><th>[14, 28, 35]</th><th>[14, 29, 34]</th><th>[14, 28, 34]</th><th>[14, 29, 33]</th><th>[14, 28, 33]</th><th>[14, 29, 32]</th><th>[14, 28, 32]</th></tr>
+<tr><th>GTX1:DRP25</th><th>[14, 29, 47]</th><th>[14, 28, 47]</th><th>[14, 29, 46]</th><th>[14, 28, 46]</th><th>[14, 29, 45]</th><th>[14, 28, 45]</th><th>[14, 29, 44]</th><th>[14, 28, 44]</th><th>[14, 29, 43]</th><th>[14, 28, 43]</th><th>[14, 29, 42]</th><th>[14, 28, 42]</th><th>[14, 29, 41]</th><th>[14, 28, 41]</th><th>[14, 29, 40]</th><th>[14, 28, 40]</th></tr>
+<tr><th>GTX1:DRP26</th><th>[14, 29, 55]</th><th>[14, 28, 55]</th><th>[14, 29, 54]</th><th>[14, 28, 54]</th><th>[14, 29, 53]</th><th>[14, 28, 53]</th><th>[14, 29, 52]</th><th>[14, 28, 52]</th><th>[14, 29, 51]</th><th>[14, 28, 51]</th><th>[14, 29, 50]</th><th>[14, 28, 50]</th><th>[14, 29, 49]</th><th>[14, 28, 49]</th><th>[14, 29, 48]</th><th>[14, 28, 48]</th></tr>
+<tr><th>GTX1:DRP27</th><th>[14, 29, 63]</th><th>[14, 28, 63]</th><th>[14, 29, 62]</th><th>[14, 28, 62]</th><th>[14, 29, 61]</th><th>[14, 28, 61]</th><th>[14, 29, 60]</th><th>[14, 28, 60]</th><th>[14, 29, 59]</th><th>[14, 28, 59]</th><th>[14, 29, 58]</th><th>[14, 28, 58]</th><th>[14, 29, 57]</th><th>[14, 28, 57]</th><th>[14, 29, 56]</th><th>[14, 28, 56]</th></tr>
+<tr><th>GTX1:DRP28</th><th>[15, 29, 7]</th><th>[15, 28, 7]</th><th>[15, 29, 6]</th><th>[15, 28, 6]</th><th>[15, 29, 5]</th><th>[15, 28, 5]</th><th>[15, 29, 4]</th><th>[15, 28, 4]</th><th>[15, 29, 3]</th><th>[15, 28, 3]</th><th>[15, 29, 2]</th><th>[15, 28, 2]</th><th>[15, 29, 1]</th><th>[15, 28, 1]</th><th>[15, 29, 0]</th><th>[15, 28, 0]</th></tr>
+<tr><th>GTX1:DRP29</th><th>[15, 29, 15]</th><th>[15, 28, 15]</th><th>[15, 29, 14]</th><th>[15, 28, 14]</th><th>[15, 29, 13]</th><th>[15, 28, 13]</th><th>[15, 29, 12]</th><th>[15, 28, 12]</th><th>[15, 29, 11]</th><th>[15, 28, 11]</th><th>[15, 29, 10]</th><th>[15, 28, 10]</th><th>[15, 29, 9]</th><th>[15, 28, 9]</th><th>[15, 29, 8]</th><th>[15, 28, 8]</th></tr>
+<tr><th>GTX1:DRP2A</th><th>[15, 29, 23]</th><th>[15, 28, 23]</th><th>[15, 29, 22]</th><th>[15, 28, 22]</th><th>[15, 29, 21]</th><th>[15, 28, 21]</th><th>[15, 29, 20]</th><th>[15, 28, 20]</th><th>[15, 29, 19]</th><th>[15, 28, 19]</th><th>[15, 29, 18]</th><th>[15, 28, 18]</th><th>[15, 29, 17]</th><th>[15, 28, 17]</th><th>[15, 29, 16]</th><th>[15, 28, 16]</th></tr>
+<tr><th>GTX1:DRP2B</th><th>[15, 29, 31]</th><th>[15, 28, 31]</th><th>[15, 29, 30]</th><th>[15, 28, 30]</th><th>[15, 29, 29]</th><th>[15, 28, 29]</th><th>[15, 29, 28]</th><th>[15, 28, 28]</th><th>[15, 29, 27]</th><th>[15, 28, 27]</th><th>[15, 29, 26]</th><th>[15, 28, 26]</th><th>[15, 29, 25]</th><th>[15, 28, 25]</th><th>[15, 29, 24]</th><th>[15, 28, 24]</th></tr>
+<tr><th>GTX1:DRP2C</th><th>[15, 29, 39]</th><th>[15, 28, 39]</th><th>[15, 29, 38]</th><th>[15, 28, 38]</th><th>[15, 29, 37]</th><th>[15, 28, 37]</th><th>[15, 29, 36]</th><th>[15, 28, 36]</th><th>[15, 29, 35]</th><th>[15, 28, 35]</th><th>[15, 29, 34]</th><th>[15, 28, 34]</th><th>[15, 29, 33]</th><th>[15, 28, 33]</th><th>[15, 29, 32]</th><th>[15, 28, 32]</th></tr>
+<tr><th>GTX1:DRP2D</th><th>[15, 29, 47]</th><th>[15, 28, 47]</th><th>[15, 29, 46]</th><th>[15, 28, 46]</th><th>[15, 29, 45]</th><th>[15, 28, 45]</th><th>[15, 29, 44]</th><th>[15, 28, 44]</th><th>[15, 29, 43]</th><th>[15, 28, 43]</th><th>[15, 29, 42]</th><th>[15, 28, 42]</th><th>[15, 29, 41]</th><th>[15, 28, 41]</th><th>[15, 29, 40]</th><th>[15, 28, 40]</th></tr>
+<tr><th>GTX1:DRP2E</th><th>[15, 29, 55]</th><th>[15, 28, 55]</th><th>[15, 29, 54]</th><th>[15, 28, 54]</th><th>[15, 29, 53]</th><th>[15, 28, 53]</th><th>[15, 29, 52]</th><th>[15, 28, 52]</th><th>[15, 29, 51]</th><th>[15, 28, 51]</th><th>[15, 29, 50]</th><th>[15, 28, 50]</th><th>[15, 29, 49]</th><th>[15, 28, 49]</th><th>[15, 29, 48]</th><th>[15, 28, 48]</th></tr>
+<tr><th>GTX1:DRP2F</th><th>[15, 29, 63]</th><th>[15, 28, 63]</th><th>[15, 29, 62]</th><th>[15, 28, 62]</th><th>[15, 29, 61]</th><th>[15, 28, 61]</th><th>[15, 29, 60]</th><th>[15, 28, 60]</th><th>[15, 29, 59]</th><th>[15, 28, 59]</th><th>[15, 29, 58]</th><th>[15, 28, 58]</th><th>[15, 29, 57]</th><th>[15, 28, 57]</th><th>[15, 29, 56]</th><th>[15, 28, 56]</th></tr>
+<tr><th>GTX1:DRP30</th><th>[16, 29, 7]</th><th>[16, 28, 7]</th><th>[16, 29, 6]</th><th>[16, 28, 6]</th><th>[16, 29, 5]</th><th>[16, 28, 5]</th><th>[16, 29, 4]</th><th>[16, 28, 4]</th><th>[16, 29, 3]</th><th>[16, 28, 3]</th><th>[16, 29, 2]</th><th>[16, 28, 2]</th><th>[16, 29, 1]</th><th>[16, 28, 1]</th><th>[16, 29, 0]</th><th>[16, 28, 0]</th></tr>
+<tr><th>GTX1:DRP31</th><th>[16, 29, 15]</th><th>[16, 28, 15]</th><th>[16, 29, 14]</th><th>[16, 28, 14]</th><th>[16, 29, 13]</th><th>[16, 28, 13]</th><th>[16, 29, 12]</th><th>[16, 28, 12]</th><th>[16, 29, 11]</th><th>[16, 28, 11]</th><th>[16, 29, 10]</th><th>[16, 28, 10]</th><th>[16, 29, 9]</th><th>[16, 28, 9]</th><th>[16, 29, 8]</th><th>[16, 28, 8]</th></tr>
+<tr><th>GTX1:DRP32</th><th>[16, 29, 23]</th><th>[16, 28, 23]</th><th>[16, 29, 22]</th><th>[16, 28, 22]</th><th>[16, 29, 21]</th><th>[16, 28, 21]</th><th>[16, 29, 20]</th><th>[16, 28, 20]</th><th>[16, 29, 19]</th><th>[16, 28, 19]</th><th>[16, 29, 18]</th><th>[16, 28, 18]</th><th>[16, 29, 17]</th><th>[16, 28, 17]</th><th>[16, 29, 16]</th><th>[16, 28, 16]</th></tr>
+<tr><th>GTX1:DRP33</th><th>[16, 29, 31]</th><th>[16, 28, 31]</th><th>[16, 29, 30]</th><th>[16, 28, 30]</th><th>[16, 29, 29]</th><th>[16, 28, 29]</th><th>[16, 29, 28]</th><th>[16, 28, 28]</th><th>[16, 29, 27]</th><th>[16, 28, 27]</th><th>[16, 29, 26]</th><th>[16, 28, 26]</th><th>[16, 29, 25]</th><th>[16, 28, 25]</th><th>[16, 29, 24]</th><th>[16, 28, 24]</th></tr>
+<tr><th>GTX1:DRP34</th><th>[16, 29, 39]</th><th>[16, 28, 39]</th><th>[16, 29, 38]</th><th>[16, 28, 38]</th><th>[16, 29, 37]</th><th>[16, 28, 37]</th><th>[16, 29, 36]</th><th>[16, 28, 36]</th><th>[16, 29, 35]</th><th>[16, 28, 35]</th><th>[16, 29, 34]</th><th>[16, 28, 34]</th><th>[16, 29, 33]</th><th>[16, 28, 33]</th><th>[16, 29, 32]</th><th>[16, 28, 32]</th></tr>
+<tr><th>GTX1:DRP35</th><th>[16, 29, 47]</th><th>[16, 28, 47]</th><th>[16, 29, 46]</th><th>[16, 28, 46]</th><th>[16, 29, 45]</th><th>[16, 28, 45]</th><th>[16, 29, 44]</th><th>[16, 28, 44]</th><th>[16, 29, 43]</th><th>[16, 28, 43]</th><th>[16, 29, 42]</th><th>[16, 28, 42]</th><th>[16, 29, 41]</th><th>[16, 28, 41]</th><th>[16, 29, 40]</th><th>[16, 28, 40]</th></tr>
+<tr><th>GTX1:DRP36</th><th>[16, 29, 55]</th><th>[16, 28, 55]</th><th>[16, 29, 54]</th><th>[16, 28, 54]</th><th>[16, 29, 53]</th><th>[16, 28, 53]</th><th>[16, 29, 52]</th><th>[16, 28, 52]</th><th>[16, 29, 51]</th><th>[16, 28, 51]</th><th>[16, 29, 50]</th><th>[16, 28, 50]</th><th>[16, 29, 49]</th><th>[16, 28, 49]</th><th>[16, 29, 48]</th><th>[16, 28, 48]</th></tr>
+<tr><th>GTX1:DRP37</th><th>[16, 29, 63]</th><th>[16, 28, 63]</th><th>[16, 29, 62]</th><th>[16, 28, 62]</th><th>[16, 29, 61]</th><th>[16, 28, 61]</th><th>[16, 29, 60]</th><th>[16, 28, 60]</th><th>[16, 29, 59]</th><th>[16, 28, 59]</th><th>[16, 29, 58]</th><th>[16, 28, 58]</th><th>[16, 29, 57]</th><th>[16, 28, 57]</th><th>[16, 29, 56]</th><th>[16, 28, 56]</th></tr>
+<tr><th>GTX1:DRP38</th><th>[17, 29, 7]</th><th>[17, 28, 7]</th><th>[17, 29, 6]</th><th>[17, 28, 6]</th><th>[17, 29, 5]</th><th>[17, 28, 5]</th><th>[17, 29, 4]</th><th>[17, 28, 4]</th><th>[17, 29, 3]</th><th>[17, 28, 3]</th><th>[17, 29, 2]</th><th>[17, 28, 2]</th><th>[17, 29, 1]</th><th>[17, 28, 1]</th><th>[17, 29, 0]</th><th>[17, 28, 0]</th></tr>
+<tr><th>GTX1:DRP39</th><th>[17, 29, 15]</th><th>[17, 28, 15]</th><th>[17, 29, 14]</th><th>[17, 28, 14]</th><th>[17, 29, 13]</th><th>[17, 28, 13]</th><th>[17, 29, 12]</th><th>[17, 28, 12]</th><th>[17, 29, 11]</th><th>[17, 28, 11]</th><th>[17, 29, 10]</th><th>[17, 28, 10]</th><th>[17, 29, 9]</th><th>[17, 28, 9]</th><th>[17, 29, 8]</th><th>[17, 28, 8]</th></tr>
+<tr><th>GTX1:DRP3A</th><th>[17, 29, 23]</th><th>[17, 28, 23]</th><th>[17, 29, 22]</th><th>[17, 28, 22]</th><th>[17, 29, 21]</th><th>[17, 28, 21]</th><th>[17, 29, 20]</th><th>[17, 28, 20]</th><th>[17, 29, 19]</th><th>[17, 28, 19]</th><th>[17, 29, 18]</th><th>[17, 28, 18]</th><th>[17, 29, 17]</th><th>[17, 28, 17]</th><th>[17, 29, 16]</th><th>[17, 28, 16]</th></tr>
+<tr><th>GTX1:DRP3B</th><th>[17, 29, 31]</th><th>[17, 28, 31]</th><th>[17, 29, 30]</th><th>[17, 28, 30]</th><th>[17, 29, 29]</th><th>[17, 28, 29]</th><th>[17, 29, 28]</th><th>[17, 28, 28]</th><th>[17, 29, 27]</th><th>[17, 28, 27]</th><th>[17, 29, 26]</th><th>[17, 28, 26]</th><th>[17, 29, 25]</th><th>[17, 28, 25]</th><th>[17, 29, 24]</th><th>[17, 28, 24]</th></tr>
+<tr><th>GTX1:DRP3C</th><th>[17, 29, 39]</th><th>[17, 28, 39]</th><th>[17, 29, 38]</th><th>[17, 28, 38]</th><th>[17, 29, 37]</th><th>[17, 28, 37]</th><th>[17, 29, 36]</th><th>[17, 28, 36]</th><th>[17, 29, 35]</th><th>[17, 28, 35]</th><th>[17, 29, 34]</th><th>[17, 28, 34]</th><th>[17, 29, 33]</th><th>[17, 28, 33]</th><th>[17, 29, 32]</th><th>[17, 28, 32]</th></tr>
+<tr><th>GTX1:DRP3D</th><th>[17, 29, 47]</th><th>[17, 28, 47]</th><th>[17, 29, 46]</th><th>[17, 28, 46]</th><th>[17, 29, 45]</th><th>[17, 28, 45]</th><th>[17, 29, 44]</th><th>[17, 28, 44]</th><th>[17, 29, 43]</th><th>[17, 28, 43]</th><th>[17, 29, 42]</th><th>[17, 28, 42]</th><th>[17, 29, 41]</th><th>[17, 28, 41]</th><th>[17, 29, 40]</th><th>[17, 28, 40]</th></tr>
+<tr><th>GTX1:DRP3E</th><th>[17, 29, 55]</th><th>[17, 28, 55]</th><th>[17, 29, 54]</th><th>[17, 28, 54]</th><th>[17, 29, 53]</th><th>[17, 28, 53]</th><th>[17, 29, 52]</th><th>[17, 28, 52]</th><th>[17, 29, 51]</th><th>[17, 28, 51]</th><th>[17, 29, 50]</th><th>[17, 28, 50]</th><th>[17, 29, 49]</th><th>[17, 28, 49]</th><th>[17, 29, 48]</th><th>[17, 28, 48]</th></tr>
+<tr><th>GTX1:DRP3F</th><th>[17, 29, 63]</th><th>[17, 28, 63]</th><th>[17, 29, 62]</th><th>[17, 28, 62]</th><th>[17, 29, 61]</th><th>[17, 28, 61]</th><th>[17, 29, 60]</th><th>[17, 28, 60]</th><th>[17, 29, 59]</th><th>[17, 28, 59]</th><th>[17, 29, 58]</th><th>[17, 28, 58]</th><th>[17, 29, 57]</th><th>[17, 28, 57]</th><th>[17, 29, 56]</th><th>[17, 28, 56]</th></tr>
+<tr><th>GTX1:DRP40</th><th>[18, 29, 7]</th><th>[18, 28, 7]</th><th>[18, 29, 6]</th><th>[18, 28, 6]</th><th>[18, 29, 5]</th><th>[18, 28, 5]</th><th>[18, 29, 4]</th><th>[18, 28, 4]</th><th>[18, 29, 3]</th><th>[18, 28, 3]</th><th>[18, 29, 2]</th><th>[18, 28, 2]</th><th>[18, 29, 1]</th><th>[18, 28, 1]</th><th>[18, 29, 0]</th><th>[18, 28, 0]</th></tr>
+<tr><th>GTX1:DRP41</th><th>[18, 29, 15]</th><th>[18, 28, 15]</th><th>[18, 29, 14]</th><th>[18, 28, 14]</th><th>[18, 29, 13]</th><th>[18, 28, 13]</th><th>[18, 29, 12]</th><th>[18, 28, 12]</th><th>[18, 29, 11]</th><th>[18, 28, 11]</th><th>[18, 29, 10]</th><th>[18, 28, 10]</th><th>[18, 29, 9]</th><th>[18, 28, 9]</th><th>[18, 29, 8]</th><th>[18, 28, 8]</th></tr>
+<tr><th>GTX1:DRP42</th><th>[18, 29, 23]</th><th>[18, 28, 23]</th><th>[18, 29, 22]</th><th>[18, 28, 22]</th><th>[18, 29, 21]</th><th>[18, 28, 21]</th><th>[18, 29, 20]</th><th>[18, 28, 20]</th><th>[18, 29, 19]</th><th>[18, 28, 19]</th><th>[18, 29, 18]</th><th>[18, 28, 18]</th><th>[18, 29, 17]</th><th>[18, 28, 17]</th><th>[18, 29, 16]</th><th>[18, 28, 16]</th></tr>
+<tr><th>GTX1:DRP43</th><th>[18, 29, 31]</th><th>[18, 28, 31]</th><th>[18, 29, 30]</th><th>[18, 28, 30]</th><th>[18, 29, 29]</th><th>[18, 28, 29]</th><th>[18, 29, 28]</th><th>[18, 28, 28]</th><th>[18, 29, 27]</th><th>[18, 28, 27]</th><th>[18, 29, 26]</th><th>[18, 28, 26]</th><th>[18, 29, 25]</th><th>[18, 28, 25]</th><th>[18, 29, 24]</th><th>[18, 28, 24]</th></tr>
+<tr><th>GTX1:DRP44</th><th>[18, 29, 39]</th><th>[18, 28, 39]</th><th>[18, 29, 38]</th><th>[18, 28, 38]</th><th>[18, 29, 37]</th><th>[18, 28, 37]</th><th>[18, 29, 36]</th><th>[18, 28, 36]</th><th>[18, 29, 35]</th><th>[18, 28, 35]</th><th>[18, 29, 34]</th><th>[18, 28, 34]</th><th>[18, 29, 33]</th><th>[18, 28, 33]</th><th>[18, 29, 32]</th><th>[18, 28, 32]</th></tr>
+<tr><th>GTX1:DRP45</th><th>[18, 29, 47]</th><th>[18, 28, 47]</th><th>[18, 29, 46]</th><th>[18, 28, 46]</th><th>[18, 29, 45]</th><th>[18, 28, 45]</th><th>[18, 29, 44]</th><th>[18, 28, 44]</th><th>[18, 29, 43]</th><th>[18, 28, 43]</th><th>[18, 29, 42]</th><th>[18, 28, 42]</th><th>[18, 29, 41]</th><th>[18, 28, 41]</th><th>[18, 29, 40]</th><th>[18, 28, 40]</th></tr>
+<tr><th>GTX1:DRP46</th><th>[18, 29, 55]</th><th>[18, 28, 55]</th><th>[18, 29, 54]</th><th>[18, 28, 54]</th><th>[18, 29, 53]</th><th>[18, 28, 53]</th><th>[18, 29, 52]</th><th>[18, 28, 52]</th><th>[18, 29, 51]</th><th>[18, 28, 51]</th><th>[18, 29, 50]</th><th>[18, 28, 50]</th><th>[18, 29, 49]</th><th>[18, 28, 49]</th><th>[18, 29, 48]</th><th>[18, 28, 48]</th></tr>
+<tr><th>GTX1:DRP47</th><th>[18, 29, 63]</th><th>[18, 28, 63]</th><th>[18, 29, 62]</th><th>[18, 28, 62]</th><th>[18, 29, 61]</th><th>[18, 28, 61]</th><th>[18, 29, 60]</th><th>[18, 28, 60]</th><th>[18, 29, 59]</th><th>[18, 28, 59]</th><th>[18, 29, 58]</th><th>[18, 28, 58]</th><th>[18, 29, 57]</th><th>[18, 28, 57]</th><th>[18, 29, 56]</th><th>[18, 28, 56]</th></tr>
+<tr><th>GTX1:DRP48</th><th>[19, 29, 7]</th><th>[19, 28, 7]</th><th>[19, 29, 6]</th><th>[19, 28, 6]</th><th>[19, 29, 5]</th><th>[19, 28, 5]</th><th>[19, 29, 4]</th><th>[19, 28, 4]</th><th>[19, 29, 3]</th><th>[19, 28, 3]</th><th>[19, 29, 2]</th><th>[19, 28, 2]</th><th>[19, 29, 1]</th><th>[19, 28, 1]</th><th>[19, 29, 0]</th><th>[19, 28, 0]</th></tr>
+<tr><th>GTX1:DRP49</th><th>[19, 29, 15]</th><th>[19, 28, 15]</th><th>[19, 29, 14]</th><th>[19, 28, 14]</th><th>[19, 29, 13]</th><th>[19, 28, 13]</th><th>[19, 29, 12]</th><th>[19, 28, 12]</th><th>[19, 29, 11]</th><th>[19, 28, 11]</th><th>[19, 29, 10]</th><th>[19, 28, 10]</th><th>[19, 29, 9]</th><th>[19, 28, 9]</th><th>[19, 29, 8]</th><th>[19, 28, 8]</th></tr>
+<tr><th>GTX1:DRP4A</th><th>[19, 29, 23]</th><th>[19, 28, 23]</th><th>[19, 29, 22]</th><th>[19, 28, 22]</th><th>[19, 29, 21]</th><th>[19, 28, 21]</th><th>[19, 29, 20]</th><th>[19, 28, 20]</th><th>[19, 29, 19]</th><th>[19, 28, 19]</th><th>[19, 29, 18]</th><th>[19, 28, 18]</th><th>[19, 29, 17]</th><th>[19, 28, 17]</th><th>[19, 29, 16]</th><th>[19, 28, 16]</th></tr>
+<tr><th>GTX1:DRP4B</th><th>[19, 29, 31]</th><th>[19, 28, 31]</th><th>[19, 29, 30]</th><th>[19, 28, 30]</th><th>[19, 29, 29]</th><th>[19, 28, 29]</th><th>[19, 29, 28]</th><th>[19, 28, 28]</th><th>[19, 29, 27]</th><th>[19, 28, 27]</th><th>[19, 29, 26]</th><th>[19, 28, 26]</th><th>[19, 29, 25]</th><th>[19, 28, 25]</th><th>[19, 29, 24]</th><th>[19, 28, 24]</th></tr>
+<tr><th>GTX1:DRP4C</th><th>[19, 29, 39]</th><th>[19, 28, 39]</th><th>[19, 29, 38]</th><th>[19, 28, 38]</th><th>[19, 29, 37]</th><th>[19, 28, 37]</th><th>[19, 29, 36]</th><th>[19, 28, 36]</th><th>[19, 29, 35]</th><th>[19, 28, 35]</th><th>[19, 29, 34]</th><th>[19, 28, 34]</th><th>[19, 29, 33]</th><th>[19, 28, 33]</th><th>[19, 29, 32]</th><th>[19, 28, 32]</th></tr>
+<tr><th>GTX1:DRP4D</th><th>[19, 29, 47]</th><th>[19, 28, 47]</th><th>[19, 29, 46]</th><th>[19, 28, 46]</th><th>[19, 29, 45]</th><th>[19, 28, 45]</th><th>[19, 29, 44]</th><th>[19, 28, 44]</th><th>[19, 29, 43]</th><th>[19, 28, 43]</th><th>[19, 29, 42]</th><th>[19, 28, 42]</th><th>[19, 29, 41]</th><th>[19, 28, 41]</th><th>[19, 29, 40]</th><th>[19, 28, 40]</th></tr>
+<tr><th>GTX1:DRP4E</th><th>[19, 29, 55]</th><th>[19, 28, 55]</th><th>[19, 29, 54]</th><th>[19, 28, 54]</th><th>[19, 29, 53]</th><th>[19, 28, 53]</th><th>[19, 29, 52]</th><th>[19, 28, 52]</th><th>[19, 29, 51]</th><th>[19, 28, 51]</th><th>[19, 29, 50]</th><th>[19, 28, 50]</th><th>[19, 29, 49]</th><th>[19, 28, 49]</th><th>[19, 29, 48]</th><th>[19, 28, 48]</th></tr>
+<tr><th>GTX1:DRP4F</th><th>[19, 29, 63]</th><th>[19, 28, 63]</th><th>[19, 29, 62]</th><th>[19, 28, 62]</th><th>[19, 29, 61]</th><th>[19, 28, 61]</th><th>[19, 29, 60]</th><th>[19, 28, 60]</th><th>[19, 29, 59]</th><th>[19, 28, 59]</th><th>[19, 29, 58]</th><th>[19, 28, 58]</th><th>[19, 29, 57]</th><th>[19, 28, 57]</th><th>[19, 29, 56]</th><th>[19, 28, 56]</th></tr>
+<tr><th>GTX1:RXUSRCLK_DLY</th><th>[10, 29, 23]</th><th>[10, 28, 23]</th><th>[10, 29, 22]</th><th>[10, 28, 22]</th><th>[10, 29, 21]</th><th>[10, 28, 21]</th><th>[10, 29, 20]</th><th>[10, 28, 20]</th><th>[10, 29, 19]</th><th>[10, 28, 19]</th><th>[10, 29, 18]</th><th>[10, 28, 18]</th><th>[10, 29, 17]</th><th>[10, 28, 17]</th><th>[10, 29, 16]</th><th>[10, 28, 16]</th></tr>
+<tr><th>GTX2:DRP00</th><th>[20, 29, 7]</th><th>[20, 28, 7]</th><th>[20, 29, 6]</th><th>[20, 28, 6]</th><th>[20, 29, 5]</th><th>[20, 28, 5]</th><th>[20, 29, 4]</th><th>[20, 28, 4]</th><th>[20, 29, 3]</th><th>[20, 28, 3]</th><th>[20, 29, 2]</th><th>[20, 28, 2]</th><th>[20, 29, 1]</th><th>[20, 28, 1]</th><th>[20, 29, 0]</th><th>[20, 28, 0]</th></tr>
+<tr><th>GTX2:DRP01</th><th>[20, 29, 15]</th><th>[20, 28, 15]</th><th>[20, 29, 14]</th><th>[20, 28, 14]</th><th>[20, 29, 13]</th><th>[20, 28, 13]</th><th>[20, 29, 12]</th><th>[20, 28, 12]</th><th>[20, 29, 11]</th><th>[20, 28, 11]</th><th>[20, 29, 10]</th><th>[20, 28, 10]</th><th>[20, 29, 9]</th><th>[20, 28, 9]</th><th>[20, 29, 8]</th><th>[20, 28, 8]</th></tr>
+<tr><th>GTX2:DRP02</th><th>[20, 29, 23]</th><th>[20, 28, 23]</th><th>[20, 29, 22]</th><th>[20, 28, 22]</th><th>[20, 29, 21]</th><th>[20, 28, 21]</th><th>[20, 29, 20]</th><th>[20, 28, 20]</th><th>[20, 29, 19]</th><th>[20, 28, 19]</th><th>[20, 29, 18]</th><th>[20, 28, 18]</th><th>[20, 29, 17]</th><th>[20, 28, 17]</th><th>[20, 29, 16]</th><th>[20, 28, 16]</th></tr>
+<tr><th>GTX2:DRP03</th><th>[20, 29, 31]</th><th>[20, 28, 31]</th><th>[20, 29, 30]</th><th>[20, 28, 30]</th><th>[20, 29, 29]</th><th>[20, 28, 29]</th><th>[20, 29, 28]</th><th>[20, 28, 28]</th><th>[20, 29, 27]</th><th>[20, 28, 27]</th><th>[20, 29, 26]</th><th>[20, 28, 26]</th><th>[20, 29, 25]</th><th>[20, 28, 25]</th><th>[20, 29, 24]</th><th>[20, 28, 24]</th></tr>
+<tr><th>GTX2:DRP04</th><th>[20, 29, 39]</th><th>[20, 28, 39]</th><th>[20, 29, 38]</th><th>[20, 28, 38]</th><th>[20, 29, 37]</th><th>[20, 28, 37]</th><th>[20, 29, 36]</th><th>[20, 28, 36]</th><th>[20, 29, 35]</th><th>[20, 28, 35]</th><th>[20, 29, 34]</th><th>[20, 28, 34]</th><th>[20, 29, 33]</th><th>[20, 28, 33]</th><th>[20, 29, 32]</th><th>[20, 28, 32]</th></tr>
+<tr><th>GTX2:DRP05</th><th>[20, 29, 47]</th><th>[20, 28, 47]</th><th>[20, 29, 46]</th><th>[20, 28, 46]</th><th>[20, 29, 45]</th><th>[20, 28, 45]</th><th>[20, 29, 44]</th><th>[20, 28, 44]</th><th>[20, 29, 43]</th><th>[20, 28, 43]</th><th>[20, 29, 42]</th><th>[20, 28, 42]</th><th>[20, 29, 41]</th><th>[20, 28, 41]</th><th>[20, 29, 40]</th><th>[20, 28, 40]</th></tr>
+<tr><th>GTX2:DRP06</th><th>[20, 29, 55]</th><th>[20, 28, 55]</th><th>[20, 29, 54]</th><th>[20, 28, 54]</th><th>[20, 29, 53]</th><th>[20, 28, 53]</th><th>[20, 29, 52]</th><th>[20, 28, 52]</th><th>[20, 29, 51]</th><th>[20, 28, 51]</th><th>[20, 29, 50]</th><th>[20, 28, 50]</th><th>[20, 29, 49]</th><th>[20, 28, 49]</th><th>[20, 29, 48]</th><th>[20, 28, 48]</th></tr>
+<tr><th>GTX2:DRP07</th><th>[20, 29, 63]</th><th>[20, 28, 63]</th><th>[20, 29, 62]</th><th>[20, 28, 62]</th><th>[20, 29, 61]</th><th>[20, 28, 61]</th><th>[20, 29, 60]</th><th>[20, 28, 60]</th><th>[20, 29, 59]</th><th>[20, 28, 59]</th><th>[20, 29, 58]</th><th>[20, 28, 58]</th><th>[20, 29, 57]</th><th>[20, 28, 57]</th><th>[20, 29, 56]</th><th>[20, 28, 56]</th></tr>
+<tr><th>GTX2:DRP08</th><th>[21, 29, 7]</th><th>[21, 28, 7]</th><th>[21, 29, 6]</th><th>[21, 28, 6]</th><th>[21, 29, 5]</th><th>[21, 28, 5]</th><th>[21, 29, 4]</th><th>[21, 28, 4]</th><th>[21, 29, 3]</th><th>[21, 28, 3]</th><th>[21, 29, 2]</th><th>[21, 28, 2]</th><th>[21, 29, 1]</th><th>[21, 28, 1]</th><th>[21, 29, 0]</th><th>[21, 28, 0]</th></tr>
+<tr><th>GTX2:DRP09</th><th>[21, 29, 15]</th><th>[21, 28, 15]</th><th>[21, 29, 14]</th><th>[21, 28, 14]</th><th>[21, 29, 13]</th><th>[21, 28, 13]</th><th>[21, 29, 12]</th><th>[21, 28, 12]</th><th>[21, 29, 11]</th><th>[21, 28, 11]</th><th>[21, 29, 10]</th><th>[21, 28, 10]</th><th>[21, 29, 9]</th><th>[21, 28, 9]</th><th>[21, 29, 8]</th><th>[21, 28, 8]</th></tr>
+<tr><th>GTX2:DRP0A</th><th>[21, 29, 23]</th><th>[21, 28, 23]</th><th>[21, 29, 22]</th><th>[21, 28, 22]</th><th>[21, 29, 21]</th><th>[21, 28, 21]</th><th>[21, 29, 20]</th><th>[21, 28, 20]</th><th>[21, 29, 19]</th><th>[21, 28, 19]</th><th>[21, 29, 18]</th><th>[21, 28, 18]</th><th>[21, 29, 17]</th><th>[21, 28, 17]</th><th>[21, 29, 16]</th><th>[21, 28, 16]</th></tr>
+<tr><th>GTX2:DRP0B</th><th>[21, 29, 31]</th><th>[21, 28, 31]</th><th>[21, 29, 30]</th><th>[21, 28, 30]</th><th>[21, 29, 29]</th><th>[21, 28, 29]</th><th>[21, 29, 28]</th><th>[21, 28, 28]</th><th>[21, 29, 27]</th><th>[21, 28, 27]</th><th>[21, 29, 26]</th><th>[21, 28, 26]</th><th>[21, 29, 25]</th><th>[21, 28, 25]</th><th>[21, 29, 24]</th><th>[21, 28, 24]</th></tr>
+<tr><th>GTX2:DRP0C</th><th>[21, 29, 39]</th><th>[21, 28, 39]</th><th>[21, 29, 38]</th><th>[21, 28, 38]</th><th>[21, 29, 37]</th><th>[21, 28, 37]</th><th>[21, 29, 36]</th><th>[21, 28, 36]</th><th>[21, 29, 35]</th><th>[21, 28, 35]</th><th>[21, 29, 34]</th><th>[21, 28, 34]</th><th>[21, 29, 33]</th><th>[21, 28, 33]</th><th>[21, 29, 32]</th><th>[21, 28, 32]</th></tr>
+<tr><th>GTX2:DRP0D</th><th>[21, 29, 47]</th><th>[21, 28, 47]</th><th>[21, 29, 46]</th><th>[21, 28, 46]</th><th>[21, 29, 45]</th><th>[21, 28, 45]</th><th>[21, 29, 44]</th><th>[21, 28, 44]</th><th>[21, 29, 43]</th><th>[21, 28, 43]</th><th>[21, 29, 42]</th><th>[21, 28, 42]</th><th>[21, 29, 41]</th><th>[21, 28, 41]</th><th>[21, 29, 40]</th><th>[21, 28, 40]</th></tr>
+<tr><th>GTX2:DRP0E</th><th>[21, 29, 55]</th><th>[21, 28, 55]</th><th>[21, 29, 54]</th><th>[21, 28, 54]</th><th>[21, 29, 53]</th><th>[21, 28, 53]</th><th>[21, 29, 52]</th><th>[21, 28, 52]</th><th>[21, 29, 51]</th><th>[21, 28, 51]</th><th>[21, 29, 50]</th><th>[21, 28, 50]</th><th>[21, 29, 49]</th><th>[21, 28, 49]</th><th>[21, 29, 48]</th><th>[21, 28, 48]</th></tr>
+<tr><th>GTX2:DRP0F</th><th>[21, 29, 63]</th><th>[21, 28, 63]</th><th>[21, 29, 62]</th><th>[21, 28, 62]</th><th>[21, 29, 61]</th><th>[21, 28, 61]</th><th>[21, 29, 60]</th><th>[21, 28, 60]</th><th>[21, 29, 59]</th><th>[21, 28, 59]</th><th>[21, 29, 58]</th><th>[21, 28, 58]</th><th>[21, 29, 57]</th><th>[21, 28, 57]</th><th>[21, 29, 56]</th><th>[21, 28, 56]</th></tr>
+<tr><th>GTX2:DRP10</th><th>[22, 29, 7]</th><th>[22, 28, 7]</th><th>[22, 29, 6]</th><th>[22, 28, 6]</th><th>[22, 29, 5]</th><th>[22, 28, 5]</th><th>[22, 29, 4]</th><th>[22, 28, 4]</th><th>[22, 29, 3]</th><th>[22, 28, 3]</th><th>[22, 29, 2]</th><th>[22, 28, 2]</th><th>[22, 29, 1]</th><th>[22, 28, 1]</th><th>[22, 29, 0]</th><th>[22, 28, 0]</th></tr>
+<tr><th>GTX2:DRP11</th><th>[22, 29, 15]</th><th>[22, 28, 15]</th><th>[22, 29, 14]</th><th>[22, 28, 14]</th><th>[22, 29, 13]</th><th>[22, 28, 13]</th><th>[22, 29, 12]</th><th>[22, 28, 12]</th><th>[22, 29, 11]</th><th>[22, 28, 11]</th><th>[22, 29, 10]</th><th>[22, 28, 10]</th><th>[22, 29, 9]</th><th>[22, 28, 9]</th><th>[22, 29, 8]</th><th>[22, 28, 8]</th></tr>
+<tr><th>GTX2:DRP12</th><th>[22, 29, 23]</th><th>[22, 28, 23]</th><th>[22, 29, 22]</th><th>[22, 28, 22]</th><th>[22, 29, 21]</th><th>[22, 28, 21]</th><th>[22, 29, 20]</th><th>[22, 28, 20]</th><th>[22, 29, 19]</th><th>[22, 28, 19]</th><th>[22, 29, 18]</th><th>[22, 28, 18]</th><th>[22, 29, 17]</th><th>[22, 28, 17]</th><th>[22, 29, 16]</th><th>[22, 28, 16]</th></tr>
+<tr><th>GTX2:DRP13</th><th>[22, 29, 31]</th><th>[22, 28, 31]</th><th>[22, 29, 30]</th><th>[22, 28, 30]</th><th>[22, 29, 29]</th><th>[22, 28, 29]</th><th>[22, 29, 28]</th><th>[22, 28, 28]</th><th>[22, 29, 27]</th><th>[22, 28, 27]</th><th>[22, 29, 26]</th><th>[22, 28, 26]</th><th>[22, 29, 25]</th><th>[22, 28, 25]</th><th>[22, 29, 24]</th><th>[22, 28, 24]</th></tr>
+<tr><th>GTX2:DRP14</th><th>[22, 29, 39]</th><th>[22, 28, 39]</th><th>[22, 29, 38]</th><th>[22, 28, 38]</th><th>[22, 29, 37]</th><th>[22, 28, 37]</th><th>[22, 29, 36]</th><th>[22, 28, 36]</th><th>[22, 29, 35]</th><th>[22, 28, 35]</th><th>[22, 29, 34]</th><th>[22, 28, 34]</th><th>[22, 29, 33]</th><th>[22, 28, 33]</th><th>[22, 29, 32]</th><th>[22, 28, 32]</th></tr>
+<tr><th>GTX2:DRP15</th><th>[22, 29, 47]</th><th>[22, 28, 47]</th><th>[22, 29, 46]</th><th>[22, 28, 46]</th><th>[22, 29, 45]</th><th>[22, 28, 45]</th><th>[22, 29, 44]</th><th>[22, 28, 44]</th><th>[22, 29, 43]</th><th>[22, 28, 43]</th><th>[22, 29, 42]</th><th>[22, 28, 42]</th><th>[22, 29, 41]</th><th>[22, 28, 41]</th><th>[22, 29, 40]</th><th>[22, 28, 40]</th></tr>
+<tr><th>GTX2:DRP16</th><th>[22, 29, 55]</th><th>[22, 28, 55]</th><th>[22, 29, 54]</th><th>[22, 28, 54]</th><th>[22, 29, 53]</th><th>[22, 28, 53]</th><th>[22, 29, 52]</th><th>[22, 28, 52]</th><th>[22, 29, 51]</th><th>[22, 28, 51]</th><th>[22, 29, 50]</th><th>[22, 28, 50]</th><th>[22, 29, 49]</th><th>[22, 28, 49]</th><th>[22, 29, 48]</th><th>[22, 28, 48]</th></tr>
+<tr><th>GTX2:DRP17</th><th>[22, 29, 63]</th><th>[22, 28, 63]</th><th>[22, 29, 62]</th><th>[22, 28, 62]</th><th>[22, 29, 61]</th><th>[22, 28, 61]</th><th>[22, 29, 60]</th><th>[22, 28, 60]</th><th>[22, 29, 59]</th><th>[22, 28, 59]</th><th>[22, 29, 58]</th><th>[22, 28, 58]</th><th>[22, 29, 57]</th><th>[22, 28, 57]</th><th>[22, 29, 56]</th><th>[22, 28, 56]</th></tr>
+<tr><th>GTX2:DRP18</th><th>[23, 29, 7]</th><th>[23, 28, 7]</th><th>[23, 29, 6]</th><th>[23, 28, 6]</th><th>[23, 29, 5]</th><th>[23, 28, 5]</th><th>[23, 29, 4]</th><th>[23, 28, 4]</th><th>[23, 29, 3]</th><th>[23, 28, 3]</th><th>[23, 29, 2]</th><th>[23, 28, 2]</th><th>[23, 29, 1]</th><th>[23, 28, 1]</th><th>[23, 29, 0]</th><th>[23, 28, 0]</th></tr>
+<tr><th>GTX2:DRP19</th><th>[23, 29, 15]</th><th>[23, 28, 15]</th><th>[23, 29, 14]</th><th>[23, 28, 14]</th><th>[23, 29, 13]</th><th>[23, 28, 13]</th><th>[23, 29, 12]</th><th>[23, 28, 12]</th><th>[23, 29, 11]</th><th>[23, 28, 11]</th><th>[23, 29, 10]</th><th>[23, 28, 10]</th><th>[23, 29, 9]</th><th>[23, 28, 9]</th><th>[23, 29, 8]</th><th>[23, 28, 8]</th></tr>
+<tr><th>GTX2:DRP1A</th><th>[23, 29, 23]</th><th>[23, 28, 23]</th><th>[23, 29, 22]</th><th>[23, 28, 22]</th><th>[23, 29, 21]</th><th>[23, 28, 21]</th><th>[23, 29, 20]</th><th>[23, 28, 20]</th><th>[23, 29, 19]</th><th>[23, 28, 19]</th><th>[23, 29, 18]</th><th>[23, 28, 18]</th><th>[23, 29, 17]</th><th>[23, 28, 17]</th><th>[23, 29, 16]</th><th>[23, 28, 16]</th></tr>
+<tr><th>GTX2:DRP1B</th><th>[23, 29, 31]</th><th>[23, 28, 31]</th><th>[23, 29, 30]</th><th>[23, 28, 30]</th><th>[23, 29, 29]</th><th>[23, 28, 29]</th><th>[23, 29, 28]</th><th>[23, 28, 28]</th><th>[23, 29, 27]</th><th>[23, 28, 27]</th><th>[23, 29, 26]</th><th>[23, 28, 26]</th><th>[23, 29, 25]</th><th>[23, 28, 25]</th><th>[23, 29, 24]</th><th>[23, 28, 24]</th></tr>
+<tr><th>GTX2:DRP1C</th><th>[23, 29, 39]</th><th>[23, 28, 39]</th><th>[23, 29, 38]</th><th>[23, 28, 38]</th><th>[23, 29, 37]</th><th>[23, 28, 37]</th><th>[23, 29, 36]</th><th>[23, 28, 36]</th><th>[23, 29, 35]</th><th>[23, 28, 35]</th><th>[23, 29, 34]</th><th>[23, 28, 34]</th><th>[23, 29, 33]</th><th>[23, 28, 33]</th><th>[23, 29, 32]</th><th>[23, 28, 32]</th></tr>
+<tr><th>GTX2:DRP1D</th><th>[23, 29, 47]</th><th>[23, 28, 47]</th><th>[23, 29, 46]</th><th>[23, 28, 46]</th><th>[23, 29, 45]</th><th>[23, 28, 45]</th><th>[23, 29, 44]</th><th>[23, 28, 44]</th><th>[23, 29, 43]</th><th>[23, 28, 43]</th><th>[23, 29, 42]</th><th>[23, 28, 42]</th><th>[23, 29, 41]</th><th>[23, 28, 41]</th><th>[23, 29, 40]</th><th>[23, 28, 40]</th></tr>
+<tr><th>GTX2:DRP1E</th><th>[23, 29, 55]</th><th>[23, 28, 55]</th><th>[23, 29, 54]</th><th>[23, 28, 54]</th><th>[23, 29, 53]</th><th>[23, 28, 53]</th><th>[23, 29, 52]</th><th>[23, 28, 52]</th><th>[23, 29, 51]</th><th>[23, 28, 51]</th><th>[23, 29, 50]</th><th>[23, 28, 50]</th><th>[23, 29, 49]</th><th>[23, 28, 49]</th><th>[23, 29, 48]</th><th>[23, 28, 48]</th></tr>
+<tr><th>GTX2:DRP1F</th><th>[23, 29, 63]</th><th>[23, 28, 63]</th><th>[23, 29, 62]</th><th>[23, 28, 62]</th><th>[23, 29, 61]</th><th>[23, 28, 61]</th><th>[23, 29, 60]</th><th>[23, 28, 60]</th><th>[23, 29, 59]</th><th>[23, 28, 59]</th><th>[23, 29, 58]</th><th>[23, 28, 58]</th><th>[23, 29, 57]</th><th>[23, 28, 57]</th><th>[23, 29, 56]</th><th>[23, 28, 56]</th></tr>
+<tr><th>GTX2:DRP20</th><th>[24, 29, 7]</th><th>[24, 28, 7]</th><th>[24, 29, 6]</th><th>[24, 28, 6]</th><th>[24, 29, 5]</th><th>[24, 28, 5]</th><th>[24, 29, 4]</th><th>[24, 28, 4]</th><th>[24, 29, 3]</th><th>[24, 28, 3]</th><th>[24, 29, 2]</th><th>[24, 28, 2]</th><th>[24, 29, 1]</th><th>[24, 28, 1]</th><th>[24, 29, 0]</th><th>[24, 28, 0]</th></tr>
+<tr><th>GTX2:DRP21</th><th>[24, 29, 15]</th><th>[24, 28, 15]</th><th>[24, 29, 14]</th><th>[24, 28, 14]</th><th>[24, 29, 13]</th><th>[24, 28, 13]</th><th>[24, 29, 12]</th><th>[24, 28, 12]</th><th>[24, 29, 11]</th><th>[24, 28, 11]</th><th>[24, 29, 10]</th><th>[24, 28, 10]</th><th>[24, 29, 9]</th><th>[24, 28, 9]</th><th>[24, 29, 8]</th><th>[24, 28, 8]</th></tr>
+<tr><th>GTX2:DRP22</th><th>[24, 29, 23]</th><th>[24, 28, 23]</th><th>[24, 29, 22]</th><th>[24, 28, 22]</th><th>[24, 29, 21]</th><th>[24, 28, 21]</th><th>[24, 29, 20]</th><th>[24, 28, 20]</th><th>[24, 29, 19]</th><th>[24, 28, 19]</th><th>[24, 29, 18]</th><th>[24, 28, 18]</th><th>[24, 29, 17]</th><th>[24, 28, 17]</th><th>[24, 29, 16]</th><th>[24, 28, 16]</th></tr>
+<tr><th>GTX2:DRP23</th><th>[24, 29, 31]</th><th>[24, 28, 31]</th><th>[24, 29, 30]</th><th>[24, 28, 30]</th><th>[24, 29, 29]</th><th>[24, 28, 29]</th><th>[24, 29, 28]</th><th>[24, 28, 28]</th><th>[24, 29, 27]</th><th>[24, 28, 27]</th><th>[24, 29, 26]</th><th>[24, 28, 26]</th><th>[24, 29, 25]</th><th>[24, 28, 25]</th><th>[24, 29, 24]</th><th>[24, 28, 24]</th></tr>
+<tr><th>GTX2:DRP24</th><th>[24, 29, 39]</th><th>[24, 28, 39]</th><th>[24, 29, 38]</th><th>[24, 28, 38]</th><th>[24, 29, 37]</th><th>[24, 28, 37]</th><th>[24, 29, 36]</th><th>[24, 28, 36]</th><th>[24, 29, 35]</th><th>[24, 28, 35]</th><th>[24, 29, 34]</th><th>[24, 28, 34]</th><th>[24, 29, 33]</th><th>[24, 28, 33]</th><th>[24, 29, 32]</th><th>[24, 28, 32]</th></tr>
+<tr><th>GTX2:DRP25</th><th>[24, 29, 47]</th><th>[24, 28, 47]</th><th>[24, 29, 46]</th><th>[24, 28, 46]</th><th>[24, 29, 45]</th><th>[24, 28, 45]</th><th>[24, 29, 44]</th><th>[24, 28, 44]</th><th>[24, 29, 43]</th><th>[24, 28, 43]</th><th>[24, 29, 42]</th><th>[24, 28, 42]</th><th>[24, 29, 41]</th><th>[24, 28, 41]</th><th>[24, 29, 40]</th><th>[24, 28, 40]</th></tr>
+<tr><th>GTX2:DRP26</th><th>[24, 29, 55]</th><th>[24, 28, 55]</th><th>[24, 29, 54]</th><th>[24, 28, 54]</th><th>[24, 29, 53]</th><th>[24, 28, 53]</th><th>[24, 29, 52]</th><th>[24, 28, 52]</th><th>[24, 29, 51]</th><th>[24, 28, 51]</th><th>[24, 29, 50]</th><th>[24, 28, 50]</th><th>[24, 29, 49]</th><th>[24, 28, 49]</th><th>[24, 29, 48]</th><th>[24, 28, 48]</th></tr>
+<tr><th>GTX2:DRP27</th><th>[24, 29, 63]</th><th>[24, 28, 63]</th><th>[24, 29, 62]</th><th>[24, 28, 62]</th><th>[24, 29, 61]</th><th>[24, 28, 61]</th><th>[24, 29, 60]</th><th>[24, 28, 60]</th><th>[24, 29, 59]</th><th>[24, 28, 59]</th><th>[24, 29, 58]</th><th>[24, 28, 58]</th><th>[24, 29, 57]</th><th>[24, 28, 57]</th><th>[24, 29, 56]</th><th>[24, 28, 56]</th></tr>
+<tr><th>GTX2:DRP28</th><th>[25, 29, 7]</th><th>[25, 28, 7]</th><th>[25, 29, 6]</th><th>[25, 28, 6]</th><th>[25, 29, 5]</th><th>[25, 28, 5]</th><th>[25, 29, 4]</th><th>[25, 28, 4]</th><th>[25, 29, 3]</th><th>[25, 28, 3]</th><th>[25, 29, 2]</th><th>[25, 28, 2]</th><th>[25, 29, 1]</th><th>[25, 28, 1]</th><th>[25, 29, 0]</th><th>[25, 28, 0]</th></tr>
+<tr><th>GTX2:DRP29</th><th>[25, 29, 15]</th><th>[25, 28, 15]</th><th>[25, 29, 14]</th><th>[25, 28, 14]</th><th>[25, 29, 13]</th><th>[25, 28, 13]</th><th>[25, 29, 12]</th><th>[25, 28, 12]</th><th>[25, 29, 11]</th><th>[25, 28, 11]</th><th>[25, 29, 10]</th><th>[25, 28, 10]</th><th>[25, 29, 9]</th><th>[25, 28, 9]</th><th>[25, 29, 8]</th><th>[25, 28, 8]</th></tr>
+<tr><th>GTX2:DRP2A</th><th>[25, 29, 23]</th><th>[25, 28, 23]</th><th>[25, 29, 22]</th><th>[25, 28, 22]</th><th>[25, 29, 21]</th><th>[25, 28, 21]</th><th>[25, 29, 20]</th><th>[25, 28, 20]</th><th>[25, 29, 19]</th><th>[25, 28, 19]</th><th>[25, 29, 18]</th><th>[25, 28, 18]</th><th>[25, 29, 17]</th><th>[25, 28, 17]</th><th>[25, 29, 16]</th><th>[25, 28, 16]</th></tr>
+<tr><th>GTX2:DRP2B</th><th>[25, 29, 31]</th><th>[25, 28, 31]</th><th>[25, 29, 30]</th><th>[25, 28, 30]</th><th>[25, 29, 29]</th><th>[25, 28, 29]</th><th>[25, 29, 28]</th><th>[25, 28, 28]</th><th>[25, 29, 27]</th><th>[25, 28, 27]</th><th>[25, 29, 26]</th><th>[25, 28, 26]</th><th>[25, 29, 25]</th><th>[25, 28, 25]</th><th>[25, 29, 24]</th><th>[25, 28, 24]</th></tr>
+<tr><th>GTX2:DRP2C</th><th>[25, 29, 39]</th><th>[25, 28, 39]</th><th>[25, 29, 38]</th><th>[25, 28, 38]</th><th>[25, 29, 37]</th><th>[25, 28, 37]</th><th>[25, 29, 36]</th><th>[25, 28, 36]</th><th>[25, 29, 35]</th><th>[25, 28, 35]</th><th>[25, 29, 34]</th><th>[25, 28, 34]</th><th>[25, 29, 33]</th><th>[25, 28, 33]</th><th>[25, 29, 32]</th><th>[25, 28, 32]</th></tr>
+<tr><th>GTX2:DRP2D</th><th>[25, 29, 47]</th><th>[25, 28, 47]</th><th>[25, 29, 46]</th><th>[25, 28, 46]</th><th>[25, 29, 45]</th><th>[25, 28, 45]</th><th>[25, 29, 44]</th><th>[25, 28, 44]</th><th>[25, 29, 43]</th><th>[25, 28, 43]</th><th>[25, 29, 42]</th><th>[25, 28, 42]</th><th>[25, 29, 41]</th><th>[25, 28, 41]</th><th>[25, 29, 40]</th><th>[25, 28, 40]</th></tr>
+<tr><th>GTX2:DRP2E</th><th>[25, 29, 55]</th><th>[25, 28, 55]</th><th>[25, 29, 54]</th><th>[25, 28, 54]</th><th>[25, 29, 53]</th><th>[25, 28, 53]</th><th>[25, 29, 52]</th><th>[25, 28, 52]</th><th>[25, 29, 51]</th><th>[25, 28, 51]</th><th>[25, 29, 50]</th><th>[25, 28, 50]</th><th>[25, 29, 49]</th><th>[25, 28, 49]</th><th>[25, 29, 48]</th><th>[25, 28, 48]</th></tr>
+<tr><th>GTX2:DRP2F</th><th>[25, 29, 63]</th><th>[25, 28, 63]</th><th>[25, 29, 62]</th><th>[25, 28, 62]</th><th>[25, 29, 61]</th><th>[25, 28, 61]</th><th>[25, 29, 60]</th><th>[25, 28, 60]</th><th>[25, 29, 59]</th><th>[25, 28, 59]</th><th>[25, 29, 58]</th><th>[25, 28, 58]</th><th>[25, 29, 57]</th><th>[25, 28, 57]</th><th>[25, 29, 56]</th><th>[25, 28, 56]</th></tr>
+<tr><th>GTX2:DRP30</th><th>[26, 29, 7]</th><th>[26, 28, 7]</th><th>[26, 29, 6]</th><th>[26, 28, 6]</th><th>[26, 29, 5]</th><th>[26, 28, 5]</th><th>[26, 29, 4]</th><th>[26, 28, 4]</th><th>[26, 29, 3]</th><th>[26, 28, 3]</th><th>[26, 29, 2]</th><th>[26, 28, 2]</th><th>[26, 29, 1]</th><th>[26, 28, 1]</th><th>[26, 29, 0]</th><th>[26, 28, 0]</th></tr>
+<tr><th>GTX2:DRP31</th><th>[26, 29, 15]</th><th>[26, 28, 15]</th><th>[26, 29, 14]</th><th>[26, 28, 14]</th><th>[26, 29, 13]</th><th>[26, 28, 13]</th><th>[26, 29, 12]</th><th>[26, 28, 12]</th><th>[26, 29, 11]</th><th>[26, 28, 11]</th><th>[26, 29, 10]</th><th>[26, 28, 10]</th><th>[26, 29, 9]</th><th>[26, 28, 9]</th><th>[26, 29, 8]</th><th>[26, 28, 8]</th></tr>
+<tr><th>GTX2:DRP32</th><th>[26, 29, 23]</th><th>[26, 28, 23]</th><th>[26, 29, 22]</th><th>[26, 28, 22]</th><th>[26, 29, 21]</th><th>[26, 28, 21]</th><th>[26, 29, 20]</th><th>[26, 28, 20]</th><th>[26, 29, 19]</th><th>[26, 28, 19]</th><th>[26, 29, 18]</th><th>[26, 28, 18]</th><th>[26, 29, 17]</th><th>[26, 28, 17]</th><th>[26, 29, 16]</th><th>[26, 28, 16]</th></tr>
+<tr><th>GTX2:DRP33</th><th>[26, 29, 31]</th><th>[26, 28, 31]</th><th>[26, 29, 30]</th><th>[26, 28, 30]</th><th>[26, 29, 29]</th><th>[26, 28, 29]</th><th>[26, 29, 28]</th><th>[26, 28, 28]</th><th>[26, 29, 27]</th><th>[26, 28, 27]</th><th>[26, 29, 26]</th><th>[26, 28, 26]</th><th>[26, 29, 25]</th><th>[26, 28, 25]</th><th>[26, 29, 24]</th><th>[26, 28, 24]</th></tr>
+<tr><th>GTX2:DRP34</th><th>[26, 29, 39]</th><th>[26, 28, 39]</th><th>[26, 29, 38]</th><th>[26, 28, 38]</th><th>[26, 29, 37]</th><th>[26, 28, 37]</th><th>[26, 29, 36]</th><th>[26, 28, 36]</th><th>[26, 29, 35]</th><th>[26, 28, 35]</th><th>[26, 29, 34]</th><th>[26, 28, 34]</th><th>[26, 29, 33]</th><th>[26, 28, 33]</th><th>[26, 29, 32]</th><th>[26, 28, 32]</th></tr>
+<tr><th>GTX2:DRP35</th><th>[26, 29, 47]</th><th>[26, 28, 47]</th><th>[26, 29, 46]</th><th>[26, 28, 46]</th><th>[26, 29, 45]</th><th>[26, 28, 45]</th><th>[26, 29, 44]</th><th>[26, 28, 44]</th><th>[26, 29, 43]</th><th>[26, 28, 43]</th><th>[26, 29, 42]</th><th>[26, 28, 42]</th><th>[26, 29, 41]</th><th>[26, 28, 41]</th><th>[26, 29, 40]</th><th>[26, 28, 40]</th></tr>
+<tr><th>GTX2:DRP36</th><th>[26, 29, 55]</th><th>[26, 28, 55]</th><th>[26, 29, 54]</th><th>[26, 28, 54]</th><th>[26, 29, 53]</th><th>[26, 28, 53]</th><th>[26, 29, 52]</th><th>[26, 28, 52]</th><th>[26, 29, 51]</th><th>[26, 28, 51]</th><th>[26, 29, 50]</th><th>[26, 28, 50]</th><th>[26, 29, 49]</th><th>[26, 28, 49]</th><th>[26, 29, 48]</th><th>[26, 28, 48]</th></tr>
+<tr><th>GTX2:DRP37</th><th>[26, 29, 63]</th><th>[26, 28, 63]</th><th>[26, 29, 62]</th><th>[26, 28, 62]</th><th>[26, 29, 61]</th><th>[26, 28, 61]</th><th>[26, 29, 60]</th><th>[26, 28, 60]</th><th>[26, 29, 59]</th><th>[26, 28, 59]</th><th>[26, 29, 58]</th><th>[26, 28, 58]</th><th>[26, 29, 57]</th><th>[26, 28, 57]</th><th>[26, 29, 56]</th><th>[26, 28, 56]</th></tr>
+<tr><th>GTX2:DRP38</th><th>[27, 29, 7]</th><th>[27, 28, 7]</th><th>[27, 29, 6]</th><th>[27, 28, 6]</th><th>[27, 29, 5]</th><th>[27, 28, 5]</th><th>[27, 29, 4]</th><th>[27, 28, 4]</th><th>[27, 29, 3]</th><th>[27, 28, 3]</th><th>[27, 29, 2]</th><th>[27, 28, 2]</th><th>[27, 29, 1]</th><th>[27, 28, 1]</th><th>[27, 29, 0]</th><th>[27, 28, 0]</th></tr>
+<tr><th>GTX2:DRP39</th><th>[27, 29, 15]</th><th>[27, 28, 15]</th><th>[27, 29, 14]</th><th>[27, 28, 14]</th><th>[27, 29, 13]</th><th>[27, 28, 13]</th><th>[27, 29, 12]</th><th>[27, 28, 12]</th><th>[27, 29, 11]</th><th>[27, 28, 11]</th><th>[27, 29, 10]</th><th>[27, 28, 10]</th><th>[27, 29, 9]</th><th>[27, 28, 9]</th><th>[27, 29, 8]</th><th>[27, 28, 8]</th></tr>
+<tr><th>GTX2:DRP3A</th><th>[27, 29, 23]</th><th>[27, 28, 23]</th><th>[27, 29, 22]</th><th>[27, 28, 22]</th><th>[27, 29, 21]</th><th>[27, 28, 21]</th><th>[27, 29, 20]</th><th>[27, 28, 20]</th><th>[27, 29, 19]</th><th>[27, 28, 19]</th><th>[27, 29, 18]</th><th>[27, 28, 18]</th><th>[27, 29, 17]</th><th>[27, 28, 17]</th><th>[27, 29, 16]</th><th>[27, 28, 16]</th></tr>
+<tr><th>GTX2:DRP3B</th><th>[27, 29, 31]</th><th>[27, 28, 31]</th><th>[27, 29, 30]</th><th>[27, 28, 30]</th><th>[27, 29, 29]</th><th>[27, 28, 29]</th><th>[27, 29, 28]</th><th>[27, 28, 28]</th><th>[27, 29, 27]</th><th>[27, 28, 27]</th><th>[27, 29, 26]</th><th>[27, 28, 26]</th><th>[27, 29, 25]</th><th>[27, 28, 25]</th><th>[27, 29, 24]</th><th>[27, 28, 24]</th></tr>
+<tr><th>GTX2:DRP3C</th><th>[27, 29, 39]</th><th>[27, 28, 39]</th><th>[27, 29, 38]</th><th>[27, 28, 38]</th><th>[27, 29, 37]</th><th>[27, 28, 37]</th><th>[27, 29, 36]</th><th>[27, 28, 36]</th><th>[27, 29, 35]</th><th>[27, 28, 35]</th><th>[27, 29, 34]</th><th>[27, 28, 34]</th><th>[27, 29, 33]</th><th>[27, 28, 33]</th><th>[27, 29, 32]</th><th>[27, 28, 32]</th></tr>
+<tr><th>GTX2:DRP3D</th><th>[27, 29, 47]</th><th>[27, 28, 47]</th><th>[27, 29, 46]</th><th>[27, 28, 46]</th><th>[27, 29, 45]</th><th>[27, 28, 45]</th><th>[27, 29, 44]</th><th>[27, 28, 44]</th><th>[27, 29, 43]</th><th>[27, 28, 43]</th><th>[27, 29, 42]</th><th>[27, 28, 42]</th><th>[27, 29, 41]</th><th>[27, 28, 41]</th><th>[27, 29, 40]</th><th>[27, 28, 40]</th></tr>
+<tr><th>GTX2:DRP3E</th><th>[27, 29, 55]</th><th>[27, 28, 55]</th><th>[27, 29, 54]</th><th>[27, 28, 54]</th><th>[27, 29, 53]</th><th>[27, 28, 53]</th><th>[27, 29, 52]</th><th>[27, 28, 52]</th><th>[27, 29, 51]</th><th>[27, 28, 51]</th><th>[27, 29, 50]</th><th>[27, 28, 50]</th><th>[27, 29, 49]</th><th>[27, 28, 49]</th><th>[27, 29, 48]</th><th>[27, 28, 48]</th></tr>
+<tr><th>GTX2:DRP3F</th><th>[27, 29, 63]</th><th>[27, 28, 63]</th><th>[27, 29, 62]</th><th>[27, 28, 62]</th><th>[27, 29, 61]</th><th>[27, 28, 61]</th><th>[27, 29, 60]</th><th>[27, 28, 60]</th><th>[27, 29, 59]</th><th>[27, 28, 59]</th><th>[27, 29, 58]</th><th>[27, 28, 58]</th><th>[27, 29, 57]</th><th>[27, 28, 57]</th><th>[27, 29, 56]</th><th>[27, 28, 56]</th></tr>
+<tr><th>GTX2:DRP40</th><th>[28, 29, 7]</th><th>[28, 28, 7]</th><th>[28, 29, 6]</th><th>[28, 28, 6]</th><th>[28, 29, 5]</th><th>[28, 28, 5]</th><th>[28, 29, 4]</th><th>[28, 28, 4]</th><th>[28, 29, 3]</th><th>[28, 28, 3]</th><th>[28, 29, 2]</th><th>[28, 28, 2]</th><th>[28, 29, 1]</th><th>[28, 28, 1]</th><th>[28, 29, 0]</th><th>[28, 28, 0]</th></tr>
+<tr><th>GTX2:DRP41</th><th>[28, 29, 15]</th><th>[28, 28, 15]</th><th>[28, 29, 14]</th><th>[28, 28, 14]</th><th>[28, 29, 13]</th><th>[28, 28, 13]</th><th>[28, 29, 12]</th><th>[28, 28, 12]</th><th>[28, 29, 11]</th><th>[28, 28, 11]</th><th>[28, 29, 10]</th><th>[28, 28, 10]</th><th>[28, 29, 9]</th><th>[28, 28, 9]</th><th>[28, 29, 8]</th><th>[28, 28, 8]</th></tr>
+<tr><th>GTX2:DRP42</th><th>[28, 29, 23]</th><th>[28, 28, 23]</th><th>[28, 29, 22]</th><th>[28, 28, 22]</th><th>[28, 29, 21]</th><th>[28, 28, 21]</th><th>[28, 29, 20]</th><th>[28, 28, 20]</th><th>[28, 29, 19]</th><th>[28, 28, 19]</th><th>[28, 29, 18]</th><th>[28, 28, 18]</th><th>[28, 29, 17]</th><th>[28, 28, 17]</th><th>[28, 29, 16]</th><th>[28, 28, 16]</th></tr>
+<tr><th>GTX2:DRP43</th><th>[28, 29, 31]</th><th>[28, 28, 31]</th><th>[28, 29, 30]</th><th>[28, 28, 30]</th><th>[28, 29, 29]</th><th>[28, 28, 29]</th><th>[28, 29, 28]</th><th>[28, 28, 28]</th><th>[28, 29, 27]</th><th>[28, 28, 27]</th><th>[28, 29, 26]</th><th>[28, 28, 26]</th><th>[28, 29, 25]</th><th>[28, 28, 25]</th><th>[28, 29, 24]</th><th>[28, 28, 24]</th></tr>
+<tr><th>GTX2:DRP44</th><th>[28, 29, 39]</th><th>[28, 28, 39]</th><th>[28, 29, 38]</th><th>[28, 28, 38]</th><th>[28, 29, 37]</th><th>[28, 28, 37]</th><th>[28, 29, 36]</th><th>[28, 28, 36]</th><th>[28, 29, 35]</th><th>[28, 28, 35]</th><th>[28, 29, 34]</th><th>[28, 28, 34]</th><th>[28, 29, 33]</th><th>[28, 28, 33]</th><th>[28, 29, 32]</th><th>[28, 28, 32]</th></tr>
+<tr><th>GTX2:DRP45</th><th>[28, 29, 47]</th><th>[28, 28, 47]</th><th>[28, 29, 46]</th><th>[28, 28, 46]</th><th>[28, 29, 45]</th><th>[28, 28, 45]</th><th>[28, 29, 44]</th><th>[28, 28, 44]</th><th>[28, 29, 43]</th><th>[28, 28, 43]</th><th>[28, 29, 42]</th><th>[28, 28, 42]</th><th>[28, 29, 41]</th><th>[28, 28, 41]</th><th>[28, 29, 40]</th><th>[28, 28, 40]</th></tr>
+<tr><th>GTX2:DRP46</th><th>[28, 29, 55]</th><th>[28, 28, 55]</th><th>[28, 29, 54]</th><th>[28, 28, 54]</th><th>[28, 29, 53]</th><th>[28, 28, 53]</th><th>[28, 29, 52]</th><th>[28, 28, 52]</th><th>[28, 29, 51]</th><th>[28, 28, 51]</th><th>[28, 29, 50]</th><th>[28, 28, 50]</th><th>[28, 29, 49]</th><th>[28, 28, 49]</th><th>[28, 29, 48]</th><th>[28, 28, 48]</th></tr>
+<tr><th>GTX2:DRP47</th><th>[28, 29, 63]</th><th>[28, 28, 63]</th><th>[28, 29, 62]</th><th>[28, 28, 62]</th><th>[28, 29, 61]</th><th>[28, 28, 61]</th><th>[28, 29, 60]</th><th>[28, 28, 60]</th><th>[28, 29, 59]</th><th>[28, 28, 59]</th><th>[28, 29, 58]</th><th>[28, 28, 58]</th><th>[28, 29, 57]</th><th>[28, 28, 57]</th><th>[28, 29, 56]</th><th>[28, 28, 56]</th></tr>
+<tr><th>GTX2:DRP48</th><th>[29, 29, 7]</th><th>[29, 28, 7]</th><th>[29, 29, 6]</th><th>[29, 28, 6]</th><th>[29, 29, 5]</th><th>[29, 28, 5]</th><th>[29, 29, 4]</th><th>[29, 28, 4]</th><th>[29, 29, 3]</th><th>[29, 28, 3]</th><th>[29, 29, 2]</th><th>[29, 28, 2]</th><th>[29, 29, 1]</th><th>[29, 28, 1]</th><th>[29, 29, 0]</th><th>[29, 28, 0]</th></tr>
+<tr><th>GTX2:DRP49</th><th>[29, 29, 15]</th><th>[29, 28, 15]</th><th>[29, 29, 14]</th><th>[29, 28, 14]</th><th>[29, 29, 13]</th><th>[29, 28, 13]</th><th>[29, 29, 12]</th><th>[29, 28, 12]</th><th>[29, 29, 11]</th><th>[29, 28, 11]</th><th>[29, 29, 10]</th><th>[29, 28, 10]</th><th>[29, 29, 9]</th><th>[29, 28, 9]</th><th>[29, 29, 8]</th><th>[29, 28, 8]</th></tr>
+<tr><th>GTX2:DRP4A</th><th>[29, 29, 23]</th><th>[29, 28, 23]</th><th>[29, 29, 22]</th><th>[29, 28, 22]</th><th>[29, 29, 21]</th><th>[29, 28, 21]</th><th>[29, 29, 20]</th><th>[29, 28, 20]</th><th>[29, 29, 19]</th><th>[29, 28, 19]</th><th>[29, 29, 18]</th><th>[29, 28, 18]</th><th>[29, 29, 17]</th><th>[29, 28, 17]</th><th>[29, 29, 16]</th><th>[29, 28, 16]</th></tr>
+<tr><th>GTX2:DRP4B</th><th>[29, 29, 31]</th><th>[29, 28, 31]</th><th>[29, 29, 30]</th><th>[29, 28, 30]</th><th>[29, 29, 29]</th><th>[29, 28, 29]</th><th>[29, 29, 28]</th><th>[29, 28, 28]</th><th>[29, 29, 27]</th><th>[29, 28, 27]</th><th>[29, 29, 26]</th><th>[29, 28, 26]</th><th>[29, 29, 25]</th><th>[29, 28, 25]</th><th>[29, 29, 24]</th><th>[29, 28, 24]</th></tr>
+<tr><th>GTX2:DRP4C</th><th>[29, 29, 39]</th><th>[29, 28, 39]</th><th>[29, 29, 38]</th><th>[29, 28, 38]</th><th>[29, 29, 37]</th><th>[29, 28, 37]</th><th>[29, 29, 36]</th><th>[29, 28, 36]</th><th>[29, 29, 35]</th><th>[29, 28, 35]</th><th>[29, 29, 34]</th><th>[29, 28, 34]</th><th>[29, 29, 33]</th><th>[29, 28, 33]</th><th>[29, 29, 32]</th><th>[29, 28, 32]</th></tr>
+<tr><th>GTX2:DRP4D</th><th>[29, 29, 47]</th><th>[29, 28, 47]</th><th>[29, 29, 46]</th><th>[29, 28, 46]</th><th>[29, 29, 45]</th><th>[29, 28, 45]</th><th>[29, 29, 44]</th><th>[29, 28, 44]</th><th>[29, 29, 43]</th><th>[29, 28, 43]</th><th>[29, 29, 42]</th><th>[29, 28, 42]</th><th>[29, 29, 41]</th><th>[29, 28, 41]</th><th>[29, 29, 40]</th><th>[29, 28, 40]</th></tr>
+<tr><th>GTX2:DRP4E</th><th>[29, 29, 55]</th><th>[29, 28, 55]</th><th>[29, 29, 54]</th><th>[29, 28, 54]</th><th>[29, 29, 53]</th><th>[29, 28, 53]</th><th>[29, 29, 52]</th><th>[29, 28, 52]</th><th>[29, 29, 51]</th><th>[29, 28, 51]</th><th>[29, 29, 50]</th><th>[29, 28, 50]</th><th>[29, 29, 49]</th><th>[29, 28, 49]</th><th>[29, 29, 48]</th><th>[29, 28, 48]</th></tr>
+<tr><th>GTX2:DRP4F</th><th>[29, 29, 63]</th><th>[29, 28, 63]</th><th>[29, 29, 62]</th><th>[29, 28, 62]</th><th>[29, 29, 61]</th><th>[29, 28, 61]</th><th>[29, 29, 60]</th><th>[29, 28, 60]</th><th>[29, 29, 59]</th><th>[29, 28, 59]</th><th>[29, 29, 58]</th><th>[29, 28, 58]</th><th>[29, 29, 57]</th><th>[29, 28, 57]</th><th>[29, 29, 56]</th><th>[29, 28, 56]</th></tr>
+<tr><th>GTX2:RXUSRCLK_DLY</th><th>[20, 29, 23]</th><th>[20, 28, 23]</th><th>[20, 29, 22]</th><th>[20, 28, 22]</th><th>[20, 29, 21]</th><th>[20, 28, 21]</th><th>[20, 29, 20]</th><th>[20, 28, 20]</th><th>[20, 29, 19]</th><th>[20, 28, 19]</th><th>[20, 29, 18]</th><th>[20, 28, 18]</th><th>[20, 29, 17]</th><th>[20, 28, 17]</th><th>[20, 29, 16]</th><th>[20, 28, 16]</th></tr>
+<tr><th>GTX3:DRP00</th><th>[30, 29, 7]</th><th>[30, 28, 7]</th><th>[30, 29, 6]</th><th>[30, 28, 6]</th><th>[30, 29, 5]</th><th>[30, 28, 5]</th><th>[30, 29, 4]</th><th>[30, 28, 4]</th><th>[30, 29, 3]</th><th>[30, 28, 3]</th><th>[30, 29, 2]</th><th>[30, 28, 2]</th><th>[30, 29, 1]</th><th>[30, 28, 1]</th><th>[30, 29, 0]</th><th>[30, 28, 0]</th></tr>
+<tr><th>GTX3:DRP01</th><th>[30, 29, 15]</th><th>[30, 28, 15]</th><th>[30, 29, 14]</th><th>[30, 28, 14]</th><th>[30, 29, 13]</th><th>[30, 28, 13]</th><th>[30, 29, 12]</th><th>[30, 28, 12]</th><th>[30, 29, 11]</th><th>[30, 28, 11]</th><th>[30, 29, 10]</th><th>[30, 28, 10]</th><th>[30, 29, 9]</th><th>[30, 28, 9]</th><th>[30, 29, 8]</th><th>[30, 28, 8]</th></tr>
+<tr><th>GTX3:DRP02</th><th>[30, 29, 23]</th><th>[30, 28, 23]</th><th>[30, 29, 22]</th><th>[30, 28, 22]</th><th>[30, 29, 21]</th><th>[30, 28, 21]</th><th>[30, 29, 20]</th><th>[30, 28, 20]</th><th>[30, 29, 19]</th><th>[30, 28, 19]</th><th>[30, 29, 18]</th><th>[30, 28, 18]</th><th>[30, 29, 17]</th><th>[30, 28, 17]</th><th>[30, 29, 16]</th><th>[30, 28, 16]</th></tr>
+<tr><th>GTX3:DRP03</th><th>[30, 29, 31]</th><th>[30, 28, 31]</th><th>[30, 29, 30]</th><th>[30, 28, 30]</th><th>[30, 29, 29]</th><th>[30, 28, 29]</th><th>[30, 29, 28]</th><th>[30, 28, 28]</th><th>[30, 29, 27]</th><th>[30, 28, 27]</th><th>[30, 29, 26]</th><th>[30, 28, 26]</th><th>[30, 29, 25]</th><th>[30, 28, 25]</th><th>[30, 29, 24]</th><th>[30, 28, 24]</th></tr>
+<tr><th>GTX3:DRP04</th><th>[30, 29, 39]</th><th>[30, 28, 39]</th><th>[30, 29, 38]</th><th>[30, 28, 38]</th><th>[30, 29, 37]</th><th>[30, 28, 37]</th><th>[30, 29, 36]</th><th>[30, 28, 36]</th><th>[30, 29, 35]</th><th>[30, 28, 35]</th><th>[30, 29, 34]</th><th>[30, 28, 34]</th><th>[30, 29, 33]</th><th>[30, 28, 33]</th><th>[30, 29, 32]</th><th>[30, 28, 32]</th></tr>
+<tr><th>GTX3:DRP05</th><th>[30, 29, 47]</th><th>[30, 28, 47]</th><th>[30, 29, 46]</th><th>[30, 28, 46]</th><th>[30, 29, 45]</th><th>[30, 28, 45]</th><th>[30, 29, 44]</th><th>[30, 28, 44]</th><th>[30, 29, 43]</th><th>[30, 28, 43]</th><th>[30, 29, 42]</th><th>[30, 28, 42]</th><th>[30, 29, 41]</th><th>[30, 28, 41]</th><th>[30, 29, 40]</th><th>[30, 28, 40]</th></tr>
+<tr><th>GTX3:DRP06</th><th>[30, 29, 55]</th><th>[30, 28, 55]</th><th>[30, 29, 54]</th><th>[30, 28, 54]</th><th>[30, 29, 53]</th><th>[30, 28, 53]</th><th>[30, 29, 52]</th><th>[30, 28, 52]</th><th>[30, 29, 51]</th><th>[30, 28, 51]</th><th>[30, 29, 50]</th><th>[30, 28, 50]</th><th>[30, 29, 49]</th><th>[30, 28, 49]</th><th>[30, 29, 48]</th><th>[30, 28, 48]</th></tr>
+<tr><th>GTX3:DRP07</th><th>[30, 29, 63]</th><th>[30, 28, 63]</th><th>[30, 29, 62]</th><th>[30, 28, 62]</th><th>[30, 29, 61]</th><th>[30, 28, 61]</th><th>[30, 29, 60]</th><th>[30, 28, 60]</th><th>[30, 29, 59]</th><th>[30, 28, 59]</th><th>[30, 29, 58]</th><th>[30, 28, 58]</th><th>[30, 29, 57]</th><th>[30, 28, 57]</th><th>[30, 29, 56]</th><th>[30, 28, 56]</th></tr>
+<tr><th>GTX3:DRP08</th><th>[31, 29, 7]</th><th>[31, 28, 7]</th><th>[31, 29, 6]</th><th>[31, 28, 6]</th><th>[31, 29, 5]</th><th>[31, 28, 5]</th><th>[31, 29, 4]</th><th>[31, 28, 4]</th><th>[31, 29, 3]</th><th>[31, 28, 3]</th><th>[31, 29, 2]</th><th>[31, 28, 2]</th><th>[31, 29, 1]</th><th>[31, 28, 1]</th><th>[31, 29, 0]</th><th>[31, 28, 0]</th></tr>
+<tr><th>GTX3:DRP09</th><th>[31, 29, 15]</th><th>[31, 28, 15]</th><th>[31, 29, 14]</th><th>[31, 28, 14]</th><th>[31, 29, 13]</th><th>[31, 28, 13]</th><th>[31, 29, 12]</th><th>[31, 28, 12]</th><th>[31, 29, 11]</th><th>[31, 28, 11]</th><th>[31, 29, 10]</th><th>[31, 28, 10]</th><th>[31, 29, 9]</th><th>[31, 28, 9]</th><th>[31, 29, 8]</th><th>[31, 28, 8]</th></tr>
+<tr><th>GTX3:DRP0A</th><th>[31, 29, 23]</th><th>[31, 28, 23]</th><th>[31, 29, 22]</th><th>[31, 28, 22]</th><th>[31, 29, 21]</th><th>[31, 28, 21]</th><th>[31, 29, 20]</th><th>[31, 28, 20]</th><th>[31, 29, 19]</th><th>[31, 28, 19]</th><th>[31, 29, 18]</th><th>[31, 28, 18]</th><th>[31, 29, 17]</th><th>[31, 28, 17]</th><th>[31, 29, 16]</th><th>[31, 28, 16]</th></tr>
+<tr><th>GTX3:DRP0B</th><th>[31, 29, 31]</th><th>[31, 28, 31]</th><th>[31, 29, 30]</th><th>[31, 28, 30]</th><th>[31, 29, 29]</th><th>[31, 28, 29]</th><th>[31, 29, 28]</th><th>[31, 28, 28]</th><th>[31, 29, 27]</th><th>[31, 28, 27]</th><th>[31, 29, 26]</th><th>[31, 28, 26]</th><th>[31, 29, 25]</th><th>[31, 28, 25]</th><th>[31, 29, 24]</th><th>[31, 28, 24]</th></tr>
+<tr><th>GTX3:DRP0C</th><th>[31, 29, 39]</th><th>[31, 28, 39]</th><th>[31, 29, 38]</th><th>[31, 28, 38]</th><th>[31, 29, 37]</th><th>[31, 28, 37]</th><th>[31, 29, 36]</th><th>[31, 28, 36]</th><th>[31, 29, 35]</th><th>[31, 28, 35]</th><th>[31, 29, 34]</th><th>[31, 28, 34]</th><th>[31, 29, 33]</th><th>[31, 28, 33]</th><th>[31, 29, 32]</th><th>[31, 28, 32]</th></tr>
+<tr><th>GTX3:DRP0D</th><th>[31, 29, 47]</th><th>[31, 28, 47]</th><th>[31, 29, 46]</th><th>[31, 28, 46]</th><th>[31, 29, 45]</th><th>[31, 28, 45]</th><th>[31, 29, 44]</th><th>[31, 28, 44]</th><th>[31, 29, 43]</th><th>[31, 28, 43]</th><th>[31, 29, 42]</th><th>[31, 28, 42]</th><th>[31, 29, 41]</th><th>[31, 28, 41]</th><th>[31, 29, 40]</th><th>[31, 28, 40]</th></tr>
+<tr><th>GTX3:DRP0E</th><th>[31, 29, 55]</th><th>[31, 28, 55]</th><th>[31, 29, 54]</th><th>[31, 28, 54]</th><th>[31, 29, 53]</th><th>[31, 28, 53]</th><th>[31, 29, 52]</th><th>[31, 28, 52]</th><th>[31, 29, 51]</th><th>[31, 28, 51]</th><th>[31, 29, 50]</th><th>[31, 28, 50]</th><th>[31, 29, 49]</th><th>[31, 28, 49]</th><th>[31, 29, 48]</th><th>[31, 28, 48]</th></tr>
+<tr><th>GTX3:DRP0F</th><th>[31, 29, 63]</th><th>[31, 28, 63]</th><th>[31, 29, 62]</th><th>[31, 28, 62]</th><th>[31, 29, 61]</th><th>[31, 28, 61]</th><th>[31, 29, 60]</th><th>[31, 28, 60]</th><th>[31, 29, 59]</th><th>[31, 28, 59]</th><th>[31, 29, 58]</th><th>[31, 28, 58]</th><th>[31, 29, 57]</th><th>[31, 28, 57]</th><th>[31, 29, 56]</th><th>[31, 28, 56]</th></tr>
+<tr><th>GTX3:DRP10</th><th>[32, 29, 7]</th><th>[32, 28, 7]</th><th>[32, 29, 6]</th><th>[32, 28, 6]</th><th>[32, 29, 5]</th><th>[32, 28, 5]</th><th>[32, 29, 4]</th><th>[32, 28, 4]</th><th>[32, 29, 3]</th><th>[32, 28, 3]</th><th>[32, 29, 2]</th><th>[32, 28, 2]</th><th>[32, 29, 1]</th><th>[32, 28, 1]</th><th>[32, 29, 0]</th><th>[32, 28, 0]</th></tr>
+<tr><th>GTX3:DRP11</th><th>[32, 29, 15]</th><th>[32, 28, 15]</th><th>[32, 29, 14]</th><th>[32, 28, 14]</th><th>[32, 29, 13]</th><th>[32, 28, 13]</th><th>[32, 29, 12]</th><th>[32, 28, 12]</th><th>[32, 29, 11]</th><th>[32, 28, 11]</th><th>[32, 29, 10]</th><th>[32, 28, 10]</th><th>[32, 29, 9]</th><th>[32, 28, 9]</th><th>[32, 29, 8]</th><th>[32, 28, 8]</th></tr>
+<tr><th>GTX3:DRP12</th><th>[32, 29, 23]</th><th>[32, 28, 23]</th><th>[32, 29, 22]</th><th>[32, 28, 22]</th><th>[32, 29, 21]</th><th>[32, 28, 21]</th><th>[32, 29, 20]</th><th>[32, 28, 20]</th><th>[32, 29, 19]</th><th>[32, 28, 19]</th><th>[32, 29, 18]</th><th>[32, 28, 18]</th><th>[32, 29, 17]</th><th>[32, 28, 17]</th><th>[32, 29, 16]</th><th>[32, 28, 16]</th></tr>
+<tr><th>GTX3:DRP13</th><th>[32, 29, 31]</th><th>[32, 28, 31]</th><th>[32, 29, 30]</th><th>[32, 28, 30]</th><th>[32, 29, 29]</th><th>[32, 28, 29]</th><th>[32, 29, 28]</th><th>[32, 28, 28]</th><th>[32, 29, 27]</th><th>[32, 28, 27]</th><th>[32, 29, 26]</th><th>[32, 28, 26]</th><th>[32, 29, 25]</th><th>[32, 28, 25]</th><th>[32, 29, 24]</th><th>[32, 28, 24]</th></tr>
+<tr><th>GTX3:DRP14</th><th>[32, 29, 39]</th><th>[32, 28, 39]</th><th>[32, 29, 38]</th><th>[32, 28, 38]</th><th>[32, 29, 37]</th><th>[32, 28, 37]</th><th>[32, 29, 36]</th><th>[32, 28, 36]</th><th>[32, 29, 35]</th><th>[32, 28, 35]</th><th>[32, 29, 34]</th><th>[32, 28, 34]</th><th>[32, 29, 33]</th><th>[32, 28, 33]</th><th>[32, 29, 32]</th><th>[32, 28, 32]</th></tr>
+<tr><th>GTX3:DRP15</th><th>[32, 29, 47]</th><th>[32, 28, 47]</th><th>[32, 29, 46]</th><th>[32, 28, 46]</th><th>[32, 29, 45]</th><th>[32, 28, 45]</th><th>[32, 29, 44]</th><th>[32, 28, 44]</th><th>[32, 29, 43]</th><th>[32, 28, 43]</th><th>[32, 29, 42]</th><th>[32, 28, 42]</th><th>[32, 29, 41]</th><th>[32, 28, 41]</th><th>[32, 29, 40]</th><th>[32, 28, 40]</th></tr>
+<tr><th>GTX3:DRP16</th><th>[32, 29, 55]</th><th>[32, 28, 55]</th><th>[32, 29, 54]</th><th>[32, 28, 54]</th><th>[32, 29, 53]</th><th>[32, 28, 53]</th><th>[32, 29, 52]</th><th>[32, 28, 52]</th><th>[32, 29, 51]</th><th>[32, 28, 51]</th><th>[32, 29, 50]</th><th>[32, 28, 50]</th><th>[32, 29, 49]</th><th>[32, 28, 49]</th><th>[32, 29, 48]</th><th>[32, 28, 48]</th></tr>
+<tr><th>GTX3:DRP17</th><th>[32, 29, 63]</th><th>[32, 28, 63]</th><th>[32, 29, 62]</th><th>[32, 28, 62]</th><th>[32, 29, 61]</th><th>[32, 28, 61]</th><th>[32, 29, 60]</th><th>[32, 28, 60]</th><th>[32, 29, 59]</th><th>[32, 28, 59]</th><th>[32, 29, 58]</th><th>[32, 28, 58]</th><th>[32, 29, 57]</th><th>[32, 28, 57]</th><th>[32, 29, 56]</th><th>[32, 28, 56]</th></tr>
+<tr><th>GTX3:DRP18</th><th>[33, 29, 7]</th><th>[33, 28, 7]</th><th>[33, 29, 6]</th><th>[33, 28, 6]</th><th>[33, 29, 5]</th><th>[33, 28, 5]</th><th>[33, 29, 4]</th><th>[33, 28, 4]</th><th>[33, 29, 3]</th><th>[33, 28, 3]</th><th>[33, 29, 2]</th><th>[33, 28, 2]</th><th>[33, 29, 1]</th><th>[33, 28, 1]</th><th>[33, 29, 0]</th><th>[33, 28, 0]</th></tr>
+<tr><th>GTX3:DRP19</th><th>[33, 29, 15]</th><th>[33, 28, 15]</th><th>[33, 29, 14]</th><th>[33, 28, 14]</th><th>[33, 29, 13]</th><th>[33, 28, 13]</th><th>[33, 29, 12]</th><th>[33, 28, 12]</th><th>[33, 29, 11]</th><th>[33, 28, 11]</th><th>[33, 29, 10]</th><th>[33, 28, 10]</th><th>[33, 29, 9]</th><th>[33, 28, 9]</th><th>[33, 29, 8]</th><th>[33, 28, 8]</th></tr>
+<tr><th>GTX3:DRP1A</th><th>[33, 29, 23]</th><th>[33, 28, 23]</th><th>[33, 29, 22]</th><th>[33, 28, 22]</th><th>[33, 29, 21]</th><th>[33, 28, 21]</th><th>[33, 29, 20]</th><th>[33, 28, 20]</th><th>[33, 29, 19]</th><th>[33, 28, 19]</th><th>[33, 29, 18]</th><th>[33, 28, 18]</th><th>[33, 29, 17]</th><th>[33, 28, 17]</th><th>[33, 29, 16]</th><th>[33, 28, 16]</th></tr>
+<tr><th>GTX3:DRP1B</th><th>[33, 29, 31]</th><th>[33, 28, 31]</th><th>[33, 29, 30]</th><th>[33, 28, 30]</th><th>[33, 29, 29]</th><th>[33, 28, 29]</th><th>[33, 29, 28]</th><th>[33, 28, 28]</th><th>[33, 29, 27]</th><th>[33, 28, 27]</th><th>[33, 29, 26]</th><th>[33, 28, 26]</th><th>[33, 29, 25]</th><th>[33, 28, 25]</th><th>[33, 29, 24]</th><th>[33, 28, 24]</th></tr>
+<tr><th>GTX3:DRP1C</th><th>[33, 29, 39]</th><th>[33, 28, 39]</th><th>[33, 29, 38]</th><th>[33, 28, 38]</th><th>[33, 29, 37]</th><th>[33, 28, 37]</th><th>[33, 29, 36]</th><th>[33, 28, 36]</th><th>[33, 29, 35]</th><th>[33, 28, 35]</th><th>[33, 29, 34]</th><th>[33, 28, 34]</th><th>[33, 29, 33]</th><th>[33, 28, 33]</th><th>[33, 29, 32]</th><th>[33, 28, 32]</th></tr>
+<tr><th>GTX3:DRP1D</th><th>[33, 29, 47]</th><th>[33, 28, 47]</th><th>[33, 29, 46]</th><th>[33, 28, 46]</th><th>[33, 29, 45]</th><th>[33, 28, 45]</th><th>[33, 29, 44]</th><th>[33, 28, 44]</th><th>[33, 29, 43]</th><th>[33, 28, 43]</th><th>[33, 29, 42]</th><th>[33, 28, 42]</th><th>[33, 29, 41]</th><th>[33, 28, 41]</th><th>[33, 29, 40]</th><th>[33, 28, 40]</th></tr>
+<tr><th>GTX3:DRP1E</th><th>[33, 29, 55]</th><th>[33, 28, 55]</th><th>[33, 29, 54]</th><th>[33, 28, 54]</th><th>[33, 29, 53]</th><th>[33, 28, 53]</th><th>[33, 29, 52]</th><th>[33, 28, 52]</th><th>[33, 29, 51]</th><th>[33, 28, 51]</th><th>[33, 29, 50]</th><th>[33, 28, 50]</th><th>[33, 29, 49]</th><th>[33, 28, 49]</th><th>[33, 29, 48]</th><th>[33, 28, 48]</th></tr>
+<tr><th>GTX3:DRP1F</th><th>[33, 29, 63]</th><th>[33, 28, 63]</th><th>[33, 29, 62]</th><th>[33, 28, 62]</th><th>[33, 29, 61]</th><th>[33, 28, 61]</th><th>[33, 29, 60]</th><th>[33, 28, 60]</th><th>[33, 29, 59]</th><th>[33, 28, 59]</th><th>[33, 29, 58]</th><th>[33, 28, 58]</th><th>[33, 29, 57]</th><th>[33, 28, 57]</th><th>[33, 29, 56]</th><th>[33, 28, 56]</th></tr>
+<tr><th>GTX3:DRP20</th><th>[34, 29, 7]</th><th>[34, 28, 7]</th><th>[34, 29, 6]</th><th>[34, 28, 6]</th><th>[34, 29, 5]</th><th>[34, 28, 5]</th><th>[34, 29, 4]</th><th>[34, 28, 4]</th><th>[34, 29, 3]</th><th>[34, 28, 3]</th><th>[34, 29, 2]</th><th>[34, 28, 2]</th><th>[34, 29, 1]</th><th>[34, 28, 1]</th><th>[34, 29, 0]</th><th>[34, 28, 0]</th></tr>
+<tr><th>GTX3:DRP21</th><th>[34, 29, 15]</th><th>[34, 28, 15]</th><th>[34, 29, 14]</th><th>[34, 28, 14]</th><th>[34, 29, 13]</th><th>[34, 28, 13]</th><th>[34, 29, 12]</th><th>[34, 28, 12]</th><th>[34, 29, 11]</th><th>[34, 28, 11]</th><th>[34, 29, 10]</th><th>[34, 28, 10]</th><th>[34, 29, 9]</th><th>[34, 28, 9]</th><th>[34, 29, 8]</th><th>[34, 28, 8]</th></tr>
+<tr><th>GTX3:DRP22</th><th>[34, 29, 23]</th><th>[34, 28, 23]</th><th>[34, 29, 22]</th><th>[34, 28, 22]</th><th>[34, 29, 21]</th><th>[34, 28, 21]</th><th>[34, 29, 20]</th><th>[34, 28, 20]</th><th>[34, 29, 19]</th><th>[34, 28, 19]</th><th>[34, 29, 18]</th><th>[34, 28, 18]</th><th>[34, 29, 17]</th><th>[34, 28, 17]</th><th>[34, 29, 16]</th><th>[34, 28, 16]</th></tr>
+<tr><th>GTX3:DRP23</th><th>[34, 29, 31]</th><th>[34, 28, 31]</th><th>[34, 29, 30]</th><th>[34, 28, 30]</th><th>[34, 29, 29]</th><th>[34, 28, 29]</th><th>[34, 29, 28]</th><th>[34, 28, 28]</th><th>[34, 29, 27]</th><th>[34, 28, 27]</th><th>[34, 29, 26]</th><th>[34, 28, 26]</th><th>[34, 29, 25]</th><th>[34, 28, 25]</th><th>[34, 29, 24]</th><th>[34, 28, 24]</th></tr>
+<tr><th>GTX3:DRP24</th><th>[34, 29, 39]</th><th>[34, 28, 39]</th><th>[34, 29, 38]</th><th>[34, 28, 38]</th><th>[34, 29, 37]</th><th>[34, 28, 37]</th><th>[34, 29, 36]</th><th>[34, 28, 36]</th><th>[34, 29, 35]</th><th>[34, 28, 35]</th><th>[34, 29, 34]</th><th>[34, 28, 34]</th><th>[34, 29, 33]</th><th>[34, 28, 33]</th><th>[34, 29, 32]</th><th>[34, 28, 32]</th></tr>
+<tr><th>GTX3:DRP25</th><th>[34, 29, 47]</th><th>[34, 28, 47]</th><th>[34, 29, 46]</th><th>[34, 28, 46]</th><th>[34, 29, 45]</th><th>[34, 28, 45]</th><th>[34, 29, 44]</th><th>[34, 28, 44]</th><th>[34, 29, 43]</th><th>[34, 28, 43]</th><th>[34, 29, 42]</th><th>[34, 28, 42]</th><th>[34, 29, 41]</th><th>[34, 28, 41]</th><th>[34, 29, 40]</th><th>[34, 28, 40]</th></tr>
+<tr><th>GTX3:DRP26</th><th>[34, 29, 55]</th><th>[34, 28, 55]</th><th>[34, 29, 54]</th><th>[34, 28, 54]</th><th>[34, 29, 53]</th><th>[34, 28, 53]</th><th>[34, 29, 52]</th><th>[34, 28, 52]</th><th>[34, 29, 51]</th><th>[34, 28, 51]</th><th>[34, 29, 50]</th><th>[34, 28, 50]</th><th>[34, 29, 49]</th><th>[34, 28, 49]</th><th>[34, 29, 48]</th><th>[34, 28, 48]</th></tr>
+<tr><th>GTX3:DRP27</th><th>[34, 29, 63]</th><th>[34, 28, 63]</th><th>[34, 29, 62]</th><th>[34, 28, 62]</th><th>[34, 29, 61]</th><th>[34, 28, 61]</th><th>[34, 29, 60]</th><th>[34, 28, 60]</th><th>[34, 29, 59]</th><th>[34, 28, 59]</th><th>[34, 29, 58]</th><th>[34, 28, 58]</th><th>[34, 29, 57]</th><th>[34, 28, 57]</th><th>[34, 29, 56]</th><th>[34, 28, 56]</th></tr>
+<tr><th>GTX3:DRP28</th><th>[35, 29, 7]</th><th>[35, 28, 7]</th><th>[35, 29, 6]</th><th>[35, 28, 6]</th><th>[35, 29, 5]</th><th>[35, 28, 5]</th><th>[35, 29, 4]</th><th>[35, 28, 4]</th><th>[35, 29, 3]</th><th>[35, 28, 3]</th><th>[35, 29, 2]</th><th>[35, 28, 2]</th><th>[35, 29, 1]</th><th>[35, 28, 1]</th><th>[35, 29, 0]</th><th>[35, 28, 0]</th></tr>
+<tr><th>GTX3:DRP29</th><th>[35, 29, 15]</th><th>[35, 28, 15]</th><th>[35, 29, 14]</th><th>[35, 28, 14]</th><th>[35, 29, 13]</th><th>[35, 28, 13]</th><th>[35, 29, 12]</th><th>[35, 28, 12]</th><th>[35, 29, 11]</th><th>[35, 28, 11]</th><th>[35, 29, 10]</th><th>[35, 28, 10]</th><th>[35, 29, 9]</th><th>[35, 28, 9]</th><th>[35, 29, 8]</th><th>[35, 28, 8]</th></tr>
+<tr><th>GTX3:DRP2A</th><th>[35, 29, 23]</th><th>[35, 28, 23]</th><th>[35, 29, 22]</th><th>[35, 28, 22]</th><th>[35, 29, 21]</th><th>[35, 28, 21]</th><th>[35, 29, 20]</th><th>[35, 28, 20]</th><th>[35, 29, 19]</th><th>[35, 28, 19]</th><th>[35, 29, 18]</th><th>[35, 28, 18]</th><th>[35, 29, 17]</th><th>[35, 28, 17]</th><th>[35, 29, 16]</th><th>[35, 28, 16]</th></tr>
+<tr><th>GTX3:DRP2B</th><th>[35, 29, 31]</th><th>[35, 28, 31]</th><th>[35, 29, 30]</th><th>[35, 28, 30]</th><th>[35, 29, 29]</th><th>[35, 28, 29]</th><th>[35, 29, 28]</th><th>[35, 28, 28]</th><th>[35, 29, 27]</th><th>[35, 28, 27]</th><th>[35, 29, 26]</th><th>[35, 28, 26]</th><th>[35, 29, 25]</th><th>[35, 28, 25]</th><th>[35, 29, 24]</th><th>[35, 28, 24]</th></tr>
+<tr><th>GTX3:DRP2C</th><th>[35, 29, 39]</th><th>[35, 28, 39]</th><th>[35, 29, 38]</th><th>[35, 28, 38]</th><th>[35, 29, 37]</th><th>[35, 28, 37]</th><th>[35, 29, 36]</th><th>[35, 28, 36]</th><th>[35, 29, 35]</th><th>[35, 28, 35]</th><th>[35, 29, 34]</th><th>[35, 28, 34]</th><th>[35, 29, 33]</th><th>[35, 28, 33]</th><th>[35, 29, 32]</th><th>[35, 28, 32]</th></tr>
+<tr><th>GTX3:DRP2D</th><th>[35, 29, 47]</th><th>[35, 28, 47]</th><th>[35, 29, 46]</th><th>[35, 28, 46]</th><th>[35, 29, 45]</th><th>[35, 28, 45]</th><th>[35, 29, 44]</th><th>[35, 28, 44]</th><th>[35, 29, 43]</th><th>[35, 28, 43]</th><th>[35, 29, 42]</th><th>[35, 28, 42]</th><th>[35, 29, 41]</th><th>[35, 28, 41]</th><th>[35, 29, 40]</th><th>[35, 28, 40]</th></tr>
+<tr><th>GTX3:DRP2E</th><th>[35, 29, 55]</th><th>[35, 28, 55]</th><th>[35, 29, 54]</th><th>[35, 28, 54]</th><th>[35, 29, 53]</th><th>[35, 28, 53]</th><th>[35, 29, 52]</th><th>[35, 28, 52]</th><th>[35, 29, 51]</th><th>[35, 28, 51]</th><th>[35, 29, 50]</th><th>[35, 28, 50]</th><th>[35, 29, 49]</th><th>[35, 28, 49]</th><th>[35, 29, 48]</th><th>[35, 28, 48]</th></tr>
+<tr><th>GTX3:DRP2F</th><th>[35, 29, 63]</th><th>[35, 28, 63]</th><th>[35, 29, 62]</th><th>[35, 28, 62]</th><th>[35, 29, 61]</th><th>[35, 28, 61]</th><th>[35, 29, 60]</th><th>[35, 28, 60]</th><th>[35, 29, 59]</th><th>[35, 28, 59]</th><th>[35, 29, 58]</th><th>[35, 28, 58]</th><th>[35, 29, 57]</th><th>[35, 28, 57]</th><th>[35, 29, 56]</th><th>[35, 28, 56]</th></tr>
+<tr><th>GTX3:DRP30</th><th>[36, 29, 7]</th><th>[36, 28, 7]</th><th>[36, 29, 6]</th><th>[36, 28, 6]</th><th>[36, 29, 5]</th><th>[36, 28, 5]</th><th>[36, 29, 4]</th><th>[36, 28, 4]</th><th>[36, 29, 3]</th><th>[36, 28, 3]</th><th>[36, 29, 2]</th><th>[36, 28, 2]</th><th>[36, 29, 1]</th><th>[36, 28, 1]</th><th>[36, 29, 0]</th><th>[36, 28, 0]</th></tr>
+<tr><th>GTX3:DRP31</th><th>[36, 29, 15]</th><th>[36, 28, 15]</th><th>[36, 29, 14]</th><th>[36, 28, 14]</th><th>[36, 29, 13]</th><th>[36, 28, 13]</th><th>[36, 29, 12]</th><th>[36, 28, 12]</th><th>[36, 29, 11]</th><th>[36, 28, 11]</th><th>[36, 29, 10]</th><th>[36, 28, 10]</th><th>[36, 29, 9]</th><th>[36, 28, 9]</th><th>[36, 29, 8]</th><th>[36, 28, 8]</th></tr>
+<tr><th>GTX3:DRP32</th><th>[36, 29, 23]</th><th>[36, 28, 23]</th><th>[36, 29, 22]</th><th>[36, 28, 22]</th><th>[36, 29, 21]</th><th>[36, 28, 21]</th><th>[36, 29, 20]</th><th>[36, 28, 20]</th><th>[36, 29, 19]</th><th>[36, 28, 19]</th><th>[36, 29, 18]</th><th>[36, 28, 18]</th><th>[36, 29, 17]</th><th>[36, 28, 17]</th><th>[36, 29, 16]</th><th>[36, 28, 16]</th></tr>
+<tr><th>GTX3:DRP33</th><th>[36, 29, 31]</th><th>[36, 28, 31]</th><th>[36, 29, 30]</th><th>[36, 28, 30]</th><th>[36, 29, 29]</th><th>[36, 28, 29]</th><th>[36, 29, 28]</th><th>[36, 28, 28]</th><th>[36, 29, 27]</th><th>[36, 28, 27]</th><th>[36, 29, 26]</th><th>[36, 28, 26]</th><th>[36, 29, 25]</th><th>[36, 28, 25]</th><th>[36, 29, 24]</th><th>[36, 28, 24]</th></tr>
+<tr><th>GTX3:DRP34</th><th>[36, 29, 39]</th><th>[36, 28, 39]</th><th>[36, 29, 38]</th><th>[36, 28, 38]</th><th>[36, 29, 37]</th><th>[36, 28, 37]</th><th>[36, 29, 36]</th><th>[36, 28, 36]</th><th>[36, 29, 35]</th><th>[36, 28, 35]</th><th>[36, 29, 34]</th><th>[36, 28, 34]</th><th>[36, 29, 33]</th><th>[36, 28, 33]</th><th>[36, 29, 32]</th><th>[36, 28, 32]</th></tr>
+<tr><th>GTX3:DRP35</th><th>[36, 29, 47]</th><th>[36, 28, 47]</th><th>[36, 29, 46]</th><th>[36, 28, 46]</th><th>[36, 29, 45]</th><th>[36, 28, 45]</th><th>[36, 29, 44]</th><th>[36, 28, 44]</th><th>[36, 29, 43]</th><th>[36, 28, 43]</th><th>[36, 29, 42]</th><th>[36, 28, 42]</th><th>[36, 29, 41]</th><th>[36, 28, 41]</th><th>[36, 29, 40]</th><th>[36, 28, 40]</th></tr>
+<tr><th>GTX3:DRP36</th><th>[36, 29, 55]</th><th>[36, 28, 55]</th><th>[36, 29, 54]</th><th>[36, 28, 54]</th><th>[36, 29, 53]</th><th>[36, 28, 53]</th><th>[36, 29, 52]</th><th>[36, 28, 52]</th><th>[36, 29, 51]</th><th>[36, 28, 51]</th><th>[36, 29, 50]</th><th>[36, 28, 50]</th><th>[36, 29, 49]</th><th>[36, 28, 49]</th><th>[36, 29, 48]</th><th>[36, 28, 48]</th></tr>
+<tr><th>GTX3:DRP37</th><th>[36, 29, 63]</th><th>[36, 28, 63]</th><th>[36, 29, 62]</th><th>[36, 28, 62]</th><th>[36, 29, 61]</th><th>[36, 28, 61]</th><th>[36, 29, 60]</th><th>[36, 28, 60]</th><th>[36, 29, 59]</th><th>[36, 28, 59]</th><th>[36, 29, 58]</th><th>[36, 28, 58]</th><th>[36, 29, 57]</th><th>[36, 28, 57]</th><th>[36, 29, 56]</th><th>[36, 28, 56]</th></tr>
+<tr><th>GTX3:DRP38</th><th>[37, 29, 7]</th><th>[37, 28, 7]</th><th>[37, 29, 6]</th><th>[37, 28, 6]</th><th>[37, 29, 5]</th><th>[37, 28, 5]</th><th>[37, 29, 4]</th><th>[37, 28, 4]</th><th>[37, 29, 3]</th><th>[37, 28, 3]</th><th>[37, 29, 2]</th><th>[37, 28, 2]</th><th>[37, 29, 1]</th><th>[37, 28, 1]</th><th>[37, 29, 0]</th><th>[37, 28, 0]</th></tr>
+<tr><th>GTX3:DRP39</th><th>[37, 29, 15]</th><th>[37, 28, 15]</th><th>[37, 29, 14]</th><th>[37, 28, 14]</th><th>[37, 29, 13]</th><th>[37, 28, 13]</th><th>[37, 29, 12]</th><th>[37, 28, 12]</th><th>[37, 29, 11]</th><th>[37, 28, 11]</th><th>[37, 29, 10]</th><th>[37, 28, 10]</th><th>[37, 29, 9]</th><th>[37, 28, 9]</th><th>[37, 29, 8]</th><th>[37, 28, 8]</th></tr>
+<tr><th>GTX3:DRP3A</th><th>[37, 29, 23]</th><th>[37, 28, 23]</th><th>[37, 29, 22]</th><th>[37, 28, 22]</th><th>[37, 29, 21]</th><th>[37, 28, 21]</th><th>[37, 29, 20]</th><th>[37, 28, 20]</th><th>[37, 29, 19]</th><th>[37, 28, 19]</th><th>[37, 29, 18]</th><th>[37, 28, 18]</th><th>[37, 29, 17]</th><th>[37, 28, 17]</th><th>[37, 29, 16]</th><th>[37, 28, 16]</th></tr>
+<tr><th>GTX3:DRP3B</th><th>[37, 29, 31]</th><th>[37, 28, 31]</th><th>[37, 29, 30]</th><th>[37, 28, 30]</th><th>[37, 29, 29]</th><th>[37, 28, 29]</th><th>[37, 29, 28]</th><th>[37, 28, 28]</th><th>[37, 29, 27]</th><th>[37, 28, 27]</th><th>[37, 29, 26]</th><th>[37, 28, 26]</th><th>[37, 29, 25]</th><th>[37, 28, 25]</th><th>[37, 29, 24]</th><th>[37, 28, 24]</th></tr>
+<tr><th>GTX3:DRP3C</th><th>[37, 29, 39]</th><th>[37, 28, 39]</th><th>[37, 29, 38]</th><th>[37, 28, 38]</th><th>[37, 29, 37]</th><th>[37, 28, 37]</th><th>[37, 29, 36]</th><th>[37, 28, 36]</th><th>[37, 29, 35]</th><th>[37, 28, 35]</th><th>[37, 29, 34]</th><th>[37, 28, 34]</th><th>[37, 29, 33]</th><th>[37, 28, 33]</th><th>[37, 29, 32]</th><th>[37, 28, 32]</th></tr>
+<tr><th>GTX3:DRP3D</th><th>[37, 29, 47]</th><th>[37, 28, 47]</th><th>[37, 29, 46]</th><th>[37, 28, 46]</th><th>[37, 29, 45]</th><th>[37, 28, 45]</th><th>[37, 29, 44]</th><th>[37, 28, 44]</th><th>[37, 29, 43]</th><th>[37, 28, 43]</th><th>[37, 29, 42]</th><th>[37, 28, 42]</th><th>[37, 29, 41]</th><th>[37, 28, 41]</th><th>[37, 29, 40]</th><th>[37, 28, 40]</th></tr>
+<tr><th>GTX3:DRP3E</th><th>[37, 29, 55]</th><th>[37, 28, 55]</th><th>[37, 29, 54]</th><th>[37, 28, 54]</th><th>[37, 29, 53]</th><th>[37, 28, 53]</th><th>[37, 29, 52]</th><th>[37, 28, 52]</th><th>[37, 29, 51]</th><th>[37, 28, 51]</th><th>[37, 29, 50]</th><th>[37, 28, 50]</th><th>[37, 29, 49]</th><th>[37, 28, 49]</th><th>[37, 29, 48]</th><th>[37, 28, 48]</th></tr>
+<tr><th>GTX3:DRP3F</th><th>[37, 29, 63]</th><th>[37, 28, 63]</th><th>[37, 29, 62]</th><th>[37, 28, 62]</th><th>[37, 29, 61]</th><th>[37, 28, 61]</th><th>[37, 29, 60]</th><th>[37, 28, 60]</th><th>[37, 29, 59]</th><th>[37, 28, 59]</th><th>[37, 29, 58]</th><th>[37, 28, 58]</th><th>[37, 29, 57]</th><th>[37, 28, 57]</th><th>[37, 29, 56]</th><th>[37, 28, 56]</th></tr>
+<tr><th>GTX3:DRP40</th><th>[38, 29, 7]</th><th>[38, 28, 7]</th><th>[38, 29, 6]</th><th>[38, 28, 6]</th><th>[38, 29, 5]</th><th>[38, 28, 5]</th><th>[38, 29, 4]</th><th>[38, 28, 4]</th><th>[38, 29, 3]</th><th>[38, 28, 3]</th><th>[38, 29, 2]</th><th>[38, 28, 2]</th><th>[38, 29, 1]</th><th>[38, 28, 1]</th><th>[38, 29, 0]</th><th>[38, 28, 0]</th></tr>
+<tr><th>GTX3:DRP41</th><th>[38, 29, 15]</th><th>[38, 28, 15]</th><th>[38, 29, 14]</th><th>[38, 28, 14]</th><th>[38, 29, 13]</th><th>[38, 28, 13]</th><th>[38, 29, 12]</th><th>[38, 28, 12]</th><th>[38, 29, 11]</th><th>[38, 28, 11]</th><th>[38, 29, 10]</th><th>[38, 28, 10]</th><th>[38, 29, 9]</th><th>[38, 28, 9]</th><th>[38, 29, 8]</th><th>[38, 28, 8]</th></tr>
+<tr><th>GTX3:DRP42</th><th>[38, 29, 23]</th><th>[38, 28, 23]</th><th>[38, 29, 22]</th><th>[38, 28, 22]</th><th>[38, 29, 21]</th><th>[38, 28, 21]</th><th>[38, 29, 20]</th><th>[38, 28, 20]</th><th>[38, 29, 19]</th><th>[38, 28, 19]</th><th>[38, 29, 18]</th><th>[38, 28, 18]</th><th>[38, 29, 17]</th><th>[38, 28, 17]</th><th>[38, 29, 16]</th><th>[38, 28, 16]</th></tr>
+<tr><th>GTX3:DRP43</th><th>[38, 29, 31]</th><th>[38, 28, 31]</th><th>[38, 29, 30]</th><th>[38, 28, 30]</th><th>[38, 29, 29]</th><th>[38, 28, 29]</th><th>[38, 29, 28]</th><th>[38, 28, 28]</th><th>[38, 29, 27]</th><th>[38, 28, 27]</th><th>[38, 29, 26]</th><th>[38, 28, 26]</th><th>[38, 29, 25]</th><th>[38, 28, 25]</th><th>[38, 29, 24]</th><th>[38, 28, 24]</th></tr>
+<tr><th>GTX3:DRP44</th><th>[38, 29, 39]</th><th>[38, 28, 39]</th><th>[38, 29, 38]</th><th>[38, 28, 38]</th><th>[38, 29, 37]</th><th>[38, 28, 37]</th><th>[38, 29, 36]</th><th>[38, 28, 36]</th><th>[38, 29, 35]</th><th>[38, 28, 35]</th><th>[38, 29, 34]</th><th>[38, 28, 34]</th><th>[38, 29, 33]</th><th>[38, 28, 33]</th><th>[38, 29, 32]</th><th>[38, 28, 32]</th></tr>
+<tr><th>GTX3:DRP45</th><th>[38, 29, 47]</th><th>[38, 28, 47]</th><th>[38, 29, 46]</th><th>[38, 28, 46]</th><th>[38, 29, 45]</th><th>[38, 28, 45]</th><th>[38, 29, 44]</th><th>[38, 28, 44]</th><th>[38, 29, 43]</th><th>[38, 28, 43]</th><th>[38, 29, 42]</th><th>[38, 28, 42]</th><th>[38, 29, 41]</th><th>[38, 28, 41]</th><th>[38, 29, 40]</th><th>[38, 28, 40]</th></tr>
+<tr><th>GTX3:DRP46</th><th>[38, 29, 55]</th><th>[38, 28, 55]</th><th>[38, 29, 54]</th><th>[38, 28, 54]</th><th>[38, 29, 53]</th><th>[38, 28, 53]</th><th>[38, 29, 52]</th><th>[38, 28, 52]</th><th>[38, 29, 51]</th><th>[38, 28, 51]</th><th>[38, 29, 50]</th><th>[38, 28, 50]</th><th>[38, 29, 49]</th><th>[38, 28, 49]</th><th>[38, 29, 48]</th><th>[38, 28, 48]</th></tr>
+<tr><th>GTX3:DRP47</th><th>[38, 29, 63]</th><th>[38, 28, 63]</th><th>[38, 29, 62]</th><th>[38, 28, 62]</th><th>[38, 29, 61]</th><th>[38, 28, 61]</th><th>[38, 29, 60]</th><th>[38, 28, 60]</th><th>[38, 29, 59]</th><th>[38, 28, 59]</th><th>[38, 29, 58]</th><th>[38, 28, 58]</th><th>[38, 29, 57]</th><th>[38, 28, 57]</th><th>[38, 29, 56]</th><th>[38, 28, 56]</th></tr>
+<tr><th>GTX3:DRP48</th><th>[39, 29, 7]</th><th>[39, 28, 7]</th><th>[39, 29, 6]</th><th>[39, 28, 6]</th><th>[39, 29, 5]</th><th>[39, 28, 5]</th><th>[39, 29, 4]</th><th>[39, 28, 4]</th><th>[39, 29, 3]</th><th>[39, 28, 3]</th><th>[39, 29, 2]</th><th>[39, 28, 2]</th><th>[39, 29, 1]</th><th>[39, 28, 1]</th><th>[39, 29, 0]</th><th>[39, 28, 0]</th></tr>
+<tr><th>GTX3:DRP49</th><th>[39, 29, 15]</th><th>[39, 28, 15]</th><th>[39, 29, 14]</th><th>[39, 28, 14]</th><th>[39, 29, 13]</th><th>[39, 28, 13]</th><th>[39, 29, 12]</th><th>[39, 28, 12]</th><th>[39, 29, 11]</th><th>[39, 28, 11]</th><th>[39, 29, 10]</th><th>[39, 28, 10]</th><th>[39, 29, 9]</th><th>[39, 28, 9]</th><th>[39, 29, 8]</th><th>[39, 28, 8]</th></tr>
+<tr><th>GTX3:DRP4A</th><th>[39, 29, 23]</th><th>[39, 28, 23]</th><th>[39, 29, 22]</th><th>[39, 28, 22]</th><th>[39, 29, 21]</th><th>[39, 28, 21]</th><th>[39, 29, 20]</th><th>[39, 28, 20]</th><th>[39, 29, 19]</th><th>[39, 28, 19]</th><th>[39, 29, 18]</th><th>[39, 28, 18]</th><th>[39, 29, 17]</th><th>[39, 28, 17]</th><th>[39, 29, 16]</th><th>[39, 28, 16]</th></tr>
+<tr><th>GTX3:DRP4B</th><th>[39, 29, 31]</th><th>[39, 28, 31]</th><th>[39, 29, 30]</th><th>[39, 28, 30]</th><th>[39, 29, 29]</th><th>[39, 28, 29]</th><th>[39, 29, 28]</th><th>[39, 28, 28]</th><th>[39, 29, 27]</th><th>[39, 28, 27]</th><th>[39, 29, 26]</th><th>[39, 28, 26]</th><th>[39, 29, 25]</th><th>[39, 28, 25]</th><th>[39, 29, 24]</th><th>[39, 28, 24]</th></tr>
+<tr><th>GTX3:DRP4C</th><th>[39, 29, 39]</th><th>[39, 28, 39]</th><th>[39, 29, 38]</th><th>[39, 28, 38]</th><th>[39, 29, 37]</th><th>[39, 28, 37]</th><th>[39, 29, 36]</th><th>[39, 28, 36]</th><th>[39, 29, 35]</th><th>[39, 28, 35]</th><th>[39, 29, 34]</th><th>[39, 28, 34]</th><th>[39, 29, 33]</th><th>[39, 28, 33]</th><th>[39, 29, 32]</th><th>[39, 28, 32]</th></tr>
+<tr><th>GTX3:DRP4D</th><th>[39, 29, 47]</th><th>[39, 28, 47]</th><th>[39, 29, 46]</th><th>[39, 28, 46]</th><th>[39, 29, 45]</th><th>[39, 28, 45]</th><th>[39, 29, 44]</th><th>[39, 28, 44]</th><th>[39, 29, 43]</th><th>[39, 28, 43]</th><th>[39, 29, 42]</th><th>[39, 28, 42]</th><th>[39, 29, 41]</th><th>[39, 28, 41]</th><th>[39, 29, 40]</th><th>[39, 28, 40]</th></tr>
+<tr><th>GTX3:DRP4E</th><th>[39, 29, 55]</th><th>[39, 28, 55]</th><th>[39, 29, 54]</th><th>[39, 28, 54]</th><th>[39, 29, 53]</th><th>[39, 28, 53]</th><th>[39, 29, 52]</th><th>[39, 28, 52]</th><th>[39, 29, 51]</th><th>[39, 28, 51]</th><th>[39, 29, 50]</th><th>[39, 28, 50]</th><th>[39, 29, 49]</th><th>[39, 28, 49]</th><th>[39, 29, 48]</th><th>[39, 28, 48]</th></tr>
+<tr><th>GTX3:DRP4F</th><th>[39, 29, 63]</th><th>[39, 28, 63]</th><th>[39, 29, 62]</th><th>[39, 28, 62]</th><th>[39, 29, 61]</th><th>[39, 28, 61]</th><th>[39, 29, 60]</th><th>[39, 28, 60]</th><th>[39, 29, 59]</th><th>[39, 28, 59]</th><th>[39, 29, 58]</th><th>[39, 28, 58]</th><th>[39, 29, 57]</th><th>[39, 28, 57]</th><th>[39, 29, 56]</th><th>[39, 28, 56]</th></tr>
+<tr><th>GTX3:RXUSRCLK_DLY</th><th>[30, 29, 23]</th><th>[30, 28, 23]</th><th>[30, 29, 22]</th><th>[30, 28, 22]</th><th>[30, 29, 21]</th><th>[30, 28, 21]</th><th>[30, 29, 20]</th><th>[30, 28, 20]</th><th>[30, 29, 19]</th><th>[30, 28, 19]</th><th>[30, 29, 18]</th><th>[30, 28, 18]</th><th>[30, 29, 17]</th><th>[30, 28, 17]</th><th>[30, 29, 16]</th><th>[30, 28, 16]</th></tr>
+<tr><td>Non-inverted</td><td>[15]</td><td>[14]</td><td>[13]</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:PMA_RX_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:PMA_RX_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:PMA_RX_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:PMA_RX_CFG"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:PMA_RX_CFG</th><th>[0, 28, 12]</th><th>[0, 29, 11]</th><th>[0, 28, 11]</th><th>[0, 29, 10]</th><th>[0, 28, 10]</th><th>[0, 29, 9]</th><th>[0, 28, 9]</th><th>[0, 29, 8]</th><th>[0, 28, 8]</th><th>[0, 29, 7]</th><th>[0, 28, 7]</th><th>[0, 29, 6]</th><th>[0, 28, 6]</th><th>[0, 29, 5]</th><th>[0, 28, 5]</th><th>[0, 29, 4]</th><th>[0, 28, 4]</th><th>[0, 29, 3]</th><th>[0, 28, 3]</th><th>[0, 29, 2]</th><th>[0, 28, 2]</th><th>[0, 29, 1]</th><th>[0, 28, 1]</th><th>[0, 29, 0]</th><th>[0, 28, 0]</th></tr>
+<tr><th>GTX1:PMA_RX_CFG</th><th>[10, 28, 12]</th><th>[10, 29, 11]</th><th>[10, 28, 11]</th><th>[10, 29, 10]</th><th>[10, 28, 10]</th><th>[10, 29, 9]</th><th>[10, 28, 9]</th><th>[10, 29, 8]</th><th>[10, 28, 8]</th><th>[10, 29, 7]</th><th>[10, 28, 7]</th><th>[10, 29, 6]</th><th>[10, 28, 6]</th><th>[10, 29, 5]</th><th>[10, 28, 5]</th><th>[10, 29, 4]</th><th>[10, 28, 4]</th><th>[10, 29, 3]</th><th>[10, 28, 3]</th><th>[10, 29, 2]</th><th>[10, 28, 2]</th><th>[10, 29, 1]</th><th>[10, 28, 1]</th><th>[10, 29, 0]</th><th>[10, 28, 0]</th></tr>
+<tr><th>GTX2:PMA_RX_CFG</th><th>[20, 28, 12]</th><th>[20, 29, 11]</th><th>[20, 28, 11]</th><th>[20, 29, 10]</th><th>[20, 28, 10]</th><th>[20, 29, 9]</th><th>[20, 28, 9]</th><th>[20, 29, 8]</th><th>[20, 28, 8]</th><th>[20, 29, 7]</th><th>[20, 28, 7]</th><th>[20, 29, 6]</th><th>[20, 28, 6]</th><th>[20, 29, 5]</th><th>[20, 28, 5]</th><th>[20, 29, 4]</th><th>[20, 28, 4]</th><th>[20, 29, 3]</th><th>[20, 28, 3]</th><th>[20, 29, 2]</th><th>[20, 28, 2]</th><th>[20, 29, 1]</th><th>[20, 28, 1]</th><th>[20, 29, 0]</th><th>[20, 28, 0]</th></tr>
+<tr><th>GTX3:PMA_RX_CFG</th><th>[30, 28, 12]</th><th>[30, 29, 11]</th><th>[30, 28, 11]</th><th>[30, 29, 10]</th><th>[30, 28, 10]</th><th>[30, 29, 9]</th><th>[30, 28, 9]</th><th>[30, 29, 8]</th><th>[30, 28, 8]</th><th>[30, 29, 7]</th><th>[30, 28, 7]</th><th>[30, 29, 6]</th><th>[30, 28, 6]</th><th>[30, 29, 5]</th><th>[30, 28, 5]</th><th>[30, 29, 4]</th><th>[30, 28, 4]</th><th>[30, 29, 3]</th><th>[30, 28, 3]</th><th>[30, 29, 2]</th><th>[30, 28, 2]</th><th>[30, 29, 1]</th><th>[30, 28, 1]</th><th>[30, 29, 0]</th><th>[30, 28, 0]</th></tr>
+<tr><td>Non-inverted</td><td>[24]</td><td>[23]</td><td>[22]</td><td>[21]</td><td>[20]</td><td>[19]</td><td>[18]</td><td>[17]</td><td>[16]</td><td>[15]</td><td>[14]</td><td>[13]</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:BIAS_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:BIAS_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:BIAS_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:BIAS_CFG"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:BIAS_CFG</th><th>[2, 28, 61]</th><th>[0, 29, 31]</th><th>[0, 28, 31]</th><th>[0, 29, 30]</th><th>[0, 28, 30]</th><th>[0, 29, 29]</th><th>[0, 28, 29]</th><th>[0, 29, 28]</th><th>[0, 28, 28]</th><th>[0, 29, 27]</th><th>[0, 28, 27]</th><th>[0, 29, 26]</th><th>[0, 28, 26]</th><th>[0, 29, 25]</th><th>[0, 28, 25]</th><th>[0, 29, 24]</th><th>[0, 28, 24]</th></tr>
+<tr><th>GTX1:BIAS_CFG</th><th>[12, 28, 61]</th><th>[10, 29, 31]</th><th>[10, 28, 31]</th><th>[10, 29, 30]</th><th>[10, 28, 30]</th><th>[10, 29, 29]</th><th>[10, 28, 29]</th><th>[10, 29, 28]</th><th>[10, 28, 28]</th><th>[10, 29, 27]</th><th>[10, 28, 27]</th><th>[10, 29, 26]</th><th>[10, 28, 26]</th><th>[10, 29, 25]</th><th>[10, 28, 25]</th><th>[10, 29, 24]</th><th>[10, 28, 24]</th></tr>
+<tr><th>GTX2:BIAS_CFG</th><th>[22, 28, 61]</th><th>[20, 29, 31]</th><th>[20, 28, 31]</th><th>[20, 29, 30]</th><th>[20, 28, 30]</th><th>[20, 29, 29]</th><th>[20, 28, 29]</th><th>[20, 29, 28]</th><th>[20, 28, 28]</th><th>[20, 29, 27]</th><th>[20, 28, 27]</th><th>[20, 29, 26]</th><th>[20, 28, 26]</th><th>[20, 29, 25]</th><th>[20, 28, 25]</th><th>[20, 29, 24]</th><th>[20, 28, 24]</th></tr>
+<tr><th>GTX3:BIAS_CFG</th><th>[32, 28, 61]</th><th>[30, 29, 31]</th><th>[30, 28, 31]</th><th>[30, 29, 30]</th><th>[30, 28, 30]</th><th>[30, 29, 29]</th><th>[30, 28, 29]</th><th>[30, 29, 28]</th><th>[30, 28, 28]</th><th>[30, 29, 27]</th><th>[30, 28, 27]</th><th>[30, 29, 26]</th><th>[30, 28, 26]</th><th>[30, 29, 25]</th><th>[30, 28, 25]</th><th>[30, 29, 24]</th><th>[30, 28, 24]</th></tr>
+<tr><td>Non-inverted</td><td>[16]</td><td>[15]</td><td>[14]</td><td>[13]</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:A_RXEQMIX"></div>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_1"></div>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_2"></div>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_3"></div>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_4"></div>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_1"></div>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_2"></div>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_3"></div>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_4"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_1"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_2"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_3"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_4"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_1"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_2"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_3"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_4"></div>
+<div id="bits-xc6v-GTX-GTX0:COMMA_10B_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX0:MCOMMA_10B_VALUE"></div>
+<div id="bits-xc6v-GTX-GTX0:PCOMMA_10B_VALUE"></div>
+<div id="bits-xc6v-GTX-GTX0:POWER_SAVE"></div>
+<div id="bits-xc6v-GTX-GTX0:RXRECCLK_DLY"></div>
+<div id="bits-xc6v-GTX-GTX0:TRANS_TIME_TO_P2"></div>
+<div id="bits-xc6v-GTX-GTX0:TXOUTCLK_DLY"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXEQMIX"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_1"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_2"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_3"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_4"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_1"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_2"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_3"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_4"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_1"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_2"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_3"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_4"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_1"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_2"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_3"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_4"></div>
+<div id="bits-xc6v-GTX-GTX1:COMMA_10B_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX1:MCOMMA_10B_VALUE"></div>
+<div id="bits-xc6v-GTX-GTX1:PCOMMA_10B_VALUE"></div>
+<div id="bits-xc6v-GTX-GTX1:POWER_SAVE"></div>
+<div id="bits-xc6v-GTX-GTX1:RXRECCLK_DLY"></div>
+<div id="bits-xc6v-GTX-GTX1:TRANS_TIME_TO_P2"></div>
+<div id="bits-xc6v-GTX-GTX1:TXOUTCLK_DLY"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXEQMIX"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_1"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_2"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_3"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_4"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_1"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_2"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_3"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_4"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_1"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_2"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_3"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_4"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_1"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_2"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_3"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_4"></div>
+<div id="bits-xc6v-GTX-GTX2:COMMA_10B_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX2:MCOMMA_10B_VALUE"></div>
+<div id="bits-xc6v-GTX-GTX2:PCOMMA_10B_VALUE"></div>
+<div id="bits-xc6v-GTX-GTX2:POWER_SAVE"></div>
+<div id="bits-xc6v-GTX-GTX2:RXRECCLK_DLY"></div>
+<div id="bits-xc6v-GTX-GTX2:TRANS_TIME_TO_P2"></div>
+<div id="bits-xc6v-GTX-GTX2:TXOUTCLK_DLY"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXEQMIX"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_1"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_2"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_3"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_4"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_1"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_2"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_3"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_4"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_1"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_2"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_3"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_4"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_1"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_2"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_3"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_4"></div>
+<div id="bits-xc6v-GTX-GTX3:COMMA_10B_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX3:MCOMMA_10B_VALUE"></div>
+<div id="bits-xc6v-GTX-GTX3:PCOMMA_10B_VALUE"></div>
+<div id="bits-xc6v-GTX-GTX3:POWER_SAVE"></div>
+<div id="bits-xc6v-GTX-GTX3:RXRECCLK_DLY"></div>
+<div id="bits-xc6v-GTX-GTX3:TRANS_TIME_TO_P2"></div>
+<div id="bits-xc6v-GTX-GTX3:TXOUTCLK_DLY"></div>
+<div id="bits-xc6v-GTX-IBUFDS_GTX0:REFCLKOUT_DLY"></div>
+<div id="bits-xc6v-GTX-IBUFDS_GTX1:REFCLKOUT_DLY"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:A_RXEQMIX</th><th>[8, 29, 4]</th><th>[8, 28, 4]</th><th>[8, 29, 3]</th><th>[8, 28, 3]</th><th>[8, 29, 2]</th><th>[8, 28, 2]</th><th>[8, 29, 1]</th><th>[8, 28, 1]</th><th>[8, 29, 0]</th><th>[8, 28, 0]</th></tr>
+<tr><th>GTX0:CHAN_BOND_SEQ_1_1</th><th>[0, 29, 36]</th><th>[0, 28, 36]</th><th>[0, 29, 35]</th><th>[0, 28, 35]</th><th>[0, 29, 34]</th><th>[0, 28, 34]</th><th>[0, 29, 33]</th><th>[0, 28, 33]</th><th>[0, 29, 32]</th><th>[0, 28, 32]</th></tr>
+<tr><th>GTX0:CHAN_BOND_SEQ_1_2</th><th>[0, 29, 44]</th><th>[0, 28, 44]</th><th>[0, 29, 43]</th><th>[0, 28, 43]</th><th>[0, 29, 42]</th><th>[0, 28, 42]</th><th>[0, 29, 41]</th><th>[0, 28, 41]</th><th>[0, 29, 40]</th><th>[0, 28, 40]</th></tr>
+<tr><th>GTX0:CHAN_BOND_SEQ_1_3</th><th>[0, 29, 52]</th><th>[0, 28, 52]</th><th>[0, 29, 51]</th><th>[0, 28, 51]</th><th>[0, 29, 50]</th><th>[0, 28, 50]</th><th>[0, 29, 49]</th><th>[0, 28, 49]</th><th>[0, 29, 48]</th><th>[0, 28, 48]</th></tr>
+<tr><th>GTX0:CHAN_BOND_SEQ_1_4</th><th>[0, 29, 60]</th><th>[0, 28, 60]</th><th>[0, 29, 59]</th><th>[0, 28, 59]</th><th>[0, 29, 58]</th><th>[0, 28, 58]</th><th>[0, 29, 57]</th><th>[0, 28, 57]</th><th>[0, 29, 56]</th><th>[0, 28, 56]</th></tr>
+<tr><th>GTX0:CHAN_BOND_SEQ_2_1</th><th>[1, 29, 4]</th><th>[1, 28, 4]</th><th>[1, 29, 3]</th><th>[1, 28, 3]</th><th>[1, 29, 2]</th><th>[1, 28, 2]</th><th>[1, 29, 1]</th><th>[1, 28, 1]</th><th>[1, 29, 0]</th><th>[1, 28, 0]</th></tr>
+<tr><th>GTX0:CHAN_BOND_SEQ_2_2</th><th>[1, 29, 12]</th><th>[1, 28, 12]</th><th>[1, 29, 11]</th><th>[1, 28, 11]</th><th>[1, 29, 10]</th><th>[1, 28, 10]</th><th>[1, 29, 9]</th><th>[1, 28, 9]</th><th>[1, 29, 8]</th><th>[1, 28, 8]</th></tr>
+<tr><th>GTX0:CHAN_BOND_SEQ_2_3</th><th>[1, 29, 20]</th><th>[1, 28, 20]</th><th>[1, 29, 19]</th><th>[1, 28, 19]</th><th>[1, 29, 18]</th><th>[1, 28, 18]</th><th>[1, 29, 17]</th><th>[1, 28, 17]</th><th>[1, 29, 16]</th><th>[1, 28, 16]</th></tr>
+<tr><th>GTX0:CHAN_BOND_SEQ_2_4</th><th>[1, 29, 28]</th><th>[1, 28, 28]</th><th>[1, 29, 27]</th><th>[1, 28, 27]</th><th>[1, 29, 26]</th><th>[1, 28, 26]</th><th>[1, 29, 25]</th><th>[1, 28, 25]</th><th>[1, 29, 24]</th><th>[1, 28, 24]</th></tr>
+<tr><th>GTX0:CLK_COR_SEQ_1_1</th><th>[1, 29, 44]</th><th>[1, 28, 44]</th><th>[1, 29, 43]</th><th>[1, 28, 43]</th><th>[1, 29, 42]</th><th>[1, 28, 42]</th><th>[1, 29, 41]</th><th>[1, 28, 41]</th><th>[1, 29, 40]</th><th>[1, 28, 40]</th></tr>
+<tr><th>GTX0:CLK_COR_SEQ_1_2</th><th>[1, 29, 52]</th><th>[1, 28, 52]</th><th>[1, 29, 51]</th><th>[1, 28, 51]</th><th>[1, 29, 50]</th><th>[1, 28, 50]</th><th>[1, 29, 49]</th><th>[1, 28, 49]</th><th>[1, 29, 48]</th><th>[1, 28, 48]</th></tr>
+<tr><th>GTX0:CLK_COR_SEQ_1_3</th><th>[1, 29, 60]</th><th>[1, 28, 60]</th><th>[1, 29, 59]</th><th>[1, 28, 59]</th><th>[1, 29, 58]</th><th>[1, 28, 58]</th><th>[1, 29, 57]</th><th>[1, 28, 57]</th><th>[1, 29, 56]</th><th>[1, 28, 56]</th></tr>
+<tr><th>GTX0:CLK_COR_SEQ_1_4</th><th>[2, 29, 4]</th><th>[2, 28, 4]</th><th>[2, 29, 3]</th><th>[2, 28, 3]</th><th>[2, 29, 2]</th><th>[2, 28, 2]</th><th>[2, 29, 1]</th><th>[2, 28, 1]</th><th>[2, 29, 0]</th><th>[2, 28, 0]</th></tr>
+<tr><th>GTX0:CLK_COR_SEQ_2_1</th><th>[2, 29, 12]</th><th>[2, 28, 12]</th><th>[2, 29, 11]</th><th>[2, 28, 11]</th><th>[2, 29, 10]</th><th>[2, 28, 10]</th><th>[2, 29, 9]</th><th>[2, 28, 9]</th><th>[2, 29, 8]</th><th>[2, 28, 8]</th></tr>
+<tr><th>GTX0:CLK_COR_SEQ_2_2</th><th>[2, 29, 20]</th><th>[2, 28, 20]</th><th>[2, 29, 19]</th><th>[2, 28, 19]</th><th>[2, 29, 18]</th><th>[2, 28, 18]</th><th>[2, 29, 17]</th><th>[2, 28, 17]</th><th>[2, 29, 16]</th><th>[2, 28, 16]</th></tr>
+<tr><th>GTX0:CLK_COR_SEQ_2_3</th><th>[2, 29, 28]</th><th>[2, 28, 28]</th><th>[2, 29, 27]</th><th>[2, 28, 27]</th><th>[2, 29, 26]</th><th>[2, 28, 26]</th><th>[2, 29, 25]</th><th>[2, 28, 25]</th><th>[2, 29, 24]</th><th>[2, 28, 24]</th></tr>
+<tr><th>GTX0:CLK_COR_SEQ_2_4</th><th>[2, 29, 36]</th><th>[2, 28, 36]</th><th>[2, 29, 35]</th><th>[2, 28, 35]</th><th>[2, 29, 34]</th><th>[2, 28, 34]</th><th>[2, 29, 33]</th><th>[2, 28, 33]</th><th>[2, 29, 32]</th><th>[2, 28, 32]</th></tr>
+<tr><th>GTX0:COMMA_10B_ENABLE</th><th>[5, 29, 60]</th><th>[5, 28, 60]</th><th>[5, 29, 59]</th><th>[5, 28, 59]</th><th>[5, 29, 58]</th><th>[5, 28, 58]</th><th>[5, 29, 57]</th><th>[5, 28, 57]</th><th>[5, 29, 56]</th><th>[5, 28, 56]</th></tr>
+<tr><th>GTX0:MCOMMA_10B_VALUE</th><th>[6, 29, 4]</th><th>[6, 28, 4]</th><th>[6, 29, 3]</th><th>[6, 28, 3]</th><th>[6, 29, 2]</th><th>[6, 28, 2]</th><th>[6, 29, 1]</th><th>[6, 28, 1]</th><th>[6, 29, 0]</th><th>[6, 28, 0]</th></tr>
+<tr><th>GTX0:PCOMMA_10B_VALUE</th><th>[6, 29, 12]</th><th>[6, 28, 12]</th><th>[6, 29, 11]</th><th>[6, 28, 11]</th><th>[6, 29, 10]</th><th>[6, 28, 10]</th><th>[6, 29, 9]</th><th>[6, 28, 9]</th><th>[6, 29, 8]</th><th>[6, 28, 8]</th></tr>
+<tr><th>GTX0:POWER_SAVE</th><th>[8, 29, 36]</th><th>[8, 28, 36]</th><th>[8, 29, 35]</th><th>[8, 28, 35]</th><th>[8, 29, 34]</th><th>[8, 28, 34]</th><th>[8, 29, 33]</th><th>[8, 28, 33]</th><th>[8, 29, 32]</th><th>[8, 28, 32]</th></tr>
+<tr><th>GTX0:RXRECCLK_DLY</th><th>[8, 29, 52]</th><th>[8, 28, 52]</th><th>[8, 29, 51]</th><th>[8, 28, 51]</th><th>[8, 29, 50]</th><th>[8, 28, 50]</th><th>[8, 29, 49]</th><th>[8, 28, 49]</th><th>[8, 29, 48]</th><th>[8, 28, 48]</th></tr>
+<tr><th>GTX0:TRANS_TIME_TO_P2</th><th>[4, 29, 28]</th><th>[4, 28, 28]</th><th>[4, 29, 27]</th><th>[4, 28, 27]</th><th>[4, 29, 26]</th><th>[4, 28, 26]</th><th>[4, 29, 25]</th><th>[4, 28, 25]</th><th>[4, 29, 24]</th><th>[4, 28, 24]</th></tr>
+<tr><th>GTX0:TXOUTCLK_DLY</th><th>[8, 29, 60]</th><th>[8, 28, 60]</th><th>[8, 29, 59]</th><th>[8, 28, 59]</th><th>[8, 29, 58]</th><th>[8, 28, 58]</th><th>[8, 29, 57]</th><th>[8, 28, 57]</th><th>[8, 29, 56]</th><th>[8, 28, 56]</th></tr>
+<tr><th>GTX1:A_RXEQMIX</th><th>[18, 29, 4]</th><th>[18, 28, 4]</th><th>[18, 29, 3]</th><th>[18, 28, 3]</th><th>[18, 29, 2]</th><th>[18, 28, 2]</th><th>[18, 29, 1]</th><th>[18, 28, 1]</th><th>[18, 29, 0]</th><th>[18, 28, 0]</th></tr>
+<tr><th>GTX1:CHAN_BOND_SEQ_1_1</th><th>[10, 29, 36]</th><th>[10, 28, 36]</th><th>[10, 29, 35]</th><th>[10, 28, 35]</th><th>[10, 29, 34]</th><th>[10, 28, 34]</th><th>[10, 29, 33]</th><th>[10, 28, 33]</th><th>[10, 29, 32]</th><th>[10, 28, 32]</th></tr>
+<tr><th>GTX1:CHAN_BOND_SEQ_1_2</th><th>[10, 29, 44]</th><th>[10, 28, 44]</th><th>[10, 29, 43]</th><th>[10, 28, 43]</th><th>[10, 29, 42]</th><th>[10, 28, 42]</th><th>[10, 29, 41]</th><th>[10, 28, 41]</th><th>[10, 29, 40]</th><th>[10, 28, 40]</th></tr>
+<tr><th>GTX1:CHAN_BOND_SEQ_1_3</th><th>[10, 29, 52]</th><th>[10, 28, 52]</th><th>[10, 29, 51]</th><th>[10, 28, 51]</th><th>[10, 29, 50]</th><th>[10, 28, 50]</th><th>[10, 29, 49]</th><th>[10, 28, 49]</th><th>[10, 29, 48]</th><th>[10, 28, 48]</th></tr>
+<tr><th>GTX1:CHAN_BOND_SEQ_1_4</th><th>[10, 29, 60]</th><th>[10, 28, 60]</th><th>[10, 29, 59]</th><th>[10, 28, 59]</th><th>[10, 29, 58]</th><th>[10, 28, 58]</th><th>[10, 29, 57]</th><th>[10, 28, 57]</th><th>[10, 29, 56]</th><th>[10, 28, 56]</th></tr>
+<tr><th>GTX1:CHAN_BOND_SEQ_2_1</th><th>[11, 29, 4]</th><th>[11, 28, 4]</th><th>[11, 29, 3]</th><th>[11, 28, 3]</th><th>[11, 29, 2]</th><th>[11, 28, 2]</th><th>[11, 29, 1]</th><th>[11, 28, 1]</th><th>[11, 29, 0]</th><th>[11, 28, 0]</th></tr>
+<tr><th>GTX1:CHAN_BOND_SEQ_2_2</th><th>[11, 29, 12]</th><th>[11, 28, 12]</th><th>[11, 29, 11]</th><th>[11, 28, 11]</th><th>[11, 29, 10]</th><th>[11, 28, 10]</th><th>[11, 29, 9]</th><th>[11, 28, 9]</th><th>[11, 29, 8]</th><th>[11, 28, 8]</th></tr>
+<tr><th>GTX1:CHAN_BOND_SEQ_2_3</th><th>[11, 29, 20]</th><th>[11, 28, 20]</th><th>[11, 29, 19]</th><th>[11, 28, 19]</th><th>[11, 29, 18]</th><th>[11, 28, 18]</th><th>[11, 29, 17]</th><th>[11, 28, 17]</th><th>[11, 29, 16]</th><th>[11, 28, 16]</th></tr>
+<tr><th>GTX1:CHAN_BOND_SEQ_2_4</th><th>[11, 29, 28]</th><th>[11, 28, 28]</th><th>[11, 29, 27]</th><th>[11, 28, 27]</th><th>[11, 29, 26]</th><th>[11, 28, 26]</th><th>[11, 29, 25]</th><th>[11, 28, 25]</th><th>[11, 29, 24]</th><th>[11, 28, 24]</th></tr>
+<tr><th>GTX1:CLK_COR_SEQ_1_1</th><th>[11, 29, 44]</th><th>[11, 28, 44]</th><th>[11, 29, 43]</th><th>[11, 28, 43]</th><th>[11, 29, 42]</th><th>[11, 28, 42]</th><th>[11, 29, 41]</th><th>[11, 28, 41]</th><th>[11, 29, 40]</th><th>[11, 28, 40]</th></tr>
+<tr><th>GTX1:CLK_COR_SEQ_1_2</th><th>[11, 29, 52]</th><th>[11, 28, 52]</th><th>[11, 29, 51]</th><th>[11, 28, 51]</th><th>[11, 29, 50]</th><th>[11, 28, 50]</th><th>[11, 29, 49]</th><th>[11, 28, 49]</th><th>[11, 29, 48]</th><th>[11, 28, 48]</th></tr>
+<tr><th>GTX1:CLK_COR_SEQ_1_3</th><th>[11, 29, 60]</th><th>[11, 28, 60]</th><th>[11, 29, 59]</th><th>[11, 28, 59]</th><th>[11, 29, 58]</th><th>[11, 28, 58]</th><th>[11, 29, 57]</th><th>[11, 28, 57]</th><th>[11, 29, 56]</th><th>[11, 28, 56]</th></tr>
+<tr><th>GTX1:CLK_COR_SEQ_1_4</th><th>[12, 29, 4]</th><th>[12, 28, 4]</th><th>[12, 29, 3]</th><th>[12, 28, 3]</th><th>[12, 29, 2]</th><th>[12, 28, 2]</th><th>[12, 29, 1]</th><th>[12, 28, 1]</th><th>[12, 29, 0]</th><th>[12, 28, 0]</th></tr>
+<tr><th>GTX1:CLK_COR_SEQ_2_1</th><th>[12, 29, 12]</th><th>[12, 28, 12]</th><th>[12, 29, 11]</th><th>[12, 28, 11]</th><th>[12, 29, 10]</th><th>[12, 28, 10]</th><th>[12, 29, 9]</th><th>[12, 28, 9]</th><th>[12, 29, 8]</th><th>[12, 28, 8]</th></tr>
+<tr><th>GTX1:CLK_COR_SEQ_2_2</th><th>[12, 29, 20]</th><th>[12, 28, 20]</th><th>[12, 29, 19]</th><th>[12, 28, 19]</th><th>[12, 29, 18]</th><th>[12, 28, 18]</th><th>[12, 29, 17]</th><th>[12, 28, 17]</th><th>[12, 29, 16]</th><th>[12, 28, 16]</th></tr>
+<tr><th>GTX1:CLK_COR_SEQ_2_3</th><th>[12, 29, 28]</th><th>[12, 28, 28]</th><th>[12, 29, 27]</th><th>[12, 28, 27]</th><th>[12, 29, 26]</th><th>[12, 28, 26]</th><th>[12, 29, 25]</th><th>[12, 28, 25]</th><th>[12, 29, 24]</th><th>[12, 28, 24]</th></tr>
+<tr><th>GTX1:CLK_COR_SEQ_2_4</th><th>[12, 29, 36]</th><th>[12, 28, 36]</th><th>[12, 29, 35]</th><th>[12, 28, 35]</th><th>[12, 29, 34]</th><th>[12, 28, 34]</th><th>[12, 29, 33]</th><th>[12, 28, 33]</th><th>[12, 29, 32]</th><th>[12, 28, 32]</th></tr>
+<tr><th>GTX1:COMMA_10B_ENABLE</th><th>[15, 29, 60]</th><th>[15, 28, 60]</th><th>[15, 29, 59]</th><th>[15, 28, 59]</th><th>[15, 29, 58]</th><th>[15, 28, 58]</th><th>[15, 29, 57]</th><th>[15, 28, 57]</th><th>[15, 29, 56]</th><th>[15, 28, 56]</th></tr>
+<tr><th>GTX1:MCOMMA_10B_VALUE</th><th>[16, 29, 4]</th><th>[16, 28, 4]</th><th>[16, 29, 3]</th><th>[16, 28, 3]</th><th>[16, 29, 2]</th><th>[16, 28, 2]</th><th>[16, 29, 1]</th><th>[16, 28, 1]</th><th>[16, 29, 0]</th><th>[16, 28, 0]</th></tr>
+<tr><th>GTX1:PCOMMA_10B_VALUE</th><th>[16, 29, 12]</th><th>[16, 28, 12]</th><th>[16, 29, 11]</th><th>[16, 28, 11]</th><th>[16, 29, 10]</th><th>[16, 28, 10]</th><th>[16, 29, 9]</th><th>[16, 28, 9]</th><th>[16, 29, 8]</th><th>[16, 28, 8]</th></tr>
+<tr><th>GTX1:POWER_SAVE</th><th>[18, 29, 36]</th><th>[18, 28, 36]</th><th>[18, 29, 35]</th><th>[18, 28, 35]</th><th>[18, 29, 34]</th><th>[18, 28, 34]</th><th>[18, 29, 33]</th><th>[18, 28, 33]</th><th>[18, 29, 32]</th><th>[18, 28, 32]</th></tr>
+<tr><th>GTX1:RXRECCLK_DLY</th><th>[18, 29, 52]</th><th>[18, 28, 52]</th><th>[18, 29, 51]</th><th>[18, 28, 51]</th><th>[18, 29, 50]</th><th>[18, 28, 50]</th><th>[18, 29, 49]</th><th>[18, 28, 49]</th><th>[18, 29, 48]</th><th>[18, 28, 48]</th></tr>
+<tr><th>GTX1:TRANS_TIME_TO_P2</th><th>[14, 29, 28]</th><th>[14, 28, 28]</th><th>[14, 29, 27]</th><th>[14, 28, 27]</th><th>[14, 29, 26]</th><th>[14, 28, 26]</th><th>[14, 29, 25]</th><th>[14, 28, 25]</th><th>[14, 29, 24]</th><th>[14, 28, 24]</th></tr>
+<tr><th>GTX1:TXOUTCLK_DLY</th><th>[18, 29, 60]</th><th>[18, 28, 60]</th><th>[18, 29, 59]</th><th>[18, 28, 59]</th><th>[18, 29, 58]</th><th>[18, 28, 58]</th><th>[18, 29, 57]</th><th>[18, 28, 57]</th><th>[18, 29, 56]</th><th>[18, 28, 56]</th></tr>
+<tr><th>GTX2:A_RXEQMIX</th><th>[28, 29, 4]</th><th>[28, 28, 4]</th><th>[28, 29, 3]</th><th>[28, 28, 3]</th><th>[28, 29, 2]</th><th>[28, 28, 2]</th><th>[28, 29, 1]</th><th>[28, 28, 1]</th><th>[28, 29, 0]</th><th>[28, 28, 0]</th></tr>
+<tr><th>GTX2:CHAN_BOND_SEQ_1_1</th><th>[20, 29, 36]</th><th>[20, 28, 36]</th><th>[20, 29, 35]</th><th>[20, 28, 35]</th><th>[20, 29, 34]</th><th>[20, 28, 34]</th><th>[20, 29, 33]</th><th>[20, 28, 33]</th><th>[20, 29, 32]</th><th>[20, 28, 32]</th></tr>
+<tr><th>GTX2:CHAN_BOND_SEQ_1_2</th><th>[20, 29, 44]</th><th>[20, 28, 44]</th><th>[20, 29, 43]</th><th>[20, 28, 43]</th><th>[20, 29, 42]</th><th>[20, 28, 42]</th><th>[20, 29, 41]</th><th>[20, 28, 41]</th><th>[20, 29, 40]</th><th>[20, 28, 40]</th></tr>
+<tr><th>GTX2:CHAN_BOND_SEQ_1_3</th><th>[20, 29, 52]</th><th>[20, 28, 52]</th><th>[20, 29, 51]</th><th>[20, 28, 51]</th><th>[20, 29, 50]</th><th>[20, 28, 50]</th><th>[20, 29, 49]</th><th>[20, 28, 49]</th><th>[20, 29, 48]</th><th>[20, 28, 48]</th></tr>
+<tr><th>GTX2:CHAN_BOND_SEQ_1_4</th><th>[20, 29, 60]</th><th>[20, 28, 60]</th><th>[20, 29, 59]</th><th>[20, 28, 59]</th><th>[20, 29, 58]</th><th>[20, 28, 58]</th><th>[20, 29, 57]</th><th>[20, 28, 57]</th><th>[20, 29, 56]</th><th>[20, 28, 56]</th></tr>
+<tr><th>GTX2:CHAN_BOND_SEQ_2_1</th><th>[21, 29, 4]</th><th>[21, 28, 4]</th><th>[21, 29, 3]</th><th>[21, 28, 3]</th><th>[21, 29, 2]</th><th>[21, 28, 2]</th><th>[21, 29, 1]</th><th>[21, 28, 1]</th><th>[21, 29, 0]</th><th>[21, 28, 0]</th></tr>
+<tr><th>GTX2:CHAN_BOND_SEQ_2_2</th><th>[21, 29, 12]</th><th>[21, 28, 12]</th><th>[21, 29, 11]</th><th>[21, 28, 11]</th><th>[21, 29, 10]</th><th>[21, 28, 10]</th><th>[21, 29, 9]</th><th>[21, 28, 9]</th><th>[21, 29, 8]</th><th>[21, 28, 8]</th></tr>
+<tr><th>GTX2:CHAN_BOND_SEQ_2_3</th><th>[21, 29, 20]</th><th>[21, 28, 20]</th><th>[21, 29, 19]</th><th>[21, 28, 19]</th><th>[21, 29, 18]</th><th>[21, 28, 18]</th><th>[21, 29, 17]</th><th>[21, 28, 17]</th><th>[21, 29, 16]</th><th>[21, 28, 16]</th></tr>
+<tr><th>GTX2:CHAN_BOND_SEQ_2_4</th><th>[21, 29, 28]</th><th>[21, 28, 28]</th><th>[21, 29, 27]</th><th>[21, 28, 27]</th><th>[21, 29, 26]</th><th>[21, 28, 26]</th><th>[21, 29, 25]</th><th>[21, 28, 25]</th><th>[21, 29, 24]</th><th>[21, 28, 24]</th></tr>
+<tr><th>GTX2:CLK_COR_SEQ_1_1</th><th>[21, 29, 44]</th><th>[21, 28, 44]</th><th>[21, 29, 43]</th><th>[21, 28, 43]</th><th>[21, 29, 42]</th><th>[21, 28, 42]</th><th>[21, 29, 41]</th><th>[21, 28, 41]</th><th>[21, 29, 40]</th><th>[21, 28, 40]</th></tr>
+<tr><th>GTX2:CLK_COR_SEQ_1_2</th><th>[21, 29, 52]</th><th>[21, 28, 52]</th><th>[21, 29, 51]</th><th>[21, 28, 51]</th><th>[21, 29, 50]</th><th>[21, 28, 50]</th><th>[21, 29, 49]</th><th>[21, 28, 49]</th><th>[21, 29, 48]</th><th>[21, 28, 48]</th></tr>
+<tr><th>GTX2:CLK_COR_SEQ_1_3</th><th>[21, 29, 60]</th><th>[21, 28, 60]</th><th>[21, 29, 59]</th><th>[21, 28, 59]</th><th>[21, 29, 58]</th><th>[21, 28, 58]</th><th>[21, 29, 57]</th><th>[21, 28, 57]</th><th>[21, 29, 56]</th><th>[21, 28, 56]</th></tr>
+<tr><th>GTX2:CLK_COR_SEQ_1_4</th><th>[22, 29, 4]</th><th>[22, 28, 4]</th><th>[22, 29, 3]</th><th>[22, 28, 3]</th><th>[22, 29, 2]</th><th>[22, 28, 2]</th><th>[22, 29, 1]</th><th>[22, 28, 1]</th><th>[22, 29, 0]</th><th>[22, 28, 0]</th></tr>
+<tr><th>GTX2:CLK_COR_SEQ_2_1</th><th>[22, 29, 12]</th><th>[22, 28, 12]</th><th>[22, 29, 11]</th><th>[22, 28, 11]</th><th>[22, 29, 10]</th><th>[22, 28, 10]</th><th>[22, 29, 9]</th><th>[22, 28, 9]</th><th>[22, 29, 8]</th><th>[22, 28, 8]</th></tr>
+<tr><th>GTX2:CLK_COR_SEQ_2_2</th><th>[22, 29, 20]</th><th>[22, 28, 20]</th><th>[22, 29, 19]</th><th>[22, 28, 19]</th><th>[22, 29, 18]</th><th>[22, 28, 18]</th><th>[22, 29, 17]</th><th>[22, 28, 17]</th><th>[22, 29, 16]</th><th>[22, 28, 16]</th></tr>
+<tr><th>GTX2:CLK_COR_SEQ_2_3</th><th>[22, 29, 28]</th><th>[22, 28, 28]</th><th>[22, 29, 27]</th><th>[22, 28, 27]</th><th>[22, 29, 26]</th><th>[22, 28, 26]</th><th>[22, 29, 25]</th><th>[22, 28, 25]</th><th>[22, 29, 24]</th><th>[22, 28, 24]</th></tr>
+<tr><th>GTX2:CLK_COR_SEQ_2_4</th><th>[22, 29, 36]</th><th>[22, 28, 36]</th><th>[22, 29, 35]</th><th>[22, 28, 35]</th><th>[22, 29, 34]</th><th>[22, 28, 34]</th><th>[22, 29, 33]</th><th>[22, 28, 33]</th><th>[22, 29, 32]</th><th>[22, 28, 32]</th></tr>
+<tr><th>GTX2:COMMA_10B_ENABLE</th><th>[25, 29, 60]</th><th>[25, 28, 60]</th><th>[25, 29, 59]</th><th>[25, 28, 59]</th><th>[25, 29, 58]</th><th>[25, 28, 58]</th><th>[25, 29, 57]</th><th>[25, 28, 57]</th><th>[25, 29, 56]</th><th>[25, 28, 56]</th></tr>
+<tr><th>GTX2:MCOMMA_10B_VALUE</th><th>[26, 29, 4]</th><th>[26, 28, 4]</th><th>[26, 29, 3]</th><th>[26, 28, 3]</th><th>[26, 29, 2]</th><th>[26, 28, 2]</th><th>[26, 29, 1]</th><th>[26, 28, 1]</th><th>[26, 29, 0]</th><th>[26, 28, 0]</th></tr>
+<tr><th>GTX2:PCOMMA_10B_VALUE</th><th>[26, 29, 12]</th><th>[26, 28, 12]</th><th>[26, 29, 11]</th><th>[26, 28, 11]</th><th>[26, 29, 10]</th><th>[26, 28, 10]</th><th>[26, 29, 9]</th><th>[26, 28, 9]</th><th>[26, 29, 8]</th><th>[26, 28, 8]</th></tr>
+<tr><th>GTX2:POWER_SAVE</th><th>[28, 29, 36]</th><th>[28, 28, 36]</th><th>[28, 29, 35]</th><th>[28, 28, 35]</th><th>[28, 29, 34]</th><th>[28, 28, 34]</th><th>[28, 29, 33]</th><th>[28, 28, 33]</th><th>[28, 29, 32]</th><th>[28, 28, 32]</th></tr>
+<tr><th>GTX2:RXRECCLK_DLY</th><th>[28, 29, 52]</th><th>[28, 28, 52]</th><th>[28, 29, 51]</th><th>[28, 28, 51]</th><th>[28, 29, 50]</th><th>[28, 28, 50]</th><th>[28, 29, 49]</th><th>[28, 28, 49]</th><th>[28, 29, 48]</th><th>[28, 28, 48]</th></tr>
+<tr><th>GTX2:TRANS_TIME_TO_P2</th><th>[24, 29, 28]</th><th>[24, 28, 28]</th><th>[24, 29, 27]</th><th>[24, 28, 27]</th><th>[24, 29, 26]</th><th>[24, 28, 26]</th><th>[24, 29, 25]</th><th>[24, 28, 25]</th><th>[24, 29, 24]</th><th>[24, 28, 24]</th></tr>
+<tr><th>GTX2:TXOUTCLK_DLY</th><th>[28, 29, 60]</th><th>[28, 28, 60]</th><th>[28, 29, 59]</th><th>[28, 28, 59]</th><th>[28, 29, 58]</th><th>[28, 28, 58]</th><th>[28, 29, 57]</th><th>[28, 28, 57]</th><th>[28, 29, 56]</th><th>[28, 28, 56]</th></tr>
+<tr><th>GTX3:A_RXEQMIX</th><th>[38, 29, 4]</th><th>[38, 28, 4]</th><th>[38, 29, 3]</th><th>[38, 28, 3]</th><th>[38, 29, 2]</th><th>[38, 28, 2]</th><th>[38, 29, 1]</th><th>[38, 28, 1]</th><th>[38, 29, 0]</th><th>[38, 28, 0]</th></tr>
+<tr><th>GTX3:CHAN_BOND_SEQ_1_1</th><th>[30, 29, 36]</th><th>[30, 28, 36]</th><th>[30, 29, 35]</th><th>[30, 28, 35]</th><th>[30, 29, 34]</th><th>[30, 28, 34]</th><th>[30, 29, 33]</th><th>[30, 28, 33]</th><th>[30, 29, 32]</th><th>[30, 28, 32]</th></tr>
+<tr><th>GTX3:CHAN_BOND_SEQ_1_2</th><th>[30, 29, 44]</th><th>[30, 28, 44]</th><th>[30, 29, 43]</th><th>[30, 28, 43]</th><th>[30, 29, 42]</th><th>[30, 28, 42]</th><th>[30, 29, 41]</th><th>[30, 28, 41]</th><th>[30, 29, 40]</th><th>[30, 28, 40]</th></tr>
+<tr><th>GTX3:CHAN_BOND_SEQ_1_3</th><th>[30, 29, 52]</th><th>[30, 28, 52]</th><th>[30, 29, 51]</th><th>[30, 28, 51]</th><th>[30, 29, 50]</th><th>[30, 28, 50]</th><th>[30, 29, 49]</th><th>[30, 28, 49]</th><th>[30, 29, 48]</th><th>[30, 28, 48]</th></tr>
+<tr><th>GTX3:CHAN_BOND_SEQ_1_4</th><th>[30, 29, 60]</th><th>[30, 28, 60]</th><th>[30, 29, 59]</th><th>[30, 28, 59]</th><th>[30, 29, 58]</th><th>[30, 28, 58]</th><th>[30, 29, 57]</th><th>[30, 28, 57]</th><th>[30, 29, 56]</th><th>[30, 28, 56]</th></tr>
+<tr><th>GTX3:CHAN_BOND_SEQ_2_1</th><th>[31, 29, 4]</th><th>[31, 28, 4]</th><th>[31, 29, 3]</th><th>[31, 28, 3]</th><th>[31, 29, 2]</th><th>[31, 28, 2]</th><th>[31, 29, 1]</th><th>[31, 28, 1]</th><th>[31, 29, 0]</th><th>[31, 28, 0]</th></tr>
+<tr><th>GTX3:CHAN_BOND_SEQ_2_2</th><th>[31, 29, 12]</th><th>[31, 28, 12]</th><th>[31, 29, 11]</th><th>[31, 28, 11]</th><th>[31, 29, 10]</th><th>[31, 28, 10]</th><th>[31, 29, 9]</th><th>[31, 28, 9]</th><th>[31, 29, 8]</th><th>[31, 28, 8]</th></tr>
+<tr><th>GTX3:CHAN_BOND_SEQ_2_3</th><th>[31, 29, 20]</th><th>[31, 28, 20]</th><th>[31, 29, 19]</th><th>[31, 28, 19]</th><th>[31, 29, 18]</th><th>[31, 28, 18]</th><th>[31, 29, 17]</th><th>[31, 28, 17]</th><th>[31, 29, 16]</th><th>[31, 28, 16]</th></tr>
+<tr><th>GTX3:CHAN_BOND_SEQ_2_4</th><th>[31, 29, 28]</th><th>[31, 28, 28]</th><th>[31, 29, 27]</th><th>[31, 28, 27]</th><th>[31, 29, 26]</th><th>[31, 28, 26]</th><th>[31, 29, 25]</th><th>[31, 28, 25]</th><th>[31, 29, 24]</th><th>[31, 28, 24]</th></tr>
+<tr><th>GTX3:CLK_COR_SEQ_1_1</th><th>[31, 29, 44]</th><th>[31, 28, 44]</th><th>[31, 29, 43]</th><th>[31, 28, 43]</th><th>[31, 29, 42]</th><th>[31, 28, 42]</th><th>[31, 29, 41]</th><th>[31, 28, 41]</th><th>[31, 29, 40]</th><th>[31, 28, 40]</th></tr>
+<tr><th>GTX3:CLK_COR_SEQ_1_2</th><th>[31, 29, 52]</th><th>[31, 28, 52]</th><th>[31, 29, 51]</th><th>[31, 28, 51]</th><th>[31, 29, 50]</th><th>[31, 28, 50]</th><th>[31, 29, 49]</th><th>[31, 28, 49]</th><th>[31, 29, 48]</th><th>[31, 28, 48]</th></tr>
+<tr><th>GTX3:CLK_COR_SEQ_1_3</th><th>[31, 29, 60]</th><th>[31, 28, 60]</th><th>[31, 29, 59]</th><th>[31, 28, 59]</th><th>[31, 29, 58]</th><th>[31, 28, 58]</th><th>[31, 29, 57]</th><th>[31, 28, 57]</th><th>[31, 29, 56]</th><th>[31, 28, 56]</th></tr>
+<tr><th>GTX3:CLK_COR_SEQ_1_4</th><th>[32, 29, 4]</th><th>[32, 28, 4]</th><th>[32, 29, 3]</th><th>[32, 28, 3]</th><th>[32, 29, 2]</th><th>[32, 28, 2]</th><th>[32, 29, 1]</th><th>[32, 28, 1]</th><th>[32, 29, 0]</th><th>[32, 28, 0]</th></tr>
+<tr><th>GTX3:CLK_COR_SEQ_2_1</th><th>[32, 29, 12]</th><th>[32, 28, 12]</th><th>[32, 29, 11]</th><th>[32, 28, 11]</th><th>[32, 29, 10]</th><th>[32, 28, 10]</th><th>[32, 29, 9]</th><th>[32, 28, 9]</th><th>[32, 29, 8]</th><th>[32, 28, 8]</th></tr>
+<tr><th>GTX3:CLK_COR_SEQ_2_2</th><th>[32, 29, 20]</th><th>[32, 28, 20]</th><th>[32, 29, 19]</th><th>[32, 28, 19]</th><th>[32, 29, 18]</th><th>[32, 28, 18]</th><th>[32, 29, 17]</th><th>[32, 28, 17]</th><th>[32, 29, 16]</th><th>[32, 28, 16]</th></tr>
+<tr><th>GTX3:CLK_COR_SEQ_2_3</th><th>[32, 29, 28]</th><th>[32, 28, 28]</th><th>[32, 29, 27]</th><th>[32, 28, 27]</th><th>[32, 29, 26]</th><th>[32, 28, 26]</th><th>[32, 29, 25]</th><th>[32, 28, 25]</th><th>[32, 29, 24]</th><th>[32, 28, 24]</th></tr>
+<tr><th>GTX3:CLK_COR_SEQ_2_4</th><th>[32, 29, 36]</th><th>[32, 28, 36]</th><th>[32, 29, 35]</th><th>[32, 28, 35]</th><th>[32, 29, 34]</th><th>[32, 28, 34]</th><th>[32, 29, 33]</th><th>[32, 28, 33]</th><th>[32, 29, 32]</th><th>[32, 28, 32]</th></tr>
+<tr><th>GTX3:COMMA_10B_ENABLE</th><th>[35, 29, 60]</th><th>[35, 28, 60]</th><th>[35, 29, 59]</th><th>[35, 28, 59]</th><th>[35, 29, 58]</th><th>[35, 28, 58]</th><th>[35, 29, 57]</th><th>[35, 28, 57]</th><th>[35, 29, 56]</th><th>[35, 28, 56]</th></tr>
+<tr><th>GTX3:MCOMMA_10B_VALUE</th><th>[36, 29, 4]</th><th>[36, 28, 4]</th><th>[36, 29, 3]</th><th>[36, 28, 3]</th><th>[36, 29, 2]</th><th>[36, 28, 2]</th><th>[36, 29, 1]</th><th>[36, 28, 1]</th><th>[36, 29, 0]</th><th>[36, 28, 0]</th></tr>
+<tr><th>GTX3:PCOMMA_10B_VALUE</th><th>[36, 29, 12]</th><th>[36, 28, 12]</th><th>[36, 29, 11]</th><th>[36, 28, 11]</th><th>[36, 29, 10]</th><th>[36, 28, 10]</th><th>[36, 29, 9]</th><th>[36, 28, 9]</th><th>[36, 29, 8]</th><th>[36, 28, 8]</th></tr>
+<tr><th>GTX3:POWER_SAVE</th><th>[38, 29, 36]</th><th>[38, 28, 36]</th><th>[38, 29, 35]</th><th>[38, 28, 35]</th><th>[38, 29, 34]</th><th>[38, 28, 34]</th><th>[38, 29, 33]</th><th>[38, 28, 33]</th><th>[38, 29, 32]</th><th>[38, 28, 32]</th></tr>
+<tr><th>GTX3:RXRECCLK_DLY</th><th>[38, 29, 52]</th><th>[38, 28, 52]</th><th>[38, 29, 51]</th><th>[38, 28, 51]</th><th>[38, 29, 50]</th><th>[38, 28, 50]</th><th>[38, 29, 49]</th><th>[38, 28, 49]</th><th>[38, 29, 48]</th><th>[38, 28, 48]</th></tr>
+<tr><th>GTX3:TRANS_TIME_TO_P2</th><th>[34, 29, 28]</th><th>[34, 28, 28]</th><th>[34, 29, 27]</th><th>[34, 28, 27]</th><th>[34, 29, 26]</th><th>[34, 28, 26]</th><th>[34, 29, 25]</th><th>[34, 28, 25]</th><th>[34, 29, 24]</th><th>[34, 28, 24]</th></tr>
+<tr><th>GTX3:TXOUTCLK_DLY</th><th>[38, 29, 60]</th><th>[38, 28, 60]</th><th>[38, 29, 59]</th><th>[38, 28, 59]</th><th>[38, 29, 58]</th><th>[38, 28, 58]</th><th>[38, 29, 57]</th><th>[38, 28, 57]</th><th>[38, 29, 56]</th><th>[38, 28, 56]</th></tr>
+<tr><th>IBUFDS_GTX0:REFCLKOUT_DLY</th><th>[19, 29, 4]</th><th>[19, 28, 4]</th><th>[19, 29, 3]</th><th>[19, 28, 3]</th><th>[19, 29, 2]</th><th>[19, 28, 2]</th><th>[19, 29, 1]</th><th>[19, 28, 1]</th><th>[19, 29, 0]</th><th>[19, 28, 0]</th></tr>
+<tr><th>IBUFDS_GTX1:REFCLKOUT_DLY</th><th>[19, 29, 12]</th><th>[19, 28, 12]</th><th>[19, 29, 11]</th><th>[19, 28, 11]</th><th>[19, 29, 10]</th><th>[19, 28, 10]</th><th>[19, 29, 9]</th><th>[19, 28, 9]</th><th>[19, 29, 8]</th><th>[19, 28, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:A_DFETAP3"></div>
+<div id="bits-xc6v-GTX-GTX0:A_DFETAP4"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXDIFFCTRL"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXPREEMPHASIS"></div>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_1_MAX_SKEW"></div>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_2_MAX_SKEW"></div>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_1_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_SEQ_1_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX0:COM_BURST_VAL"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_DLYALIGN_CTRINC"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_DLYALIGN_LPFINC"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_IDLE_HI_CNT"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_IDLE_LO_CNT"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_SLIDE_AUTO_WAIT"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_DLYALIGN_CTRINC"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_DLYALIGN_LPFINC"></div>
+<div id="bits-xc6v-GTX-GTX1:A_DFETAP3"></div>
+<div id="bits-xc6v-GTX-GTX1:A_DFETAP4"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXDIFFCTRL"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXPREEMPHASIS"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_1_MAX_SKEW"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_2_MAX_SKEW"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_1_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_SEQ_1_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX1:COM_BURST_VAL"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_DLYALIGN_CTRINC"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_DLYALIGN_LPFINC"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_IDLE_HI_CNT"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_IDLE_LO_CNT"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_SLIDE_AUTO_WAIT"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_DLYALIGN_CTRINC"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_DLYALIGN_LPFINC"></div>
+<div id="bits-xc6v-GTX-GTX2:A_DFETAP3"></div>
+<div id="bits-xc6v-GTX-GTX2:A_DFETAP4"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXDIFFCTRL"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXPREEMPHASIS"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_1_MAX_SKEW"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_2_MAX_SKEW"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_1_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_SEQ_1_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX2:COM_BURST_VAL"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_DLYALIGN_CTRINC"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_DLYALIGN_LPFINC"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_IDLE_HI_CNT"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_IDLE_LO_CNT"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_SLIDE_AUTO_WAIT"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_DLYALIGN_CTRINC"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_DLYALIGN_LPFINC"></div>
+<div id="bits-xc6v-GTX-GTX3:A_DFETAP3"></div>
+<div id="bits-xc6v-GTX-GTX3:A_DFETAP4"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXDIFFCTRL"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXPREEMPHASIS"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_1_MAX_SKEW"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_2_MAX_SKEW"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_1_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_SEQ_1_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_ENABLE"></div>
+<div id="bits-xc6v-GTX-GTX3:COM_BURST_VAL"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_DLYALIGN_CTRINC"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_DLYALIGN_LPFINC"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_IDLE_HI_CNT"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_IDLE_LO_CNT"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_SLIDE_AUTO_WAIT"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_DLYALIGN_CTRINC"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_DLYALIGN_LPFINC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:A_DFETAP3</th><th>[5, 28, 28]</th><th>[5, 29, 27]</th><th>[5, 28, 27]</th><th>[5, 29, 26]</th></tr>
+<tr><th>GTX0:A_DFETAP4</th><th>[5, 28, 36]</th><th>[5, 29, 35]</th><th>[5, 28, 35]</th><th>[5, 29, 34]</th></tr>
+<tr><th>GTX0:A_TXDIFFCTRL</th><th>[7, 29, 41]</th><th>[7, 28, 41]</th><th>[7, 29, 40]</th><th>[7, 28, 40]</th></tr>
+<tr><th>GTX0:A_TXPREEMPHASIS</th><th>[7, 28, 45]</th><th>[7, 29, 44]</th><th>[7, 28, 44]</th><th>[7, 29, 43]</th></tr>
+<tr><th>GTX0:CHAN_BOND_1_MAX_SKEW</th><th>[0, 29, 46]</th><th>[0, 28, 46]</th><th>[0, 29, 45]</th><th>[0, 28, 45]</th></tr>
+<tr><th>GTX0:CHAN_BOND_2_MAX_SKEW</th><th>[1, 29, 14]</th><th>[1, 28, 14]</th><th>[1, 29, 13]</th><th>[1, 28, 13]</th></tr>
+<tr><th>GTX0:CHAN_BOND_SEQ_1_ENABLE</th><th>[0, 29, 38]</th><th>[0, 28, 38]</th><th>[0, 29, 37]</th><th>[0, 28, 37]</th></tr>
+<tr><th>GTX0:CHAN_BOND_SEQ_2_ENABLE</th><th>[1, 29, 6]</th><th>[1, 28, 6]</th><th>[1, 29, 5]</th><th>[1, 28, 5]</th></tr>
+<tr><th>GTX0:CLK_COR_SEQ_1_ENABLE</th><th>[1, 29, 46]</th><th>[1, 28, 46]</th><th>[1, 29, 45]</th><th>[1, 28, 45]</th></tr>
+<tr><th>GTX0:CLK_COR_SEQ_2_ENABLE</th><th>[2, 29, 14]</th><th>[2, 28, 14]</th><th>[2, 29, 13]</th><th>[2, 28, 13]</th></tr>
+<tr><th>GTX0:COM_BURST_VAL</th><th>[4, 29, 39]</th><th>[4, 28, 39]</th><th>[4, 29, 38]</th><th>[4, 28, 38]</th></tr>
+<tr><th>GTX0:RX_DLYALIGN_CTRINC</th><th>[9, 29, 41]</th><th>[9, 28, 41]</th><th>[9, 29, 40]</th><th>[9, 28, 40]</th></tr>
+<tr><th>GTX0:RX_DLYALIGN_LPFINC</th><th>[9, 29, 43]</th><th>[9, 28, 43]</th><th>[9, 29, 42]</th><th>[9, 28, 42]</th></tr>
+<tr><th>GTX0:RX_IDLE_HI_CNT</th><th>[1, 29, 31]</th><th>[1, 28, 31]</th><th>[1, 29, 30]</th><th>[1, 28, 30]</th></tr>
+<tr><th>GTX0:RX_IDLE_LO_CNT</th><th>[0, 29, 63]</th><th>[0, 28, 63]</th><th>[0, 29, 62]</th><th>[0, 28, 62]</th></tr>
+<tr><th>GTX0:RX_SLIDE_AUTO_WAIT</th><th>[2, 29, 31]</th><th>[2, 28, 31]</th><th>[2, 29, 30]</th><th>[2, 28, 30]</th></tr>
+<tr><th>GTX0:TX_DLYALIGN_CTRINC</th><th>[9, 29, 33]</th><th>[9, 28, 33]</th><th>[9, 29, 32]</th><th>[9, 28, 32]</th></tr>
+<tr><th>GTX0:TX_DLYALIGN_LPFINC</th><th>[9, 29, 35]</th><th>[9, 28, 35]</th><th>[9, 29, 34]</th><th>[9, 28, 34]</th></tr>
+<tr><th>GTX1:A_DFETAP3</th><th>[15, 28, 28]</th><th>[15, 29, 27]</th><th>[15, 28, 27]</th><th>[15, 29, 26]</th></tr>
+<tr><th>GTX1:A_DFETAP4</th><th>[15, 28, 36]</th><th>[15, 29, 35]</th><th>[15, 28, 35]</th><th>[15, 29, 34]</th></tr>
+<tr><th>GTX1:A_TXDIFFCTRL</th><th>[17, 29, 41]</th><th>[17, 28, 41]</th><th>[17, 29, 40]</th><th>[17, 28, 40]</th></tr>
+<tr><th>GTX1:A_TXPREEMPHASIS</th><th>[17, 28, 45]</th><th>[17, 29, 44]</th><th>[17, 28, 44]</th><th>[17, 29, 43]</th></tr>
+<tr><th>GTX1:CHAN_BOND_1_MAX_SKEW</th><th>[10, 29, 46]</th><th>[10, 28, 46]</th><th>[10, 29, 45]</th><th>[10, 28, 45]</th></tr>
+<tr><th>GTX1:CHAN_BOND_2_MAX_SKEW</th><th>[11, 29, 14]</th><th>[11, 28, 14]</th><th>[11, 29, 13]</th><th>[11, 28, 13]</th></tr>
+<tr><th>GTX1:CHAN_BOND_SEQ_1_ENABLE</th><th>[10, 29, 38]</th><th>[10, 28, 38]</th><th>[10, 29, 37]</th><th>[10, 28, 37]</th></tr>
+<tr><th>GTX1:CHAN_BOND_SEQ_2_ENABLE</th><th>[11, 29, 6]</th><th>[11, 28, 6]</th><th>[11, 29, 5]</th><th>[11, 28, 5]</th></tr>
+<tr><th>GTX1:CLK_COR_SEQ_1_ENABLE</th><th>[11, 29, 46]</th><th>[11, 28, 46]</th><th>[11, 29, 45]</th><th>[11, 28, 45]</th></tr>
+<tr><th>GTX1:CLK_COR_SEQ_2_ENABLE</th><th>[12, 29, 14]</th><th>[12, 28, 14]</th><th>[12, 29, 13]</th><th>[12, 28, 13]</th></tr>
+<tr><th>GTX1:COM_BURST_VAL</th><th>[14, 29, 39]</th><th>[14, 28, 39]</th><th>[14, 29, 38]</th><th>[14, 28, 38]</th></tr>
+<tr><th>GTX1:RX_DLYALIGN_CTRINC</th><th>[19, 29, 41]</th><th>[19, 28, 41]</th><th>[19, 29, 40]</th><th>[19, 28, 40]</th></tr>
+<tr><th>GTX1:RX_DLYALIGN_LPFINC</th><th>[19, 29, 43]</th><th>[19, 28, 43]</th><th>[19, 29, 42]</th><th>[19, 28, 42]</th></tr>
+<tr><th>GTX1:RX_IDLE_HI_CNT</th><th>[11, 29, 31]</th><th>[11, 28, 31]</th><th>[11, 29, 30]</th><th>[11, 28, 30]</th></tr>
+<tr><th>GTX1:RX_IDLE_LO_CNT</th><th>[10, 29, 63]</th><th>[10, 28, 63]</th><th>[10, 29, 62]</th><th>[10, 28, 62]</th></tr>
+<tr><th>GTX1:RX_SLIDE_AUTO_WAIT</th><th>[12, 29, 31]</th><th>[12, 28, 31]</th><th>[12, 29, 30]</th><th>[12, 28, 30]</th></tr>
+<tr><th>GTX1:TX_DLYALIGN_CTRINC</th><th>[19, 29, 33]</th><th>[19, 28, 33]</th><th>[19, 29, 32]</th><th>[19, 28, 32]</th></tr>
+<tr><th>GTX1:TX_DLYALIGN_LPFINC</th><th>[19, 29, 35]</th><th>[19, 28, 35]</th><th>[19, 29, 34]</th><th>[19, 28, 34]</th></tr>
+<tr><th>GTX2:A_DFETAP3</th><th>[25, 28, 28]</th><th>[25, 29, 27]</th><th>[25, 28, 27]</th><th>[25, 29, 26]</th></tr>
+<tr><th>GTX2:A_DFETAP4</th><th>[25, 28, 36]</th><th>[25, 29, 35]</th><th>[25, 28, 35]</th><th>[25, 29, 34]</th></tr>
+<tr><th>GTX2:A_TXDIFFCTRL</th><th>[27, 29, 41]</th><th>[27, 28, 41]</th><th>[27, 29, 40]</th><th>[27, 28, 40]</th></tr>
+<tr><th>GTX2:A_TXPREEMPHASIS</th><th>[27, 28, 45]</th><th>[27, 29, 44]</th><th>[27, 28, 44]</th><th>[27, 29, 43]</th></tr>
+<tr><th>GTX2:CHAN_BOND_1_MAX_SKEW</th><th>[20, 29, 46]</th><th>[20, 28, 46]</th><th>[20, 29, 45]</th><th>[20, 28, 45]</th></tr>
+<tr><th>GTX2:CHAN_BOND_2_MAX_SKEW</th><th>[21, 29, 14]</th><th>[21, 28, 14]</th><th>[21, 29, 13]</th><th>[21, 28, 13]</th></tr>
+<tr><th>GTX2:CHAN_BOND_SEQ_1_ENABLE</th><th>[20, 29, 38]</th><th>[20, 28, 38]</th><th>[20, 29, 37]</th><th>[20, 28, 37]</th></tr>
+<tr><th>GTX2:CHAN_BOND_SEQ_2_ENABLE</th><th>[21, 29, 6]</th><th>[21, 28, 6]</th><th>[21, 29, 5]</th><th>[21, 28, 5]</th></tr>
+<tr><th>GTX2:CLK_COR_SEQ_1_ENABLE</th><th>[21, 29, 46]</th><th>[21, 28, 46]</th><th>[21, 29, 45]</th><th>[21, 28, 45]</th></tr>
+<tr><th>GTX2:CLK_COR_SEQ_2_ENABLE</th><th>[22, 29, 14]</th><th>[22, 28, 14]</th><th>[22, 29, 13]</th><th>[22, 28, 13]</th></tr>
+<tr><th>GTX2:COM_BURST_VAL</th><th>[24, 29, 39]</th><th>[24, 28, 39]</th><th>[24, 29, 38]</th><th>[24, 28, 38]</th></tr>
+<tr><th>GTX2:RX_DLYALIGN_CTRINC</th><th>[29, 29, 41]</th><th>[29, 28, 41]</th><th>[29, 29, 40]</th><th>[29, 28, 40]</th></tr>
+<tr><th>GTX2:RX_DLYALIGN_LPFINC</th><th>[29, 29, 43]</th><th>[29, 28, 43]</th><th>[29, 29, 42]</th><th>[29, 28, 42]</th></tr>
+<tr><th>GTX2:RX_IDLE_HI_CNT</th><th>[21, 29, 31]</th><th>[21, 28, 31]</th><th>[21, 29, 30]</th><th>[21, 28, 30]</th></tr>
+<tr><th>GTX2:RX_IDLE_LO_CNT</th><th>[20, 29, 63]</th><th>[20, 28, 63]</th><th>[20, 29, 62]</th><th>[20, 28, 62]</th></tr>
+<tr><th>GTX2:RX_SLIDE_AUTO_WAIT</th><th>[22, 29, 31]</th><th>[22, 28, 31]</th><th>[22, 29, 30]</th><th>[22, 28, 30]</th></tr>
+<tr><th>GTX2:TX_DLYALIGN_CTRINC</th><th>[29, 29, 33]</th><th>[29, 28, 33]</th><th>[29, 29, 32]</th><th>[29, 28, 32]</th></tr>
+<tr><th>GTX2:TX_DLYALIGN_LPFINC</th><th>[29, 29, 35]</th><th>[29, 28, 35]</th><th>[29, 29, 34]</th><th>[29, 28, 34]</th></tr>
+<tr><th>GTX3:A_DFETAP3</th><th>[35, 28, 28]</th><th>[35, 29, 27]</th><th>[35, 28, 27]</th><th>[35, 29, 26]</th></tr>
+<tr><th>GTX3:A_DFETAP4</th><th>[35, 28, 36]</th><th>[35, 29, 35]</th><th>[35, 28, 35]</th><th>[35, 29, 34]</th></tr>
+<tr><th>GTX3:A_TXDIFFCTRL</th><th>[37, 29, 41]</th><th>[37, 28, 41]</th><th>[37, 29, 40]</th><th>[37, 28, 40]</th></tr>
+<tr><th>GTX3:A_TXPREEMPHASIS</th><th>[37, 28, 45]</th><th>[37, 29, 44]</th><th>[37, 28, 44]</th><th>[37, 29, 43]</th></tr>
+<tr><th>GTX3:CHAN_BOND_1_MAX_SKEW</th><th>[30, 29, 46]</th><th>[30, 28, 46]</th><th>[30, 29, 45]</th><th>[30, 28, 45]</th></tr>
+<tr><th>GTX3:CHAN_BOND_2_MAX_SKEW</th><th>[31, 29, 14]</th><th>[31, 28, 14]</th><th>[31, 29, 13]</th><th>[31, 28, 13]</th></tr>
+<tr><th>GTX3:CHAN_BOND_SEQ_1_ENABLE</th><th>[30, 29, 38]</th><th>[30, 28, 38]</th><th>[30, 29, 37]</th><th>[30, 28, 37]</th></tr>
+<tr><th>GTX3:CHAN_BOND_SEQ_2_ENABLE</th><th>[31, 29, 6]</th><th>[31, 28, 6]</th><th>[31, 29, 5]</th><th>[31, 28, 5]</th></tr>
+<tr><th>GTX3:CLK_COR_SEQ_1_ENABLE</th><th>[31, 29, 46]</th><th>[31, 28, 46]</th><th>[31, 29, 45]</th><th>[31, 28, 45]</th></tr>
+<tr><th>GTX3:CLK_COR_SEQ_2_ENABLE</th><th>[32, 29, 14]</th><th>[32, 28, 14]</th><th>[32, 29, 13]</th><th>[32, 28, 13]</th></tr>
+<tr><th>GTX3:COM_BURST_VAL</th><th>[34, 29, 39]</th><th>[34, 28, 39]</th><th>[34, 29, 38]</th><th>[34, 28, 38]</th></tr>
+<tr><th>GTX3:RX_DLYALIGN_CTRINC</th><th>[39, 29, 41]</th><th>[39, 28, 41]</th><th>[39, 29, 40]</th><th>[39, 28, 40]</th></tr>
+<tr><th>GTX3:RX_DLYALIGN_LPFINC</th><th>[39, 29, 43]</th><th>[39, 28, 43]</th><th>[39, 29, 42]</th><th>[39, 28, 42]</th></tr>
+<tr><th>GTX3:RX_IDLE_HI_CNT</th><th>[31, 29, 31]</th><th>[31, 28, 31]</th><th>[31, 29, 30]</th><th>[31, 28, 30]</th></tr>
+<tr><th>GTX3:RX_IDLE_LO_CNT</th><th>[30, 29, 63]</th><th>[30, 28, 63]</th><th>[30, 29, 62]</th><th>[30, 28, 62]</th></tr>
+<tr><th>GTX3:RX_SLIDE_AUTO_WAIT</th><th>[32, 29, 31]</th><th>[32, 28, 31]</th><th>[32, 29, 30]</th><th>[32, 28, 30]</th></tr>
+<tr><th>GTX3:TX_DLYALIGN_CTRINC</th><th>[39, 29, 33]</th><th>[39, 28, 33]</th><th>[39, 29, 32]</th><th>[39, 28, 32]</th></tr>
+<tr><th>GTX3:TX_DLYALIGN_LPFINC</th><th>[39, 29, 35]</th><th>[39, 28, 35]</th><th>[39, 29, 34]</th><th>[39, 28, 34]</th></tr>
+<tr><td>Non-inverted</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:AC_CAP_DIS"></div>
+<div id="bits-xc6v-GTX-GTX0:A_DFEDLYOVRD"></div>
+<div id="bits-xc6v-GTX-GTX0:A_DFETAPOVRD"></div>
+<div id="bits-xc6v-GTX-GTX0:A_GTXRXRESET"></div>
+<div id="bits-xc6v-GTX-GTX0:A_GTXTXRESET"></div>
+<div id="bits-xc6v-GTX-GTX0:A_PLLCLKRXRESET"></div>
+<div id="bits-xc6v-GTX-GTX0:A_PLLCLKTXRESET"></div>
+<div id="bits-xc6v-GTX-GTX0:A_PLLRXRESET"></div>
+<div id="bits-xc6v-GTX-GTX0:A_PLLTXRESET"></div>
+<div id="bits-xc6v-GTX-GTX0:A_PRBSCNTRESET"></div>
+<div id="bits-xc6v-GTX-GTX0:A_RXBUFRESET"></div>
+<div id="bits-xc6v-GTX-GTX0:A_RXCDRFREQRESET"></div>
+<div id="bits-xc6v-GTX-GTX0:A_RXCDRHOLD"></div>
+<div id="bits-xc6v-GTX-GTX0:A_RXCDRPHASERESET"></div>
+<div id="bits-xc6v-GTX-GTX0:A_RXCDRRESET"></div>
+<div id="bits-xc6v-GTX-GTX0:A_RXDFERESET"></div>
+<div id="bits-xc6v-GTX-GTX0:A_RXENPMAPHASEALIGN"></div>
+<div id="bits-xc6v-GTX-GTX0:A_RXENSAMPLEALIGN"></div>
+<div id="bits-xc6v-GTX-GTX0:A_RXPLLLKDETEN"></div>
+<div id="bits-xc6v-GTX-GTX0:A_RXPLLPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX0:A_RXPMASETPHASE"></div>
+<div id="bits-xc6v-GTX-GTX0:A_RXPOLARITY"></div>
+<div id="bits-xc6v-GTX-GTX0:A_RXRESET"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXDEEMPH"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXELECIDLE"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXENPMAPHASEALIGN"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXPLLLKDETEN"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXPLLPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXPMASETPHASE"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXPOLARITY"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXPRBSFORCEERR"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXRESET"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXSWING"></div>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_KEEP_ALIGN"></div>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_USE"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_CORRECT_USE"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_INSERT_IDLE_FLAG"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_KEEP_IDLE"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_PRECEDENCE"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_SEQ_2_USE"></div>
+<div id="bits-xc6v-GTX-GTX0:COMMA_DOUBLE"></div>
+<div id="bits-xc6v-GTX-GTX0:DEC_MCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX0:DEC_PCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX0:DEC_VALID_COMMA_ONLY"></div>
+<div id="bits-xc6v-GTX-GTX0:DFE_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX0:GEN_RXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX0:GEN_TXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX0:GTX_CFG_PWRUP"></div>
+<div id="bits-xc6v-GTX-GTX0:LOOPBACK_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX0:MASTER_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX0:MCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX0:PCI_EXPRESS_MODE"></div>
+<div id="bits-xc6v-GTX-GTX0:PCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX0:PDELIDLE_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX0:PHASEALIGN_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX0:PLL_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX0:PMA_CAS_CLK_EN"></div>
+<div id="bits-xc6v-GTX-GTX0:POLARITY_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX0:PRBS_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX0:RCV_TERM_GND"></div>
+<div id="bits-xc6v-GTX-GTX0:RCV_TERM_VTTRX"></div>
+<div id="bits-xc6v-GTX-GTX0:RESET_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX0:RXBUF_OVRD_THRESH"></div>
+<div id="bits-xc6v-GTX-GTX0:RXGEARBOX_USE"></div>
+<div id="bits-xc6v-GTX-GTX0:RXPLL_STARTUP_EN"></div>
+<div id="bits-xc6v-GTX-GTX0:RXPRBSERR_LOOPBACK"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_BUFFER_USE"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_CDR_FORCE_ROTATE"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_DECODE_SEQ_MATCH"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_EN_IDLE_HOLD_CDR"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_EN_IDLE_HOLD_DFE"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_EN_IDLE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_EN_IDLE_RESET_FR"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_EN_IDLE_RESET_PH"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_EN_MODE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_EN_RATE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_EN_REALIGN_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_EN_REALIGN_RESET_BUF2"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_LOSS_OF_SYNC_FSM"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_OVERSAMPLE_MODE"></div>
+<div id="bits-xc6v-GTX-GTX0:SHOW_REALIGN_COMMA"></div>
+<div id="bits-xc6v-GTX-GTX0:TERMINATION_OVRD"></div>
+<div id="bits-xc6v-GTX-GTX0:TXDRIVE_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX0:TXGEARBOX_USE"></div>
+<div id="bits-xc6v-GTX-GTX0:TXOUTCLKPCS_SEL"></div>
+<div id="bits-xc6v-GTX-GTX0:TXPLL_STARTUP_EN"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_BUFFER_USE"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_EN_RATE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_OVERSAMPLE_MODE"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_PMADATA_OPT"></div>
+<div id="bits-xc6v-GTX-GTX0:USR_CODE_ERR_CLR"></div>
+<div id="bits-xc6v-GTX-GTX1:AC_CAP_DIS"></div>
+<div id="bits-xc6v-GTX-GTX1:A_DFEDLYOVRD"></div>
+<div id="bits-xc6v-GTX-GTX1:A_DFETAPOVRD"></div>
+<div id="bits-xc6v-GTX-GTX1:A_GTXRXRESET"></div>
+<div id="bits-xc6v-GTX-GTX1:A_GTXTXRESET"></div>
+<div id="bits-xc6v-GTX-GTX1:A_PLLCLKRXRESET"></div>
+<div id="bits-xc6v-GTX-GTX1:A_PLLCLKTXRESET"></div>
+<div id="bits-xc6v-GTX-GTX1:A_PLLRXRESET"></div>
+<div id="bits-xc6v-GTX-GTX1:A_PLLTXRESET"></div>
+<div id="bits-xc6v-GTX-GTX1:A_PRBSCNTRESET"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXBUFRESET"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXCDRFREQRESET"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXCDRHOLD"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXCDRPHASERESET"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXCDRRESET"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXDFERESET"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXENPMAPHASEALIGN"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXENSAMPLEALIGN"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXPLLLKDETEN"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXPLLPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXPMASETPHASE"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXPOLARITY"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXRESET"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXDEEMPH"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXELECIDLE"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXENPMAPHASEALIGN"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXPLLLKDETEN"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXPLLPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXPMASETPHASE"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXPOLARITY"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXPRBSFORCEERR"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXRESET"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXSWING"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_KEEP_ALIGN"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_USE"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_CORRECT_USE"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_INSERT_IDLE_FLAG"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_KEEP_IDLE"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_PRECEDENCE"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_SEQ_2_USE"></div>
+<div id="bits-xc6v-GTX-GTX1:COMMA_DOUBLE"></div>
+<div id="bits-xc6v-GTX-GTX1:DEC_MCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX1:DEC_PCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX1:DEC_VALID_COMMA_ONLY"></div>
+<div id="bits-xc6v-GTX-GTX1:DFE_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX1:GEN_RXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX1:GEN_TXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX1:GTX_CFG_PWRUP"></div>
+<div id="bits-xc6v-GTX-GTX1:LOOPBACK_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX1:MASTER_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX1:MCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX1:PCI_EXPRESS_MODE"></div>
+<div id="bits-xc6v-GTX-GTX1:PCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX1:PDELIDLE_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX1:PHASEALIGN_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX1:PLL_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX1:PMA_CAS_CLK_EN"></div>
+<div id="bits-xc6v-GTX-GTX1:POLARITY_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX1:PRBS_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX1:RCV_TERM_GND"></div>
+<div id="bits-xc6v-GTX-GTX1:RCV_TERM_VTTRX"></div>
+<div id="bits-xc6v-GTX-GTX1:RESET_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX1:RXBUF_OVRD_THRESH"></div>
+<div id="bits-xc6v-GTX-GTX1:RXGEARBOX_USE"></div>
+<div id="bits-xc6v-GTX-GTX1:RXPLL_STARTUP_EN"></div>
+<div id="bits-xc6v-GTX-GTX1:RXPRBSERR_LOOPBACK"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_BUFFER_USE"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_CDR_FORCE_ROTATE"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_DECODE_SEQ_MATCH"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_EN_IDLE_HOLD_CDR"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_EN_IDLE_HOLD_DFE"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_EN_IDLE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_EN_IDLE_RESET_FR"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_EN_IDLE_RESET_PH"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_EN_MODE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_EN_RATE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_EN_REALIGN_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_EN_REALIGN_RESET_BUF2"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_LOSS_OF_SYNC_FSM"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_OVERSAMPLE_MODE"></div>
+<div id="bits-xc6v-GTX-GTX1:SHOW_REALIGN_COMMA"></div>
+<div id="bits-xc6v-GTX-GTX1:TERMINATION_OVRD"></div>
+<div id="bits-xc6v-GTX-GTX1:TXDRIVE_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX1:TXGEARBOX_USE"></div>
+<div id="bits-xc6v-GTX-GTX1:TXOUTCLKPCS_SEL"></div>
+<div id="bits-xc6v-GTX-GTX1:TXPLL_STARTUP_EN"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_BUFFER_USE"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_EN_RATE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_OVERSAMPLE_MODE"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_PMADATA_OPT"></div>
+<div id="bits-xc6v-GTX-GTX1:USR_CODE_ERR_CLR"></div>
+<div id="bits-xc6v-GTX-GTX2:AC_CAP_DIS"></div>
+<div id="bits-xc6v-GTX-GTX2:A_DFEDLYOVRD"></div>
+<div id="bits-xc6v-GTX-GTX2:A_DFETAPOVRD"></div>
+<div id="bits-xc6v-GTX-GTX2:A_GTXRXRESET"></div>
+<div id="bits-xc6v-GTX-GTX2:A_GTXTXRESET"></div>
+<div id="bits-xc6v-GTX-GTX2:A_PLLCLKRXRESET"></div>
+<div id="bits-xc6v-GTX-GTX2:A_PLLCLKTXRESET"></div>
+<div id="bits-xc6v-GTX-GTX2:A_PLLRXRESET"></div>
+<div id="bits-xc6v-GTX-GTX2:A_PLLTXRESET"></div>
+<div id="bits-xc6v-GTX-GTX2:A_PRBSCNTRESET"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXBUFRESET"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXCDRFREQRESET"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXCDRHOLD"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXCDRPHASERESET"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXCDRRESET"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXDFERESET"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXENPMAPHASEALIGN"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXENSAMPLEALIGN"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXPLLLKDETEN"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXPLLPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXPMASETPHASE"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXPOLARITY"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXRESET"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXDEEMPH"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXELECIDLE"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXENPMAPHASEALIGN"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXPLLLKDETEN"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXPLLPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXPMASETPHASE"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXPOLARITY"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXPRBSFORCEERR"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXRESET"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXSWING"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_KEEP_ALIGN"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_USE"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_CORRECT_USE"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_INSERT_IDLE_FLAG"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_KEEP_IDLE"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_PRECEDENCE"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_SEQ_2_USE"></div>
+<div id="bits-xc6v-GTX-GTX2:COMMA_DOUBLE"></div>
+<div id="bits-xc6v-GTX-GTX2:DEC_MCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX2:DEC_PCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX2:DEC_VALID_COMMA_ONLY"></div>
+<div id="bits-xc6v-GTX-GTX2:DFE_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX2:GEN_RXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX2:GEN_TXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX2:GTX_CFG_PWRUP"></div>
+<div id="bits-xc6v-GTX-GTX2:LOOPBACK_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX2:MASTER_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX2:MCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX2:PCI_EXPRESS_MODE"></div>
+<div id="bits-xc6v-GTX-GTX2:PCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX2:PDELIDLE_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX2:PHASEALIGN_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX2:PLL_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX2:PMA_CAS_CLK_EN"></div>
+<div id="bits-xc6v-GTX-GTX2:POLARITY_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX2:PRBS_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX2:RCV_TERM_GND"></div>
+<div id="bits-xc6v-GTX-GTX2:RCV_TERM_VTTRX"></div>
+<div id="bits-xc6v-GTX-GTX2:RESET_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX2:RXBUF_OVRD_THRESH"></div>
+<div id="bits-xc6v-GTX-GTX2:RXGEARBOX_USE"></div>
+<div id="bits-xc6v-GTX-GTX2:RXPLL_STARTUP_EN"></div>
+<div id="bits-xc6v-GTX-GTX2:RXPRBSERR_LOOPBACK"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_BUFFER_USE"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_CDR_FORCE_ROTATE"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_DECODE_SEQ_MATCH"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_EN_IDLE_HOLD_CDR"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_EN_IDLE_HOLD_DFE"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_EN_IDLE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_EN_IDLE_RESET_FR"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_EN_IDLE_RESET_PH"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_EN_MODE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_EN_RATE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_EN_REALIGN_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_EN_REALIGN_RESET_BUF2"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_LOSS_OF_SYNC_FSM"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_OVERSAMPLE_MODE"></div>
+<div id="bits-xc6v-GTX-GTX2:SHOW_REALIGN_COMMA"></div>
+<div id="bits-xc6v-GTX-GTX2:TERMINATION_OVRD"></div>
+<div id="bits-xc6v-GTX-GTX2:TXDRIVE_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX2:TXGEARBOX_USE"></div>
+<div id="bits-xc6v-GTX-GTX2:TXOUTCLKPCS_SEL"></div>
+<div id="bits-xc6v-GTX-GTX2:TXPLL_STARTUP_EN"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_BUFFER_USE"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_EN_RATE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_OVERSAMPLE_MODE"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_PMADATA_OPT"></div>
+<div id="bits-xc6v-GTX-GTX2:USR_CODE_ERR_CLR"></div>
+<div id="bits-xc6v-GTX-GTX3:AC_CAP_DIS"></div>
+<div id="bits-xc6v-GTX-GTX3:A_DFEDLYOVRD"></div>
+<div id="bits-xc6v-GTX-GTX3:A_DFETAPOVRD"></div>
+<div id="bits-xc6v-GTX-GTX3:A_GTXRXRESET"></div>
+<div id="bits-xc6v-GTX-GTX3:A_GTXTXRESET"></div>
+<div id="bits-xc6v-GTX-GTX3:A_PLLCLKRXRESET"></div>
+<div id="bits-xc6v-GTX-GTX3:A_PLLCLKTXRESET"></div>
+<div id="bits-xc6v-GTX-GTX3:A_PLLRXRESET"></div>
+<div id="bits-xc6v-GTX-GTX3:A_PLLTXRESET"></div>
+<div id="bits-xc6v-GTX-GTX3:A_PRBSCNTRESET"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXBUFRESET"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXCDRFREQRESET"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXCDRHOLD"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXCDRPHASERESET"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXCDRRESET"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXDFERESET"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXENPMAPHASEALIGN"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXENSAMPLEALIGN"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXPLLLKDETEN"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXPLLPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXPMASETPHASE"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXPOLARITY"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXRESET"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXDEEMPH"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXELECIDLE"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXENPMAPHASEALIGN"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXPLLLKDETEN"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXPLLPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXPMASETPHASE"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXPOLARITY"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXPRBSFORCEERR"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXRESET"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXSWING"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_KEEP_ALIGN"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_USE"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_CORRECT_USE"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_INSERT_IDLE_FLAG"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_KEEP_IDLE"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_PRECEDENCE"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_SEQ_2_USE"></div>
+<div id="bits-xc6v-GTX-GTX3:COMMA_DOUBLE"></div>
+<div id="bits-xc6v-GTX-GTX3:DEC_MCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX3:DEC_PCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX3:DEC_VALID_COMMA_ONLY"></div>
+<div id="bits-xc6v-GTX-GTX3:DFE_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX3:GEN_RXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX3:GEN_TXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX3:GTX_CFG_PWRUP"></div>
+<div id="bits-xc6v-GTX-GTX3:LOOPBACK_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX3:MASTER_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX3:MCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX3:PCI_EXPRESS_MODE"></div>
+<div id="bits-xc6v-GTX-GTX3:PCOMMA_DETECT"></div>
+<div id="bits-xc6v-GTX-GTX3:PDELIDLE_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX3:PHASEALIGN_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX3:PLL_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX3:PMA_CAS_CLK_EN"></div>
+<div id="bits-xc6v-GTX-GTX3:POLARITY_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX3:PRBS_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX3:RCV_TERM_GND"></div>
+<div id="bits-xc6v-GTX-GTX3:RCV_TERM_VTTRX"></div>
+<div id="bits-xc6v-GTX-GTX3:RESET_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX3:RXBUF_OVRD_THRESH"></div>
+<div id="bits-xc6v-GTX-GTX3:RXGEARBOX_USE"></div>
+<div id="bits-xc6v-GTX-GTX3:RXPLL_STARTUP_EN"></div>
+<div id="bits-xc6v-GTX-GTX3:RXPRBSERR_LOOPBACK"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_BUFFER_USE"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_CDR_FORCE_ROTATE"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_DECODE_SEQ_MATCH"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_EN_IDLE_HOLD_CDR"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_EN_IDLE_HOLD_DFE"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_EN_IDLE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_EN_IDLE_RESET_FR"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_EN_IDLE_RESET_PH"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_EN_MODE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_EN_RATE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_EN_REALIGN_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_EN_REALIGN_RESET_BUF2"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_LOSS_OF_SYNC_FSM"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_OVERSAMPLE_MODE"></div>
+<div id="bits-xc6v-GTX-GTX3:SHOW_REALIGN_COMMA"></div>
+<div id="bits-xc6v-GTX-GTX3:TERMINATION_OVRD"></div>
+<div id="bits-xc6v-GTX-GTX3:TXDRIVE_DRP_EN"></div>
+<div id="bits-xc6v-GTX-GTX3:TXGEARBOX_USE"></div>
+<div id="bits-xc6v-GTX-GTX3:TXOUTCLKPCS_SEL"></div>
+<div id="bits-xc6v-GTX-GTX3:TXPLL_STARTUP_EN"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_BUFFER_USE"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_EN_RATE_RESET_BUF"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_OVERSAMPLE_MODE"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_PMADATA_OPT"></div>
+<div id="bits-xc6v-GTX-GTX3:USR_CODE_ERR_CLR"></div>
+<div id="bits-xc6v-GTX-HCLK_GTX:DRPMASK_N"></div>
+<div id="bits-xc6v-GTX-HCLK_GTX:DRPMASK_S"></div>
+<div id="bits-xc6v-GTX-IBUFDS_GTX0:CLKCM_CFG"></div>
+<div id="bits-xc6v-GTX-IBUFDS_GTX0:CLKRCV_TRST"></div>
+<div id="bits-xc6v-GTX-IBUFDS_GTX1:CLKCM_CFG"></div>
+<div id="bits-xc6v-GTX-IBUFDS_GTX1:CLKRCV_TRST"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:AC_CAP_DIS</th><th>[2, 28, 58]</th></tr>
+<tr><th>GTX0:A_DFEDLYOVRD</th><th>[5, 28, 31]</th></tr>
+<tr><th>GTX0:A_DFETAPOVRD</th><th>[5, 29, 31]</th></tr>
+<tr><th>GTX0:A_GTXRXRESET</th><th>[3, 28, 3]</th></tr>
+<tr><th>GTX0:A_GTXTXRESET</th><th>[3, 29, 2]</th></tr>
+<tr><th>GTX0:A_PLLCLKRXRESET</th><th>[3, 28, 38]</th></tr>
+<tr><th>GTX0:A_PLLCLKTXRESET</th><th>[4, 28, 6]</th></tr>
+<tr><th>GTX0:A_PLLRXRESET</th><th>[3, 28, 37]</th></tr>
+<tr><th>GTX0:A_PLLTXRESET</th><th>[4, 28, 5]</th></tr>
+<tr><th>GTX0:A_PRBSCNTRESET</th><th>[5, 28, 23]</th></tr>
+<tr><th>GTX0:A_RXBUFRESET</th><th>[3, 29, 3]</th></tr>
+<tr><th>GTX0:A_RXCDRFREQRESET</th><th>[3, 29, 5]</th></tr>
+<tr><th>GTX0:A_RXCDRHOLD</th><th>[3, 28, 5]</th></tr>
+<tr><th>GTX0:A_RXCDRPHASERESET</th><th>[3, 28, 6]</th></tr>
+<tr><th>GTX0:A_RXCDRRESET</th><th>[3, 28, 2]</th></tr>
+<tr><th>GTX0:A_RXDFERESET</th><th>[3, 29, 6]</th></tr>
+<tr><th>GTX0:A_RXENPMAPHASEALIGN</th><th>[4, 28, 47]</th></tr>
+<tr><th>GTX0:A_RXENSAMPLEALIGN</th><th>[5, 28, 15]</th></tr>
+<tr><th>GTX0:A_RXPLLLKDETEN</th><th>[3, 29, 37]</th></tr>
+<tr><th>GTX0:A_RXPLLPOWERDOWN</th><th>[3, 28, 39]</th></tr>
+<tr><th>GTX0:A_RXPMASETPHASE</th><th>[4, 29, 46]</th></tr>
+<tr><th>GTX0:A_RXPOLARITY</th><th>[4, 28, 45]</th></tr>
+<tr><th>GTX0:A_RXRESET</th><th>[3, 28, 4]</th></tr>
+<tr><th>GTX0:A_TXDEEMPH</th><th>[7, 29, 31]</th></tr>
+<tr><th>GTX0:A_TXELECIDLE</th><th>[4, 28, 15]</th></tr>
+<tr><th>GTX0:A_TXENPMAPHASEALIGN</th><th>[5, 29, 14]</th></tr>
+<tr><th>GTX0:A_TXPLLLKDETEN</th><th>[4, 29, 5]</th></tr>
+<tr><th>GTX0:A_TXPLLPOWERDOWN</th><th>[4, 28, 7]</th></tr>
+<tr><th>GTX0:A_TXPMASETPHASE</th><th>[5, 28, 14]</th></tr>
+<tr><th>GTX0:A_TXPOLARITY</th><th>[4, 29, 45]</th></tr>
+<tr><th>GTX0:A_TXPRBSFORCEERR</th><th>[5, 28, 21]</th></tr>
+<tr><th>GTX0:A_TXRESET</th><th>[3, 29, 4]</th></tr>
+<tr><th>GTX0:A_TXSWING</th><th>[7, 28, 31]</th></tr>
+<tr><th>GTX0:CHAN_BOND_KEEP_ALIGN</th><th>[1, 28, 15]</th></tr>
+<tr><th>GTX0:CHAN_BOND_SEQ_2_USE</th><th>[1, 28, 23]</th></tr>
+<tr><th>GTX0:CLK_CORRECT_USE</th><th>[1, 28, 47]</th></tr>
+<tr><th>GTX0:CLK_COR_INSERT_IDLE_FLAG</th><th>[2, 29, 15]</th></tr>
+<tr><th>GTX0:CLK_COR_KEEP_IDLE</th><th>[1, 29, 55]</th></tr>
+<tr><th>GTX0:CLK_COR_PRECEDENCE</th><th>[1, 29, 47]</th></tr>
+<tr><th>GTX0:CLK_COR_SEQ_2_USE</th><th>[2, 28, 15]</th></tr>
+<tr><th>GTX0:COMMA_DOUBLE</th><th>[5, 28, 61]</th></tr>
+<tr><th>GTX0:DEC_MCOMMA_DETECT</th><th>[2, 29, 37]</th></tr>
+<tr><th>GTX0:DEC_PCOMMA_DETECT</th><th>[2, 28, 37]</th></tr>
+<tr><th>GTX0:DEC_VALID_COMMA_ONLY</th><th>[2, 29, 39]</th></tr>
+<tr><th>GTX0:DFE_DRP_EN</th><th>[5, 29, 39]</th></tr>
+<tr><th>GTX0:GEN_RXUSRCLK</th><th>[2, 29, 63]</th></tr>
+<tr><th>GTX0:GEN_TXUSRCLK</th><th>[6, 29, 15]</th></tr>
+<tr><th>GTX0:GTX_CFG_PWRUP</th><th>[2, 29, 57]</th></tr>
+<tr><th>GTX0:LOOPBACK_DRP_EN</th><th>[5, 28, 16]</th></tr>
+<tr><th>GTX0:MASTER_DRP_EN</th><th>[3, 29, 7]</th></tr>
+<tr><th>GTX0:MCOMMA_DETECT</th><th>[6, 28, 5]</th></tr>
+<tr><th>GTX0:PCI_EXPRESS_MODE</th><th>[4, 29, 15]</th></tr>
+<tr><th>GTX0:PCOMMA_DETECT</th><th>[6, 28, 13]</th></tr>
+<tr><th>GTX0:PDELIDLE_DRP_EN</th><th>[4, 29, 6]</th></tr>
+<tr><th>GTX0:PHASEALIGN_DRP_EN</th><th>[5, 29, 15]</th></tr>
+<tr><th>GTX0:PLL_DRP_EN</th><th>[3, 29, 38]</th></tr>
+<tr><th>GTX0:PMA_CAS_CLK_EN</th><th>[4, 29, 23]</th></tr>
+<tr><th>GTX0:POLARITY_DRP_EN</th><th>[4, 28, 46]</th></tr>
+<tr><th>GTX0:PRBS_DRP_EN</th><th>[5, 29, 23]</th></tr>
+<tr><th>GTX0:RCV_TERM_GND</th><th>[5, 29, 51]</th></tr>
+<tr><th>GTX0:RCV_TERM_VTTRX</th><th>[5, 28, 52]</th></tr>
+<tr><th>GTX0:RESET_DRP_EN</th><th>[3, 28, 7]</th></tr>
+<tr><th>GTX0:RXBUF_OVRD_THRESH</th><th>[1, 28, 38]</th></tr>
+<tr><th>GTX0:RXGEARBOX_USE</th><th>[3, 29, 1]</th></tr>
+<tr><th>GTX0:RXPLL_STARTUP_EN</th><th>[3, 29, 27]</th></tr>
+<tr><th>GTX0:RXPRBSERR_LOOPBACK</th><th>[5, 28, 20]</th></tr>
+<tr><th>GTX0:RX_BUFFER_USE</th><th>[0, 28, 39]</th></tr>
+<tr><th>GTX0:RX_CDR_FORCE_ROTATE</th><th>[2, 29, 23]</th></tr>
+<tr><th>GTX0:RX_DECODE_SEQ_MATCH</th><th>[2, 29, 38]</th></tr>
+<tr><th>GTX0:RX_EN_IDLE_HOLD_CDR</th><th>[5, 29, 28]</th></tr>
+<tr><th>GTX0:RX_EN_IDLE_HOLD_DFE</th><th>[5, 29, 29]</th></tr>
+<tr><th>GTX0:RX_EN_IDLE_RESET_BUF</th><th>[1, 28, 29]</th></tr>
+<tr><th>GTX0:RX_EN_IDLE_RESET_FR</th><th>[5, 28, 29]</th></tr>
+<tr><th>GTX0:RX_EN_IDLE_RESET_PH</th><th>[1, 29, 23]</th></tr>
+<tr><th>GTX0:RX_EN_MODE_RESET_BUF</th><th>[1, 29, 15]</th></tr>
+<tr><th>GTX0:RX_EN_RATE_RESET_BUF</th><th>[1, 29, 7]</th></tr>
+<tr><th>GTX0:RX_EN_REALIGN_RESET_BUF</th><th>[1, 28, 7]</th></tr>
+<tr><th>GTX0:RX_EN_REALIGN_RESET_BUF2</th><th>[9, 28, 31]</th></tr>
+<tr><th>GTX0:RX_LOSS_OF_SYNC_FSM</th><th>[0, 29, 39]</th></tr>
+<tr><th>GTX0:RX_OVERSAMPLE_MODE</th><th>[3, 29, 39]</th></tr>
+<tr><th>GTX0:SHOW_REALIGN_COMMA</th><th>[2, 28, 23]</th></tr>
+<tr><th>GTX0:TERMINATION_OVRD</th><th>[5, 28, 51]</th></tr>
+<tr><th>GTX0:TXDRIVE_DRP_EN</th><th>[7, 28, 39]</th></tr>
+<tr><th>GTX0:TXGEARBOX_USE</th><th>[5, 29, 63]</th></tr>
+<tr><th>GTX0:TXOUTCLKPCS_SEL</th><th>[7, 28, 7]</th></tr>
+<tr><th>GTX0:TXPLL_STARTUP_EN</th><th>[3, 29, 59]</th></tr>
+<tr><th>GTX0:TX_BUFFER_USE</th><th>[6, 29, 13]</th></tr>
+<tr><th>GTX0:TX_EN_RATE_RESET_BUF</th><th>[4, 29, 63]</th></tr>
+<tr><th>GTX0:TX_OVERSAMPLE_MODE</th><th>[4, 29, 7]</th></tr>
+<tr><th>GTX0:TX_PMADATA_OPT</th><th>[4, 29, 47]</th></tr>
+<tr><th>GTX0:USR_CODE_ERR_CLR</th><th>[2, 28, 38]</th></tr>
+<tr><th>GTX1:AC_CAP_DIS</th><th>[12, 28, 58]</th></tr>
+<tr><th>GTX1:A_DFEDLYOVRD</th><th>[15, 28, 31]</th></tr>
+<tr><th>GTX1:A_DFETAPOVRD</th><th>[15, 29, 31]</th></tr>
+<tr><th>GTX1:A_GTXRXRESET</th><th>[13, 28, 3]</th></tr>
+<tr><th>GTX1:A_GTXTXRESET</th><th>[13, 29, 2]</th></tr>
+<tr><th>GTX1:A_PLLCLKRXRESET</th><th>[13, 28, 38]</th></tr>
+<tr><th>GTX1:A_PLLCLKTXRESET</th><th>[14, 28, 6]</th></tr>
+<tr><th>GTX1:A_PLLRXRESET</th><th>[13, 28, 37]</th></tr>
+<tr><th>GTX1:A_PLLTXRESET</th><th>[14, 28, 5]</th></tr>
+<tr><th>GTX1:A_PRBSCNTRESET</th><th>[15, 28, 23]</th></tr>
+<tr><th>GTX1:A_RXBUFRESET</th><th>[13, 29, 3]</th></tr>
+<tr><th>GTX1:A_RXCDRFREQRESET</th><th>[13, 29, 5]</th></tr>
+<tr><th>GTX1:A_RXCDRHOLD</th><th>[13, 28, 5]</th></tr>
+<tr><th>GTX1:A_RXCDRPHASERESET</th><th>[13, 28, 6]</th></tr>
+<tr><th>GTX1:A_RXCDRRESET</th><th>[13, 28, 2]</th></tr>
+<tr><th>GTX1:A_RXDFERESET</th><th>[13, 29, 6]</th></tr>
+<tr><th>GTX1:A_RXENPMAPHASEALIGN</th><th>[14, 28, 47]</th></tr>
+<tr><th>GTX1:A_RXENSAMPLEALIGN</th><th>[15, 28, 15]</th></tr>
+<tr><th>GTX1:A_RXPLLLKDETEN</th><th>[13, 29, 37]</th></tr>
+<tr><th>GTX1:A_RXPLLPOWERDOWN</th><th>[13, 28, 39]</th></tr>
+<tr><th>GTX1:A_RXPMASETPHASE</th><th>[14, 29, 46]</th></tr>
+<tr><th>GTX1:A_RXPOLARITY</th><th>[14, 28, 45]</th></tr>
+<tr><th>GTX1:A_RXRESET</th><th>[13, 28, 4]</th></tr>
+<tr><th>GTX1:A_TXDEEMPH</th><th>[17, 29, 31]</th></tr>
+<tr><th>GTX1:A_TXELECIDLE</th><th>[14, 28, 15]</th></tr>
+<tr><th>GTX1:A_TXENPMAPHASEALIGN</th><th>[15, 29, 14]</th></tr>
+<tr><th>GTX1:A_TXPLLLKDETEN</th><th>[14, 29, 5]</th></tr>
+<tr><th>GTX1:A_TXPLLPOWERDOWN</th><th>[14, 28, 7]</th></tr>
+<tr><th>GTX1:A_TXPMASETPHASE</th><th>[15, 28, 14]</th></tr>
+<tr><th>GTX1:A_TXPOLARITY</th><th>[14, 29, 45]</th></tr>
+<tr><th>GTX1:A_TXPRBSFORCEERR</th><th>[15, 28, 21]</th></tr>
+<tr><th>GTX1:A_TXRESET</th><th>[13, 29, 4]</th></tr>
+<tr><th>GTX1:A_TXSWING</th><th>[17, 28, 31]</th></tr>
+<tr><th>GTX1:CHAN_BOND_KEEP_ALIGN</th><th>[11, 28, 15]</th></tr>
+<tr><th>GTX1:CHAN_BOND_SEQ_2_USE</th><th>[11, 28, 23]</th></tr>
+<tr><th>GTX1:CLK_CORRECT_USE</th><th>[11, 28, 47]</th></tr>
+<tr><th>GTX1:CLK_COR_INSERT_IDLE_FLAG</th><th>[12, 29, 15]</th></tr>
+<tr><th>GTX1:CLK_COR_KEEP_IDLE</th><th>[11, 29, 55]</th></tr>
+<tr><th>GTX1:CLK_COR_PRECEDENCE</th><th>[11, 29, 47]</th></tr>
+<tr><th>GTX1:CLK_COR_SEQ_2_USE</th><th>[12, 28, 15]</th></tr>
+<tr><th>GTX1:COMMA_DOUBLE</th><th>[15, 28, 61]</th></tr>
+<tr><th>GTX1:DEC_MCOMMA_DETECT</th><th>[12, 29, 37]</th></tr>
+<tr><th>GTX1:DEC_PCOMMA_DETECT</th><th>[12, 28, 37]</th></tr>
+<tr><th>GTX1:DEC_VALID_COMMA_ONLY</th><th>[12, 29, 39]</th></tr>
+<tr><th>GTX1:DFE_DRP_EN</th><th>[15, 29, 39]</th></tr>
+<tr><th>GTX1:GEN_RXUSRCLK</th><th>[12, 29, 63]</th></tr>
+<tr><th>GTX1:GEN_TXUSRCLK</th><th>[16, 29, 15]</th></tr>
+<tr><th>GTX1:GTX_CFG_PWRUP</th><th>[12, 29, 57]</th></tr>
+<tr><th>GTX1:LOOPBACK_DRP_EN</th><th>[15, 28, 16]</th></tr>
+<tr><th>GTX1:MASTER_DRP_EN</th><th>[13, 29, 7]</th></tr>
+<tr><th>GTX1:MCOMMA_DETECT</th><th>[16, 28, 5]</th></tr>
+<tr><th>GTX1:PCI_EXPRESS_MODE</th><th>[14, 29, 15]</th></tr>
+<tr><th>GTX1:PCOMMA_DETECT</th><th>[16, 28, 13]</th></tr>
+<tr><th>GTX1:PDELIDLE_DRP_EN</th><th>[14, 29, 6]</th></tr>
+<tr><th>GTX1:PHASEALIGN_DRP_EN</th><th>[15, 29, 15]</th></tr>
+<tr><th>GTX1:PLL_DRP_EN</th><th>[13, 29, 38]</th></tr>
+<tr><th>GTX1:PMA_CAS_CLK_EN</th><th>[14, 29, 23]</th></tr>
+<tr><th>GTX1:POLARITY_DRP_EN</th><th>[14, 28, 46]</th></tr>
+<tr><th>GTX1:PRBS_DRP_EN</th><th>[15, 29, 23]</th></tr>
+<tr><th>GTX1:RCV_TERM_GND</th><th>[15, 29, 51]</th></tr>
+<tr><th>GTX1:RCV_TERM_VTTRX</th><th>[15, 28, 52]</th></tr>
+<tr><th>GTX1:RESET_DRP_EN</th><th>[13, 28, 7]</th></tr>
+<tr><th>GTX1:RXBUF_OVRD_THRESH</th><th>[11, 28, 38]</th></tr>
+<tr><th>GTX1:RXGEARBOX_USE</th><th>[13, 29, 1]</th></tr>
+<tr><th>GTX1:RXPLL_STARTUP_EN</th><th>[13, 29, 27]</th></tr>
+<tr><th>GTX1:RXPRBSERR_LOOPBACK</th><th>[15, 28, 20]</th></tr>
+<tr><th>GTX1:RX_BUFFER_USE</th><th>[10, 28, 39]</th></tr>
+<tr><th>GTX1:RX_CDR_FORCE_ROTATE</th><th>[12, 29, 23]</th></tr>
+<tr><th>GTX1:RX_DECODE_SEQ_MATCH</th><th>[12, 29, 38]</th></tr>
+<tr><th>GTX1:RX_EN_IDLE_HOLD_CDR</th><th>[15, 29, 28]</th></tr>
+<tr><th>GTX1:RX_EN_IDLE_HOLD_DFE</th><th>[15, 29, 29]</th></tr>
+<tr><th>GTX1:RX_EN_IDLE_RESET_BUF</th><th>[11, 28, 29]</th></tr>
+<tr><th>GTX1:RX_EN_IDLE_RESET_FR</th><th>[15, 28, 29]</th></tr>
+<tr><th>GTX1:RX_EN_IDLE_RESET_PH</th><th>[11, 29, 23]</th></tr>
+<tr><th>GTX1:RX_EN_MODE_RESET_BUF</th><th>[11, 29, 15]</th></tr>
+<tr><th>GTX1:RX_EN_RATE_RESET_BUF</th><th>[11, 29, 7]</th></tr>
+<tr><th>GTX1:RX_EN_REALIGN_RESET_BUF</th><th>[11, 28, 7]</th></tr>
+<tr><th>GTX1:RX_EN_REALIGN_RESET_BUF2</th><th>[19, 28, 31]</th></tr>
+<tr><th>GTX1:RX_LOSS_OF_SYNC_FSM</th><th>[10, 29, 39]</th></tr>
+<tr><th>GTX1:RX_OVERSAMPLE_MODE</th><th>[13, 29, 39]</th></tr>
+<tr><th>GTX1:SHOW_REALIGN_COMMA</th><th>[12, 28, 23]</th></tr>
+<tr><th>GTX1:TERMINATION_OVRD</th><th>[15, 28, 51]</th></tr>
+<tr><th>GTX1:TXDRIVE_DRP_EN</th><th>[17, 28, 39]</th></tr>
+<tr><th>GTX1:TXGEARBOX_USE</th><th>[15, 29, 63]</th></tr>
+<tr><th>GTX1:TXOUTCLKPCS_SEL</th><th>[17, 28, 7]</th></tr>
+<tr><th>GTX1:TXPLL_STARTUP_EN</th><th>[13, 29, 59]</th></tr>
+<tr><th>GTX1:TX_BUFFER_USE</th><th>[16, 29, 13]</th></tr>
+<tr><th>GTX1:TX_EN_RATE_RESET_BUF</th><th>[14, 29, 63]</th></tr>
+<tr><th>GTX1:TX_OVERSAMPLE_MODE</th><th>[14, 29, 7]</th></tr>
+<tr><th>GTX1:TX_PMADATA_OPT</th><th>[14, 29, 47]</th></tr>
+<tr><th>GTX1:USR_CODE_ERR_CLR</th><th>[12, 28, 38]</th></tr>
+<tr><th>GTX2:AC_CAP_DIS</th><th>[22, 28, 58]</th></tr>
+<tr><th>GTX2:A_DFEDLYOVRD</th><th>[25, 28, 31]</th></tr>
+<tr><th>GTX2:A_DFETAPOVRD</th><th>[25, 29, 31]</th></tr>
+<tr><th>GTX2:A_GTXRXRESET</th><th>[23, 28, 3]</th></tr>
+<tr><th>GTX2:A_GTXTXRESET</th><th>[23, 29, 2]</th></tr>
+<tr><th>GTX2:A_PLLCLKRXRESET</th><th>[23, 28, 38]</th></tr>
+<tr><th>GTX2:A_PLLCLKTXRESET</th><th>[24, 28, 6]</th></tr>
+<tr><th>GTX2:A_PLLRXRESET</th><th>[23, 28, 37]</th></tr>
+<tr><th>GTX2:A_PLLTXRESET</th><th>[24, 28, 5]</th></tr>
+<tr><th>GTX2:A_PRBSCNTRESET</th><th>[25, 28, 23]</th></tr>
+<tr><th>GTX2:A_RXBUFRESET</th><th>[23, 29, 3]</th></tr>
+<tr><th>GTX2:A_RXCDRFREQRESET</th><th>[23, 29, 5]</th></tr>
+<tr><th>GTX2:A_RXCDRHOLD</th><th>[23, 28, 5]</th></tr>
+<tr><th>GTX2:A_RXCDRPHASERESET</th><th>[23, 28, 6]</th></tr>
+<tr><th>GTX2:A_RXCDRRESET</th><th>[23, 28, 2]</th></tr>
+<tr><th>GTX2:A_RXDFERESET</th><th>[23, 29, 6]</th></tr>
+<tr><th>GTX2:A_RXENPMAPHASEALIGN</th><th>[24, 28, 47]</th></tr>
+<tr><th>GTX2:A_RXENSAMPLEALIGN</th><th>[25, 28, 15]</th></tr>
+<tr><th>GTX2:A_RXPLLLKDETEN</th><th>[23, 29, 37]</th></tr>
+<tr><th>GTX2:A_RXPLLPOWERDOWN</th><th>[23, 28, 39]</th></tr>
+<tr><th>GTX2:A_RXPMASETPHASE</th><th>[24, 29, 46]</th></tr>
+<tr><th>GTX2:A_RXPOLARITY</th><th>[24, 28, 45]</th></tr>
+<tr><th>GTX2:A_RXRESET</th><th>[23, 28, 4]</th></tr>
+<tr><th>GTX2:A_TXDEEMPH</th><th>[27, 29, 31]</th></tr>
+<tr><th>GTX2:A_TXELECIDLE</th><th>[24, 28, 15]</th></tr>
+<tr><th>GTX2:A_TXENPMAPHASEALIGN</th><th>[25, 29, 14]</th></tr>
+<tr><th>GTX2:A_TXPLLLKDETEN</th><th>[24, 29, 5]</th></tr>
+<tr><th>GTX2:A_TXPLLPOWERDOWN</th><th>[24, 28, 7]</th></tr>
+<tr><th>GTX2:A_TXPMASETPHASE</th><th>[25, 28, 14]</th></tr>
+<tr><th>GTX2:A_TXPOLARITY</th><th>[24, 29, 45]</th></tr>
+<tr><th>GTX2:A_TXPRBSFORCEERR</th><th>[25, 28, 21]</th></tr>
+<tr><th>GTX2:A_TXRESET</th><th>[23, 29, 4]</th></tr>
+<tr><th>GTX2:A_TXSWING</th><th>[27, 28, 31]</th></tr>
+<tr><th>GTX2:CHAN_BOND_KEEP_ALIGN</th><th>[21, 28, 15]</th></tr>
+<tr><th>GTX2:CHAN_BOND_SEQ_2_USE</th><th>[21, 28, 23]</th></tr>
+<tr><th>GTX2:CLK_CORRECT_USE</th><th>[21, 28, 47]</th></tr>
+<tr><th>GTX2:CLK_COR_INSERT_IDLE_FLAG</th><th>[22, 29, 15]</th></tr>
+<tr><th>GTX2:CLK_COR_KEEP_IDLE</th><th>[21, 29, 55]</th></tr>
+<tr><th>GTX2:CLK_COR_PRECEDENCE</th><th>[21, 29, 47]</th></tr>
+<tr><th>GTX2:CLK_COR_SEQ_2_USE</th><th>[22, 28, 15]</th></tr>
+<tr><th>GTX2:COMMA_DOUBLE</th><th>[25, 28, 61]</th></tr>
+<tr><th>GTX2:DEC_MCOMMA_DETECT</th><th>[22, 29, 37]</th></tr>
+<tr><th>GTX2:DEC_PCOMMA_DETECT</th><th>[22, 28, 37]</th></tr>
+<tr><th>GTX2:DEC_VALID_COMMA_ONLY</th><th>[22, 29, 39]</th></tr>
+<tr><th>GTX2:DFE_DRP_EN</th><th>[25, 29, 39]</th></tr>
+<tr><th>GTX2:GEN_RXUSRCLK</th><th>[22, 29, 63]</th></tr>
+<tr><th>GTX2:GEN_TXUSRCLK</th><th>[26, 29, 15]</th></tr>
+<tr><th>GTX2:GTX_CFG_PWRUP</th><th>[22, 29, 57]</th></tr>
+<tr><th>GTX2:LOOPBACK_DRP_EN</th><th>[25, 28, 16]</th></tr>
+<tr><th>GTX2:MASTER_DRP_EN</th><th>[23, 29, 7]</th></tr>
+<tr><th>GTX2:MCOMMA_DETECT</th><th>[26, 28, 5]</th></tr>
+<tr><th>GTX2:PCI_EXPRESS_MODE</th><th>[24, 29, 15]</th></tr>
+<tr><th>GTX2:PCOMMA_DETECT</th><th>[26, 28, 13]</th></tr>
+<tr><th>GTX2:PDELIDLE_DRP_EN</th><th>[24, 29, 6]</th></tr>
+<tr><th>GTX2:PHASEALIGN_DRP_EN</th><th>[25, 29, 15]</th></tr>
+<tr><th>GTX2:PLL_DRP_EN</th><th>[23, 29, 38]</th></tr>
+<tr><th>GTX2:PMA_CAS_CLK_EN</th><th>[24, 29, 23]</th></tr>
+<tr><th>GTX2:POLARITY_DRP_EN</th><th>[24, 28, 46]</th></tr>
+<tr><th>GTX2:PRBS_DRP_EN</th><th>[25, 29, 23]</th></tr>
+<tr><th>GTX2:RCV_TERM_GND</th><th>[25, 29, 51]</th></tr>
+<tr><th>GTX2:RCV_TERM_VTTRX</th><th>[25, 28, 52]</th></tr>
+<tr><th>GTX2:RESET_DRP_EN</th><th>[23, 28, 7]</th></tr>
+<tr><th>GTX2:RXBUF_OVRD_THRESH</th><th>[21, 28, 38]</th></tr>
+<tr><th>GTX2:RXGEARBOX_USE</th><th>[23, 29, 1]</th></tr>
+<tr><th>GTX2:RXPLL_STARTUP_EN</th><th>[23, 29, 27]</th></tr>
+<tr><th>GTX2:RXPRBSERR_LOOPBACK</th><th>[25, 28, 20]</th></tr>
+<tr><th>GTX2:RX_BUFFER_USE</th><th>[20, 28, 39]</th></tr>
+<tr><th>GTX2:RX_CDR_FORCE_ROTATE</th><th>[22, 29, 23]</th></tr>
+<tr><th>GTX2:RX_DECODE_SEQ_MATCH</th><th>[22, 29, 38]</th></tr>
+<tr><th>GTX2:RX_EN_IDLE_HOLD_CDR</th><th>[25, 29, 28]</th></tr>
+<tr><th>GTX2:RX_EN_IDLE_HOLD_DFE</th><th>[25, 29, 29]</th></tr>
+<tr><th>GTX2:RX_EN_IDLE_RESET_BUF</th><th>[21, 28, 29]</th></tr>
+<tr><th>GTX2:RX_EN_IDLE_RESET_FR</th><th>[25, 28, 29]</th></tr>
+<tr><th>GTX2:RX_EN_IDLE_RESET_PH</th><th>[21, 29, 23]</th></tr>
+<tr><th>GTX2:RX_EN_MODE_RESET_BUF</th><th>[21, 29, 15]</th></tr>
+<tr><th>GTX2:RX_EN_RATE_RESET_BUF</th><th>[21, 29, 7]</th></tr>
+<tr><th>GTX2:RX_EN_REALIGN_RESET_BUF</th><th>[21, 28, 7]</th></tr>
+<tr><th>GTX2:RX_EN_REALIGN_RESET_BUF2</th><th>[29, 28, 31]</th></tr>
+<tr><th>GTX2:RX_LOSS_OF_SYNC_FSM</th><th>[20, 29, 39]</th></tr>
+<tr><th>GTX2:RX_OVERSAMPLE_MODE</th><th>[23, 29, 39]</th></tr>
+<tr><th>GTX2:SHOW_REALIGN_COMMA</th><th>[22, 28, 23]</th></tr>
+<tr><th>GTX2:TERMINATION_OVRD</th><th>[25, 28, 51]</th></tr>
+<tr><th>GTX2:TXDRIVE_DRP_EN</th><th>[27, 28, 39]</th></tr>
+<tr><th>GTX2:TXGEARBOX_USE</th><th>[25, 29, 63]</th></tr>
+<tr><th>GTX2:TXOUTCLKPCS_SEL</th><th>[27, 28, 7]</th></tr>
+<tr><th>GTX2:TXPLL_STARTUP_EN</th><th>[23, 29, 59]</th></tr>
+<tr><th>GTX2:TX_BUFFER_USE</th><th>[26, 29, 13]</th></tr>
+<tr><th>GTX2:TX_EN_RATE_RESET_BUF</th><th>[24, 29, 63]</th></tr>
+<tr><th>GTX2:TX_OVERSAMPLE_MODE</th><th>[24, 29, 7]</th></tr>
+<tr><th>GTX2:TX_PMADATA_OPT</th><th>[24, 29, 47]</th></tr>
+<tr><th>GTX2:USR_CODE_ERR_CLR</th><th>[22, 28, 38]</th></tr>
+<tr><th>GTX3:AC_CAP_DIS</th><th>[32, 28, 58]</th></tr>
+<tr><th>GTX3:A_DFEDLYOVRD</th><th>[35, 28, 31]</th></tr>
+<tr><th>GTX3:A_DFETAPOVRD</th><th>[35, 29, 31]</th></tr>
+<tr><th>GTX3:A_GTXRXRESET</th><th>[33, 28, 3]</th></tr>
+<tr><th>GTX3:A_GTXTXRESET</th><th>[33, 29, 2]</th></tr>
+<tr><th>GTX3:A_PLLCLKRXRESET</th><th>[33, 28, 38]</th></tr>
+<tr><th>GTX3:A_PLLCLKTXRESET</th><th>[34, 28, 6]</th></tr>
+<tr><th>GTX3:A_PLLRXRESET</th><th>[33, 28, 37]</th></tr>
+<tr><th>GTX3:A_PLLTXRESET</th><th>[34, 28, 5]</th></tr>
+<tr><th>GTX3:A_PRBSCNTRESET</th><th>[35, 28, 23]</th></tr>
+<tr><th>GTX3:A_RXBUFRESET</th><th>[33, 29, 3]</th></tr>
+<tr><th>GTX3:A_RXCDRFREQRESET</th><th>[33, 29, 5]</th></tr>
+<tr><th>GTX3:A_RXCDRHOLD</th><th>[33, 28, 5]</th></tr>
+<tr><th>GTX3:A_RXCDRPHASERESET</th><th>[33, 28, 6]</th></tr>
+<tr><th>GTX3:A_RXCDRRESET</th><th>[33, 28, 2]</th></tr>
+<tr><th>GTX3:A_RXDFERESET</th><th>[33, 29, 6]</th></tr>
+<tr><th>GTX3:A_RXENPMAPHASEALIGN</th><th>[34, 28, 47]</th></tr>
+<tr><th>GTX3:A_RXENSAMPLEALIGN</th><th>[35, 28, 15]</th></tr>
+<tr><th>GTX3:A_RXPLLLKDETEN</th><th>[33, 29, 37]</th></tr>
+<tr><th>GTX3:A_RXPLLPOWERDOWN</th><th>[33, 28, 39]</th></tr>
+<tr><th>GTX3:A_RXPMASETPHASE</th><th>[34, 29, 46]</th></tr>
+<tr><th>GTX3:A_RXPOLARITY</th><th>[34, 28, 45]</th></tr>
+<tr><th>GTX3:A_RXRESET</th><th>[33, 28, 4]</th></tr>
+<tr><th>GTX3:A_TXDEEMPH</th><th>[37, 29, 31]</th></tr>
+<tr><th>GTX3:A_TXELECIDLE</th><th>[34, 28, 15]</th></tr>
+<tr><th>GTX3:A_TXENPMAPHASEALIGN</th><th>[35, 29, 14]</th></tr>
+<tr><th>GTX3:A_TXPLLLKDETEN</th><th>[34, 29, 5]</th></tr>
+<tr><th>GTX3:A_TXPLLPOWERDOWN</th><th>[34, 28, 7]</th></tr>
+<tr><th>GTX3:A_TXPMASETPHASE</th><th>[35, 28, 14]</th></tr>
+<tr><th>GTX3:A_TXPOLARITY</th><th>[34, 29, 45]</th></tr>
+<tr><th>GTX3:A_TXPRBSFORCEERR</th><th>[35, 28, 21]</th></tr>
+<tr><th>GTX3:A_TXRESET</th><th>[33, 29, 4]</th></tr>
+<tr><th>GTX3:A_TXSWING</th><th>[37, 28, 31]</th></tr>
+<tr><th>GTX3:CHAN_BOND_KEEP_ALIGN</th><th>[31, 28, 15]</th></tr>
+<tr><th>GTX3:CHAN_BOND_SEQ_2_USE</th><th>[31, 28, 23]</th></tr>
+<tr><th>GTX3:CLK_CORRECT_USE</th><th>[31, 28, 47]</th></tr>
+<tr><th>GTX3:CLK_COR_INSERT_IDLE_FLAG</th><th>[32, 29, 15]</th></tr>
+<tr><th>GTX3:CLK_COR_KEEP_IDLE</th><th>[31, 29, 55]</th></tr>
+<tr><th>GTX3:CLK_COR_PRECEDENCE</th><th>[31, 29, 47]</th></tr>
+<tr><th>GTX3:CLK_COR_SEQ_2_USE</th><th>[32, 28, 15]</th></tr>
+<tr><th>GTX3:COMMA_DOUBLE</th><th>[35, 28, 61]</th></tr>
+<tr><th>GTX3:DEC_MCOMMA_DETECT</th><th>[32, 29, 37]</th></tr>
+<tr><th>GTX3:DEC_PCOMMA_DETECT</th><th>[32, 28, 37]</th></tr>
+<tr><th>GTX3:DEC_VALID_COMMA_ONLY</th><th>[32, 29, 39]</th></tr>
+<tr><th>GTX3:DFE_DRP_EN</th><th>[35, 29, 39]</th></tr>
+<tr><th>GTX3:GEN_RXUSRCLK</th><th>[32, 29, 63]</th></tr>
+<tr><th>GTX3:GEN_TXUSRCLK</th><th>[36, 29, 15]</th></tr>
+<tr><th>GTX3:GTX_CFG_PWRUP</th><th>[32, 29, 57]</th></tr>
+<tr><th>GTX3:LOOPBACK_DRP_EN</th><th>[35, 28, 16]</th></tr>
+<tr><th>GTX3:MASTER_DRP_EN</th><th>[33, 29, 7]</th></tr>
+<tr><th>GTX3:MCOMMA_DETECT</th><th>[36, 28, 5]</th></tr>
+<tr><th>GTX3:PCI_EXPRESS_MODE</th><th>[34, 29, 15]</th></tr>
+<tr><th>GTX3:PCOMMA_DETECT</th><th>[36, 28, 13]</th></tr>
+<tr><th>GTX3:PDELIDLE_DRP_EN</th><th>[34, 29, 6]</th></tr>
+<tr><th>GTX3:PHASEALIGN_DRP_EN</th><th>[35, 29, 15]</th></tr>
+<tr><th>GTX3:PLL_DRP_EN</th><th>[33, 29, 38]</th></tr>
+<tr><th>GTX3:PMA_CAS_CLK_EN</th><th>[34, 29, 23]</th></tr>
+<tr><th>GTX3:POLARITY_DRP_EN</th><th>[34, 28, 46]</th></tr>
+<tr><th>GTX3:PRBS_DRP_EN</th><th>[35, 29, 23]</th></tr>
+<tr><th>GTX3:RCV_TERM_GND</th><th>[35, 29, 51]</th></tr>
+<tr><th>GTX3:RCV_TERM_VTTRX</th><th>[35, 28, 52]</th></tr>
+<tr><th>GTX3:RESET_DRP_EN</th><th>[33, 28, 7]</th></tr>
+<tr><th>GTX3:RXBUF_OVRD_THRESH</th><th>[31, 28, 38]</th></tr>
+<tr><th>GTX3:RXGEARBOX_USE</th><th>[33, 29, 1]</th></tr>
+<tr><th>GTX3:RXPLL_STARTUP_EN</th><th>[33, 29, 27]</th></tr>
+<tr><th>GTX3:RXPRBSERR_LOOPBACK</th><th>[35, 28, 20]</th></tr>
+<tr><th>GTX3:RX_BUFFER_USE</th><th>[30, 28, 39]</th></tr>
+<tr><th>GTX3:RX_CDR_FORCE_ROTATE</th><th>[32, 29, 23]</th></tr>
+<tr><th>GTX3:RX_DECODE_SEQ_MATCH</th><th>[32, 29, 38]</th></tr>
+<tr><th>GTX3:RX_EN_IDLE_HOLD_CDR</th><th>[35, 29, 28]</th></tr>
+<tr><th>GTX3:RX_EN_IDLE_HOLD_DFE</th><th>[35, 29, 29]</th></tr>
+<tr><th>GTX3:RX_EN_IDLE_RESET_BUF</th><th>[31, 28, 29]</th></tr>
+<tr><th>GTX3:RX_EN_IDLE_RESET_FR</th><th>[35, 28, 29]</th></tr>
+<tr><th>GTX3:RX_EN_IDLE_RESET_PH</th><th>[31, 29, 23]</th></tr>
+<tr><th>GTX3:RX_EN_MODE_RESET_BUF</th><th>[31, 29, 15]</th></tr>
+<tr><th>GTX3:RX_EN_RATE_RESET_BUF</th><th>[31, 29, 7]</th></tr>
+<tr><th>GTX3:RX_EN_REALIGN_RESET_BUF</th><th>[31, 28, 7]</th></tr>
+<tr><th>GTX3:RX_EN_REALIGN_RESET_BUF2</th><th>[39, 28, 31]</th></tr>
+<tr><th>GTX3:RX_LOSS_OF_SYNC_FSM</th><th>[30, 29, 39]</th></tr>
+<tr><th>GTX3:RX_OVERSAMPLE_MODE</th><th>[33, 29, 39]</th></tr>
+<tr><th>GTX3:SHOW_REALIGN_COMMA</th><th>[32, 28, 23]</th></tr>
+<tr><th>GTX3:TERMINATION_OVRD</th><th>[35, 28, 51]</th></tr>
+<tr><th>GTX3:TXDRIVE_DRP_EN</th><th>[37, 28, 39]</th></tr>
+<tr><th>GTX3:TXGEARBOX_USE</th><th>[35, 29, 63]</th></tr>
+<tr><th>GTX3:TXOUTCLKPCS_SEL</th><th>[37, 28, 7]</th></tr>
+<tr><th>GTX3:TXPLL_STARTUP_EN</th><th>[33, 29, 59]</th></tr>
+<tr><th>GTX3:TX_BUFFER_USE</th><th>[36, 29, 13]</th></tr>
+<tr><th>GTX3:TX_EN_RATE_RESET_BUF</th><th>[34, 29, 63]</th></tr>
+<tr><th>GTX3:TX_OVERSAMPLE_MODE</th><th>[34, 29, 7]</th></tr>
+<tr><th>GTX3:TX_PMADATA_OPT</th><th>[34, 29, 47]</th></tr>
+<tr><th>GTX3:USR_CODE_ERR_CLR</th><th>[32, 28, 38]</th></tr>
+<tr><th>HCLK_GTX:DRPMASK_N</th><th>[40, 25, 13]</th></tr>
+<tr><th>HCLK_GTX:DRPMASK_S</th><th>[40, 24, 13]</th></tr>
+<tr><th>IBUFDS_GTX0:CLKCM_CFG</th><th>[11, 28, 39]</th></tr>
+<tr><th>IBUFDS_GTX0:CLKRCV_TRST</th><th>[15, 28, 30]</th></tr>
+<tr><th>IBUFDS_GTX1:CLKCM_CFG</th><th>[11, 29, 39]</th></tr>
+<tr><th>IBUFDS_GTX1:CLKRCV_TRST</th><th>[15, 29, 30]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:INV.DCLK"></div>
+<div id="bits-xc6v-GTX-GTX0:INV.GREFCLKRX"></div>
+<div id="bits-xc6v-GTX-GTX0:INV.GREFCLKTX"></div>
+<div id="bits-xc6v-GTX-GTX0:INV.RXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX0:INV.RXUSRCLK2"></div>
+<div id="bits-xc6v-GTX-GTX0:INV.SCANCLK"></div>
+<div id="bits-xc6v-GTX-GTX0:INV.TSTCLK0"></div>
+<div id="bits-xc6v-GTX-GTX0:INV.TSTCLK1"></div>
+<div id="bits-xc6v-GTX-GTX0:INV.TXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX0:INV.TXUSRCLK2"></div>
+<div id="bits-xc6v-GTX-GTX0:TXDRIVE_LOOPBACK_HIZ"></div>
+<div id="bits-xc6v-GTX-GTX0:TXDRIVE_LOOPBACK_PD"></div>
+<div id="bits-xc6v-GTX-GTX1:INV.DCLK"></div>
+<div id="bits-xc6v-GTX-GTX1:INV.GREFCLKRX"></div>
+<div id="bits-xc6v-GTX-GTX1:INV.GREFCLKTX"></div>
+<div id="bits-xc6v-GTX-GTX1:INV.RXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX1:INV.RXUSRCLK2"></div>
+<div id="bits-xc6v-GTX-GTX1:INV.SCANCLK"></div>
+<div id="bits-xc6v-GTX-GTX1:INV.TSTCLK0"></div>
+<div id="bits-xc6v-GTX-GTX1:INV.TSTCLK1"></div>
+<div id="bits-xc6v-GTX-GTX1:INV.TXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX1:INV.TXUSRCLK2"></div>
+<div id="bits-xc6v-GTX-GTX1:TXDRIVE_LOOPBACK_HIZ"></div>
+<div id="bits-xc6v-GTX-GTX1:TXDRIVE_LOOPBACK_PD"></div>
+<div id="bits-xc6v-GTX-GTX2:INV.DCLK"></div>
+<div id="bits-xc6v-GTX-GTX2:INV.GREFCLKRX"></div>
+<div id="bits-xc6v-GTX-GTX2:INV.GREFCLKTX"></div>
+<div id="bits-xc6v-GTX-GTX2:INV.RXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX2:INV.RXUSRCLK2"></div>
+<div id="bits-xc6v-GTX-GTX2:INV.SCANCLK"></div>
+<div id="bits-xc6v-GTX-GTX2:INV.TSTCLK0"></div>
+<div id="bits-xc6v-GTX-GTX2:INV.TSTCLK1"></div>
+<div id="bits-xc6v-GTX-GTX2:INV.TXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX2:INV.TXUSRCLK2"></div>
+<div id="bits-xc6v-GTX-GTX2:TXDRIVE_LOOPBACK_HIZ"></div>
+<div id="bits-xc6v-GTX-GTX2:TXDRIVE_LOOPBACK_PD"></div>
+<div id="bits-xc6v-GTX-GTX3:INV.DCLK"></div>
+<div id="bits-xc6v-GTX-GTX3:INV.GREFCLKRX"></div>
+<div id="bits-xc6v-GTX-GTX3:INV.GREFCLKTX"></div>
+<div id="bits-xc6v-GTX-GTX3:INV.RXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX3:INV.RXUSRCLK2"></div>
+<div id="bits-xc6v-GTX-GTX3:INV.SCANCLK"></div>
+<div id="bits-xc6v-GTX-GTX3:INV.TSTCLK0"></div>
+<div id="bits-xc6v-GTX-GTX3:INV.TSTCLK1"></div>
+<div id="bits-xc6v-GTX-GTX3:INV.TXUSRCLK"></div>
+<div id="bits-xc6v-GTX-GTX3:INV.TXUSRCLK2"></div>
+<div id="bits-xc6v-GTX-GTX3:TXDRIVE_LOOPBACK_HIZ"></div>
+<div id="bits-xc6v-GTX-GTX3:TXDRIVE_LOOPBACK_PD"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:INV.DCLK</th><th>[7, 29, 7]</th></tr>
+<tr><th>GTX0:INV.GREFCLKRX</th><th>[8, 29, 31]</th></tr>
+<tr><th>GTX0:INV.GREFCLKTX</th><th>[8, 28, 31]</th></tr>
+<tr><th>GTX0:INV.RXUSRCLK</th><th>[0, 28, 47]</th></tr>
+<tr><th>GTX0:INV.RXUSRCLK2</th><th>[0, 29, 47]</th></tr>
+<tr><th>GTX0:INV.SCANCLK</th><th>[8, 29, 30]</th></tr>
+<tr><th>GTX0:INV.TSTCLK0</th><th>[8, 28, 29]</th></tr>
+<tr><th>GTX0:INV.TSTCLK1</th><th>[8, 29, 29]</th></tr>
+<tr><th>GTX0:INV.TXUSRCLK</th><th>[6, 28, 7]</th></tr>
+<tr><th>GTX0:INV.TXUSRCLK2</th><th>[6, 29, 7]</th></tr>
+<tr><th>GTX0:TXDRIVE_LOOPBACK_HIZ</th><th>[7, 28, 23]</th></tr>
+<tr><th>GTX0:TXDRIVE_LOOPBACK_PD</th><th>[7, 29, 23]</th></tr>
+<tr><th>GTX1:INV.DCLK</th><th>[17, 29, 7]</th></tr>
+<tr><th>GTX1:INV.GREFCLKRX</th><th>[18, 29, 31]</th></tr>
+<tr><th>GTX1:INV.GREFCLKTX</th><th>[18, 28, 31]</th></tr>
+<tr><th>GTX1:INV.RXUSRCLK</th><th>[10, 28, 47]</th></tr>
+<tr><th>GTX1:INV.RXUSRCLK2</th><th>[10, 29, 47]</th></tr>
+<tr><th>GTX1:INV.SCANCLK</th><th>[18, 29, 30]</th></tr>
+<tr><th>GTX1:INV.TSTCLK0</th><th>[18, 28, 29]</th></tr>
+<tr><th>GTX1:INV.TSTCLK1</th><th>[18, 29, 29]</th></tr>
+<tr><th>GTX1:INV.TXUSRCLK</th><th>[16, 28, 7]</th></tr>
+<tr><th>GTX1:INV.TXUSRCLK2</th><th>[16, 29, 7]</th></tr>
+<tr><th>GTX1:TXDRIVE_LOOPBACK_HIZ</th><th>[17, 28, 23]</th></tr>
+<tr><th>GTX1:TXDRIVE_LOOPBACK_PD</th><th>[17, 29, 23]</th></tr>
+<tr><th>GTX2:INV.DCLK</th><th>[27, 29, 7]</th></tr>
+<tr><th>GTX2:INV.GREFCLKRX</th><th>[28, 29, 31]</th></tr>
+<tr><th>GTX2:INV.GREFCLKTX</th><th>[28, 28, 31]</th></tr>
+<tr><th>GTX2:INV.RXUSRCLK</th><th>[20, 28, 47]</th></tr>
+<tr><th>GTX2:INV.RXUSRCLK2</th><th>[20, 29, 47]</th></tr>
+<tr><th>GTX2:INV.SCANCLK</th><th>[28, 29, 30]</th></tr>
+<tr><th>GTX2:INV.TSTCLK0</th><th>[28, 28, 29]</th></tr>
+<tr><th>GTX2:INV.TSTCLK1</th><th>[28, 29, 29]</th></tr>
+<tr><th>GTX2:INV.TXUSRCLK</th><th>[26, 28, 7]</th></tr>
+<tr><th>GTX2:INV.TXUSRCLK2</th><th>[26, 29, 7]</th></tr>
+<tr><th>GTX2:TXDRIVE_LOOPBACK_HIZ</th><th>[27, 28, 23]</th></tr>
+<tr><th>GTX2:TXDRIVE_LOOPBACK_PD</th><th>[27, 29, 23]</th></tr>
+<tr><th>GTX3:INV.DCLK</th><th>[37, 29, 7]</th></tr>
+<tr><th>GTX3:INV.GREFCLKRX</th><th>[38, 29, 31]</th></tr>
+<tr><th>GTX3:INV.GREFCLKTX</th><th>[38, 28, 31]</th></tr>
+<tr><th>GTX3:INV.RXUSRCLK</th><th>[30, 28, 47]</th></tr>
+<tr><th>GTX3:INV.RXUSRCLK2</th><th>[30, 29, 47]</th></tr>
+<tr><th>GTX3:INV.SCANCLK</th><th>[38, 29, 30]</th></tr>
+<tr><th>GTX3:INV.TSTCLK0</th><th>[38, 28, 29]</th></tr>
+<tr><th>GTX3:INV.TSTCLK1</th><th>[38, 29, 29]</th></tr>
+<tr><th>GTX3:INV.TXUSRCLK</th><th>[36, 28, 7]</th></tr>
+<tr><th>GTX3:INV.TXUSRCLK2</th><th>[36, 29, 7]</th></tr>
+<tr><th>GTX3:TXDRIVE_LOOPBACK_HIZ</th><th>[37, 28, 23]</th></tr>
+<tr><th>GTX3:TXDRIVE_LOOPBACK_PD</th><th>[37, 29, 23]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:RX_LOS_THRESHOLD"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_LOS_THRESHOLD"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_LOS_THRESHOLD"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_LOS_THRESHOLD"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:RX_LOS_THRESHOLD</th><th>[0, 28, 54]</th><th>[0, 29, 53]</th><th>[0, 28, 53]</th></tr>
+<tr><th>GTX1:RX_LOS_THRESHOLD</th><th>[10, 28, 54]</th><th>[10, 29, 53]</th><th>[10, 28, 53]</th></tr>
+<tr><th>GTX2:RX_LOS_THRESHOLD</th><th>[20, 28, 54]</th><th>[20, 29, 53]</th><th>[20, 28, 53]</th></tr>
+<tr><th>GTX3:RX_LOS_THRESHOLD</th><th>[30, 28, 54]</th><th>[30, 29, 53]</th><th>[30, 28, 53]</th></tr>
+<tr><td>4</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>8</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>16</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>32</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>64</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>128</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>256</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>512</td><td>1</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_LEN"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_ADJ_LEN"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_DET_LEN"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_LEN"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_ADJ_LEN"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_DET_LEN"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_LEN"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_ADJ_LEN"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_DET_LEN"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_LEN"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_ADJ_LEN"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_DET_LEN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:CHAN_BOND_SEQ_LEN</th><th>[0, 29, 61]</th><th>[0, 28, 61]</th></tr>
+<tr><th>GTX0:CLK_COR_ADJ_LEN</th><th>[2, 29, 21]</th><th>[2, 28, 21]</th></tr>
+<tr><th>GTX0:CLK_COR_DET_LEN</th><th>[2, 29, 29]</th><th>[2, 28, 29]</th></tr>
+<tr><th>GTX1:CHAN_BOND_SEQ_LEN</th><th>[10, 29, 61]</th><th>[10, 28, 61]</th></tr>
+<tr><th>GTX1:CLK_COR_ADJ_LEN</th><th>[12, 29, 21]</th><th>[12, 28, 21]</th></tr>
+<tr><th>GTX1:CLK_COR_DET_LEN</th><th>[12, 29, 29]</th><th>[12, 28, 29]</th></tr>
+<tr><th>GTX2:CHAN_BOND_SEQ_LEN</th><th>[20, 29, 61]</th><th>[20, 28, 61]</th></tr>
+<tr><th>GTX2:CLK_COR_ADJ_LEN</th><th>[22, 29, 21]</th><th>[22, 28, 21]</th></tr>
+<tr><th>GTX2:CLK_COR_DET_LEN</th><th>[22, 29, 29]</th><th>[22, 28, 29]</th></tr>
+<tr><th>GTX3:CHAN_BOND_SEQ_LEN</th><th>[30, 29, 61]</th><th>[30, 28, 61]</th></tr>
+<tr><th>GTX3:CLK_COR_ADJ_LEN</th><th>[32, 29, 21]</th><th>[32, 28, 21]</th></tr>
+<tr><th>GTX3:CLK_COR_DET_LEN</th><th>[32, 29, 29]</th><th>[32, 28, 29]</th></tr>
+<tr><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>2</td><td>0</td><td>1</td></tr>
+<tr><td>3</td><td>1</td><td>0</td></tr>
+<tr><td>4</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:PMA_RXSYNC_CFG"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_0"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_1"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_2"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_3"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_MARGIN_FULL_4"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_0"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_1"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_2"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_3"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_MARGIN_LOW_4"></div>
+<div id="bits-xc6v-GTX-GTX1:PMA_RXSYNC_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_0"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_1"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_2"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_3"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_MARGIN_FULL_4"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_0"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_1"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_2"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_3"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_MARGIN_LOW_4"></div>
+<div id="bits-xc6v-GTX-GTX2:PMA_RXSYNC_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_0"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_1"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_2"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_3"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_MARGIN_FULL_4"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_0"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_1"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_2"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_3"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_MARGIN_LOW_4"></div>
+<div id="bits-xc6v-GTX-GTX3:PMA_RXSYNC_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_0"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_1"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_2"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_3"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_MARGIN_FULL_4"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_0"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_1"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_2"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_3"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_MARGIN_LOW_4"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:PMA_RXSYNC_CFG</th><th>[0, 29, 15]</th><th>[0, 28, 15]</th><th>[0, 29, 14]</th><th>[0, 28, 14]</th><th>[0, 29, 13]</th><th>[0, 28, 13]</th><th>[0, 29, 12]</th></tr>
+<tr><th>GTX0:TX_MARGIN_FULL_0</th><th>[7, 29, 6]</th><th>[7, 28, 6]</th><th>[7, 29, 5]</th><th>[7, 28, 5]</th><th>[7, 29, 4]</th><th>[7, 28, 4]</th><th>[7, 29, 3]</th></tr>
+<tr><th>GTX0:TX_MARGIN_FULL_1</th><th>[7, 29, 14]</th><th>[7, 28, 14]</th><th>[7, 29, 13]</th><th>[7, 28, 13]</th><th>[7, 29, 12]</th><th>[7, 28, 12]</th><th>[7, 29, 11]</th></tr>
+<tr><th>GTX0:TX_MARGIN_FULL_2</th><th>[7, 29, 22]</th><th>[7, 28, 22]</th><th>[7, 29, 21]</th><th>[7, 28, 21]</th><th>[7, 29, 20]</th><th>[7, 28, 20]</th><th>[7, 29, 19]</th></tr>
+<tr><th>GTX0:TX_MARGIN_FULL_3</th><th>[7, 29, 30]</th><th>[7, 28, 30]</th><th>[7, 29, 29]</th><th>[7, 28, 29]</th><th>[7, 29, 28]</th><th>[7, 28, 28]</th><th>[7, 29, 27]</th></tr>
+<tr><th>GTX0:TX_MARGIN_FULL_4</th><th>[7, 29, 38]</th><th>[7, 28, 38]</th><th>[7, 29, 37]</th><th>[7, 28, 37]</th><th>[7, 29, 36]</th><th>[7, 28, 36]</th><th>[7, 29, 35]</th></tr>
+<tr><th>GTX0:TX_MARGIN_LOW_0</th><th>[7, 28, 3]</th><th>[7, 29, 2]</th><th>[7, 28, 2]</th><th>[7, 29, 1]</th><th>[7, 28, 1]</th><th>[7, 29, 0]</th><th>[7, 28, 0]</th></tr>
+<tr><th>GTX0:TX_MARGIN_LOW_1</th><th>[7, 28, 11]</th><th>[7, 29, 10]</th><th>[7, 28, 10]</th><th>[7, 29, 9]</th><th>[7, 28, 9]</th><th>[7, 29, 8]</th><th>[7, 28, 8]</th></tr>
+<tr><th>GTX0:TX_MARGIN_LOW_2</th><th>[7, 28, 19]</th><th>[7, 29, 18]</th><th>[7, 28, 18]</th><th>[7, 29, 17]</th><th>[7, 28, 17]</th><th>[7, 29, 16]</th><th>[7, 28, 16]</th></tr>
+<tr><th>GTX0:TX_MARGIN_LOW_3</th><th>[7, 28, 27]</th><th>[7, 29, 26]</th><th>[7, 28, 26]</th><th>[7, 29, 25]</th><th>[7, 28, 25]</th><th>[7, 29, 24]</th><th>[7, 28, 24]</th></tr>
+<tr><th>GTX0:TX_MARGIN_LOW_4</th><th>[7, 28, 35]</th><th>[7, 29, 34]</th><th>[7, 28, 34]</th><th>[7, 29, 33]</th><th>[7, 28, 33]</th><th>[7, 29, 32]</th><th>[7, 28, 32]</th></tr>
+<tr><th>GTX1:PMA_RXSYNC_CFG</th><th>[10, 29, 15]</th><th>[10, 28, 15]</th><th>[10, 29, 14]</th><th>[10, 28, 14]</th><th>[10, 29, 13]</th><th>[10, 28, 13]</th><th>[10, 29, 12]</th></tr>
+<tr><th>GTX1:TX_MARGIN_FULL_0</th><th>[17, 29, 6]</th><th>[17, 28, 6]</th><th>[17, 29, 5]</th><th>[17, 28, 5]</th><th>[17, 29, 4]</th><th>[17, 28, 4]</th><th>[17, 29, 3]</th></tr>
+<tr><th>GTX1:TX_MARGIN_FULL_1</th><th>[17, 29, 14]</th><th>[17, 28, 14]</th><th>[17, 29, 13]</th><th>[17, 28, 13]</th><th>[17, 29, 12]</th><th>[17, 28, 12]</th><th>[17, 29, 11]</th></tr>
+<tr><th>GTX1:TX_MARGIN_FULL_2</th><th>[17, 29, 22]</th><th>[17, 28, 22]</th><th>[17, 29, 21]</th><th>[17, 28, 21]</th><th>[17, 29, 20]</th><th>[17, 28, 20]</th><th>[17, 29, 19]</th></tr>
+<tr><th>GTX1:TX_MARGIN_FULL_3</th><th>[17, 29, 30]</th><th>[17, 28, 30]</th><th>[17, 29, 29]</th><th>[17, 28, 29]</th><th>[17, 29, 28]</th><th>[17, 28, 28]</th><th>[17, 29, 27]</th></tr>
+<tr><th>GTX1:TX_MARGIN_FULL_4</th><th>[17, 29, 38]</th><th>[17, 28, 38]</th><th>[17, 29, 37]</th><th>[17, 28, 37]</th><th>[17, 29, 36]</th><th>[17, 28, 36]</th><th>[17, 29, 35]</th></tr>
+<tr><th>GTX1:TX_MARGIN_LOW_0</th><th>[17, 28, 3]</th><th>[17, 29, 2]</th><th>[17, 28, 2]</th><th>[17, 29, 1]</th><th>[17, 28, 1]</th><th>[17, 29, 0]</th><th>[17, 28, 0]</th></tr>
+<tr><th>GTX1:TX_MARGIN_LOW_1</th><th>[17, 28, 11]</th><th>[17, 29, 10]</th><th>[17, 28, 10]</th><th>[17, 29, 9]</th><th>[17, 28, 9]</th><th>[17, 29, 8]</th><th>[17, 28, 8]</th></tr>
+<tr><th>GTX1:TX_MARGIN_LOW_2</th><th>[17, 28, 19]</th><th>[17, 29, 18]</th><th>[17, 28, 18]</th><th>[17, 29, 17]</th><th>[17, 28, 17]</th><th>[17, 29, 16]</th><th>[17, 28, 16]</th></tr>
+<tr><th>GTX1:TX_MARGIN_LOW_3</th><th>[17, 28, 27]</th><th>[17, 29, 26]</th><th>[17, 28, 26]</th><th>[17, 29, 25]</th><th>[17, 28, 25]</th><th>[17, 29, 24]</th><th>[17, 28, 24]</th></tr>
+<tr><th>GTX1:TX_MARGIN_LOW_4</th><th>[17, 28, 35]</th><th>[17, 29, 34]</th><th>[17, 28, 34]</th><th>[17, 29, 33]</th><th>[17, 28, 33]</th><th>[17, 29, 32]</th><th>[17, 28, 32]</th></tr>
+<tr><th>GTX2:PMA_RXSYNC_CFG</th><th>[20, 29, 15]</th><th>[20, 28, 15]</th><th>[20, 29, 14]</th><th>[20, 28, 14]</th><th>[20, 29, 13]</th><th>[20, 28, 13]</th><th>[20, 29, 12]</th></tr>
+<tr><th>GTX2:TX_MARGIN_FULL_0</th><th>[27, 29, 6]</th><th>[27, 28, 6]</th><th>[27, 29, 5]</th><th>[27, 28, 5]</th><th>[27, 29, 4]</th><th>[27, 28, 4]</th><th>[27, 29, 3]</th></tr>
+<tr><th>GTX2:TX_MARGIN_FULL_1</th><th>[27, 29, 14]</th><th>[27, 28, 14]</th><th>[27, 29, 13]</th><th>[27, 28, 13]</th><th>[27, 29, 12]</th><th>[27, 28, 12]</th><th>[27, 29, 11]</th></tr>
+<tr><th>GTX2:TX_MARGIN_FULL_2</th><th>[27, 29, 22]</th><th>[27, 28, 22]</th><th>[27, 29, 21]</th><th>[27, 28, 21]</th><th>[27, 29, 20]</th><th>[27, 28, 20]</th><th>[27, 29, 19]</th></tr>
+<tr><th>GTX2:TX_MARGIN_FULL_3</th><th>[27, 29, 30]</th><th>[27, 28, 30]</th><th>[27, 29, 29]</th><th>[27, 28, 29]</th><th>[27, 29, 28]</th><th>[27, 28, 28]</th><th>[27, 29, 27]</th></tr>
+<tr><th>GTX2:TX_MARGIN_FULL_4</th><th>[27, 29, 38]</th><th>[27, 28, 38]</th><th>[27, 29, 37]</th><th>[27, 28, 37]</th><th>[27, 29, 36]</th><th>[27, 28, 36]</th><th>[27, 29, 35]</th></tr>
+<tr><th>GTX2:TX_MARGIN_LOW_0</th><th>[27, 28, 3]</th><th>[27, 29, 2]</th><th>[27, 28, 2]</th><th>[27, 29, 1]</th><th>[27, 28, 1]</th><th>[27, 29, 0]</th><th>[27, 28, 0]</th></tr>
+<tr><th>GTX2:TX_MARGIN_LOW_1</th><th>[27, 28, 11]</th><th>[27, 29, 10]</th><th>[27, 28, 10]</th><th>[27, 29, 9]</th><th>[27, 28, 9]</th><th>[27, 29, 8]</th><th>[27, 28, 8]</th></tr>
+<tr><th>GTX2:TX_MARGIN_LOW_2</th><th>[27, 28, 19]</th><th>[27, 29, 18]</th><th>[27, 28, 18]</th><th>[27, 29, 17]</th><th>[27, 28, 17]</th><th>[27, 29, 16]</th><th>[27, 28, 16]</th></tr>
+<tr><th>GTX2:TX_MARGIN_LOW_3</th><th>[27, 28, 27]</th><th>[27, 29, 26]</th><th>[27, 28, 26]</th><th>[27, 29, 25]</th><th>[27, 28, 25]</th><th>[27, 29, 24]</th><th>[27, 28, 24]</th></tr>
+<tr><th>GTX2:TX_MARGIN_LOW_4</th><th>[27, 28, 35]</th><th>[27, 29, 34]</th><th>[27, 28, 34]</th><th>[27, 29, 33]</th><th>[27, 28, 33]</th><th>[27, 29, 32]</th><th>[27, 28, 32]</th></tr>
+<tr><th>GTX3:PMA_RXSYNC_CFG</th><th>[30, 29, 15]</th><th>[30, 28, 15]</th><th>[30, 29, 14]</th><th>[30, 28, 14]</th><th>[30, 29, 13]</th><th>[30, 28, 13]</th><th>[30, 29, 12]</th></tr>
+<tr><th>GTX3:TX_MARGIN_FULL_0</th><th>[37, 29, 6]</th><th>[37, 28, 6]</th><th>[37, 29, 5]</th><th>[37, 28, 5]</th><th>[37, 29, 4]</th><th>[37, 28, 4]</th><th>[37, 29, 3]</th></tr>
+<tr><th>GTX3:TX_MARGIN_FULL_1</th><th>[37, 29, 14]</th><th>[37, 28, 14]</th><th>[37, 29, 13]</th><th>[37, 28, 13]</th><th>[37, 29, 12]</th><th>[37, 28, 12]</th><th>[37, 29, 11]</th></tr>
+<tr><th>GTX3:TX_MARGIN_FULL_2</th><th>[37, 29, 22]</th><th>[37, 28, 22]</th><th>[37, 29, 21]</th><th>[37, 28, 21]</th><th>[37, 29, 20]</th><th>[37, 28, 20]</th><th>[37, 29, 19]</th></tr>
+<tr><th>GTX3:TX_MARGIN_FULL_3</th><th>[37, 29, 30]</th><th>[37, 28, 30]</th><th>[37, 29, 29]</th><th>[37, 28, 29]</th><th>[37, 29, 28]</th><th>[37, 28, 28]</th><th>[37, 29, 27]</th></tr>
+<tr><th>GTX3:TX_MARGIN_FULL_4</th><th>[37, 29, 38]</th><th>[37, 28, 38]</th><th>[37, 29, 37]</th><th>[37, 28, 37]</th><th>[37, 29, 36]</th><th>[37, 28, 36]</th><th>[37, 29, 35]</th></tr>
+<tr><th>GTX3:TX_MARGIN_LOW_0</th><th>[37, 28, 3]</th><th>[37, 29, 2]</th><th>[37, 28, 2]</th><th>[37, 29, 1]</th><th>[37, 28, 1]</th><th>[37, 29, 0]</th><th>[37, 28, 0]</th></tr>
+<tr><th>GTX3:TX_MARGIN_LOW_1</th><th>[37, 28, 11]</th><th>[37, 29, 10]</th><th>[37, 28, 10]</th><th>[37, 29, 9]</th><th>[37, 28, 9]</th><th>[37, 29, 8]</th><th>[37, 28, 8]</th></tr>
+<tr><th>GTX3:TX_MARGIN_LOW_2</th><th>[37, 28, 19]</th><th>[37, 29, 18]</th><th>[37, 28, 18]</th><th>[37, 29, 17]</th><th>[37, 28, 17]</th><th>[37, 29, 16]</th><th>[37, 28, 16]</th></tr>
+<tr><th>GTX3:TX_MARGIN_LOW_3</th><th>[37, 28, 27]</th><th>[37, 29, 26]</th><th>[37, 28, 26]</th><th>[37, 29, 25]</th><th>[37, 28, 25]</th><th>[37, 29, 24]</th><th>[37, 28, 24]</th></tr>
+<tr><th>GTX3:TX_MARGIN_LOW_4</th><th>[37, 28, 35]</th><th>[37, 29, 34]</th><th>[37, 28, 34]</th><th>[37, 29, 33]</th><th>[37, 28, 33]</th><th>[37, 29, 32]</th><th>[37, 28, 32]</th></tr>
+<tr><td>Non-inverted</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:RX_LOS_INVALID_INCR"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_LOS_INVALID_INCR"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_LOS_INVALID_INCR"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_LOS_INVALID_INCR"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:RX_LOS_INVALID_INCR</th><th>[0, 29, 55]</th><th>[0, 28, 55]</th><th>[0, 29, 54]</th></tr>
+<tr><th>GTX1:RX_LOS_INVALID_INCR</th><th>[10, 29, 55]</th><th>[10, 28, 55]</th><th>[10, 29, 54]</th></tr>
+<tr><th>GTX2:RX_LOS_INVALID_INCR</th><th>[20, 29, 55]</th><th>[20, 28, 55]</th><th>[20, 29, 54]</th></tr>
+<tr><th>GTX3:RX_LOS_INVALID_INCR</th><th>[30, 29, 55]</th><th>[30, 28, 55]</th><th>[30, 29, 54]</th></tr>
+<tr><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>2</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>4</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>8</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>16</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>32</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>64</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>128</td><td>1</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:A_DFETAP1"></div>
+<div id="bits-xc6v-GTX-GTX0:A_DFETAP2"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXPOSTEMPHASIS"></div>
+<div id="bits-xc6v-GTX-GTX0:CDR_PH_ADJ_TIME"></div>
+<div id="bits-xc6v-GTX-GTX0:CHAN_BOND_SEQ_2_CFG"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_REPEAT_WAIT"></div>
+<div id="bits-xc6v-GTX-GTX0:DFE_CAL_TIME"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_DLYALIGN_EDGESET"></div>
+<div id="bits-xc6v-GTX-GTX0:TERMINATION_CTRL"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_DEEMPH_0"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_DEEMPH_1"></div>
+<div id="bits-xc6v-GTX-GTX1:A_DFETAP1"></div>
+<div id="bits-xc6v-GTX-GTX1:A_DFETAP2"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXPOSTEMPHASIS"></div>
+<div id="bits-xc6v-GTX-GTX1:CDR_PH_ADJ_TIME"></div>
+<div id="bits-xc6v-GTX-GTX1:CHAN_BOND_SEQ_2_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_REPEAT_WAIT"></div>
+<div id="bits-xc6v-GTX-GTX1:DFE_CAL_TIME"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_DLYALIGN_EDGESET"></div>
+<div id="bits-xc6v-GTX-GTX1:TERMINATION_CTRL"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_DEEMPH_0"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_DEEMPH_1"></div>
+<div id="bits-xc6v-GTX-GTX2:A_DFETAP1"></div>
+<div id="bits-xc6v-GTX-GTX2:A_DFETAP2"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXPOSTEMPHASIS"></div>
+<div id="bits-xc6v-GTX-GTX2:CDR_PH_ADJ_TIME"></div>
+<div id="bits-xc6v-GTX-GTX2:CHAN_BOND_SEQ_2_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_REPEAT_WAIT"></div>
+<div id="bits-xc6v-GTX-GTX2:DFE_CAL_TIME"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_DLYALIGN_EDGESET"></div>
+<div id="bits-xc6v-GTX-GTX2:TERMINATION_CTRL"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_DEEMPH_0"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_DEEMPH_1"></div>
+<div id="bits-xc6v-GTX-GTX3:A_DFETAP1"></div>
+<div id="bits-xc6v-GTX-GTX3:A_DFETAP2"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXPOSTEMPHASIS"></div>
+<div id="bits-xc6v-GTX-GTX3:CDR_PH_ADJ_TIME"></div>
+<div id="bits-xc6v-GTX-GTX3:CHAN_BOND_SEQ_2_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_REPEAT_WAIT"></div>
+<div id="bits-xc6v-GTX-GTX3:DFE_CAL_TIME"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_DLYALIGN_EDGESET"></div>
+<div id="bits-xc6v-GTX-GTX3:TERMINATION_CTRL"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_DEEMPH_0"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_DEEMPH_1"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:A_DFETAP1</th><th>[5, 28, 26]</th><th>[5, 29, 25]</th><th>[5, 28, 25]</th><th>[5, 29, 24]</th><th>[5, 28, 24]</th></tr>
+<tr><th>GTX0:A_DFETAP2</th><th>[5, 28, 34]</th><th>[5, 29, 33]</th><th>[5, 28, 33]</th><th>[5, 29, 32]</th><th>[5, 28, 32]</th></tr>
+<tr><th>GTX0:A_TXPOSTEMPHASIS</th><th>[7, 29, 47]</th><th>[7, 28, 47]</th><th>[7, 29, 46]</th><th>[7, 28, 46]</th><th>[7, 29, 45]</th></tr>
+<tr><th>GTX0:CDR_PH_ADJ_TIME</th><th>[2, 29, 55]</th><th>[2, 28, 55]</th><th>[2, 29, 54]</th><th>[2, 28, 54]</th><th>[2, 29, 53]</th></tr>
+<tr><th>GTX0:CHAN_BOND_SEQ_2_CFG</th><th>[2, 29, 61]</th><th>[1, 29, 22]</th><th>[1, 28, 22]</th><th>[1, 29, 21]</th><th>[1, 28, 21]</th></tr>
+<tr><th>GTX0:CLK_COR_REPEAT_WAIT</th><th>[1, 28, 55]</th><th>[1, 29, 54]</th><th>[1, 28, 54]</th><th>[1, 29, 53]</th><th>[1, 28, 53]</th></tr>
+<tr><th>GTX0:DFE_CAL_TIME</th><th>[5, 29, 55]</th><th>[5, 28, 55]</th><th>[5, 29, 54]</th><th>[5, 28, 54]</th><th>[5, 29, 53]</th></tr>
+<tr><th>GTX0:RX_DLYALIGN_EDGESET</th><th>[9, 28, 29]</th><th>[9, 29, 28]</th><th>[9, 28, 28]</th><th>[9, 29, 27]</th><th>[9, 28, 27]</th></tr>
+<tr><th>GTX0:TERMINATION_CTRL</th><th>[5, 28, 50]</th><th>[5, 29, 49]</th><th>[5, 28, 49]</th><th>[5, 29, 48]</th><th>[5, 28, 48]</th></tr>
+<tr><th>GTX0:TX_DEEMPH_0</th><th>[7, 28, 50]</th><th>[7, 29, 49]</th><th>[7, 28, 49]</th><th>[7, 29, 48]</th><th>[7, 28, 48]</th></tr>
+<tr><th>GTX0:TX_DEEMPH_1</th><th>[7, 29, 52]</th><th>[7, 28, 52]</th><th>[7, 29, 51]</th><th>[7, 28, 51]</th><th>[7, 29, 50]</th></tr>
+<tr><th>GTX1:A_DFETAP1</th><th>[15, 28, 26]</th><th>[15, 29, 25]</th><th>[15, 28, 25]</th><th>[15, 29, 24]</th><th>[15, 28, 24]</th></tr>
+<tr><th>GTX1:A_DFETAP2</th><th>[15, 28, 34]</th><th>[15, 29, 33]</th><th>[15, 28, 33]</th><th>[15, 29, 32]</th><th>[15, 28, 32]</th></tr>
+<tr><th>GTX1:A_TXPOSTEMPHASIS</th><th>[17, 29, 47]</th><th>[17, 28, 47]</th><th>[17, 29, 46]</th><th>[17, 28, 46]</th><th>[17, 29, 45]</th></tr>
+<tr><th>GTX1:CDR_PH_ADJ_TIME</th><th>[12, 29, 55]</th><th>[12, 28, 55]</th><th>[12, 29, 54]</th><th>[12, 28, 54]</th><th>[12, 29, 53]</th></tr>
+<tr><th>GTX1:CHAN_BOND_SEQ_2_CFG</th><th>[12, 29, 61]</th><th>[11, 29, 22]</th><th>[11, 28, 22]</th><th>[11, 29, 21]</th><th>[11, 28, 21]</th></tr>
+<tr><th>GTX1:CLK_COR_REPEAT_WAIT</th><th>[11, 28, 55]</th><th>[11, 29, 54]</th><th>[11, 28, 54]</th><th>[11, 29, 53]</th><th>[11, 28, 53]</th></tr>
+<tr><th>GTX1:DFE_CAL_TIME</th><th>[15, 29, 55]</th><th>[15, 28, 55]</th><th>[15, 29, 54]</th><th>[15, 28, 54]</th><th>[15, 29, 53]</th></tr>
+<tr><th>GTX1:RX_DLYALIGN_EDGESET</th><th>[19, 28, 29]</th><th>[19, 29, 28]</th><th>[19, 28, 28]</th><th>[19, 29, 27]</th><th>[19, 28, 27]</th></tr>
+<tr><th>GTX1:TERMINATION_CTRL</th><th>[15, 28, 50]</th><th>[15, 29, 49]</th><th>[15, 28, 49]</th><th>[15, 29, 48]</th><th>[15, 28, 48]</th></tr>
+<tr><th>GTX1:TX_DEEMPH_0</th><th>[17, 28, 50]</th><th>[17, 29, 49]</th><th>[17, 28, 49]</th><th>[17, 29, 48]</th><th>[17, 28, 48]</th></tr>
+<tr><th>GTX1:TX_DEEMPH_1</th><th>[17, 29, 52]</th><th>[17, 28, 52]</th><th>[17, 29, 51]</th><th>[17, 28, 51]</th><th>[17, 29, 50]</th></tr>
+<tr><th>GTX2:A_DFETAP1</th><th>[25, 28, 26]</th><th>[25, 29, 25]</th><th>[25, 28, 25]</th><th>[25, 29, 24]</th><th>[25, 28, 24]</th></tr>
+<tr><th>GTX2:A_DFETAP2</th><th>[25, 28, 34]</th><th>[25, 29, 33]</th><th>[25, 28, 33]</th><th>[25, 29, 32]</th><th>[25, 28, 32]</th></tr>
+<tr><th>GTX2:A_TXPOSTEMPHASIS</th><th>[27, 29, 47]</th><th>[27, 28, 47]</th><th>[27, 29, 46]</th><th>[27, 28, 46]</th><th>[27, 29, 45]</th></tr>
+<tr><th>GTX2:CDR_PH_ADJ_TIME</th><th>[22, 29, 55]</th><th>[22, 28, 55]</th><th>[22, 29, 54]</th><th>[22, 28, 54]</th><th>[22, 29, 53]</th></tr>
+<tr><th>GTX2:CHAN_BOND_SEQ_2_CFG</th><th>[22, 29, 61]</th><th>[21, 29, 22]</th><th>[21, 28, 22]</th><th>[21, 29, 21]</th><th>[21, 28, 21]</th></tr>
+<tr><th>GTX2:CLK_COR_REPEAT_WAIT</th><th>[21, 28, 55]</th><th>[21, 29, 54]</th><th>[21, 28, 54]</th><th>[21, 29, 53]</th><th>[21, 28, 53]</th></tr>
+<tr><th>GTX2:DFE_CAL_TIME</th><th>[25, 29, 55]</th><th>[25, 28, 55]</th><th>[25, 29, 54]</th><th>[25, 28, 54]</th><th>[25, 29, 53]</th></tr>
+<tr><th>GTX2:RX_DLYALIGN_EDGESET</th><th>[29, 28, 29]</th><th>[29, 29, 28]</th><th>[29, 28, 28]</th><th>[29, 29, 27]</th><th>[29, 28, 27]</th></tr>
+<tr><th>GTX2:TERMINATION_CTRL</th><th>[25, 28, 50]</th><th>[25, 29, 49]</th><th>[25, 28, 49]</th><th>[25, 29, 48]</th><th>[25, 28, 48]</th></tr>
+<tr><th>GTX2:TX_DEEMPH_0</th><th>[27, 28, 50]</th><th>[27, 29, 49]</th><th>[27, 28, 49]</th><th>[27, 29, 48]</th><th>[27, 28, 48]</th></tr>
+<tr><th>GTX2:TX_DEEMPH_1</th><th>[27, 29, 52]</th><th>[27, 28, 52]</th><th>[27, 29, 51]</th><th>[27, 28, 51]</th><th>[27, 29, 50]</th></tr>
+<tr><th>GTX3:A_DFETAP1</th><th>[35, 28, 26]</th><th>[35, 29, 25]</th><th>[35, 28, 25]</th><th>[35, 29, 24]</th><th>[35, 28, 24]</th></tr>
+<tr><th>GTX3:A_DFETAP2</th><th>[35, 28, 34]</th><th>[35, 29, 33]</th><th>[35, 28, 33]</th><th>[35, 29, 32]</th><th>[35, 28, 32]</th></tr>
+<tr><th>GTX3:A_TXPOSTEMPHASIS</th><th>[37, 29, 47]</th><th>[37, 28, 47]</th><th>[37, 29, 46]</th><th>[37, 28, 46]</th><th>[37, 29, 45]</th></tr>
+<tr><th>GTX3:CDR_PH_ADJ_TIME</th><th>[32, 29, 55]</th><th>[32, 28, 55]</th><th>[32, 29, 54]</th><th>[32, 28, 54]</th><th>[32, 29, 53]</th></tr>
+<tr><th>GTX3:CHAN_BOND_SEQ_2_CFG</th><th>[32, 29, 61]</th><th>[31, 29, 22]</th><th>[31, 28, 22]</th><th>[31, 29, 21]</th><th>[31, 28, 21]</th></tr>
+<tr><th>GTX3:CLK_COR_REPEAT_WAIT</th><th>[31, 28, 55]</th><th>[31, 29, 54]</th><th>[31, 28, 54]</th><th>[31, 29, 53]</th><th>[31, 28, 53]</th></tr>
+<tr><th>GTX3:DFE_CAL_TIME</th><th>[35, 29, 55]</th><th>[35, 28, 55]</th><th>[35, 29, 54]</th><th>[35, 28, 54]</th><th>[35, 29, 53]</th></tr>
+<tr><th>GTX3:RX_DLYALIGN_EDGESET</th><th>[39, 28, 29]</th><th>[39, 29, 28]</th><th>[39, 28, 28]</th><th>[39, 29, 27]</th><th>[39, 28, 27]</th></tr>
+<tr><th>GTX3:TERMINATION_CTRL</th><th>[35, 28, 50]</th><th>[35, 29, 49]</th><th>[35, 28, 49]</th><th>[35, 29, 48]</th><th>[35, 28, 48]</th></tr>
+<tr><th>GTX3:TX_DEEMPH_0</th><th>[37, 28, 50]</th><th>[37, 29, 49]</th><th>[37, 28, 49]</th><th>[37, 29, 48]</th><th>[37, 28, 48]</th></tr>
+<tr><th>GTX3:TX_DEEMPH_1</th><th>[37, 29, 52]</th><th>[37, 28, 52]</th><th>[37, 29, 51]</th><th>[37, 28, 51]</th><th>[37, 29, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:A_DFECLKDLYADJ"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_MAX_LAT"></div>
+<div id="bits-xc6v-GTX-GTX0:CLK_COR_MIN_LAT"></div>
+<div id="bits-xc6v-GTX-GTX0:RXBUF_OVFL_THRESH"></div>
+<div id="bits-xc6v-GTX-GTX0:RXBUF_UDFL_THRESH"></div>
+<div id="bits-xc6v-GTX-GTX0:SAS_MAX_COMSAS"></div>
+<div id="bits-xc6v-GTX-GTX0:SAS_MIN_COMSAS"></div>
+<div id="bits-xc6v-GTX-GTX0:SATA_MAX_BURST"></div>
+<div id="bits-xc6v-GTX-GTX0:SATA_MAX_INIT"></div>
+<div id="bits-xc6v-GTX-GTX0:SATA_MAX_WAKE"></div>
+<div id="bits-xc6v-GTX-GTX0:SATA_MIN_BURST"></div>
+<div id="bits-xc6v-GTX-GTX0:SATA_MIN_INIT"></div>
+<div id="bits-xc6v-GTX-GTX0:SATA_MIN_WAKE"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_BYTECLK_CFG"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_USRCLK_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:A_DFECLKDLYADJ"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_MAX_LAT"></div>
+<div id="bits-xc6v-GTX-GTX1:CLK_COR_MIN_LAT"></div>
+<div id="bits-xc6v-GTX-GTX1:RXBUF_OVFL_THRESH"></div>
+<div id="bits-xc6v-GTX-GTX1:RXBUF_UDFL_THRESH"></div>
+<div id="bits-xc6v-GTX-GTX1:SAS_MAX_COMSAS"></div>
+<div id="bits-xc6v-GTX-GTX1:SAS_MIN_COMSAS"></div>
+<div id="bits-xc6v-GTX-GTX1:SATA_MAX_BURST"></div>
+<div id="bits-xc6v-GTX-GTX1:SATA_MAX_INIT"></div>
+<div id="bits-xc6v-GTX-GTX1:SATA_MAX_WAKE"></div>
+<div id="bits-xc6v-GTX-GTX1:SATA_MIN_BURST"></div>
+<div id="bits-xc6v-GTX-GTX1:SATA_MIN_INIT"></div>
+<div id="bits-xc6v-GTX-GTX1:SATA_MIN_WAKE"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_BYTECLK_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_USRCLK_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:A_DFECLKDLYADJ"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_MAX_LAT"></div>
+<div id="bits-xc6v-GTX-GTX2:CLK_COR_MIN_LAT"></div>
+<div id="bits-xc6v-GTX-GTX2:RXBUF_OVFL_THRESH"></div>
+<div id="bits-xc6v-GTX-GTX2:RXBUF_UDFL_THRESH"></div>
+<div id="bits-xc6v-GTX-GTX2:SAS_MAX_COMSAS"></div>
+<div id="bits-xc6v-GTX-GTX2:SAS_MIN_COMSAS"></div>
+<div id="bits-xc6v-GTX-GTX2:SATA_MAX_BURST"></div>
+<div id="bits-xc6v-GTX-GTX2:SATA_MAX_INIT"></div>
+<div id="bits-xc6v-GTX-GTX2:SATA_MAX_WAKE"></div>
+<div id="bits-xc6v-GTX-GTX2:SATA_MIN_BURST"></div>
+<div id="bits-xc6v-GTX-GTX2:SATA_MIN_INIT"></div>
+<div id="bits-xc6v-GTX-GTX2:SATA_MIN_WAKE"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_BYTECLK_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_USRCLK_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:A_DFECLKDLYADJ"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_MAX_LAT"></div>
+<div id="bits-xc6v-GTX-GTX3:CLK_COR_MIN_LAT"></div>
+<div id="bits-xc6v-GTX-GTX3:RXBUF_OVFL_THRESH"></div>
+<div id="bits-xc6v-GTX-GTX3:RXBUF_UDFL_THRESH"></div>
+<div id="bits-xc6v-GTX-GTX3:SAS_MAX_COMSAS"></div>
+<div id="bits-xc6v-GTX-GTX3:SAS_MIN_COMSAS"></div>
+<div id="bits-xc6v-GTX-GTX3:SATA_MAX_BURST"></div>
+<div id="bits-xc6v-GTX-GTX3:SATA_MAX_INIT"></div>
+<div id="bits-xc6v-GTX-GTX3:SATA_MAX_WAKE"></div>
+<div id="bits-xc6v-GTX-GTX3:SATA_MIN_BURST"></div>
+<div id="bits-xc6v-GTX-GTX3:SATA_MIN_INIT"></div>
+<div id="bits-xc6v-GTX-GTX3:SATA_MIN_WAKE"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_BYTECLK_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_USRCLK_CFG"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:A_DFECLKDLYADJ</th><th>[5, 28, 39]</th><th>[5, 29, 38]</th><th>[5, 28, 38]</th><th>[5, 29, 37]</th><th>[5, 28, 37]</th><th>[5, 29, 36]</th></tr>
+<tr><th>GTX0:CLK_COR_MAX_LAT</th><th>[2, 29, 7]</th><th>[2, 28, 7]</th><th>[2, 29, 6]</th><th>[2, 28, 6]</th><th>[2, 29, 5]</th><th>[2, 28, 5]</th></tr>
+<tr><th>GTX0:CLK_COR_MIN_LAT</th><th>[1, 29, 63]</th><th>[1, 28, 63]</th><th>[1, 29, 62]</th><th>[1, 28, 62]</th><th>[1, 29, 61]</th><th>[1, 28, 61]</th></tr>
+<tr><th>GTX0:RXBUF_OVFL_THRESH</th><th>[1, 29, 34]</th><th>[1, 28, 34]</th><th>[1, 29, 33]</th><th>[1, 28, 33]</th><th>[1, 29, 32]</th><th>[1, 28, 32]</th></tr>
+<tr><th>GTX0:RXBUF_UDFL_THRESH</th><th>[1, 29, 37]</th><th>[1, 28, 37]</th><th>[1, 29, 36]</th><th>[1, 28, 36]</th><th>[1, 29, 35]</th><th>[1, 28, 35]</th></tr>
+<tr><th>GTX0:SAS_MAX_COMSAS</th><th>[5, 29, 10]</th><th>[5, 28, 10]</th><th>[5, 29, 9]</th><th>[5, 28, 9]</th><th>[5, 29, 8]</th><th>[5, 28, 8]</th></tr>
+<tr><th>GTX0:SAS_MIN_COMSAS</th><th>[5, 29, 13]</th><th>[5, 28, 13]</th><th>[5, 29, 12]</th><th>[5, 28, 12]</th><th>[5, 29, 11]</th><th>[5, 28, 11]</th></tr>
+<tr><th>GTX0:SATA_MAX_BURST</th><th>[5, 29, 2]</th><th>[5, 28, 2]</th><th>[5, 29, 1]</th><th>[5, 28, 1]</th><th>[5, 29, 0]</th><th>[5, 28, 0]</th></tr>
+<tr><th>GTX0:SATA_MAX_INIT</th><th>[4, 29, 58]</th><th>[4, 28, 58]</th><th>[4, 29, 57]</th><th>[4, 28, 57]</th><th>[4, 29, 56]</th><th>[4, 28, 56]</th></tr>
+<tr><th>GTX0:SATA_MAX_WAKE</th><th>[4, 29, 50]</th><th>[4, 28, 50]</th><th>[4, 29, 49]</th><th>[4, 28, 49]</th><th>[4, 29, 48]</th><th>[4, 28, 48]</th></tr>
+<tr><th>GTX0:SATA_MIN_BURST</th><th>[5, 29, 5]</th><th>[5, 28, 5]</th><th>[5, 29, 4]</th><th>[5, 28, 4]</th><th>[5, 29, 3]</th><th>[5, 28, 3]</th></tr>
+<tr><th>GTX0:SATA_MIN_INIT</th><th>[4, 29, 61]</th><th>[4, 28, 61]</th><th>[4, 29, 60]</th><th>[4, 28, 60]</th><th>[4, 29, 59]</th><th>[4, 28, 59]</th></tr>
+<tr><th>GTX0:SATA_MIN_WAKE</th><th>[4, 29, 53]</th><th>[4, 28, 53]</th><th>[4, 29, 52]</th><th>[4, 28, 52]</th><th>[4, 29, 51]</th><th>[4, 28, 51]</th></tr>
+<tr><th>GTX0:TX_BYTECLK_CFG</th><th>[8, 29, 42]</th><th>[8, 28, 42]</th><th>[8, 29, 41]</th><th>[8, 28, 41]</th><th>[8, 29, 40]</th><th>[8, 28, 40]</th></tr>
+<tr><th>GTX0:TX_USRCLK_CFG</th><th>[8, 29, 45]</th><th>[8, 28, 45]</th><th>[8, 29, 44]</th><th>[8, 28, 44]</th><th>[8, 29, 43]</th><th>[8, 28, 43]</th></tr>
+<tr><th>GTX1:A_DFECLKDLYADJ</th><th>[15, 28, 39]</th><th>[15, 29, 38]</th><th>[15, 28, 38]</th><th>[15, 29, 37]</th><th>[15, 28, 37]</th><th>[15, 29, 36]</th></tr>
+<tr><th>GTX1:CLK_COR_MAX_LAT</th><th>[12, 29, 7]</th><th>[12, 28, 7]</th><th>[12, 29, 6]</th><th>[12, 28, 6]</th><th>[12, 29, 5]</th><th>[12, 28, 5]</th></tr>
+<tr><th>GTX1:CLK_COR_MIN_LAT</th><th>[11, 29, 63]</th><th>[11, 28, 63]</th><th>[11, 29, 62]</th><th>[11, 28, 62]</th><th>[11, 29, 61]</th><th>[11, 28, 61]</th></tr>
+<tr><th>GTX1:RXBUF_OVFL_THRESH</th><th>[11, 29, 34]</th><th>[11, 28, 34]</th><th>[11, 29, 33]</th><th>[11, 28, 33]</th><th>[11, 29, 32]</th><th>[11, 28, 32]</th></tr>
+<tr><th>GTX1:RXBUF_UDFL_THRESH</th><th>[11, 29, 37]</th><th>[11, 28, 37]</th><th>[11, 29, 36]</th><th>[11, 28, 36]</th><th>[11, 29, 35]</th><th>[11, 28, 35]</th></tr>
+<tr><th>GTX1:SAS_MAX_COMSAS</th><th>[15, 29, 10]</th><th>[15, 28, 10]</th><th>[15, 29, 9]</th><th>[15, 28, 9]</th><th>[15, 29, 8]</th><th>[15, 28, 8]</th></tr>
+<tr><th>GTX1:SAS_MIN_COMSAS</th><th>[15, 29, 13]</th><th>[15, 28, 13]</th><th>[15, 29, 12]</th><th>[15, 28, 12]</th><th>[15, 29, 11]</th><th>[15, 28, 11]</th></tr>
+<tr><th>GTX1:SATA_MAX_BURST</th><th>[15, 29, 2]</th><th>[15, 28, 2]</th><th>[15, 29, 1]</th><th>[15, 28, 1]</th><th>[15, 29, 0]</th><th>[15, 28, 0]</th></tr>
+<tr><th>GTX1:SATA_MAX_INIT</th><th>[14, 29, 58]</th><th>[14, 28, 58]</th><th>[14, 29, 57]</th><th>[14, 28, 57]</th><th>[14, 29, 56]</th><th>[14, 28, 56]</th></tr>
+<tr><th>GTX1:SATA_MAX_WAKE</th><th>[14, 29, 50]</th><th>[14, 28, 50]</th><th>[14, 29, 49]</th><th>[14, 28, 49]</th><th>[14, 29, 48]</th><th>[14, 28, 48]</th></tr>
+<tr><th>GTX1:SATA_MIN_BURST</th><th>[15, 29, 5]</th><th>[15, 28, 5]</th><th>[15, 29, 4]</th><th>[15, 28, 4]</th><th>[15, 29, 3]</th><th>[15, 28, 3]</th></tr>
+<tr><th>GTX1:SATA_MIN_INIT</th><th>[14, 29, 61]</th><th>[14, 28, 61]</th><th>[14, 29, 60]</th><th>[14, 28, 60]</th><th>[14, 29, 59]</th><th>[14, 28, 59]</th></tr>
+<tr><th>GTX1:SATA_MIN_WAKE</th><th>[14, 29, 53]</th><th>[14, 28, 53]</th><th>[14, 29, 52]</th><th>[14, 28, 52]</th><th>[14, 29, 51]</th><th>[14, 28, 51]</th></tr>
+<tr><th>GTX1:TX_BYTECLK_CFG</th><th>[18, 29, 42]</th><th>[18, 28, 42]</th><th>[18, 29, 41]</th><th>[18, 28, 41]</th><th>[18, 29, 40]</th><th>[18, 28, 40]</th></tr>
+<tr><th>GTX1:TX_USRCLK_CFG</th><th>[18, 29, 45]</th><th>[18, 28, 45]</th><th>[18, 29, 44]</th><th>[18, 28, 44]</th><th>[18, 29, 43]</th><th>[18, 28, 43]</th></tr>
+<tr><th>GTX2:A_DFECLKDLYADJ</th><th>[25, 28, 39]</th><th>[25, 29, 38]</th><th>[25, 28, 38]</th><th>[25, 29, 37]</th><th>[25, 28, 37]</th><th>[25, 29, 36]</th></tr>
+<tr><th>GTX2:CLK_COR_MAX_LAT</th><th>[22, 29, 7]</th><th>[22, 28, 7]</th><th>[22, 29, 6]</th><th>[22, 28, 6]</th><th>[22, 29, 5]</th><th>[22, 28, 5]</th></tr>
+<tr><th>GTX2:CLK_COR_MIN_LAT</th><th>[21, 29, 63]</th><th>[21, 28, 63]</th><th>[21, 29, 62]</th><th>[21, 28, 62]</th><th>[21, 29, 61]</th><th>[21, 28, 61]</th></tr>
+<tr><th>GTX2:RXBUF_OVFL_THRESH</th><th>[21, 29, 34]</th><th>[21, 28, 34]</th><th>[21, 29, 33]</th><th>[21, 28, 33]</th><th>[21, 29, 32]</th><th>[21, 28, 32]</th></tr>
+<tr><th>GTX2:RXBUF_UDFL_THRESH</th><th>[21, 29, 37]</th><th>[21, 28, 37]</th><th>[21, 29, 36]</th><th>[21, 28, 36]</th><th>[21, 29, 35]</th><th>[21, 28, 35]</th></tr>
+<tr><th>GTX2:SAS_MAX_COMSAS</th><th>[25, 29, 10]</th><th>[25, 28, 10]</th><th>[25, 29, 9]</th><th>[25, 28, 9]</th><th>[25, 29, 8]</th><th>[25, 28, 8]</th></tr>
+<tr><th>GTX2:SAS_MIN_COMSAS</th><th>[25, 29, 13]</th><th>[25, 28, 13]</th><th>[25, 29, 12]</th><th>[25, 28, 12]</th><th>[25, 29, 11]</th><th>[25, 28, 11]</th></tr>
+<tr><th>GTX2:SATA_MAX_BURST</th><th>[25, 29, 2]</th><th>[25, 28, 2]</th><th>[25, 29, 1]</th><th>[25, 28, 1]</th><th>[25, 29, 0]</th><th>[25, 28, 0]</th></tr>
+<tr><th>GTX2:SATA_MAX_INIT</th><th>[24, 29, 58]</th><th>[24, 28, 58]</th><th>[24, 29, 57]</th><th>[24, 28, 57]</th><th>[24, 29, 56]</th><th>[24, 28, 56]</th></tr>
+<tr><th>GTX2:SATA_MAX_WAKE</th><th>[24, 29, 50]</th><th>[24, 28, 50]</th><th>[24, 29, 49]</th><th>[24, 28, 49]</th><th>[24, 29, 48]</th><th>[24, 28, 48]</th></tr>
+<tr><th>GTX2:SATA_MIN_BURST</th><th>[25, 29, 5]</th><th>[25, 28, 5]</th><th>[25, 29, 4]</th><th>[25, 28, 4]</th><th>[25, 29, 3]</th><th>[25, 28, 3]</th></tr>
+<tr><th>GTX2:SATA_MIN_INIT</th><th>[24, 29, 61]</th><th>[24, 28, 61]</th><th>[24, 29, 60]</th><th>[24, 28, 60]</th><th>[24, 29, 59]</th><th>[24, 28, 59]</th></tr>
+<tr><th>GTX2:SATA_MIN_WAKE</th><th>[24, 29, 53]</th><th>[24, 28, 53]</th><th>[24, 29, 52]</th><th>[24, 28, 52]</th><th>[24, 29, 51]</th><th>[24, 28, 51]</th></tr>
+<tr><th>GTX2:TX_BYTECLK_CFG</th><th>[28, 29, 42]</th><th>[28, 28, 42]</th><th>[28, 29, 41]</th><th>[28, 28, 41]</th><th>[28, 29, 40]</th><th>[28, 28, 40]</th></tr>
+<tr><th>GTX2:TX_USRCLK_CFG</th><th>[28, 29, 45]</th><th>[28, 28, 45]</th><th>[28, 29, 44]</th><th>[28, 28, 44]</th><th>[28, 29, 43]</th><th>[28, 28, 43]</th></tr>
+<tr><th>GTX3:A_DFECLKDLYADJ</th><th>[35, 28, 39]</th><th>[35, 29, 38]</th><th>[35, 28, 38]</th><th>[35, 29, 37]</th><th>[35, 28, 37]</th><th>[35, 29, 36]</th></tr>
+<tr><th>GTX3:CLK_COR_MAX_LAT</th><th>[32, 29, 7]</th><th>[32, 28, 7]</th><th>[32, 29, 6]</th><th>[32, 28, 6]</th><th>[32, 29, 5]</th><th>[32, 28, 5]</th></tr>
+<tr><th>GTX3:CLK_COR_MIN_LAT</th><th>[31, 29, 63]</th><th>[31, 28, 63]</th><th>[31, 29, 62]</th><th>[31, 28, 62]</th><th>[31, 29, 61]</th><th>[31, 28, 61]</th></tr>
+<tr><th>GTX3:RXBUF_OVFL_THRESH</th><th>[31, 29, 34]</th><th>[31, 28, 34]</th><th>[31, 29, 33]</th><th>[31, 28, 33]</th><th>[31, 29, 32]</th><th>[31, 28, 32]</th></tr>
+<tr><th>GTX3:RXBUF_UDFL_THRESH</th><th>[31, 29, 37]</th><th>[31, 28, 37]</th><th>[31, 29, 36]</th><th>[31, 28, 36]</th><th>[31, 29, 35]</th><th>[31, 28, 35]</th></tr>
+<tr><th>GTX3:SAS_MAX_COMSAS</th><th>[35, 29, 10]</th><th>[35, 28, 10]</th><th>[35, 29, 9]</th><th>[35, 28, 9]</th><th>[35, 29, 8]</th><th>[35, 28, 8]</th></tr>
+<tr><th>GTX3:SAS_MIN_COMSAS</th><th>[35, 29, 13]</th><th>[35, 28, 13]</th><th>[35, 29, 12]</th><th>[35, 28, 12]</th><th>[35, 29, 11]</th><th>[35, 28, 11]</th></tr>
+<tr><th>GTX3:SATA_MAX_BURST</th><th>[35, 29, 2]</th><th>[35, 28, 2]</th><th>[35, 29, 1]</th><th>[35, 28, 1]</th><th>[35, 29, 0]</th><th>[35, 28, 0]</th></tr>
+<tr><th>GTX3:SATA_MAX_INIT</th><th>[34, 29, 58]</th><th>[34, 28, 58]</th><th>[34, 29, 57]</th><th>[34, 28, 57]</th><th>[34, 29, 56]</th><th>[34, 28, 56]</th></tr>
+<tr><th>GTX3:SATA_MAX_WAKE</th><th>[34, 29, 50]</th><th>[34, 28, 50]</th><th>[34, 29, 49]</th><th>[34, 28, 49]</th><th>[34, 29, 48]</th><th>[34, 28, 48]</th></tr>
+<tr><th>GTX3:SATA_MIN_BURST</th><th>[35, 29, 5]</th><th>[35, 28, 5]</th><th>[35, 29, 4]</th><th>[35, 28, 4]</th><th>[35, 29, 3]</th><th>[35, 28, 3]</th></tr>
+<tr><th>GTX3:SATA_MIN_INIT</th><th>[34, 29, 61]</th><th>[34, 28, 61]</th><th>[34, 29, 60]</th><th>[34, 28, 60]</th><th>[34, 29, 59]</th><th>[34, 28, 59]</th></tr>
+<tr><th>GTX3:SATA_MIN_WAKE</th><th>[34, 29, 53]</th><th>[34, 28, 53]</th><th>[34, 29, 52]</th><th>[34, 28, 52]</th><th>[34, 29, 51]</th><th>[34, 28, 51]</th></tr>
+<tr><th>GTX3:TX_BYTECLK_CFG</th><th>[38, 29, 42]</th><th>[38, 28, 42]</th><th>[38, 29, 41]</th><th>[38, 28, 41]</th><th>[38, 29, 40]</th><th>[38, 28, 40]</th></tr>
+<tr><th>GTX3:TX_USRCLK_CFG</th><th>[38, 29, 45]</th><th>[38, 28, 45]</th><th>[38, 29, 44]</th><th>[38, 28, 44]</th><th>[38, 29, 43]</th><th>[38, 28, 43]</th></tr>
+<tr><td>Non-inverted</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:RX_XCLK_SEL"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_XCLK_SEL"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_XCLK_SEL"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_XCLK_SEL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:RX_XCLK_SEL</th><th>[1, 29, 29]</th></tr>
+<tr><th>GTX1:RX_XCLK_SEL</th><th>[11, 29, 29]</th></tr>
+<tr><th>GTX2:RX_XCLK_SEL</th><th>[21, 29, 29]</th></tr>
+<tr><th>GTX3:RX_XCLK_SEL</th><th>[31, 29, 29]</th></tr>
+<tr><td>RXREC</td><td>0</td></tr>
+<tr><td>RXUSR</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:RX_FIFO_ADDR_MODE"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_FIFO_ADDR_MODE"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_FIFO_ADDR_MODE"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_FIFO_ADDR_MODE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:RX_FIFO_ADDR_MODE</th><th>[1, 29, 38]</th></tr>
+<tr><th>GTX1:RX_FIFO_ADDR_MODE</th><th>[11, 29, 38]</th></tr>
+<tr><th>GTX2:RX_FIFO_ADDR_MODE</th><th>[21, 29, 38]</th></tr>
+<tr><th>GTX3:RX_FIFO_ADDR_MODE</th><th>[31, 29, 38]</th></tr>
+<tr><td>FULL</td><td>0</td></tr>
+<tr><td>FAST</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:RX_SLIDE_MODE"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_SLIDE_MODE"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_SLIDE_MODE"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_SLIDE_MODE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:RX_SLIDE_MODE</th><th>[2, 29, 22]</th><th>[2, 28, 22]</th></tr>
+<tr><th>GTX1:RX_SLIDE_MODE</th><th>[12, 29, 22]</th><th>[12, 28, 22]</th></tr>
+<tr><th>GTX2:RX_SLIDE_MODE</th><th>[22, 29, 22]</th><th>[22, 28, 22]</th></tr>
+<tr><th>GTX3:RX_SLIDE_MODE</th><th>[32, 29, 22]</th><th>[32, 28, 22]</th></tr>
+<tr><td>#OFF</td><td>0</td><td>0</td></tr>
+<tr><td>AUTO</td><td>0</td><td>1</td></tr>
+<tr><td>PCS</td><td>1</td><td>0</td></tr>
+<tr><td>PMA</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:ALIGN_COMMA_WORD"></div>
+<div id="bits-xc6v-GTX-GTX1:ALIGN_COMMA_WORD"></div>
+<div id="bits-xc6v-GTX-GTX2:ALIGN_COMMA_WORD"></div>
+<div id="bits-xc6v-GTX-GTX3:ALIGN_COMMA_WORD"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:ALIGN_COMMA_WORD</th><th>[2, 28, 39]</th></tr>
+<tr><th>GTX1:ALIGN_COMMA_WORD</th><th>[12, 28, 39]</th></tr>
+<tr><th>GTX2:ALIGN_COMMA_WORD</th><th>[22, 28, 39]</th></tr>
+<tr><th>GTX3:ALIGN_COMMA_WORD</th><th>[32, 28, 39]</th></tr>
+<tr><td>1</td><td>0</td></tr>
+<tr><td>2</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:PMA_CDR_SCAN"></div>
+<div id="bits-xc6v-GTX-GTX1:PMA_CDR_SCAN"></div>
+<div id="bits-xc6v-GTX-GTX2:PMA_CDR_SCAN"></div>
+<div id="bits-xc6v-GTX-GTX3:PMA_CDR_SCAN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:PMA_CDR_SCAN</th><th>[2, 28, 53]</th><th>[2, 29, 52]</th><th>[2, 28, 52]</th><th>[2, 29, 51]</th><th>[2, 28, 51]</th><th>[2, 29, 50]</th><th>[2, 28, 50]</th><th>[2, 29, 49]</th><th>[2, 28, 49]</th><th>[2, 29, 48]</th><th>[2, 28, 48]</th><th>[2, 29, 47]</th><th>[2, 28, 47]</th><th>[2, 29, 46]</th><th>[2, 28, 46]</th><th>[2, 29, 45]</th><th>[2, 28, 45]</th><th>[2, 29, 44]</th><th>[2, 28, 44]</th><th>[2, 29, 43]</th><th>[2, 28, 43]</th><th>[2, 29, 42]</th><th>[2, 28, 42]</th><th>[2, 29, 41]</th><th>[2, 28, 41]</th><th>[2, 29, 40]</th><th>[2, 28, 40]</th></tr>
+<tr><th>GTX1:PMA_CDR_SCAN</th><th>[12, 28, 53]</th><th>[12, 29, 52]</th><th>[12, 28, 52]</th><th>[12, 29, 51]</th><th>[12, 28, 51]</th><th>[12, 29, 50]</th><th>[12, 28, 50]</th><th>[12, 29, 49]</th><th>[12, 28, 49]</th><th>[12, 29, 48]</th><th>[12, 28, 48]</th><th>[12, 29, 47]</th><th>[12, 28, 47]</th><th>[12, 29, 46]</th><th>[12, 28, 46]</th><th>[12, 29, 45]</th><th>[12, 28, 45]</th><th>[12, 29, 44]</th><th>[12, 28, 44]</th><th>[12, 29, 43]</th><th>[12, 28, 43]</th><th>[12, 29, 42]</th><th>[12, 28, 42]</th><th>[12, 29, 41]</th><th>[12, 28, 41]</th><th>[12, 29, 40]</th><th>[12, 28, 40]</th></tr>
+<tr><th>GTX2:PMA_CDR_SCAN</th><th>[22, 28, 53]</th><th>[22, 29, 52]</th><th>[22, 28, 52]</th><th>[22, 29, 51]</th><th>[22, 28, 51]</th><th>[22, 29, 50]</th><th>[22, 28, 50]</th><th>[22, 29, 49]</th><th>[22, 28, 49]</th><th>[22, 29, 48]</th><th>[22, 28, 48]</th><th>[22, 29, 47]</th><th>[22, 28, 47]</th><th>[22, 29, 46]</th><th>[22, 28, 46]</th><th>[22, 29, 45]</th><th>[22, 28, 45]</th><th>[22, 29, 44]</th><th>[22, 28, 44]</th><th>[22, 29, 43]</th><th>[22, 28, 43]</th><th>[22, 29, 42]</th><th>[22, 28, 42]</th><th>[22, 29, 41]</th><th>[22, 28, 41]</th><th>[22, 29, 40]</th><th>[22, 28, 40]</th></tr>
+<tr><th>GTX3:PMA_CDR_SCAN</th><th>[32, 28, 53]</th><th>[32, 29, 52]</th><th>[32, 28, 52]</th><th>[32, 29, 51]</th><th>[32, 28, 51]</th><th>[32, 29, 50]</th><th>[32, 28, 50]</th><th>[32, 29, 49]</th><th>[32, 28, 49]</th><th>[32, 29, 48]</th><th>[32, 28, 48]</th><th>[32, 29, 47]</th><th>[32, 28, 47]</th><th>[32, 29, 46]</th><th>[32, 28, 46]</th><th>[32, 29, 45]</th><th>[32, 28, 45]</th><th>[32, 29, 44]</th><th>[32, 28, 44]</th><th>[32, 29, 43]</th><th>[32, 28, 43]</th><th>[32, 29, 42]</th><th>[32, 28, 42]</th><th>[32, 29, 41]</th><th>[32, 28, 41]</th><th>[32, 29, 40]</th><th>[32, 28, 40]</th></tr>
+<tr><td>Non-inverted</td><td>[26]</td><td>[25]</td><td>[24]</td><td>[23]</td><td>[22]</td><td>[21]</td><td>[20]</td><td>[19]</td><td>[18]</td><td>[17]</td><td>[16]</td><td>[15]</td><td>[14]</td><td>[13]</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:A_LOOPBACK"></div>
+<div id="bits-xc6v-GTX-GTX0:A_RXENPRBSTST"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXBUFDIFFCTRL"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXENPRBSTST"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXMARGIN"></div>
+<div id="bits-xc6v-GTX-GTX0:GEARBOX_ENDEC"></div>
+<div id="bits-xc6v-GTX-GTX0:OOBDETECT_THRESHOLD"></div>
+<div id="bits-xc6v-GTX-GTX0:RXPLL_LKDET_CFG"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_DLYALIGN_MONSEL"></div>
+<div id="bits-xc6v-GTX-GTX0:SATA_BURST_VAL"></div>
+<div id="bits-xc6v-GTX-GTX0:SATA_IDLE_VAL"></div>
+<div id="bits-xc6v-GTX-GTX0:TXPLL_LKDET_CFG"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_DLYALIGN_MONSEL"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_IDLE_ASSERT_DELAY"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_IDLE_DEASSERT_DELAY"></div>
+<div id="bits-xc6v-GTX-GTX1:A_LOOPBACK"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXENPRBSTST"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXBUFDIFFCTRL"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXENPRBSTST"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXMARGIN"></div>
+<div id="bits-xc6v-GTX-GTX1:GEARBOX_ENDEC"></div>
+<div id="bits-xc6v-GTX-GTX1:OOBDETECT_THRESHOLD"></div>
+<div id="bits-xc6v-GTX-GTX1:RXPLL_LKDET_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_DLYALIGN_MONSEL"></div>
+<div id="bits-xc6v-GTX-GTX1:SATA_BURST_VAL"></div>
+<div id="bits-xc6v-GTX-GTX1:SATA_IDLE_VAL"></div>
+<div id="bits-xc6v-GTX-GTX1:TXPLL_LKDET_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_DLYALIGN_MONSEL"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_IDLE_ASSERT_DELAY"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_IDLE_DEASSERT_DELAY"></div>
+<div id="bits-xc6v-GTX-GTX2:A_LOOPBACK"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXENPRBSTST"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXBUFDIFFCTRL"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXENPRBSTST"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXMARGIN"></div>
+<div id="bits-xc6v-GTX-GTX2:GEARBOX_ENDEC"></div>
+<div id="bits-xc6v-GTX-GTX2:OOBDETECT_THRESHOLD"></div>
+<div id="bits-xc6v-GTX-GTX2:RXPLL_LKDET_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_DLYALIGN_MONSEL"></div>
+<div id="bits-xc6v-GTX-GTX2:SATA_BURST_VAL"></div>
+<div id="bits-xc6v-GTX-GTX2:SATA_IDLE_VAL"></div>
+<div id="bits-xc6v-GTX-GTX2:TXPLL_LKDET_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_DLYALIGN_MONSEL"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_IDLE_ASSERT_DELAY"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_IDLE_DEASSERT_DELAY"></div>
+<div id="bits-xc6v-GTX-GTX3:A_LOOPBACK"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXENPRBSTST"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXBUFDIFFCTRL"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXENPRBSTST"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXMARGIN"></div>
+<div id="bits-xc6v-GTX-GTX3:GEARBOX_ENDEC"></div>
+<div id="bits-xc6v-GTX-GTX3:OOBDETECT_THRESHOLD"></div>
+<div id="bits-xc6v-GTX-GTX3:RXPLL_LKDET_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_DLYALIGN_MONSEL"></div>
+<div id="bits-xc6v-GTX-GTX3:SATA_BURST_VAL"></div>
+<div id="bits-xc6v-GTX-GTX3:SATA_IDLE_VAL"></div>
+<div id="bits-xc6v-GTX-GTX3:TXPLL_LKDET_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_DLYALIGN_MONSEL"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_IDLE_ASSERT_DELAY"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_IDLE_DEASSERT_DELAY"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:A_LOOPBACK</th><th>[5, 29, 17]</th><th>[5, 28, 17]</th><th>[5, 29, 16]</th></tr>
+<tr><th>GTX0:A_RXENPRBSTST</th><th>[5, 29, 19]</th><th>[5, 28, 19]</th><th>[5, 29, 18]</th></tr>
+<tr><th>GTX0:A_TXBUFDIFFCTRL</th><th>[7, 28, 43]</th><th>[7, 29, 42]</th><th>[7, 28, 42]</th></tr>
+<tr><th>GTX0:A_TXENPRBSTST</th><th>[5, 29, 22]</th><th>[5, 28, 22]</th><th>[5, 29, 21]</th></tr>
+<tr><th>GTX0:A_TXMARGIN</th><th>[7, 29, 55]</th><th>[7, 28, 55]</th><th>[7, 29, 54]</th></tr>
+<tr><th>GTX0:GEARBOX_ENDEC</th><th>[3, 28, 1]</th><th>[3, 29, 0]</th><th>[3, 28, 0]</th></tr>
+<tr><th>GTX0:OOBDETECT_THRESHOLD</th><th>[2, 28, 57]</th><th>[2, 29, 56]</th><th>[2, 28, 56]</th></tr>
+<tr><th>GTX0:RXPLL_LKDET_CFG</th><th>[3, 29, 30]</th><th>[3, 28, 30]</th><th>[3, 29, 29]</th></tr>
+<tr><th>GTX0:RX_DLYALIGN_MONSEL</th><th>[9, 28, 25]</th><th>[9, 29, 24]</th><th>[9, 28, 24]</th></tr>
+<tr><th>GTX0:SATA_BURST_VAL</th><th>[5, 28, 7]</th><th>[5, 29, 6]</th><th>[5, 28, 6]</th></tr>
+<tr><th>GTX0:SATA_IDLE_VAL</th><th>[4, 28, 63]</th><th>[4, 29, 62]</th><th>[4, 28, 62]</th></tr>
+<tr><th>GTX0:TXPLL_LKDET_CFG</th><th>[3, 29, 62]</th><th>[3, 28, 62]</th><th>[3, 29, 61]</th></tr>
+<tr><th>GTX0:TX_DLYALIGN_MONSEL</th><th>[9, 29, 26]</th><th>[9, 28, 26]</th><th>[9, 29, 25]</th></tr>
+<tr><th>GTX0:TX_IDLE_ASSERT_DELAY</th><th>[5, 29, 62]</th><th>[5, 28, 62]</th><th>[5, 29, 61]</th></tr>
+<tr><th>GTX0:TX_IDLE_DEASSERT_DELAY</th><th>[6, 29, 6]</th><th>[6, 28, 6]</th><th>[6, 29, 5]</th></tr>
+<tr><th>GTX1:A_LOOPBACK</th><th>[15, 29, 17]</th><th>[15, 28, 17]</th><th>[15, 29, 16]</th></tr>
+<tr><th>GTX1:A_RXENPRBSTST</th><th>[15, 29, 19]</th><th>[15, 28, 19]</th><th>[15, 29, 18]</th></tr>
+<tr><th>GTX1:A_TXBUFDIFFCTRL</th><th>[17, 28, 43]</th><th>[17, 29, 42]</th><th>[17, 28, 42]</th></tr>
+<tr><th>GTX1:A_TXENPRBSTST</th><th>[15, 29, 22]</th><th>[15, 28, 22]</th><th>[15, 29, 21]</th></tr>
+<tr><th>GTX1:A_TXMARGIN</th><th>[17, 29, 55]</th><th>[17, 28, 55]</th><th>[17, 29, 54]</th></tr>
+<tr><th>GTX1:GEARBOX_ENDEC</th><th>[13, 28, 1]</th><th>[13, 29, 0]</th><th>[13, 28, 0]</th></tr>
+<tr><th>GTX1:OOBDETECT_THRESHOLD</th><th>[12, 28, 57]</th><th>[12, 29, 56]</th><th>[12, 28, 56]</th></tr>
+<tr><th>GTX1:RXPLL_LKDET_CFG</th><th>[13, 29, 30]</th><th>[13, 28, 30]</th><th>[13, 29, 29]</th></tr>
+<tr><th>GTX1:RX_DLYALIGN_MONSEL</th><th>[19, 28, 25]</th><th>[19, 29, 24]</th><th>[19, 28, 24]</th></tr>
+<tr><th>GTX1:SATA_BURST_VAL</th><th>[15, 28, 7]</th><th>[15, 29, 6]</th><th>[15, 28, 6]</th></tr>
+<tr><th>GTX1:SATA_IDLE_VAL</th><th>[14, 28, 63]</th><th>[14, 29, 62]</th><th>[14, 28, 62]</th></tr>
+<tr><th>GTX1:TXPLL_LKDET_CFG</th><th>[13, 29, 62]</th><th>[13, 28, 62]</th><th>[13, 29, 61]</th></tr>
+<tr><th>GTX1:TX_DLYALIGN_MONSEL</th><th>[19, 29, 26]</th><th>[19, 28, 26]</th><th>[19, 29, 25]</th></tr>
+<tr><th>GTX1:TX_IDLE_ASSERT_DELAY</th><th>[15, 29, 62]</th><th>[15, 28, 62]</th><th>[15, 29, 61]</th></tr>
+<tr><th>GTX1:TX_IDLE_DEASSERT_DELAY</th><th>[16, 29, 6]</th><th>[16, 28, 6]</th><th>[16, 29, 5]</th></tr>
+<tr><th>GTX2:A_LOOPBACK</th><th>[25, 29, 17]</th><th>[25, 28, 17]</th><th>[25, 29, 16]</th></tr>
+<tr><th>GTX2:A_RXENPRBSTST</th><th>[25, 29, 19]</th><th>[25, 28, 19]</th><th>[25, 29, 18]</th></tr>
+<tr><th>GTX2:A_TXBUFDIFFCTRL</th><th>[27, 28, 43]</th><th>[27, 29, 42]</th><th>[27, 28, 42]</th></tr>
+<tr><th>GTX2:A_TXENPRBSTST</th><th>[25, 29, 22]</th><th>[25, 28, 22]</th><th>[25, 29, 21]</th></tr>
+<tr><th>GTX2:A_TXMARGIN</th><th>[27, 29, 55]</th><th>[27, 28, 55]</th><th>[27, 29, 54]</th></tr>
+<tr><th>GTX2:GEARBOX_ENDEC</th><th>[23, 28, 1]</th><th>[23, 29, 0]</th><th>[23, 28, 0]</th></tr>
+<tr><th>GTX2:OOBDETECT_THRESHOLD</th><th>[22, 28, 57]</th><th>[22, 29, 56]</th><th>[22, 28, 56]</th></tr>
+<tr><th>GTX2:RXPLL_LKDET_CFG</th><th>[23, 29, 30]</th><th>[23, 28, 30]</th><th>[23, 29, 29]</th></tr>
+<tr><th>GTX2:RX_DLYALIGN_MONSEL</th><th>[29, 28, 25]</th><th>[29, 29, 24]</th><th>[29, 28, 24]</th></tr>
+<tr><th>GTX2:SATA_BURST_VAL</th><th>[25, 28, 7]</th><th>[25, 29, 6]</th><th>[25, 28, 6]</th></tr>
+<tr><th>GTX2:SATA_IDLE_VAL</th><th>[24, 28, 63]</th><th>[24, 29, 62]</th><th>[24, 28, 62]</th></tr>
+<tr><th>GTX2:TXPLL_LKDET_CFG</th><th>[23, 29, 62]</th><th>[23, 28, 62]</th><th>[23, 29, 61]</th></tr>
+<tr><th>GTX2:TX_DLYALIGN_MONSEL</th><th>[29, 29, 26]</th><th>[29, 28, 26]</th><th>[29, 29, 25]</th></tr>
+<tr><th>GTX2:TX_IDLE_ASSERT_DELAY</th><th>[25, 29, 62]</th><th>[25, 28, 62]</th><th>[25, 29, 61]</th></tr>
+<tr><th>GTX2:TX_IDLE_DEASSERT_DELAY</th><th>[26, 29, 6]</th><th>[26, 28, 6]</th><th>[26, 29, 5]</th></tr>
+<tr><th>GTX3:A_LOOPBACK</th><th>[35, 29, 17]</th><th>[35, 28, 17]</th><th>[35, 29, 16]</th></tr>
+<tr><th>GTX3:A_RXENPRBSTST</th><th>[35, 29, 19]</th><th>[35, 28, 19]</th><th>[35, 29, 18]</th></tr>
+<tr><th>GTX3:A_TXBUFDIFFCTRL</th><th>[37, 28, 43]</th><th>[37, 29, 42]</th><th>[37, 28, 42]</th></tr>
+<tr><th>GTX3:A_TXENPRBSTST</th><th>[35, 29, 22]</th><th>[35, 28, 22]</th><th>[35, 29, 21]</th></tr>
+<tr><th>GTX3:A_TXMARGIN</th><th>[37, 29, 55]</th><th>[37, 28, 55]</th><th>[37, 29, 54]</th></tr>
+<tr><th>GTX3:GEARBOX_ENDEC</th><th>[33, 28, 1]</th><th>[33, 29, 0]</th><th>[33, 28, 0]</th></tr>
+<tr><th>GTX3:OOBDETECT_THRESHOLD</th><th>[32, 28, 57]</th><th>[32, 29, 56]</th><th>[32, 28, 56]</th></tr>
+<tr><th>GTX3:RXPLL_LKDET_CFG</th><th>[33, 29, 30]</th><th>[33, 28, 30]</th><th>[33, 29, 29]</th></tr>
+<tr><th>GTX3:RX_DLYALIGN_MONSEL</th><th>[39, 28, 25]</th><th>[39, 29, 24]</th><th>[39, 28, 24]</th></tr>
+<tr><th>GTX3:SATA_BURST_VAL</th><th>[35, 28, 7]</th><th>[35, 29, 6]</th><th>[35, 28, 6]</th></tr>
+<tr><th>GTX3:SATA_IDLE_VAL</th><th>[34, 28, 63]</th><th>[34, 29, 62]</th><th>[34, 28, 62]</th></tr>
+<tr><th>GTX3:TXPLL_LKDET_CFG</th><th>[33, 29, 62]</th><th>[33, 28, 62]</th><th>[33, 29, 61]</th></tr>
+<tr><th>GTX3:TX_DLYALIGN_MONSEL</th><th>[39, 29, 26]</th><th>[39, 28, 26]</th><th>[39, 29, 25]</th></tr>
+<tr><th>GTX3:TX_IDLE_ASSERT_DELAY</th><th>[35, 29, 62]</th><th>[35, 28, 62]</th><th>[35, 29, 61]</th></tr>
+<tr><th>GTX3:TX_IDLE_DEASSERT_DELAY</th><th>[36, 29, 6]</th><th>[36, 28, 6]</th><th>[36, 29, 5]</th></tr>
+<tr><td>Non-inverted</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:RX_DATA_WIDTH"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_DATA_WIDTH"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_DATA_WIDTH"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_DATA_WIDTH"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_DATA_WIDTH"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_DATA_WIDTH"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_DATA_WIDTH"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_DATA_WIDTH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:RX_DATA_WIDTH</th><th>[2, 28, 63]</th><th>[2, 29, 62]</th><th>[2, 28, 62]</th></tr>
+<tr><th>GTX0:TX_DATA_WIDTH</th><th>[6, 28, 15]</th><th>[6, 29, 14]</th><th>[6, 28, 14]</th></tr>
+<tr><th>GTX1:RX_DATA_WIDTH</th><th>[12, 28, 63]</th><th>[12, 29, 62]</th><th>[12, 28, 62]</th></tr>
+<tr><th>GTX1:TX_DATA_WIDTH</th><th>[16, 28, 15]</th><th>[16, 29, 14]</th><th>[16, 28, 14]</th></tr>
+<tr><th>GTX2:RX_DATA_WIDTH</th><th>[22, 28, 63]</th><th>[22, 29, 62]</th><th>[22, 28, 62]</th></tr>
+<tr><th>GTX2:TX_DATA_WIDTH</th><th>[26, 28, 15]</th><th>[26, 29, 14]</th><th>[26, 28, 14]</th></tr>
+<tr><th>GTX3:RX_DATA_WIDTH</th><th>[32, 28, 63]</th><th>[32, 29, 62]</th><th>[32, 28, 62]</th></tr>
+<tr><th>GTX3:TX_DATA_WIDTH</th><th>[36, 28, 15]</th><th>[36, 29, 14]</th><th>[36, 28, 14]</th></tr>
+<tr><td>8</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>10</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>16</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>20</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>32</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>40</td><td>1</td><td>0</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:RX_CLK25_DIVIDER"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_CLK25_DIVIDER"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_CLK25_DIVIDER"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_CLK25_DIVIDER"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_CLK25_DIVIDER"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_CLK25_DIVIDER"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_CLK25_DIVIDER"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_CLK25_DIVIDER"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:RX_CLK25_DIVIDER</th><th>[2, 29, 60]</th><th>[2, 28, 60]</th><th>[2, 29, 59]</th><th>[2, 28, 59]</th><th>[2, 29, 58]</th></tr>
+<tr><th>GTX0:TX_CLK25_DIVIDER</th><th>[4, 28, 31]</th><th>[4, 29, 30]</th><th>[4, 28, 30]</th><th>[4, 29, 29]</th><th>[4, 28, 29]</th></tr>
+<tr><th>GTX1:RX_CLK25_DIVIDER</th><th>[12, 29, 60]</th><th>[12, 28, 60]</th><th>[12, 29, 59]</th><th>[12, 28, 59]</th><th>[12, 29, 58]</th></tr>
+<tr><th>GTX1:TX_CLK25_DIVIDER</th><th>[14, 28, 31]</th><th>[14, 29, 30]</th><th>[14, 28, 30]</th><th>[14, 29, 29]</th><th>[14, 28, 29]</th></tr>
+<tr><th>GTX2:RX_CLK25_DIVIDER</th><th>[22, 29, 60]</th><th>[22, 28, 60]</th><th>[22, 29, 59]</th><th>[22, 28, 59]</th><th>[22, 29, 58]</th></tr>
+<tr><th>GTX2:TX_CLK25_DIVIDER</th><th>[24, 28, 31]</th><th>[24, 29, 30]</th><th>[24, 28, 30]</th><th>[24, 29, 29]</th><th>[24, 28, 29]</th></tr>
+<tr><th>GTX3:RX_CLK25_DIVIDER</th><th>[32, 29, 60]</th><th>[32, 28, 60]</th><th>[32, 29, 59]</th><th>[32, 28, 59]</th><th>[32, 29, 58]</th></tr>
+<tr><th>GTX3:TX_CLK25_DIVIDER</th><th>[34, 28, 31]</th><th>[34, 29, 30]</th><th>[34, 28, 30]</th><th>[34, 29, 29]</th><th>[34, 28, 29]</th></tr>
+<tr><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>2</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>3</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>4</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>5</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>6</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>7</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>8</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>9</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>10</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>11</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>12</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>13</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>14</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>15</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>16</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>17</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>18</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>19</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>20</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>21</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>22</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>23</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>24</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>25</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>26</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>27</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>28</td><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>29</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>30</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>31</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>32</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:RXPLL_COM_CFG"></div>
+<div id="bits-xc6v-GTX-GTX0:TXPLL_COM_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:RXPLL_COM_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:TXPLL_COM_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:RXPLL_COM_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:TXPLL_COM_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:RXPLL_COM_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:TXPLL_COM_CFG"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:RXPLL_COM_CFG</th><th>[3, 29, 19]</th><th>[3, 28, 19]</th><th>[3, 29, 18]</th><th>[3, 28, 18]</th><th>[3, 29, 17]</th><th>[3, 28, 17]</th><th>[3, 29, 16]</th><th>[3, 28, 16]</th><th>[3, 29, 15]</th><th>[3, 28, 15]</th><th>[3, 29, 14]</th><th>[3, 28, 14]</th><th>[3, 29, 13]</th><th>[3, 28, 13]</th><th>[3, 29, 12]</th><th>[3, 28, 12]</th><th>[3, 29, 11]</th><th>[3, 28, 11]</th><th>[3, 29, 10]</th><th>[3, 28, 10]</th><th>[3, 29, 9]</th><th>[3, 28, 9]</th><th>[3, 29, 8]</th><th>[3, 28, 8]</th></tr>
+<tr><th>GTX0:TXPLL_COM_CFG</th><th>[3, 29, 51]</th><th>[3, 28, 51]</th><th>[3, 29, 50]</th><th>[3, 28, 50]</th><th>[3, 29, 49]</th><th>[3, 28, 49]</th><th>[3, 29, 48]</th><th>[3, 28, 48]</th><th>[3, 29, 47]</th><th>[3, 28, 47]</th><th>[3, 29, 46]</th><th>[3, 28, 46]</th><th>[3, 29, 45]</th><th>[3, 28, 45]</th><th>[3, 29, 44]</th><th>[3, 28, 44]</th><th>[3, 29, 43]</th><th>[3, 28, 43]</th><th>[3, 29, 42]</th><th>[3, 28, 42]</th><th>[3, 29, 41]</th><th>[3, 28, 41]</th><th>[3, 29, 40]</th><th>[3, 28, 40]</th></tr>
+<tr><th>GTX1:RXPLL_COM_CFG</th><th>[13, 29, 19]</th><th>[13, 28, 19]</th><th>[13, 29, 18]</th><th>[13, 28, 18]</th><th>[13, 29, 17]</th><th>[13, 28, 17]</th><th>[13, 29, 16]</th><th>[13, 28, 16]</th><th>[13, 29, 15]</th><th>[13, 28, 15]</th><th>[13, 29, 14]</th><th>[13, 28, 14]</th><th>[13, 29, 13]</th><th>[13, 28, 13]</th><th>[13, 29, 12]</th><th>[13, 28, 12]</th><th>[13, 29, 11]</th><th>[13, 28, 11]</th><th>[13, 29, 10]</th><th>[13, 28, 10]</th><th>[13, 29, 9]</th><th>[13, 28, 9]</th><th>[13, 29, 8]</th><th>[13, 28, 8]</th></tr>
+<tr><th>GTX1:TXPLL_COM_CFG</th><th>[13, 29, 51]</th><th>[13, 28, 51]</th><th>[13, 29, 50]</th><th>[13, 28, 50]</th><th>[13, 29, 49]</th><th>[13, 28, 49]</th><th>[13, 29, 48]</th><th>[13, 28, 48]</th><th>[13, 29, 47]</th><th>[13, 28, 47]</th><th>[13, 29, 46]</th><th>[13, 28, 46]</th><th>[13, 29, 45]</th><th>[13, 28, 45]</th><th>[13, 29, 44]</th><th>[13, 28, 44]</th><th>[13, 29, 43]</th><th>[13, 28, 43]</th><th>[13, 29, 42]</th><th>[13, 28, 42]</th><th>[13, 29, 41]</th><th>[13, 28, 41]</th><th>[13, 29, 40]</th><th>[13, 28, 40]</th></tr>
+<tr><th>GTX2:RXPLL_COM_CFG</th><th>[23, 29, 19]</th><th>[23, 28, 19]</th><th>[23, 29, 18]</th><th>[23, 28, 18]</th><th>[23, 29, 17]</th><th>[23, 28, 17]</th><th>[23, 29, 16]</th><th>[23, 28, 16]</th><th>[23, 29, 15]</th><th>[23, 28, 15]</th><th>[23, 29, 14]</th><th>[23, 28, 14]</th><th>[23, 29, 13]</th><th>[23, 28, 13]</th><th>[23, 29, 12]</th><th>[23, 28, 12]</th><th>[23, 29, 11]</th><th>[23, 28, 11]</th><th>[23, 29, 10]</th><th>[23, 28, 10]</th><th>[23, 29, 9]</th><th>[23, 28, 9]</th><th>[23, 29, 8]</th><th>[23, 28, 8]</th></tr>
+<tr><th>GTX2:TXPLL_COM_CFG</th><th>[23, 29, 51]</th><th>[23, 28, 51]</th><th>[23, 29, 50]</th><th>[23, 28, 50]</th><th>[23, 29, 49]</th><th>[23, 28, 49]</th><th>[23, 29, 48]</th><th>[23, 28, 48]</th><th>[23, 29, 47]</th><th>[23, 28, 47]</th><th>[23, 29, 46]</th><th>[23, 28, 46]</th><th>[23, 29, 45]</th><th>[23, 28, 45]</th><th>[23, 29, 44]</th><th>[23, 28, 44]</th><th>[23, 29, 43]</th><th>[23, 28, 43]</th><th>[23, 29, 42]</th><th>[23, 28, 42]</th><th>[23, 29, 41]</th><th>[23, 28, 41]</th><th>[23, 29, 40]</th><th>[23, 28, 40]</th></tr>
+<tr><th>GTX3:RXPLL_COM_CFG</th><th>[33, 29, 19]</th><th>[33, 28, 19]</th><th>[33, 29, 18]</th><th>[33, 28, 18]</th><th>[33, 29, 17]</th><th>[33, 28, 17]</th><th>[33, 29, 16]</th><th>[33, 28, 16]</th><th>[33, 29, 15]</th><th>[33, 28, 15]</th><th>[33, 29, 14]</th><th>[33, 28, 14]</th><th>[33, 29, 13]</th><th>[33, 28, 13]</th><th>[33, 29, 12]</th><th>[33, 28, 12]</th><th>[33, 29, 11]</th><th>[33, 28, 11]</th><th>[33, 29, 10]</th><th>[33, 28, 10]</th><th>[33, 29, 9]</th><th>[33, 28, 9]</th><th>[33, 29, 8]</th><th>[33, 28, 8]</th></tr>
+<tr><th>GTX3:TXPLL_COM_CFG</th><th>[33, 29, 51]</th><th>[33, 28, 51]</th><th>[33, 29, 50]</th><th>[33, 28, 50]</th><th>[33, 29, 49]</th><th>[33, 28, 49]</th><th>[33, 29, 48]</th><th>[33, 28, 48]</th><th>[33, 29, 47]</th><th>[33, 28, 47]</th><th>[33, 29, 46]</th><th>[33, 28, 46]</th><th>[33, 29, 45]</th><th>[33, 28, 45]</th><th>[33, 29, 44]</th><th>[33, 28, 44]</th><th>[33, 29, 43]</th><th>[33, 28, 43]</th><th>[33, 29, 42]</th><th>[33, 28, 42]</th><th>[33, 29, 41]</th><th>[33, 28, 41]</th><th>[33, 29, 40]</th><th>[33, 28, 40]</th></tr>
+<tr><td>Non-inverted</td><td>[23]</td><td>[22]</td><td>[21]</td><td>[20]</td><td>[19]</td><td>[18]</td><td>[17]</td><td>[16]</td><td>[15]</td><td>[14]</td><td>[13]</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:DFE_CFG"></div>
+<div id="bits-xc6v-GTX-GTX0:RXPLL_CP_CFG"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_DLYALIGN_OVRDSETTING"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_EYE_OFFSET"></div>
+<div id="bits-xc6v-GTX-GTX0:TRANS_TIME_NON_P2"></div>
+<div id="bits-xc6v-GTX-GTX0:TRANS_TIME_RATE"></div>
+<div id="bits-xc6v-GTX-GTX0:TXPLL_CP_CFG"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_DLYALIGN_OVRDSETTING"></div>
+<div id="bits-xc6v-GTX-GTX1:DFE_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:RXPLL_CP_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_DLYALIGN_OVRDSETTING"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_EYE_OFFSET"></div>
+<div id="bits-xc6v-GTX-GTX1:TRANS_TIME_NON_P2"></div>
+<div id="bits-xc6v-GTX-GTX1:TRANS_TIME_RATE"></div>
+<div id="bits-xc6v-GTX-GTX1:TXPLL_CP_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_DLYALIGN_OVRDSETTING"></div>
+<div id="bits-xc6v-GTX-GTX2:DFE_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:RXPLL_CP_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_DLYALIGN_OVRDSETTING"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_EYE_OFFSET"></div>
+<div id="bits-xc6v-GTX-GTX2:TRANS_TIME_NON_P2"></div>
+<div id="bits-xc6v-GTX-GTX2:TRANS_TIME_RATE"></div>
+<div id="bits-xc6v-GTX-GTX2:TXPLL_CP_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_DLYALIGN_OVRDSETTING"></div>
+<div id="bits-xc6v-GTX-GTX3:DFE_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:RXPLL_CP_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_DLYALIGN_OVRDSETTING"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_EYE_OFFSET"></div>
+<div id="bits-xc6v-GTX-GTX3:TRANS_TIME_NON_P2"></div>
+<div id="bits-xc6v-GTX-GTX3:TRANS_TIME_RATE"></div>
+<div id="bits-xc6v-GTX-GTX3:TXPLL_CP_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_DLYALIGN_OVRDSETTING"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:DFE_CFG</th><th>[5, 29, 43]</th><th>[5, 28, 43]</th><th>[5, 29, 42]</th><th>[5, 28, 42]</th><th>[5, 29, 41]</th><th>[5, 28, 41]</th><th>[5, 29, 40]</th><th>[5, 28, 40]</th></tr>
+<tr><th>GTX0:RXPLL_CP_CFG</th><th>[3, 29, 23]</th><th>[3, 28, 23]</th><th>[3, 29, 22]</th><th>[3, 28, 22]</th><th>[3, 29, 21]</th><th>[3, 28, 21]</th><th>[3, 29, 20]</th><th>[3, 28, 20]</th></tr>
+<tr><th>GTX0:RX_DLYALIGN_OVRDSETTING</th><th>[9, 29, 47]</th><th>[9, 28, 47]</th><th>[9, 29, 46]</th><th>[9, 28, 46]</th><th>[9, 29, 45]</th><th>[9, 28, 45]</th><th>[9, 29, 44]</th><th>[9, 28, 44]</th></tr>
+<tr><th>GTX0:RX_EYE_OFFSET</th><th>[5, 29, 47]</th><th>[5, 28, 47]</th><th>[5, 29, 46]</th><th>[5, 28, 46]</th><th>[5, 29, 45]</th><th>[5, 28, 45]</th><th>[5, 29, 44]</th><th>[5, 28, 44]</th></tr>
+<tr><th>GTX0:TRANS_TIME_NON_P2</th><th>[4, 29, 43]</th><th>[4, 28, 43]</th><th>[4, 29, 42]</th><th>[4, 28, 42]</th><th>[4, 29, 41]</th><th>[4, 28, 41]</th><th>[4, 29, 40]</th><th>[4, 28, 40]</th></tr>
+<tr><th>GTX0:TRANS_TIME_RATE</th><th>[7, 29, 59]</th><th>[7, 28, 59]</th><th>[7, 29, 58]</th><th>[7, 28, 58]</th><th>[7, 29, 57]</th><th>[7, 28, 57]</th><th>[7, 29, 56]</th><th>[7, 28, 56]</th></tr>
+<tr><th>GTX0:TXPLL_CP_CFG</th><th>[3, 29, 55]</th><th>[3, 28, 55]</th><th>[3, 29, 54]</th><th>[3, 28, 54]</th><th>[3, 29, 53]</th><th>[3, 28, 53]</th><th>[3, 29, 52]</th><th>[3, 28, 52]</th></tr>
+<tr><th>GTX0:TX_DLYALIGN_OVRDSETTING</th><th>[9, 29, 39]</th><th>[9, 28, 39]</th><th>[9, 29, 38]</th><th>[9, 28, 38]</th><th>[9, 29, 37]</th><th>[9, 28, 37]</th><th>[9, 29, 36]</th><th>[9, 28, 36]</th></tr>
+<tr><th>GTX1:DFE_CFG</th><th>[15, 29, 43]</th><th>[15, 28, 43]</th><th>[15, 29, 42]</th><th>[15, 28, 42]</th><th>[15, 29, 41]</th><th>[15, 28, 41]</th><th>[15, 29, 40]</th><th>[15, 28, 40]</th></tr>
+<tr><th>GTX1:RXPLL_CP_CFG</th><th>[13, 29, 23]</th><th>[13, 28, 23]</th><th>[13, 29, 22]</th><th>[13, 28, 22]</th><th>[13, 29, 21]</th><th>[13, 28, 21]</th><th>[13, 29, 20]</th><th>[13, 28, 20]</th></tr>
+<tr><th>GTX1:RX_DLYALIGN_OVRDSETTING</th><th>[19, 29, 47]</th><th>[19, 28, 47]</th><th>[19, 29, 46]</th><th>[19, 28, 46]</th><th>[19, 29, 45]</th><th>[19, 28, 45]</th><th>[19, 29, 44]</th><th>[19, 28, 44]</th></tr>
+<tr><th>GTX1:RX_EYE_OFFSET</th><th>[15, 29, 47]</th><th>[15, 28, 47]</th><th>[15, 29, 46]</th><th>[15, 28, 46]</th><th>[15, 29, 45]</th><th>[15, 28, 45]</th><th>[15, 29, 44]</th><th>[15, 28, 44]</th></tr>
+<tr><th>GTX1:TRANS_TIME_NON_P2</th><th>[14, 29, 43]</th><th>[14, 28, 43]</th><th>[14, 29, 42]</th><th>[14, 28, 42]</th><th>[14, 29, 41]</th><th>[14, 28, 41]</th><th>[14, 29, 40]</th><th>[14, 28, 40]</th></tr>
+<tr><th>GTX1:TRANS_TIME_RATE</th><th>[17, 29, 59]</th><th>[17, 28, 59]</th><th>[17, 29, 58]</th><th>[17, 28, 58]</th><th>[17, 29, 57]</th><th>[17, 28, 57]</th><th>[17, 29, 56]</th><th>[17, 28, 56]</th></tr>
+<tr><th>GTX1:TXPLL_CP_CFG</th><th>[13, 29, 55]</th><th>[13, 28, 55]</th><th>[13, 29, 54]</th><th>[13, 28, 54]</th><th>[13, 29, 53]</th><th>[13, 28, 53]</th><th>[13, 29, 52]</th><th>[13, 28, 52]</th></tr>
+<tr><th>GTX1:TX_DLYALIGN_OVRDSETTING</th><th>[19, 29, 39]</th><th>[19, 28, 39]</th><th>[19, 29, 38]</th><th>[19, 28, 38]</th><th>[19, 29, 37]</th><th>[19, 28, 37]</th><th>[19, 29, 36]</th><th>[19, 28, 36]</th></tr>
+<tr><th>GTX2:DFE_CFG</th><th>[25, 29, 43]</th><th>[25, 28, 43]</th><th>[25, 29, 42]</th><th>[25, 28, 42]</th><th>[25, 29, 41]</th><th>[25, 28, 41]</th><th>[25, 29, 40]</th><th>[25, 28, 40]</th></tr>
+<tr><th>GTX2:RXPLL_CP_CFG</th><th>[23, 29, 23]</th><th>[23, 28, 23]</th><th>[23, 29, 22]</th><th>[23, 28, 22]</th><th>[23, 29, 21]</th><th>[23, 28, 21]</th><th>[23, 29, 20]</th><th>[23, 28, 20]</th></tr>
+<tr><th>GTX2:RX_DLYALIGN_OVRDSETTING</th><th>[29, 29, 47]</th><th>[29, 28, 47]</th><th>[29, 29, 46]</th><th>[29, 28, 46]</th><th>[29, 29, 45]</th><th>[29, 28, 45]</th><th>[29, 29, 44]</th><th>[29, 28, 44]</th></tr>
+<tr><th>GTX2:RX_EYE_OFFSET</th><th>[25, 29, 47]</th><th>[25, 28, 47]</th><th>[25, 29, 46]</th><th>[25, 28, 46]</th><th>[25, 29, 45]</th><th>[25, 28, 45]</th><th>[25, 29, 44]</th><th>[25, 28, 44]</th></tr>
+<tr><th>GTX2:TRANS_TIME_NON_P2</th><th>[24, 29, 43]</th><th>[24, 28, 43]</th><th>[24, 29, 42]</th><th>[24, 28, 42]</th><th>[24, 29, 41]</th><th>[24, 28, 41]</th><th>[24, 29, 40]</th><th>[24, 28, 40]</th></tr>
+<tr><th>GTX2:TRANS_TIME_RATE</th><th>[27, 29, 59]</th><th>[27, 28, 59]</th><th>[27, 29, 58]</th><th>[27, 28, 58]</th><th>[27, 29, 57]</th><th>[27, 28, 57]</th><th>[27, 29, 56]</th><th>[27, 28, 56]</th></tr>
+<tr><th>GTX2:TXPLL_CP_CFG</th><th>[23, 29, 55]</th><th>[23, 28, 55]</th><th>[23, 29, 54]</th><th>[23, 28, 54]</th><th>[23, 29, 53]</th><th>[23, 28, 53]</th><th>[23, 29, 52]</th><th>[23, 28, 52]</th></tr>
+<tr><th>GTX2:TX_DLYALIGN_OVRDSETTING</th><th>[29, 29, 39]</th><th>[29, 28, 39]</th><th>[29, 29, 38]</th><th>[29, 28, 38]</th><th>[29, 29, 37]</th><th>[29, 28, 37]</th><th>[29, 29, 36]</th><th>[29, 28, 36]</th></tr>
+<tr><th>GTX3:DFE_CFG</th><th>[35, 29, 43]</th><th>[35, 28, 43]</th><th>[35, 29, 42]</th><th>[35, 28, 42]</th><th>[35, 29, 41]</th><th>[35, 28, 41]</th><th>[35, 29, 40]</th><th>[35, 28, 40]</th></tr>
+<tr><th>GTX3:RXPLL_CP_CFG</th><th>[33, 29, 23]</th><th>[33, 28, 23]</th><th>[33, 29, 22]</th><th>[33, 28, 22]</th><th>[33, 29, 21]</th><th>[33, 28, 21]</th><th>[33, 29, 20]</th><th>[33, 28, 20]</th></tr>
+<tr><th>GTX3:RX_DLYALIGN_OVRDSETTING</th><th>[39, 29, 47]</th><th>[39, 28, 47]</th><th>[39, 29, 46]</th><th>[39, 28, 46]</th><th>[39, 29, 45]</th><th>[39, 28, 45]</th><th>[39, 29, 44]</th><th>[39, 28, 44]</th></tr>
+<tr><th>GTX3:RX_EYE_OFFSET</th><th>[35, 29, 47]</th><th>[35, 28, 47]</th><th>[35, 29, 46]</th><th>[35, 28, 46]</th><th>[35, 29, 45]</th><th>[35, 28, 45]</th><th>[35, 29, 44]</th><th>[35, 28, 44]</th></tr>
+<tr><th>GTX3:TRANS_TIME_NON_P2</th><th>[34, 29, 43]</th><th>[34, 28, 43]</th><th>[34, 29, 42]</th><th>[34, 28, 42]</th><th>[34, 29, 41]</th><th>[34, 28, 41]</th><th>[34, 29, 40]</th><th>[34, 28, 40]</th></tr>
+<tr><th>GTX3:TRANS_TIME_RATE</th><th>[37, 29, 59]</th><th>[37, 28, 59]</th><th>[37, 29, 58]</th><th>[37, 28, 58]</th><th>[37, 29, 57]</th><th>[37, 28, 57]</th><th>[37, 29, 56]</th><th>[37, 28, 56]</th></tr>
+<tr><th>GTX3:TXPLL_CP_CFG</th><th>[33, 29, 55]</th><th>[33, 28, 55]</th><th>[33, 29, 54]</th><th>[33, 28, 54]</th><th>[33, 29, 53]</th><th>[33, 28, 53]</th><th>[33, 29, 52]</th><th>[33, 28, 52]</th></tr>
+<tr><th>GTX3:TX_DLYALIGN_OVRDSETTING</th><th>[39, 29, 39]</th><th>[39, 28, 39]</th><th>[39, 29, 38]</th><th>[39, 28, 38]</th><th>[39, 29, 37]</th><th>[39, 28, 37]</th><th>[39, 29, 36]</th><th>[39, 28, 36]</th></tr>
+<tr><td>Non-inverted</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:RXPLL_DIVSEL45_FB"></div>
+<div id="bits-xc6v-GTX-GTX0:TXPLL_DIVSEL45_FB"></div>
+<div id="bits-xc6v-GTX-GTX1:RXPLL_DIVSEL45_FB"></div>
+<div id="bits-xc6v-GTX-GTX1:TXPLL_DIVSEL45_FB"></div>
+<div id="bits-xc6v-GTX-GTX2:RXPLL_DIVSEL45_FB"></div>
+<div id="bits-xc6v-GTX-GTX2:TXPLL_DIVSEL45_FB"></div>
+<div id="bits-xc6v-GTX-GTX3:RXPLL_DIVSEL45_FB"></div>
+<div id="bits-xc6v-GTX-GTX3:TXPLL_DIVSEL45_FB"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:RXPLL_DIVSEL45_FB</th><th>[3, 28, 27]</th></tr>
+<tr><th>GTX0:TXPLL_DIVSEL45_FB</th><th>[3, 28, 59]</th></tr>
+<tr><th>GTX1:RXPLL_DIVSEL45_FB</th><th>[13, 28, 27]</th></tr>
+<tr><th>GTX1:TXPLL_DIVSEL45_FB</th><th>[13, 28, 59]</th></tr>
+<tr><th>GTX2:RXPLL_DIVSEL45_FB</th><th>[23, 28, 27]</th></tr>
+<tr><th>GTX2:TXPLL_DIVSEL45_FB</th><th>[23, 28, 59]</th></tr>
+<tr><th>GTX3:RXPLL_DIVSEL45_FB</th><th>[33, 28, 27]</th></tr>
+<tr><th>GTX3:TXPLL_DIVSEL45_FB</th><th>[33, 28, 59]</th></tr>
+<tr><td>4</td><td>0</td></tr>
+<tr><td>5</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:RXPLL_DIVSEL_OUT"></div>
+<div id="bits-xc6v-GTX-GTX0:TXPLL_DIVSEL_OUT"></div>
+<div id="bits-xc6v-GTX-GTX1:RXPLL_DIVSEL_OUT"></div>
+<div id="bits-xc6v-GTX-GTX1:TXPLL_DIVSEL_OUT"></div>
+<div id="bits-xc6v-GTX-GTX2:RXPLL_DIVSEL_OUT"></div>
+<div id="bits-xc6v-GTX-GTX2:TXPLL_DIVSEL_OUT"></div>
+<div id="bits-xc6v-GTX-GTX3:RXPLL_DIVSEL_OUT"></div>
+<div id="bits-xc6v-GTX-GTX3:TXPLL_DIVSEL_OUT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:RXPLL_DIVSEL_OUT</th><th>[3, 29, 31]</th><th>[3, 28, 31]</th></tr>
+<tr><th>GTX0:TXPLL_DIVSEL_OUT</th><th>[3, 29, 63]</th><th>[3, 28, 63]</th></tr>
+<tr><th>GTX1:RXPLL_DIVSEL_OUT</th><th>[13, 29, 31]</th><th>[13, 28, 31]</th></tr>
+<tr><th>GTX1:TXPLL_DIVSEL_OUT</th><th>[13, 29, 63]</th><th>[13, 28, 63]</th></tr>
+<tr><th>GTX2:RXPLL_DIVSEL_OUT</th><th>[23, 29, 31]</th><th>[23, 28, 31]</th></tr>
+<tr><th>GTX2:TXPLL_DIVSEL_OUT</th><th>[23, 29, 63]</th><th>[23, 28, 63]</th></tr>
+<tr><th>GTX3:RXPLL_DIVSEL_OUT</th><th>[33, 29, 31]</th><th>[33, 28, 31]</th></tr>
+<tr><th>GTX3:TXPLL_DIVSEL_OUT</th><th>[33, 29, 63]</th><th>[33, 28, 63]</th></tr>
+<tr><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>2</td><td>0</td><td>1</td></tr>
+<tr><td>4</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:RXPLLREFSEL_TESTCLK"></div>
+<div id="bits-xc6v-GTX-GTX0:TXPLLREFSEL_TESTCLK"></div>
+<div id="bits-xc6v-GTX-GTX1:RXPLLREFSEL_TESTCLK"></div>
+<div id="bits-xc6v-GTX-GTX1:TXPLLREFSEL_TESTCLK"></div>
+<div id="bits-xc6v-GTX-GTX2:RXPLLREFSEL_TESTCLK"></div>
+<div id="bits-xc6v-GTX-GTX2:TXPLLREFSEL_TESTCLK"></div>
+<div id="bits-xc6v-GTX-GTX3:RXPLLREFSEL_TESTCLK"></div>
+<div id="bits-xc6v-GTX-GTX3:TXPLLREFSEL_TESTCLK"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:RXPLLREFSEL_TESTCLK</th><th>[3, 28, 32]</th></tr>
+<tr><th>GTX0:TXPLLREFSEL_TESTCLK</th><th>[4, 28, 0]</th></tr>
+<tr><th>GTX1:RXPLLREFSEL_TESTCLK</th><th>[13, 28, 32]</th></tr>
+<tr><th>GTX1:TXPLLREFSEL_TESTCLK</th><th>[14, 28, 0]</th></tr>
+<tr><th>GTX2:RXPLLREFSEL_TESTCLK</th><th>[23, 28, 32]</th></tr>
+<tr><th>GTX2:TXPLLREFSEL_TESTCLK</th><th>[24, 28, 0]</th></tr>
+<tr><th>GTX3:RXPLLREFSEL_TESTCLK</th><th>[33, 28, 32]</th></tr>
+<tr><th>GTX3:TXPLLREFSEL_TESTCLK</th><th>[34, 28, 0]</th></tr>
+<tr><td>GREFCLK</td><td>0</td></tr>
+<tr><td>PERFCLK</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:RXPLLREFSEL_MODE"></div>
+<div id="bits-xc6v-GTX-GTX0:TXPLLREFSEL_MODE"></div>
+<div id="bits-xc6v-GTX-GTX1:RXPLLREFSEL_MODE"></div>
+<div id="bits-xc6v-GTX-GTX1:TXPLLREFSEL_MODE"></div>
+<div id="bits-xc6v-GTX-GTX2:RXPLLREFSEL_MODE"></div>
+<div id="bits-xc6v-GTX-GTX2:TXPLLREFSEL_MODE"></div>
+<div id="bits-xc6v-GTX-GTX3:RXPLLREFSEL_MODE"></div>
+<div id="bits-xc6v-GTX-GTX3:TXPLLREFSEL_MODE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:RXPLLREFSEL_MODE</th><th>[3, 28, 35]</th></tr>
+<tr><th>GTX0:TXPLLREFSEL_MODE</th><th>[4, 28, 3]</th></tr>
+<tr><th>GTX1:RXPLLREFSEL_MODE</th><th>[13, 28, 35]</th></tr>
+<tr><th>GTX1:TXPLLREFSEL_MODE</th><th>[14, 28, 3]</th></tr>
+<tr><th>GTX2:RXPLLREFSEL_MODE</th><th>[23, 28, 35]</th></tr>
+<tr><th>GTX2:TXPLLREFSEL_MODE</th><th>[24, 28, 3]</th></tr>
+<tr><th>GTX3:RXPLLREFSEL_MODE</th><th>[33, 28, 35]</th></tr>
+<tr><th>GTX3:TXPLLREFSEL_MODE</th><th>[34, 28, 3]</th></tr>
+<tr><td>STATIC</td><td>0</td></tr>
+<tr><td>DYNAMIC</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:TX_CLK_SOURCE"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_CLK_SOURCE"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_CLK_SOURCE"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_CLK_SOURCE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:TX_CLK_SOURCE</th><th>[3, 28, 60]</th></tr>
+<tr><th>GTX1:TX_CLK_SOURCE</th><th>[13, 28, 60]</th></tr>
+<tr><th>GTX2:TX_CLK_SOURCE</th><th>[23, 28, 60]</th></tr>
+<tr><th>GTX3:TX_CLK_SOURCE</th><th>[33, 28, 60]</th></tr>
+<tr><td>TXPLL</td><td>0</td></tr>
+<tr><td>RXPLL</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:RXPLL_DIVSEL_FB"></div>
+<div id="bits-xc6v-GTX-GTX0:RXPLL_DIVSEL_REF"></div>
+<div id="bits-xc6v-GTX-GTX0:TXPLL_DIVSEL_FB"></div>
+<div id="bits-xc6v-GTX-GTX0:TXPLL_DIVSEL_REF"></div>
+<div id="bits-xc6v-GTX-GTX1:RXPLL_DIVSEL_FB"></div>
+<div id="bits-xc6v-GTX-GTX1:RXPLL_DIVSEL_REF"></div>
+<div id="bits-xc6v-GTX-GTX1:TXPLL_DIVSEL_FB"></div>
+<div id="bits-xc6v-GTX-GTX1:TXPLL_DIVSEL_REF"></div>
+<div id="bits-xc6v-GTX-GTX2:RXPLL_DIVSEL_FB"></div>
+<div id="bits-xc6v-GTX-GTX2:RXPLL_DIVSEL_REF"></div>
+<div id="bits-xc6v-GTX-GTX2:TXPLL_DIVSEL_FB"></div>
+<div id="bits-xc6v-GTX-GTX2:TXPLL_DIVSEL_REF"></div>
+<div id="bits-xc6v-GTX-GTX3:RXPLL_DIVSEL_FB"></div>
+<div id="bits-xc6v-GTX-GTX3:RXPLL_DIVSEL_REF"></div>
+<div id="bits-xc6v-GTX-GTX3:TXPLL_DIVSEL_FB"></div>
+<div id="bits-xc6v-GTX-GTX3:TXPLL_DIVSEL_REF"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:RXPLL_DIVSEL_FB</th><th>[3, 28, 26]</th><th>[3, 29, 25]</th><th>[3, 28, 25]</th><th>[3, 29, 24]</th><th>[3, 29, 26]</th></tr>
+<tr><th>GTX0:RXPLL_DIVSEL_REF</th><th>[3, 28, 34]</th><th>[3, 29, 33]</th><th>[3, 28, 33]</th><th>[3, 29, 32]</th><th>[3, 29, 34]</th></tr>
+<tr><th>GTX0:TXPLL_DIVSEL_FB</th><th>[3, 28, 58]</th><th>[3, 29, 57]</th><th>[3, 28, 57]</th><th>[3, 29, 56]</th><th>[3, 29, 58]</th></tr>
+<tr><th>GTX0:TXPLL_DIVSEL_REF</th><th>[4, 28, 2]</th><th>[4, 29, 1]</th><th>[4, 28, 1]</th><th>[4, 29, 0]</th><th>[4, 29, 2]</th></tr>
+<tr><th>GTX1:RXPLL_DIVSEL_FB</th><th>[13, 28, 26]</th><th>[13, 29, 25]</th><th>[13, 28, 25]</th><th>[13, 29, 24]</th><th>[13, 29, 26]</th></tr>
+<tr><th>GTX1:RXPLL_DIVSEL_REF</th><th>[13, 28, 34]</th><th>[13, 29, 33]</th><th>[13, 28, 33]</th><th>[13, 29, 32]</th><th>[13, 29, 34]</th></tr>
+<tr><th>GTX1:TXPLL_DIVSEL_FB</th><th>[13, 28, 58]</th><th>[13, 29, 57]</th><th>[13, 28, 57]</th><th>[13, 29, 56]</th><th>[13, 29, 58]</th></tr>
+<tr><th>GTX1:TXPLL_DIVSEL_REF</th><th>[14, 28, 2]</th><th>[14, 29, 1]</th><th>[14, 28, 1]</th><th>[14, 29, 0]</th><th>[14, 29, 2]</th></tr>
+<tr><th>GTX2:RXPLL_DIVSEL_FB</th><th>[23, 28, 26]</th><th>[23, 29, 25]</th><th>[23, 28, 25]</th><th>[23, 29, 24]</th><th>[23, 29, 26]</th></tr>
+<tr><th>GTX2:RXPLL_DIVSEL_REF</th><th>[23, 28, 34]</th><th>[23, 29, 33]</th><th>[23, 28, 33]</th><th>[23, 29, 32]</th><th>[23, 29, 34]</th></tr>
+<tr><th>GTX2:TXPLL_DIVSEL_FB</th><th>[23, 28, 58]</th><th>[23, 29, 57]</th><th>[23, 28, 57]</th><th>[23, 29, 56]</th><th>[23, 29, 58]</th></tr>
+<tr><th>GTX2:TXPLL_DIVSEL_REF</th><th>[24, 28, 2]</th><th>[24, 29, 1]</th><th>[24, 28, 1]</th><th>[24, 29, 0]</th><th>[24, 29, 2]</th></tr>
+<tr><th>GTX3:RXPLL_DIVSEL_FB</th><th>[33, 28, 26]</th><th>[33, 29, 25]</th><th>[33, 28, 25]</th><th>[33, 29, 24]</th><th>[33, 29, 26]</th></tr>
+<tr><th>GTX3:RXPLL_DIVSEL_REF</th><th>[33, 28, 34]</th><th>[33, 29, 33]</th><th>[33, 28, 33]</th><th>[33, 29, 32]</th><th>[33, 29, 34]</th></tr>
+<tr><th>GTX3:TXPLL_DIVSEL_FB</th><th>[33, 28, 58]</th><th>[33, 29, 57]</th><th>[33, 28, 57]</th><th>[33, 29, 56]</th><th>[33, 29, 58]</th></tr>
+<tr><th>GTX3:TXPLL_DIVSEL_REF</th><th>[34, 28, 2]</th><th>[34, 29, 1]</th><th>[34, 28, 1]</th><th>[34, 29, 0]</th><th>[34, 29, 2]</th></tr>
+<tr><td>2</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>3</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>4</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>5</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>6</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>8</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>10</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>12</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>16</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>20</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:A_RXPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX0:A_TXPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX0:BGTEST_CFG"></div>
+<div id="bits-xc6v-GTX-GTX0:CM_TRIM"></div>
+<div id="bits-xc6v-GTX-GTX0:RX_EYE_SCANMODE"></div>
+<div id="bits-xc6v-GTX-GTX0:TXPLL_SATA"></div>
+<div id="bits-xc6v-GTX-GTX0:TX_TDCC_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:A_RXPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX1:A_TXPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX1:BGTEST_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:CM_TRIM"></div>
+<div id="bits-xc6v-GTX-GTX1:RX_EYE_SCANMODE"></div>
+<div id="bits-xc6v-GTX-GTX1:TXPLL_SATA"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_TDCC_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:A_RXPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX2:A_TXPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX2:BGTEST_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:CM_TRIM"></div>
+<div id="bits-xc6v-GTX-GTX2:RX_EYE_SCANMODE"></div>
+<div id="bits-xc6v-GTX-GTX2:TXPLL_SATA"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_TDCC_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:A_RXPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX3:A_TXPOWERDOWN"></div>
+<div id="bits-xc6v-GTX-GTX3:BGTEST_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:CM_TRIM"></div>
+<div id="bits-xc6v-GTX-GTX3:RX_EYE_SCANMODE"></div>
+<div id="bits-xc6v-GTX-GTX3:TXPLL_SATA"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_TDCC_CFG"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:A_RXPOWERDOWN</th><th>[3, 28, 29]</th><th>[3, 29, 28]</th></tr>
+<tr><th>GTX0:A_TXPOWERDOWN</th><th>[3, 28, 61]</th><th>[3, 29, 60]</th></tr>
+<tr><th>GTX0:BGTEST_CFG</th><th>[4, 29, 55]</th><th>[4, 28, 55]</th></tr>
+<tr><th>GTX0:CM_TRIM</th><th>[4, 29, 44]</th><th>[4, 28, 44]</th></tr>
+<tr><th>GTX0:RX_EYE_SCANMODE</th><th>[5, 28, 53]</th><th>[5, 29, 52]</th></tr>
+<tr><th>GTX0:TXPLL_SATA</th><th>[4, 29, 54]</th><th>[4, 28, 54]</th></tr>
+<tr><th>GTX0:TX_TDCC_CFG</th><th>[7, 29, 15]</th><th>[7, 28, 15]</th></tr>
+<tr><th>GTX1:A_RXPOWERDOWN</th><th>[13, 28, 29]</th><th>[13, 29, 28]</th></tr>
+<tr><th>GTX1:A_TXPOWERDOWN</th><th>[13, 28, 61]</th><th>[13, 29, 60]</th></tr>
+<tr><th>GTX1:BGTEST_CFG</th><th>[14, 29, 55]</th><th>[14, 28, 55]</th></tr>
+<tr><th>GTX1:CM_TRIM</th><th>[14, 29, 44]</th><th>[14, 28, 44]</th></tr>
+<tr><th>GTX1:RX_EYE_SCANMODE</th><th>[15, 28, 53]</th><th>[15, 29, 52]</th></tr>
+<tr><th>GTX1:TXPLL_SATA</th><th>[14, 29, 54]</th><th>[14, 28, 54]</th></tr>
+<tr><th>GTX1:TX_TDCC_CFG</th><th>[17, 29, 15]</th><th>[17, 28, 15]</th></tr>
+<tr><th>GTX2:A_RXPOWERDOWN</th><th>[23, 28, 29]</th><th>[23, 29, 28]</th></tr>
+<tr><th>GTX2:A_TXPOWERDOWN</th><th>[23, 28, 61]</th><th>[23, 29, 60]</th></tr>
+<tr><th>GTX2:BGTEST_CFG</th><th>[24, 29, 55]</th><th>[24, 28, 55]</th></tr>
+<tr><th>GTX2:CM_TRIM</th><th>[24, 29, 44]</th><th>[24, 28, 44]</th></tr>
+<tr><th>GTX2:RX_EYE_SCANMODE</th><th>[25, 28, 53]</th><th>[25, 29, 52]</th></tr>
+<tr><th>GTX2:TXPLL_SATA</th><th>[24, 29, 54]</th><th>[24, 28, 54]</th></tr>
+<tr><th>GTX2:TX_TDCC_CFG</th><th>[27, 29, 15]</th><th>[27, 28, 15]</th></tr>
+<tr><th>GTX3:A_RXPOWERDOWN</th><th>[33, 28, 29]</th><th>[33, 29, 28]</th></tr>
+<tr><th>GTX3:A_TXPOWERDOWN</th><th>[33, 28, 61]</th><th>[33, 29, 60]</th></tr>
+<tr><th>GTX3:BGTEST_CFG</th><th>[34, 29, 55]</th><th>[34, 28, 55]</th></tr>
+<tr><th>GTX3:CM_TRIM</th><th>[34, 29, 44]</th><th>[34, 28, 44]</th></tr>
+<tr><th>GTX3:RX_EYE_SCANMODE</th><th>[35, 28, 53]</th><th>[35, 29, 52]</th></tr>
+<tr><th>GTX3:TXPLL_SATA</th><th>[34, 29, 54]</th><th>[34, 28, 54]</th></tr>
+<tr><th>GTX3:TX_TDCC_CFG</th><th>[37, 29, 15]</th><th>[37, 28, 15]</th></tr>
+<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:RXPLLREFSEL_STATIC"></div>
+<div id="bits-xc6v-GTX-GTX0:TXPLLREFSEL_STATIC"></div>
+<div id="bits-xc6v-GTX-GTX1:RXPLLREFSEL_STATIC"></div>
+<div id="bits-xc6v-GTX-GTX1:TXPLLREFSEL_STATIC"></div>
+<div id="bits-xc6v-GTX-GTX2:RXPLLREFSEL_STATIC"></div>
+<div id="bits-xc6v-GTX-GTX2:TXPLLREFSEL_STATIC"></div>
+<div id="bits-xc6v-GTX-GTX3:RXPLLREFSEL_STATIC"></div>
+<div id="bits-xc6v-GTX-GTX3:TXPLLREFSEL_STATIC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:RXPLLREFSEL_STATIC</th><th>[3, 29, 36]</th><th>[3, 28, 36]</th><th>[3, 29, 35]</th></tr>
+<tr><th>GTX0:TXPLLREFSEL_STATIC</th><th>[4, 29, 4]</th><th>[4, 28, 4]</th><th>[4, 29, 3]</th></tr>
+<tr><th>GTX1:RXPLLREFSEL_STATIC</th><th>[13, 29, 36]</th><th>[13, 28, 36]</th><th>[13, 29, 35]</th></tr>
+<tr><th>GTX1:TXPLLREFSEL_STATIC</th><th>[14, 29, 4]</th><th>[14, 28, 4]</th><th>[14, 29, 3]</th></tr>
+<tr><th>GTX2:RXPLLREFSEL_STATIC</th><th>[23, 29, 36]</th><th>[23, 28, 36]</th><th>[23, 29, 35]</th></tr>
+<tr><th>GTX2:TXPLLREFSEL_STATIC</th><th>[24, 29, 4]</th><th>[24, 28, 4]</th><th>[24, 29, 3]</th></tr>
+<tr><th>GTX3:RXPLLREFSEL_STATIC</th><th>[33, 29, 36]</th><th>[33, 28, 36]</th><th>[33, 29, 35]</th></tr>
+<tr><th>GTX3:TXPLLREFSEL_STATIC</th><th>[34, 29, 4]</th><th>[34, 28, 4]</th><th>[34, 29, 3]</th></tr>
+<tr><td>MGTREFCLK0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>MGTREFCLK1</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>NORTHREFCLK0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>NORTHREFCLK1</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>SOUTHREFCLK0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>SOUTHREFCLK1</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>CAS_CLK</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>TESTCLK</td><td>1</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:TX_DETECT_RX_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_DETECT_RX_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_DETECT_RX_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_DETECT_RX_CFG"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:TX_DETECT_RX_CFG</th><th>[4, 29, 14]</th><th>[4, 28, 14]</th><th>[4, 29, 13]</th><th>[4, 28, 13]</th><th>[4, 29, 12]</th><th>[4, 28, 12]</th><th>[4, 29, 11]</th><th>[4, 28, 11]</th><th>[4, 29, 10]</th><th>[4, 28, 10]</th><th>[4, 29, 9]</th><th>[4, 28, 9]</th><th>[4, 29, 8]</th><th>[4, 28, 8]</th></tr>
+<tr><th>GTX1:TX_DETECT_RX_CFG</th><th>[14, 29, 14]</th><th>[14, 28, 14]</th><th>[14, 29, 13]</th><th>[14, 28, 13]</th><th>[14, 29, 12]</th><th>[14, 28, 12]</th><th>[14, 29, 11]</th><th>[14, 28, 11]</th><th>[14, 29, 10]</th><th>[14, 28, 10]</th><th>[14, 29, 9]</th><th>[14, 28, 9]</th><th>[14, 29, 8]</th><th>[14, 28, 8]</th></tr>
+<tr><th>GTX2:TX_DETECT_RX_CFG</th><th>[24, 29, 14]</th><th>[24, 28, 14]</th><th>[24, 29, 13]</th><th>[24, 28, 13]</th><th>[24, 29, 12]</th><th>[24, 28, 12]</th><th>[24, 29, 11]</th><th>[24, 28, 11]</th><th>[24, 29, 10]</th><th>[24, 28, 10]</th><th>[24, 29, 9]</th><th>[24, 28, 9]</th><th>[24, 29, 8]</th><th>[24, 28, 8]</th></tr>
+<tr><th>GTX3:TX_DETECT_RX_CFG</th><th>[34, 29, 14]</th><th>[34, 28, 14]</th><th>[34, 29, 13]</th><th>[34, 28, 13]</th><th>[34, 29, 12]</th><th>[34, 28, 12]</th><th>[34, 29, 11]</th><th>[34, 28, 11]</th><th>[34, 29, 10]</th><th>[34, 28, 10]</th><th>[34, 29, 9]</th><th>[34, 28, 9]</th><th>[34, 29, 8]</th><th>[34, 28, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[13]</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:TRANS_TIME_FROM_P2"></div>
+<div id="bits-xc6v-GTX-GTX1:TRANS_TIME_FROM_P2"></div>
+<div id="bits-xc6v-GTX-GTX2:TRANS_TIME_FROM_P2"></div>
+<div id="bits-xc6v-GTX-GTX3:TRANS_TIME_FROM_P2"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:TRANS_TIME_FROM_P2</th><th>[4, 29, 37]</th><th>[4, 28, 37]</th><th>[4, 29, 36]</th><th>[4, 28, 36]</th><th>[4, 29, 35]</th><th>[4, 28, 35]</th><th>[4, 29, 34]</th><th>[4, 28, 34]</th><th>[4, 29, 33]</th><th>[4, 28, 33]</th><th>[4, 29, 32]</th><th>[4, 28, 32]</th></tr>
+<tr><th>GTX1:TRANS_TIME_FROM_P2</th><th>[14, 29, 37]</th><th>[14, 28, 37]</th><th>[14, 29, 36]</th><th>[14, 28, 36]</th><th>[14, 29, 35]</th><th>[14, 28, 35]</th><th>[14, 29, 34]</th><th>[14, 28, 34]</th><th>[14, 29, 33]</th><th>[14, 28, 33]</th><th>[14, 29, 32]</th><th>[14, 28, 32]</th></tr>
+<tr><th>GTX2:TRANS_TIME_FROM_P2</th><th>[24, 29, 37]</th><th>[24, 28, 37]</th><th>[24, 29, 36]</th><th>[24, 28, 36]</th><th>[24, 29, 35]</th><th>[24, 28, 35]</th><th>[24, 29, 34]</th><th>[24, 28, 34]</th><th>[24, 29, 33]</th><th>[24, 28, 33]</th><th>[24, 29, 32]</th><th>[24, 28, 32]</th></tr>
+<tr><th>GTX3:TRANS_TIME_FROM_P2</th><th>[34, 29, 37]</th><th>[34, 28, 37]</th><th>[34, 29, 36]</th><th>[34, 28, 36]</th><th>[34, 29, 35]</th><th>[34, 28, 35]</th><th>[34, 29, 34]</th><th>[34, 28, 34]</th><th>[34, 29, 33]</th><th>[34, 28, 33]</th><th>[34, 29, 32]</th><th>[34, 28, 32]</th></tr>
+<tr><td>Non-inverted</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:TX_XCLK_SEL"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_XCLK_SEL"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_XCLK_SEL"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_XCLK_SEL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:TX_XCLK_SEL</th><th>[5, 28, 63]</th></tr>
+<tr><th>GTX1:TX_XCLK_SEL</th><th>[15, 28, 63]</th></tr>
+<tr><th>GTX2:TX_XCLK_SEL</th><th>[25, 28, 63]</th></tr>
+<tr><th>GTX3:TX_XCLK_SEL</th><th>[35, 28, 63]</th></tr>
+<tr><td>TXOUT</td><td>0</td></tr>
+<tr><td>TXUSR</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:PMA_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:PMA_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:PMA_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:PMA_CFG"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:PMA_CFG</th><th>[6, 29, 55]</th><th>[6, 28, 55]</th><th>[6, 29, 54]</th><th>[6, 28, 54]</th><th>[6, 29, 53]</th><th>[6, 28, 53]</th><th>[6, 29, 52]</th><th>[6, 28, 52]</th><th>[6, 29, 51]</th><th>[6, 28, 51]</th><th>[6, 29, 50]</th><th>[6, 28, 50]</th><th>[6, 29, 47]</th><th>[6, 28, 47]</th><th>[6, 29, 46]</th><th>[6, 28, 46]</th><th>[6, 29, 45]</th><th>[6, 28, 45]</th><th>[6, 29, 44]</th><th>[6, 28, 44]</th><th>[6, 29, 43]</th><th>[6, 28, 43]</th><th>[6, 29, 42]</th><th>[6, 28, 42]</th><th>[6, 29, 41]</th><th>[6, 28, 41]</th><th>[6, 29, 40]</th><th>[6, 28, 40]</th><th>[6, 29, 39]</th><th>[6, 28, 39]</th><th>[6, 29, 38]</th><th>[6, 28, 38]</th><th>[6, 29, 37]</th><th>[6, 28, 37]</th><th>[6, 29, 36]</th><th>[6, 28, 36]</th><th>[6, 29, 35]</th><th>[6, 28, 35]</th><th>[6, 29, 34]</th><th>[6, 28, 34]</th><th>[6, 29, 33]</th><th>[6, 28, 33]</th><th>[6, 29, 32]</th><th>[6, 28, 32]</th><th>[6, 29, 31]</th><th>[6, 28, 31]</th><th>[6, 29, 30]</th><th>[6, 28, 30]</th><th>[6, 29, 29]</th><th>[6, 28, 29]</th><th>[6, 29, 28]</th><th>[6, 28, 28]</th><th>[6, 29, 27]</th><th>[6, 28, 27]</th><th>[6, 29, 26]</th><th>[6, 28, 26]</th><th>[6, 29, 25]</th><th>[6, 28, 25]</th><th>[6, 29, 24]</th><th>[6, 28, 24]</th><th>[6, 29, 23]</th><th>[6, 28, 23]</th><th>[6, 29, 22]</th><th>[6, 28, 22]</th><th>[6, 29, 21]</th><th>[6, 28, 21]</th><th>[6, 29, 20]</th><th>[6, 28, 20]</th><th>[6, 29, 19]</th><th>[6, 28, 19]</th><th>[6, 29, 18]</th><th>[6, 28, 18]</th><th>[6, 29, 17]</th><th>[6, 28, 17]</th><th>[6, 29, 16]</th><th>[6, 28, 16]</th></tr>
+<tr><th>GTX1:PMA_CFG</th><th>[16, 29, 55]</th><th>[16, 28, 55]</th><th>[16, 29, 54]</th><th>[16, 28, 54]</th><th>[16, 29, 53]</th><th>[16, 28, 53]</th><th>[16, 29, 52]</th><th>[16, 28, 52]</th><th>[16, 29, 51]</th><th>[16, 28, 51]</th><th>[16, 29, 50]</th><th>[16, 28, 50]</th><th>[16, 29, 47]</th><th>[16, 28, 47]</th><th>[16, 29, 46]</th><th>[16, 28, 46]</th><th>[16, 29, 45]</th><th>[16, 28, 45]</th><th>[16, 29, 44]</th><th>[16, 28, 44]</th><th>[16, 29, 43]</th><th>[16, 28, 43]</th><th>[16, 29, 42]</th><th>[16, 28, 42]</th><th>[16, 29, 41]</th><th>[16, 28, 41]</th><th>[16, 29, 40]</th><th>[16, 28, 40]</th><th>[16, 29, 39]</th><th>[16, 28, 39]</th><th>[16, 29, 38]</th><th>[16, 28, 38]</th><th>[16, 29, 37]</th><th>[16, 28, 37]</th><th>[16, 29, 36]</th><th>[16, 28, 36]</th><th>[16, 29, 35]</th><th>[16, 28, 35]</th><th>[16, 29, 34]</th><th>[16, 28, 34]</th><th>[16, 29, 33]</th><th>[16, 28, 33]</th><th>[16, 29, 32]</th><th>[16, 28, 32]</th><th>[16, 29, 31]</th><th>[16, 28, 31]</th><th>[16, 29, 30]</th><th>[16, 28, 30]</th><th>[16, 29, 29]</th><th>[16, 28, 29]</th><th>[16, 29, 28]</th><th>[16, 28, 28]</th><th>[16, 29, 27]</th><th>[16, 28, 27]</th><th>[16, 29, 26]</th><th>[16, 28, 26]</th><th>[16, 29, 25]</th><th>[16, 28, 25]</th><th>[16, 29, 24]</th><th>[16, 28, 24]</th><th>[16, 29, 23]</th><th>[16, 28, 23]</th><th>[16, 29, 22]</th><th>[16, 28, 22]</th><th>[16, 29, 21]</th><th>[16, 28, 21]</th><th>[16, 29, 20]</th><th>[16, 28, 20]</th><th>[16, 29, 19]</th><th>[16, 28, 19]</th><th>[16, 29, 18]</th><th>[16, 28, 18]</th><th>[16, 29, 17]</th><th>[16, 28, 17]</th><th>[16, 29, 16]</th><th>[16, 28, 16]</th></tr>
+<tr><th>GTX2:PMA_CFG</th><th>[26, 29, 55]</th><th>[26, 28, 55]</th><th>[26, 29, 54]</th><th>[26, 28, 54]</th><th>[26, 29, 53]</th><th>[26, 28, 53]</th><th>[26, 29, 52]</th><th>[26, 28, 52]</th><th>[26, 29, 51]</th><th>[26, 28, 51]</th><th>[26, 29, 50]</th><th>[26, 28, 50]</th><th>[26, 29, 47]</th><th>[26, 28, 47]</th><th>[26, 29, 46]</th><th>[26, 28, 46]</th><th>[26, 29, 45]</th><th>[26, 28, 45]</th><th>[26, 29, 44]</th><th>[26, 28, 44]</th><th>[26, 29, 43]</th><th>[26, 28, 43]</th><th>[26, 29, 42]</th><th>[26, 28, 42]</th><th>[26, 29, 41]</th><th>[26, 28, 41]</th><th>[26, 29, 40]</th><th>[26, 28, 40]</th><th>[26, 29, 39]</th><th>[26, 28, 39]</th><th>[26, 29, 38]</th><th>[26, 28, 38]</th><th>[26, 29, 37]</th><th>[26, 28, 37]</th><th>[26, 29, 36]</th><th>[26, 28, 36]</th><th>[26, 29, 35]</th><th>[26, 28, 35]</th><th>[26, 29, 34]</th><th>[26, 28, 34]</th><th>[26, 29, 33]</th><th>[26, 28, 33]</th><th>[26, 29, 32]</th><th>[26, 28, 32]</th><th>[26, 29, 31]</th><th>[26, 28, 31]</th><th>[26, 29, 30]</th><th>[26, 28, 30]</th><th>[26, 29, 29]</th><th>[26, 28, 29]</th><th>[26, 29, 28]</th><th>[26, 28, 28]</th><th>[26, 29, 27]</th><th>[26, 28, 27]</th><th>[26, 29, 26]</th><th>[26, 28, 26]</th><th>[26, 29, 25]</th><th>[26, 28, 25]</th><th>[26, 29, 24]</th><th>[26, 28, 24]</th><th>[26, 29, 23]</th><th>[26, 28, 23]</th><th>[26, 29, 22]</th><th>[26, 28, 22]</th><th>[26, 29, 21]</th><th>[26, 28, 21]</th><th>[26, 29, 20]</th><th>[26, 28, 20]</th><th>[26, 29, 19]</th><th>[26, 28, 19]</th><th>[26, 29, 18]</th><th>[26, 28, 18]</th><th>[26, 29, 17]</th><th>[26, 28, 17]</th><th>[26, 29, 16]</th><th>[26, 28, 16]</th></tr>
+<tr><th>GTX3:PMA_CFG</th><th>[36, 29, 55]</th><th>[36, 28, 55]</th><th>[36, 29, 54]</th><th>[36, 28, 54]</th><th>[36, 29, 53]</th><th>[36, 28, 53]</th><th>[36, 29, 52]</th><th>[36, 28, 52]</th><th>[36, 29, 51]</th><th>[36, 28, 51]</th><th>[36, 29, 50]</th><th>[36, 28, 50]</th><th>[36, 29, 47]</th><th>[36, 28, 47]</th><th>[36, 29, 46]</th><th>[36, 28, 46]</th><th>[36, 29, 45]</th><th>[36, 28, 45]</th><th>[36, 29, 44]</th><th>[36, 28, 44]</th><th>[36, 29, 43]</th><th>[36, 28, 43]</th><th>[36, 29, 42]</th><th>[36, 28, 42]</th><th>[36, 29, 41]</th><th>[36, 28, 41]</th><th>[36, 29, 40]</th><th>[36, 28, 40]</th><th>[36, 29, 39]</th><th>[36, 28, 39]</th><th>[36, 29, 38]</th><th>[36, 28, 38]</th><th>[36, 29, 37]</th><th>[36, 28, 37]</th><th>[36, 29, 36]</th><th>[36, 28, 36]</th><th>[36, 29, 35]</th><th>[36, 28, 35]</th><th>[36, 29, 34]</th><th>[36, 28, 34]</th><th>[36, 29, 33]</th><th>[36, 28, 33]</th><th>[36, 29, 32]</th><th>[36, 28, 32]</th><th>[36, 29, 31]</th><th>[36, 28, 31]</th><th>[36, 29, 30]</th><th>[36, 28, 30]</th><th>[36, 29, 29]</th><th>[36, 28, 29]</th><th>[36, 29, 28]</th><th>[36, 28, 28]</th><th>[36, 29, 27]</th><th>[36, 28, 27]</th><th>[36, 29, 26]</th><th>[36, 28, 26]</th><th>[36, 29, 25]</th><th>[36, 28, 25]</th><th>[36, 29, 24]</th><th>[36, 28, 24]</th><th>[36, 29, 23]</th><th>[36, 28, 23]</th><th>[36, 29, 22]</th><th>[36, 28, 22]</th><th>[36, 29, 21]</th><th>[36, 28, 21]</th><th>[36, 29, 20]</th><th>[36, 28, 20]</th><th>[36, 29, 19]</th><th>[36, 28, 19]</th><th>[36, 29, 18]</th><th>[36, 28, 18]</th><th>[36, 29, 17]</th><th>[36, 28, 17]</th><th>[36, 29, 16]</th><th>[36, 28, 16]</th></tr>
+<tr><td>Non-inverted</td><td>[75]</td><td>[74]</td><td>[73]</td><td>[72]</td><td>[71]</td><td>[70]</td><td>[69]</td><td>[68]</td><td>[67]</td><td>[66]</td><td>[65]</td><td>[64]</td><td>[63]</td><td>[62]</td><td>[61]</td><td>[60]</td><td>[59]</td><td>[58]</td><td>[57]</td><td>[56]</td><td>[55]</td><td>[54]</td><td>[53]</td><td>[52]</td><td>[51]</td><td>[50]</td><td>[49]</td><td>[48]</td><td>[47]</td><td>[46]</td><td>[45]</td><td>[44]</td><td>[43]</td><td>[42]</td><td>[41]</td><td>[40]</td><td>[39]</td><td>[38]</td><td>[37]</td><td>[36]</td><td>[35]</td><td>[34]</td><td>[33]</td><td>[32]</td><td>[31]</td><td>[30]</td><td>[29]</td><td>[28]</td><td>[27]</td><td>[26]</td><td>[25]</td><td>[24]</td><td>[23]</td><td>[22]</td><td>[21]</td><td>[20]</td><td>[19]</td><td>[18]</td><td>[17]</td><td>[16]</td><td>[15]</td><td>[14]</td><td>[13]</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:PMA_TX_CFG"></div>
+<div id="bits-xc6v-GTX-GTX1:PMA_TX_CFG"></div>
+<div id="bits-xc6v-GTX-GTX2:PMA_TX_CFG"></div>
+<div id="bits-xc6v-GTX-GTX3:PMA_TX_CFG"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:PMA_TX_CFG</th><th>[6, 29, 49]</th><th>[6, 28, 49]</th><th>[6, 29, 48]</th><th>[6, 28, 48]</th><th>[6, 29, 63]</th><th>[6, 28, 63]</th><th>[6, 29, 62]</th><th>[6, 28, 62]</th><th>[6, 29, 61]</th><th>[6, 28, 61]</th><th>[6, 29, 60]</th><th>[6, 28, 60]</th><th>[6, 29, 59]</th><th>[6, 28, 59]</th><th>[6, 29, 58]</th><th>[6, 28, 58]</th><th>[6, 29, 57]</th><th>[6, 28, 57]</th><th>[6, 29, 56]</th><th>[6, 28, 56]</th></tr>
+<tr><th>GTX1:PMA_TX_CFG</th><th>[16, 29, 49]</th><th>[16, 28, 49]</th><th>[16, 29, 48]</th><th>[16, 28, 48]</th><th>[16, 29, 63]</th><th>[16, 28, 63]</th><th>[16, 29, 62]</th><th>[16, 28, 62]</th><th>[16, 29, 61]</th><th>[16, 28, 61]</th><th>[16, 29, 60]</th><th>[16, 28, 60]</th><th>[16, 29, 59]</th><th>[16, 28, 59]</th><th>[16, 29, 58]</th><th>[16, 28, 58]</th><th>[16, 29, 57]</th><th>[16, 28, 57]</th><th>[16, 29, 56]</th><th>[16, 28, 56]</th></tr>
+<tr><th>GTX2:PMA_TX_CFG</th><th>[26, 29, 49]</th><th>[26, 28, 49]</th><th>[26, 29, 48]</th><th>[26, 28, 48]</th><th>[26, 29, 63]</th><th>[26, 28, 63]</th><th>[26, 29, 62]</th><th>[26, 28, 62]</th><th>[26, 29, 61]</th><th>[26, 28, 61]</th><th>[26, 29, 60]</th><th>[26, 28, 60]</th><th>[26, 29, 59]</th><th>[26, 28, 59]</th><th>[26, 29, 58]</th><th>[26, 28, 58]</th><th>[26, 29, 57]</th><th>[26, 28, 57]</th><th>[26, 29, 56]</th><th>[26, 28, 56]</th></tr>
+<tr><th>GTX3:PMA_TX_CFG</th><th>[36, 29, 49]</th><th>[36, 28, 49]</th><th>[36, 29, 48]</th><th>[36, 28, 48]</th><th>[36, 29, 63]</th><th>[36, 28, 63]</th><th>[36, 29, 62]</th><th>[36, 28, 62]</th><th>[36, 29, 61]</th><th>[36, 28, 61]</th><th>[36, 29, 60]</th><th>[36, 28, 60]</th><th>[36, 29, 59]</th><th>[36, 28, 59]</th><th>[36, 29, 58]</th><th>[36, 28, 58]</th><th>[36, 29, 57]</th><th>[36, 28, 57]</th><th>[36, 29, 56]</th><th>[36, 28, 56]</th></tr>
+<tr><td>Non-inverted</td><td>[19]</td><td>[18]</td><td>[17]</td><td>[16]</td><td>[15]</td><td>[14]</td><td>[13]</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:TX_DRIVE_MODE"></div>
+<div id="bits-xc6v-GTX-GTX1:TX_DRIVE_MODE"></div>
+<div id="bits-xc6v-GTX-GTX2:TX_DRIVE_MODE"></div>
+<div id="bits-xc6v-GTX-GTX3:TX_DRIVE_MODE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:TX_DRIVE_MODE</th><th>[7, 29, 39]</th></tr>
+<tr><th>GTX1:TX_DRIVE_MODE</th><th>[17, 29, 39]</th></tr>
+<tr><th>GTX2:TX_DRIVE_MODE</th><th>[27, 29, 39]</th></tr>
+<tr><th>GTX3:TX_DRIVE_MODE</th><th>[37, 29, 39]</th></tr>
+<tr><td>DIRECT</td><td>0</td></tr>
+<tr><td>PIPE</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:TST_ATTR"></div>
+<div id="bits-xc6v-GTX-GTX1:TST_ATTR"></div>
+<div id="bits-xc6v-GTX-GTX2:TST_ATTR"></div>
+<div id="bits-xc6v-GTX-GTX3:TST_ATTR"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:TST_ATTR</th><th>[8, 29, 15]</th><th>[8, 28, 15]</th><th>[8, 29, 14]</th><th>[8, 28, 14]</th><th>[8, 29, 13]</th><th>[8, 28, 13]</th><th>[8, 29, 12]</th><th>[8, 28, 12]</th><th>[8, 29, 11]</th><th>[8, 28, 11]</th><th>[8, 29, 10]</th><th>[8, 28, 10]</th><th>[8, 29, 9]</th><th>[8, 28, 9]</th><th>[8, 29, 8]</th><th>[8, 28, 8]</th><th>[8, 29, 23]</th><th>[8, 28, 23]</th><th>[8, 29, 22]</th><th>[8, 28, 22]</th><th>[8, 29, 21]</th><th>[8, 28, 21]</th><th>[8, 29, 20]</th><th>[8, 28, 20]</th><th>[8, 29, 19]</th><th>[8, 28, 19]</th><th>[8, 29, 18]</th><th>[8, 28, 18]</th><th>[8, 29, 17]</th><th>[8, 28, 17]</th><th>[8, 29, 16]</th><th>[8, 28, 16]</th></tr>
+<tr><th>GTX1:TST_ATTR</th><th>[18, 29, 15]</th><th>[18, 28, 15]</th><th>[18, 29, 14]</th><th>[18, 28, 14]</th><th>[18, 29, 13]</th><th>[18, 28, 13]</th><th>[18, 29, 12]</th><th>[18, 28, 12]</th><th>[18, 29, 11]</th><th>[18, 28, 11]</th><th>[18, 29, 10]</th><th>[18, 28, 10]</th><th>[18, 29, 9]</th><th>[18, 28, 9]</th><th>[18, 29, 8]</th><th>[18, 28, 8]</th><th>[18, 29, 23]</th><th>[18, 28, 23]</th><th>[18, 29, 22]</th><th>[18, 28, 22]</th><th>[18, 29, 21]</th><th>[18, 28, 21]</th><th>[18, 29, 20]</th><th>[18, 28, 20]</th><th>[18, 29, 19]</th><th>[18, 28, 19]</th><th>[18, 29, 18]</th><th>[18, 28, 18]</th><th>[18, 29, 17]</th><th>[18, 28, 17]</th><th>[18, 29, 16]</th><th>[18, 28, 16]</th></tr>
+<tr><th>GTX2:TST_ATTR</th><th>[28, 29, 15]</th><th>[28, 28, 15]</th><th>[28, 29, 14]</th><th>[28, 28, 14]</th><th>[28, 29, 13]</th><th>[28, 28, 13]</th><th>[28, 29, 12]</th><th>[28, 28, 12]</th><th>[28, 29, 11]</th><th>[28, 28, 11]</th><th>[28, 29, 10]</th><th>[28, 28, 10]</th><th>[28, 29, 9]</th><th>[28, 28, 9]</th><th>[28, 29, 8]</th><th>[28, 28, 8]</th><th>[28, 29, 23]</th><th>[28, 28, 23]</th><th>[28, 29, 22]</th><th>[28, 28, 22]</th><th>[28, 29, 21]</th><th>[28, 28, 21]</th><th>[28, 29, 20]</th><th>[28, 28, 20]</th><th>[28, 29, 19]</th><th>[28, 28, 19]</th><th>[28, 29, 18]</th><th>[28, 28, 18]</th><th>[28, 29, 17]</th><th>[28, 28, 17]</th><th>[28, 29, 16]</th><th>[28, 28, 16]</th></tr>
+<tr><th>GTX3:TST_ATTR</th><th>[38, 29, 15]</th><th>[38, 28, 15]</th><th>[38, 29, 14]</th><th>[38, 28, 14]</th><th>[38, 29, 13]</th><th>[38, 28, 13]</th><th>[38, 29, 12]</th><th>[38, 28, 12]</th><th>[38, 29, 11]</th><th>[38, 28, 11]</th><th>[38, 29, 10]</th><th>[38, 28, 10]</th><th>[38, 29, 9]</th><th>[38, 28, 9]</th><th>[38, 29, 8]</th><th>[38, 28, 8]</th><th>[38, 29, 23]</th><th>[38, 28, 23]</th><th>[38, 29, 22]</th><th>[38, 28, 22]</th><th>[38, 29, 21]</th><th>[38, 28, 21]</th><th>[38, 29, 20]</th><th>[38, 28, 20]</th><th>[38, 29, 19]</th><th>[38, 28, 19]</th><th>[38, 29, 18]</th><th>[38, 28, 18]</th><th>[38, 29, 17]</th><th>[38, 28, 17]</th><th>[38, 29, 16]</th><th>[38, 28, 16]</th></tr>
+<tr><td>Non-inverted</td><td>[31]</td><td>[30]</td><td>[29]</td><td>[28]</td><td>[27]</td><td>[26]</td><td>[25]</td><td>[24]</td><td>[23]</td><td>[22]</td><td>[21]</td><td>[20]</td><td>[19]</td><td>[18]</td><td>[17]</td><td>[16]</td><td>[15]</td><td>[14]</td><td>[13]</td><td>[12]</td><td>[11]</td><td>[10]</td><td>[9]</td><td>[8]</td><td>[7]</td><td>[6]</td><td>[5]</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:TXOUTCLK_CTRL"></div>
+<div id="bits-xc6v-GTX-GTX1:TXOUTCLK_CTRL"></div>
+<div id="bits-xc6v-GTX-GTX2:TXOUTCLK_CTRL"></div>
+<div id="bits-xc6v-GTX-GTX3:TXOUTCLK_CTRL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:TXOUTCLK_CTRL</th><th>[8, 28, 24]</th><th>[8, 29, 24]</th><th>[8, 28, 25]</th></tr>
+<tr><th>GTX1:TXOUTCLK_CTRL</th><th>[18, 28, 24]</th><th>[18, 29, 24]</th><th>[18, 28, 25]</th></tr>
+<tr><th>GTX2:TXOUTCLK_CTRL</th><th>[28, 28, 24]</th><th>[28, 29, 24]</th><th>[28, 28, 25]</th></tr>
+<tr><th>GTX3:TXOUTCLK_CTRL</th><th>[38, 28, 24]</th><th>[38, 29, 24]</th><th>[38, 28, 25]</th></tr>
+<tr><td>TXOUTCLKPCS</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>TXPLLREFCLK_DIV2</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>TXOUTCLKPMA_DIV2</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF_HIGH</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>TXOUTCLKPMA_DIV1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF_LOW</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>TXPLLREFCLK_DIV1</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>CLKTESTSIG0</td><td>1</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-GTX0:RXRECCLK_CTRL"></div>
+<div id="bits-xc6v-GTX-GTX1:RXRECCLK_CTRL"></div>
+<div id="bits-xc6v-GTX-GTX2:RXRECCLK_CTRL"></div>
+<div id="bits-xc6v-GTX-GTX3:RXRECCLK_CTRL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>GTX0:RXRECCLK_CTRL</th><th>[8, 29, 25]</th><th>[8, 28, 26]</th><th>[8, 29, 26]</th></tr>
+<tr><th>GTX1:RXRECCLK_CTRL</th><th>[18, 29, 25]</th><th>[18, 28, 26]</th><th>[18, 29, 26]</th></tr>
+<tr><th>GTX2:RXRECCLK_CTRL</th><th>[28, 29, 25]</th><th>[28, 28, 26]</th><th>[28, 29, 26]</th></tr>
+<tr><th>GTX3:RXRECCLK_CTRL</th><th>[38, 29, 25]</th><th>[38, 28, 26]</th><th>[38, 29, 26]</th></tr>
+<tr><td>RXRECCLKPCS</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>RXPLLREFCLK_DIV2</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>RXRECCLKPMA_DIV2</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF_HIGH</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>RXRECCLKPMA_DIV1</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF_LOW</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>RXPLLREFCLK_DIV1</td><td>1</td><td>1</td><td>0</td></tr>
+<tr><td>CLKTESTSIG1</td><td>1</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-HCLK_GTX:MUX.PERFCLK"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>HCLK_GTX:MUX.PERFCLK</th><th>[14, 29, 22]</th><th>[14, 28, 22]</th><th>[14, 28, 23]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>PERF0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>PERF1</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>PERF2</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>PERF3</td><td>1</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-IBUFDS_GTX0:MUX.HCLK_OUT"></div>
+<div id="bits-xc6v-GTX-IBUFDS_GTX1:MUX.HCLK_OUT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IBUFDS_GTX0:MUX.HCLK_OUT</th><th>[18, 28, 27]</th><th>[18, 29, 27]</th></tr>
+<tr><th>IBUFDS_GTX1:MUX.HCLK_OUT</th><th>[18, 28, 28]</th><th>[18, 29, 28]</th></tr>
+<tr><td>O</td><td>0</td><td>0</td></tr>
+<tr><td>NONE</td><td>0</td><td>1</td></tr>
+<tr><td>ODIV2</td><td>1</td><td>0</td></tr>
+<tr><td>CLKTESTSIG</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-HCLK_GTX:MUX.NORTHREFCLKOUT0"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>HCLK_GTX:MUX.NORTHREFCLKOUT0</th><th>[34, 29, 16]</th><th>[34, 28, 16]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td></tr>
+<tr><td>NORTHREFCLKIN0</td><td>0</td><td>1</td></tr>
+<tr><td>MGTREFCLKOUT0</td><td>1</td><td>0</td></tr>
+<tr><td>MGTREFCLKOUT1</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-HCLK_GTX:MUX.SOUTHREFCLKOUT0"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>HCLK_GTX:MUX.SOUTHREFCLKOUT0</th><th>[34, 29, 19]</th><th>[34, 28, 19]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td></tr>
+<tr><td>SOUTHREFCLKIN0</td><td>0</td><td>1</td></tr>
+<tr><td>MGTREFCLKIN0</td><td>1</td><td>0</td></tr>
+<tr><td>MGTREFCLKIN1</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-HCLK_GTX:MUX.NORTHREFCLKOUT1"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>HCLK_GTX:MUX.NORTHREFCLKOUT1</th><th>[34, 28, 18]</th><th>[34, 29, 17]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td></tr>
+<tr><td>NORTHREFCLKIN1</td><td>0</td><td>1</td></tr>
+<tr><td>MGTREFCLKOUT0</td><td>1</td><td>0</td></tr>
+<tr><td>MGTREFCLKOUT1</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc6v-GTX-HCLK_GTX:MUX.SOUTHREFCLKOUT1"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>HCLK_GTX:MUX.SOUTHREFCLKOUT1</th><th>[34, 28, 21]</th><th>[34, 29, 20]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td></tr>
+<tr><td>SOUTHREFCLKIN1</td><td>0</td><td>1</td></tr>
+<tr><td>MGTREFCLKIN0</td><td>1</td><td>0</td></tr>
+<tr><td>MGTREFCLKIN1</td><td>1</td><td>1</td></tr>
+</table>
+</section>
+</section>
+
+
+           </div>
+          </div>
+          <footer><div class="rst-footer-buttons" role="navigation" aria-label="Footer">
+        <a href="pcie.html" class="btn btn-neutral float-left" title="PCI Express cores" accesskey="p" rel="prev"><span class="fa fa-arrow-circle-left" aria-hidden="true"></span> Previous</a>
+        <a href="config.html" class="btn btn-neutral float-right" title="Configuration registers" accesskey="n" rel="next">Next <span class="fa fa-arrow-circle-right" aria-hidden="true"></span></a>
+    </div>
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+
+  <div role="contentinfo">
+    <p>&#169; Copyright 2023, Wanda.</p>
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diff --git a/xilinx/virtex6/index.html b/xilinx/virtex6/index.html
index a4693e5b..4b4fca1f 100644
--- a/xilinx/virtex6/index.html
+++ b/xilinx/virtex6/index.html
@@ -66,6 +66,7 @@
 <li class="toctree-l3"><a class="reference internal" href="center.html">Configuration Center</a></li>
 <li class="toctree-l3"><a class="reference internal" href="emac.html">Ethernet MACs</a></li>
 <li class="toctree-l3"><a class="reference internal" href="pcie.html">PCI Express cores</a></li>
+<li class="toctree-l3"><a class="reference internal" href="gtx.html">GTX transceivers</a></li>
 <li class="toctree-l3"><a class="reference internal" href="config.html">Configuration registers</a></li>
 </ul>
 </li>
@@ -150,6 +151,10 @@ <h1>Virtex 6<a class="headerlink" href="#virtex-6" title="Link to this heading">
 <li class="toctree-l2"><a class="reference internal" href="pcie.html#bitstream">Bitstream</a></li>
 </ul>
 </li>
+<li class="toctree-l1"><a class="reference internal" href="gtx.html">GTX transceivers</a><ul>
+<li class="toctree-l2"><a class="reference internal" href="gtx.html#bitstream">Bitstream</a></li>
+</ul>
+</li>
 <li class="toctree-l1"><a class="reference internal" href="config.html">Configuration registers</a><ul>
 <li class="toctree-l2"><a class="reference internal" href="config.html#cor"><code class="docutils literal notranslate"><span class="pre">COR</span></code></a></li>
 <li class="toctree-l2"><a class="reference internal" href="config.html#cor1"><code class="docutils literal notranslate"><span class="pre">COR1</span></code></a></li>
diff --git a/xilinx/virtex6/interconnect.html b/xilinx/virtex6/interconnect.html
index 4354dd69..1b4dce8e 100644
--- a/xilinx/virtex6/interconnect.html
+++ b/xilinx/virtex6/interconnect.html
@@ -71,6 +71,7 @@
 <li class="toctree-l3"><a class="reference internal" href="center.html">Configuration Center</a></li>
 <li class="toctree-l3"><a class="reference internal" href="emac.html">Ethernet MACs</a></li>
 <li class="toctree-l3"><a class="reference internal" href="pcie.html">PCI Express cores</a></li>
+<li class="toctree-l3"><a class="reference internal" href="gtx.html">GTX transceivers</a></li>
 <li class="toctree-l3"><a class="reference internal" href="config.html">Configuration registers</a></li>
 </ul>
 </li>
diff --git a/xilinx/virtex6/io.html b/xilinx/virtex6/io.html
index b93db83f..90994017 100644
--- a/xilinx/virtex6/io.html
+++ b/xilinx/virtex6/io.html
@@ -70,6 +70,7 @@
 <li class="toctree-l3"><a class="reference internal" href="center.html">Configuration Center</a></li>
 <li class="toctree-l3"><a class="reference internal" href="emac.html">Ethernet MACs</a></li>
 <li class="toctree-l3"><a class="reference internal" href="pcie.html">PCI Express cores</a></li>
+<li class="toctree-l3"><a class="reference internal" href="gtx.html">GTX transceivers</a></li>
 <li class="toctree-l3"><a class="reference internal" href="config.html">Configuration registers</a></li>
 </ul>
 </li>
diff --git a/xilinx/virtex6/pcie.html b/xilinx/virtex6/pcie.html
index 2bfa5e09..805a6c0c 100644
--- a/xilinx/virtex6/pcie.html
+++ b/xilinx/virtex6/pcie.html
@@ -19,7 +19,7 @@
     <script src="../../_static/js/theme.js"></script>
     <link rel="index" title="Index" href="../../genindex.html" />
     <link rel="search" title="Search" href="../../search.html" />
-    <link rel="next" title="Configuration registers" href="config.html" />
+    <link rel="next" title="GTX transceivers" href="gtx.html" />
     <link rel="prev" title="Ethernet MACs" href="emac.html" /> 
 </head>
 
@@ -69,6 +69,7 @@
 <li class="toctree-l4"><a class="reference internal" href="#bitstream">Bitstream</a></li>
 </ul>
 </li>
+<li class="toctree-l3"><a class="reference internal" href="gtx.html">GTX transceivers</a></li>
 <li class="toctree-l3"><a class="reference internal" href="config.html">Configuration registers</a></li>
 </ul>
 </li>
@@ -2309,7 +2310,7 @@ <h2>Bitstream<a class="headerlink" href="#bitstream" title="Link to this heading
           </div>
           <footer><div class="rst-footer-buttons" role="navigation" aria-label="Footer">
         <a href="emac.html" class="btn btn-neutral float-left" title="Ethernet MACs" accesskey="p" rel="prev"><span class="fa fa-arrow-circle-left" aria-hidden="true"></span> Previous</a>
-        <a href="config.html" class="btn btn-neutral float-right" title="Configuration registers" accesskey="n" rel="next">Next <span class="fa fa-arrow-circle-right" aria-hidden="true"></span></a>
+        <a href="gtx.html" class="btn btn-neutral float-right" title="GTX transceivers" accesskey="n" rel="next">Next <span class="fa fa-arrow-circle-right" aria-hidden="true"></span></a>
     </div>
 
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