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Add risc-v support #7

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Dec 14, 2024
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4 changes: 2 additions & 2 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -27,8 +27,8 @@ jobs:
cargo install cargo-binutils
rustup component add llvm-tools-preview
- name: Check
run: cargo check --target thumbv7em-none-eabi
run: cargo check --features cortex-m --target thumbv7em-none-eabi
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- name: Clippy
run: cargo clippy --target thumbv7em-none-eabi
run: cargo clippy --features cortex-m --target thumbv7em-none-eabi
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- name: Format
run: cargo fmt
2 changes: 2 additions & 0 deletions Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -15,3 +15,5 @@ default = ["erase-chip", "panic-handler"]
erase-chip = []
panic-handler = []
verify = []
cortex-m = []
risc-v = []
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6 changes: 6 additions & 0 deletions src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,14 @@
#[cfg(all(not(test), feature = "panic-handler"))]
#[panic_handler]
fn panic(_info: &core::panic::PanicInfo) -> ! {
#[cfg(not(any(target_arch = "arm", target_arch = "riscv32")))]
compile_error!("Panic handler can only be compiled for arm and riscv32");

unsafe {
#[cfg(target_arch = "arm")]
core::arch::asm!("udf #0");
#[cfg(target_arch = "riscv32")]
core::arch::asm!("UNIMP");
core::hint::unreachable_unchecked();
}
}
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