diff --git a/Bender.lock b/Bender.lock index c2c00146..16294f8d 100644 --- a/Bender.lock +++ b/Bender.lock @@ -99,8 +99,8 @@ packages: dependencies: - common_cells axi_vga: - revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084 - version: 0.1.3 + revision: 4d3e70d4f47bb74edc1ab68d99ffc02382e0fb9e + version: 0.1.4 source: Git: https://github.com/pulp-platform/axi_vga.git dependencies: @@ -235,6 +235,17 @@ packages: Git: https://github.com/pulp-platform/event_unit_flex.git dependencies: - common_cells + floo_noc: + revision: a1241c0bce20c33504e1cffdb89fed630ee6a514 + version: null + source: + Git: https://github.com/pulp-platform/FlooNoC.git + dependencies: + - axi + - axi_riscv_atomics + - common_cells + - common_verification + - idma fpnew: revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315 version: null @@ -461,8 +472,8 @@ packages: - register_interface - tech_cells_generic register_interface: - revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d - version: 0.4.4 + revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467 + version: 0.4.5 source: Git: https://github.com/pulp-platform/register_interface.git dependencies: diff --git a/Bender.yml b/Bender.yml index 8bb837c6..3b5aa30d 100644 --- a/Bender.yml +++ b/Bender.yml @@ -28,6 +28,7 @@ dependencies: common_cells: { git: https://github.com/pulp-platform/common_cells.git, version: 1.37.0 } # branch: master pulp-ethernet: { git: https://github.com/pulp-platform/pulp-ethernet.git, rev: 2bea11658d2bc368ae2af0a3f71b4253ba4f713f } # branch: handshake riscv-dbg: { git: https://github.com/pulp-platform/riscv-dbg.git, version: =0.8.0 } + floo_noc: { git: https://github.com/pulp-platform/FlooNoC.git, rev: a1241c0bce20c33504e1cffdb89fed630ee6a514 } # branch: yt/test workspace: package_links: @@ -40,6 +41,10 @@ workspace: sources: # Configurations # "Small" Astral configuration + - target: astral_noc + files: + - hw/configs/astral_noc.sv + - target: carfield_l2dual_secure_pulp_periph_can files: - hw/configs/carfield_l2dual_secure_pulp_periph_can.sv @@ -92,6 +97,7 @@ sources: - hw/hyperbus_wrap.sv - hw/l2_wrap.sv - hw/ethernet_wrap.sv + - hw/noc_wrap.sv - hw/carfield_rstgen.sv # Level 2 - hw/carfield.sv diff --git a/bender-common.mk b/bender-common.mk index 0f12d785..604f2926 100644 --- a/bender-common.mk +++ b/bender-common.mk @@ -6,7 +6,7 @@ # Author: Matteo Perotti # Runtime-selectable Carfield configuration -CARFIELD_CONFIG ?= carfield_l2dual_secure_pulp_periph_can +CARFIELD_CONFIG ?= astral_noc # bender targets common_targs += -t cva6 diff --git a/carfield.mk b/carfield.mk index 2b9e266c..56a26cc0 100644 --- a/carfield.mk +++ b/carfield.mk @@ -24,6 +24,7 @@ CAR_TGT_DIR := $(CAR_ROOT)/target/ CAR_XIL_DIR := $(CAR_TGT_DIR)/xilinx CAR_SIM_DIR := $(CAR_TGT_DIR)/sim SECD_ROOT ?= $(shell $(BENDER) path opentitan) +NOC_ROOT ?= $(shell $(BENDER) path floo_noc) # Questasim CAR_VSIM_DIR := $(CAR_TGT_DIR)/sim/vsim @@ -238,6 +239,15 @@ car-hw-init: $(SPATZD_HW_INIT) chs-hw-init $(SECD_HW_INIT) secd-hw-init: $(MAKE) -C $(SECD_ROOT)/hw/vendor/pulp_riscv_dbg/debug_rom clean all FLAGS=-DCARFIELD=1 +## @section NoC genration +FLOOGEN ?= floogen +.PHONY: regenerate_noc +install_floogen: | venv + source $(VENVDIR)/bin/activate; cd $(NOC_ROOT); pip install .; cd $(ROOT); deactivate + +regenerate_noc: install_floogen | venv + source $(VENVDIR)/bin/activate; $(FLOOGEN) -c $(NOC_ROOT)/floogen/examples/astral.yml -o $(NOC_ROOT)/hw/astral --no-format; deactivate + ## @section Carfield platform PCRs generation .PHONY: regenerate_soc_regs ## Regenerate the toplevel PCRs from the CSV description of all registers in diff --git a/hw/carfield.sv b/hw/carfield.sv index f6aba4f8..ab526b9c 100644 --- a/hw/carfield.sv +++ b/hw/carfield.sv @@ -333,7 +333,7 @@ typedef logic [ Cfg.AddrWidth-1:0] car_addrw_t; typedef logic [ Cfg.AxiDataWidth-1:0] car_dataw_t; typedef logic [(Cfg.AxiDataWidth)/8-1:0] car_strb_t; typedef logic [ Cfg.AxiUserWidth-1:0] car_usr_t; -typedef logic [ AxiSlvIdWidth-1:0] car_slv_id_t; +typedef logic [ Cfg.AxiMstIdWidth-1:0] car_mst_id_t; // Slave CDC parameters localparam int unsigned CarfieldAxiSlvAwWidth = @@ -380,9 +380,7 @@ carfield_reg_req_t [iomsb(NumSyncRegSlv):0] ext_reg_req, ext_reg_req_cut; carfield_reg_rsp_t [iomsb(NumSyncRegSlv):0] ext_reg_rsp, ext_reg_rsp_cut; `ifndef GEN_NO_HYPERBUS // bender-xilinx.mk -localparam int unsigned LlcIdWidth = Cfg.AxiMstIdWidth + - $clog2(AxiIn.num_in)+ - Cfg.LlcNotBypass ; +localparam int unsigned LlcIdWidth = AxiSlvIdWidth + Cfg.LlcNotBypass; localparam int unsigned LlcArWidth = (2**LogDepth)* axi_pkg::ar_width(Cfg.AddrWidth , LlcIdWidth , @@ -402,6 +400,8 @@ localparam int unsigned LlcWWidth = (2**LogDepth)* axi_pkg::w_width(Cfg.AxiDataWidth, Cfg.AxiUserWidth ); +localparam int unsigned NumNocMst = CarfieldAxiNumSlaves -1; + logic [LlcArWidth-1:0] llc_ar_data; logic [ LogDepth:0] llc_ar_wptr; logic [ LogDepth:0] llc_ar_rptr; @@ -424,42 +424,42 @@ logic hyper_isolate_req, hyper_isolated_rsp; logic security_island_isolate_req; logic ethernet_isolate_req, ethernet_isolated_rsp; -logic [iomsb(Cfg.AxiExtNumSlv):0] slave_isolate_req, slave_isolated_rsp, slave_isolated; -logic [iomsb(Cfg.AxiExtNumMst):0] master_isolated_rsp; +logic [NumNocMst-1:0] slave_isolate_req, slave_isolated_rsp, slave_isolated; +logic [CarfieldAxiNumMasters-1:0] master_isolated_rsp; // All AXI Slaves (except the Mailbox) -logic [iomsb(NumSlaveCDCs):0][CarfieldAxiSlvAwWidth-1:0] axi_slv_ext_aw_data; -logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_aw_wptr; -logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_aw_rptr; -logic [iomsb(NumSlaveCDCs):0][ CarfieldAxiSlvWWidth-1:0] axi_slv_ext_w_data ; -logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_w_wptr ; -logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_w_rptr ; -logic [iomsb(NumSlaveCDCs):0][ CarfieldAxiSlvBWidth-1:0] axi_slv_ext_b_data ; -logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_b_wptr ; -logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_b_rptr ; -logic [iomsb(NumSlaveCDCs):0][CarfieldAxiSlvArWidth-1:0] axi_slv_ext_ar_data; -logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_ar_wptr; -logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_ar_rptr; -logic [iomsb(NumSlaveCDCs):0][ CarfieldAxiSlvRWidth-1:0] axi_slv_ext_r_data ; -logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_r_wptr ; -logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_r_rptr ; +logic [NumNocMst-1:0][CarfieldAxiMstAwWidth-1:0] axi_mst_ext_aw_data; +logic [NumNocMst-1:0][ LogDepth:0] axi_mst_ext_aw_wptr; +logic [NumNocMst-1:0][ LogDepth:0] axi_mst_ext_aw_rptr; +logic [NumNocMst-1:0][ CarfieldAxiMstWWidth-1:0] axi_mst_ext_w_data ; +logic [NumNocMst-1:0][ LogDepth:0] axi_mst_ext_w_wptr ; +logic [NumNocMst-1:0][ LogDepth:0] axi_mst_ext_w_rptr ; +logic [NumNocMst-1:0][ CarfieldAxiMstBWidth-1:0] axi_mst_ext_b_data ; +logic [NumNocMst-1:0][ LogDepth:0] axi_mst_ext_b_wptr ; +logic [NumNocMst-1:0][ LogDepth:0] axi_mst_ext_b_rptr ; +logic [NumNocMst-1:0][CarfieldAxiMstArWidth-1:0] axi_mst_ext_ar_data; +logic [NumNocMst-1:0][ LogDepth:0] axi_mst_ext_ar_wptr; +logic [NumNocMst-1:0][ LogDepth:0] axi_mst_ext_ar_rptr; +logic [NumNocMst-1:0][ CarfieldAxiMstRWidth-1:0] axi_mst_ext_r_data ; +logic [NumNocMst-1:0][ LogDepth:0] axi_mst_ext_r_wptr ; +logic [NumNocMst-1:0][ LogDepth:0] axi_mst_ext_r_rptr ; // All AXI Masters -logic [iomsb(Cfg.AxiExtNumMst):0][CarfieldAxiMstAwWidth-1:0] axi_mst_ext_aw_data; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_aw_wptr; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_aw_rptr; -logic [iomsb(Cfg.AxiExtNumMst):0][ CarfieldAxiMstWWidth-1:0] axi_mst_ext_w_data ; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_w_wptr ; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_w_rptr ; -logic [iomsb(Cfg.AxiExtNumMst):0][ CarfieldAxiMstBWidth-1:0] axi_mst_ext_b_data ; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_b_wptr ; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_b_rptr ; -logic [iomsb(Cfg.AxiExtNumMst):0][CarfieldAxiMstArWidth-1:0] axi_mst_ext_ar_data; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_ar_wptr; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_ar_rptr; -logic [iomsb(Cfg.AxiExtNumMst):0][ CarfieldAxiMstRWidth-1:0] axi_mst_ext_r_data ; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_r_wptr ; -logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_r_rptr ; +logic [CarfieldAxiNumMasters-1:0][CarfieldAxiSlvAwWidth-1:0] axi_slv_ext_aw_data; +logic [CarfieldAxiNumMasters-1:0][ LogDepth:0] axi_slv_ext_aw_wptr; +logic [CarfieldAxiNumMasters-1:0][ LogDepth:0] axi_slv_ext_aw_rptr; +logic [CarfieldAxiNumMasters-1:0][ CarfieldAxiSlvWWidth-1:0] axi_slv_ext_w_data ; +logic [CarfieldAxiNumMasters-1:0][ LogDepth:0] axi_slv_ext_w_wptr ; +logic [CarfieldAxiNumMasters-1:0][ LogDepth:0] axi_slv_ext_w_rptr ; +logic [CarfieldAxiNumMasters-1:0][ CarfieldAxiSlvBWidth-1:0] axi_slv_ext_b_data ; +logic [CarfieldAxiNumMasters-1:0][ LogDepth:0] axi_slv_ext_b_wptr ; +logic [CarfieldAxiNumMasters-1:0][ LogDepth:0] axi_slv_ext_b_rptr ; +logic [CarfieldAxiNumMasters-1:0][CarfieldAxiSlvArWidth-1:0] axi_slv_ext_ar_data; +logic [CarfieldAxiNumMasters-1:0][ LogDepth:0] axi_slv_ext_ar_wptr; +logic [CarfieldAxiNumMasters-1:0][ LogDepth:0] axi_slv_ext_ar_rptr; +logic [CarfieldAxiNumMasters-1:0][ CarfieldAxiSlvRWidth-1:0] axi_slv_ext_r_data ; +logic [CarfieldAxiNumMasters-1:0][ LogDepth:0] axi_slv_ext_r_wptr ; +logic [CarfieldAxiNumMasters-1:0][ LogDepth:0] axi_slv_ext_r_rptr ; // soc reg signals carfield_reg2hw_t car_regs_reg2hw; @@ -697,10 +697,10 @@ carfield_a32_d32_reg_req_t reg_wdt_req; carfield_a32_d32_reg_rsp_t reg_wdt_rsp; // mailbox -carfield_axi_slv_req_t axi_mbox_req, axi_amo_mbox_req, - axi_pre_amo_cut_mbox_req, axi_post_amo_cut_mbox_req; -carfield_axi_slv_rsp_t axi_mbox_rsp, axi_amo_mbox_rsp, - axi_pre_amo_cut_mbox_rsp, axi_post_amo_cut_mbox_rsp; +carfield_axi_mst_req_t axi_mbox_req, axi_amo_mbox_req, + axi_pre_amo_cut_mbox_req, axi_post_amo_cut_mbox_req; +carfield_axi_mst_rsp_t axi_mbox_rsp, axi_amo_mbox_rsp, + axi_pre_amo_cut_mbox_rsp, axi_post_amo_cut_mbox_rsp; ////////////////// // Carfield IPs // @@ -732,6 +732,91 @@ assign chs_ext_intrs = { pulpcl_eoc // from integer cluster }; +carfield_axi_slv_req_t cheshire_slv_req; +carfield_axi_slv_rsp_t cheshire_slv_rsp; +carfield_axi_mst_req_t cheshire_mst_req; +carfield_axi_mst_rsp_t cheshire_mst_rsp; + +noc_wrap #( + .Cfg ( Cfg ), + .LogDepth ( LogDepth ), + .CdcSyncStages ( SyncStages ), + // NoC master ports connect to external slave devices, and vice versa + .NocSlvIdWidth ( AxiSlvIdWidth ), + .LlcIdWidth ( LlcIdWidth ), + .NumNocSlv ( carfield_pkg::CarfieldAxiNumMasters ), + .NumNocMst ( carfield_pkg::CarfieldAxiNumSlaves - 1 ), + .LlcArWidth ( LlcArWidth ), + .LlcAwWidth ( LlcAwWidth ), + .LlcBWidth ( LlcBWidth ), + .LlcRWidth ( LlcRWidth ), + .LlcWWidth ( LlcWWidth ), + .noc_llc_ar_chan_t ( carfield_axi_llc_ar_chan_t ), + .noc_llc_aw_chan_t ( carfield_axi_llc_aw_chan_t ), + .noc_llc_b_chan_t ( carfield_axi_llc_b_chan_t ), + .noc_llc_r_chan_t ( carfield_axi_llc_r_chan_t ), + .noc_llc_w_chan_t ( carfield_axi_llc_w_chan_t ), + .noc_llc_req_t ( carfield_axi_llc_req_t ), + .noc_llc_rsp_t ( carfield_axi_llc_rsp_t ), + .noc_mst_ar_chan_t ( carfield_axi_mst_ar_chan_t ), + .noc_mst_aw_chan_t ( carfield_axi_mst_aw_chan_t ), + .noc_mst_b_chan_t ( carfield_axi_mst_b_chan_t ), + .noc_mst_r_chan_t ( carfield_axi_mst_r_chan_t ), + .noc_mst_w_chan_t ( carfield_axi_mst_w_chan_t ), + .noc_mst_req_t ( carfield_axi_mst_req_t ), + .noc_mst_rsp_t ( carfield_axi_mst_rsp_t ), + .noc_slv_ar_chan_t ( carfield_axi_slv_ar_chan_t ), + .noc_slv_aw_chan_t ( carfield_axi_slv_aw_chan_t ), + .noc_slv_b_chan_t ( carfield_axi_slv_b_chan_t ), + .noc_slv_r_chan_t ( carfield_axi_slv_r_chan_t ), + .noc_slv_w_chan_t ( carfield_axi_slv_w_chan_t ), + .noc_slv_req_t ( carfield_axi_slv_req_t ), + .noc_slv_rsp_t ( carfield_axi_slv_rsp_t ) +) i_noc ( + .clk_i ( host_clk_i ), + .rst_ni ( host_pwr_on_rst_n ), + .noc_ext_slv_isolate_i ( slave_isolate_req ), + .noc_ext_slv_isolated_o ( slave_isolated_rsp ), + .cheshire_slv_req_i ( cheshire_slv_req ), + .cheshire_slv_rsp_o ( cheshire_slv_rsp ), + .cheshire_mst_req_o ( cheshire_mst_req ), + .cheshire_mst_rsp_i ( cheshire_mst_rsp ), + .mailbox_mst_req_o ( ), + .mailbox_mst_rsp_i ( axi_mbox_rsp ), + // External async AXI master Ports + .noc_ext_mst_ar_data_o ( axi_mst_ext_ar_data ), + .noc_ext_mst_ar_wptr_o ( axi_mst_ext_ar_wptr ), + .noc_ext_mst_ar_rptr_i ( axi_mst_ext_ar_rptr ), + .noc_ext_mst_aw_data_o ( axi_mst_ext_aw_data ), + .noc_ext_mst_aw_wptr_o ( axi_mst_ext_aw_wptr ), + .noc_ext_mst_aw_rptr_i ( axi_mst_ext_aw_rptr ), + .noc_ext_mst_b_data_i ( axi_mst_ext_b_data ), + .noc_ext_mst_b_wptr_i ( axi_mst_ext_b_wptr ), + .noc_ext_mst_b_rptr_o ( axi_mst_ext_b_rptr ), + .noc_ext_mst_r_data_i ( axi_mst_ext_r_data ), + .noc_ext_mst_r_wptr_i ( axi_mst_ext_r_wptr ), + .noc_ext_mst_r_rptr_o ( axi_mst_ext_r_rptr ), + .noc_ext_mst_w_data_o ( axi_mst_ext_w_data ), + .noc_ext_mst_w_wptr_o ( axi_mst_ext_w_wptr ), + .noc_ext_mst_w_rptr_i ( axi_mst_ext_w_rptr ), + // External async AXI slave Ports + .noc_ext_slv_ar_data_i ( axi_slv_ext_ar_data ), + .noc_ext_slv_ar_wptr_i ( axi_slv_ext_ar_wptr ), + .noc_ext_slv_ar_rptr_o ( axi_slv_ext_ar_rptr ), + .noc_ext_slv_aw_data_i ( axi_slv_ext_aw_data ), + .noc_ext_slv_aw_wptr_i ( axi_slv_ext_aw_wptr ), + .noc_ext_slv_aw_rptr_o ( axi_slv_ext_aw_rptr ), + .noc_ext_slv_b_data_o ( axi_slv_ext_b_data ), + .noc_ext_slv_b_wptr_o ( axi_slv_ext_b_wptr ), + .noc_ext_slv_b_rptr_i ( axi_slv_ext_b_rptr ), + .noc_ext_slv_r_data_o ( axi_slv_ext_r_data ), + .noc_ext_slv_r_wptr_o ( axi_slv_ext_r_wptr ), + .noc_ext_slv_r_rptr_i ( axi_slv_ext_r_rptr ), + .noc_ext_slv_w_data_i ( axi_slv_ext_w_data ), + .noc_ext_slv_w_wptr_i ( axi_slv_ext_w_wptr ), + .noc_ext_slv_w_rptr_o ( axi_slv_ext_w_rptr ) +); + `ifndef CHS_NETLIST cheshire_wrap #( .Cfg ( Cfg ), @@ -762,9 +847,15 @@ cheshire_wrap #( .cheshire_reg_ext_rsp_t ( carfield_reg_rsp_t ), .LogDepth ( LogDepth ), .CdcSyncStages ( SyncStages ), - .NumSlaveCDCs ( NumSlaveCDCs ), .AxiIn ( AxiIn ), - .AxiOut ( AxiOut ) + .AxiOut ( AxiOut ), + .ExtSlvIdWidth ( AxiSlvIdWidth ), + .LlcIdWidth ( LlcIdWidth ), + .LlcArWidth ( LlcArWidth ), + .LlcAwWidth ( LlcAwWidth ), + .LlcBWidth ( LlcBWidth ), + .LlcRWidth ( LlcRWidth ), + .LlcWWidth ( LlcWWidth ) ) i_cheshire_wrap ( `else cheshire i_cheshire_wrap ( @@ -777,58 +868,27 @@ cheshire i_cheshire_wrap ( // External AXI LLC (DRAM) port .axi_llc_isolate_i ( hyper_isolate_req ), .axi_llc_isolated_o ( hyper_isolated_rsp ), - .llc_mst_ar_data_o ( llc_ar_data ), - .llc_mst_ar_wptr_o ( llc_ar_wptr ), - .llc_mst_ar_rptr_i ( llc_ar_rptr ), - .llc_mst_aw_data_o ( llc_aw_data ), - .llc_mst_aw_wptr_o ( llc_aw_wptr ), - .llc_mst_aw_rptr_i ( llc_aw_rptr ), - .llc_mst_b_data_i ( llc_b_data ), - .llc_mst_b_wptr_i ( llc_b_wptr ), - .llc_mst_b_rptr_o ( llc_b_rptr ), - .llc_mst_r_data_i ( llc_r_data ), - .llc_mst_r_wptr_i ( llc_r_wptr ), - .llc_mst_r_rptr_o ( llc_r_rptr ), - .llc_mst_w_data_o ( llc_w_data ), - .llc_mst_w_wptr_o ( llc_w_wptr ), - .llc_mst_w_rptr_i ( llc_w_rptr ), + .llc_ar_data_o ( llc_ar_data ), + .llc_ar_wptr_o ( llc_ar_wptr ), + .llc_ar_rptr_i ( llc_ar_rptr ), + .llc_aw_data_o ( llc_aw_data ), + .llc_aw_wptr_o ( llc_aw_wptr ), + .llc_aw_rptr_i ( llc_aw_rptr ), + .llc_b_data_i ( llc_b_data ), + .llc_b_wptr_i ( llc_b_wptr ), + .llc_b_rptr_o ( llc_b_rptr ), + .llc_r_data_i ( llc_r_data ), + .llc_r_wptr_i ( llc_r_wptr ), + .llc_r_rptr_o ( llc_r_rptr ), + .llc_w_data_o ( llc_w_data ), + .llc_w_wptr_o ( llc_w_wptr ), + .llc_w_rptr_i ( llc_w_rptr ), // External AXI slave devices - .axi_ext_slv_isolate_i ( slave_isolate_req ), - .axi_ext_slv_isolated_o ( slave_isolated_rsp ), - .axi_ext_slv_ar_data_o ( axi_slv_ext_ar_data ), - .axi_ext_slv_ar_wptr_o ( axi_slv_ext_ar_wptr ), - .axi_ext_slv_ar_rptr_i ( axi_slv_ext_ar_rptr ), - .axi_ext_slv_aw_data_o ( axi_slv_ext_aw_data ), - .axi_ext_slv_aw_wptr_o ( axi_slv_ext_aw_wptr ), - .axi_ext_slv_aw_rptr_i ( axi_slv_ext_aw_rptr ), - .axi_ext_slv_b_data_i ( axi_slv_ext_b_data ), - .axi_ext_slv_b_wptr_i ( axi_slv_ext_b_wptr ), - .axi_ext_slv_b_rptr_o ( axi_slv_ext_b_rptr ), - .axi_ext_slv_r_data_i ( axi_slv_ext_r_data ), - .axi_ext_slv_r_wptr_i ( axi_slv_ext_r_wptr ), - .axi_ext_slv_r_rptr_o ( axi_slv_ext_r_rptr ), - .axi_ext_slv_w_data_o ( axi_slv_ext_w_data ), - .axi_ext_slv_w_wptr_o ( axi_slv_ext_w_wptr ), - .axi_ext_slv_w_rptr_i ( axi_slv_ext_w_rptr ), + .axi_ext_slv_req_o ( cheshire_slv_req ), + .axi_ext_slv_rsp_i ( cheshire_slv_rsp ), // External AXI master devices - .axi_ext_mst_ar_data_i ( axi_mst_ext_ar_data ), - .axi_ext_mst_ar_wptr_i ( axi_mst_ext_ar_wptr ), - .axi_ext_mst_ar_rptr_o ( axi_mst_ext_ar_rptr ), - .axi_ext_mst_aw_data_i ( axi_mst_ext_aw_data ), - .axi_ext_mst_aw_wptr_i ( axi_mst_ext_aw_wptr ), - .axi_ext_mst_aw_rptr_o ( axi_mst_ext_aw_rptr ), - .axi_ext_mst_b_data_o ( axi_mst_ext_b_data ), - .axi_ext_mst_b_wptr_o ( axi_mst_ext_b_wptr ), - .axi_ext_mst_b_rptr_i ( axi_mst_ext_b_rptr ), - .axi_ext_mst_r_data_o ( axi_mst_ext_r_data ), - .axi_ext_mst_r_wptr_o ( axi_mst_ext_r_wptr ), - .axi_ext_mst_r_rptr_i ( axi_mst_ext_r_rptr ), - .axi_ext_mst_w_data_i ( axi_mst_ext_w_data ), - .axi_ext_mst_w_wptr_i ( axi_mst_ext_w_wptr ), - .axi_ext_mst_w_rptr_o ( axi_mst_ext_w_rptr ), - // Mailboxes - .axi_mbox_slv_req_o ( axi_mbox_req ), - .axi_mbox_slv_rsp_i ( axi_mbox_rsp ), + .axi_ext_mst_req_i ( cheshire_mst_req ), + .axi_ext_mst_rsp_o ( cheshire_mst_rsp ), // External reg demux slaves Cheshire's clock domain (sync) .reg_ext_slv_req_o ( ext_reg_req ), .reg_ext_slv_rsp_i ( ext_reg_rsp ), @@ -963,13 +1023,13 @@ assign hyper_isolate_req = car_regs_reg2hw.periph_isolate.q; .RstChipSpace ( HypNumPhys * HypNumChips * 'h800_0000 ), .PhyStartupCycles ( 300 * 200 ), .AxiLogDepth ( LogDepth ), - .AxiSlaveArWidth ( LlcArWidth ), - .AxiSlaveAwWidth ( LlcAwWidth ), - .AxiSlaveBWidth ( LlcBWidth ), - .AxiSlaveRWidth ( LlcRWidth ), - .AxiSlaveWWidth ( LlcWWidth ), - .AxiMaxTrans ( Cfg.AxiMaxSlvTrans ), - .CdcSyncStages ( SyncStages ) + .AxiSlaveArWidth ( LlcArWidth ), + .AxiSlaveAwWidth ( LlcAwWidth ), + .AxiSlaveBWidth ( LlcBWidth ), + .AxiSlaveRWidth ( LlcRWidth ), + .AxiSlaveWWidth ( LlcWWidth ), + .AxiMaxTrans ( Cfg.AxiMaxSlvTrans ), + .CdcSyncStages ( SyncStages ) ) i_hyperbus_wrap ( .clk_i ( hyp_clk ), .rst_ni ( periph_rst_n ), @@ -1059,9 +1119,9 @@ if (CarfieldIslandsCfg.l2_port0.enable) begin: gen_l2 .NumPort ( NumL2Ports ), .AxiAddrWidth ( Cfg.AddrWidth ), .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiIdWidth ( AxiSlvIdWidth ), + .AxiIdWidth ( Cfg.AxiMstIdWidth ), .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiMaxTrans ( Cfg.AxiMaxSlvTrans ), + .AxiMaxTrans ( Cfg.AxiMaxMstTrans ), .LogDepth ( LogDepth ), .CdcSyncStages( SyncStages ), .NumRules ( L2NumRules ), @@ -1083,21 +1143,21 @@ if (CarfieldIslandsCfg.l2_port0.enable) begin: gen_l2 .clk_i ( l2_clk ), .rst_ni ( l2_rst_n ), .pwr_on_rst_ni ( l2_pwr_on_rst_n ), - .slvport_ar_data_i ( axi_slv_ext_ar_data [NumL2Ports-1:0] ), - .slvport_ar_wptr_i ( axi_slv_ext_ar_wptr [NumL2Ports-1:0] ), - .slvport_ar_rptr_o ( axi_slv_ext_ar_rptr [NumL2Ports-1:0] ), - .slvport_aw_data_i ( axi_slv_ext_aw_data [NumL2Ports-1:0] ), - .slvport_aw_wptr_i ( axi_slv_ext_aw_wptr [NumL2Ports-1:0] ), - .slvport_aw_rptr_o ( axi_slv_ext_aw_rptr [NumL2Ports-1:0] ), - .slvport_b_data_o ( axi_slv_ext_b_data [NumL2Ports-1:0] ), - .slvport_b_wptr_o ( axi_slv_ext_b_wptr [NumL2Ports-1:0] ), - .slvport_b_rptr_i ( axi_slv_ext_b_rptr [NumL2Ports-1:0] ), - .slvport_r_data_o ( axi_slv_ext_r_data [NumL2Ports-1:0] ), - .slvport_r_wptr_o ( axi_slv_ext_r_wptr [NumL2Ports-1:0] ), - .slvport_r_rptr_i ( axi_slv_ext_r_rptr [NumL2Ports-1:0] ), - .slvport_w_data_i ( axi_slv_ext_w_data [NumL2Ports-1:0] ), - .slvport_w_wptr_i ( axi_slv_ext_w_wptr [NumL2Ports-1:0] ), - .slvport_w_rptr_o ( axi_slv_ext_w_rptr [NumL2Ports-1:0] ), + .slvport_ar_data_i ( axi_mst_ext_ar_data [L2PortId:L2Port0SlvIdx] ), + .slvport_ar_wptr_i ( axi_mst_ext_ar_wptr [L2PortId:L2Port0SlvIdx] ), + .slvport_ar_rptr_o ( axi_mst_ext_ar_rptr [L2PortId:L2Port0SlvIdx] ), + .slvport_aw_data_i ( axi_mst_ext_aw_data [L2PortId:L2Port0SlvIdx] ), + .slvport_aw_wptr_i ( axi_mst_ext_aw_wptr [L2PortId:L2Port0SlvIdx] ), + .slvport_aw_rptr_o ( axi_mst_ext_aw_rptr [L2PortId:L2Port0SlvIdx] ), + .slvport_b_data_o ( axi_mst_ext_b_data [L2PortId:L2Port0SlvIdx] ), + .slvport_b_wptr_o ( axi_mst_ext_b_wptr [L2PortId:L2Port0SlvIdx] ), + .slvport_b_rptr_i ( axi_mst_ext_b_rptr [L2PortId:L2Port0SlvIdx] ), + .slvport_r_data_o ( axi_mst_ext_r_data [L2PortId:L2Port0SlvIdx] ), + .slvport_r_wptr_o ( axi_mst_ext_r_wptr [L2PortId:L2Port0SlvIdx] ), + .slvport_r_rptr_i ( axi_mst_ext_r_rptr [L2PortId:L2Port0SlvIdx] ), + .slvport_w_data_i ( axi_mst_ext_w_data [L2PortId:L2Port0SlvIdx] ), + .slvport_w_wptr_i ( axi_mst_ext_w_wptr [L2PortId:L2Port0SlvIdx] ), + .slvport_w_rptr_o ( axi_mst_ext_w_rptr [L2PortId:L2Port0SlvIdx] ), .l2_ecc_reg_async_mst_req_i ( ext_reg_async_slv_req_out [EccAsyncIdx] ), .l2_ecc_reg_async_mst_ack_o ( ext_reg_async_slv_ack_in [EccAsyncIdx] ), .l2_ecc_reg_async_mst_data_i ( ext_reg_async_slv_data_out[EccAsyncIdx] ), @@ -1200,8 +1260,8 @@ if (CarfieldIslandsCfg.safed.enable) begin : gen_safety_island .AxiAddrWidth ( Cfg.AddrWidth ), .AxiDataWidth ( Cfg.AxiDataWidth ), .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiInIdWidth ( AxiSlvIdWidth ), - .AxiOutIdWidth ( Cfg.AxiMstIdWidth ), + .AxiInIdWidth ( Cfg.AxiMstIdWidth ), + .AxiOutIdWidth ( AxiSlvIdWidth ), .AxiUserAtop ( 1'b1 ), .AxiUserAtopMsb ( Cfg.AxiUserAmoMsb ), @@ -1223,33 +1283,33 @@ if (CarfieldIslandsCfg.safed.enable) begin : gen_safety_island .SelectableHarts ( SafetyIslandExtHarts ), .HartInfo ( SafetyIslandExtHartinfo ), - .axi_in_aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .axi_in_w_chan_t ( carfield_axi_slv_w_chan_t ), - .axi_in_b_chan_t ( carfield_axi_slv_b_chan_t ), - .axi_in_ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .axi_in_r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_in_req_t ( carfield_axi_slv_req_t ), - .axi_in_resp_t ( carfield_axi_slv_rsp_t ), - - .axi_out_aw_chan_t ( carfield_axi_mst_aw_chan_t ), - .axi_out_w_chan_t ( carfield_axi_mst_w_chan_t ), - .axi_out_b_chan_t ( carfield_axi_mst_b_chan_t ), - .axi_out_ar_chan_t ( carfield_axi_mst_ar_chan_t ), - .axi_out_r_chan_t ( carfield_axi_mst_r_chan_t ), - .axi_out_req_t ( carfield_axi_mst_req_t ), - .axi_out_resp_t ( carfield_axi_mst_rsp_t ), - - .AsyncAxiInAwWidth ( CarfieldAxiSlvAwWidth ), - .AsyncAxiInWWidth ( CarfieldAxiSlvWWidth ), - .AsyncAxiInBWidth ( CarfieldAxiSlvBWidth ), - .AsyncAxiInArWidth ( CarfieldAxiSlvArWidth ), - .AsyncAxiInRWidth ( CarfieldAxiSlvRWidth ), - - .AsyncAxiOutAwWidth ( CarfieldAxiMstAwWidth ), - .AsyncAxiOutWWidth ( CarfieldAxiMstWWidth ), - .AsyncAxiOutBWidth ( CarfieldAxiMstBWidth ), - .AsyncAxiOutArWidth ( CarfieldAxiMstArWidth ), - .AsyncAxiOutRWidth ( CarfieldAxiMstRWidth ) + .axi_in_aw_chan_t ( carfield_axi_mst_aw_chan_t ), + .axi_in_w_chan_t ( carfield_axi_mst_w_chan_t ), + .axi_in_b_chan_t ( carfield_axi_mst_b_chan_t ), + .axi_in_ar_chan_t ( carfield_axi_mst_ar_chan_t ), + .axi_in_r_chan_t ( carfield_axi_mst_r_chan_t ), + .axi_in_req_t ( carfield_axi_mst_req_t ), + .axi_in_resp_t ( carfield_axi_mst_rsp_t ), + + .axi_out_aw_chan_t ( carfield_axi_slv_aw_chan_t ), + .axi_out_w_chan_t ( carfield_axi_slv_w_chan_t ), + .axi_out_b_chan_t ( carfield_axi_slv_b_chan_t ), + .axi_out_ar_chan_t ( carfield_axi_slv_ar_chan_t ), + .axi_out_r_chan_t ( carfield_axi_slv_r_chan_t ), + .axi_out_req_t ( carfield_axi_slv_req_t ), + .axi_out_resp_t ( carfield_axi_slv_rsp_t ), + + .AsyncAxiInAwWidth ( CarfieldAxiMstAwWidth ), + .AsyncAxiInWWidth ( CarfieldAxiMstWWidth ), + .AsyncAxiInBWidth ( CarfieldAxiMstBWidth ), + .AsyncAxiInArWidth ( CarfieldAxiMstArWidth ), + .AsyncAxiInRWidth ( CarfieldAxiMstRWidth ), + + .AsyncAxiOutAwWidth ( CarfieldAxiSlvAwWidth ), + .AsyncAxiOutWWidth ( CarfieldAxiSlvWWidth ), + .AsyncAxiOutBWidth ( CarfieldAxiSlvBWidth ), + .AsyncAxiOutArWidth ( CarfieldAxiSlvArWidth ), + .AsyncAxiOutRWidth ( CarfieldAxiSlvRWidth ) ) i_safety_island_wrap ( `else safety_island i_safety_island_wrap ( @@ -1271,37 +1331,37 @@ if (CarfieldIslandsCfg.safed.enable) begin : gen_safety_island .jtag_tdi_i ( jtag_safety_island_tdi_i ), .jtag_tdo_o ( jtag_safety_island_tdo_o ), // Slave port - .async_axi_in_aw_data_i ( axi_slv_ext_aw_data [SafetyIslandSlvIdx] ), - .async_axi_in_aw_wptr_i ( axi_slv_ext_aw_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_aw_rptr_o ( axi_slv_ext_aw_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_w_data_i ( axi_slv_ext_w_data [SafetyIslandSlvIdx] ), - .async_axi_in_w_wptr_i ( axi_slv_ext_w_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_w_rptr_o ( axi_slv_ext_w_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_b_data_o ( axi_slv_ext_b_data [SafetyIslandSlvIdx] ), - .async_axi_in_b_wptr_o ( axi_slv_ext_b_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_b_rptr_i ( axi_slv_ext_b_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_ar_data_i ( axi_slv_ext_ar_data [SafetyIslandSlvIdx] ), - .async_axi_in_ar_wptr_i ( axi_slv_ext_ar_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_ar_rptr_o ( axi_slv_ext_ar_rptr [SafetyIslandSlvIdx] ), - .async_axi_in_r_data_o ( axi_slv_ext_r_data [SafetyIslandSlvIdx] ), - .async_axi_in_r_wptr_o ( axi_slv_ext_r_wptr [SafetyIslandSlvIdx] ), - .async_axi_in_r_rptr_i ( axi_slv_ext_r_rptr [SafetyIslandSlvIdx] ), + .async_axi_in_aw_data_i ( axi_mst_ext_aw_data [SafetyIslandSlvIdx] ), + .async_axi_in_aw_wptr_i ( axi_mst_ext_aw_wptr [SafetyIslandSlvIdx] ), + .async_axi_in_aw_rptr_o ( axi_mst_ext_aw_rptr [SafetyIslandSlvIdx] ), + .async_axi_in_w_data_i ( axi_mst_ext_w_data [SafetyIslandSlvIdx] ), + .async_axi_in_w_wptr_i ( axi_mst_ext_w_wptr [SafetyIslandSlvIdx] ), + .async_axi_in_w_rptr_o ( axi_mst_ext_w_rptr [SafetyIslandSlvIdx] ), + .async_axi_in_b_data_o ( axi_mst_ext_b_data [SafetyIslandSlvIdx] ), + .async_axi_in_b_wptr_o ( axi_mst_ext_b_wptr [SafetyIslandSlvIdx] ), + .async_axi_in_b_rptr_i ( axi_mst_ext_b_rptr [SafetyIslandSlvIdx] ), + .async_axi_in_ar_data_i ( axi_mst_ext_ar_data [SafetyIslandSlvIdx] ), + .async_axi_in_ar_wptr_i ( axi_mst_ext_ar_wptr [SafetyIslandSlvIdx] ), + .async_axi_in_ar_rptr_o ( axi_mst_ext_ar_rptr [SafetyIslandSlvIdx] ), + .async_axi_in_r_data_o ( axi_mst_ext_r_data [SafetyIslandSlvIdx] ), + .async_axi_in_r_wptr_o ( axi_mst_ext_r_wptr [SafetyIslandSlvIdx] ), + .async_axi_in_r_rptr_i ( axi_mst_ext_r_rptr [SafetyIslandSlvIdx] ), // Master port - .async_axi_out_aw_data_o ( axi_mst_ext_aw_data [SafetyIslandMstIdx] ), - .async_axi_out_aw_wptr_o ( axi_mst_ext_aw_wptr [SafetyIslandMstIdx] ), - .async_axi_out_aw_rptr_i ( axi_mst_ext_aw_rptr [SafetyIslandMstIdx] ), - .async_axi_out_w_data_o ( axi_mst_ext_w_data [SafetyIslandMstIdx] ), - .async_axi_out_w_wptr_o ( axi_mst_ext_w_wptr [SafetyIslandMstIdx] ), - .async_axi_out_w_rptr_i ( axi_mst_ext_w_rptr [SafetyIslandMstIdx] ), - .async_axi_out_b_data_i ( axi_mst_ext_b_data [SafetyIslandMstIdx] ), - .async_axi_out_b_wptr_i ( axi_mst_ext_b_wptr [SafetyIslandMstIdx] ), - .async_axi_out_b_rptr_o ( axi_mst_ext_b_rptr [SafetyIslandMstIdx] ), - .async_axi_out_ar_data_o ( axi_mst_ext_ar_data [SafetyIslandMstIdx] ), - .async_axi_out_ar_wptr_o ( axi_mst_ext_ar_wptr [SafetyIslandMstIdx] ), - .async_axi_out_ar_rptr_i ( axi_mst_ext_ar_rptr [SafetyIslandMstIdx] ), - .async_axi_out_r_data_i ( axi_mst_ext_r_data [SafetyIslandMstIdx] ), - .async_axi_out_r_wptr_i ( axi_mst_ext_r_wptr [SafetyIslandMstIdx] ), - .async_axi_out_r_rptr_o ( axi_mst_ext_r_rptr [SafetyIslandMstIdx] ) + .async_axi_out_aw_data_o ( axi_slv_ext_aw_data [SafetyIslandMstIdx] ), + .async_axi_out_aw_wptr_o ( axi_slv_ext_aw_wptr [SafetyIslandMstIdx] ), + .async_axi_out_aw_rptr_i ( axi_slv_ext_aw_rptr [SafetyIslandMstIdx] ), + .async_axi_out_w_data_o ( axi_slv_ext_w_data [SafetyIslandMstIdx] ), + .async_axi_out_w_wptr_o ( axi_slv_ext_w_wptr [SafetyIslandMstIdx] ), + .async_axi_out_w_rptr_i ( axi_slv_ext_w_rptr [SafetyIslandMstIdx] ), + .async_axi_out_b_data_i ( axi_slv_ext_b_data [SafetyIslandMstIdx] ), + .async_axi_out_b_wptr_i ( axi_slv_ext_b_wptr [SafetyIslandMstIdx] ), + .async_axi_out_b_rptr_o ( axi_slv_ext_b_rptr [SafetyIslandMstIdx] ), + .async_axi_out_ar_data_o ( axi_slv_ext_ar_data [SafetyIslandMstIdx] ), + .async_axi_out_ar_wptr_o ( axi_slv_ext_ar_wptr [SafetyIslandMstIdx] ), + .async_axi_out_ar_rptr_i ( axi_slv_ext_ar_rptr [SafetyIslandMstIdx] ), + .async_axi_out_r_data_i ( axi_slv_ext_r_data [SafetyIslandMstIdx] ), + .async_axi_out_r_wptr_i ( axi_slv_ext_r_wptr [SafetyIslandMstIdx] ), + .async_axi_out_r_rptr_o ( axi_slv_ext_r_rptr [SafetyIslandMstIdx] ) ); end else begin : gen_no_safety_island @@ -1390,14 +1450,14 @@ localparam pulp_cluster_package::pulp_cluster_cfg_t PulpClusterCfg = '{ NumSharedFpu: 0, NumAxiIn: 4, NumAxiOut: 3, - AxiIdInWidth: AxiSlvIdWidth, - AxiIdOutWidth: Cfg.AxiMstIdWidth, + AxiIdInWidth: Cfg.AxiMstIdWidth, + AxiIdOutWidth: AxiSlvIdWidth, AxiAddrWidth: Cfg.AddrWidth, AxiDataInWidth: Cfg.AxiDataWidth, AxiDataOutWidth: Cfg.AxiDataWidth, AxiUserWidth: Cfg.AxiUserWidth, - AxiMaxInTrans: Cfg.AxiMaxSlvTrans, - AxiMaxOutTrans: Cfg.AxiMaxMstTrans, + AxiMaxInTrans: Cfg.AxiMaxMstTrans, + AxiMaxOutTrans: Cfg.AxiMaxSlvTrans, AxiCdcLogDepth: 3, AxiCdcSyncStages: carfield_pkg::SyncStages, SyncStages: carfield_pkg::SyncStages, @@ -1441,37 +1501,37 @@ localparam pulp_cluster_package::pulp_cluster_cfg_t PulpClusterCfg = '{ .async_cluster_events_rptr_o ( ), .async_cluster_events_data_i ( '0 ), // AXI4 Slave port - .async_data_slave_aw_data_i ( axi_slv_ext_aw_data [IntClusterSlvIdx] ), - .async_data_slave_aw_wptr_i ( axi_slv_ext_aw_wptr [IntClusterSlvIdx] ), - .async_data_slave_aw_rptr_o ( axi_slv_ext_aw_rptr [IntClusterSlvIdx] ), - .async_data_slave_ar_data_i ( axi_slv_ext_ar_data [IntClusterSlvIdx] ), - .async_data_slave_ar_wptr_i ( axi_slv_ext_ar_wptr [IntClusterSlvIdx] ), - .async_data_slave_ar_rptr_o ( axi_slv_ext_ar_rptr [IntClusterSlvIdx] ), - .async_data_slave_w_data_i ( axi_slv_ext_w_data [IntClusterSlvIdx] ), - .async_data_slave_w_wptr_i ( axi_slv_ext_w_wptr [IntClusterSlvIdx] ), - .async_data_slave_w_rptr_o ( axi_slv_ext_w_rptr [IntClusterSlvIdx] ), - .async_data_slave_r_data_o ( axi_slv_ext_r_data [IntClusterSlvIdx] ), - .async_data_slave_r_wptr_o ( axi_slv_ext_r_wptr [IntClusterSlvIdx] ), - .async_data_slave_r_rptr_i ( axi_slv_ext_r_rptr [IntClusterSlvIdx] ), - .async_data_slave_b_data_o ( axi_slv_ext_b_data [IntClusterSlvIdx] ), - .async_data_slave_b_wptr_o ( axi_slv_ext_b_wptr [IntClusterSlvIdx] ), - .async_data_slave_b_rptr_i ( axi_slv_ext_b_rptr [IntClusterSlvIdx] ), + .async_data_slave_aw_data_i ( axi_mst_ext_aw_data [IntClusterSlvIdx] ), + .async_data_slave_aw_wptr_i ( axi_mst_ext_aw_wptr [IntClusterSlvIdx] ), + .async_data_slave_aw_rptr_o ( axi_mst_ext_aw_rptr [IntClusterSlvIdx] ), + .async_data_slave_ar_data_i ( axi_mst_ext_ar_data [IntClusterSlvIdx] ), + .async_data_slave_ar_wptr_i ( axi_mst_ext_ar_wptr [IntClusterSlvIdx] ), + .async_data_slave_ar_rptr_o ( axi_mst_ext_ar_rptr [IntClusterSlvIdx] ), + .async_data_slave_w_data_i ( axi_mst_ext_w_data [IntClusterSlvIdx] ), + .async_data_slave_w_wptr_i ( axi_mst_ext_w_wptr [IntClusterSlvIdx] ), + .async_data_slave_w_rptr_o ( axi_mst_ext_w_rptr [IntClusterSlvIdx] ), + .async_data_slave_r_data_o ( axi_mst_ext_r_data [IntClusterSlvIdx] ), + .async_data_slave_r_wptr_o ( axi_mst_ext_r_wptr [IntClusterSlvIdx] ), + .async_data_slave_r_rptr_i ( axi_mst_ext_r_rptr [IntClusterSlvIdx] ), + .async_data_slave_b_data_o ( axi_mst_ext_b_data [IntClusterSlvIdx] ), + .async_data_slave_b_wptr_o ( axi_mst_ext_b_wptr [IntClusterSlvIdx] ), + .async_data_slave_b_rptr_i ( axi_mst_ext_b_rptr [IntClusterSlvIdx] ), // AXI4 Master Port - .async_data_master_aw_data_o ( axi_mst_ext_aw_data [IntClusterMstIdx] ), - .async_data_master_aw_wptr_o ( axi_mst_ext_aw_wptr [IntClusterMstIdx] ), - .async_data_master_aw_rptr_i ( axi_mst_ext_aw_rptr [IntClusterMstIdx] ), - .async_data_master_ar_data_o ( axi_mst_ext_ar_data [IntClusterMstIdx] ), - .async_data_master_ar_wptr_o ( axi_mst_ext_ar_wptr [IntClusterMstIdx] ), - .async_data_master_ar_rptr_i ( axi_mst_ext_ar_rptr [IntClusterMstIdx] ), - .async_data_master_w_data_o ( axi_mst_ext_w_data [IntClusterMstIdx] ), - .async_data_master_w_wptr_o ( axi_mst_ext_w_wptr [IntClusterMstIdx] ), - .async_data_master_w_rptr_i ( axi_mst_ext_w_rptr [IntClusterMstIdx] ), - .async_data_master_r_data_i ( axi_mst_ext_r_data [IntClusterMstIdx] ), - .async_data_master_r_wptr_i ( axi_mst_ext_r_wptr [IntClusterMstIdx] ), - .async_data_master_r_rptr_o ( axi_mst_ext_r_rptr [IntClusterMstIdx] ), - .async_data_master_b_data_i ( axi_mst_ext_b_data [IntClusterMstIdx] ), - .async_data_master_b_wptr_i ( axi_mst_ext_b_wptr [IntClusterMstIdx] ), - .async_data_master_b_rptr_o ( axi_mst_ext_b_rptr [IntClusterMstIdx] ) + .async_data_master_aw_data_o ( axi_slv_ext_aw_data [IntClusterMstIdx] ), + .async_data_master_aw_wptr_o ( axi_slv_ext_aw_wptr [IntClusterMstIdx] ), + .async_data_master_aw_rptr_i ( axi_slv_ext_aw_rptr [IntClusterMstIdx] ), + .async_data_master_ar_data_o ( axi_slv_ext_ar_data [IntClusterMstIdx] ), + .async_data_master_ar_wptr_o ( axi_slv_ext_ar_wptr [IntClusterMstIdx] ), + .async_data_master_ar_rptr_i ( axi_slv_ext_ar_rptr [IntClusterMstIdx] ), + .async_data_master_w_data_o ( axi_slv_ext_w_data [IntClusterMstIdx] ), + .async_data_master_w_wptr_o ( axi_slv_ext_w_wptr [IntClusterMstIdx] ), + .async_data_master_w_rptr_i ( axi_slv_ext_w_rptr [IntClusterMstIdx] ), + .async_data_master_r_data_i ( axi_slv_ext_r_data [IntClusterMstIdx] ), + .async_data_master_r_wptr_i ( axi_slv_ext_r_wptr [IntClusterMstIdx] ), + .async_data_master_r_rptr_o ( axi_slv_ext_r_rptr [IntClusterMstIdx] ), + .async_data_master_b_data_i ( axi_slv_ext_b_data [IntClusterMstIdx] ), + .async_data_master_b_wptr_i ( axi_slv_ext_b_wptr [IntClusterMstIdx] ), + .async_data_master_b_rptr_o ( axi_slv_ext_b_rptr [IntClusterMstIdx] ) ); for (genvar i = 0; i < CheshireNumIntHarts; i++ ) begin : gen_pulpcl_mbox_intrs @@ -1549,41 +1609,41 @@ if (CarfieldIslandsCfg.spatz.enable) begin : gen_spatz_cluster .AxiAddrWidth ( Cfg.AddrWidth ), .AxiDataWidth ( Cfg.AxiDataWidth ), .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiInIdWidth ( AxiSlvIdWidth ), - .AxiOutIdWidth ( Cfg.AxiMstIdWidth ), + .AxiInIdWidth ( Cfg.AxiMstIdWidth ), + .AxiOutIdWidth ( AxiSlvIdWidth ), .IwcAxiIdOutWidth ( 3 ), .LogDepth ( LogDepth ), .CdcSyncStages ( SyncStages ), .SyncStages ( SyncStages ), .AxiMaxOutTrans ( 4 ), // AXI type IN - .axi_in_resp_t ( carfield_axi_slv_rsp_t ), - .axi_in_req_t ( carfield_axi_slv_req_t ), - .axi_in_aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .axi_in_w_chan_t ( carfield_axi_slv_w_chan_t ), - .axi_in_b_chan_t ( carfield_axi_slv_b_chan_t ), - .axi_in_ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .axi_in_r_chan_t ( carfield_axi_slv_r_chan_t ), + .axi_in_resp_t ( carfield_axi_mst_rsp_t ), + .axi_in_req_t ( carfield_axi_mst_req_t ), + .axi_in_aw_chan_t ( carfield_axi_mst_aw_chan_t ), + .axi_in_w_chan_t ( carfield_axi_mst_w_chan_t ), + .axi_in_b_chan_t ( carfield_axi_mst_b_chan_t ), + .axi_in_ar_chan_t ( carfield_axi_mst_ar_chan_t ), + .axi_in_r_chan_t ( carfield_axi_mst_r_chan_t ), // AXI type OUT - .axi_out_resp_t ( carfield_axi_mst_rsp_t ), - .axi_out_req_t ( carfield_axi_mst_req_t ), - .axi_out_aw_chan_t ( carfield_axi_mst_aw_chan_t ), - .axi_out_w_chan_t ( carfield_axi_mst_w_chan_t ), - .axi_out_b_chan_t ( carfield_axi_mst_b_chan_t ), - .axi_out_ar_chan_t ( carfield_axi_mst_ar_chan_t ), - .axi_out_r_chan_t ( carfield_axi_mst_r_chan_t ), + .axi_out_resp_t ( carfield_axi_slv_rsp_t ), + .axi_out_req_t ( carfield_axi_slv_req_t ), + .axi_out_aw_chan_t ( carfield_axi_slv_aw_chan_t ), + .axi_out_w_chan_t ( carfield_axi_slv_w_chan_t ), + .axi_out_b_chan_t ( carfield_axi_slv_b_chan_t ), + .axi_out_ar_chan_t ( carfield_axi_slv_ar_chan_t ), + .axi_out_r_chan_t ( carfield_axi_slv_r_chan_t ), //CDC AXI Slv parameters - .AsyncAxiInAwWidth ( CarfieldAxiSlvAwWidth ), - .AsyncAxiInWWidth ( CarfieldAxiSlvWWidth ), - .AsyncAxiInBWidth ( CarfieldAxiSlvBWidth ), - .AsyncAxiInArWidth ( CarfieldAxiSlvArWidth ), - .AsyncAxiInRWidth ( CarfieldAxiSlvRWidth ), + .AsyncAxiInAwWidth ( CarfieldAxiMstAwWidth ), + .AsyncAxiInWWidth ( CarfieldAxiMstWWidth ), + .AsyncAxiInBWidth ( CarfieldAxiMstBWidth ), + .AsyncAxiInArWidth ( CarfieldAxiMstArWidth ), + .AsyncAxiInRWidth ( CarfieldAxiMstRWidth ), //CDC AXI Mst parameters - .AsyncAxiOutAwWidth ( CarfieldAxiMstAwWidth ), - .AsyncAxiOutWWidth ( CarfieldAxiMstWWidth ), - .AsyncAxiOutBWidth ( CarfieldAxiMstBWidth ), - .AsyncAxiOutArWidth ( CarfieldAxiMstArWidth ), - .AsyncAxiOutRWidth ( CarfieldAxiMstRWidth ) + .AsyncAxiOutAwWidth ( CarfieldAxiSlvAwWidth ), + .AsyncAxiOutWWidth ( CarfieldAxiSlvWWidth ), + .AsyncAxiOutBWidth ( CarfieldAxiSlvBWidth ), + .AsyncAxiOutArWidth ( CarfieldAxiSlvArWidth ), + .AsyncAxiOutRWidth ( CarfieldAxiSlvRWidth ) ) i_fp_cluster_wrapper ( `else spatz_cluster_wrapper i_fp_cluster_wrapper ( @@ -1599,38 +1659,38 @@ if (CarfieldIslandsCfg.spatz.enable) begin : gen_spatz_cluster .axi_isolate_i ( slave_isolate_req [FPClusterSlvIdx] ), .axi_isolated_o ( master_isolated_rsp [FPClusterMstIdx] ), - //AXI FP Cluster Slave Port <- Carfield Master Port - .async_axi_in_aw_data_i ( axi_slv_ext_aw_data [FPClusterSlvIdx] ), - .async_axi_in_aw_wptr_i ( axi_slv_ext_aw_wptr [FPClusterSlvIdx] ), - .async_axi_in_aw_rptr_o ( axi_slv_ext_aw_rptr [FPClusterSlvIdx] ), - .async_axi_in_w_data_i ( axi_slv_ext_w_data [FPClusterSlvIdx] ), - .async_axi_in_w_wptr_i ( axi_slv_ext_w_wptr [FPClusterSlvIdx] ), - .async_axi_in_w_rptr_o ( axi_slv_ext_w_rptr [FPClusterSlvIdx] ), - .async_axi_in_b_data_o ( axi_slv_ext_b_data [FPClusterSlvIdx] ), - .async_axi_in_b_wptr_o ( axi_slv_ext_b_wptr [FPClusterSlvIdx] ), - .async_axi_in_b_rptr_i ( axi_slv_ext_b_rptr [FPClusterSlvIdx] ), - .async_axi_in_ar_data_i ( axi_slv_ext_ar_data [FPClusterSlvIdx] ), - .async_axi_in_ar_wptr_i ( axi_slv_ext_ar_wptr [FPClusterSlvIdx] ), - .async_axi_in_ar_rptr_o ( axi_slv_ext_ar_rptr [FPClusterSlvIdx] ), - .async_axi_in_r_data_o ( axi_slv_ext_r_data [FPClusterSlvIdx] ), - .async_axi_in_r_wptr_o ( axi_slv_ext_r_wptr [FPClusterSlvIdx] ), - .async_axi_in_r_rptr_i ( axi_slv_ext_r_rptr [FPClusterSlvIdx] ), - //AXI FP Cluster Master Port -> Carfield Slave Port - .async_axi_out_aw_data_o ( axi_mst_ext_aw_data [FPClusterMstIdx] ), - .async_axi_out_aw_wptr_o ( axi_mst_ext_aw_wptr [FPClusterMstIdx] ), - .async_axi_out_aw_rptr_i ( axi_mst_ext_aw_rptr [FPClusterMstIdx] ), - .async_axi_out_w_data_o ( axi_mst_ext_w_data [FPClusterMstIdx] ), - .async_axi_out_w_wptr_o ( axi_mst_ext_w_wptr [FPClusterMstIdx] ), - .async_axi_out_w_rptr_i ( axi_mst_ext_w_rptr [FPClusterMstIdx] ), - .async_axi_out_b_data_i ( axi_mst_ext_b_data [FPClusterMstIdx] ), - .async_axi_out_b_wptr_i ( axi_mst_ext_b_wptr [FPClusterMstIdx] ), - .async_axi_out_b_rptr_o ( axi_mst_ext_b_rptr [FPClusterMstIdx] ), - .async_axi_out_ar_data_o ( axi_mst_ext_ar_data [FPClusterMstIdx] ), - .async_axi_out_ar_wptr_o ( axi_mst_ext_ar_wptr [FPClusterMstIdx] ), - .async_axi_out_ar_rptr_i ( axi_mst_ext_ar_rptr [FPClusterMstIdx] ), - .async_axi_out_r_data_i ( axi_mst_ext_r_data [FPClusterMstIdx] ), - .async_axi_out_r_wptr_i ( axi_mst_ext_r_wptr [FPClusterMstIdx] ), - .async_axi_out_r_rptr_o ( axi_mst_ext_r_rptr [FPClusterMstIdx] ), + // AXI FP Cluster Slave Port <- Carfield Master Port + .async_axi_in_aw_data_i ( axi_mst_ext_aw_data [FPClusterSlvIdx] ), + .async_axi_in_aw_wptr_i ( axi_mst_ext_aw_wptr [FPClusterSlvIdx] ), + .async_axi_in_aw_rptr_o ( axi_mst_ext_aw_rptr [FPClusterSlvIdx] ), + .async_axi_in_w_data_i ( axi_mst_ext_w_data [FPClusterSlvIdx] ), + .async_axi_in_w_wptr_i ( axi_mst_ext_w_wptr [FPClusterSlvIdx] ), + .async_axi_in_w_rptr_o ( axi_mst_ext_w_rptr [FPClusterSlvIdx] ), + .async_axi_in_b_data_o ( axi_mst_ext_b_data [FPClusterSlvIdx] ), + .async_axi_in_b_wptr_o ( axi_mst_ext_b_wptr [FPClusterSlvIdx] ), + .async_axi_in_b_rptr_i ( axi_mst_ext_b_rptr [FPClusterSlvIdx] ), + .async_axi_in_ar_data_i ( axi_mst_ext_ar_data [FPClusterSlvIdx] ), + .async_axi_in_ar_wptr_i ( axi_mst_ext_ar_wptr [FPClusterSlvIdx] ), + .async_axi_in_ar_rptr_o ( axi_mst_ext_ar_rptr [FPClusterSlvIdx] ), + .async_axi_in_r_data_o ( axi_mst_ext_r_data [FPClusterSlvIdx] ), + .async_axi_in_r_wptr_o ( axi_mst_ext_r_wptr [FPClusterSlvIdx] ), + .async_axi_in_r_rptr_i ( axi_mst_ext_r_rptr [FPClusterSlvIdx] ), + // AXI FP Cluster Master Port -> Carfield Slave Port + .async_axi_out_aw_data_o ( axi_slv_ext_aw_data [FPClusterMstIdx] ), + .async_axi_out_aw_wptr_o ( axi_slv_ext_aw_wptr [FPClusterMstIdx] ), + .async_axi_out_aw_rptr_i ( axi_slv_ext_aw_rptr [FPClusterMstIdx] ), + .async_axi_out_w_data_o ( axi_slv_ext_w_data [FPClusterMstIdx] ), + .async_axi_out_w_wptr_o ( axi_slv_ext_w_wptr [FPClusterMstIdx] ), + .async_axi_out_w_rptr_i ( axi_slv_ext_w_rptr [FPClusterMstIdx] ), + .async_axi_out_b_data_i ( axi_slv_ext_b_data [FPClusterMstIdx] ), + .async_axi_out_b_wptr_i ( axi_slv_ext_b_wptr [FPClusterMstIdx] ), + .async_axi_out_b_rptr_o ( axi_slv_ext_b_rptr [FPClusterMstIdx] ), + .async_axi_out_ar_data_o ( axi_slv_ext_ar_data [FPClusterMstIdx] ), + .async_axi_out_ar_wptr_o ( axi_slv_ext_ar_wptr [FPClusterMstIdx] ), + .async_axi_out_ar_rptr_i ( axi_slv_ext_ar_rptr [FPClusterMstIdx] ), + .async_axi_out_r_data_i ( axi_slv_ext_r_data [FPClusterMstIdx] ), + .async_axi_out_r_wptr_i ( axi_slv_ext_r_wptr [FPClusterMstIdx] ), + .async_axi_out_r_rptr_o ( axi_slv_ext_r_rptr [FPClusterMstIdx] ), .cluster_probe_o ( car_regs_hw2reg.spatz_cluster_busy.d ) ); @@ -1713,9 +1773,9 @@ if (CarfieldIslandsCfg.secured.enable) begin : gen_secure_subsystem typedef logic [AxiNarrowDataWidth-1:0] narrow_axi_data_t; typedef logic [AxiNarrowDataWidth/8-1:0] narrow_axi_strb_t; typedef logic [Cfg.AxiUserWidth-1:0] narrow_axi_user_t; - typedef logic [Cfg.AxiMstIdWidth-1:0] narrow_axi_out_id_t; + typedef logic [AxiSlvIdWidth-1:0] narrow_axi_out_id_t; - `AXI_TYPEDEF_ALL(carfield_axi_mst_narrow, narrow_axi_addr_t, narrow_axi_out_id_t, + `AXI_TYPEDEF_ALL(carfield_axi_slv_narrow, narrow_axi_addr_t, narrow_axi_out_id_t, narrow_axi_data_t, narrow_axi_strb_t, narrow_axi_user_t) `ifndef SECD_NETLIST @@ -1724,30 +1784,30 @@ if (CarfieldIslandsCfg.secured.enable) begin : gen_secure_subsystem .AxiAddrWidth ( Cfg.AddrWidth ), .AxiDataWidth ( Cfg.AxiDataWidth ), .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiOutIdWidth ( Cfg.AxiMstIdWidth ), + .AxiOutIdWidth ( AxiSlvIdWidth ), .AxiOtAddrWidth ( Cfg.AddrWidth ), .AxiOtDataWidth ( AxiNarrowDataWidth ), // TODO: why is this exposed? .AxiOtUserWidth ( Cfg.AxiUserWidth ), - .AxiOtOutIdWidth ( Cfg.AxiMstIdWidth ), - .AsyncAxiOutAwWidth ( CarfieldAxiMstAwWidth ), - .AsyncAxiOutWWidth ( CarfieldAxiMstWWidth ), - .AsyncAxiOutBWidth ( CarfieldAxiMstBWidth ), - .AsyncAxiOutArWidth ( CarfieldAxiMstArWidth ), - .AsyncAxiOutRWidth ( CarfieldAxiMstRWidth ), - .axi_out_aw_chan_t ( carfield_axi_mst_aw_chan_t ), - .axi_out_w_chan_t ( carfield_axi_mst_w_chan_t ), - .axi_out_b_chan_t ( carfield_axi_mst_b_chan_t ), - .axi_out_ar_chan_t ( carfield_axi_mst_ar_chan_t ), - .axi_out_r_chan_t ( carfield_axi_mst_r_chan_t ), - .axi_out_req_t ( carfield_axi_mst_req_t ), - .axi_out_resp_t ( carfield_axi_mst_rsp_t ), - .axi_ot_out_aw_chan_t ( carfield_axi_mst_narrow_aw_chan_t ), - .axi_ot_out_w_chan_t ( carfield_axi_mst_narrow_w_chan_t ), - .axi_ot_out_b_chan_t ( carfield_axi_mst_narrow_b_chan_t ), - .axi_ot_out_ar_chan_t ( carfield_axi_mst_narrow_ar_chan_t ), - .axi_ot_out_r_chan_t ( carfield_axi_mst_narrow_r_chan_t ), - .axi_ot_out_req_t ( carfield_axi_mst_narrow_req_t ), - .axi_ot_out_resp_t ( carfield_axi_mst_narrow_resp_t ), + .AxiOtOutIdWidth ( AxiSlvIdWidth ), + .AsyncAxiOutAwWidth ( CarfieldAxiSlvAwWidth ), + .AsyncAxiOutWWidth ( CarfieldAxiSlvWWidth ), + .AsyncAxiOutBWidth ( CarfieldAxiSlvBWidth ), + .AsyncAxiOutArWidth ( CarfieldAxiSlvArWidth ), + .AsyncAxiOutRWidth ( CarfieldAxiSlvRWidth ), + .axi_out_aw_chan_t ( carfield_axi_slv_aw_chan_t ), + .axi_out_w_chan_t ( carfield_axi_slv_w_chan_t ), + .axi_out_b_chan_t ( carfield_axi_slv_b_chan_t ), + .axi_out_ar_chan_t ( carfield_axi_slv_ar_chan_t ), + .axi_out_r_chan_t ( carfield_axi_slv_r_chan_t ), + .axi_out_req_t ( carfield_axi_slv_req_t ), + .axi_out_resp_t ( carfield_axi_slv_rsp_t ), + .axi_ot_out_aw_chan_t ( carfield_axi_slv_narrow_aw_chan_t ), + .axi_ot_out_w_chan_t ( carfield_axi_slv_narrow_w_chan_t ), + .axi_ot_out_b_chan_t ( carfield_axi_slv_narrow_b_chan_t ), + .axi_ot_out_ar_chan_t ( carfield_axi_slv_narrow_ar_chan_t ), + .axi_ot_out_r_chan_t ( carfield_axi_slv_narrow_r_chan_t ), + .axi_ot_out_req_t ( carfield_axi_slv_narrow_req_t ), + .axi_ot_out_resp_t ( carfield_axi_slv_narrow_resp_t ), .CdcSyncStages ( SyncStages ), .SyncStages ( SyncStages ) ) i_security_island ( @@ -1770,37 +1830,37 @@ if (CarfieldIslandsCfg.secured.enable) begin : gen_secure_subsystem .jtag_tdo_o ( jtag_ot_tdo_o ), .jtag_tdo_oe_o ( jtag_ot_tdo_oe_o), // Asynch axi port - .async_axi_out_aw_data_o ( axi_mst_ext_aw_data [SecurityIslandTlulMstIdx] ), - .async_axi_out_aw_wptr_o ( axi_mst_ext_aw_wptr [SecurityIslandTlulMstIdx] ), - .async_axi_out_aw_rptr_i ( axi_mst_ext_aw_rptr [SecurityIslandTlulMstIdx] ), - .async_axi_out_w_data_o ( axi_mst_ext_w_data [SecurityIslandTlulMstIdx] ), - .async_axi_out_w_wptr_o ( axi_mst_ext_w_wptr [SecurityIslandTlulMstIdx] ), - .async_axi_out_w_rptr_i ( axi_mst_ext_w_rptr [SecurityIslandTlulMstIdx] ), - .async_axi_out_b_data_i ( axi_mst_ext_b_data [SecurityIslandTlulMstIdx] ), - .async_axi_out_b_wptr_i ( axi_mst_ext_b_wptr [SecurityIslandTlulMstIdx] ), - .async_axi_out_b_rptr_o ( axi_mst_ext_b_rptr [SecurityIslandTlulMstIdx] ), - .async_axi_out_ar_data_o ( axi_mst_ext_ar_data [SecurityIslandTlulMstIdx] ), - .async_axi_out_ar_wptr_o ( axi_mst_ext_ar_wptr [SecurityIslandTlulMstIdx] ), - .async_axi_out_ar_rptr_i ( axi_mst_ext_ar_rptr [SecurityIslandTlulMstIdx] ), - .async_axi_out_r_data_i ( axi_mst_ext_r_data [SecurityIslandTlulMstIdx] ), - .async_axi_out_r_wptr_i ( axi_mst_ext_r_wptr [SecurityIslandTlulMstIdx] ), - .async_axi_out_r_rptr_o ( axi_mst_ext_r_rptr [SecurityIslandTlulMstIdx] ), - - .async_idma_axi_out_aw_data_o ( axi_mst_ext_aw_data [SecurityIslandiDMAMstIdx] ), - .async_idma_axi_out_aw_wptr_o ( axi_mst_ext_aw_wptr [SecurityIslandiDMAMstIdx] ), - .async_idma_axi_out_aw_rptr_i ( axi_mst_ext_aw_rptr [SecurityIslandiDMAMstIdx] ), - .async_idma_axi_out_w_data_o ( axi_mst_ext_w_data [SecurityIslandiDMAMstIdx] ), - .async_idma_axi_out_w_wptr_o ( axi_mst_ext_w_wptr [SecurityIslandiDMAMstIdx] ), - .async_idma_axi_out_w_rptr_i ( axi_mst_ext_w_rptr [SecurityIslandiDMAMstIdx] ), - .async_idma_axi_out_b_data_i ( axi_mst_ext_b_data [SecurityIslandiDMAMstIdx] ), - .async_idma_axi_out_b_wptr_i ( axi_mst_ext_b_wptr [SecurityIslandiDMAMstIdx] ), - .async_idma_axi_out_b_rptr_o ( axi_mst_ext_b_rptr [SecurityIslandiDMAMstIdx] ), - .async_idma_axi_out_ar_data_o ( axi_mst_ext_ar_data [SecurityIslandiDMAMstIdx] ), - .async_idma_axi_out_ar_wptr_o ( axi_mst_ext_ar_wptr [SecurityIslandiDMAMstIdx] ), - .async_idma_axi_out_ar_rptr_i ( axi_mst_ext_ar_rptr [SecurityIslandiDMAMstIdx] ), - .async_idma_axi_out_r_data_i ( axi_mst_ext_r_data [SecurityIslandiDMAMstIdx] ), - .async_idma_axi_out_r_wptr_i ( axi_mst_ext_r_wptr [SecurityIslandiDMAMstIdx] ), - .async_idma_axi_out_r_rptr_o ( axi_mst_ext_r_rptr [SecurityIslandiDMAMstIdx] ), + .async_axi_out_aw_data_o ( axi_slv_ext_aw_data [SecurityIslandTlulMstIdx] ), + .async_axi_out_aw_wptr_o ( axi_slv_ext_aw_wptr [SecurityIslandTlulMstIdx] ), + .async_axi_out_aw_rptr_i ( axi_slv_ext_aw_rptr [SecurityIslandTlulMstIdx] ), + .async_axi_out_w_data_o ( axi_slv_ext_w_data [SecurityIslandTlulMstIdx] ), + .async_axi_out_w_wptr_o ( axi_slv_ext_w_wptr [SecurityIslandTlulMstIdx] ), + .async_axi_out_w_rptr_i ( axi_slv_ext_w_rptr [SecurityIslandTlulMstIdx] ), + .async_axi_out_b_data_i ( axi_slv_ext_b_data [SecurityIslandTlulMstIdx] ), + .async_axi_out_b_wptr_i ( axi_slv_ext_b_wptr [SecurityIslandTlulMstIdx] ), + .async_axi_out_b_rptr_o ( axi_slv_ext_b_rptr [SecurityIslandTlulMstIdx] ), + .async_axi_out_ar_data_o ( axi_slv_ext_ar_data [SecurityIslandTlulMstIdx] ), + .async_axi_out_ar_wptr_o ( axi_slv_ext_ar_wptr [SecurityIslandTlulMstIdx] ), + .async_axi_out_ar_rptr_i ( axi_slv_ext_ar_rptr [SecurityIslandTlulMstIdx] ), + .async_axi_out_r_data_i ( axi_slv_ext_r_data [SecurityIslandTlulMstIdx] ), + .async_axi_out_r_wptr_i ( axi_slv_ext_r_wptr [SecurityIslandTlulMstIdx] ), + .async_axi_out_r_rptr_o ( axi_slv_ext_r_rptr [SecurityIslandTlulMstIdx] ), + + .async_idma_axi_out_aw_data_o ( axi_slv_ext_aw_data [SecurityIslandiDMAMstIdx] ), + .async_idma_axi_out_aw_wptr_o ( axi_slv_ext_aw_wptr [SecurityIslandiDMAMstIdx] ), + .async_idma_axi_out_aw_rptr_i ( axi_slv_ext_aw_rptr [SecurityIslandiDMAMstIdx] ), + .async_idma_axi_out_w_data_o ( axi_slv_ext_w_data [SecurityIslandiDMAMstIdx] ), + .async_idma_axi_out_w_wptr_o ( axi_slv_ext_w_wptr [SecurityIslandiDMAMstIdx] ), + .async_idma_axi_out_w_rptr_i ( axi_slv_ext_w_rptr [SecurityIslandiDMAMstIdx] ), + .async_idma_axi_out_b_data_i ( axi_slv_ext_b_data [SecurityIslandiDMAMstIdx] ), + .async_idma_axi_out_b_wptr_i ( axi_slv_ext_b_wptr [SecurityIslandiDMAMstIdx] ), + .async_idma_axi_out_b_rptr_o ( axi_slv_ext_b_rptr [SecurityIslandiDMAMstIdx] ), + .async_idma_axi_out_ar_data_o ( axi_slv_ext_ar_data [SecurityIslandiDMAMstIdx] ), + .async_idma_axi_out_ar_wptr_o ( axi_slv_ext_ar_wptr [SecurityIslandiDMAMstIdx] ), + .async_idma_axi_out_ar_rptr_i ( axi_slv_ext_ar_rptr [SecurityIslandiDMAMstIdx] ), + .async_idma_axi_out_r_data_i ( axi_slv_ext_r_data [SecurityIslandiDMAMstIdx] ), + .async_idma_axi_out_r_wptr_i ( axi_slv_ext_r_wptr [SecurityIslandiDMAMstIdx] ), + .async_idma_axi_out_r_rptr_o ( axi_slv_ext_r_rptr [SecurityIslandiDMAMstIdx] ), .axi_isolate_i ( security_island_isolate_req ), .axi_isolated_o ( { master_isolated_rsp[SecurityIslandiDMAMstIdx], master_isolated_rsp[SecurityIslandTlulMstIdx] } ), @@ -1840,13 +1900,13 @@ end // AXI cut axi_cut #( .Bypass ( 1'b0 ), - .aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .w_chan_t ( carfield_axi_slv_w_chan_t ), - .b_chan_t ( carfield_axi_slv_b_chan_t ), - .ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_resp_t ( carfield_axi_slv_rsp_t ) + .aw_chan_t ( carfield_axi_mst_aw_chan_t ), + .w_chan_t ( carfield_axi_mst_w_chan_t ), + .b_chan_t ( carfield_axi_mst_b_chan_t ), + .ar_chan_t ( carfield_axi_mst_ar_chan_t ), + .r_chan_t ( carfield_axi_mst_r_chan_t ), + .axi_req_t ( carfield_axi_mst_req_t ), + .axi_resp_t ( carfield_axi_mst_rsp_t ) ) i_cut_pre_amo_mbox ( .clk_i ( host_clk_i ), .rst_ni ( host_pwr_on_rst_n ), @@ -1861,7 +1921,7 @@ axi_cut #( axi_riscv_atomics_structs #( .AxiAddrWidth ( Cfg.AddrWidth ), .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiIdWidth ( AxiSlvIdWidth ), + .AxiIdWidth ( Cfg.AxiMstIdWidth ), .AxiUserWidth ( Cfg.AxiUserWidth ), .AxiMaxReadTxns ( Cfg.RegMaxReadTxns ), .AxiMaxWriteTxns ( Cfg.RegMaxWriteTxns ), @@ -1870,8 +1930,8 @@ axi_riscv_atomics_structs #( .AxiUserIdLsb ( Cfg.AxiUserAmoLsb ), .RiscvWordWidth ( 64 ), .NAxiCuts ( 0 ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_rsp_t ( carfield_axi_slv_rsp_t ) + .axi_req_t ( carfield_axi_mst_req_t ), + .axi_rsp_t ( carfield_axi_mst_rsp_t ) ) i_atomics_mbox ( .clk_i ( host_clk_i ), .rst_ni ( host_pwr_on_rst_n ), @@ -1884,13 +1944,13 @@ axi_riscv_atomics_structs #( // AXI cut axi_cut #( .Bypass ( ~Cfg.RegAmoPostCut ), - .aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .w_chan_t ( carfield_axi_slv_w_chan_t ), - .b_chan_t ( carfield_axi_slv_b_chan_t ), - .ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_resp_t ( carfield_axi_slv_rsp_t ) + .aw_chan_t ( carfield_axi_mst_aw_chan_t ), + .w_chan_t ( carfield_axi_mst_w_chan_t ), + .b_chan_t ( carfield_axi_mst_b_chan_t ), + .ar_chan_t ( carfield_axi_mst_ar_chan_t ), + .r_chan_t ( carfield_axi_mst_r_chan_t ), + .axi_req_t ( carfield_axi_mst_req_t ), + .axi_resp_t ( carfield_axi_mst_rsp_t ) ) i_cut_post_amo_mbox ( .clk_i ( host_clk_i ), .rst_ni ( host_pwr_on_rst_n ), @@ -1907,11 +1967,11 @@ carfield_reg_rsp_t reg_mbox_rsp; axi_to_reg_v2 #( .AxiAddrWidth ( Cfg.AddrWidth ), .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiIdWidth ( AxiSlvIdWidth ), + .AxiIdWidth ( Cfg.AxiMstIdWidth), .AxiUserWidth ( Cfg.AxiUserWidth ), .RegDataWidth ( AxiNarrowDataWidth ), // 32-bit - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_rsp_t ( carfield_axi_slv_rsp_t ), + .axi_req_t ( carfield_axi_mst_req_t ), + .axi_rsp_t ( carfield_axi_mst_rsp_t ), .reg_req_t ( carfield_reg_req_t ), .reg_rsp_t ( carfield_reg_rsp_t ) ) i_axi_to_reg_v2_mbox ( @@ -1981,25 +2041,25 @@ if (CarfieldIslandsCfg.ethernet.enable) begin : gen_ethernet .AddrWidth ( Cfg.AddrWidth ), .DataWidth ( Cfg.AxiDataWidth ), .UserWidth ( Cfg.AxiUserWidth ), - .AxiIdWidth ( Cfg.AxiMstIdWidth ), + .AxiIdWidth ( AxiSlvIdWidth ), .NumAxInFlight ( EthDmaNumAxInFlight ), .BufferDepth ( EthDmaBufferDepth ), .TFLenWidth ( EthDmaTFLenWidth ), .MemSysDepth ( EthDmaMemSysDepth ), .TxFifoLogDepth ( EthTxFifoLogDepth ), .RxFifoLogDepth ( EthRxFifoLogDepth ), - .AsyncAxiOutAwWidth ( CarfieldAxiMstAwWidth ), - .AsyncAxiOutWWidth ( CarfieldAxiMstWWidth ), - .AsyncAxiOutBWidth ( CarfieldAxiMstBWidth ), - .AsyncAxiOutArWidth ( CarfieldAxiMstArWidth ), - .AsyncAxiOutRWidth ( CarfieldAxiMstRWidth ), - .axi_out_aw_chan_t ( carfield_axi_mst_aw_chan_t ), - .axi_out_w_chan_t ( carfield_axi_mst_w_chan_t ), - .axi_out_b_chan_t ( carfield_axi_mst_b_chan_t ), - .axi_out_ar_chan_t ( carfield_axi_mst_ar_chan_t ), - .axi_out_r_chan_t ( carfield_axi_mst_r_chan_t ), - .axi_out_req_t ( carfield_axi_mst_req_t ), - .axi_out_resp_t ( carfield_axi_mst_rsp_t ), + .AsyncAxiOutAwWidth ( CarfieldAxiSlvAwWidth ), + .AsyncAxiOutWWidth ( CarfieldAxiSlvWWidth ), + .AsyncAxiOutBWidth ( CarfieldAxiSlvBWidth ), + .AsyncAxiOutArWidth ( CarfieldAxiSlvArWidth ), + .AsyncAxiOutRWidth ( CarfieldAxiSlvRWidth ), + .axi_out_aw_chan_t ( carfield_axi_slv_aw_chan_t ), + .axi_out_w_chan_t ( carfield_axi_slv_w_chan_t ), + .axi_out_b_chan_t ( carfield_axi_slv_b_chan_t ), + .axi_out_ar_chan_t ( carfield_axi_slv_ar_chan_t ), + .axi_out_r_chan_t ( carfield_axi_slv_r_chan_t ), + .axi_out_req_t ( carfield_axi_slv_req_t ), + .axi_out_resp_t ( carfield_axi_slv_rsp_t ), .LogDepth ( LogDepth ), .CdcSyncStages ( SyncStages ), .SyncStages ( SyncStages ), @@ -2026,21 +2086,21 @@ if (CarfieldIslandsCfg.ethernet.enable) begin : gen_ethernet .testmode_i ( test_mode_i ), .axi_isolate_i ( ethernet_isolate_req ), .axi_isolated_o ( ethernet_isolated_rsp ), - .async_axi_out_aw_data_o ( axi_mst_ext_aw_data [EthernetMstIdx] ), - .async_axi_out_aw_wptr_o ( axi_mst_ext_aw_wptr [EthernetMstIdx] ), - .async_axi_out_aw_rptr_i ( axi_mst_ext_aw_rptr [EthernetMstIdx] ), - .async_axi_out_w_data_o ( axi_mst_ext_w_data [EthernetMstIdx] ), - .async_axi_out_w_wptr_o ( axi_mst_ext_w_wptr [EthernetMstIdx] ), - .async_axi_out_w_rptr_i ( axi_mst_ext_w_rptr [EthernetMstIdx] ), - .async_axi_out_b_data_i ( axi_mst_ext_b_data [EthernetMstIdx] ), - .async_axi_out_b_wptr_i ( axi_mst_ext_b_wptr [EthernetMstIdx] ), - .async_axi_out_b_rptr_o ( axi_mst_ext_b_rptr [EthernetMstIdx] ), - .async_axi_out_ar_data_o ( axi_mst_ext_ar_data [EthernetMstIdx] ), - .async_axi_out_ar_wptr_o ( axi_mst_ext_ar_wptr [EthernetMstIdx] ), - .async_axi_out_ar_rptr_i ( axi_mst_ext_ar_rptr [EthernetMstIdx] ), - .async_axi_out_r_data_i ( axi_mst_ext_r_data [EthernetMstIdx] ), - .async_axi_out_r_wptr_i ( axi_mst_ext_r_wptr [EthernetMstIdx] ), - .async_axi_out_r_rptr_o ( axi_mst_ext_r_rptr [EthernetMstIdx] ), + .async_axi_out_aw_data_o ( axi_slv_ext_aw_data [EthernetMstIdx] ), + .async_axi_out_aw_wptr_o ( axi_slv_ext_aw_wptr [EthernetMstIdx] ), + .async_axi_out_aw_rptr_i ( axi_slv_ext_aw_rptr [EthernetMstIdx] ), + .async_axi_out_w_data_o ( axi_slv_ext_w_data [EthernetMstIdx] ), + .async_axi_out_w_wptr_o ( axi_slv_ext_w_wptr [EthernetMstIdx] ), + .async_axi_out_w_rptr_i ( axi_slv_ext_w_rptr [EthernetMstIdx] ), + .async_axi_out_b_data_i ( axi_slv_ext_b_data [EthernetMstIdx] ), + .async_axi_out_b_wptr_i ( axi_slv_ext_b_wptr [EthernetMstIdx] ), + .async_axi_out_b_rptr_o ( axi_slv_ext_b_rptr [EthernetMstIdx] ), + .async_axi_out_ar_data_o ( axi_slv_ext_ar_data [EthernetMstIdx] ), + .async_axi_out_ar_wptr_o ( axi_slv_ext_ar_wptr [EthernetMstIdx] ), + .async_axi_out_ar_rptr_i ( axi_slv_ext_ar_rptr [EthernetMstIdx] ), + .async_axi_out_r_data_i ( axi_slv_ext_r_data [EthernetMstIdx] ), + .async_axi_out_r_wptr_i ( axi_slv_ext_r_wptr [EthernetMstIdx] ), + .async_axi_out_r_rptr_o ( axi_slv_ext_r_rptr [EthernetMstIdx] ), .reg_async_mst_req_i ( ext_reg_async_slv_req_out [EthAsyncIdx] ), .reg_async_mst_ack_o ( ext_reg_async_slv_ack_in [EthAsyncIdx] ), .reg_async_mst_data_i ( ext_reg_async_slv_data_out[EthAsyncIdx] ), @@ -2073,36 +2133,36 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... hyper_isolated_rsp & ethernet_isolated_rsp; assign car_regs_hw2reg.periph_isolate_status.de = 1'b1; - carfield_axi_slv_req_t axi_d64_a48_peripherals_req; - carfield_axi_slv_rsp_t axi_d64_a48_peripherals_rsp; + carfield_axi_mst_req_t axi_d64_a48_peripherals_req; + carfield_axi_mst_rsp_t axi_d64_a48_peripherals_rsp; axi_cdc_dst #( .LogDepth ( LogDepth ), .SyncStages ( SyncStages ), - .aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .w_chan_t ( carfield_axi_slv_w_chan_t ), - .b_chan_t ( carfield_axi_slv_b_chan_t ), - .ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_resp_t ( carfield_axi_slv_rsp_t ) + .aw_chan_t ( carfield_axi_mst_aw_chan_t ), + .w_chan_t ( carfield_axi_mst_w_chan_t ), + .b_chan_t ( carfield_axi_mst_b_chan_t ), + .ar_chan_t ( carfield_axi_mst_ar_chan_t ), + .r_chan_t ( carfield_axi_mst_r_chan_t ), + .axi_req_t ( carfield_axi_mst_req_t ), + .axi_resp_t ( carfield_axi_mst_rsp_t ) ) i_cdc_dst_peripherals ( // asynchronous slave port - .async_data_slave_aw_data_i ( axi_slv_ext_aw_data [PeriphsSlvIdx] ), - .async_data_slave_aw_wptr_i ( axi_slv_ext_aw_wptr [PeriphsSlvIdx] ), - .async_data_slave_aw_rptr_o ( axi_slv_ext_aw_rptr [PeriphsSlvIdx] ), - .async_data_slave_w_data_i ( axi_slv_ext_w_data [PeriphsSlvIdx] ), - .async_data_slave_w_wptr_i ( axi_slv_ext_w_wptr [PeriphsSlvIdx] ), - .async_data_slave_w_rptr_o ( axi_slv_ext_w_rptr [PeriphsSlvIdx] ), - .async_data_slave_b_data_o ( axi_slv_ext_b_data [PeriphsSlvIdx] ), - .async_data_slave_b_wptr_o ( axi_slv_ext_b_wptr [PeriphsSlvIdx] ), - .async_data_slave_b_rptr_i ( axi_slv_ext_b_rptr [PeriphsSlvIdx] ), - .async_data_slave_ar_data_i ( axi_slv_ext_ar_data [PeriphsSlvIdx] ), - .async_data_slave_ar_wptr_i ( axi_slv_ext_ar_wptr [PeriphsSlvIdx] ), - .async_data_slave_ar_rptr_o ( axi_slv_ext_ar_rptr [PeriphsSlvIdx] ), - .async_data_slave_r_data_o ( axi_slv_ext_r_data [PeriphsSlvIdx] ), - .async_data_slave_r_wptr_o ( axi_slv_ext_r_wptr [PeriphsSlvIdx] ), - .async_data_slave_r_rptr_i ( axi_slv_ext_r_rptr [PeriphsSlvIdx] ), + .async_data_slave_aw_data_i ( axi_mst_ext_aw_data [PeriphsSlvIdx] ), + .async_data_slave_aw_wptr_i ( axi_mst_ext_aw_wptr [PeriphsSlvIdx] ), + .async_data_slave_aw_rptr_o ( axi_mst_ext_aw_rptr [PeriphsSlvIdx] ), + .async_data_slave_w_data_i ( axi_mst_ext_w_data [PeriphsSlvIdx] ), + .async_data_slave_w_wptr_i ( axi_mst_ext_w_wptr [PeriphsSlvIdx] ), + .async_data_slave_w_rptr_o ( axi_mst_ext_w_rptr [PeriphsSlvIdx] ), + .async_data_slave_b_data_o ( axi_mst_ext_b_data [PeriphsSlvIdx] ), + .async_data_slave_b_wptr_o ( axi_mst_ext_b_wptr [PeriphsSlvIdx] ), + .async_data_slave_b_rptr_i ( axi_mst_ext_b_rptr [PeriphsSlvIdx] ), + .async_data_slave_ar_data_i ( axi_mst_ext_ar_data [PeriphsSlvIdx] ), + .async_data_slave_ar_wptr_i ( axi_mst_ext_ar_wptr [PeriphsSlvIdx] ), + .async_data_slave_ar_rptr_o ( axi_mst_ext_ar_rptr [PeriphsSlvIdx] ), + .async_data_slave_r_data_o ( axi_mst_ext_r_data [PeriphsSlvIdx] ), + .async_data_slave_r_wptr_o ( axi_mst_ext_r_wptr [PeriphsSlvIdx] ), + .async_data_slave_r_rptr_i ( axi_mst_ext_r_rptr [PeriphsSlvIdx] ), // synchronous master port .dst_clk_i ( periph_clk ), .dst_rst_ni ( periph_pwr_on_rst_n ), @@ -2110,15 +2170,15 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... .dst_resp_i ( axi_d64_a48_peripherals_rsp ) ); - carfield_axi_slv_req_t axi_d64_a48_amo_peripherals_req; - carfield_axi_slv_rsp_t axi_d64_a48_amo_peripherals_rsp; + carfield_axi_mst_req_t axi_d64_a48_amo_peripherals_req; + carfield_axi_mst_rsp_t axi_d64_a48_amo_peripherals_rsp; // Shim atomics, which are not supported in reg // TODO: should we use a filter instead here? axi_riscv_atomics_structs #( .AxiAddrWidth ( Cfg.AddrWidth ), .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiIdWidth ( AxiSlvIdWidth ), + .AxiIdWidth ( Cfg.AxiMstIdWidth ), .AxiUserWidth ( Cfg.AxiUserWidth ), .AxiMaxReadTxns ( Cfg.RegMaxReadTxns ), .AxiMaxWriteTxns ( Cfg.RegMaxWriteTxns ), @@ -2127,8 +2187,8 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... .AxiUserIdLsb ( Cfg.AxiUserAmoLsb ), .RiscvWordWidth ( 64 ), .NAxiCuts ( Cfg.RegAmoNumCuts ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_rsp_t ( carfield_axi_slv_rsp_t ) + .axi_req_t ( carfield_axi_mst_req_t ), + .axi_rsp_t ( carfield_axi_mst_rsp_t ) ) i_atomics_peripherals ( .clk_i ( periph_clk ), .rst_ni ( periph_pwr_on_rst_n ), @@ -2138,18 +2198,18 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... .axi_mst_rsp_i ( axi_d64_a48_amo_peripherals_rsp ) ); - carfield_axi_slv_req_t axi_d64_a48_amo_cut_peripherals_req; - carfield_axi_slv_rsp_t axi_d64_a48_amo_cut_peripherals_rsp; + carfield_axi_mst_req_t axi_d64_a48_amo_cut_peripherals_req; + carfield_axi_mst_rsp_t axi_d64_a48_amo_cut_peripherals_rsp; axi_cut #( .Bypass ( ~Cfg.RegAmoPostCut ), - .aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .w_chan_t ( carfield_axi_slv_w_chan_t ), - .b_chan_t ( carfield_axi_slv_b_chan_t ), - .ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_resp_t ( carfield_axi_slv_rsp_t ) + .aw_chan_t ( carfield_axi_mst_aw_chan_t ), + .w_chan_t ( carfield_axi_mst_w_chan_t ), + .b_chan_t ( carfield_axi_mst_b_chan_t ), + .ar_chan_t ( carfield_axi_mst_ar_chan_t ), + .r_chan_t ( carfield_axi_mst_r_chan_t ), + .axi_req_t ( carfield_axi_mst_req_t ), + .axi_resp_t ( carfield_axi_mst_rsp_t ) ) i_atomics_cut_peripherals ( .clk_i ( periph_clk ), .rst_ni ( periph_pwr_on_rst_n ), @@ -2161,28 +2221,28 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... // Convert to d32 a48 // verilog_lint: waive-start line-length - `AXI_TYPEDEF_ALL_CT(carfield_axi_d32_a48_slv, carfield_axi_d32_a48_slv_req_t, carfield_axi_d32_a48_slv_rsp_t, car_addrw_t, car_slv_id_t, car_nar_dataw_t, car_nar_strb_t, car_usr_t) + `AXI_TYPEDEF_ALL_CT(carfield_axi_d32_a48_mst, carfield_axi_d32_a48_mst_req_t, carfield_axi_d32_a48_mst_rsp_t, car_addrw_t, car_mst_id_t, car_nar_dataw_t, car_nar_strb_t, car_usr_t) // verilog_lint: waive-stop line-length - carfield_axi_d32_a48_slv_req_t axi_d32_a48_peripherals_req; - carfield_axi_d32_a48_slv_rsp_t axi_d32_a48_peripherals_rsp; + carfield_axi_d32_a48_mst_req_t axi_d32_a48_peripherals_req; + carfield_axi_d32_a48_mst_rsp_t axi_d32_a48_peripherals_rsp; axi_dw_converter #( .AxiSlvPortDataWidth ( Cfg.AxiDataWidth ), .AxiMstPortDataWidth ( AxiNarrowDataWidth ), .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiIdWidth ( AxiSlvIdWidth ), - .aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .mst_w_chan_t ( carfield_axi_d32_a48_slv_w_chan_t ), - .slv_w_chan_t ( carfield_axi_slv_w_chan_t ), - .b_chan_t ( carfield_axi_slv_b_chan_t ), - .ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .mst_r_chan_t ( carfield_axi_d32_a48_slv_r_chan_t ), - .slv_r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_mst_req_t ( carfield_axi_d32_a48_slv_req_t ), - .axi_mst_resp_t ( carfield_axi_d32_a48_slv_rsp_t ), - .axi_slv_req_t ( carfield_axi_slv_req_t ), - .axi_slv_resp_t ( carfield_axi_slv_rsp_t ) + .AxiIdWidth ( Cfg.AxiMstIdWidth ), + .aw_chan_t ( carfield_axi_mst_aw_chan_t ), + .mst_w_chan_t ( carfield_axi_d32_a48_mst_w_chan_t ), + .slv_w_chan_t ( carfield_axi_mst_w_chan_t ), + .b_chan_t ( carfield_axi_mst_b_chan_t ), + .ar_chan_t ( carfield_axi_mst_ar_chan_t ), + .mst_r_chan_t ( carfield_axi_d32_a48_mst_r_chan_t ), + .slv_r_chan_t ( carfield_axi_mst_r_chan_t ), + .axi_mst_req_t ( carfield_axi_d32_a48_mst_req_t ), + .axi_mst_resp_t ( carfield_axi_d32_a48_mst_rsp_t ), + .axi_slv_req_t ( carfield_axi_mst_req_t ), + .axi_slv_resp_t ( carfield_axi_mst_rsp_t ) ) i_axi_dw_converter_peripherals ( .clk_i ( periph_clk ), .rst_ni ( periph_pwr_on_rst_n ), @@ -2194,17 +2254,17 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... // Convert to d32_a32 // verilog_lint: waive-start line-length - `AXI_TYPEDEF_ALL_CT(carfield_axi_d32_a32_slv, carfield_axi_d32_a32_slv_req_t, carfield_axi_d32_a32_slv_rsp_t, car_nar_addrw_t, car_slv_id_t, car_nar_dataw_t, car_nar_strb_t, car_usr_t) + `AXI_TYPEDEF_ALL_CT(carfield_axi_d32_a32_mst, carfield_axi_d32_a32_mst_req_t, carfield_axi_d32_a32_mst_rsp_t, car_nar_addrw_t, car_mst_id_t, car_nar_dataw_t, car_nar_strb_t, car_usr_t) // verilog_lint: waive-stop line-length - carfield_axi_d32_a32_slv_req_t axi_d32_a32_peripherals_req; - carfield_axi_d32_a32_slv_rsp_t axi_d32_a32_peripherals_rsp; + carfield_axi_d32_a32_mst_req_t axi_d32_a32_peripherals_req; + carfield_axi_d32_a32_mst_rsp_t axi_d32_a32_peripherals_rsp; axi_modify_address #( - .slv_req_t ( carfield_axi_d32_a48_slv_req_t ), + .slv_req_t ( carfield_axi_d32_a48_mst_req_t ), .mst_addr_t ( car_nar_addrw_t ), - .mst_req_t ( carfield_axi_d32_a32_slv_req_t ), - .axi_resp_t ( carfield_axi_d32_a32_slv_rsp_t ) + .mst_req_t ( carfield_axi_d32_a32_mst_req_t ), + .axi_resp_t ( carfield_axi_d32_a32_mst_rsp_t ) ) i_axi_modify_addr_peripherals ( .slv_req_i ( axi_d32_a48_peripherals_req ), .slv_resp_o ( axi_d32_a48_peripherals_rsp ), @@ -2216,24 +2276,24 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... // AXI to AXI lite conversion // verilog_lint: waive-start line-length - `AXI_LITE_TYPEDEF_ALL_CT(carfield_axi_lite_d32_a32, carfield_axi_lite_d32_a32_slv_req_t, carfield_axi_lite_d32_a32_slv_rsp_t, car_nar_addrw_t, car_nar_dataw_t, car_nar_strb_t) + `AXI_LITE_TYPEDEF_ALL_CT(carfield_axi_lite_d32_a32, carfield_axi_lite_d32_a32_mst_req_t, carfield_axi_lite_d32_a32_mst_rsp_t, car_nar_addrw_t, car_nar_dataw_t, car_nar_strb_t) // verilog_lint: waive-stop line-length - carfield_axi_lite_d32_a32_slv_req_t axi_lite_d32_a32_peripherals_req; - carfield_axi_lite_d32_a32_slv_rsp_t axi_lite_d32_a32_peripherals_rsp; + carfield_axi_lite_d32_a32_mst_req_t axi_lite_d32_a32_peripherals_req; + carfield_axi_lite_d32_a32_mst_rsp_t axi_lite_d32_a32_peripherals_rsp; axi_to_axi_lite #( .AxiAddrWidth ( AxiNarrowAddrWidth ), .AxiDataWidth ( AxiNarrowDataWidth ), - .AxiIdWidth ( AxiSlvIdWidth ), + .AxiIdWidth ( Cfg.AxiMstIdWidth ), .AxiUserWidth ( Cfg.AxiUserWidth ), .AxiMaxWriteTxns( 1 ), .AxiMaxReadTxns ( 1 ), .FallThrough ( 1 ), - .full_req_t ( carfield_axi_d32_a32_slv_req_t ), - .full_resp_t ( carfield_axi_d32_a32_slv_rsp_t ), - .lite_req_t ( carfield_axi_lite_d32_a32_slv_req_t ), - .lite_resp_t ( carfield_axi_lite_d32_a32_slv_rsp_t ) + .full_req_t ( carfield_axi_d32_a32_mst_req_t ), + .full_resp_t ( carfield_axi_d32_a32_mst_rsp_t ), + .lite_req_t ( carfield_axi_lite_d32_a32_mst_req_t ), + .lite_resp_t ( carfield_axi_lite_d32_a32_mst_rsp_t ) ) i_axi_to_axi_lite_peripherals ( .clk_i ( periph_clk ), .rst_ni ( periph_pwr_on_rst_n ), @@ -2259,8 +2319,8 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... .DataWidth ( AxiNarrowDataWidth ), .PipelineRequest ( '0 ), .PipelineResponse( '0 ), - .axi_lite_req_t ( carfield_axi_lite_d32_a32_slv_req_t ), - .axi_lite_resp_t ( carfield_axi_lite_d32_a32_slv_rsp_t ), + .axi_lite_req_t ( carfield_axi_lite_d32_a32_mst_req_t ), + .axi_lite_resp_t ( carfield_axi_lite_d32_a32_mst_rsp_t ), .apb_req_t ( carfield_apb_req_t ), .apb_resp_t ( carfield_apb_rsp_t ), .rule_t ( carfield_addr_map_rule_t ) diff --git a/hw/carfield_pkg.sv b/hw/carfield_pkg.sv index bb84fac8..4693f302 100644 --- a/hw/carfield_pkg.sv +++ b/hw/carfield_pkg.sv @@ -32,6 +32,7 @@ typedef struct packed { } islands_properties_t; typedef struct packed { + islands_properties_t cheshire; islands_properties_t l2_port0; islands_properties_t l2_port1; islands_properties_t safed; @@ -40,6 +41,7 @@ typedef struct packed { islands_properties_t spatz; islands_properties_t pulp; islands_properties_t secured; + islands_properties_t dram; islands_properties_t mbox; } islands_cfg_t; @@ -62,6 +64,7 @@ typedef struct packed { byte_bt periph; byte_bt spatz; byte_bt pulp; + byte_bt dram; byte_bt mbox; } carfield_slave_idx_t; @@ -87,6 +90,7 @@ function automatic int unsigned gen_num_axi_slave(islands_cfg_t island_cfg); if (island_cfg.periph.enable ) begin ret++; end if (island_cfg.spatz.enable ) begin ret++; end if (island_cfg.pulp.enable ) begin ret++; end + if (island_cfg.dram.enable ) begin ret++; end if (island_cfg.mbox.enable ) begin ret++; end return ret; endfunction @@ -110,6 +114,8 @@ function automatic carfield_slave_idx_t carfield_gen_axi_slave_idx(islands_cfg_t end else begin ret.spatz = MaxExtAxiSlv + j; j++; end if (island_cfg.pulp.enable) begin ret.pulp = i; i++; end else begin ret.pulp = MaxExtAxiSlv + j; j++; end + if (island_cfg.dram.enable) begin ret.dram = i; i++; + end else begin ret.dram = MaxExtAxiSlv + j; j++; end if (island_cfg.mbox.enable) begin ret.mbox = i; i++; end else begin ret.mbox = MaxExtAxiSlv + j; j++; end return ret; @@ -188,6 +194,12 @@ function automatic axi_struct_t carfield_gen_axi_map(int unsigned NumSlave , ret.AxiEnd[i] = island_cfg.pulp.base + island_cfg.pulp.size; if (i < NumSlave - 1) i++; end + if (island_cfg.dram.enable) begin + ret.AxiIdx[i] = idx.dram; + ret.AxiStart[i] = island_cfg.dram.base; + ret.AxiEnd[i] = island_cfg.dram.base + island_cfg.dram.size; + if (i < NumSlave - 1) i++; + end if (island_cfg.mbox.enable) begin ret.AxiIdx[i] = idx.mbox; ret.AxiStart[i] = island_cfg.mbox.base; @@ -323,6 +335,7 @@ function automatic int unsigned gen_carfield_domains(islands_cfg_t island_cfg); endfunction localparam islands_cfg_t CarfieldIslandsCfg = '{ + cheshire: '{1, CheshireBase, CheshireSize}, l2_port0: '{L2Port0Enable, L2Port0Base, L2Port0Size}, l2_port1: '{L2Port1Enable, L2Port1Base, L2Port1Size}, safed: '{SafetyIslandEnable, SafetyIslandBase, SafetyIslandSize}, @@ -331,6 +344,7 @@ localparam islands_cfg_t CarfieldIslandsCfg = '{ spatz: '{SpatzClusterEnable, SpatzClusterBase, SpatzClusterSize}, pulp: '{PulpClusterEnable, PulpClusterBase, PulpClusterSize}, secured: '{SecurityIslandEnable, SecurityIslandBase, SecurityIslandSize}, + dram: '{DramEnable, DramBase, DramSize}, mbox: '{MailboxEnable, MailboxBase, MailboxSize} }; @@ -419,6 +433,7 @@ typedef enum byte_bt { PeriphsSlvIdx = CarfieldAxiSlvIdx.periph, FPClusterSlvIdx = CarfieldAxiSlvIdx.spatz, IntClusterSlvIdx = CarfieldAxiSlvIdx.pulp, + DramSlvIdx = CarfieldAxiSlvIdx.dram, MailboxSlvIdx = CarfieldAxiSlvIdx.mbox } axi_slv_idx_t; @@ -578,7 +593,7 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{ AddrWidth : 48, AxiDataWidth : 64, AxiUserWidth : 10, // {CACHE_PARTITIONING(5[9:5]), ECC_ERROR(1[4:4]), ATOPS(4[3:0])} - AxiMstIdWidth : 2, + AxiMstIdWidth : 3, TFLenWidth : 32, AxiMaxMstTrans : 64, AxiMaxSlvTrans : 64, @@ -593,13 +608,13 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{ RegAmoPostCut : 1, RegAdaptMemCut : 1, // External AXI ports (at most 8 ports and rules) - AxiExtNumMst : CarfieldAxiNumMasters, - AxiExtNumSlv : CarfieldAxiNumSlaves, - AxiExtNumRules : CarfieldAxiNumSlaves, + AxiExtNumMst : 1, + AxiExtNumSlv : 1, + AxiExtNumRules : 1, // External AXI region map - AxiExtRegionIdx : CarfieldAxiMap.AxiIdx, - AxiExtRegionStart : CarfieldAxiMap.AxiStart, - AxiExtRegionEnd : CarfieldAxiMap.AxiEnd, + AxiExtRegionIdx : 'h0, + AxiExtRegionStart : CarfieldIslandsCfg.cheshire.base + CarfieldIslandsCfg.cheshire.size, + AxiExtRegionEnd : CarfieldIslandsCfg.dram.base, // External reg slaves (at most 8 ports and rules) RegExtNumSlv : NumTotalRegSlv, RegExtNumRules : NumTotalRegSlv, @@ -649,9 +664,9 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{ LlcMaxWriteTxns : 32, LlcAmoNumCuts : 1, LlcAmoPostCut : 1, - LlcOutConnect : 1, - LlcOutRegionStart : 'h8000_0000, - LlcOutRegionEnd : 'h1_0000_0000, + LlcOutConnect : CarfieldIslandsCfg.dram.enable, + LlcOutRegionStart : CarfieldIslandsCfg.dram.base, + LlcOutRegionEnd : CarfieldIslandsCfg.dram.base + CarfieldIslandsCfg.dram.size, LlcUserMsb : 9, LlcUserLsb : 5, LlcCachePartition : 1, @@ -709,6 +724,8 @@ localparam int unsigned LogDepth = 3; /* L2 Parameters */ /*****************/ localparam int unsigned NumL2Ports = (CarfieldIslandsCfg.l2_port1.enable) ? 2 : 1; +localparam int unsigned L2PortId = (CarfieldIslandsCfg.l2_port1.enable) ? L2Port1SlvIdx + : L2Port0SlvIdx; localparam int unsigned L2MemSize = CarfieldIslandsCfg.l2_port0.size/2; localparam int unsigned L2NumRules = 4; // 2 rules per each access mode // (interleaved, non-interleaved) diff --git a/hw/cheshire_wrap.sv b/hw/cheshire_wrap.sv index 58882b7d..ef44676f 100644 --- a/hw/cheshire_wrap.sv +++ b/hw/cheshire_wrap.sv @@ -18,6 +18,8 @@ module cheshire_wrap parameter cheshire_cfg_t Cfg = '0, parameter dm::hartinfo_t [iomsb(Cfg.NumExtDbgHarts)-1:0] ExtHartinfo = '0, parameter int unsigned NumExtIntrs = 32, + parameter axi_in_t AxiIn = gen_axi_in(Cfg) , + parameter axi_out_t AxiOut = gen_axi_out(Cfg), parameter type cheshire_axi_ext_llc_ar_chan_t = logic, parameter type cheshire_axi_ext_llc_aw_chan_t = logic, parameter type cheshire_axi_ext_llc_b_chan_t = logic, @@ -43,35 +45,30 @@ module cheshire_wrap parameter type cheshire_reg_ext_rsp_t = logic, parameter int unsigned LogDepth = 3, parameter int unsigned CdcSyncStages = 2, - // External Slaves Parameters - // Having a dedicated synchronous port, the mailbox is not taken into account - parameter int unsigned NumSlaveCDCs = Cfg.AxiExtNumSlv - 1, - parameter axi_in_t AxiIn = gen_axi_in(Cfg) , - parameter axi_out_t AxiOut = gen_axi_out(Cfg), + parameter int unsigned ExtSlvIdWidth = Cfg.AxiMstIdWidth + + $clog2(AxiIn.num_in), + parameter int unsigned LlcIdWidth = ExtSlvIdWidth + + Cfg.LlcNotBypass, // LLC Parameters - localparam int unsigned LlcIdWidth = Cfg.AxiMstIdWidth + - $clog2(AxiIn.num_in)+ - Cfg.LlcNotBypass , - localparam int unsigned LlcArWidth = (2**LogDepth)* + parameter int unsigned LlcArWidth = (2**LogDepth)* axi_pkg::ar_width(Cfg.AddrWidth , LlcIdWidth , Cfg.AxiUserWidth), - localparam int unsigned LlcAwWidth = (2**LogDepth)* - axi_pkg::aw_width(Cfg.AddrWidth , - LlcIdWidth , - Cfg.AxiUserWidth), - localparam int unsigned LlcBWidth = (2**LogDepth)* - axi_pkg::b_width(LlcIdWidth , + parameter int unsigned LlcAwWidth = (2**LogDepth)* + axi_pkg::aw_width(Cfg.AddrWidth , + LlcIdWidth , Cfg.AxiUserWidth), - localparam int unsigned LlcRWidth = (2**LogDepth)* - axi_pkg::r_width(Cfg.AxiDataWidth, - LlcIdWidth , + parameter int unsigned LlcBWidth = (2**LogDepth)* + axi_pkg::b_width(LlcIdWidth , Cfg.AxiUserWidth), - localparam int unsigned LlcWWidth = (2**LogDepth)* - axi_pkg::w_width(Cfg.AxiDataWidth, - Cfg.AxiUserWidth), - localparam int unsigned ExtSlvIdWidth = Cfg.AxiMstIdWidth + - $clog2(AxiIn.num_in ), + parameter int unsigned LlcRWidth = (2**LogDepth)* + axi_pkg::r_width(Cfg.AxiDataWidth , + LlcIdWidth , + Cfg.AxiUserWidth), + parameter int unsigned LlcWWidth = (2**LogDepth)* + axi_pkg::w_width(Cfg.AxiDataWidth , + Cfg.AxiUserWidth), + // External Slaves Parameters localparam int unsigned ExtSlvArWidth = (2**LogDepth)* axi_pkg::ar_width(Cfg.AddrWidth , ExtSlvIdWidth , @@ -118,59 +115,27 @@ module cheshire_wrap // External AXI LLC (DRAM) port input logic axi_llc_isolate_i, output logic axi_llc_isolated_o, - output logic [LlcArWidth-1:0] llc_mst_ar_data_o, - output logic [ LogDepth:0] llc_mst_ar_wptr_o, - input logic [ LogDepth:0] llc_mst_ar_rptr_i, - output logic [LlcAwWidth-1:0] llc_mst_aw_data_o, - output logic [ LogDepth:0] llc_mst_aw_wptr_o, - input logic [ LogDepth:0] llc_mst_aw_rptr_i, - input logic [ LlcBWidth-1:0] llc_mst_b_data_i , - input logic [ LogDepth:0] llc_mst_b_wptr_i , - output logic [ LogDepth:0] llc_mst_b_rptr_o , - input logic [ LlcRWidth-1:0] llc_mst_r_data_i , - input logic [ LogDepth:0] llc_mst_r_wptr_i , - output logic [ LogDepth:0] llc_mst_r_rptr_o , - output logic [ LlcWWidth-1:0] llc_mst_w_data_o , - output logic [ LogDepth:0] llc_mst_w_wptr_o , - input logic [ LogDepth:0] llc_mst_w_rptr_i , - // External AXI isolate slave Ports (except the Mailbox) - input logic [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_isolate_i, - output logic [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_isolated_o, + output logic [LlcArWidth-1:0] llc_ar_data_o, + output logic [ LogDepth:0] llc_ar_wptr_o, + input logic [ LogDepth:0] llc_ar_rptr_i, + output logic [LlcAwWidth-1:0] llc_aw_data_o, + output logic [ LogDepth:0] llc_aw_wptr_o, + input logic [ LogDepth:0] llc_aw_rptr_i, + input logic [ LlcBWidth-1:0] llc_b_data_i , + input logic [ LogDepth:0] llc_b_wptr_i , + output logic [ LogDepth:0] llc_b_rptr_o , + input logic [ LlcRWidth-1:0] llc_r_data_i , + input logic [ LogDepth:0] llc_r_wptr_i , + output logic [ LogDepth:0] llc_r_rptr_o , + output logic [ LlcWWidth-1:0] llc_w_data_o , + output logic [ LogDepth:0] llc_w_wptr_o , + input logic [ LogDepth:0] llc_w_rptr_i , // External async AXI slave Ports (except the Mailbox) - output logic [iomsb(NumSlaveCDCs):0][ExtSlvArWidth-1:0] axi_ext_slv_ar_data_o, - output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_ar_wptr_o, - input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_ar_rptr_i, - output logic [iomsb(NumSlaveCDCs):0][ExtSlvAwWidth-1:0] axi_ext_slv_aw_data_o, - output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_aw_wptr_o, - input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_aw_rptr_i, - input logic [iomsb(NumSlaveCDCs):0][ ExtSlvBWidth-1:0] axi_ext_slv_b_data_i , - input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_b_wptr_i , - output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_b_rptr_o , - input logic [iomsb(NumSlaveCDCs):0][ ExtSlvRWidth-1:0] axi_ext_slv_r_data_i , - input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_r_wptr_i , - output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_r_rptr_o , - output logic [iomsb(NumSlaveCDCs):0][ ExtSlvWWidth-1:0] axi_ext_slv_w_data_o , - output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_w_wptr_o , - input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_w_rptr_i , + output cheshire_axi_ext_slv_req_t axi_ext_slv_req_o, + input cheshire_axi_ext_slv_rsp_t axi_ext_slv_rsp_i, // External async AXI master Ports - input logic [iomsb(Cfg.AxiExtNumMst):0][ExtMstArWidth-1:0] axi_ext_mst_ar_data_i, - input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_ar_wptr_i, - output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_ar_rptr_o, - input logic [iomsb(Cfg.AxiExtNumMst):0][ExtMstAwWidth-1:0] axi_ext_mst_aw_data_i, - input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_aw_wptr_i, - output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_aw_rptr_o, - output logic [iomsb(Cfg.AxiExtNumMst):0][ ExtMstBWidth-1:0] axi_ext_mst_b_data_o , - output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_b_wptr_o , - input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_b_rptr_i , - output logic [iomsb(Cfg.AxiExtNumMst):0][ ExtMstRWidth-1:0] axi_ext_mst_r_data_o , - output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_r_wptr_o , - input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_r_rptr_i , - input logic [iomsb(Cfg.AxiExtNumMst):0][ ExtMstWWidth-1:0] axi_ext_mst_w_data_i , - input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_w_wptr_i , - output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_w_rptr_o , - // Mailboxes - output cheshire_axi_ext_slv_req_t axi_mbox_slv_req_o, - input cheshire_axi_ext_slv_rsp_t axi_mbox_slv_rsp_i, + input cheshire_axi_ext_mst_req_t axi_ext_mst_req_i, + output cheshire_axi_ext_mst_rsp_t axi_ext_mst_rsp_o, // External reg demux slaves Cheshire's clock domain (sync) output cheshire_reg_ext_req_t [iomsb(NumSyncRegSlv):0] reg_ext_slv_req_o, input cheshire_reg_ext_rsp_t [iomsb(NumSyncRegSlv):0] reg_ext_slv_rsp_i, @@ -242,25 +207,10 @@ module cheshire_wrap output logic [Cfg.VgaBlueWidth -1:0] vga_blue_o ); -// All AXI slave buses -cheshire_axi_ext_slv_req_t [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_req; -cheshire_axi_ext_slv_rsp_t [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_rsp; - -cheshire_axi_ext_slv_req_t [iomsb(NumSlaveCDCs):0] axi_ext_slv_isolated_req; -cheshire_axi_ext_slv_rsp_t [iomsb(NumSlaveCDCs):0] axi_ext_slv_isolated_rsp; - -// All AXI master buses -cheshire_axi_ext_mst_req_t [iomsb(Cfg.AxiExtNumMst):0] axi_ext_mst_req; -cheshire_axi_ext_mst_rsp_t [iomsb(Cfg.AxiExtNumMst):0] axi_ext_mst_rsp; - // External LLC (DRAM) bus cheshire_axi_ext_llc_req_t axi_llc_mst_req, axi_llc_mst_isolated_req; cheshire_axi_ext_llc_rsp_t axi_llc_mst_rsp, axi_llc_mst_isolated_rsp; -// Feedthrough mailbox req/rsp: same clock domain of cheshire (no CDCs) -`AXI_ASSIGN_REQ_STRUCT(axi_mbox_slv_req_o, axi_ext_slv_req[MailboxSlvIdx]) -`AXI_ASSIGN_RESP_STRUCT(axi_ext_slv_rsp[MailboxSlvIdx], axi_mbox_slv_rsp_i) - cheshire_reg_ext_req_t [iomsb(Cfg.RegExtNumSlv):0] ext_reg_req; cheshire_reg_ext_rsp_t [iomsb(Cfg.RegExtNumSlv):0] ext_reg_rsp; @@ -291,13 +241,13 @@ cheshire_soc #( .axi_llc_mst_req_o ( axi_llc_mst_req ), .axi_llc_mst_rsp_i ( axi_llc_mst_rsp ), // External AXI crossbar ports - .axi_ext_mst_req_i ( axi_ext_mst_req ), - .axi_ext_mst_rsp_o ( axi_ext_mst_rsp ), - .axi_ext_slv_req_o ( axi_ext_slv_req ), - .axi_ext_slv_rsp_i ( axi_ext_slv_rsp ), + .axi_ext_mst_req_i ( axi_ext_mst_req_i ), + .axi_ext_mst_rsp_o ( axi_ext_mst_rsp_o ), + .axi_ext_slv_req_o ( axi_ext_slv_req_o ), + .axi_ext_slv_rsp_i ( axi_ext_slv_rsp_i ), // External reg demux slaves - .reg_ext_slv_req_o ( ext_reg_req ), - .reg_ext_slv_rsp_i ( ext_reg_rsp ), + .reg_ext_slv_req_o ( ext_reg_req ), + .reg_ext_slv_rsp_i ( ext_reg_rsp ), // Interrupts from external devices .intr_ext_i, .intr_ext_o, @@ -358,102 +308,6 @@ cheshire_soc #( .vga_blue_o ); -// Cheshire's AXI master cdc generation, the Mailbox (slave 7) -for (genvar i = 0; i < NumSlaveCDCs; i++) begin: gen_ext_slv_src_cdc - axi_isolate #( - .NumPending ( Cfg.AxiMaxSlvTrans ), - .TerminateTransaction ( 1 ), - .AtopSupport ( 1 ), - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiIdWidth ( ExtSlvIdWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .axi_req_t ( cheshire_axi_ext_slv_req_t ), - .axi_resp_t ( cheshire_axi_ext_slv_rsp_t ) - ) i_axi_ext_slave_isolate ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( axi_ext_slv_req [i] ), - .slv_resp_o ( axi_ext_slv_rsp [i] ), - .mst_req_o ( axi_ext_slv_isolated_req [i] ), - .mst_resp_i ( axi_ext_slv_isolated_rsp [i] ), - .isolate_i ( axi_ext_slv_isolate_i [i] ), - .isolated_o ( axi_ext_slv_isolated_o [i] ) - ); - - axi_cdc_src #( - .LogDepth ( LogDepth ), - .SyncStages ( CdcSyncStages ), - .aw_chan_t ( cheshire_axi_ext_slv_aw_chan_t ), - .w_chan_t ( cheshire_axi_ext_slv_w_chan_t ), - .b_chan_t ( cheshire_axi_ext_slv_b_chan_t ), - .ar_chan_t ( cheshire_axi_ext_slv_ar_chan_t ), - .r_chan_t ( cheshire_axi_ext_slv_r_chan_t ), - .axi_req_t ( cheshire_axi_ext_slv_req_t ), - .axi_resp_t ( cheshire_axi_ext_slv_rsp_t ) - ) i_cheshire_ext_slv_cdc_src ( - // synchronous slave port - .src_clk_i ( clk_i ), - .src_rst_ni ( rst_ni ), - .src_req_i ( axi_ext_slv_isolated_req [i] ), - .src_resp_o ( axi_ext_slv_isolated_rsp [i] ), - // asynchronous master port - .async_data_master_aw_data_o ( axi_ext_slv_aw_data_o [i] ), - .async_data_master_aw_wptr_o ( axi_ext_slv_aw_wptr_o [i] ), - .async_data_master_aw_rptr_i ( axi_ext_slv_aw_rptr_i [i] ), - .async_data_master_w_data_o ( axi_ext_slv_w_data_o [i] ), - .async_data_master_w_wptr_o ( axi_ext_slv_w_wptr_o [i] ), - .async_data_master_w_rptr_i ( axi_ext_slv_w_rptr_i [i] ), - .async_data_master_b_data_i ( axi_ext_slv_b_data_i [i] ), - .async_data_master_b_wptr_i ( axi_ext_slv_b_wptr_i [i] ), - .async_data_master_b_rptr_o ( axi_ext_slv_b_rptr_o [i] ), - .async_data_master_ar_data_o ( axi_ext_slv_ar_data_o [i] ), - .async_data_master_ar_wptr_o ( axi_ext_slv_ar_wptr_o [i] ), - .async_data_master_ar_rptr_i ( axi_ext_slv_ar_rptr_i [i] ), - .async_data_master_r_data_i ( axi_ext_slv_r_data_i [i] ), - .async_data_master_r_wptr_i ( axi_ext_slv_r_wptr_i [i] ), - .async_data_master_r_rptr_o ( axi_ext_slv_r_rptr_o [i] ) - ); -end - -// Cheshire's AXI slave cdc and isolate generation -for (genvar i = 0; i < Cfg.AxiExtNumMst; i++) begin: gen_ext_mst_dst_cdc - axi_cdc_dst #( - .LogDepth ( LogDepth ), - .SyncStages ( CdcSyncStages ), - .aw_chan_t ( cheshire_axi_ext_mst_aw_chan_t ), - .w_chan_t ( cheshire_axi_ext_mst_w_chan_t ), - .b_chan_t ( cheshire_axi_ext_mst_b_chan_t ), - .ar_chan_t ( cheshire_axi_ext_mst_ar_chan_t ), - .r_chan_t ( cheshire_axi_ext_mst_r_chan_t ), - .axi_req_t ( cheshire_axi_ext_mst_req_t ), - .axi_resp_t ( cheshire_axi_ext_mst_rsp_t ) - ) i_cheshire_ext_mst_cdc_dst ( - // asynchronous slave port - .async_data_slave_aw_data_i ( axi_ext_mst_aw_data_i [i] ), - .async_data_slave_aw_wptr_i ( axi_ext_mst_aw_wptr_i [i] ), - .async_data_slave_aw_rptr_o ( axi_ext_mst_aw_rptr_o [i] ), - .async_data_slave_w_data_i ( axi_ext_mst_w_data_i [i] ), - .async_data_slave_w_wptr_i ( axi_ext_mst_w_wptr_i [i] ), - .async_data_slave_w_rptr_o ( axi_ext_mst_w_rptr_o [i] ), - .async_data_slave_b_data_o ( axi_ext_mst_b_data_o [i] ), - .async_data_slave_b_wptr_o ( axi_ext_mst_b_wptr_o [i] ), - .async_data_slave_b_rptr_i ( axi_ext_mst_b_rptr_i [i] ), - .async_data_slave_ar_data_i ( axi_ext_mst_ar_data_i [i] ), - .async_data_slave_ar_wptr_i ( axi_ext_mst_ar_wptr_i [i] ), - .async_data_slave_ar_rptr_o ( axi_ext_mst_ar_rptr_o [i] ), - .async_data_slave_r_data_o ( axi_ext_mst_r_data_o [i] ), - .async_data_slave_r_wptr_o ( axi_ext_mst_r_wptr_o [i] ), - .async_data_slave_r_rptr_i ( axi_ext_mst_r_rptr_i [i] ), - // synchronous master port - .dst_clk_i ( clk_i ), - .dst_rst_ni ( rst_ni ), - .dst_req_o ( axi_ext_mst_req [i] ), - .dst_resp_i ( axi_ext_mst_rsp [i] ) - ); -end - -// AXI isolate and CDC for external LLC connection axi_isolate #( .NumPending ( Cfg.AxiMaxSlvTrans ), .TerminateTransaction ( 1 ), @@ -492,21 +346,21 @@ axi_cdc_src #( .src_req_i ( axi_llc_mst_isolated_req ), .src_resp_o ( axi_llc_mst_isolated_rsp ), // asynchronous master port - .async_data_master_aw_data_o ( llc_mst_aw_data_o ), - .async_data_master_aw_wptr_o ( llc_mst_aw_wptr_o ), - .async_data_master_aw_rptr_i ( llc_mst_aw_rptr_i ), - .async_data_master_w_data_o ( llc_mst_w_data_o ), - .async_data_master_w_wptr_o ( llc_mst_w_wptr_o ), - .async_data_master_w_rptr_i ( llc_mst_w_rptr_i ), - .async_data_master_b_data_i ( llc_mst_b_data_i ), - .async_data_master_b_wptr_i ( llc_mst_b_wptr_i ), - .async_data_master_b_rptr_o ( llc_mst_b_rptr_o ), - .async_data_master_ar_data_o ( llc_mst_ar_data_o ), - .async_data_master_ar_wptr_o ( llc_mst_ar_wptr_o ), - .async_data_master_ar_rptr_i ( llc_mst_ar_rptr_i ), - .async_data_master_r_data_i ( llc_mst_r_data_i ), - .async_data_master_r_wptr_i ( llc_mst_r_wptr_i ), - .async_data_master_r_rptr_o ( llc_mst_r_rptr_o ) + .async_data_master_aw_data_o ( llc_aw_data_o ), + .async_data_master_aw_wptr_o ( llc_aw_wptr_o ), + .async_data_master_aw_rptr_i ( llc_aw_rptr_i ), + .async_data_master_w_data_o ( llc_w_data_o ), + .async_data_master_w_wptr_o ( llc_w_wptr_o ), + .async_data_master_w_rptr_i ( llc_w_rptr_i ), + .async_data_master_b_data_i ( llc_b_data_i ), + .async_data_master_b_wptr_i ( llc_b_wptr_i ), + .async_data_master_b_rptr_o ( llc_b_rptr_o ), + .async_data_master_ar_data_o ( llc_ar_data_o ), + .async_data_master_ar_wptr_o ( llc_ar_wptr_o ), + .async_data_master_ar_rptr_i ( llc_ar_rptr_i ), + .async_data_master_r_data_i ( llc_r_data_i ), + .async_data_master_r_wptr_i ( llc_r_wptr_i ), + .async_data_master_r_rptr_o ( llc_r_rptr_o ) ); // Async reg interface: diff --git a/hw/configs/astral_noc.sv b/hw/configs/astral_noc.sv new file mode 100644 index 00000000..6a002dfd --- /dev/null +++ b/hw/configs/astral_noc.sv @@ -0,0 +1,98 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +package carfield_configuration; + +import cheshire_pkg::*; +/********************* + * AXI Configuration * + ********************/ +//L2, port 0 +localparam bit L2Port0Enable = 1; +localparam doub_bt L2Port0Base = 'h78000000; +localparam doub_bt L2Port0Size = 'h00020000; +// L2, port 1 +localparam bit L2Port1Enable = 1; +localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size; +localparam doub_bt L2Port1Size = L2Port0Size; +// Safety Island +localparam bit SafetyIslandEnable = 0; +localparam doub_bt SafetyIslandBase = 'h60000000; +localparam doub_bt SafetyIslandSize = 'h00800000; +// Spatz cluster +localparam bit SpatzClusterEnable = 0; +localparam doub_bt SpatzClusterBase = 'h51000000; +localparam doub_bt SpatzClusterSize = 'h00800000; +// PULP cluster +localparam bit PulpClusterEnable = 1; +localparam doub_bt PulpClusterBase = 'h50000000; +localparam doub_bt PulpClusterSize = 'h00800000; +// Security Island +localparam bit SecurityIslandEnable = 1; +localparam doub_bt SecurityIslandBase = 'h0; +localparam doub_bt SecurityIslandSize = 'h0; +// Peripherals +localparam bit PeriphEnable = 1; +localparam doub_bt PeriphBase = 'h21000000; +localparam doub_bt PeriphSize = 'h01000000; +// Ethernet config +localparam bit EthernetEnable = 1; +localparam doub_bt EthernetBase = PeriphBase; +localparam doub_bt EthernetSize = 'h00001000; +// Mailbox +localparam bit MailboxEnable = 1; +localparam doub_bt MailboxBase = 'h40000000; +localparam doub_bt MailboxSize = 'h00003000; +/********************* + * APB Configuration * + ********************/ +// Can +localparam bit CanEnable = 1; +localparam doub_bt CanBase = EthernetBase + EthernetSize; +localparam doub_bt CanSize = 'h00001000; +// System Timer +localparam doub_bt SystemTimerBase = 'h21004000; +localparam doub_bt SystemTimerSize = 'h00001000; +// System Advanced Timer +localparam doub_bt SystemAdvancedTimerBase = 'h21005000; +localparam doub_bt SystemAdvancedTimerSize = 'h00001000; +// System Watchdog +localparam doub_bt SystemWatchdogBase = 'h21007000; +localparam doub_bt SystemWatchdogSize = 'h00001000; +// Hyperbus Config +localparam doub_bt HyperBusBase = 'h21008000; +localparam doub_bt HyperBusSize = 'h00001000; +/************************ + * RegBus Configuration * + ***********************/ +// Padframe +localparam bit PadframeCfgEnable = 1; +localparam doub_bt PadframeCfgBase = 'h20000000; +localparam doub_bt PadframeCfgSize = 'h00001000; +// L2 ECC +localparam bit L2EccCfgEnable = 1; +localparam doub_bt L2EccCfgBase = 'h20001000; +localparam doub_bt L2EccCfgSize = 'h00001000; +// Platform control registers +localparam doub_bt PcrsBase = 'h20002000; +localparam doub_bt PcrsSize = 'h00001000; +// PLL +localparam bit PllCfgEnable = 1; +localparam doub_bt PllCfgBase = 'h20003000; +localparam doub_bt PllCfgSize = 'h00001000; +/************************** + * HyperBus Configuration * + **************************/ +localparam doub_bt NumHypPhys = 1; +localparam doub_bt NumHypChips = 2; +localparam bit DramEnable = 1; +localparam doub_bt DramBase = 'h80000000; +localparam doub_bt DramSize = 'h80000000; +// Cheshire slave +localparam doub_bt CheshireBase = 'h00000000; +localparam doub_bt CheshireSize = PeriphBase; + +endpackage diff --git a/hw/noc_wrap.sv b/hw/noc_wrap.sv new file mode 100644 index 00000000..9eb91118 --- /dev/null +++ b/hw/noc_wrap.sv @@ -0,0 +1,274 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +module noc_wrap #( + parameter cheshire_pkg::cheshire_cfg_t Cfg = '0, + parameter int unsigned LogDepth = 3, + parameter int unsigned CdcSyncStages = 2, + // NoC master ports connect to external slave devices, and viceversa + parameter int unsigned NumNocSlv = carfield_pkg::CarfieldAxiNumMasters, + parameter int unsigned NumNocMst = carfield_pkg::CarfieldAxiNumSlaves - 1, + parameter type noc_llc_ar_chan_t = logic, + parameter type noc_llc_aw_chan_t = logic, + parameter type noc_llc_b_chan_t = logic, + parameter type noc_llc_r_chan_t = logic, + parameter type noc_llc_w_chan_t = logic, + parameter type noc_llc_req_t = logic, + parameter type noc_llc_rsp_t = logic, + parameter type noc_mst_ar_chan_t = logic, + parameter type noc_mst_aw_chan_t = logic, + parameter type noc_mst_b_chan_t = logic, + parameter type noc_mst_r_chan_t = logic, + parameter type noc_mst_w_chan_t = logic, + parameter type noc_mst_req_t = logic, + parameter type noc_mst_rsp_t = logic, + parameter type noc_slv_ar_chan_t = logic, + parameter type noc_slv_aw_chan_t = logic, + parameter type noc_slv_b_chan_t = logic, + parameter type noc_slv_r_chan_t = logic, + parameter type noc_slv_w_chan_t = logic, + parameter type noc_slv_req_t = logic, + parameter type noc_slv_rsp_t = logic, + parameter int unsigned NocSlvIdWidth = Cfg.AxiMstIdWidth, + parameter int unsigned LlcIdWidth = NocSlvIdWidth + Cfg.LlcNotBypass, + // LLC Parameters + parameter int unsigned LlcArWidth = (2**LogDepth)* + axi_pkg::ar_width(Cfg.AddrWidth , + LlcIdWidth , + Cfg.AxiUserWidth), + parameter int unsigned LlcAwWidth = (2**LogDepth)* + axi_pkg::aw_width(Cfg.AddrWidth , + LlcIdWidth , + Cfg.AxiUserWidth), + parameter int unsigned LlcBWidth = (2**LogDepth)* + axi_pkg::b_width(LlcIdWidth , + Cfg.AxiUserWidth), + parameter int unsigned LlcRWidth = (2**LogDepth)* + axi_pkg::r_width(Cfg.AxiDataWidth, + LlcIdWidth , + Cfg.AxiUserWidth), + parameter int unsigned LlcWWidth = (2**LogDepth)* + axi_pkg::w_width(Cfg.AxiDataWidth, + Cfg.AxiUserWidth), + // External slaves Parameters + localparam int unsigned NocSlvArWidth = (2**LogDepth)* + axi_pkg::ar_width(Cfg.AddrWidth , + NocSlvIdWidth , + Cfg.AxiUserWidth), + localparam int unsigned NocSlvAwWidth = (2**LogDepth)* + axi_pkg::aw_width(Cfg.AddrWidth , + NocSlvIdWidth , + Cfg.AxiUserWidth), + localparam int unsigned NocSlvBWidth = (2**LogDepth)* + axi_pkg::b_width(NocSlvIdWidth , + Cfg.AxiUserWidth), + localparam int unsigned NocSlvRWidth = (2**LogDepth)* + axi_pkg::r_width(Cfg.AxiDataWidth, + NocSlvIdWidth , + Cfg.AxiUserWidth), + localparam int unsigned NocSlvWWidth = (2**LogDepth)* + axi_pkg::w_width(Cfg.AxiDataWidth, + Cfg.AxiUserWidth), + // External Master Parameters + localparam int unsigned NocMstArWidth = (2**LogDepth)* + axi_pkg::ar_width(Cfg.AddrWidth , + Cfg.AxiMstIdWidth, + Cfg.AxiUserWidth ), + localparam int unsigned NocMstAwWidth = (2**LogDepth)* + axi_pkg::aw_width(Cfg.AddrWidth , + Cfg.AxiMstIdWidth, + Cfg.AxiUserWidth ), + localparam int unsigned NocMstBWidth = (2**LogDepth)* + axi_pkg::b_width(Cfg.AxiMstIdWidth, + Cfg.AxiUserWidth ), + localparam int unsigned NocMstRWidth = (2**LogDepth)* + axi_pkg::r_width(Cfg.AxiDataWidth , + Cfg.AxiMstIdWidth, + Cfg.AxiUserWidth ), + localparam int unsigned NocMstWWidth = (2**LogDepth)* + axi_pkg::w_width(Cfg.AxiDataWidth, + Cfg.AxiUserWidth) +)( + input logic clk_i, + input logic rst_ni, + input logic [NumNocMst-1:0] noc_ext_slv_isolate_i, + output logic [NumNocMst-1:0] noc_ext_slv_isolated_o, + input noc_slv_req_t cheshire_slv_req_i, + output noc_slv_rsp_t cheshire_slv_rsp_o, + output noc_mst_req_t cheshire_mst_req_o, + input noc_mst_rsp_t cheshire_mst_rsp_i, + output noc_mst_req_t mailbox_mst_req_o, + input noc_mst_rsp_t mailbox_mst_rsp_i, + // External async AXI master Ports + output logic [NumNocMst-1:0][NocMstArWidth-1:0] noc_ext_mst_ar_data_o, + output logic [NumNocMst-1:0][ LogDepth:0] noc_ext_mst_ar_wptr_o, + input logic [NumNocMst-1:0][ LogDepth:0] noc_ext_mst_ar_rptr_i, + output logic [NumNocMst-1:0][NocMstAwWidth-1:0] noc_ext_mst_aw_data_o, + output logic [NumNocMst-1:0][ LogDepth:0] noc_ext_mst_aw_wptr_o, + input logic [NumNocMst-1:0][ LogDepth:0] noc_ext_mst_aw_rptr_i, + input logic [NumNocMst-1:0][ NocMstBWidth-1:0] noc_ext_mst_b_data_i , + input logic [NumNocMst-1:0][ LogDepth:0] noc_ext_mst_b_wptr_i , + output logic [NumNocMst-1:0][ LogDepth:0] noc_ext_mst_b_rptr_o , + input logic [NumNocMst-1:0][ NocMstRWidth-1:0] noc_ext_mst_r_data_i , + input logic [NumNocMst-1:0][ LogDepth:0] noc_ext_mst_r_wptr_i , + output logic [NumNocMst-1:0][ LogDepth:0] noc_ext_mst_r_rptr_o , + output logic [NumNocMst-1:0][ NocMstWWidth-1:0] noc_ext_mst_w_data_o , + output logic [NumNocMst-1:0][ LogDepth:0] noc_ext_mst_w_wptr_o , + input logic [NumNocMst-1:0][ LogDepth:0] noc_ext_mst_w_rptr_i , + // External async AXI slave Ports + input logic [NumNocSlv-1:0][NocSlvArWidth-1:0] noc_ext_slv_ar_data_i, + input logic [NumNocSlv-1:0][ LogDepth:0] noc_ext_slv_ar_wptr_i, + output logic [NumNocSlv-1:0][ LogDepth:0] noc_ext_slv_ar_rptr_o, + input logic [NumNocSlv-1:0][NocSlvAwWidth-1:0] noc_ext_slv_aw_data_i, + input logic [NumNocSlv-1:0][ LogDepth:0] noc_ext_slv_aw_wptr_i, + output logic [NumNocSlv-1:0][ LogDepth:0] noc_ext_slv_aw_rptr_o, + output logic [NumNocSlv-1:0][ NocSlvBWidth-1:0] noc_ext_slv_b_data_o , + output logic [NumNocSlv-1:0][ LogDepth:0] noc_ext_slv_b_wptr_o , + input logic [NumNocSlv-1:0][ LogDepth:0] noc_ext_slv_b_rptr_i , + output logic [NumNocSlv-1:0][ NocSlvRWidth-1:0] noc_ext_slv_r_data_o , + output logic [NumNocSlv-1:0][ LogDepth:0] noc_ext_slv_r_wptr_o , + input logic [NumNocSlv-1:0][ LogDepth:0] noc_ext_slv_r_rptr_i , + input logic [NumNocSlv-1:0][ NocSlvWWidth-1:0] noc_ext_slv_w_data_i , + input logic [NumNocSlv-1:0][ LogDepth:0] noc_ext_slv_w_wptr_i , + output logic [NumNocSlv-1:0][ LogDepth:0] noc_ext_slv_w_rptr_o +); + +noc_mst_req_t [NumNocMst-1:0] mst_req, mst_isolated_req; +noc_mst_rsp_t [NumNocMst-1:0] mst_rsp, mst_isolated_rsp; + +noc_slv_req_t [NumNocSlv-1:0] slv_req; +noc_slv_rsp_t [NumNocSlv-1:0] slv_rsp; + +noc_llc_req_t llc_req, llc_isolated_req; +noc_llc_rsp_t llc_rsp, llc_isolated_rsp; + +for (genvar i = 0; i < NumNocMst; i++) begin: gen_mst_src_cdc + + axi_isolate #( + .NumPending ( Cfg.AxiMaxMstTrans ), + .TerminateTransaction ( 1 ), + .AtopSupport ( 1 ), + .AxiAddrWidth ( Cfg.AddrWidth ), + .AxiDataWidth ( Cfg.AxiDataWidth ), + .AxiIdWidth ( Cfg.AxiMstIdWidth ), + .AxiUserWidth ( Cfg.AxiUserWidth ), + .axi_req_t ( noc_mst_req_t ), + .axi_resp_t ( noc_mst_rsp_t ) + ) i_slave_isolate ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( mst_req [i] ), + .slv_resp_o ( mst_rsp [i] ), + .mst_req_o ( mst_isolated_req [i] ), + .mst_resp_i ( mst_isolated_rsp [i] ), + .isolate_i ( noc_ext_slv_isolate_i [i] ), + .isolated_o ( noc_ext_slv_isolated_o [i] ) + ); + + axi_cdc_src #( + .LogDepth ( LogDepth ), + .SyncStages ( CdcSyncStages ), + .aw_chan_t ( noc_mst_aw_chan_t ), + .w_chan_t ( noc_mst_w_chan_t ), + .b_chan_t ( noc_mst_b_chan_t ), + .ar_chan_t ( noc_mst_ar_chan_t ), + .r_chan_t ( noc_mst_r_chan_t ), + .axi_req_t ( noc_mst_req_t ), + .axi_resp_t ( noc_mst_rsp_t ) + ) i_slv_cdc_src ( + // synchronous slave port + .src_clk_i ( clk_i ), + .src_rst_ni ( rst_ni ), + .src_req_i ( mst_isolated_req [i] ), + .src_resp_o ( mst_isolated_rsp [i] ), + // asynchronous master port + .async_data_master_aw_data_o ( noc_ext_mst_aw_data_o [i] ), + .async_data_master_aw_wptr_o ( noc_ext_mst_aw_wptr_o [i] ), + .async_data_master_aw_rptr_i ( noc_ext_mst_aw_rptr_i [i] ), + .async_data_master_w_data_o ( noc_ext_mst_w_data_o [i] ), + .async_data_master_w_wptr_o ( noc_ext_mst_w_wptr_o [i] ), + .async_data_master_w_rptr_i ( noc_ext_mst_w_rptr_i [i] ), + .async_data_master_b_data_i ( noc_ext_mst_b_data_i [i] ), + .async_data_master_b_wptr_i ( noc_ext_mst_b_wptr_i [i] ), + .async_data_master_b_rptr_o ( noc_ext_mst_b_rptr_o [i] ), + .async_data_master_ar_data_o ( noc_ext_mst_ar_data_o [i] ), + .async_data_master_ar_wptr_o ( noc_ext_mst_ar_wptr_o [i] ), + .async_data_master_ar_rptr_i ( noc_ext_mst_ar_rptr_i [i] ), + .async_data_master_r_data_i ( noc_ext_mst_r_data_i [i] ), + .async_data_master_r_wptr_i ( noc_ext_mst_r_wptr_i [i] ), + .async_data_master_r_rptr_o ( noc_ext_mst_r_rptr_o [i] ) + ); +end + +for (genvar i = 0; i < NumNocSlv; i++) begin: gen_ext_slv_dst_cdc + axi_cdc_dst #( + .LogDepth ( LogDepth ), + .SyncStages ( CdcSyncStages ), + .aw_chan_t ( noc_slv_aw_chan_t ), + .w_chan_t ( noc_slv_w_chan_t ), + .b_chan_t ( noc_slv_b_chan_t ), + .ar_chan_t ( noc_slv_ar_chan_t ), + .r_chan_t ( noc_slv_r_chan_t ), + .axi_req_t ( noc_slv_req_t ), + .axi_resp_t ( noc_slv_rsp_t ) + ) i_cheshire_ext_mst_cdc_dst ( + // asynchronous slave port + .async_data_slave_aw_data_i ( noc_ext_slv_aw_data_i [i] ), + .async_data_slave_aw_wptr_i ( noc_ext_slv_aw_wptr_i [i] ), + .async_data_slave_aw_rptr_o ( noc_ext_slv_aw_rptr_o [i] ), + .async_data_slave_w_data_i ( noc_ext_slv_w_data_i [i] ), + .async_data_slave_w_wptr_i ( noc_ext_slv_w_wptr_i [i] ), + .async_data_slave_w_rptr_o ( noc_ext_slv_w_rptr_o [i] ), + .async_data_slave_b_data_o ( noc_ext_slv_b_data_o [i] ), + .async_data_slave_b_wptr_o ( noc_ext_slv_b_wptr_o [i] ), + .async_data_slave_b_rptr_i ( noc_ext_slv_b_rptr_i [i] ), + .async_data_slave_ar_data_i ( noc_ext_slv_ar_data_i [i] ), + .async_data_slave_ar_wptr_i ( noc_ext_slv_ar_wptr_i [i] ), + .async_data_slave_ar_rptr_o ( noc_ext_slv_ar_rptr_o [i] ), + .async_data_slave_r_data_o ( noc_ext_slv_r_data_o [i] ), + .async_data_slave_r_wptr_o ( noc_ext_slv_r_wptr_o [i] ), + .async_data_slave_r_rptr_i ( noc_ext_slv_r_rptr_i [i] ), + // synchronous master port + .dst_clk_i ( clk_i ), + .dst_rst_ni ( rst_ni ), + .dst_req_o ( slv_req [i] ), + .dst_resp_i ( slv_rsp [i] ) + ); +end + +floo_astral_noc i_astral_noc ( + .clk_i, + .rst_ni, + .test_enable_i ( '0 ), + .cheshire_axi_in_req_i ( cheshire_slv_req_i ), + .cheshire_axi_in_rsp_o ( cheshire_slv_rsp_o ), + .cheshire_axi_out_req_o ( cheshire_mst_req_o ), + .cheshire_axi_out_rsp_i ( cheshire_mst_rsp_i ), + .opentitan_main_axi_in_req_i ( slv_req [carfield_pkg::SecurityIslandTlulMstIdx] ), + .opentitan_main_axi_in_rsp_o ( slv_rsp [carfield_pkg::SecurityIslandTlulMstIdx] ), + .opentitan_dma_axi_in_req_i ( slv_req [carfield_pkg::SecurityIslandiDMAMstIdx] ), + .opentitan_dma_axi_in_rsp_o ( slv_rsp [carfield_pkg::SecurityIslandiDMAMstIdx] ), + .l2_port0_axi_out_req_o ( mst_req [carfield_pkg::L2Port0SlvIdx] ), + .l2_port0_axi_out_rsp_i ( mst_rsp [carfield_pkg::L2Port0SlvIdx] ), + .l2_port1_axi_out_req_o ( mst_req [carfield_pkg::L2Port1SlvIdx] ), + .l2_port1_axi_out_rsp_i ( mst_rsp [carfield_pkg::L2Port1SlvIdx] ), + .cluster_axi_in_req_i ( slv_req [carfield_pkg::IntClusterMstIdx] ), + .cluster_axi_in_rsp_o ( slv_rsp [carfield_pkg::IntClusterMstIdx] ), + .cluster_axi_out_req_o ( mst_req [carfield_pkg::IntClusterSlvIdx] ), + .cluster_axi_out_rsp_i ( mst_rsp [carfield_pkg::IntClusterSlvIdx] ), + .ethernet_axi_in_req_i ( slv_req [carfield_pkg::EthernetMstIdx] ), + .ethernet_axi_in_rsp_o ( slv_rsp [carfield_pkg::EthernetMstIdx] ), + .mbox_axi_out_req_o ( mailbox_mst_req_o ), + .mbox_axi_out_rsp_i ( mailbox_mst_rsp_i ), + .peripherals_axi_out_req_o ( mst_req [carfield_pkg::PeriphsSlvIdx] ), + .peripherals_axi_out_rsp_i ( mst_rsp [carfield_pkg::PeriphsSlvIdx] ), + .dram_axi_in_req_i ( '0 ), + .dram_axi_in_rsp_o ( ), + .dram_axi_out_req_o ( ), + .dram_axi_out_rsp_i ( '0 ) +); + +endmodule: noc_wrap diff --git a/sw/include/car_memory_map.h b/sw/include/car_memory_map.h index 9729716b..1b705e17 100644 --- a/sw/include/car_memory_map.h +++ b/sw/include/car_memory_map.h @@ -113,7 +113,7 @@ extern void *__base_l2; #define CAR_CLIC_CFG_BASE_ADDR(id) 0x000008000000 // from carfield proper -#define CAR_PERIPHS_BASE_ADDR 0x20000000 +#define CAR_PERIPHS_BASE_ADDR 0x21000000 #define CAR_ETHERNET_OFFSET 0x0000000 #define CAR_CAN_OFFSET 0x0001000 @@ -159,7 +159,7 @@ extern void *__base_l2; #define MBOX_CAR_LETTER1(id) (CAR_MBOX_BASE_ADDR + MBOX_LETTER1_OFFSET + (id*0x100)) // PLL -#define CAR_PLL_BASE_ADDRESS 0x21003000 +#define CAR_PLL_BASE_ADDRESS 0x20003000 #define PLL_ADDR_SPACE 0x200 #define PLL_BASE_ADDRESS(id) (CAR_PLL_BASE_ADDRESS + (id+1)*PLL_ADDR_SPACE) diff --git a/sw/include/car_params.h b/sw/include/car_params.h index ab515a23..e9e09793 100644 --- a/sw/include/car_params.h +++ b/sw/include/car_params.h @@ -10,7 +10,7 @@ #pragma once #ifndef LINUX_APP // Hardcoded const pointers -const void* car_soc_ctrl = 0x21002000; +const void* car_soc_ctrl = 0x20002000; const void* car_safety_island = 0x60000000; const void* car_integer_cluster = 0x50000000; const void* car_spatz_cluster = 0x51000000;