diff --git a/carfield.mk b/carfield.mk
index e2901b33..f7c89147 100644
--- a/carfield.mk
+++ b/carfield.mk
@@ -304,6 +304,11 @@ update_plic: $(CHS_ROOT)/hw/rv_plic.cfg.hjson
 update_serial_link: $(CHS_ROOT)/hw/serial_link.hjson
 	sed -i 's/\(default: "\)8/\116/' $<
 
+## Install basic python packages used to build Cheshire HW.
+.PHONY: python_requirements
+python_requirements:
+	pip install tabulate hjson
+
 ## Generate Spatz HW starting from a configuration file. This includes register file, memory map,
 ## interconnect parametrization.
 .PHONY: spatzd-hw-init
diff --git a/target/sim/sim.mk b/target/sim/sim.mk
index 3f4cee04..e66ffefb 100644
--- a/target/sim/sim.mk
+++ b/target/sim/sim.mk
@@ -6,7 +6,7 @@
 
 ## @section Carfield platform simulation
 
-QUESTA ?= questa-2023.4
+QUESTA ?=
 TBENCH ?= tb_astral
 
 ## Get HyperRAM verification IP (VIP) for simulation
diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk
index 973e7e4f..eedc9547 100644
--- a/target/xilinx/xilinx.mk
+++ b/target/xilinx/xilinx.mk
@@ -10,13 +10,13 @@
 # Makefile variables (user inputs are in capital letters)
 #
 
-VIVADO   ?= vitis-2020.2 vivado
+VIVADO ?= vivado
 
 XILINX_PROJECT ?= carfield
 # XILINX_FLAVOR in {vanilla,bd} see carfield_bd.mk
-XILINX_FLAVOR  ?= bd
+XILINX_FLAVOR  ?= vanilla
 # XILINX_BOARD in {vcu128, vcu118}
-XILINX_BOARD   ?= vcu128
+XILINX_BOARD   ?= vcu118
 
 ifeq ($(XILINX_BOARD),vcu128)
 	xilinx_part       := xcvu37p-fsvh2892-2L-e