diff --git a/Bender.lock b/Bender.lock index 5897b27f..91339789 100644 --- a/Bender.lock +++ b/Bender.lock @@ -16,8 +16,8 @@ packages: - common_verification - tech_cells_generic common_cells: - revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f - version: 1.32.0 + revision: 13f28aa0021fc22c0d01a12d618fda58d2c93239 + version: 1.33.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: diff --git a/Bender.yml b/Bender.yml index 1b836e97..9b9094c5 100644 --- a/Bender.yml +++ b/Bender.yml @@ -14,7 +14,7 @@ package: - "Axel Vanoni " dependencies: - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.33.0 } common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 } axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.3 } @@ -44,13 +44,12 @@ sources: - src/backend/idma_error_handler.sv - src/backend/idma_init_read.sv - src/backend/idma_init_write.sv + - src/backend/idma_legalizer_page_splitter.sv + - src/backend/idma_legalizer_pow2_splitter.sv - src/backend/idma_obi_read.sv - src/backend/idma_obi_write.sv - src/backend/idma_tilelink_read.sv - src/backend/idma_tilelink_write.sv - - src/future/idma_improved_fifo.sv - - src/future/idma_legalizer_page_splitter.sv - - src/future/idma_legalizer_pow2_splitter.sv # Generated content - target: rtl @@ -114,7 +113,6 @@ sources: - test/future/idma_tb_per2axi.sv - test/future/idma_obi_asserter.sv - test/future/TLToAXI4.v - - test/future/tb_idma_improved_fifo.sv - test/midend/tb_idma_nd_midend.sv - test/midend/tb_idma_rt_midend.sv # Level 2 diff --git a/VERSION b/VERSION index 5d4294b9..eace7d32 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -0.5.1 \ No newline at end of file +0.6.0-beta \ No newline at end of file diff --git a/src/backend/idma_dataflow_element.sv b/src/backend/idma_dataflow_element.sv index ca9599ae..00744710 100644 --- a/src/backend/idma_dataflow_element.sv +++ b/src/backend/idma_dataflow_element.sv @@ -34,11 +34,11 @@ module idma_dataflow_element #( // buffer is implemented as an array of FIFOs for (genvar i = 0; i < StrbWidth; i++) begin : gen_fifo_buffer - idma_improved_fifo #( + passthrough_stream_fifo #( .type_t ( byte_t ), .Depth ( BufferDepth ), .PrintInfo ( PrintFifoInfo ) - ) i_byte_buffer ( + ) i_passthrough_stream_fifo ( .clk_i, .rst_ni, .testmode_i, diff --git a/src/future/idma_legalizer_page_splitter.sv b/src/backend/idma_legalizer_page_splitter.sv similarity index 100% rename from src/future/idma_legalizer_page_splitter.sv rename to src/backend/idma_legalizer_page_splitter.sv diff --git a/src/future/idma_legalizer_pow2_splitter.sv b/src/backend/idma_legalizer_pow2_splitter.sv similarity index 100% rename from src/future/idma_legalizer_pow2_splitter.sv rename to src/backend/idma_legalizer_pow2_splitter.sv diff --git a/src/future/idma_improved_fifo.sv b/src/future/idma_improved_fifo.sv deleted file mode 100644 index d38e8a5e..00000000 --- a/src/future/idma_improved_fifo.sv +++ /dev/null @@ -1,142 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Authors: -// - Thomas Benz -// - Tobias Senti - -`include "common_cells/assertions.svh" -`include "common_cells/registers.svh" -`include "idma/guard.svh" - -/// Optimal implementation of a stream FIFO -module idma_improved_fifo #( - /// Depth can be arbitrary from 2 to 2**32 - parameter int unsigned Depth = 32'd8, - /// Print information when the simulation launches - parameter bit PrintInfo = 1'b0, - /// If the FIFO is full, allow reading and writing in the same cycle - parameter bit SameCycleRW = 1'b1, - /// Type of the FIFO - parameter type type_t = logic -) ( - /// Clock - input logic clk_i, - /// Asynchronous reset active low - input logic rst_ni, - /// Fifo flush - input logic flush_i, - /// Bypass clock gate - input logic testmode_i, - /// data to push into the fifo - input type_t data_i, - /// input data valid - input logic valid_i, - /// fifo is not full - output logic ready_o, - /// output data - output type_t data_o, - /// fifo is not empty - output logic valid_o, - /// pop head from fifo - input logic ready_i -); - /// Bit Width of the read and write pointers - /// One additional bit to detect overflows - localparam int unsigned PointerWidth = $clog2(Depth) + 1; - - //-------------------------------------- - // Prevent Depth 0 - //-------------------------------------- - // Throw an error if depth is 0 and 1 - `IDMA_NONSYNTH_BLOCK( - if (Depth < 32'd2) begin : gen_fatal - initial begin - $fatal(1, "FIFO of depth %d does not make any sense!", Depth); - end - end - ) - - // print info - `IDMA_NONSYNTH_BLOCK( - if (PrintInfo) begin : gen_info - initial begin - $info("[%m] Instantiate stream FIFO of depth %d with Pointer Width of %d", Depth, PointerWidth); - end - end - ) - - // Read and write pointers - logic [PointerWidth-1:0] read_ptr_d, read_ptr_q; - logic [PointerWidth-1:0] write_ptr_d, write_ptr_q; - - // Data - type_t [Depth-1 :0] data_d, data_q; - - // Data Clock gate - logic clock_gate; - - assign data_o = data_q[read_ptr_q[PointerWidth-2:0]]; - - // Logic - always_comb begin - // Default - clock_gate = 1'b0; - read_ptr_d = read_ptr_q; - write_ptr_d = write_ptr_q; - data_d = data_q; - - if (flush_i) begin // Flush - read_ptr_d = '0; - write_ptr_d = '0; - valid_o = 1'b0; - ready_o = 1'b0; - end else begin - // Read - valid_o = read_ptr_q[PointerWidth-1] == write_ptr_q[PointerWidth-1] - ? read_ptr_q[PointerWidth-2:0] != write_ptr_q[PointerWidth-2:0] : 1'b1; - if (ready_i) begin - if (read_ptr_q[PointerWidth-2:0] == (Depth-1)) begin - // On overflow reset pointer to zero and flip imaginary bit - read_ptr_d[PointerWidth-2:0] = '0; - read_ptr_d[PointerWidth-1] = !read_ptr_q[PointerWidth-1]; - end else begin - // Increment counter - read_ptr_d = read_ptr_q + 'd1; - end - end - - // Write -> Also able to write if we read in the same cycle - ready_o = (read_ptr_q[PointerWidth-1] == write_ptr_q[PointerWidth-1] - ? 1'b1 : write_ptr_q[PointerWidth-2:0] != read_ptr_q[PointerWidth-2:0]) - || (SameCycleRW && ready_i && valid_o); - - if (valid_i) begin - clock_gate = 1'b1; - data_d[write_ptr_q[PointerWidth-2:0]] = data_i; - - if (write_ptr_q[PointerWidth-2:0] == (Depth-1)) begin - // On overflow reset pointer to zero and flip imaginary bit - write_ptr_d[PointerWidth-2:0] = '0; - write_ptr_d[PointerWidth-1] = !write_ptr_q[PointerWidth-1]; - end else begin - // Increment pointer - write_ptr_d = write_ptr_q + 'd1; - end - end - end - end - - // Flip Flops - `FF( read_ptr_q, read_ptr_d, '0, clk_i, rst_ni) - `FF(write_ptr_q, write_ptr_d, '0, clk_i, rst_ni) - - `FFL(data_q, data_d, clock_gate || testmode_i, '0, clk_i, rst_ni) - - // no full push - `ASSERT_NEVER(CheckFullPush, (!ready_o & valid_i), clk_i, !rst_ni) - // empty pop - `ASSERT_NEVER(CheckEmptyPop, (!valid_o & ready_i), clk_i, !rst_ni) - -endmodule diff --git a/test/future/tb_idma_improved_fifo.sv b/test/future/tb_idma_improved_fifo.sv deleted file mode 100644 index 53d065ca..00000000 --- a/test/future/tb_idma_improved_fifo.sv +++ /dev/null @@ -1,133 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Authors: -// - Tobias Senti - -`timescale 1ns/1ns -module tb_idma_improved_fifo #( - parameter int unsigned TCK = 10, - parameter int unsigned DataWidth = 8, - parameter int unsigned Depth = 10, - parameter int unsigned NumStims = 1000, - parameter int unsigned WriteProbability = 10, - parameter int unsigned ReadProbability = 10, - parameter bit SameCycleRW = 1'b1 -) (); - typedef logic [DataWidth-1:0] data_t; - - int unsigned applied_stims, acquired_stims; - - logic clk, rst_n; - - data_t in_data, out_data; - logic in_valid, in_ready, out_valid, out_ready; - - // Data queues - data_t app_queue[$], acq_queue[$]; - - //Clock generator - clk_rst_gen #( - .ClkPeriod ( TCK ), - .RstClkCycles ( 1 ) - ) i_clk_rst_gen ( - .clk_o ( clk ), - .rst_no ( rst_n ) - ); - - // DUT - idma_improved_fifo #( - .Depth ( Depth ), - .type_t ( data_t ), - .PrintInfo ( 1'b1 ), - .SameCycleRW ( SameCycleRW ) - ) dut ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), - - .data_i ( (in_valid && in_ready) ? in_data : 'x ), - .valid_i ( in_valid && in_ready ), - .ready_o ( in_ready ), - - .data_o ( out_data ), - .valid_o ( out_valid ), - .ready_i ( out_ready && out_valid ) - ); - - // Application - initial begin - applied_stims = 0; - in_data = '0; - in_valid = 1'b0; - - // Wait for reset - wait(rst_n); - - $display("Started application!"); - - while(applied_stims < NumStims) begin - @(negedge clk); - in_valid = $urandom_range(0, WriteProbability) == 0; - in_data = $urandom(); - @(posedge clk); - if (in_valid && in_ready) begin - $display("%d Applied: %d", applied_stims, in_data); - app_queue.push_back(in_data); - applied_stims++; - end - end - in_valid = 1'b0; - - $display("Applied %d stimuli", applied_stims); - end - - // Acquisition - initial begin - acquired_stims = 0; - out_ready = 1'b0; - - // Wait for reset - wait(rst_n); - - $display("Started acquisition!"); - - forever begin - @(negedge clk); - out_ready = $urandom_range(0, ReadProbability) == 0; - @(posedge clk); - if (out_valid && out_ready) begin - $display("%d Acquired: %d", acquired_stims, out_data); - acq_queue.push_back(out_data); - acquired_stims++; - end - end - end - - // Response Checking - initial begin - int unsigned num_errors; - data_t acq_data, app_data; - - num_errors = 0; - - while((acquired_stims < NumStims) || (applied_stims < NumStims)) begin - wait((app_queue.size() != 0) && (acq_queue.size() != 0)); - - acq_data = acq_queue.pop_front(); - app_data = app_queue.pop_front(); - - if (app_data != acq_data) begin - $display("Missmatch! Applied: %d Acquired: %d", app_data, acq_data); - num_errors++; - end else begin - $display("Match! Applied: %d Acquired: %d", app_data, acq_data); - end - end - $display("Applied %d stimuli and acquired %d responses", applied_stims, acquired_stims); - $display("Errors: %d", num_errors); - $stop(); - end -endmodule : tb_idma_improved_fifo