From c0c5dca263c58ee99b4f249d9bece21ab28d59f1 Mon Sep 17 00:00:00 2001 From: Thomas Benz Date: Fri, 13 Jan 2023 15:58:08 +0100 Subject: [PATCH] Towards Release --- .ci/gitlab-ci.yml.tpl | 5 +- .github/verible.waiver | 13 + .github/workflows/analyze.yml | 66 + .github/workflows/build.yml | 68 + .github/workflows/ci.yml | 207 -- .github/workflows/docs.yml | 80 + .github/workflows/lint.yml | 127 ++ .github/yamllint-conf.yml | 26 + .gitignore | 27 +- .gitlab-ci.yml | 193 -- Bender.local | 2 + Bender.lock | 51 +- Bender.yml | 98 +- Makefile | 387 +--- README.md | 13 +- doc/.gitignore | 1 + doc/Makefile | 38 - doc/{images => fig}/backend.png | Bin doc/{images => fig}/backend_buffer.png | Bin doc/{images => fig}/bslk_thumb.png | Bin doc/{images => fig}/iDMA_overview | 0 doc/{images => fig}/iDMA_overview.pdf | Bin doc/{images => fig}/iDMA_overview.svg | 0 doc/{images => fig}/verification.png | Bin doc/{source => src}/backend.rst | 4 +- doc/{source => src}/conf.py | 8 +- doc/{source => src}/error_handling.rst | 0 doc/{source => src}/frontend.rst | 0 doc/{source => src}/frontends/ariane_fe.rst | 4 + doc/{source => src}/frontends/register_fe.rst | 7 +- doc/{source => src}/frontends/snitch_fe.rst | 0 doc/{source => src}/index.rst | 20 +- doc/{source => src}/midend.rst | 0 doc/{source => src}/system_integration.rst | 0 doc/{source => src}/verification.rst | 2 +- idma.mk | 401 ++++ jobs.json => jobs/jobs.json | 46 +- logs/.gitkeep | 0 requirements.txt | 2 +- scripts/check-license | 10 - scripts/list-contributors | 13 +- scripts/list-todos | 13 +- scripts/python-lint | 19 - scripts/verible-lint | 25 - scripts/waves/vsim_backend.do.tpl | 173 -- src/backend/.gitignore | 2 + src/backend/Bender.yml.tpl | 43 - src/backend/{src => }/idma_axi_read.sv | 20 +- src/backend/{src => }/idma_axi_write.sv | 29 +- ...dma_axi_lite_read.sv => idma_axil_read.sv} | 25 +- ...a_axi_lite_write.sv => idma_axil_write.sv} | 26 +- ...a_axi_stream_read.sv => idma_axis_read.sv} | 21 +- ...axi_stream_write.sv => idma_axis_write.sv} | 17 +- src/backend/{src => }/idma_channel_coupler.sv | 11 +- .../{src => }/idma_dataflow_element.sv | 24 +- src/backend/{src => }/idma_error_handler.sv | 51 +- src/backend/{src => }/idma_init_read.sv | 19 +- src/backend/{src => }/idma_obi_read.sv | 17 +- src/backend/{src => }/idma_obi_write.sv | 10 +- src/backend/{src => }/idma_tilelink_read.sv | 22 +- src/backend/{src => }/idma_tilelink_write.sv | 28 +- src/backend/src/idma_buffer.sv | 54 - src/backend/src/idma_legalizer.sv.tpl | 1027 ---------- src/backend/src/idma_stream_fifo.sv | 128 -- src/backend/{src => tpl}/idma_backend.sv.tpl | 340 ++-- .../{src => tpl}/idma_backend_synth.sv.tpl | 67 +- src/backend/tpl/idma_legalizer.sv.tpl | 670 +++++++ .../{src => tpl}/idma_transport_layer.sv.tpl | 94 +- .../idma_axi.yaml => db/idma_axi.yml} | 63 +- .../idma_axi_lite.yml} | 51 +- .../idma_axi_stream.yml} | 45 +- .../idma_init.yaml => db/idma_init.yml} | 23 +- .../idma_obi.yaml => db/idma_obi.yml} | 40 +- .../idma_tilelink.yml} | 69 +- ...esc64_frontend.hjson => idma_desc64.hjson} | 4 +- src/frontends/desc64/idma_desc64_frontend.h | 31 - .../desc64/idma_desc64_frontend.html | 46 - src/frontends/desc64/idma_desc64_reg_pkg.sv | 59 - src/frontends/desc64/idma_desc64_reg_top.sv | 207 -- .../desc64/idma_desc64_reg_wrapper.sv | 5 +- .../desc64/idma_desc64_shared_counter.sv | 3 +- src/frontends/desc64/idma_desc64_synth.sv | 5 +- src/frontends/desc64/idma_desc64_synth_pkg.sv | 5 +- src/frontends/desc64/idma_desc64_top.sv | 30 +- src/frontends/desc64/reg_html.css | 74 - src/frontends/idma_transfer_id_gen.sv | 3 +- .../axi_dma_error_handler.sv | 8 +- .../axi_dma_perf_counters.sv | 5 +- .../{snitch => inst64}/axi_dma_pkg.sv | 7 +- .../axi_dma_tc_snitch_fe.sv | 8 +- .../{snitch => inst64}/sdma_synth_wrapper.sv | 6 +- .../idma_reg32_2d.hjson} | 6 +- .../idma_reg32_2d.sv} | 16 +- .../idma_reg64.hjson} | 6 +- .../idma_reg64.sv} | 19 +- .../idma_reg64_2d.hjson} | 6 +- .../idma_reg64_2d.sv} | 18 +- .../idma_reg32_2d_frontend.h | 75 - .../idma_reg32_2d_frontend.html | 180 -- .../idma_reg32_2d_frontend_reg_pkg.sv | 159 -- .../idma_reg32_2d_frontend_reg_top.sv | 638 ------- src/frontends/register_32bit_2d/reg_html.css | 74 - .../register_64bit/idma_reg64_frontend.h | 48 - .../register_64bit/idma_reg64_frontend.html | 136 -- .../idma_reg64_frontend_reg_pkg.sv | 116 -- .../idma_reg64_frontend_reg_top.sv | 410 ---- src/frontends/register_64bit/reg_html.css | 74 - .../idma_reg64_2d_frontend.h | 57 - .../idma_reg64_2d_frontend.html | 190 -- .../idma_reg64_2d_frontend_reg_pkg.sv | 140 -- .../idma_reg64_2d_frontend_reg_top.sv | 527 ------ src/frontends/register_64bit_2d/reg_html.css | 74 - .../src => future}/idma_improved_fifo.sv | 68 +- .../idma_legalizer_page_splitter.sv | 28 +- .../idma_legalizer_pow2_splitter.sv | 24 +- src/{package => }/idma_pkg.sv | 7 +- src/include/idma/guard.svh | 5 +- src/include/idma/typedef.svh | 5 +- src/legacy/axi_dma_backend.sv | 5 +- src/legacy/midends/idma_2D_midend.sv | 5 +- src/midends/idma_nd_midend.sv | 5 +- src/package/Bender.yml | 13 - src/systems/cva6_desc/dma_desc_wrap.sv | 3 +- src/systems/cva6_desc/dma_reg_to_axi.sv | 3 +- src/systems/cva6_reg/dma_core_wrap.sv | 12 +- src/systems/cva6_reg/driver/cva6_idma.h | 10 +- src/systems/cva6_reg/driver/encoding.h | 1675 +++++++++-------- src/systems/cva6_reg/driver/main.c | 62 +- src/systems/cva6_reg/driver/trap.c | 107 +- src/systems/cva6_reg/driver/uart.c | 60 +- src/systems/cva6_reg/driver/uart.h | 2 +- src/systems/pulpopen/dmac_wrap.sv | 17 +- src/systems/pulpopen/driver/archi/idma_v1.h | 7 +- src/systems/pulpopen/driver/hal/idma_v1.h | 377 ++-- src/systems/pulpopen/synth_dmac_wrap.sv | 10 + target/.gitignore | 2 + target/rtl/.gitignore | 2 + target/rtl/tpl/Bender.yml.tpl | 42 + scripts/start_vcs => target/sim/vcs/start | 3 + target/sim/vsim/.gitignore | 2 + .../sim/vsim/start.tcl | 3 +- target/sim/vsim/wave/tpl/backend.do.tpl | 177 ++ test/Bender.yml | 42 - test/frontends/tb_idma_desc64_top.sv | 3 +- test/idma_intf.sv | 5 +- test/idma_obi2axi_bridge.sv | 5 +- test/idma_obi_asserter.sv | 5 +- test/idma_tb_per2axi.sv | 68 +- test/idma_test.sv | 5 +- test/idma_tilelink2axi_bridge.sv | 5 +- test/include/tb_tasks.svh | 5 +- test/tb_idma_improved_fifo.sv | 5 +- test/{ => tpl}/tb_idma_backend.sv.tpl | 7 + util/.gitignore | 1 + util/gen_ci.py | 3 +- util/gen_idma.py | 77 + util/gen_jobs.py | 10 +- util/idma_gen.py | 585 ------ util/licence-checker.hjson | 27 - util/list-contributors.py | 3 + util/list-todos.py | 5 +- util/lowrisc_misc-linters/CONTRIBUTING.md | 48 - util/lowrisc_misc-linters/LICENSE | 202 -- util/lowrisc_misc-linters/README.md | 21 - .../licence-checker/README.md | 45 - .../licence-checker/licence-checker.py | 518 ----- util/lowrisc_misc-linters/requirements.txt | 8 - util/make_multiprotocol.py | 5 +- util/mario/backend.py | 51 + util/mario/bender.py | 36 + util/mario/database.py | 25 + util/mario/legalizer.py | 93 + util/mario/synth.py | 58 + util/mario/testbench.py | 95 + util/mario/transport_layer.py | 191 ++ util/mario/util.py | 115 ++ util/mario/wave.py | 47 + util/waiver.verible | 23 - verilator/scripts/preprocess.py | 21 - working_dir/axi | 1 - 180 files changed, 4698 insertions(+), 9172 deletions(-) create mode 100644 .github/verible.waiver create mode 100644 .github/workflows/analyze.yml create mode 100644 .github/workflows/build.yml delete mode 100644 .github/workflows/ci.yml create mode 100644 .github/workflows/docs.yml create mode 100644 .github/workflows/lint.yml create mode 100644 .github/yamllint-conf.yml delete mode 100644 .gitlab-ci.yml create mode 100644 Bender.local create mode 100644 doc/.gitignore delete mode 100644 doc/Makefile rename doc/{images => fig}/backend.png (100%) rename doc/{images => fig}/backend_buffer.png (100%) rename doc/{images => fig}/bslk_thumb.png (100%) rename doc/{images => fig}/iDMA_overview (100%) rename doc/{images => fig}/iDMA_overview.pdf (100%) rename doc/{images => fig}/iDMA_overview.svg (100%) rename doc/{images => fig}/verification.png (100%) rename doc/{source => src}/backend.rst (99%) rename doc/{source => src}/conf.py (97%) rename doc/{source => src}/error_handling.rst (100%) rename doc/{source => src}/frontend.rst (100%) rename doc/{source => src}/frontends/ariane_fe.rst (55%) rename doc/{source => src}/frontends/register_fe.rst (72%) rename doc/{source => src}/frontends/snitch_fe.rst (100%) rename doc/{source => src}/index.rst (71%) rename doc/{source => src}/midend.rst (100%) rename doc/{source => src}/system_integration.rst (100%) rename doc/{source => src}/verification.rst (93%) create mode 100644 idma.mk rename jobs.json => jobs/jobs.json (87%) delete mode 100644 logs/.gitkeep delete mode 100755 scripts/check-license delete mode 100755 scripts/python-lint delete mode 100755 scripts/verible-lint delete mode 100644 scripts/waves/vsim_backend.do.tpl create mode 100644 src/backend/.gitignore delete mode 100644 src/backend/Bender.yml.tpl rename src/backend/{src => }/idma_axi_read.sv (95%) rename src/backend/{src => }/idma_axi_write.sv (95%) rename src/backend/{src/idma_axi_lite_read.sv => idma_axil_read.sv} (91%) rename src/backend/{src/idma_axi_lite_write.sv => idma_axil_write.sv} (94%) rename src/backend/{src/idma_axi_stream_read.sv => idma_axis_read.sv} (92%) rename src/backend/{src/idma_axi_stream_write.sv => idma_axis_write.sv} (96%) rename src/backend/{src => }/idma_channel_coupler.sv (97%) rename src/backend/{src => }/idma_dataflow_element.sv (73%) rename src/backend/{src => }/idma_error_handler.sv (92%) rename src/backend/{src => }/idma_init_read.sv (92%) rename src/backend/{src => }/idma_obi_read.sv (93%) rename src/backend/{src => }/idma_obi_write.sv (97%) rename src/backend/{src => }/idma_tilelink_read.sv (96%) rename src/backend/{src => }/idma_tilelink_write.sv (94%) delete mode 100644 src/backend/src/idma_buffer.sv delete mode 100644 src/backend/src/idma_legalizer.sv.tpl delete mode 100644 src/backend/src/idma_stream_fifo.sv rename src/backend/{src => tpl}/idma_backend.sv.tpl (76%) rename src/backend/{src => tpl}/idma_backend_synth.sv.tpl (88%) create mode 100644 src/backend/tpl/idma_legalizer.sv.tpl rename src/backend/{src => tpl}/idma_transport_layer.sv.tpl (89%) rename src/{backend/database/idma_axi.yaml => db/idma_axi.yml} (81%) rename src/{backend/database/idma_axi_lite.yaml => db/idma_axi_lite.yml} (83%) rename src/{backend/database/idma_axi_stream.yaml => db/idma_axi_stream.yml} (92%) rename src/{backend/database/idma_init.yaml => db/idma_init.yml} (90%) rename src/{backend/database/idma_obi.yaml => db/idma_obi.yml} (88%) rename src/{backend/database/idma_tilelink.yaml => db/idma_tilelink.yml} (85%) rename src/frontends/desc64/{idma_desc64_frontend.hjson => idma_desc64.hjson} (91%) delete mode 100644 src/frontends/desc64/idma_desc64_frontend.h delete mode 100644 src/frontends/desc64/idma_desc64_frontend.html delete mode 100644 src/frontends/desc64/idma_desc64_reg_pkg.sv delete mode 100644 src/frontends/desc64/idma_desc64_reg_top.sv delete mode 100644 src/frontends/desc64/reg_html.css rename src/frontends/{snitch => inst64}/axi_dma_error_handler.sv (97%) rename src/frontends/{snitch => inst64}/axi_dma_perf_counters.sv (98%) rename src/frontends/{snitch => inst64}/axi_dma_pkg.sv (82%) rename src/frontends/{snitch => inst64}/axi_dma_tc_snitch_fe.sv (98%) rename src/frontends/{snitch => inst64}/sdma_synth_wrapper.sv (94%) rename src/frontends/{register_32bit_2d/idma_reg32_2d_frontend.hjson => reg32_2d/idma_reg32_2d.hjson} (97%) rename src/frontends/{register_32bit_2d/idma_reg32_2d_frontend.sv => reg32_2d/idma_reg32_2d.sv} (94%) rename src/frontends/{register_64bit/idma_reg64_frontend.hjson => reg64/idma_reg64.hjson} (96%) rename src/frontends/{register_64bit/idma_reg64_frontend.sv => reg64/idma_reg64.sv} (93%) rename src/frontends/{register_64bit_2d/idma_reg64_2d_frontend.hjson => reg64_2d/idma_reg64_2d.hjson} (97%) rename src/frontends/{register_64bit_2d/idma_reg64_2d_frontend.sv => reg64_2d/idma_reg64_2d.sv} (93%) delete mode 100644 src/frontends/register_32bit_2d/idma_reg32_2d_frontend.h delete mode 100644 src/frontends/register_32bit_2d/idma_reg32_2d_frontend.html delete mode 100644 src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_pkg.sv delete mode 100644 src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_top.sv delete mode 100644 src/frontends/register_32bit_2d/reg_html.css delete mode 100644 src/frontends/register_64bit/idma_reg64_frontend.h delete mode 100644 src/frontends/register_64bit/idma_reg64_frontend.html delete mode 100644 src/frontends/register_64bit/idma_reg64_frontend_reg_pkg.sv delete mode 100644 src/frontends/register_64bit/idma_reg64_frontend_reg_top.sv delete mode 100644 src/frontends/register_64bit/reg_html.css delete mode 100644 src/frontends/register_64bit_2d/idma_reg64_2d_frontend.h delete mode 100644 src/frontends/register_64bit_2d/idma_reg64_2d_frontend.html delete mode 100644 src/frontends/register_64bit_2d/idma_reg64_2d_frontend_reg_pkg.sv delete mode 100644 src/frontends/register_64bit_2d/idma_reg64_2d_frontend_reg_top.sv delete mode 100644 src/frontends/register_64bit_2d/reg_html.css rename src/{backend/src => future}/idma_improved_fifo.sv (74%) rename src/{backend/src => future}/idma_legalizer_page_splitter.sv (76%) rename src/{backend/src => future}/idma_legalizer_pow2_splitter.sv (83%) rename src/{package => }/idma_pkg.sv (97%) delete mode 100644 src/package/Bender.yml create mode 100644 target/.gitignore create mode 100644 target/rtl/.gitignore create mode 100644 target/rtl/tpl/Bender.yml.tpl rename scripts/start_vcs => target/sim/vcs/start (83%) create mode 100644 target/sim/vsim/.gitignore rename scripts/start_vsim.tcl => target/sim/vsim/start.tcl (81%) create mode 100644 target/sim/vsim/wave/tpl/backend.do.tpl delete mode 100644 test/Bender.yml rename test/{ => tpl}/tb_idma_backend.sv.tpl (99%) create mode 100644 util/.gitignore create mode 100644 util/gen_idma.py delete mode 100644 util/idma_gen.py delete mode 100644 util/licence-checker.hjson delete mode 100644 util/lowrisc_misc-linters/CONTRIBUTING.md delete mode 100644 util/lowrisc_misc-linters/LICENSE delete mode 100644 util/lowrisc_misc-linters/README.md delete mode 100644 util/lowrisc_misc-linters/licence-checker/README.md delete mode 100755 util/lowrisc_misc-linters/licence-checker/licence-checker.py delete mode 100644 util/lowrisc_misc-linters/requirements.txt create mode 100644 util/mario/backend.py create mode 100644 util/mario/bender.py create mode 100644 util/mario/database.py create mode 100644 util/mario/legalizer.py create mode 100644 util/mario/synth.py create mode 100644 util/mario/testbench.py create mode 100644 util/mario/transport_layer.py create mode 100644 util/mario/util.py create mode 100644 util/mario/wave.py delete mode 100644 util/waiver.verible delete mode 100644 verilator/scripts/preprocess.py delete mode 160000 working_dir/axi diff --git a/.ci/gitlab-ci.yml.tpl b/.ci/gitlab-ci.yml.tpl index d676d495..73349b89 100644 --- a/.ci/gitlab-ci.yml.tpl +++ b/.ci/gitlab-ci.yml.tpl @@ -2,7 +2,8 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# Author: Thomas Benz +# Authors: +# - Thomas Benz variables: SPHINXBUILD: "/home/tbenz/.local/bin/sphinx-build" @@ -22,7 +23,7 @@ prepare-non-free: script: - git clone git@iis-git.ee.ethz.ch:bslk/idma/idma-non-free.git - cd idma-non-free - - git checkout tsenti + - git checkout deploy-mdma - make -B gen_sub_ci artifacts: paths: diff --git a/.github/verible.waiver b/.github/verible.waiver new file mode 100644 index 00000000..5b8f931c --- /dev/null +++ b/.github/verible.waiver @@ -0,0 +1,13 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Authors: +# - Thomas Benz + +# Fix this ... +waive --rule=line-length --location="src/frontends/desc64/idma_desc64_top.sv" + +# Declare zero-based big-endian unpacked dimensions sized as [N] -> legacy PULP code :S +waive --rule=unpacked-dimensions-range-ordering --location="src/systems/pulpopen/dmac_wrap.sv" +waive --rule=line-length --location="src/systems/pulpopen/dmac_wrap.sv" diff --git a/.github/workflows/analyze.yml b/.github/workflows/analyze.yml new file mode 100644 index 00000000..e3c512c5 --- /dev/null +++ b/.github/workflows/analyze.yml @@ -0,0 +1,66 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Authors: +# - Paul Scheffler +# - Thomas Benz + +name: analyze + +on: [ push, pull_request, workflow_dispatch ] + +jobs: + + analyze-contributors: + runs-on: ubuntu-latest + steps: + - + name: Checkout + uses: actions/checkout@v3 + - + name: Install Python + uses: actions/setup-python@v4 + with: + python-version: '3.9' + cache: 'pip' + - + name: Python Requirements + run: pip install -r requirements.txt + - + name: List contributors + run: scripts/list-contributors | tee contributions.txt + - + name: Upload contributions.txt + uses: actions/upload-artifact@v2 + with: + name: contributions + path: contributions.txt + retention-days: 7 + + analyze-todos: + runs-on: ubuntu-latest + continue-on-error: true + steps: + - + name: Checkout + uses: actions/checkout@v3 + - + name: Install Python + uses: actions/setup-python@v4 + with: + python-version: '3.9' + cache: 'pip' + - + name: Python Requirements + run: pip install -r requirements.txt + - + name: List todos + run: scripts/list-todos | tee open_todos.txt + - + name: Upload todos.txt + uses: actions/upload-artifact@v2 + with: + name: open_todos + path: open_todos.txt + retention-days: 7 diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml new file mode 100644 index 00000000..b800dd79 --- /dev/null +++ b/.github/workflows/build.yml @@ -0,0 +1,68 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Authors: +# - Paul Scheffler +# - Thomas Benz + +name: build + +on: [ push, pull_request, workflow_dispatch ] + +jobs: + + build: + strategy: + matrix: + target: [rtl, doc] + fail-fast: false + runs-on: ubuntu-22.04 + steps: + - + name: Checkout + uses: actions/checkout@v3 + - + name: Install Python + uses: actions/setup-python@v2 + with: + python-version: 3.9 + cache: pip + - + name: Install Python requirements + run: pip install -r requirements.txt + - + name: Setup Graphviz + uses: ts-graphviz/setup-graphviz@v1 + - + name: Install RISC-V GCC toolchain + uses: pulp-platform/pulp-actions/riscv-gcc-install@v2 + with: + distro: ubuntu-22.04 + nightly-date: '2023.03.14' + target: riscv64-elf + - + name: Install Bender + uses: pulp-platform/pulp-actions/bender-install@v2 + with: + version: 0.27.3 + - + name: Install Morty + run: | + curl --proto '=https' --tlsv1.2 -sLO https://github.com/pulp-platform/morty/releases/download/v0.9.0/morty-ubuntu.22.04-x86_64.tar.gz + tar -xvf morty-ubuntu.22.04-x86_64.tar.gz morty + rm -f morty-ubuntu.22.04-x86_64.tar.gz + chmod 777 morty + echo "PATH=.:$PATH" >> ${GITHUB_ENV} + - + name: Check clean + run: make idma_clean_all + - + name: Check whether clean + run: git status && test -z "$(git status --porcelain --ignore-submodules)" + - + name: Build target + run: make -j9 idma_${{ matrix.target }}_all + - + name: Check whether stale + run: git status && test -z "$(git status --porcelain --ignore-submodules)" diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml deleted file mode 100644 index f61c3bfe..00000000 --- a/.github/workflows/ci.yml +++ /dev/null @@ -1,207 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 - -# Author: Michael Rogenmoser - -name: ci - -on: - push: - branches: [ master ] - pull_request: - branches: [ master ] - workflow_dispatch: - -env: - BENDER: ./bender - -jobs: - check-clean: - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v3 - - uses: actions/setup-python@v4 - with: - python-version: '3.9' - cache: 'pip' - - name: Install Bender - run: make bender - - name: Python Requirements - run: pip install -r requirements.txt - - name: Check clean make targets - run: | - make -B prepare_sim gen_ci gen_regs - make clean - git status && test -z "$(git status --porcelain)" - check-stale: - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v3 - - uses: actions/setup-python@v4 - with: - python-version: '3.9' - cache: 'pip' - - name: Install Bender - run: make bender - - name: Python Requirements - run: pip install -r requirements.txt - - name: Check clean makefile - run: | - make -B prepare_sim gen_ci gen_regs - git status && test -z "$(git status --porcelain)" - lint: - runs-on: ubuntu-latest - needs: [check-clean, check-stale] - strategy: - fail-fast: false - matrix: - lint_check: [license, python] - steps: - - uses: actions/checkout@v3 - - uses: actions/setup-python@v4 - with: - python-version: '3.9' - cache: 'pip' - - name: Python Requirements - run: python3 -m pip install -r requirements.txt - - name: Install Bender - run: make bender - - name: Lint license - if: ${{ matrix.lint_check == 'license' }} - run: scripts/check-license - - name: Lint python - if: ${{ matrix.lint_check == 'python' }} - run: scripts/python-lint - lint-commit: - runs-on: ubuntu-latest - needs: [check-clean, check-stale] - steps: - - uses: actions/checkout@v3 - if: ${{ github.event_name == 'push' }} - - uses: actions/checkout@v3 - if: ${{ github.event_name == 'pull_request' }} - with: - ref: ${{ github.event.pull_request.head.sha }} - - uses: actions/setup-python@v4 - with: - python-version: '3.9' - cache: 'pip' - - name: Python Requirements - run: python3 -m pip install -r requirements.txt - - name: Lint commits - run: python3 util/lint-commits.py HEAD - - lint-verilog: - runs-on: ubuntu-latest - needs: [check-clean, check-stale] - steps: - - uses: actions/checkout@v3 - - uses: chipsalliance/verible-linter-action@main - with: - paths: | - ./src - exclude_paths: | - ./src/test - ./src/systems/idma_axi_to_mem.sv - extra_args: "--rules=-interface-name-style --lint_fatal --parse_fatal --waiver_files util/waiver.verible" - github_token: ${{ secrets.GITHUB_TOKEN }} - reviewdog_reporter: github-check - - analyze-contributors: - runs-on: ubuntu-latest - needs: lint - steps: - - uses: actions/checkout@v3 - - uses: actions/setup-python@v4 - with: - python-version: '3.9' - cache: 'pip' - - name: Python Requirements - run: pip install -r requirements.txt - - name: List contributors - run: scripts/list-contributors | tee contributions.txt - - name: Upload contributions.txt - uses: actions/upload-artifact@v2 - with: - name: contributions - path: contributions.txt - retention-days: 7 - analyze-todos: - runs-on: ubuntu-latest - needs: lint - continue-on-error: true - steps: - - uses: actions/checkout@v3 - - uses: actions/setup-python@v4 - with: - python-version: '3.9' - cache: 'pip' - - name: Python Requirements - run: pip install -r requirements.txt - - name: List todos - run: scripts/list-todos | tee open_todos.txt - - name: Upload todos.txt - uses: actions/upload-artifact@v2 - with: - name: open_todos - path: open_todos.txt - retention-days: 7 - - docs: - runs-on: ubuntu-22.04 - needs: [lint, lint-verilog] - env: - MORTY: ./morty - steps: - - uses: actions/checkout@v3 - - name: Install Bender - run: make bender - - uses: actions/setup-python@v4 - with: - python-version: '3.9' - cache: 'pip' - - name: Python Requirements - run: python3 -m pip install -r requirements.txt - - name: Install Morty - run: | - curl --proto '=https' --tlsv1.2 -sLO https://github.com/pulp-platform/morty/releases/download/v0.7.0/morty-ubuntu.22.04-x86_64.tar.gz - tar -xvf morty-ubuntu.22.04-x86_64.tar.gz morty - rm -f morty-ubuntu.22.04-x86_64.tar.gz - cp morty doc - - name: Build Doc - run: make doc - - name: Pickle - run: make -B pickle - - name: Upload doc - uses: actions/upload-artifact@v2 - with: - name: doc - path: doc/build - retention-days: 7 - - name: Upload pickle - uses: actions/upload-artifact@v2 - with: - name: pickle - path: pickle - retention-days: 7 - - name: Create publish docs - if: ${{ github.event_name == 'push' }} - uses: actions/upload-pages-artifact@main - with: - path: doc/build/html - - deploy-pages: - needs: docs - permissions: - pages: write - id-token: write - environment: - name: github-pages - url: ${{ steps.deployment.output.page_url }} - runs-on: ubuntu-latest - if: ${{ github.event_name == 'push' }} - steps: - - name: Deploy to Github Pages - id: deployment - uses: actions/deploy-pages@v1 diff --git a/.github/workflows/docs.yml b/.github/workflows/docs.yml new file mode 100644 index 00000000..097eddd1 --- /dev/null +++ b/.github/workflows/docs.yml @@ -0,0 +1,80 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Author: Paul Scheffler + +name: docs + +on: + push: + branches: [ master ] + pull_request: + branches: [ master ] + workflow_dispatch: + +jobs: + + doc: + runs-on: ubuntu-22.04 + steps: + - + name: Checkout + uses: actions/checkout@v3 + - + name: Install Python + uses: actions/setup-python@v2 + with: + python-version: 3.9 + cache: pip + - + name: Install Python requirements + run: pip install -r requirements.txt + - + name: Setup Graphviz + uses: ts-graphviz/setup-graphviz@v1 + - + name: Install RISC-V GCC toolchain + uses: pulp-platform/pulp-actions/riscv-gcc-install@v2 + with: + distro: ubuntu-22.04 + nightly-date: '2023.03.14' + target: riscv64-elf + - + name: Install Bender + uses: pulp-platform/pulp-actions/bender-install@v2 + with: + version: 0.27.3 + - + name: Install Morty + run: | + curl --proto '=https' --tlsv1.2 -sLO https://github.com/pulp-platform/morty/releases/download/v0.9.0/morty-ubuntu.22.04-x86_64.tar.gz + tar -xvf morty-ubuntu.22.04-x86_64.tar.gz morty + rm -f morty-ubuntu.22.04-x86_64.tar.gz + chmod 777 morty + echo "PATH=.:$PATH" >> ${GITHUB_ENV} + - + name: Build Doc + run: make idma_doc_all + - + name: Create publish docs + if: ${{ github.event_name == 'push' }} + uses: actions/upload-pages-artifact@main + with: + path: target/doc/html + + deploy-pages: + needs: doc + permissions: + pages: write + id-token: write + environment: + name: github-pages + url: ${{ steps.deployment.output.page_url }} + runs-on: ubuntu-latest + if: ${{ github.event_name == 'push' }} + steps: + - + name: Deploy to Github Pages + id: deployment + uses: actions/deploy-pages@v1 diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml new file mode 100644 index 00000000..ad09dde1 --- /dev/null +++ b/.github/workflows/lint.yml @@ -0,0 +1,127 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Authors: +# - Paul Scheffler +# - Thomas Benz + +name: lint + +on: [ push, pull_request, workflow_dispatch ] + +jobs: + + lint-license: + runs-on: ubuntu-latest + steps: + - + name: Checkout + uses: actions/checkout@v3 + - + name: Check license + uses: pulp-platform/pulp-actions/lint-license@v2 + with: + license: | + Copyright (\d{4}(-\d{4})?\s)?(ETH Zurich and University of Bologna|lowRISC contributors). + (Solderpad Hardware License, Version 0.51|Licensed under the Apache License, Version 2.0), see LICENSE for details. + SPDX-License-Identifier: (SHL-0.51|Apache-2.0) + + lint-sv: + runs-on: ubuntu-latest + steps: + - + name: Checkout + uses: actions/checkout@v3 + - + name: Run Verible + uses: chipsalliance/verible-linter-action@main + with: + paths: src + extra_args: "--waiver_files .github/verible.waiver" + github_token: ${{ secrets.GITHUB_TOKEN }} + fail_on_error: true + reviewdog_reporter: github-check + + lint-cxx: + runs-on: ubuntu-latest + steps: + - + name: Checkout + uses: actions/checkout@v3 + - + name: Run Clang-format + uses: DoozyX/clang-format-lint-action@v0.14 + with: + extensions: 'c,h,cpp' + clangFormatVersion: 14 + style: > + { + IndentWidth: 4, + ColumnLimit: 100, + AlignEscapedNewlines: DontAlign, + SortIncludes: false, + AllowShortFunctionsOnASingleLine: None, + AllowShortIfStatementsOnASingleLine: true, + AllowShortLoopsOnASingleLine: true + } + exclude_paths: src/systems/cva6_reg/driver/*.h target/sim/vsim/wave/tpl/*.tpl + + lint-python: + runs-on: ubuntu-latest + steps: + - + name: Checkout + uses: actions/checkout@v3 + - + name: Install Python + uses: actions/setup-python@v2 + with: + python-version: 3.9 + - + name: Lint Python + uses: py-actions/flake8@v2 + with: + max-line-length: "100" + ignore: E128 + + lint-yaml: + runs-on: ubuntu-latest + steps: + - + name: Checkout + uses: actions/checkout@v3 + - + name: Install Python + uses: actions/setup-python@v2 + with: + python-version: 3.9 + - + name: Lint Yaml + uses: ibiqlik/action-yamllint@v3 + with: + file_or_dir: Bender.yml src/db/*.yml + config_file: .github/yamllint-conf.yml + + lint-commit: + runs-on: ubuntu-latest + steps: + - + uses: actions/checkout@v3 + if: ${{ github.event_name == 'push' }} + - + uses: actions/checkout@v3 + if: ${{ github.event_name == 'pull_request' }} + with: + ref: ${{ github.event.pull_request.head.sha }} + - + uses: actions/setup-python@v2 + with: + python-version: '3.9' + cache: 'pip' + - + name: Python Requirements + run: python3 -m pip install -r requirements.txt + - + name: Lint commits + run: python3 util/lint-commits.py HEAD diff --git a/.github/yamllint-conf.yml b/.github/yamllint-conf.yml new file mode 100644 index 00000000..332f191d --- /dev/null +++ b/.github/yamllint-conf.yml @@ -0,0 +1,26 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Authors: +# - Thomas Benz + +extends: default + +rules: + # 100 chars should be enough, but don't fail if a line is longer + line-length: + max: 100 + level: warning + trailing-spaces: + level: warning + colons: + level: warning + braces: + level: warning + brackets: + level: warning + commas: + level: warning + indentation: + level: warning diff --git a/.gitignore b/.gitignore index 7aa293a3..5e2a4903 100644 --- a/.gitignore +++ b/.gitignore @@ -1,27 +1,6 @@ .bender doc/build -logs/* -!logs/.gitkeep scripts/__pycache__ -scripts/compile_vsim.tcl -scripts/compile_vcs.sh -verilator/files*.txt -work -*.wlf -modelsim.ini -transcript -*.vstf -vc_hdrs.h -ucli.key -work-vcs -bin -*.elf -AN.DB -*.log -obj_* -sources.txt -pickle -*.frag contributions.txt open_todos.txt gmon.out @@ -29,7 +8,5 @@ gmon.out *non-free* bender morty -src/backend/Bender.yml -src/backend/backend_* -test/tb_idma_backend_*.sv -scripts/waves/vsim_backend_*.do \ No newline at end of file +!target/* +working_dir diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml deleted file mode 100644 index a1f94930..00000000 --- a/.gitlab-ci.yml +++ /dev/null @@ -1,193 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 - -# Author: Thomas Benz - -variables: - SPHINXBUILD: "/home/tbenz/.local/bin/sphinx-build" - MORTY: "/home/tbenz/.cargo/bin/morty" - -before_script: - - source ~paulsc/.bashrc - -stages: - - prepare-non-free - - iDMA - -############# Below: only works on IIS machines #################### - -prepare-non-free: - stage: prepare-non-free - script: - - git clone git@iis-git.ee.ethz.ch:bslk/idma/idma-non-free.git - - cd idma-non-free - - git checkout tsenti - - make -B gen_sub_ci - artifacts: - paths: - - idma-non-free/ci/*.yml - - -# Below: Automatically generated by util/gen_ci.py - -axi_backend_combined_shifter-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-axi_backend_combined_shifter-ci.yml - job: prepare-non-free - strategy: depend - -axi_backend-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-axi_backend-ci.yml - job: prepare-non-free - strategy: depend - -obi_backend-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-obi_backend-ci.yml - job: prepare-non-free - strategy: depend - -axi_to_obi_backend-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-axi_to_obi_backend-ci.yml - job: prepare-non-free - strategy: depend - -obi_to_axi_backend-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-obi_to_axi_backend-ci.yml - job: prepare-non-free - strategy: depend - -axi_obi_backend-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-axi_obi_backend-ci.yml - job: prepare-non-free - strategy: depend - -axi_lite_backend-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-axi_lite_backend-ci.yml - job: prepare-non-free - strategy: depend - -axi_axi_lite_axi_stream_obi_init_backend-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-axi_axi_lite_axi_stream_obi_init_backend-ci.yml - job: prepare-non-free - strategy: depend - -tilelink_backend-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-tilelink_backend-ci.yml - job: prepare-non-free - strategy: depend - -axi_to_tilelink_backend-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-axi_to_tilelink_backend-ci.yml - job: prepare-non-free - strategy: depend - -tilelink_to_axi_backend-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-tilelink_to_axi_backend-ci.yml - job: prepare-non-free - strategy: depend - -axi_init_to_axi_backend-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-axi_init_to_axi_backend-ci.yml - job: prepare-non-free - strategy: depend - -axi_stream_backend-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-axi_stream_backend-ci.yml - job: prepare-non-free - strategy: depend - -axi_to_axi_stream_backend-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-axi_to_axi_stream_backend-ci.yml - job: prepare-non-free - strategy: depend - -axi_stream_to_axi_backend-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-axi_stream_to_axi_backend-ci.yml - job: prepare-non-free - strategy: depend - -axi_axi_stream_backend-run: - stage: iDMA - needs: - - prepare-non-free - trigger: - include: - - artifact: idma-non-free/ci/gitlab-axi_axi_stream_backend-ci.yml - job: prepare-non-free - strategy: depend - diff --git a/Bender.local b/Bender.local new file mode 100644 index 00000000..7ec9112d --- /dev/null +++ b/Bender.local @@ -0,0 +1,2 @@ +overrides: + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0 } \ No newline at end of file diff --git a/Bender.lock b/Bender.lock index 2c684666..7b5e1062 100644 --- a/Bender.lock +++ b/Bender.lock @@ -1,7 +1,14 @@ packages: + apb: + revision: 77ddf073f194d44b9119949d2421be59789e69ae + version: 0.2.4 + source: + Git: https://github.com/pulp-platform/apb.git + dependencies: + - common_cells axi: - revision: 96f749dc4ae62ed6b90e44aabb5d9460f1b0d858 - version: 0.39.0-beta.3 + revision: fccffb5953ec8564218ba05e20adbedec845e014 + version: 0.39.1 source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -9,8 +16,8 @@ packages: - common_verification - tech_cells_generic common_cells: - revision: 9c1a1bdbd1a0928340863cad90c6fc0503da43a7 - version: 1.27.1 + revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f + version: 1.32.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -22,44 +29,28 @@ packages: source: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] - idma_backend: + idma_gen: revision: null version: null source: - Path: /home/bsc22h2/bachelor-thesis/mdma/src/backend + Path: target/rtl dependencies: - axi - common_cells - - idma_pkg - - tb_idma_backend - idma_pkg: - revision: null - version: null - source: - Path: /home/bsc22h2/bachelor-thesis/mdma/src/package - dependencies: - - axi + - register_interface register_interface: - revision: 4632515363fcb1a8ab7735c996753631abf5c7ef - version: null + revision: d7693be4aef1fc7e7eb2b00b41c42e87d959866c + version: 0.4.2 source: - Git: https://github.com/TheMightyDuckOfDoom/register_interface.git + Git: https://github.com/pulp-platform/register_interface.git dependencies: + - apb - axi - common_cells - tb_idma_backend: - revision: null - version: null - source: - Path: /home/bsc22h2/bachelor-thesis/mdma/src/backend/../../test - dependencies: - - axi - - common_cells - - idma_pkg - - register_interface + - common_verification tech_cells_generic: - revision: aef525b2dc7670525fc293dfc55f167e371b8c35 - version: 0.2.10 + revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf + version: 0.2.13 source: Git: https://github.com/pulp-platform/tech_cells_generic.git dependencies: diff --git a/Bender.yml b/Bender.yml index ea48a5c7..c0dac528 100644 --- a/Bender.yml +++ b/Bender.yml @@ -10,13 +10,11 @@ package: - "Tobias Senti " dependencies: - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.27.1 } - common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.2 } - axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0-beta.3 } - register_interface: { git: "https://github.com/TheMightyDuckOfDoom/register_interface.git", rev: master } - - idma_backend: { path: "src/backend" } - idma_pkg: { path: "src/package" } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 } + common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 } + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 } + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.2 } + idma_gen: { path: "target/rtl" } export_include_dirs: - src/include @@ -26,7 +24,26 @@ sources: # package. Files in level 1 only depend on files in level 0, files in level 2 on files in # levels 1 and 0, etc. Files within a level are ordered alphabetically. # Level 0 + - src/idma_pkg.sv + - src/backend/idma_axil_read.sv + - src/backend/idma_axil_write.sv + - src/backend/idma_axi_read.sv + - src/backend/idma_axis_read.sv + - src/backend/idma_axis_write.sv + - src/backend/idma_axi_write.sv + - src/backend/idma_channel_coupler.sv + - src/backend/idma_dataflow_element.sv + - src/backend/idma_error_handler.sv + - src/backend/idma_init_read.sv + - src/backend/idma_obi_read.sv + - src/backend/idma_obi_write.sv + - src/backend/idma_tilelink_read.sv + - src/backend/idma_tilelink_write.sv - src/frontends/idma_transfer_id_gen.sv + - src/future/idma_improved_fifo.sv + - src/future/idma_legalizer_page_splitter.sv + - src/future/idma_legalizer_pow2_splitter.sv + - src/future/idma_stream_fifo.sv # Midends # Level 0 @@ -34,51 +51,28 @@ sources: - src/midends/idma_nd_midend.sv # Frontends - - files: # 32bit register frontend - # Level 0 - - src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_pkg.sv - # Level 1 - - src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_top.sv - # Level 2 - - src/frontends/register_32bit_2d/idma_reg32_2d_frontend.sv - - - files: # 64bit register frontend - # Level 0 - - src/frontends/register_64bit/idma_reg64_frontend_reg_pkg.sv - # Level 1 - - src/frontends/register_64bit/idma_reg64_frontend_reg_top.sv - # Level 2 - - src/frontends/register_64bit/idma_reg64_frontend.sv - - - files: # 2D 64bit register frontend - # Level 0 - - src/frontends/register_64bit_2d/idma_reg64_2d_frontend_reg_pkg.sv - # Level 1 - - src/frontends/register_64bit_2d/idma_reg64_2d_frontend_reg_top.sv - # Level 2 - - src/frontends/register_64bit_2d/idma_reg64_2d_frontend.sv + # Level 0 + - src/frontends/reg32_2d/idma_reg32_2d.sv + - src/frontends/reg64/idma_reg64.sv + - src/frontends/reg64_2d/idma_reg64_2d.sv - - files: # 64bit descriptor frontend - # Level 0 - - src/frontends/desc64/idma_desc64_reg_pkg.sv - # Level 1 - - src/frontends/desc64/idma_desc64_reg_top.sv - - src/frontends/desc64/idma_desc64_shared_counter.sv - # Level 2 - - src/frontends/desc64/idma_desc64_reg_wrapper.sv - # Level 3 - - src/frontends/desc64/idma_desc64_top.sv + # Level 0 + - src/frontends/desc64/idma_desc64_shared_counter.sv + # Level 2 + - src/frontends/desc64/idma_desc64_reg_wrapper.sv + # Level 3 + - src/frontends/desc64/idma_desc64_top.sv - # Systems - - target: all(pulp, not(mchan)) - files: - - src/systems/pulpopen/dmac_wrap.sv - - src/systems/pulpopen/synth_dmac_wrap.sv + # # Systems + # - target: all(pulp, not(mchan)) + # files: + # - src/systems/pulpopen/dmac_wrap.sv + # - src/systems/pulpopen/synth_dmac_wrap.sv - - target: cva6 - files: - - src/systems/cva6_reg/dma_core_wrap.sv - - - target: test - files: - - test/tb_idma_improved_fifo.sv + # - target: cva6 + # files: + # - src/systems/cva6_reg/dma_core_wrap.sv + # + # - target: test + # files: + # - test/tb_idma_improved_fifo.sv diff --git a/Makefile b/Makefile index 1b42d062..e0b51c60 100644 --- a/Makefile +++ b/Makefile @@ -2,388 +2,9 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# Author: Thomas Benz +# Authors: +# - Thomas Benz -GIT ?= git -BENDER ?= bender -PYTHON ?= python3 +IDMA_ROOT ?= . -RTL_CFGS ?= \ - gen_rtl_axi.obi.split \ - gen_rtl_obi.axi.split \ - gen_rtl_axi.axi.split \ - gen_rtl_axi-obi.axi-obi.split \ - gen_rtl_axi.axi.combined - -# Extracting word nr. $(1) from $(2)-separated list $(3) -pw = $(word $(1), $(subst $(2), ,$(3))) - -.PHONY: all help prepare_sim - -# phony targets -all: help - -prepare_sim: scripts/compile_vsim.tcl scripts/compile_vcs.sh - -clean: sim_clean vcs_clean ver_clean pickle_clean doc_clean misc_clean jobs_clean - -# Ensure half-built targets are purged -.DELETE_ON_ERROR: - - -# -------------- -# help -# -------------- - -help: - @echo "" - @echo "iDMA Makefile" - @echo "-------------" - @echo "" - @echo "prepare_sim: uses bender to generate the analyze scripts needed for simulating the iDMA" - @echo "bin/iDMA.vcs VCS_TP=**YOUR_TB**: creates the VCS executable" - @echo "obj_iDMA VLT_TOP=**YOUR_TOP_LVL**: elaborates the hardware using verilator" - @echo "pickle: uses morty to generate a pickled version of the hardware" - @echo "doc: generates the documentation in doc/build" - @echo "gen_ci: regenerates the gitlab CI (only ETH internal used)" - @echo "gen_regs: regenerates the registers using reggen" - @echo "" - @echo "clean: cleans generated files" - @echo "nuke: cleans all generated file, also almost all files checked in" - @echo "" - - -# -------------- -# QuestaSim -# -------------- - -.PHONY: sim_clean - -VLOG_ARGS += -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale \"1 ns / 1 ps\" -XVLOG_ARGS += -64bit -compile -vtimescale 1ns/1ns -quiet - -define generate_vsim - echo 'set ROOT [file normalize [file dirname [info script]]/$3]' > $1 - $(BENDER) script vsim --vlog-arg="$(VLOG_ARGS)" $2 | grep -v "set ROOT" >> $1 - echo >> $1 -endef - -scripts/compile_vsim.tcl: Bender.yml src/backend/Bender.yml - $(BENDER) update - $(call generate_vsim, $@, -t rtl -t test,..) - -sim_clean: - rm -rf scripts/compile_vsim.tcl - rm -rf work - rm -f dma_trace_* - rm -f dma_transfers.txt - rm -f transcript - rm -f wlf* - rm -f logs/wlf* - rm -f logs/*.wlf - rm -f *.vstf - rm -f *.vcd - rm -f modelsim.ini - rm -f logs/*vsim.log - - -# -------------- -# VCS -# -------------- - -.PHONY: vcs_compile vcs_clean - -VLOGAN_ARGS := -assert svaext -VLOGAN_ARGS += -assert disable_cover -VLOGAN_ARGS += -full64 -VLOGAN_ARGS += -sysc=q -VLOGAN_ARGS += -nc -VLOGAN_ARGS += -q -VLOGAN_ARGS += -timescale=1ns/1ns - -VCS_ARGS := -full64 -VCS_ARGS += -Mlib=work-vcs -VCS_ARGS += -Mdir=work-vcs -VCS_ARGS += -debug_access+r -VCS_ARGS += -j 8 -VCS_ARGS += -CFLAGS "-Os" - -VCS_PARAMS ?= -VCS_TB ?= - -VLOGAN_BIN ?= vlogan -VCS_BIN ?= vcs - -VLOGAN_REL_PATHS ?= | grep -v "ROOT=" | sed '3 i ROOT="."' - -scripts/compile_vcs.sh: Bender.yml Bender.lock src/backend/Bender.yml - $(BENDER) update - $(BENDER) script vcs -t test -t rtl -t simulation --vlog-arg "\$(VLOGAN_ARGS)" --vlogan-bin "$(VLOGAN_BIN)" $(VLOGAN_REL_PATHS) > $@ - chmod +x $@ - -vcs_compile: scripts/compile_vcs.sh - scripts/compile_vcs.sh - -bin/%.vcs: scripts/compile_vcs.sh vcs_compile - mkdir -p bin - $(VCS_BIN) $(VCS_ARGS) $(VCS_PARAMS) $(VCS_TB) -o $@ - -vcs_clean: - rm -rf AN.DB - rm -f scripts/compile_vcs.sh - rm -rf bin - rm -rf work-vcs - rm -f ucli.key - rm -f vc_hdrs.h - rm -f logs/*.vcs.log - - -## -------------- -## Verilator -## -------------- - -.PHONY: ver_clean - -VERILATOR ?= verilator - -VLT_ARGS := -VLT_ARGS += --cc -VLT_ARGS += --Wall -VLT_ARGS += --Wno-fatal -VLT_ARGS += +1800-2017ext+ -VLT_ARGS += --assert -VLT_ARGS += --hierarchical -VLT_ARGS += --no-skip-identical - -VLT_TOP ?= - -verilator/files_raw.txt: Bender.yml Bender.lock src/backend/Bender.yml - $(BENDER) update - $(BENDER) script verilator -t synthesis > $@ - -verilator/files.txt: verilator/scripts/preprocess.py verilator/files_raw.txt - $(PYTHON) $^ > $@ - -obj_%: verilator/files.txt - $(VERILATOR) $(VLT_ARGS) -Mdir obj_$* -f $^ --top-module $(VLT_TOP) 2> logs/verilator_$*_elab.log - -ver_clean: - rm -rf obj_* - rm -f logs/verilator*.log - rm -f verilator/files*.txt - - -# --------------- -# Morty (Pickle) -# --------------- - -.PHONY: pickle pickle_clean - -MORTY ?= morty -PATH_ESCAPED = $(shell pwd | sed 's_/_\\/_g') -RELATIVE_PATH_REGEX = 's/$(PATH_ESCAPED)/./' - -pickle: pickle/idma_pickle.sv pickle/idma_pickle_stripped.sv - -sources.txt: Bender.yml Bender.lock - $(BENDER) update - $(BENDER) script flist -t rtl -t synthesis -t pulp -t cva6 | sed -e $(RELATIVE_PATH_REGEX) > sources.txt - -pickle/idma_pickle.sv: sources.txt gen_regs - mkdir -p pickle - $(MORTY) -s _pickle $$(cat sources.txt | sed -e "s/+incdir+/-I /") -o $@ - -pickle/idma_pickle_stripped.sv: sources.txt gen_regs - mkdir -p pickle - $(MORTY) --strip-comments -s _pickle_stripped $$(cat sources.txt | sed -e "s/+incdir+/-I /") -o $@ - -pickle_clean: - rm -rf pickle - - -# -------------- -# Doc -# -------------- - -.PHONY: doc doc_clean - -SPHINXBUILD ?= sphinx-build - -doc: sources.txt gen_regs - $(MAKE) -C doc morty-docs regs html SPHINXBUILD=$(SPHINXBUILD) - -doc_clean: - $(MAKE) -C doc clean - rm -rf doc/build - rm -f doc/gmon.out - - -# -------------- -# Misc Clean -# -------------- - -.PHONY: misc_clean nuke - -misc_clean: - rm -f src/backend/Bender.yml - rm -rf src/backend/backend_* - rm -rf scripts/__pycache__ - rm -rf scripts/synth.*.params.tcl - rm -f scripts/waves/vsim_backend_*.do - rm -f sources.txt - rm -f contributions.txt - rm -f open_todos.txt - rm -f gmon.out - -nuke: clean regs_clean ci_clean - rm -rf .bender - - -## -------------- -## Job File -## -------------- - -.PHONY: gen_jobs jobs_clean - -JOBS_JSON ?= jobs.json -JOBS_OUTDIR ?= jobs - -$(JOBS_OUTDIR): - mkdir -p $(JOBS_OUTDIR) - -gen_jobs: $(JOBS_JSON) util/gen_jobs.py | $(JOBS_OUTDIR) - $(PYTHON) util/gen_jobs.py $(JOBS_JSON) $(JOBS_OUTDIR) - -jobs_clean: - rm -f jobs/gen_*.txt - rm -f jobs/*/gen_*.txt - - -## -------------- -## CI -## -------------- - -.PHONY: gen_ci ci_clean - -CI_TPL ?= .ci/gitlab-ci.yml.tpl - -gen_ci: .gitlab-ci.yml - -.gitlab-ci.yml: $(CI_TPL) util/gen_ci.py $(JOBS_JSON) - $(PYTHON) util/gen_ci.py $(JOBS_JSON) $(CI_TPL) > $@ - -ci_clean: - rm -f .gitlab-ci.yml - -bender: -ifeq (,$(wildcard ./bender)) - curl --proto '=https' --tlsv1.2 -sSf https://pulp-platform.github.io/bender/init \ - | bash -s -- 0.25.3 - touch bender -endif - -.PHONY: bender-rm -bender-rm: - rm -f bender - - -## -------------- -## RTL -## -------------- - -.PHONY: gen_rtl rtl_clean - -gen_rtl: $(RTL_CFGS) - -gen_rtl_%: util/idma_gen.py Makefile - $(PYTHON) util/idma_gen.py backend \ - --read-protocols $(subst -, ,$(call pw,1,.,$*)) \ - --write-protocols $(subst -, ,$(call pw,2,.,$*)) \ - --shifter $(call pw,3,.,$*) - $(PYTHON) util/idma_gen.py synth_wrapper \ - --read-protocols $(subst -, ,$(call pw,1,.,$*)) \ - --write-protocols $(subst -, ,$(call pw,2,.,$*)) - $(PYTHON) util/idma_gen.py testbench \ - --read-protocols $(subst -, ,$(call pw,1,.,$*)) \ - --write-protocols $(subst -, ,$(call pw,2,.,$*)) - -rtl_clean: - rm -f src/backend/Bender.yml - rm -rf src/backend/backend_* - rm -f scripts/waves/vsim_backend_*.do - -## -------------- -## Register -## -------------- - -.PHONY: gen_regs reg32_2d_regs reg64_regs desc64_regs regs_clean - -REG_PATH ?= $(shell $(BENDER) path register_interface) -REG_TOOL ?= $(REG_PATH)/vendor/lowrisc_opentitan/util/regtool.py - -REG32_2D_FE_DIR = src/frontends/register_32bit_2d/ -REG32_2D_HJSON = $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.hjson -REG64_FE_DIR = src/frontends/register_64bit/ -REG64_HJSON = $(REG64_FE_DIR)/idma_reg64_frontend.hjson -REG64_2D_FE_DIR = src/frontends/register_64bit_2d/ -REG64_2D_HJSON = $(REG64_2D_FE_DIR)/idma_reg64_2d_frontend.hjson -DESC64_FE_DIR = src/frontends/desc64/ -DESC64_HJSON = $(DESC64_FE_DIR)/idma_desc64_frontend.hjson - -REG_HTML_STRING = "\n\n\n\n\n" - -gen_regs: reg32_2d_regs reg64_regs desc64_regs reg64_2d_regs - -reg32_2d_regs: - $(PYTHON) $(REG_TOOL) $(REG32_2D_HJSON) -t $(REG32_2D_FE_DIR) -r - $(PYTHON) $(REG_TOOL) $(REG32_2D_HJSON) -D > $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.h - printf $(REG_HTML_STRING) > $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.html - $(PYTHON) $(REG_TOOL) $(REG32_2D_HJSON) -d >> $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.html - printf "\n" >> $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.html - cp $(REG_PATH)/vendor/lowrisc_opentitan/util/reggen/reg_html.css $(REG32_2D_FE_DIR) - -reg64_regs: - $(PYTHON) $(REG_TOOL) $(REG64_HJSON) -t $(REG64_FE_DIR) -r - $(PYTHON) $(REG_TOOL) $(REG64_HJSON) -D > $(REG64_FE_DIR)/idma_reg64_frontend.h - printf $(REG_HTML_STRING) > $(REG64_FE_DIR)/idma_reg64_frontend.html - $(PYTHON) $(REG_TOOL) $(REG64_HJSON) -d >> $(REG64_FE_DIR)/idma_reg64_frontend.html - printf "\n" >> $(REG64_FE_DIR)/idma_reg64_frontend.html - cp $(REG_PATH)/vendor/lowrisc_opentitan/util/reggen/reg_html.css $(REG64_FE_DIR) - -reg64_2d_regs: - $(PYTHON) $(REG_TOOL) $(REG64_2D_HJSON) -t $(REG64_2D_FE_DIR) -r - $(PYTHON) $(REG_TOOL) $(REG64_2D_HJSON) -D > $(REG64_2D_FE_DIR)/idma_reg64_2d_frontend.h - printf $(REG_HTML_STRING) > $(REG64_2D_FE_DIR)/idma_reg64_2d_frontend.html - $(PYTHON) $(REG_TOOL) $(REG64_2D_HJSON) -d >> $(REG64_2D_FE_DIR)/idma_reg64_2d_frontend.html - printf "\n" >> $(REG64_2D_FE_DIR)/idma_reg64_2d_frontend.html - cp $(REG_PATH)/vendor/lowrisc_opentitan/util/reggen/reg_html.css $(REG64_2D_FE_DIR) - -desc64_regs: - $(PYTHON) $(REG_TOOL) $(DESC64_HJSON) -t $(DESC64_FE_DIR) -r - $(PYTHON) $(REG_TOOL) $(DESC64_HJSON) -D > $(DESC64_FE_DIR)/idma_desc64_frontend.h - printf $(REG_HTML_STRING) > $(DESC64_FE_DIR)/idma_desc64_frontend.html - $(PYTHON) $(REG_TOOL) $(DESC64_HJSON) -d >> $(DESC64_FE_DIR)/idma_desc64_frontend.html - printf "\n" >> $(DESC64_FE_DIR)/idma_desc64_frontend.html - cp $(REG_PATH)/vendor/lowrisc_opentitan/util/reggen/reg_html.css $(DESC64_FE_DIR) - -regs_clean: - rm -f $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.h - rm -f $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend_reg_pkg.sv - rm -f $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend_reg_top.sv - rm -f $(REG32_2D_FE_DIR)/idma_reg32_2d_frontend.html - rm -f $(REG32_2D_FE_DIR)/reg_html.css - rm -f $(REG64_FE_DIR)/idma_reg64_frontend.h - rm -f $(REG64_FE_DIR)/idma_reg64_frontend_reg_pkg.sv - rm -f $(REG64_FE_DIR)/idma_reg64_frontend_reg_top.sv - rm -f $(REG64_FE_DIR)/idma_reg64_frontend.html - rm -f $(REG64_FE_DIR)/reg_html.css - rm -f $(REG64_2D_FE_DIR)/idma_reg64_2d_frontend.h - rm -f $(REG64_2D_FE_DIR)/idma_reg64_2d_frontend_reg_pkg.sv - rm -f $(REG64_2D_FE_DIR)/idma_reg64_2d_frontend_reg_top.sv - rm -f $(REG64_2D_FE_DIR)/idma_reg64_2d_frontend.html - rm -f $(REG64_2D_FE_DIR)/reg_html.css - rm -f $(DESC64_FE_DIR)/idma_desc64_frontend.h - rm -f $(DESC64_FE_DIR)/idma_desc64_reg_pkg.sv - rm -f $(DESC64_FE_DIR)/idma_desc64_reg_top.sv - rm -f $(DESC64_FE_DIR)/idma_desc64_frontend.html - rm -f $(DESC64_FE_DIR)/reg_html.css +include idma.mk diff --git a/README.md b/README.md index 5a117c31..0c321168 100644 --- a/README.md +++ b/README.md @@ -282,6 +282,7 @@ We currently do not include any free and open-source simulation setup. However, a simulation can be launched using: ```bash +make gen_rtl_axi.obi.split make prepare_sim export VSIM="questa-2022.3 vsim" $VSIM -c -do "source scripts/compile_vsim.tcl; quit" @@ -293,13 +294,17 @@ $VSIM -c -t 1ps -voptargs=+acc \ -do "source scripts/start_vsim.tcl; run -all" ``` with gui: -``` +```bash +make gen_rtl_axi-tilelink.axi.split +make prepare_sim +export VSIM="questa-2022.3 vsim" +$VSIM -c -do "source scripts/compile_vsim.tcl; quit" $VSIM -t 1ps -voptargs=+acc \ +job_file=jobs/backend/man_tiny.txt \ -logfile logs/backend.simple.vsim.log \ - -wlf logs/backend.simple.wlf \ - tb_idma_backend_r_axi_w_tilelink \ - -do "source scripts/start_vsim.tcl; source scripts/waves/vsim_backend_r_axi_w_tilelink.do; run -all" + -wlf logs/backend.medium.wlf \ + tb_idma_backend_rw_axi_r_tilelink \ + -do "source scripts/start_vsim.tcl; source scripts/waves/vsim_backend_rw_axi_r_tilelink.do; run -all" ``` Where: diff --git a/doc/.gitignore b/doc/.gitignore new file mode 100644 index 00000000..fff39eba --- /dev/null +++ b/doc/.gitignore @@ -0,0 +1 @@ +fig/graph diff --git a/doc/Makefile b/doc/Makefile deleted file mode 100644 index b1cf64b2..00000000 --- a/doc/Makefile +++ /dev/null @@ -1,38 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 - -# Minimal makefile for Sphinx documentation - -# You can set these variables from the command line. -SPHINXOPTS = -SPHINXBUILD ?= sphinx-build -SPHINXPROJ = iDMA -SOURCEDIR = source -BUILDDIR = build -MORTY ?= morty - -all-html: morty-docs regs html - -# Put it first so that "make" without argument is like "make help". -help: - @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) - -.PHONY: help Makefile morty-docs - -# Catch-all target: route all unknown targets to Sphinx using the new -# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). -%: Makefile - @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) - -# Requires an up-to-date morty installation -morty-docs: - $(MORTY) $$(cat ../sources.txt | sed -e "s/+incdir+/-I /" | sed -e "s/.\//..\//" | grep "\.\.\/src/\|-I") --doc $(BUILDDIR)/html/morty - -regs: - mkdir -p $(BUILDDIR)/html/regs - cp ../src/frontends/register_32bit_2d/idma_reg32_2d_frontend.html $(BUILDDIR)/html/regs/. - cp ../src/frontends/register_64bit/idma_reg64_frontend.html $(BUILDDIR)/html/regs/. - cp ../src/frontends/desc64/idma_desc64_frontend.html build/html/regs/. - cp ../src/frontends/register_32bit_2d/reg_html.css $(BUILDDIR)/html/regs/. - diff --git a/doc/images/backend.png b/doc/fig/backend.png similarity index 100% rename from doc/images/backend.png rename to doc/fig/backend.png diff --git a/doc/images/backend_buffer.png b/doc/fig/backend_buffer.png similarity index 100% rename from doc/images/backend_buffer.png rename to doc/fig/backend_buffer.png diff --git a/doc/images/bslk_thumb.png b/doc/fig/bslk_thumb.png similarity index 100% rename from doc/images/bslk_thumb.png rename to doc/fig/bslk_thumb.png diff --git a/doc/images/iDMA_overview b/doc/fig/iDMA_overview similarity index 100% rename from doc/images/iDMA_overview rename to doc/fig/iDMA_overview diff --git a/doc/images/iDMA_overview.pdf b/doc/fig/iDMA_overview.pdf similarity index 100% rename from doc/images/iDMA_overview.pdf rename to doc/fig/iDMA_overview.pdf diff --git a/doc/images/iDMA_overview.svg b/doc/fig/iDMA_overview.svg similarity index 100% rename from doc/images/iDMA_overview.svg rename to doc/fig/iDMA_overview.svg diff --git a/doc/images/verification.png b/doc/fig/verification.png similarity index 100% rename from doc/images/verification.png rename to doc/fig/verification.png diff --git a/doc/source/backend.rst b/doc/src/backend.rst similarity index 99% rename from doc/source/backend.rst rename to doc/src/backend.rst index 86c20890..2e9953b4 100644 --- a/doc/source/backend.rst +++ b/doc/src/backend.rst @@ -9,7 +9,7 @@ It contains two important modules: - :ref:`Legalizer` - :ref:`Transport Layer` -.. image:: ../images/backend.png +.. image:: ../fig/backend.png :width: 600 Parameters @@ -197,6 +197,6 @@ The transport layer is responsible for the AXI communication, taking AW and AR r + R/W: route them through DMA? + AW/AR/B? -.. image:: ../images/backend_buffer.png +.. image:: ../fig/backend_buffer.png :width: 600 diff --git a/doc/source/conf.py b/doc/src/conf.py similarity index 97% rename from doc/source/conf.py rename to doc/src/conf.py index 3327f8da..464e0f72 100644 --- a/doc/source/conf.py +++ b/doc/src/conf.py @@ -45,9 +45,7 @@ 'sphinx.ext.todo', 'recommonmark', 'sphinxcontrib.inkscapeconverter', -# 'sphinxcontrib.wavedrom', ] -#wavedrom_html_jsinline = False # Add any paths that contain templates here, relative to this directory. templates_path = ['ytemplates'] @@ -74,7 +72,7 @@ exclude_patterns = [] # Numbering -numfig=True +numfig = True numfig_format = {'figure': 'Figure %s', 'table': 'Table %s', 'code-block': 'Listing %s'} # The name of the Pygments (syntax highlighting) style to use. @@ -86,7 +84,6 @@ # The theme to use for HTML and HTML Help pages. See the documentation for # a list of builtin themes. # -#html_theme = 'alabaster' html_theme = 'sphinx_rtd_theme' # Theme options are theme-specific and customize the look and feel of a theme @@ -94,12 +91,11 @@ # documentation. # html_theme_options = {'style_nav_header_background': '#DDDDDD'} -html_logo = '../images/bslk_thumb.png' +html_logo = '../fig/bslk_thumb.png' # Add any paths that contain custom static files (such as style sheets) here, # relative to this directory. They are copied after the builtin static files, # so a file named "default.css" will overwrite the builtin "default.css". -#html_static_path = ['ystatic'] # Set html_static_path to null on the advice of RTDs: html_static_path = [] diff --git a/doc/source/error_handling.rst b/doc/src/error_handling.rst similarity index 100% rename from doc/source/error_handling.rst rename to doc/src/error_handling.rst diff --git a/doc/source/frontend.rst b/doc/src/frontend.rst similarity index 100% rename from doc/source/frontend.rst rename to doc/src/frontend.rst diff --git a/doc/source/frontends/ariane_fe.rst b/doc/src/frontends/ariane_fe.rst similarity index 55% rename from doc/source/frontends/ariane_fe.rst rename to doc/src/frontends/ariane_fe.rst index a16c014c..e57ccc02 100644 --- a/doc/source/frontends/ariane_fe.rst +++ b/doc/src/frontends/ariane_fe.rst @@ -2,3 +2,7 @@ Ariane/Linux Frontend ===================== Frontend for Ariane (CVA6) ready for Linux use. + +.. only:: html + +- `32bit 2D register frontend <../regs/idma_desc64.html>`_ diff --git a/doc/source/frontends/register_fe.rst b/doc/src/frontends/register_fe.rst similarity index 72% rename from doc/source/frontends/register_fe.rst rename to doc/src/frontends/register_fe.rst index a3154b0a..92107d85 100644 --- a/doc/source/frontends/register_fe.rst +++ b/doc/src/frontends/register_fe.rst @@ -11,7 +11,6 @@ Currently supported are: .. only:: html -- `32bit 2D register frontend <../regs/idma_reg32_2d_frontend.html>`_ -- `64bit register frontend <../regs/idma_reg64_frontend.html>`_ - -Please see the corresponding folder in the src/frontends directory for register description and header files. +- `32bit 2D register frontend <../regs/idma_reg32_2d.html>`_ +- `64bit register frontend <../regs/idma_reg64.html>`_ +- `64bit 2D register frontend <../regs/idma_reg64_2d.html>`_ diff --git a/doc/source/frontends/snitch_fe.rst b/doc/src/frontends/snitch_fe.rst similarity index 100% rename from doc/source/frontends/snitch_fe.rst rename to doc/src/frontends/snitch_fe.rst diff --git a/doc/source/index.rst b/doc/src/index.rst similarity index 71% rename from doc/source/index.rst rename to doc/src/index.rst index 06683698..c148e367 100644 --- a/doc/source/index.rst +++ b/doc/src/index.rst @@ -10,7 +10,7 @@ The modules of the :doc:`backend ` provide the basics of moving data ov The modules of the :doc:`frontend ` implement the programming interface and can be customized depending on the needs of a project. An optional :doc:`midend ` can be added to allow for translation of N-D requests from the :doc:`frontend ` to the :ref:`1-D requests ` accepted by the :doc:`backend `. -.. image:: ../images/iDMA_overview.svg +.. image:: ../fig/iDMA_overview.svg :width: 600 Philosophy / Idea @@ -38,6 +38,22 @@ The main documentation of the submodules is divided into the following sections: verification.rst system_integration.rst + +The morty docs provide the generated description of the SystemVerilog files within this repository. + .. only:: html - The `Morty docs `_ provide the generated description of the SystemVerilog files within this repository. + `R_AXI_W_OBI `_ + + `R_OBI_W_AXI `_ + + `RW_AXI `_ + +.. image:: ../fig/graph/idma_backend_r_axi_w_obi.png + :width: 600 + +.. image:: ../fig/graph/idma_backend_r_obi_w_axi.png + :width: 600 + +.. image:: ../fig/graph/idma_backend_rw_axi.png + :width: 600 \ No newline at end of file diff --git a/doc/source/midend.rst b/doc/src/midend.rst similarity index 100% rename from doc/source/midend.rst rename to doc/src/midend.rst diff --git a/doc/source/system_integration.rst b/doc/src/system_integration.rst similarity index 100% rename from doc/source/system_integration.rst rename to doc/src/system_integration.rst diff --git a/doc/source/verification.rst b/doc/src/verification.rst similarity index 93% rename from doc/source/verification.rst rename to doc/src/verification.rst index f11d036e..6318ed28 100644 --- a/doc/source/verification.rst +++ b/doc/src/verification.rst @@ -5,7 +5,7 @@ Exhaustive verification of the DMA backend is a necessity to ensure proper funct For verification, two golden models will be used: -.. image:: ../images/verification.png +.. image:: ../fig/verification.png :width: 300 :class: float-right diff --git a/idma.mk b/idma.mk new file mode 100644 index 00000000..ac15ddd6 --- /dev/null +++ b/idma.mk @@ -0,0 +1,401 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Authors: +# - Thomas Benz + +BENDER ?= bender +DOT ?= dot +GIT ?= git +MORTY ?= morty +PRINTF ?= printf +PYTHON ?= python3 +SPHINXBUILD ?= sphinx-build +VCS ?= vcs +VERILATOR ?= verilator +VLOGAN ?= vlogan + +# iDMA paths +IDMA_ROOT ?= $(shell $(BENDER) path idma) +IDMA_REG_DIR := $(shell $(BENDER) path register_interface) +IDMA_REGTOOL ?= $(IDMA_REG_DIR)/vendor/lowrisc_opentitan/util/regtool.py +IDMA_UTIL_DIR := $(IDMA_ROOT)/util +IDMA_RTL_DIR := $(IDMA_ROOT)/target/rtl + +# Bender files +IDMA_GEN_BENDER := $(IDMA_RTL_DIR)/Bender.yml +IDMA_BENDER_FILES := $(IDMA_ROOT)/Bender.yml \ + $(IDMA_ROOT)/Bender.lock \ + $(IDMA_GEN_BENDER) + +# Helper functions +# Relative paths for VLOGAN +IDMA_VLOGAN_REL_PATHS := | grep -v "ROOT=" | sed '3 i ROOT="."' +# Morty helpers +IDMA_PATH_ESCAPED := $(shell pwd | sed 's_/_\\/_g') +IDMA_RELATIVE_PATH_REGEX := 's/$(IDMA_PATH_ESCAPED)/./' + +# Ensure half-built targets are purged +.DELETE_ON_ERROR: + + +# -------------- +# Help +# -------------- +.PHONY: idma-all idma-help + +idma-all: + @echo $(IDMA_PATH_ESCAPED) + +idma-help: + @echo "" + @echo "iDMA Makefile" + @echo "-------------" + @echo "" + @echo "prepare_sim: uses bender to generate the analyze scripts needed for simulating the iDMA" + @echo "bin/iDMA.vcs VCS_TP=**YOUR_TB**: creates the VCS executable" + @echo "obj_iDMA VLT_TOP=**YOUR_TOP_LVL**: elaborates the hardware using verilator" + @echo "pickle: uses morty to generate a pickled version of the hardware" + @echo "doc: generates the documentation in doc/build" + @echo "gen_ci: regenerates the gitlab CI (only ETH internal used)" + @echo "gen_regs: regenerates the registers using reggen" + @echo "" + @echo "clean: cleans generated files" + @echo "nuke: cleans all generated file, also almost all files checked in" + @echo "" + + +## -------------- +## RTL +## -------------- + +.PHONY: idma_rtl_clean + +IDMA_BACKEND_IDS = rw_axi r_obi_w_axi r_axi_w_obi + +# All RTL files +IDMA_RTL_ALL := +IDMA_TB_ALL := +IDMA_RTL_DOC_ALL := + +IDMA_GEN := $(IDMA_UTIL_DIR)/gen_idma.py +IDMA_GEN_SRC := $(IDMA_UTIL_DIR)/mario/backend.py \ + $(IDMA_UTIL_DIR)/mario/bender.py \ + $(IDMA_UTIL_DIR)/mario/database.py \ + $(IDMA_UTIL_DIR)/mario/legalizer.py \ + $(IDMA_UTIL_DIR)/mario/synth.py \ + $(IDMA_UTIL_DIR)/mario/testbench.py \ + $(IDMA_UTIL_DIR)/mario/transport_layer.py \ + $(IDMA_UTIL_DIR)/mario/util.py \ + $(IDMA_UTIL_DIR)/mario/wave.py +IDMA_DB_DIR := $(IDMA_ROOT)/src/db +IDMA_DB_FILES := $(IDMA_DB_DIR)/idma_axi.yml \ + $(IDMA_DB_DIR)/idma_axi_lite.yml \ + $(IDMA_DB_DIR)/idma_axi_stream.yml \ + $(IDMA_DB_DIR)/idma_init.yml \ + $(IDMA_DB_DIR)/idma_obi.yml \ + $(IDMA_DB_DIR)/idma_tilelink.yml +IDMA_RTL_FILES := $(IDMA_RTL_DIR)/idma_transport_layer \ + $(IDMA_RTL_DIR)/idma_legalizer \ + $(IDMA_RTL_DIR)/idma_backend \ + $(IDMA_RTL_DIR)/idma_backend_synth +IDMA_VSIM_DIR := $(IDMA_ROOT)/target/sim/vsim + +define idma_gen + $(PYTHON) $(IDMA_GEN) --entity $1 --tpl $2 --db $3 --ids $4 > $5 +endef + +$(IDMA_GEN_BENDER): $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_RTL_DIR)/tpl/Bender.yml.tpl $(IDMA_DB_FILES) $(IDMA_ROOT)/idma.mk + $(call idma_gen,bender,$(IDMA_RTL_DIR)/tpl/Bender.yml.tpl,$(IDMA_DB_FILES),$(IDMA_BACKEND_IDS),$@) + +$(IDMA_RTL_DIR)/idma_transport_layer_%.sv: $(IDMA_GEN) $(IDMA_GEN_BENDER) $(IDMA_ROOT)/src/backend/tpl/idma_transport_layer.sv.tpl + $(call idma_gen,transport,$(IDMA_ROOT)/src/backend/tpl/idma_transport_layer.sv.tpl,$(IDMA_DB_FILES),$*,$@) + +$(IDMA_RTL_DIR)/idma_legalizer_%.sv: $(IDMA_GEN) $(IDMA_GEN_BENDER) $(IDMA_ROOT)/src/backend/tpl/idma_legalizer.sv.tpl + $(call idma_gen,legalizer,$(IDMA_ROOT)/src/backend/tpl/idma_legalizer.sv.tpl,$(IDMA_DB_FILES),$*,$@) + +$(IDMA_RTL_DIR)/idma_backend_%.sv: $(IDMA_GEN) $(IDMA_RTL_DIR)/idma_legalizer_%.sv $(IDMA_RTL_DIR)/idma_transport_layer_%.sv $(IDMA_ROOT)/src/backend/tpl/idma_backend.sv.tpl + $(call idma_gen,backend,$(IDMA_ROOT)/src/backend/tpl/idma_backend.sv.tpl,$(IDMA_DB_FILES),$*,$@) + +$(IDMA_RTL_DIR)/idma_backend_synth_%.sv: $(IDMA_GEN) $(IDMA_RTL_DIR)/idma_backend_%.sv $(IDMA_ROOT)/src/backend/tpl/idma_backend_synth.sv.tpl + $(call idma_gen,synth_wrapper,$(IDMA_ROOT)/src/backend/tpl/idma_backend_synth.sv.tpl,$(IDMA_DB_FILES),$*,$@) + +$(IDMA_RTL_DIR)/tb_idma_backend_%.sv: $(IDMA_GEN) $(IDMA_RTL_DIR)/idma_backend_%.sv $(IDMA_ROOT)/test/tpl/tb_idma_backend.sv.tpl + $(call idma_gen,testbench,$(IDMA_ROOT)/test/tpl/tb_idma_backend.sv.tpl,$(IDMA_DB_FILES),$*,$@) + +$(IDMA_VSIM_DIR)/wave/backend_%.do: $(IDMA_GEN) $(IDMA_RTL_DIR)/tb_idma_backend_%.sv $(IDMA_VSIM_DIR)/wave/tpl/backend.do.tpl + $(call idma_gen,vsim_wave,$(IDMA_VSIM_DIR)/wave/tpl/backend.do.tpl,$(IDMA_DB_FILES),$*,$@) + +idma_rtl_clean: + rm -f $(IDMA_RTL_DIR)/Bender.yml + rm -f $(IDMA_RTL_DIR)/*.sv + rm -f $(IDMA_VSIM_DIR)/wave/*.do + +# assemble the required files +IDMA_RTL_ALL += $(foreach X,$(IDMA_RTL_FILES),$(foreach Y,$(IDMA_BACKEND_IDS),$X_$Y.sv)) +IDMA_TB_ALL += $(foreach Y,$(IDMA_BACKEND_IDS),$(IDMA_RTL_DIR)/tb_idma_backend_$Y.sv) +IDMA_TB_ALL += $(foreach Y,$(IDMA_BACKEND_IDS),$(IDMA_VSIM_DIR)/wave/backend_$Y.do) + + +## -------------- +## Register +## -------------- + +.PHONY: idma_reg_clean + +IDMA_DOC_SRC_DIR := $(IDMA_ROOT)/doc/src +IDMA_DOC_FIG_DIR := $(IDMA_ROOT)/doc/fig +IDMA_DOC_OUT_DIR := $(IDMA_ROOT)/target/doc +IDMA_HTML_DIR := $(IDMA_DOC_OUT_DIR)/html +IDMA_FE_DIR := $(IDMA_ROOT)/src/frontends +IDMA_FE_REGS := desc64 reg32_2d reg64 reg64_2d + +$(IDMA_HTML_DIR)/regs/reg_html.css: + mkdir -p $(IDMA_HTML_DIR)/regs + cp $(IDMA_REG_DIR)/vendor/lowrisc_opentitan/util/reggen/reg_html.css $@ + +$(IDMA_RTL_DIR)/idma_%_reg_pkg.sv $(IDMA_RTL_DIR)/idma_%_reg_top.sv: $(IDMA_GEN_BENDER) + $(PYTHON) $(IDMA_REGTOOL) $(IDMA_FE_DIR)/$*/idma_$*.hjson -t $(IDMA_RTL_DIR) -r + +$(IDMA_HTML_DIR)/regs/idma_%.html: $(IDMA_HTML_DIR)/regs/reg_html.css + $(PRINTF) "\n\n\n\n\n" > $@ + $(PYTHON) $(IDMA_REGTOOL) $(IDMA_FE_DIR)/$*/idma_$*.hjson -d >> $@ + $(PRINTF) "\n" >> $@ + +idma_reg_clean: + rm -rf $(IDMA_HTML_DIR)/regs + rm -f $(IDMA_RTL_DIR)/*_reg_top.sv + rm -f $(IDMA_RTL_DIR)/*_reg_pkg.sv + rm -f $(IDMA_RTL_DIR)/Bender.yml + +# assemble the required files +IDMA_RTL_ALL += $(foreach Y,$(IDMA_FE_REGS),$(IDMA_RTL_DIR)/idma_$Y_reg_pkg.sv) +IDMA_RTL_ALL += $(foreach Y,$(IDMA_FE_REGS),$(IDMA_RTL_DIR)/idma_$Y_reg_top.sv) +IDMA_RTL_DOC_ALL += $(foreach Y,$(IDMA_FE_REGS),$(IDMA_HTML_DIR)/regs/idma_$Y.html) + + +# --------------- +# Morty +# --------------- + +.PHONY: idma_morty_clean + +IDMA_PICKLE_DIR := $(IDMA_ROOT)/target/morty + +$(IDMA_PICKLE_DIR)/sources.json: $(IDMA_BENDER_FILES) $(IDMA_TB_ALL) $(IDMA_RTL_ALL) + $(BENDER) update + $(BENDER) checkout + mkdir -p $(IDMA_PICKLE_DIR) + $(BENDER) sources -f -t rtl -t synthesis -t pulp -t asic | sed -e $(IDMA_RELATIVE_PATH_REGEX) > $@ + +$(IDMA_PICKLE_DIR)/%.sv: $(IDMA_PICKLE_DIR)/sources.json + $(MORTY) -f $< -i --top $* --propagate_defines -o $@ + +$(IDMA_HTML_DIR)/%/index.html: $(IDMA_PICKLE_DIR)/%.sv + mkdir -p $(IDMA_HTML_DIR)/$* + $(MORTY) -i --doc $(IDMA_HTML_DIR)/$* $< + +$(IDMA_PICKLE_DIR)/%.dot: $(IDMA_PICKLE_DIR)/sources.json + $(MORTY) -f $< -i --top $* --propagate_defines --graph_file $@ > /dev/null + +$(IDMA_DOC_FIG_DIR)/graph/%.png: $(IDMA_PICKLE_DIR)/%.dot + mkdir -p $(IDMA_DOC_FIG_DIR)/graph + $(DOT) -Tpng $< > $@ + +idma_morty_clean: + rm -rf $(IDMA_PICKLE_DIR) + rm -f $(IDMA_DOC_FIG_DIR)/graph/*.png + rm -rf $(IDMA_HTML_DIR) + +IDMA_RTL_DOC_ALL += $(foreach Y,$(IDMA_BACKEND_IDS),$(IDMA_DOC_FIG_DIR)/graph/idma_backend_$Y.png) +IDMA_RTL_DOC_ALL += $(foreach Y,$(IDMA_BACKEND_IDS),$(IDMA_HTML_DIR)/idma_backend_$Y/index.html) + + +# -------------- +# QuestaSim +# -------------- + +.PHONY: idma_sim_clean + +IDMA_VLOG_ARGS := -suppress vlog-2583 \ + -suppress vlog-13314 \ + -suppress vlog-13233 \ + -timescale \"1 ns / 1 ps\" + +define idma_generate_vsim + echo 'set ROOT [file normalize [file dirname [info script]]/$3]' > $1 + $(BENDER) script vsim --vlog-arg="$(IDMA_VLOG_ARGS)" $2 | grep -v "set ROOT" >> $1 + echo >> $1 +endef + +$(IDMA_VSIM_DIR)/compile.tcl: $(IDMA_BENDER_FILES) $(IDMA_TB_ALL) $(IDMA_RTL_ALL) + $(BENDER) update + $(BENDER) checkout + $(call idma_generate_vsim, $@, -t sim -t test -t rtl -t asic,../../..) + +idma_sim_clean: + rm -rf $(IDMA_VSIM_DIR)/compile.tcl + rm -rf $(IDMA_VSIM_DIR)/work + rm -f $(IDMA_VSIM_DIR)/dma_trace_* + rm -f $(IDMA_VSIM_DIR)/dma_transfers.txt + rm -f $(IDMA_VSIM_DIR)/transcript + rm -f $(IDMA_VSIM_DIR)/wlf* + rm -f $(IDMA_VSIM_DIR)/logs/wlf* + rm -f $(IDMA_VSIM_DIR)/logs/*.wlf + rm -f $(IDMA_VSIM_DIR)/*.vstf + rm -f $(IDMA_VSIM_DIR)/*.vcd + rm -f $(IDMA_VSIM_DIR)/modelsim.ini + rm -f $(IDMA_VSIM_DIR)/logs/*vsim.log + + +# -------------- +# VCS +# -------------- + +.PHONY: idma_vcs_compile idma_vcs_clean + +IDMA_VCS_DIR := $(IDMA_ROOT)/target/sim/vcs +IDMA_VLOGAN_ARGS := -assert svaext \ + -assert disable_cover \ + -full64 \ + -sysc=q \ + -nc \ + -q \ + -timescale=1ns/1ns +IDMA_VCS_ARGS := -full64 \ + -debug_access+r \ + -j 8 \ + -CFLAGS "-Os" +IDMA_VCS_PARAMS ?= +IDMA_VCS_TB ?= + +$(IDMA_VCS_DIR)/compile.sh: $(IDMA_BENDER_FILES) $(IDMA_TB_ALL) $(IDMA_RTL_ALL) + $(BENDER) update + $(BENDER) checkout + $(BENDER) script vcs -t test -t rtl -t simulation --vlog-arg "\$(VLOGAN_ARGS)" --vlogan-bin "$(VLOGAN)" $(VLOGAN_REL_PATHS) > $@ + chmod +x $@ + +idma_vcs_compile: $(IDMA_VCS_DIR)/compile_vcs.sh + cd $(IDMA_VCS_DIR); ./compile.sh + +$(IDMA_VCS_DIR)/bin/%.vcs: idma_vcs_compile + mkdir -p $(IDMA_VCS_DIR)/bin + cd $(IDMA_VCS_DIR); $(VCS) $(IDMA_VCS_ARGS) $(IDMA_VCS_PARAMS) $(IDMA_VCS_TB) -o $@ + +idma_vcs_clean: + rm -rf $(IDMA_VCS_DIR)/AN.DB + rm -f $(IDMA_VCS_DIR)/compile.sh + rm -rf $(IDMA_VCS_DIR)/bin + rm -f $(IDMA_VCS_DIR)/ucli.key + rm -f $(IDMA_VCS_DIR)/vc_hdrs.h + rm -f $(IDMA_VCS_DIR)/logs/*.vcs.log + + +## -------------- +## Verilator +## -------------- + +.PHONY: idma_verilator_clean + +IDMA_VLT_DIR := $(IDMA_ROOT)/target/sim/verilator +IDMA_VLT_ARGS := --cc \ + --Wall \ + --Wno-fatal \ + +1800-2017ext+ \ + --assert \ + --hierarchical \ + --no-skip-identical + +$(IDMA_VLT_DIR)/obj_%: $(IDMA_PICKLE_DIR)/%.sv + cd$(IDMA_VLT_DIR); $(VERILATOR) $(IDMA_VLT_ARGS) -Mdir obj_$* $^ --top-module $* 2> $*_elab.log + +idma_verilator_clean: + rm -rf $(IDMA_VLT_DIR)/obj_* + rm -f $(IDMA_VLT_DIR)/*.log + + +# --------------- +# Doc +# --------------- + +.PHONY: idma_spinx_doc idma_spinx_doc_clean + +idma_spinx_doc: $(IDMA_RTL_DOC_ALL) $(IDMA_RTL_DOC_ALL) + $(SPHINXBUILD) -M html $(IDMA_DOC_SRC_DIR) $(IDMA_DOC_OUT_DIR) + +idma_spinx_doc_clean: + rm -rf $(IDMA_DOC_OUT_DIR) + + +## -------------- +## Job File +## -------------- + +.PHONY: idma_jobs idma_jobs_clean + +IDMA_JOBS_DIR := $(IDMA_ROOT)/jobs +IDMA_JOBS_JSON := $(IDMA_JOBS_DIR)/jobs.json + +idma_jobs: $(IDMA_JOBS_JSON) $(IDMA_UTIL_DIR)/gen_jobs.py + $(PYTHON) $< $(IDMA_JOBS_JSON) $(IDMA_JOBS_DIR) + +idma_jobs_clean: + rm -f $(IDMA_JOBS_DIR)/gen_*.txt + rm -f $(IDMA_JOBS_DIR)/*/gen_*.txt + + +# -------------- +# Misc Clean +# -------------- + +.PHONY: idma_clean_all idma_clean idma_misc_clean + +idma_clean_all idma_clean: idma_rtl_clean idma_reg_clean idma_morty_clean idma_sim_clean idma_vcs_clean idma_verilator_clean idma_spinx_doc_clean idma_jobs_clean + +idma_misc_clean: + rm -rf scripts/__pycache__ + rm -rf util/__pycache__ + rm -rf util/mario/__pycache__ + rm -f gmon.out + +idma_nuke: idma_clean + rm -rf .bender + + +## -------------- +## Phony Targets +## -------------- + +.PHONY: idma_rtl_all idma_doc_all + +idma_rtl_all: $(IDMA_RTL_ALL) + +idma_doc_all: idma_spinx_doc + +### -------------- +### CI +### -------------- +# +#.PHONY: gen_ci ci_clean +# +#CI_TPL ?= .ci/gitlab-ci.yml.tpl +# +#gen_ci: .gitlab-ci.yml +# +#.gitlab-ci.yml: $(CI_TPL) util/gen_ci.py $(JOBS_JSON) +# $(PYTHON) util/gen_ci.py $(JOBS_JSON) $(CI_TPL) > $@ +# +#ci_clean: +# rm -f .gitlab-ci.yml +# +#bender: +#ifeq (,$(wildcard ./bender)) +# curl --proto '=https' --tlsv1.2 -sSf https://pulp-platform.github.io/bender/init \ +# | bash -s -- 0.25.3 +# touch bender +#endif +# +#.PHONY: bender-rm +#bender-rm: +# rm -f bender diff --git a/jobs.json b/jobs/jobs.json similarity index 87% rename from jobs.json rename to jobs/jobs.json index 400d15b9..01ace9ac 100644 --- a/jobs.json +++ b/jobs/jobs.json @@ -146,9 +146,9 @@ "overrides" : { } }, - "axi_axi_lite_axi_stream_obi_init_backend" : { - "read" : ["axi", "axi_lite", "axi_stream", "obi", "init"], - "write": ["axi", "axi_lite", "axi_stream", "obi"], + "monster_backend" : { + "read" : ["axi", "axi_lite", "axi_stream", "obi", "tilelink", "init"], + "write": ["axi", "axi_lite", "axi_stream", "obi", "tilelink"], "seed" : 1336, "man_jobs" : { "simple" : "backend/man_simple.txt", @@ -186,6 +186,46 @@ "overrides" : { } }, + "tilelink_axi_backend" : { + "read" : ["tilelink", "axi"], + "write": ["tilelink", "axi"], + "seed" : 1336, + "man_jobs" : { + "simple" : "backend/man_simple.txt", + "same_dst_simple" : "backend/man_same_dst_simple.txt", + "huge" : "backend/man_huge.txt", + "large" : "backend/man_large.txt", + "medium" : "backend/man_medium.txt", + "mixed" : "backend/man_mixed.txt", + "small" : "backend/man_small.txt", + "tiny" : "backend/man_tiny.txt", + "zero_transfer" : "backend/man_zero_transfer.txt" + }, + "gen_jobs" : { + }, + "overrides" : { + } + }, + "tilelink_obi_backend" : { + "read" : ["tilelink", "obi"], + "write": ["tilelink", "obi"], + "seed" : 1336, + "man_jobs" : { + "simple" : "backend/man_simple.txt", + "same_dst_simple" : "backend/man_same_dst_simple.txt", + "huge" : "backend/man_huge.txt", + "large" : "backend/man_large.txt", + "medium" : "backend/man_medium.txt", + "mixed" : "backend/man_mixed.txt", + "small" : "backend/man_small.txt", + "tiny" : "backend/man_tiny.txt", + "zero_transfer" : "backend/man_zero_transfer.txt" + }, + "gen_jobs" : { + }, + "overrides" : { + } + }, "axi_to_tilelink_backend" : { "read" : ["axi"], "write": ["tilelink"], diff --git a/logs/.gitkeep b/logs/.gitkeep deleted file mode 100644 index e69de29b..00000000 diff --git a/requirements.txt b/requirements.txt index 4c63cd28..3bef2fab 100644 --- a/requirements.txt +++ b/requirements.txt @@ -7,4 +7,4 @@ sphinx sphinx-rtd-theme recommonmark sphinxcontrib-svg2pdfconverter -pylint \ No newline at end of file +pylint diff --git a/scripts/check-license b/scripts/check-license deleted file mode 100755 index d97653b5..00000000 --- a/scripts/check-license +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/bash -# Copyright 2020 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 - -set -e -ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) - -echo $ROOT -$ROOT/util/lowrisc_misc-linters/licence-checker/licence-checker.py -v --config $ROOT/util/licence-checker.hjson diff --git a/scripts/list-contributors b/scripts/list-contributors index 74bf6b94..72846b99 100755 --- a/scripts/list-contributors +++ b/scripts/list-contributors @@ -3,22 +3,13 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# Thomas Benz +# Authors: +# - Thomas Benz set -e ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) EXCLUDED=" \ - licence-checker.py \ - idma_reg32_2d_frontend_reg_pkg.sv \ - idma_reg32_2d_frontend_reg_top.sv \ - idma_reg32_2d_frontend.h \ - idma_reg64_frontend_reg_pkg.sv \ - idma_reg64_frontend_reg_top.sv \ - idma_reg64_frontend.h \ - idma_desc64_reg_top.sv \ - idma_desc64_reg_pkg.sv \ - idma_desc64.h \ encoding.h \ " diff --git a/scripts/list-todos b/scripts/list-todos index f6fda875..7184d1ed 100755 --- a/scripts/list-todos +++ b/scripts/list-todos @@ -3,22 +3,13 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# Thomas Benz +# Authors: +# - Thomas Benz set -e ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) EXCLUDED=" \ - licence-checker.py \ - idma_reg32_2d_frontend_reg_pkg.sv \ - idma_reg32_2d_frontend_reg_top.sv \ - idma_reg32_2d_frontend.h \ - idma_reg64_frontend_reg_pkg.sv \ - idma_reg64_frontend_reg_top.sv \ - idma_reg64_frontend.h \ - idma_desc64_reg_top.sv \ - idma_desc64_reg_pkg.sv \ - idma_desc64.h \ encoding.h \ list-todos.py \ doc/source/conf.py \ diff --git a/scripts/python-lint b/scripts/python-lint deleted file mode 100755 index 1d73935d..00000000 --- a/scripts/python-lint +++ /dev/null @@ -1,19 +0,0 @@ -#!/bin/bash -# Copyright 2020 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 - -set -e -ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) - -# Skip third party sources. -find $ROOT/ \ - -not \( -path '*.bender' -prune \) \ - -not \( -path '*util/lowrisc_misc-linters' -prune \) \ - -not \( -path '*doc/source' -prune \) \ - -not \( -name 'lint-commits.py' \) \ - -name '*.py' \ - | xargs pylint --reports=y --suggestion-mode=y \ - --disable=W0632 \ - --disable=C0103 \ - --disable=R0801 diff --git a/scripts/verible-lint b/scripts/verible-lint deleted file mode 100755 index 21d482ba..00000000 --- a/scripts/verible-lint +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/bash -# Copyright 2020 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 - -set -e -ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) - -# Skip third party sources and testbenches. -find $ROOT/ \ - -not \( -path '*.bender/*' -prune \) \ - -not \( -path '*morty/*' -prune \) \ - -not \( -path '*test/*' -prune \) \ - -not \( -path '*systems/pulpopen/idma_axi_to_mem.sv' -prune \) \ - -name '*.sv' - -find $ROOT/ \ - -not \( -path '*.bender/*' -prune \) \ - -not \( -path '*morty/*' -prune \) \ - -not \( -path '*test/*' -prune \) \ - -not \( -path '*systems/pulpopen/idma_axi_to_mem.sv' -prune \) \ - -name '*.sv' \ - | xargs verible-verilog-lint \ - --rules=-interface-name-style --lint_fatal --parse_fatal \ - --waiver_files $ROOT/util/waiver.verible diff --git a/scripts/waves/vsim_backend.do.tpl b/scripts/waves/vsim_backend.do.tpl deleted file mode 100644 index 8b0a8026..00000000 --- a/scripts/waves/vsim_backend.do.tpl +++ /dev/null @@ -1,173 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/clk_i -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/rst_ni -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/testmode_i -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/idma_req_i -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/req_valid_i -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/req_ready_o -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/idma_rsp_o -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/rsp_valid_o -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/rsp_ready_i -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/idma_eh_req_i -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/eh_req_valid_i -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/eh_req_ready_o -% for protocol in used_read_protocols: -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/${protocol}_read_req_o -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/${protocol}_read_rsp_i -% endfor -% for protocol in used_write_protocols: -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/${protocol}_write_req_o -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/${protocol}_write_rsp_i -% endfor -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/busy_o -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/dp_busy -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/dp_poison -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/r_req -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/w_req -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/r_valid -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/w_valid -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/r_ready -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/w_ready -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/w_last_burst -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/w_last_ready -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/w_super_last -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/r_dp_req_in_ready -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/w_dp_req_in_ready -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/r_dp_req_out_valid -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/w_dp_req_out_valid -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/r_dp_req_out_ready -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/w_dp_req_out_ready -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/r_dp_req_out -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/w_dp_req_out -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/r_dp_rsp -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/w_dp_rsp -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/r_dp_rsp_valid -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/w_dp_rsp_valid -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/r_dp_rsp_ready -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/w_dp_rsp_ready -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/ar_ready -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/aw_ready -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/aw_ready_dp -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/aw_valid_dp -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/aw_req_dp -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/legalizer_flush -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/legalizer_kill -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/is_length_zero -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/req_valid -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/idma_rsp -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/rsp_valid -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/rsp_ready -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/clk_i -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/rst_ni -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/req_i -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/valid_i -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/ready_o -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_req_o -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_valid_o -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_ready_i -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_req_o -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_valid_o -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_ready_i -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/flush_i -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/kill_i -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_busy_o -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_busy_o -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_tf_q -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_tf_q -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/opt_tf_q -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_tf_ena -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_tf_ena -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_num_bytes_to_pb -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_num_bytes_to_pb -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/c_num_bytes_to_pb -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_num_bytes_possible -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_num_bytes -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_addr_offset -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_done -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_num_bytes_possible -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_num_bytes -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_addr_offset -add wave -noupdate -group Legalizer /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_done -add wave -noupdate -group {Transport Layer} /tb_idma_backend${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/clk_i -add wave -noupdate -group {Transport Layer} /tb_idma_backend${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/rst_ni -add wave -noupdate -group {Transport Layer} /tb_idma_backend${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/testmode_i -% for protocol in used_read_protocols: -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/${protocol}_read_req_o -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/${protocol}_read_rsp_i -% endfor -% for protocol in used_write_protocols: -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/${protocol}_write_req_o -add wave -noupdate -expand -group Backend /tb_idma_backend${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/${protocol}_write_rsp_i -% endfor -add wave -noupdate -group {Transport Layer} /tb_idma_backend${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/* -% for protocol in used_read_protocols: -add wave -noupdate -group {${database[protocol]['full_name']} Read} -expand /tb_idma_backend${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/i_idma_${protocol}_read/* -% endfor -% for protocol in used_write_protocols: -add wave -noupdate -group {${database[protocol]['full_name']} Write} -expand /tb_idma_backend${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/i_idma_${protocol}_write/* -% endfor -% if not one_write_port: -add wave -noupdate -group {Write Response FIFO} -expand /tb_idma_backend${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/i_write_response_fifo/* -% endif -% if one_read_port and one_write_port and ('axi' in used_read_protocols) and ('axi' in used_write_protocols): -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/clk_i -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/rst_ni -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/testmode_i -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/r_rsp_valid_i -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/r_rsp_ready_i -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/r_rsp_first_i -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/r_decouple_aw_i -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_decouple_aw_i -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_req_i -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_valid_i -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_ready_o -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_req_o -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_valid_o -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_ready_i -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_req_in -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_req_out -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_ready -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_valid -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/first -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_sent -add wave -noupdate -group R-AW-Coupler /tb_idma_backend${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_to_send_q -% endif -add wave -noupdate -divider BUS -% for protocol in used_protocols: - % if protocol == 'axi': -add wave -noupdate -group {${database[protocol]['full_name']} IF} -label AW /tb_idma_backend${name_uniqueifier}/i_aw_hl/in_wave -add wave -noupdate -group {${database[protocol]['full_name']} IF} -label AR /tb_idma_backend${name_uniqueifier}/i_ar_hl/in_wave -add wave -noupdate -group {${database[protocol]['full_name']} IF} -label W /tb_idma_backend${name_uniqueifier}/i_w_hl/in_wave -add wave -noupdate -group {${database[protocol]['full_name']} IF} -label R /tb_idma_backend${name_uniqueifier}/i_r_hl/in_wave -add wave -noupdate -group {${database[protocol]['full_name']} IF} -label B /tb_idma_backend${name_uniqueifier}/i_b_hl/in_wave - % else: -add wave -noupdate -group {${database[protocol]['full_name']} ${database['axi']['full_name']} IF} -label AW /tb_idma_backend${name_uniqueifier}/i_${protocol}_aw_hl/in_wave -add wave -noupdate -group {${database[protocol]['full_name']} ${database['axi']['full_name']} IF} -label AR /tb_idma_backend${name_uniqueifier}/i_${protocol}_ar_hl/in_wave -add wave -noupdate -group {${database[protocol]['full_name']} ${database['axi']['full_name']} IF} -label W /tb_idma_backend${name_uniqueifier}/i_${protocol}_w_hl/in_wave -add wave -noupdate -group {${database[protocol]['full_name']} ${database['axi']['full_name']} IF} -label R /tb_idma_backend${name_uniqueifier}/i_${protocol}_r_hl/in_wave -add wave -noupdate -group {${database[protocol]['full_name']} ${database['axi']['full_name']} IF} -label B /tb_idma_backend${name_uniqueifier}/i_${protocol}_b_hl/in_wave - % endif -% endfor -add wave -noupdate -group {iDMA IF} -label {iDMA REQ} /tb_idma_backend${name_uniqueifier}/i_req_hl/in_wave -add wave -noupdate -group {iDMA IF} -label {iDMA RSP} -expand -subitemconfig {/tb_idma_backend${name_uniqueifier}/i_rsp_hl/in_wave.pld -expand} /tb_idma_backend${name_uniqueifier}/i_rsp_hl/in_wave -add wave -noupdate -group {iDMA IF} -label {iDMA EH} /tb_idma_backend${name_uniqueifier}/i_eh_hl/in_wave -add wave -noupdate -group Busy -expand /tb_idma_backend${name_uniqueifier}/i_idma_backend/busy_o -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {0 ps} 0} -quietly wave cursor active 1 -configure wave -namecolwidth 150 -configure wave -valuecolwidth 427 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {1121282 ps} {1235722 ps} diff --git a/src/backend/.gitignore b/src/backend/.gitignore new file mode 100644 index 00000000..33061980 --- /dev/null +++ b/src/backend/.gitignore @@ -0,0 +1,2 @@ +Bender.yml +./*.sv diff --git a/src/backend/Bender.yml.tpl b/src/backend/Bender.yml.tpl deleted file mode 100644 index 6bb7aece..00000000 --- a/src/backend/Bender.yml.tpl +++ /dev/null @@ -1,43 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -package: - name: idma_backend - authors: - - "Tobias Senti " - -dependencies: - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.26.0 } - axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0-beta.2 } - tb_idma_backend: { path: "../../test" } - idma_pkg: { path: "../package" } - -export_include_dirs: - - ../include - -sources: - # Source files grouped in levels. Files in level 0 have no dependencies on files in this - # package. Files in level 1 only depend on files in level 0, files in level 2 on files in - # levels 1 and 0, etc. Files within a level are ordered alphabetically. - # Level 0 - - src/idma_axi_lite_read.sv - - src/idma_axi_lite_write.sv - - src/idma_axi_read.sv - - src/idma_axi_write.sv - - src/idma_obi_read.sv - - src/idma_obi_write.sv - - src/idma_tilelink_read.sv - - src/idma_tilelink_write.sv - - src/idma_init_read.sv - - src/idma_axi_stream_read.sv - - src/idma_axi_stream_write.sv - - src/idma_stream_fifo.sv - - src/idma_improved_fifo.sv - - src/idma_legalizer_page_splitter.sv - - src/idma_legalizer_pow2_splitter.sv - # Level 1 - - src/idma_dataflow_element.sv - - src/idma_error_handler.sv - - src/idma_channel_coupler.sv - - # Backends diff --git a/src/backend/src/idma_axi_read.sv b/src/backend/idma_axi_read.sv similarity index 95% rename from src/backend/src/idma_axi_read.sv rename to src/backend/idma_axi_read.sv index 8b130d61..8eb36751 100644 --- a/src/backend/src/idma_axi_read.sv +++ b/src/backend/idma_axi_read.sv @@ -1,8 +1,10 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti `include "common_cells/registers.svh" @@ -55,9 +57,9 @@ module idma_axi_read #( output logic ar_ready_o, /// AXI4+ATOP read manager port request - output read_req_t read_req_o, + output read_req_t read_req_o, /// AXI4+ATOP read manager port response - input read_rsp_t read_rsp_i, + input read_rsp_t read_rsp_i, /// Response channel valid and ready output logic r_chan_ready_o, @@ -167,7 +169,7 @@ module idma_axi_read #( // once valid data is applied, it can be pushed in all the selected (mask_in) buffers // be sure the response channel is ready - assign in_valid = read_rsp_i.r_valid & in_ready & r_dp_ready_i; + assign in_valid = read_rsp_i.r_valid & in_ready & r_dp_ready_i; assign buffer_in_valid_o = in_valid ? mask_in : '0; // r_dp_ready_o is triggered by the last element arriving from the read @@ -190,15 +192,15 @@ module idma_axi_read #( // Unused AXI signals //-------------------------------------- assign read_req_o.aw_valid = 1'b0; - assign read_req_o.w_valid = 1'b0; - assign read_req_o.b_ready = 1'b0; + assign read_req_o.w_valid = 1'b0; + assign read_req_o.b_ready = 1'b0; assign read_req_o.aw = '0; - assign read_req_o.w = '0; + assign read_req_o.w = '0; //-------------------------------------- // State //-------------------------------------- `FF(first_r_q, first_r_d, '1, clk_i, rst_ni) -endmodule : idma_axi_read +endmodule diff --git a/src/backend/src/idma_axi_write.sv b/src/backend/idma_axi_write.sv similarity index 95% rename from src/backend/src/idma_axi_write.sv rename to src/backend/idma_axi_write.sv index d50bc8c9..cc8a925c 100644 --- a/src/backend/src/idma_axi_write.sv +++ b/src/backend/idma_axi_write.sv @@ -1,8 +1,10 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti `include "common_cells/registers.svh" @@ -180,8 +182,8 @@ module idma_axi_write #( // always_comb process implements masking of invalid data always_comb begin : proc_mask // defaults - write_req_o.w.data = '0; - write_req_o.w.strb = '0; + write_req_o.w.data = '0; + write_req_o.w.strb = '0; buffer_data_masked = '0; // control the write to the bus apply data to the bus only if data should be written if (ready_to_write == 1'b1 & !dp_poison_i) begin @@ -200,8 +202,8 @@ module idma_axi_write #( // not used signal assign buffer_data_masked = '0; // simpler: direct connection - assign write_req_o.w.data = buffer_out_i; - assign write_req_o.w.strb = dp_poison_i ? '0 : mask_out; + assign write_req_o.w.data = buffer_out_i; + assign write_req_o.w.strb = dp_poison_i ? '0 : mask_out; end // the w last signal should only be applied to the bus if an actual transfer happens @@ -214,11 +216,11 @@ module idma_axi_write #( always_comb begin : proc_write_control // defaults: // beat counter - w_num_beats_d = w_num_beats_q; - w_cnt_valid_d = w_cnt_valid_q; + w_num_beats_d = w_num_beats_q; + w_cnt_valid_d = w_cnt_valid_q; // mask control - first_w = 1'b0; - last_w = 1'b0; + first_w = 1'b0; + last_w = 1'b0; // differentiate between the burst and non-burst case. If a transfer // consists just of one beat the counters are disabled @@ -279,10 +281,9 @@ module idma_axi_write #( //-------------------------------------- // Unused AXI signals //-------------------------------------- + assign write_req_o.ar = '0; assign write_req_o.ar_valid = 1'b0; - assign write_req_o.r_ready = 1'b0; - - assign write_req_o.ar = '0; + assign write_req_o.r_ready = 1'b0; //-------------------------------------- // State @@ -290,4 +291,4 @@ module idma_axi_write #( `FF(w_cnt_valid_q, w_cnt_valid_d, '0, clk_i, rst_ni) `FF(w_num_beats_q, w_num_beats_d, '0, clk_i, rst_ni) -endmodule : idma_axi_write +endmodule diff --git a/src/backend/src/idma_axi_lite_read.sv b/src/backend/idma_axil_read.sv similarity index 91% rename from src/backend/src/idma_axi_lite_read.sv rename to src/backend/idma_axil_read.sv index c6815cb4..2d7a231b 100644 --- a/src/backend/src/idma_axi_lite_read.sv +++ b/src/backend/idma_axil_read.sv @@ -1,11 +1,13 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti /// Implementing the AXI Lite read task in the iDMA transport layer. -module idma_axi_lite_read #( +module idma_axil_read #( /// Stobe width parameter int unsigned StrbWidth = 32'd16, @@ -48,9 +50,9 @@ module idma_axi_lite_read #( output logic ar_ready_o, /// AXI Lite read manager port request - output read_req_t read_req_o, + output read_req_t read_req_o, /// AXI Lite read manager port response - input read_rsp_t read_rsp_i, + input read_rsp_t read_rsp_i, /// Response channel valid and ready output logic r_chan_ready_o, @@ -119,7 +121,7 @@ module idma_axi_lite_read #( // once valid data is applied, it can be pushed in all the selected (mask_in) buffers // be sure the response channel is ready - assign in_valid = read_rsp_i.r_valid & in_ready & r_dp_ready_i; + assign in_valid = read_rsp_i.r_valid & in_ready & r_dp_ready_i; assign buffer_in_valid_o = in_valid ? mask_in : '0; // r_dp_ready_o is triggered by the last element arriving from the read @@ -131,8 +133,7 @@ module idma_axi_lite_read #( assign r_dp_rsp_o.first = 1'b1; // r_dp_valid_o is triggered once the last element is here or an error occurs - assign r_dp_valid_o = read_rsp_i.r_valid & in_ready; - + assign r_dp_valid_o = read_rsp_i.r_valid & in_ready; assign r_chan_ready_o = read_req_o.r_ready; assign r_chan_valid_o = read_rsp_i.r_valid; @@ -140,10 +141,10 @@ module idma_axi_lite_read #( // Unused AXI Lite signals //-------------------------------------- assign read_req_o.aw_valid = 1'b0; - assign read_req_o.w_valid = 1'b0; - assign read_req_o.b_ready = 1'b0; + assign read_req_o.w_valid = 1'b0; + assign read_req_o.b_ready = 1'b0; assign read_req_o.aw = '0; - assign read_req_o.w = '0; + assign read_req_o.w = '0; -endmodule : idma_axi_lite_read +endmodule diff --git a/src/backend/src/idma_axi_lite_write.sv b/src/backend/idma_axil_write.sv similarity index 94% rename from src/backend/src/idma_axi_lite_write.sv rename to src/backend/idma_axil_write.sv index ee73469b..25465390 100644 --- a/src/backend/src/idma_axi_lite_write.sv +++ b/src/backend/idma_axil_write.sv @@ -1,11 +1,13 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti /// Implementing the AXI Lite write task in the iDMA transport layer. -module idma_axi_lite_write #( +module idma_axil_write #( /// Stobe width parameter int unsigned StrbWidth = 32'd16, /// Mask invalid data on the manager interface @@ -99,7 +101,6 @@ module idma_axi_lite_write #( assign mask_out = ('1 << w_dp_req_i.offset) & ((w_dp_req_i.tailer != '0) ? ('1 >> (StrbWidth - w_dp_req_i.tailer)) : '1); - //-------------------------------------- // Write control //-------------------------------------- @@ -133,8 +134,8 @@ module idma_axi_lite_write #( // always_comb process implements masking of invalid data always_comb begin : proc_mask // defaults - write_req_o.w.data = '0; - write_req_o.w.strb = '0; + write_req_o.w.data = '0; + write_req_o.w.strb = '0; buffer_data_masked = '0; // control the write to the bus apply data to the bus only if data should be written if (ready_to_write == 1'b1 & !dp_poison_i) begin @@ -153,14 +154,13 @@ module idma_axi_lite_write #( // not used signal assign buffer_data_masked = '0; // simpler: direct connection - assign write_req_o.w.data = buffer_out_i; - assign write_req_o.w.strb = dp_poison_i ? '0 : mask_out; + assign write_req_o.w.data = buffer_out_i; + assign write_req_o.w.strb = dp_poison_i ? '0 : mask_out; end // we are ready for the next transfer internally, once the w last signal is applied assign w_dp_ready_o = write_happening; - //-------------------------------------- // Write response //-------------------------------------- @@ -174,13 +174,11 @@ module idma_axi_lite_write #( // write responses assign write_req_o.b_ready = w_dp_ready_i; - //-------------------------------------- // Unused AXI Lite signals //-------------------------------------- + assign write_req_o.ar = '0; assign write_req_o.ar_valid = 1'b0; - assign write_req_o.r_ready = 1'b0; - - assign write_req_o.ar = '0; + assign write_req_o.r_ready = 1'b0; -endmodule : idma_axi_lite_write +endmodule diff --git a/src/backend/src/idma_axi_stream_read.sv b/src/backend/idma_axis_read.sv similarity index 92% rename from src/backend/src/idma_axi_stream_read.sv rename to src/backend/idma_axis_read.sv index dc4aa607..62735300 100644 --- a/src/backend/src/idma_axi_stream_read.sv +++ b/src/backend/idma_axis_read.sv @@ -1,11 +1,13 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti /// Implementing the AXI Stream read task in the iDMA transport layer. -module idma_axi_stream_read #( +module idma_axis_read #( /// Stobe width parameter int unsigned StrbWidth = 32'd16, @@ -48,9 +50,9 @@ module idma_axi_stream_read #( output logic read_meta_ready_o, /// AXI Stream read manager port request - output read_req_t read_req_o, + output read_req_t read_req_o, /// AXI Stream read manager port response - input read_rsp_t read_rsp_i, + input read_rsp_t read_rsp_i, /// Response channel valid and ready output logic r_chan_ready_o, @@ -117,14 +119,13 @@ module idma_axi_stream_read #( // once valid data is applied, it can be pushed in all the selected (mask_in) buffers // be sure the response channel is ready - assign in_valid = read_rsp_i.tvalid & in_ready & r_dp_rsp_ready_i; + assign in_valid = read_rsp_i.tvalid & in_ready & r_dp_rsp_ready_i; assign buffer_in_valid_o = in_valid ? mask_in : '0; // r_dp_ready_o is triggered by the last element arriving from the read assign r_dp_req_ready_o = r_dp_req_valid_i & r_dp_rsp_ready_i & read_rsp_i.tvalid & in_ready; - - assign r_chan_ready_o = read_req_o.tready; - assign r_chan_valid_o = read_rsp_i.tvalid; + assign r_chan_ready_o = read_req_o.tready; + assign r_chan_valid_o = read_rsp_i.tvalid; // connect r_dp response payload assign r_dp_rsp_o.resp = '0; @@ -134,4 +135,4 @@ module idma_axi_stream_read #( // r_dp_valid_o is triggered once the last element is here or an error occurs assign r_dp_rsp_valid_o = read_rsp_i.tvalid & in_ready; -endmodule : idma_axi_stream_read +endmodule diff --git a/src/backend/src/idma_axi_stream_write.sv b/src/backend/idma_axis_write.sv similarity index 96% rename from src/backend/src/idma_axi_stream_write.sv rename to src/backend/idma_axis_write.sv index afe868ff..f8e1aacf 100644 --- a/src/backend/src/idma_axi_stream_write.sv +++ b/src/backend/idma_axis_write.sv @@ -1,11 +1,13 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti /// Implementing the AXI Stream write task in the iDMA transport layer. -module idma_axi_stream_write #( +module idma_axis_write #( /// Stobe width parameter int unsigned StrbWidth = 32'd16, /// Mask invalid data on the manager interface @@ -29,7 +31,7 @@ module idma_axi_stream_write #( parameter type w_dp_rsp_t = logic, /// AXI 4 `AW` channel type parameter type write_meta_channel_t = logic -) ( +) ( /// Clock input logic clk_i, /// Asynchronous reset, active low @@ -122,7 +124,7 @@ module idma_axi_stream_write #( // always_comb process implements masking of invalid data always_comb begin : proc_mask // defaults - write_req_o.t = aw_req_i.axi_stream.t_chan; + write_req_o.t = aw_req_i.axi_stream.t_chan; buffer_data_masked = '0; // control the write to the bus apply data to the bus only if data should be written if (ready_to_write == 1'b1 & !dp_poison_i) begin @@ -148,7 +150,7 @@ module idma_axi_stream_write #( // we are ready for the next transfer internally, once the w last signal is applied assign w_dp_req_ready_o = write_happening; - assign aw_ready_o = write_happening; + assign aw_ready_o = write_happening; //-------------------------------------- // Write response @@ -170,4 +172,5 @@ module idma_axi_stream_write #( .valid_o ( { w_dp_rsp_valid_o, write_req_o.tvalid } ), .ready_i ( { w_dp_rsp_ready_i, write_rsp_i.tready } ) ); -endmodule : idma_axi_stream_write + +endmodule diff --git a/src/backend/src/idma_channel_coupler.sv b/src/backend/idma_channel_coupler.sv similarity index 97% rename from src/backend/src/idma_channel_coupler.sv rename to src/backend/idma_channel_coupler.sv index 24f99f26..96d68f63 100644 --- a/src/backend/src/idma_channel_coupler.sv +++ b/src/backend/idma_channel_coupler.sv @@ -1,8 +1,9 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz + +// Authors: +// - Thomas Benz `include "common_cells/registers.svh" `include "axi/typedef.svh" @@ -120,7 +121,7 @@ module idma_channel_coupler #( assign aw_req_in.decoupled = aw_decouple_aw_i; // aw payload is just connected to fifo - assign aw_req_o = aw_req_out.aw; + assign aw_req_o = aw_req_out.aw; // use a credit counter to keep track of AWs to send always_comb begin : proc_credit_cnt @@ -129,7 +130,7 @@ module idma_channel_coupler #( aw_to_send_d = aw_to_send_q; // if we bypass the logic - aw_sent = aw_req_out.decoupled & aw_valid; + aw_sent = aw_req_out.decoupled & aw_valid; // first is asserted and aw is ready -> just send AW out // without changing the credit counter value @@ -177,4 +178,4 @@ module idma_channel_coupler #( `FF(aw_to_send_q, aw_to_send_d, '0, clk_i, rst_ni) -endmodule : idma_channel_coupler +endmodule diff --git a/src/backend/src/idma_dataflow_element.sv b/src/backend/idma_dataflow_element.sv similarity index 73% rename from src/backend/src/idma_dataflow_element.sv rename to src/backend/idma_dataflow_element.sv index c48dc047..cd90bd94 100644 --- a/src/backend/src/idma_dataflow_element.sv +++ b/src/backend/idma_dataflow_element.sv @@ -1,9 +1,10 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti /// A byte-granular buffer holding data while it is copied. module idma_dataflow_element #( @@ -41,15 +42,14 @@ module idma_dataflow_element #( .clk_i, .rst_ni, .testmode_i, - .flush_i ( 1'b0 ), - .data_i ( data_i [i] ), - .valid_i ( valid_i [i] ), - .ready_o ( ready_o [i] ), - .data_o ( data_o [i] ), - .valid_o ( valid_o [i] ), - .ready_i ( ready_i [i] ) + .flush_i ( 1'b0 ), + .data_i ( data_i [i] ), + .valid_i ( valid_i [i] ), + .ready_o ( ready_o [i] ), + .data_o ( data_o [i] ), + .valid_o ( valid_o [i] ), + .ready_i ( ready_i [i] ) ); end : gen_fifo_buffer -endmodule : idma_dataflow_element - +endmodule diff --git a/src/backend/src/idma_error_handler.sv b/src/backend/idma_error_handler.sv similarity index 92% rename from src/backend/src/idma_error_handler.sv rename to src/backend/idma_error_handler.sv index ec911876..3ef9f586 100644 --- a/src/backend/src/idma_error_handler.sv +++ b/src/backend/idma_error_handler.sv @@ -1,8 +1,9 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz + +// Authors: +// - Thomas Benz `include "common_cells/registers.svh" `include "common_cells/assertions.svh" @@ -55,13 +56,13 @@ module idma_error_handler #( input logic req_ready_i, /// The current read address (burst address) injected into the datapath - input addr_t r_addr_i, + input addr_t r_addr_i, /// The address is consumed by the datapath - input logic r_consume_i, + input logic r_consume_i, /// The current write address (burst address) injected into the datapath - input addr_t w_addr_i, + input addr_t w_addr_i, /// The address is consumed by the datapath - input logic w_consume_i, + input logic w_consume_i, /// Invalidate the current burst transfer, stops emission of requests output logic legalizer_flush_o, @@ -230,9 +231,9 @@ module idma_error_handler #( // a proper write response (lowest priority) if (w_dp_rsp_i.resp == axi_pkg::RESP_OKAY & w_dp_valid_i & w_last_burst_i) begin - rsp_o = '0; - rsp_o.last = w_super_last_i; - rsp_valid_o = 1'b1; + rsp_o = '0; + rsp_o.last = w_super_last_i; + rsp_valid_o = 1'b1; //rb_out_ready = 1'b1; // pop buffer end @@ -250,9 +251,9 @@ module idma_error_handler #( r_dp_ready_o = 1'b0; // go to one of the wait states if (w_last_burst_i) begin - state_d = WAIT_LAST_W; + state_d = WAIT_LAST_W; end else begin - state_d = WAIT; + state_d = WAIT; end end @@ -279,8 +280,8 @@ module idma_error_handler #( if (eh_valid_i) begin // continue case (~error reporting) if (eh_i == idma_pkg::CONTINUE) begin - eh_ready_o = 1'b1; - state_d = IDLE; + eh_ready_o = 1'b1; + state_d = IDLE; end // abort if (eh_i == idma_pkg::ABORT) begin @@ -289,13 +290,13 @@ module idma_error_handler #( // - some transfers might complete properly so no flush allowed! // in this case just continue if (num_outst_q > 'd1) begin - eh_ready_o = 1'b1; - state_d = IDLE; + eh_ready_o = 1'b1; + state_d = IDLE; // we are aborting a long transfer (it is still in the legalizer and // therefore the only active transfer in the datapath) end else if (num_outst_q == 'd1) begin - eh_ready_o = 1'b1; - state_d = LEG_FLUSH; + eh_ready_o = 1'b1; + state_d = LEG_FLUSH; // the counter is 0 -> no transfer in the datapath. This is an impossible // state end else begin @@ -312,7 +313,7 @@ module idma_error_handler #( WAIT_LAST_W : begin // continue case (~error reporting) if (eh_i == idma_pkg::CONTINUE) begin - eh_ready_o = 1'b1; + eh_ready_o = 1'b1; state_d = EMIT_EXTRA_RSP; end // abort @@ -322,13 +323,13 @@ module idma_error_handler #( // - some transfers might complete properly so no flush allowed! // in this case just continue if (num_outst_q > 'd1) begin - eh_ready_o = 1'b1; - state_d = EMIT_EXTRA_RSP; + eh_ready_o = 1'b1; + state_d = EMIT_EXTRA_RSP; // we are aborting a long transfer (it is still in the legalizer and // therefore the only active transfer in the datapath) end else if (num_outst_q == 'd1) begin - eh_ready_o = 1'b1; - state_d = LEG_FLUSH; + eh_ready_o = 1'b1; + state_d = LEG_FLUSH; // the counter is 0 -> no transfer in the datapath. This is an impossible // state end else begin @@ -356,8 +357,8 @@ module idma_error_handler #( r_dp_ready_o = 1'b1; // once the datapath is idle return to idle if (!dp_busy_i) begin - state_d = EMIT_EXTRA_RSP; - legalizer_kill_o = 1'b1; + state_d = EMIT_EXTRA_RSP; + legalizer_kill_o = 1'b1; end end @@ -380,4 +381,4 @@ module idma_error_handler #( `FF(state_q, state_d, IDLE, clk_i, rst_ni) `FF(num_outst_q, num_outst_d, '0, clk_i, rst_ni) -endmodule : idma_error_handler +endmodule diff --git a/src/backend/src/idma_init_read.sv b/src/backend/idma_init_read.sv similarity index 92% rename from src/backend/src/idma_init_read.sv rename to src/backend/idma_init_read.sv index 3674d76d..65f7df95 100644 --- a/src/backend/src/idma_init_read.sv +++ b/src/backend/idma_init_read.sv @@ -1,8 +1,10 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti /// Implementing the INIT read task in the iDMA transport layer. module idma_init_read #( @@ -48,9 +50,9 @@ module idma_init_read #( output logic read_meta_ready_o, /// INIT read manager port request - output read_req_t read_req_o, + output read_req_t read_req_o, /// INIT read manager port response - input read_rsp_t read_rsp_i, + input read_rsp_t read_rsp_i, /// Response channel valid and ready output logic r_chan_ready_o, @@ -78,7 +80,7 @@ module idma_init_read #( //-------------------------------------- // Read meta channel //-------------------------------------- - // connect the ar requests to the AXI bus + // connect the ar requests to the INIT read bus assign read_req_o.req_chan = read_meta_req_i.init.req_chan; assign read_req_o.req_valid = read_meta_valid_i; assign read_meta_ready_o = read_rsp_i.req_ready; @@ -119,12 +121,11 @@ module idma_init_read #( // once valid data is applied, it can be pushed in all the selected (mask_in) buffers // be sure the response channel is ready - assign in_valid = read_rsp_i.rsp_valid & in_ready & r_dp_ready_i; + assign in_valid = read_rsp_i.rsp_valid & in_ready & r_dp_ready_i; assign buffer_in_valid_o = in_valid ? mask_in : '0; // r_dp_ready_o is triggered by the last element arriving from the read - assign r_dp_ready_o = r_dp_valid_i & r_dp_ready_i & read_rsp_i.rsp_valid & in_ready; - + assign r_dp_ready_o = r_dp_valid_i & r_dp_ready_i & read_rsp_i.rsp_valid & in_ready; assign r_chan_ready_o = read_req_o.rsp_ready; assign r_chan_valid_o = read_rsp_i.rsp_valid; @@ -136,4 +137,4 @@ module idma_init_read #( // r_dp_valid_o is triggered once the last element is here or an error occurs assign r_dp_valid_o = read_rsp_i.rsp_valid & in_ready; -endmodule : idma_init_read +endmodule diff --git a/src/backend/src/idma_obi_read.sv b/src/backend/idma_obi_read.sv similarity index 93% rename from src/backend/src/idma_obi_read.sv rename to src/backend/idma_obi_read.sv index 8d6a9f6f..2c7a60ab 100644 --- a/src/backend/src/idma_obi_read.sv +++ b/src/backend/idma_obi_read.sv @@ -1,8 +1,10 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti /// Implementing the OBI read task in the iDMA transport layer. module idma_obi_read #( @@ -48,9 +50,9 @@ module idma_obi_read #( output logic read_meta_ready_o, /// OBI read manager port request - output read_req_t read_req_o, + output read_req_t read_req_o, /// OBI read manager port response - input read_rsp_t read_rsp_i, + input read_rsp_t read_rsp_i, /// Response channel valid and ready output logic r_chan_ready_o, @@ -119,12 +121,11 @@ module idma_obi_read #( // once valid data is applied, it can be pushed in all the selected (mask_in) buffers // be sure the response channel is ready - assign in_valid = read_rsp_i.r_valid & in_ready & r_dp_ready_i; + assign in_valid = read_rsp_i.r_valid & in_ready & r_dp_ready_i; assign buffer_in_valid_o = in_valid ? mask_in : '0; // r_dp_ready_o is triggered by the last element arriving from the read - assign r_dp_ready_o = r_dp_valid_i & r_dp_ready_i & read_rsp_i.r_valid & in_ready; - + assign r_dp_ready_o = r_dp_valid_i & r_dp_ready_i & read_rsp_i.r_valid & in_ready; assign r_chan_ready_o = read_req_o.r_ready; assign r_chan_valid_o = read_rsp_i.r_valid; @@ -136,4 +137,4 @@ module idma_obi_read #( // r_dp_valid_o is triggered once the last element is here or an error occurs assign r_dp_valid_o = read_rsp_i.r_valid & in_ready; -endmodule : idma_obi_read +endmodule diff --git a/src/backend/src/idma_obi_write.sv b/src/backend/idma_obi_write.sv similarity index 97% rename from src/backend/src/idma_obi_write.sv rename to src/backend/idma_obi_write.sv index 2ae4123d..2e2e7250 100644 --- a/src/backend/src/idma_obi_write.sv +++ b/src/backend/idma_obi_write.sv @@ -1,8 +1,10 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti /// Implementing the OBI write task in the iDMA transport layer. module idma_obi_write #( @@ -145,7 +147,7 @@ module idma_obi_write #( // we are ready for the next transfer internally, once the w last signal is applied assign w_dp_ready_o = write_happening; - assign aw_ready_o = write_happening; + assign aw_ready_o = write_happening; //-------------------------------------- // Write response @@ -160,4 +162,4 @@ module idma_obi_write #( // write responses assign write_req_o.r_ready = w_dp_ready_i; -endmodule : idma_obi_write +endmodule diff --git a/src/backend/src/idma_tilelink_read.sv b/src/backend/idma_tilelink_read.sv similarity index 96% rename from src/backend/src/idma_tilelink_read.sv rename to src/backend/idma_tilelink_read.sv index 1327f7be..e37bd707 100644 --- a/src/backend/src/idma_tilelink_read.sv +++ b/src/backend/idma_tilelink_read.sv @@ -1,8 +1,10 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti `include "common_cells/registers.svh" @@ -57,9 +59,9 @@ module idma_tilelink_read #( output logic read_meta_ready_o, /// TileLink read manager port request - output read_req_t read_req_o, + output read_req_t read_req_o, /// TileLink read manager port response - input read_rsp_t read_rsp_i, + input read_rsp_t read_rsp_i, /// Response channel valid and ready output logic r_chan_ready_o, @@ -154,14 +156,14 @@ module idma_tilelink_read #( // Read control //-------------------------------------- // controls the next state of the read flag - + assign last = (!first_r_q && (counter_r_q == 'd2)) | r_dp_req_i.is_single; - + always_comb begin : proc_first_read // Default first_r_d = first_r_q; counter_r_d = counter_r_q; - + // Check for response handshake if (read_rsp_i.d_valid && read_req_o.d_ready) begin if (last) begin @@ -179,7 +181,7 @@ module idma_tilelink_read #( counter_r_d = counter_r_q - 'd1; end end - end + end end // the buffer can be pushed to if all the masked FIFO buffers (mask_in) are ready. @@ -189,7 +191,7 @@ module idma_tilelink_read #( // once valid data is applied, it can be pushed in all the selected (mask_in) buffers // be sure the response channel is ready - assign in_valid = read_rsp_i.d_valid & in_ready & r_dp_ready_i; + assign in_valid = read_rsp_i.d_valid & in_ready & r_dp_ready_i; assign buffer_in_valid_o = in_valid ? mask_in : '0; // r_dp_ready_o is triggered by the last element arriving from the read @@ -214,4 +216,4 @@ module idma_tilelink_read #( `FF(first_r_q, first_r_d, '1, clk_i, rst_ni) `FF(counter_r_q, counter_r_d, '0, clk_i, rst_ni) -endmodule : idma_tilelink_read +endmodule diff --git a/src/backend/src/idma_tilelink_write.sv b/src/backend/idma_tilelink_write.sv similarity index 94% rename from src/backend/src/idma_tilelink_write.sv rename to src/backend/idma_tilelink_write.sv index aa9fb13d..ec5ac017 100644 --- a/src/backend/src/idma_tilelink_write.sv +++ b/src/backend/idma_tilelink_write.sv @@ -1,8 +1,10 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti `include "common_cells/registers.svh" @@ -97,8 +99,8 @@ module idma_tilelink_write #( logic write_happening; // A temporary signal required to write the output of the buffer to before assigning it to - // the TileLink bus. This is required to be compatible with some of the Questasim Versions and some - // of the parametrizations (e.g. DataWidth = 16) + // the TileLink bus. This is required to be compatible with some of the Questasim Versions and + // some of the parametrizations (e.g. DataWidth = 16) data_t buffer_data_masked; // we require a counter to hold the current beat in the write burst @@ -147,8 +149,8 @@ module idma_tilelink_write #( // Once buffer contains a full line -> all FIFOs are non-empty push it out. // all elements needed (defined by the mask) are in the buffer and the buffer is non-empty - assign ready_to_write = write_meta_valid_i & w_dp_valid_i & ((buffer_out_valid_i & mask_out) == mask_out) - & (buffer_out_valid_i != '0); + assign ready_to_write = write_meta_valid_i & w_dp_valid_i + & ((buffer_out_valid_i & mask_out) == mask_out) & (buffer_out_valid_i != '0); // data needed by the first mask is available in the buffer -> r_first happened for sure // this signal can be high during a transfer as well, it needs to be masked @@ -192,8 +194,8 @@ module idma_tilelink_write #( // not used signal assign buffer_data_masked = '0; // simpler: direct connection - assign write_req_o.a.data = buffer_out_i; - assign write_req_o.a.mask = dp_poison_i ? '0 : mask_out; + assign write_req_o.a.data = buffer_out_i; + assign write_req_o.a.mask = dp_poison_i ? '0 : mask_out; end // the w last signal should only be applied to the bus if an actual transfer happens @@ -207,11 +209,11 @@ module idma_tilelink_write #( always_comb begin : proc_write_control // defaults: // beat counter - w_num_beats_d = w_num_beats_q; - w_cnt_valid_d = w_cnt_valid_q; + w_num_beats_d = w_num_beats_q; + w_cnt_valid_d = w_cnt_valid_q; // mask control - first_w = 1'b0; - last_w = 1'b0; + first_w = 1'b0; + last_w = 1'b0; // differentiate between the burst and non-burst case. If a transfer // consists just of one beat the counters are disabled @@ -268,4 +270,4 @@ module idma_tilelink_write #( `FF(w_cnt_valid_q, w_cnt_valid_d, '0, clk_i, rst_ni) `FF(w_num_beats_q, w_num_beats_d, '0, clk_i, rst_ni) -endmodule : idma_tilelink_write +endmodule diff --git a/src/backend/src/idma_buffer.sv b/src/backend/src/idma_buffer.sv deleted file mode 100644 index c3eadeea..00000000 --- a/src/backend/src/idma_buffer.sv +++ /dev/null @@ -1,54 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz - -/// A byte-granular buffer holding data while it is copied. -module idma_buffer #( - /// The depth of the buffer - parameter int unsigned BufferDepth = 32'd3, - /// The width of the buffer in bytes - parameter int unsigned StrbWidth = 32'd1, - /// Print the info of the FIFO configuration - parameter bit PrintFifoInfo = 1'b0, - /// The strobe type - parameter type strb_t = logic, - /// The byte type - parameter type byte_t = logic [7:0] -)( - input logic clk_i, - input logic rst_ni, - input logic testmode_i, - - input byte_t [StrbWidth-1:0] data_i, - input strb_t valid_i, - output strb_t ready_o, - - output byte_t [StrbWidth-1:0] data_o, - output strb_t valid_o, - input strb_t ready_i -); - - // buffer is implemented as an array of stream FIFOs - for (genvar i = 0; i < StrbWidth; i++) begin : gen_fifo_buffer - idma_stream_fifo #( - .type_t ( byte_t ), - .Depth ( BufferDepth ), - .PrintInfo ( PrintFifoInfo ) - ) i_byte_buffer ( - .clk_i, - .rst_ni, - .testmode_i, - .flush_i ( 1'b0 ), - .usage_o ( /* NOT CONNECTED */ ), - .data_i ( data_i [i] ), - .valid_i ( valid_i [i] ), - .ready_o ( ready_o [i] ), - .data_o ( data_o [i] ), - .valid_o ( valid_o [i] ), - .ready_i ( ready_i [i] ) - ); - end : gen_fifo_buffer - -endmodule : idma_buffer diff --git a/src/backend/src/idma_legalizer.sv.tpl b/src/backend/src/idma_legalizer.sv.tpl deleted file mode 100644 index cd168ee0..00000000 --- a/src/backend/src/idma_legalizer.sv.tpl +++ /dev/null @@ -1,1027 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz -// Tobias Senti - -`include "common_cells/registers.svh" -`include "common_cells/assertions.svh" -`include "idma/guard.svh" - -/// Legalizes a generic 1D transfer according to the rules given by the -/// used protocol. -module idma_legalizer${name_uniqueifier} #( - /// Data width - parameter int unsigned DataWidth = 32'd16, - /// Address width - parameter int unsigned AddrWidth = 32'd24, - /// 1D iDMA request type: - /// - `length`: the length of the transfer in bytes - /// - `*_addr`: the source / target byte addresses of the transfer - /// - `opt`: the options field - parameter type idma_req_t = logic, - /// Read request type - parameter type idma_r_req_t = logic, - /// Write request type - parameter type idma_w_req_t = logic, - /// Mutable transfer type - parameter type idma_mut_tf_t = logic, - /// Mutable options type - parameter type idma_mut_tf_opt_t = logic -)( - /// Clock - input logic clk_i, - /// Asynchronous reset, active low - input logic rst_ni, - - /// 1D request - input idma_req_t req_i, - /// 1D request valid - input logic valid_i, - /// 1D request ready - output logic ready_o, - - /// Read request; contains datapath and meta information - output idma_r_req_t r_req_o, - /// Read request valid - output logic r_valid_o, - /// Read request ready - input logic r_ready_i, - - /// Write request; contains datapath and meta information - output idma_w_req_t w_req_o, - /// Write request valid - output logic w_valid_o, - /// Write request ready - input logic w_ready_i, - - /// Invalidate the current burst transfer, stops emission of requests - input logic flush_i, - /// Kill the active 1D transfer; reload a new transfer - input logic kill_i, - - /// Read machine of the legalizer is busy - output logic r_busy_o, - /// Write machine of the legalizer is busy - output logic w_busy_o -); -% if len(used_protocols) != 1: - function int unsigned max_size(input int unsigned a, b); - return a > b ? a : b; - endfunction - -% endif - /// Stobe width - localparam int unsigned StrbWidth = DataWidth / 8; - /// Offset width - localparam int unsigned OffsetWidth = $clog2(StrbWidth); - /// The size of a page in byte - localparam int unsigned PageSize = \ -% if len(used_protocols) == 1: - % if database[used_protocols[0]]['bursts'] == 'not_supported': -StrbWidth; - % elif database[used_protocols[0]]['bursts'] == 'only_pow2': -${database[used_protocols[0]]['page_size']}; - % elif database[used_protocols[0]]['bursts'] == 'split_at_page_boundary': -${database[used_read_protocols[0]]['max_beats_per_burst']} * StrbWidth > ${database[used_protocols[0]]['page_size']}\ - ? ${database[used_protocols[0]]['page_size']} : ${database[used_read_protocols[0]]['max_beats_per_burst']} * StrbWidth; - % endif -% else: - % for index, p in enumerate(used_protocols): - % if index < len(used_protocols)-1: -max_size(\ - % if database[p]['bursts'] == 'not_supported': -StrbWidth\ - % elif database[p]['bursts'] == 'only_pow2': -${database[p]['page_size']}\ - % elif database[p]['bursts'] == 'split_at_page_boundary': -${database[p]['max_beats_per_burst']} * StrbWidth > ${database[p]['page_size']}\ - ? ${database[p]['page_size']} : ${database[p]['max_beats_per_burst']} * StrbWidth\ - % endif -, \ - % else: - % if database[p]['bursts'] == 'not_supported': -StrbWidth\ - % elif database[p]['bursts'] == 'only_pow2': -${database[p]['page_size']}\ - % elif database[p]['bursts'] == 'split_at_page_boundary': -${database[p]['max_beats_per_burst']} * StrbWidth > ${database[p]['page_size']}\ - ? ${database[p]['page_size']} : ${database[p]['max_beats_per_burst']} * StrbWidth\ - % endif - % endif - % endfor - % for i in range(0, len(used_protocols)-1): -)\ - % endfor -; -% endif - /// The width of page offset byte addresses - localparam int unsigned PageAddrWidth = $clog2(PageSize); - - /// Offset type - typedef logic [ OffsetWidth-1:0] offset_t; - /// Address type - typedef logic [ AddrWidth-1:0] addr_t; - /// Page address type - typedef logic [PageAddrWidth-1:0] page_addr_t; - /// Page length type - typedef logic [ PageAddrWidth:0] page_len_t; - - - // state: internally hold one transfer, this is mutated - idma_mut_tf_t r_tf_d, r_tf_q; - idma_mut_tf_t w_tf_d, w_tf_q; - idma_mut_tf_opt_t opt_tf_d, opt_tf_q; - - // enable signals for next mutable transfer storage - logic r_tf_ena; - logic w_tf_ena; - - // page boundaries - page_len_t r_num_bytes_to_pb; - page_len_t w_num_bytes_to_pb; - page_len_t c_num_bytes_to_pb; - - // read process - page_len_t r_num_bytes_possible; - page_len_t r_num_bytes; - offset_t r_addr_offset; - logic r_done; - - // write process - page_len_t w_num_bytes_possible; - page_len_t w_num_bytes; - offset_t w_addr_offset; - logic w_done; - - - //-------------------------------------- - // read boundary check - //-------------------------------------- -% if one_read_port: - % if database[used_read_protocols[0]]['bursts'] == 'not_supported': - idma_legalizer_page_splitter #( - .OffsetWidth ( OffsetWidth ), - .PageAddrWidth ( PageSize ), - .addr_t ( addr_t ), - .page_len_t ( page_len_t ), - .page_addr_t ( page_addr_t ) - ) i_read_page_splitter ( - .not_bursting_i ( 1'b1 ), - - .reduce_len_i ( opt_tf_q.src_reduce_len ), - .max_llen_i ( opt_tf_q.src_max_llen ), - - .addr_i ( r_tf_q.addr ), - .num_bytes_to_pb_o ( r_num_bytes_to_pb ) - ); - % elif database[used_read_protocols[0]]['bursts'] == 'split_at_page_boundary': - idma_legalizer_page_splitter #( - .OffsetWidth ( OffsetWidth ), - .PageAddrWidth ( $clog2((${database[used_read_protocols[0]]['max_beats_per_burst']} * StrbWidth\ - > ${database[used_read_protocols[0]]['page_size']}) ?\ - ${database[used_read_protocols[0]]['page_size']} :\ - ${database[used_read_protocols[0]]['max_beats_per_burst']} * StrbWidth) ), - .addr_t ( addr_t ), - .page_len_t ( page_len_t ), - .page_addr_t ( page_addr_t ) - ) i_read_page_splitter ( - .not_bursting_i ( 1'b0 ), - .reduce_len_i ( opt_tf_q.src_reduce_len ), - .max_llen_i ( opt_tf_q.src_max_llen ), - - .addr_i ( r_tf_q.addr ), - .num_bytes_to_pb_o ( r_num_bytes_to_pb ) - ); - % elif database[used_read_protocols[0]]['bursts'] == 'only_pow2': - idma_legalizer_pow2_splitter #( - .PageAddrWidth ( $clog2(${database[used_read_protocols[0]]['page_size']}) ), - .OffsetWidth ( OffsetWidth ), - .addr_t ( addr_t ), - .len_t ( page_len_t ) - ) i_read_pow2_splitter ( - .addr_i ( r_tf_q.addr ), - .length_i ( \ -% if database[used_read_protocols[0]]['tltoaxi4_compatibility_mode'] == "true": -|r_tf_q.length[$bits(r_tf_q.length)-1:PageAddrWidth] ? page_len_t'('d${database[used_read_protocols[0]]['page_size']} - r_tf_q.addr[PageAddrWidth-1:0]) : r_tf_q.length[PageAddrWidth:0] ), - .length_larger_i ( 1'b0 ), -% else: -r_tf_q.length[PageAddrWidth:0] ), - .length_larger_i ( |r_tf_q.length[$bits(r_tf_q.length)-1:PageAddrWidth+1] ), -% endif - .bytes_to_transfer_o ( r_num_bytes_to_pb ) - ); - % else: - `IDMA_NONSYNTH_BLOCK( - initial begin - $fatal(1, "bursts value '${database[used_read_protocols[0]]['bursts']}' for read protocol ${database[used_read_protocols[0]]['full_name']} not implemented in template!"); - end - ) - assign r_page_addr_width = '0; - % endif -% elif no_read_bursting: - idma_legalizer_page_splitter #( - .OffsetWidth ( OffsetWidth ), - .PageAddrWidth ( PageSize ), - .addr_t ( addr_t ), - .page_len_t ( page_len_t ), - .page_addr_t ( page_addr_t ) - ) i_read_page_splitter ( - .not_bursting_i ( 1'b1 ), - - .reduce_len_i ( opt_tf_q.src_reduce_len ), - .max_llen_i ( opt_tf_q.src_max_llen ), - - .addr_i ( r_tf_q.addr ), - .num_bytes_to_pb_o ( r_num_bytes_to_pb ) - ); -% else: - idma_legalizer_page_splitter #( - .OffsetWidth ( OffsetWidth ), - .PageAddrWidth ( PageSize ), - .addr_t ( addr_t ), - .page_len_t ( page_len_t ), - .page_addr_t ( page_addr_t ) - ) i_read_page_splitter ( - .not_bursting_i ( opt_tf_q.src_protocol inside {\ - % for index, protocol in enumerate(used_non_bursting_read_protocols): - idma_pkg::${database[protocol]['protocol_enum']}\ - % if index != len(used_non_bursting_read_protocols)-1: -,\ - % endif - % endfor -} ), - - .reduce_len_i ( opt_tf_q.src_reduce_len ), - .max_llen_i ( opt_tf_q.src_max_llen ), - - .addr_i ( r_tf_q.addr ), - .num_bytes_to_pb_o ( r_num_bytes_to_pb ) - ); -% endif - - //-------------------------------------- - // write boundary check - //-------------------------------------- -% if one_write_port: - % if database[used_write_protocols[0]]['bursts'] == 'not_supported': - idma_legalizer_page_splitter #( - .OffsetWidth ( OffsetWidth ), - .PageAddrWidth ( PageSize ), - .addr_t ( addr_t ), - .page_len_t ( page_len_t ), - .page_addr_t ( page_addr_t ) - ) i_write_page_splitter ( - .not_bursting_i ( 1'b1 ), - - .reduce_len_i ( opt_tf_q.dst_reduce_len ), - .max_llen_i ( opt_tf_q.dst_max_llen ), - - .addr_i ( w_tf_q.addr ), - .num_bytes_to_pb_o ( w_num_bytes_to_pb ) - ); - % elif database[used_write_protocols[0]]['bursts'] == 'split_at_page_boundary': - idma_legalizer_page_splitter #( - .OffsetWidth ( OffsetWidth ), - .PageAddrWidth ( $clog2((${database[used_write_protocols[0]]['max_beats_per_burst']} * StrbWidth\ - > ${database[used_write_protocols[0]]['page_size']}) ?\ - ${database[used_write_protocols[0]]['page_size']} :\ - ${database[used_write_protocols[0]]['max_beats_per_burst']} * StrbWidth) ), - .addr_t ( addr_t ), - .page_len_t ( page_len_t ), - .page_addr_t ( page_addr_t ) - ) i_write_page_splitter ( - .not_bursting_i ( 1'b0 ), - .reduce_len_i ( opt_tf_q.dst_reduce_len ), - .max_llen_i ( opt_tf_q.dst_max_llen ), - - .addr_i ( w_tf_q.addr ), - .num_bytes_to_pb_o ( w_num_bytes_to_pb ) - ); - % elif database[used_write_protocols[0]]['bursts'] == 'only_pow2': - idma_legalizer_pow2_splitter #( - .PageAddrWidth ( \ -% if database[used_write_protocols[0]]['tltoaxi4_compatibility_mode'] == "true": -$clog2((32 * StrbWidth) > ${database[used_write_protocols[0]]['page_size']} ? ${database[used_write_protocols[0]]['page_size']} : (32 * StrbWidth)) ), -% else: -$clog2(${database[used_write_protocols[0]]['page_size']}) ), -% endif - .OffsetWidth ( OffsetWidth ), - .addr_t ( addr_t ), - .len_t ( page_len_t ) - ) i_write_pow2_splitter ( - .addr_i ( w_tf_q.addr ), - .length_i ( \ -% if database[used_write_protocols[0]]['tltoaxi4_compatibility_mode'] == "true": -|w_tf_q.length[$bits(w_tf_q.length)-1:PageAddrWidth] ? page_len_t'('d${database[used_write_protocols[0]]['page_size']} - w_tf_q.addr[PageAddrWidth-1:0]) : w_tf_q.length[PageAddrWidth:0] ), - .length_larger_i ( 1'b0 ), -% else: -w_tf_q.length[PageAddrWidth:0] ), - .length_larger_i ( |w_tf_q.length[$bits(w_tf_q.length)-1:PageAddrWidth+1] ), -% endif - .bytes_to_transfer_o ( w_num_bytes_to_pb ) - ); - % else: - `IDMA_NONSYNTH_BLOCK( - initial begin - $fatal(1, "bursts value '${database[used_write_protocols[0]]['bursts']}' for write protocol ${database[used_write_protocols[0]]['full_name']} not implemented in template!"); - end - ) - assign w_page_addr_width = '0; - % endif -% elif no_write_bursting: - idma_legalizer_page_splitter #( - .OffsetWidth ( OffsetWidth ), - .PageAddrWidth ( PageSize ), - .addr_t ( addr_t ), - .page_len_t ( page_len_t ), - .page_addr_t ( page_addr_t ) - ) i_write_page_splitter ( - .not_bursting_i ( 1'b1 ), - - .reduce_len_i ( opt_tf_q.dst_reduce_len ), - .max_llen_i ( opt_tf_q.dst_max_llen ), - - .addr_i ( w_tf_q.addr ), - .num_bytes_to_pb_o ( w_num_bytes_to_pb ) - ); -% else: - idma_legalizer_page_splitter #( - .OffsetWidth ( OffsetWidth ), - .PageAddrWidth ( PageSize ), - .addr_t ( addr_t ), - .page_len_t ( page_len_t ), - .page_addr_t ( page_addr_t ) - ) i_write_page_splitter ( - .not_bursting_i ( opt_tf_q.dst_protocol inside {\ - % for index, protocol in enumerate(used_non_bursting_write_protocols): - idma_pkg::${database[protocol]['protocol_enum']}\ - % if index != len(used_non_bursting_write_protocols)-1: -,\ - % endif - % endfor -} ), - - .reduce_len_i ( opt_tf_q.dst_reduce_len ), - .max_llen_i ( opt_tf_q.dst_max_llen ), - - .addr_i ( w_tf_q.addr ), - .num_bytes_to_pb_o ( w_num_bytes_to_pb ) - ); -% endif - - //-------------------------------------- - // page boundary check - //-------------------------------------- - // how many transfers are remaining when concerning both r/w pages? - // take the boundary that is closer - assign c_num_bytes_to_pb = (r_num_bytes_to_pb > w_num_bytes_to_pb) ? - w_num_bytes_to_pb : r_num_bytes_to_pb; - - - //-------------------------------------- - // Synchronized R/W process - //-------------------------------------- -% if one_read_port and one_write_port: - % if (no_read_bursting or no_write_bursting) or ('tilelink' in used_protocols): - assign r_num_bytes_possible = r_num_bytes_to_pb; - assign w_num_bytes_possible = w_num_bytes_to_pb; - % else: - assign r_num_bytes_possible = opt_tf_q.decouple_rw ? - r_num_bytes_to_pb : c_num_bytes_to_pb; - assign w_num_bytes_possible = opt_tf_q.decouple_rw ? - w_num_bytes_to_pb : c_num_bytes_to_pb; - % endif -% else: - % if no_read_bursting and no_write_bursting: - // No Bursting at all - assign r_num_bytes_possible = opt_tf_q.decouple_rw ? - r_num_bytes_to_pb : c_num_bytes_to_pb; - assign w_num_bytes_possible = opt_tf_q.decouple_rw ? - w_num_bytes_to_pb : c_num_bytes_to_pb; - % elif no_read_bursting and (not no_write_bursting): - // Only write bursts possible - assign r_num_bytes_possible = r_num_bytes_to_pb; - assign w_num_bytes_possible = (opt_tf_q.decouple_rw || (opt_tf_q.dst_protocol inside {\ - % for index, protocol in enumerate(used_non_bursting_write_protocols): - idma_pkg::${database[protocol]['protocol_enum']}\ - % if index != len(used_non_bursting_write_protocols)-1: -,\ - % endif - % endfor - })) ? - w_num_bytes_to_pb : c_num_bytes_to_pb; - % elif (not no_read_bursting) and no_write_bursting: - // Only read bursts possible - assign w_num_bytes_possible = w_num_bytes_to_pb; - assign r_num_bytes_possible = (opt_tf_q.decouple_rw || (opt_tf_q.src_protocol inside {\ - % for index, protocol in enumerate(used_non_bursting_read_protocols): - idma_pkg::${database[protocol]['protocol_enum']}\ - % if index != len(used_non_bursting_read_protocols)-1: -,\ - % endif - % endfor - })) ? - r_num_bytes_to_pb : c_num_bytes_to_pb; - % else: - // Both read and write bursts possible - always_comb begin - r_num_bytes_possible = c_num_bytes_to_pb; - w_num_bytes_possible = c_num_bytes_to_pb; - - if ( opt_tf_q.decouple_rw\ - % if len(used_non_bursting_read_protocols) != 0: - - || (opt_tf_q.src_protocol inside {\ - % for index, protocol in enumerate(used_non_bursting_read_protocols): - idma_pkg::${database[protocol]['protocol_enum']}\ - % if index != len(used_non_bursting_read_protocols)-1: -,\ - % endif - % endfor - })\ - % endif - % if len(used_non_bursting_write_protocols) != 0: - - || (opt_tf_q.dst_protocol inside {\ - % for index, protocol in enumerate(used_non_bursting_write_protocols): - idma_pkg::${database[protocol]['protocol_enum']}\ - % if index != len(used_non_bursting_write_protocols)-1: -,\ - % endif - % endfor - })\ - % endif - - ) begin - r_num_bytes_possible = r_num_bytes_to_pb; - w_num_bytes_possible = w_num_bytes_to_pb; - end - end - % endif -% endif - - assign r_addr_offset = r_tf_q.addr[OffsetWidth-1:0]; - assign w_addr_offset = w_tf_q.addr[OffsetWidth-1:0]; - - // legalization process -> read and write is coupled together - always_comb begin : proc_read_write_transaction - - // default: keep state - r_tf_d = r_tf_q; - w_tf_d = w_tf_q; - opt_tf_d = opt_tf_q; - - // default: not done - r_done = 1'b0; - w_done = 1'b0; - - //-------------------------------------- - // Legalize read transaction - //-------------------------------------- - // more bytes remaining than we can read - if (r_tf_q.length > r_num_bytes_possible) begin - r_num_bytes = r_num_bytes_possible; - // calculate remainder - r_tf_d.length = r_tf_q.length - r_num_bytes_possible; - // next address - r_tf_d.addr = r_tf_q.addr + r_num_bytes; - - // remaining bytes fit in one burst - end else begin - r_num_bytes = r_tf_q.length[PageAddrWidth:0]; - // finished - r_tf_d.valid = 1'b0; - r_done = 1'b1; - end - - //-------------------------------------- - // Legalize write transaction - //-------------------------------------- - // more bytes remaining than we can write - if (w_tf_q.length > w_num_bytes_possible) begin - w_num_bytes = w_num_bytes_possible; - // calculate remainder - w_tf_d.length = w_tf_q.length - w_num_bytes_possible; - // next address - w_tf_d.addr = w_tf_q.addr + w_num_bytes; - - // remaining bytes fit in one burst - end else begin - w_num_bytes = w_tf_q.length[PageAddrWidth:0]; - // finished - w_tf_d.valid = 1'b0; - w_done = 1'b1; - end - - //-------------------------------------- - // Kill - //-------------------------------------- - if (kill_i) begin - // kill the current state - r_tf_d = '0; - r_done = 1'b1; - w_tf_d = '0; - w_done = 1'b1; - end - - //-------------------------------------- - // Refill - //-------------------------------------- - // new request is taken in if both r and w machines are ready. - if (ready_o & valid_i) begin - - // load all three mutable objects (source, destination, option) - // source or read - r_tf_d = '{ - length: req_i.length, - addr: req_i.src_addr, - valid: 1'b1, - base_addr: req_i.src_addr - }; - // destination or write - w_tf_d = '{ - length: req_i.length, - addr: req_i.dst_addr, - valid: 1'b1, - base_addr: req_i.dst_addr - }; - // options - opt_tf_d = '{ - src_protocol: req_i.opt.src_protocol, - dst_protocol: req_i.opt.dst_protocol, -% if combined_shifter: - read_shift: req_i.src_addr[OffsetWidth-1:0] - req_i.dst_addr[OffsetWidth-1:0], - write_shift: '0, -% else: - read_shift: req_i.src_addr[OffsetWidth-1:0], - write_shift: - req_i.dst_addr[OffsetWidth-1:0], -% endif - decouple_rw: req_i.opt.beo.decouple_rw, - decouple_aw: req_i.opt.beo.decouple_aw, - src_max_llen: req_i.opt.beo.src_max_llen, - dst_max_llen: req_i.opt.beo.dst_max_llen, - src_reduce_len: req_i.opt.beo.src_reduce_len, - dst_reduce_len: req_i.opt.beo.dst_reduce_len, - axi_id: req_i.opt.axi_id, - src_axi_opt: req_i.opt.src, - dst_axi_opt: req_i.opt.dst, - super_last: req_i.opt.last - }; - end - end - - - //-------------------------------------- - // Connect outputs - //-------------------------------------- -% if one_read_port: - % if 'axi' in used_read_protocols: - assign r_req_o.ar_req.axi.ar_chan = '{ - id: opt_tf_q.axi_id, - addr: { r_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - len: ((r_num_bytes + r_addr_offset - 'd1) >> OffsetWidth), - size: axi_pkg::size_t'(OffsetWidth), - burst: opt_tf_q.src_axi_opt.burst, - lock: opt_tf_q.src_axi_opt.lock, - cache: opt_tf_q.src_axi_opt.cache, - prot: opt_tf_q.src_axi_opt.prot, - qos: opt_tf_q.src_axi_opt.qos, - region: opt_tf_q.src_axi_opt.region, - user: '0 - }; - % elif 'axi_lite' in used_read_protocols: - assign r_req_o.ar_req.axi_lite.ar_chan = '{ - addr: { r_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - prot: opt_tf_q.src_axi_opt.prot - }; - % elif 'obi' in used_read_protocols: - assign r_req_o.ar_req.obi.a_chan = '{ - addr: { r_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - be: '1, - we: 1'b0, - wdata: '0, - aid: opt_tf_q.axi_id - }; - % elif 'tilelink' in used_read_protocols: - always_comb begin - r_req_o.ar_req.tilelink.a_chan.size = '0; - for (int i = 0; i <= PageAddrWidth; i++) begin - if ((1 << i) == r_num_bytes) begin - r_req_o.ar_req.tilelink.a_chan.size = i; - end - end - r_req_o.ar_req.tilelink.a_chan.opcode = 3'd4; - r_req_o.ar_req.tilelink.a_chan.param = 3'd0; - r_req_o.ar_req.tilelink.a_chan.source = opt_tf_q.axi_id; - r_req_o.ar_req.tilelink.a_chan.address = { r_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }; - r_req_o.ar_req.tilelink.a_chan.mask = '1; - r_req_o.ar_req.tilelink.a_chan.data = '0; - r_req_o.ar_req.tilelink.a_chan.corrupt = 1'b0; - end - % elif 'init' in used_read_protocols: - assign r_req_o.ar_req.init.req_chan = '{ - cfg: r_tf_q.base_addr - }; - % elif 'axi_stream' in used_read_protocols: - assign r_req_o.ar_req = '0; - % else: - `IDMA_NONSYNTH_BLOCK( - initial begin - $fatal(1, "One Read Port not implemented for ${used_read_protocols[0]}"); - end - ) - % endif -% else: - always_comb begin : gen_read_meta_channel - r_req_o.ar_req = '0; - case(opt_tf_q.src_protocol) - % if 'axi' in used_read_protocols: - idma_pkg::AXI: - r_req_o.ar_req.axi.ar_chan = '{ - id: opt_tf_q.axi_id, - addr: { r_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - len: ((r_num_bytes + r_addr_offset - 'd1) >> OffsetWidth), - size: axi_pkg::size_t'(OffsetWidth), - burst: opt_tf_q.src_axi_opt.burst, - lock: opt_tf_q.src_axi_opt.lock, - cache: opt_tf_q.src_axi_opt.cache, - prot: opt_tf_q.src_axi_opt.prot, - qos: opt_tf_q.src_axi_opt.qos, - region: opt_tf_q.src_axi_opt.region, - user: '0 - }; - % endif - % if 'axi_lite' in used_read_protocols: - idma_pkg::AXI_LITE: - r_req_o.ar_req.axi_lite.ar_chan = '{ - addr: { r_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - prot: opt_tf_q.src_axi_opt.prot - }; - % endif - % if 'obi' in used_read_protocols: - idma_pkg::OBI: - r_req_o.ar_req.obi.a_chan = '{ - addr: { r_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - be: '1, - we: 1'b0, - wdata: '0, - aid: opt_tf_q.axi_id - }; - % endif - % if 'tilelink' in used_read_protocols: - idma_pkg::TILELINK: - r_req_o.ar_req.tilelink.a_chan = '{ - opcode: 3'd4, - param: 3'd0, - size: OffsetWidth, - source: opt_tf_q.axi_id, - address: { r_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - mask: '1, - data: '0, - corrupt: 1'b0 - }; - % endif - % if 'init' in used_read_protocols: - idma_pkg::INIT: - r_req_o.ar_req.init.req_chan = '{\ - cfg: r_tf_q.base_addr - }; - % endif - default: - r_req_o.ar_req = '0; - endcase - end -% endif - -% if one_write_port: - % if 'axi' in used_write_protocols: - assign w_req_o.aw_req.axi.aw_chan = '{ - id: opt_tf_q.axi_id, - addr: { w_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - len: ((w_num_bytes + w_addr_offset - 'd1) >> OffsetWidth), - size: axi_pkg::size_t'(OffsetWidth), - burst: opt_tf_q.dst_axi_opt.burst, - lock: opt_tf_q.dst_axi_opt.lock, - cache: opt_tf_q.dst_axi_opt.cache, - prot: opt_tf_q.dst_axi_opt.prot, - qos: opt_tf_q.dst_axi_opt.qos, - region: opt_tf_q.dst_axi_opt.region, - user: '0, - atop: '0 - }; - assign w_req_o.w_dp_req = '{ - dst_protocol: opt_tf_q.dst_protocol, - offset: w_addr_offset, - tailer: OffsetWidth'(w_num_bytes + w_addr_offset), - shift: opt_tf_q.write_shift, - num_beats: w_req_o.aw_req.axi.aw_chan.len, - is_single: w_req_o.aw_req.axi.aw_chan.len == '0 - }; - % elif 'axi_lite' in used_write_protocols: - assign w_req_o.aw_req.axi_lite.aw_chan = '{ - addr: { w_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - prot: opt_tf_q.dst_axi_opt.prot - }; - - assign w_req_o.w_dp_req = '{ - dst_protocol: opt_tf_q.dst_protocol, - offset: w_addr_offset, - tailer: OffsetWidth'(w_num_bytes + w_addr_offset), - shift: opt_tf_q.write_shift, - num_beats: 'd0, - is_single: 1'b1 - }; - % elif 'obi' in used_write_protocols: - assign w_req_o.aw_req.obi.a_chan = '{ - addr: { w_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - be: '0, - we: 1, - wdata: '0, - aid: opt_tf_q.axi_id - }; - - assign w_req_o.w_dp_req = '{ - dst_protocol: opt_tf_q.dst_protocol, - offset: w_addr_offset, - tailer: OffsetWidth'(w_num_bytes + w_addr_offset), - shift: opt_tf_q.write_shift, - num_beats: 'd0, - is_single: 1'b1 - }; - % elif 'tilelink' in used_write_protocols: - always_comb begin - w_req_o.aw_req.tilelink.a_chan.size = '0; - for (int i = 0; i < PageAddrWidth; i++) begin - if ((1 << i) == w_num_bytes) begin - w_req_o.aw_req.tilelink.a_chan.size = i; - end - end - w_req_o.aw_req.tilelink.a_chan.opcode = 3'd1; - w_req_o.aw_req.tilelink.a_chan.param = 3'd0; - w_req_o.aw_req.tilelink.a_chan.source = opt_tf_q.axi_id; - w_req_o.aw_req.tilelink.a_chan.address = { w_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }; - w_req_o.aw_req.tilelink.a_chan.mask = '0; - w_req_o.aw_req.tilelink.a_chan.data = '0; - w_req_o.aw_req.tilelink.a_chan.corrupt = 1'b0; - end - - assign w_req_o.w_dp_req = '{ - dst_protocol: opt_tf_q.dst_protocol, - offset: w_addr_offset, - tailer: OffsetWidth'(w_num_bytes + w_addr_offset), - shift: opt_tf_q.write_shift, - num_beats: 'd0, - is_single: w_num_bytes <= StrbWidth - }; - % elif 'axi_stream' in used_write_protocols: - assign w_req_o.aw_req.axi_stream.t_chan = '{ - data: '0, - strb: '1, - keep: '0, - last: w_tf_q.length == w_num_bytes, - id: opt_tf_q.axi_id, - dest: w_tf_q.base_addr[$bits(w_req_o.aw_req.axi_stream.t_chan.dest)-1:0], - user: w_tf_q.base_addr[$bits(w_req_o.aw_req.axi_stream.t_chan.user)-1+:$bits(w_req_o.aw_req.axi_stream.t_chan.dest)] - }; - - assign w_req_o.w_dp_req = '{ - dst_protocol: opt_tf_q.dst_protocol, - offset: w_addr_offset, - tailer: OffsetWidth'(w_num_bytes + w_addr_offset), - shift: opt_tf_q.write_shift, - num_beats: 'd0, - is_single: 1'b1 - }; - % else: - `IDMA_NONSYNTH_BLOCK( - initial begin - $fatal(1, "Single write protocol not implemented!"); - end - ) - % endif -% else: - always_comb begin : gen_write_meta_channel - w_req_o.aw_req = '0; - case(opt_tf_q.dst_protocol) - % if 'axi' in used_write_protocols: - idma_pkg::AXI: - w_req_o.aw_req.axi.aw_chan = '{ - id: opt_tf_q.axi_id, - addr: { w_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - len: ((w_num_bytes + w_addr_offset - 'd1) >> OffsetWidth), - size: axi_pkg::size_t'(OffsetWidth), - burst: opt_tf_q.dst_axi_opt.burst, - lock: opt_tf_q.dst_axi_opt.lock, - cache: opt_tf_q.dst_axi_opt.cache, - prot: opt_tf_q.dst_axi_opt.prot, - qos: opt_tf_q.dst_axi_opt.qos, - region: opt_tf_q.dst_axi_opt.region, - user: '0, - atop: '0 - }; - % endif - % if 'axi_lite' in used_write_protocols: - idma_pkg::AXI_LITE: - w_req_o.aw_req.axi_lite.aw_chan = '{ - addr: { w_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - prot: opt_tf_q.dst_axi_opt.prot - }; - % endif - % if 'obi' in used_write_protocols: - idma_pkg::OBI: - w_req_o.aw_req.obi.a_chan = '{ - addr: { w_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - be: '0, - we: 1, - wdata: '0, - aid: opt_tf_q.axi_id - }; - % endif - % if 'tilelink' in used_write_protocols: - idma_pkg::TILELINK: - w_req_o.aw_req.tilelink.a_chan = '{ - opcode: 3'd1, - param: 3'd0, - size: OffsetWidth, - source: opt_tf_q.axi_id, - address: { w_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - mask: '0, - data: '0, - corrupt: 1'b0 - }; - % endif - % if 'axi_stream' in used_write_protocols: - idma_pkg::AXI_STREAM: - w_req_o.aw_req.axi_stream.t_chan = '{ - data: '0, - strb: '1, - keep: '0, - last: w_tf_q.length == w_num_bytes, - id: opt_tf_q.axi_id, - dest: w_tf_q.base_addr[$bits(w_req_o.aw_req.axi_stream.t_chan.dest)-1:0], - user: w_tf_q.base_addr[$bits(w_req_o.aw_req.axi_stream.t_chan.user)-1+:$bits(w_req_o.aw_req.axi_stream.t_chan.dest)] - }; - % endif - default: - w_req_o.aw_req = '0; - endcase - end - - // assign the signals needed to set-up the write data path - % if 'axi' in used_write_protocols: - always_comb begin : gen_write_data_path - if (opt_tf_q.dst_protocol == idma_pkg::AXI) begin - w_req_o.w_dp_req = '{ - dst_protocol: opt_tf_q.dst_protocol, - offset: w_addr_offset, - tailer: OffsetWidth'(w_num_bytes + w_addr_offset), - shift: opt_tf_q.write_shift, - num_beats: w_req_o.aw_req.axi.aw_chan.len, - is_single: w_req_o.aw_req.axi.aw_chan.len == '0 - }; - end else begin - w_req_o.w_dp_req = '{ - dst_protocol: opt_tf_q.dst_protocol, - offset: w_addr_offset, - tailer: OffsetWidth'(w_num_bytes + w_addr_offset), - shift: opt_tf_q.write_shift, - num_beats: 'd0, - is_single: 1'b1 - }; - end - end - % else: - assign w_req_o.w_dp_req = '{ - dst_protocol: opt_tf_q.dst_protocol, - offset: w_addr_offset, - tailer: OffsetWidth'(w_num_bytes + w_addr_offset), - shift: opt_tf_q.write_shift, - num_beats: 'd0, - is_single: 1'b1 - }; - % endif - -% endif - // assign the signals needed to set-up the read data path - assign r_req_o.r_dp_req = '{ - src_protocol: opt_tf_q.src_protocol, - offset: r_addr_offset, - tailer: OffsetWidth'(r_num_bytes + r_addr_offset), - shift: opt_tf_q.read_shift, - decouple_aw: opt_tf_q.decouple_aw, - is_single: r_num_bytes <= StrbWidth - }; - - // last burst in generic 1D transfer? - assign w_req_o.last = w_done; - - // last burst indicated by midend - assign w_req_o.super_last = opt_tf_q.super_last; - - // assign aw decouple flag - assign w_req_o.decouple_aw = opt_tf_q.decouple_aw; - - // busy output - assign r_busy_o = r_tf_q.valid; - assign w_busy_o = w_tf_q.valid; - - - //-------------------------------------- - // Flow Control - //-------------------------------------- - // only advance to next state if: - // * rw_coupled: both machines advance - // * rw_decoupled: either machine advances -% if one_read_port and one_write_port: - % if (no_read_bursting != no_write_bursting) or 'tilelink' in used_protocols: - always_comb begin : proc_legalizer_flow_control - //Onesided bursting -> decouple - r_tf_ena = (r_ready_i & !flush_i) | kill_i; - w_tf_ena = (w_ready_i & !flush_i) | kill_i; - - r_valid_o = r_tf_q.valid & r_ready_i & !flush_i; - w_valid_o = w_tf_q.valid & w_ready_i & !flush_i; - end - % else: - always_comb begin : proc_legalizer_flow_control - if ( opt_tf_q.decouple_rw ) begin - r_tf_ena = (r_ready_i & !flush_i) | kill_i; - w_tf_ena = (w_ready_i & !flush_i) | kill_i; - - r_valid_o = r_tf_q.valid & r_ready_i & !flush_i; - w_valid_o = w_tf_q.valid & w_ready_i & !flush_i; - end else begin - r_tf_ena = (r_ready_i & w_ready_i & !flush_i) | kill_i; - w_tf_ena = (r_ready_i & w_ready_i & !flush_i) | kill_i; - - r_valid_o = r_tf_q.valid & w_ready_i & r_ready_i & !flush_i; - w_valid_o = w_tf_q.valid & r_ready_i & w_ready_i & !flush_i; - end - end - % endif -% else: - always_comb begin : proc_legalizer_flow_control - if ( opt_tf_q.decouple_rw\ -% if (not one_read_port) or (not one_write_port): -% if len(used_non_bursting_read_protocols) != 0: - - || (opt_tf_q.src_protocol inside {\ - % for index, protocol in enumerate(used_non_bursting_read_protocols): - idma_pkg::${database[protocol]['protocol_enum']}\ - % if index != len(used_non_bursting_read_protocols)-1: -,\ - % endif - % endfor - })\ -% endif -% if len(used_non_bursting_write_protocols) != 0: - - || (opt_tf_q.dst_protocol inside {\ - % for index, protocol in enumerate(used_non_bursting_write_protocols): - idma_pkg::${database[protocol]['protocol_enum']}\ - % if index != len(used_non_bursting_write_protocols)-1: -,\ - % endif - % endfor - })\ -% endif -% endif - ) begin - r_tf_ena = (r_ready_i & !flush_i) | kill_i; - w_tf_ena = (w_ready_i & !flush_i) | kill_i; - - r_valid_o = r_tf_q.valid & r_ready_i & !flush_i; - w_valid_o = w_tf_q.valid & w_ready_i & !flush_i; - end else begin - r_tf_ena = (r_ready_i & w_ready_i & !flush_i) | kill_i; - w_tf_ena = (r_ready_i & w_ready_i & !flush_i) | kill_i; - - r_valid_o = r_tf_q.valid & w_ready_i & r_ready_i & !flush_i; - w_valid_o = w_tf_q.valid & r_ready_i & w_ready_i & !flush_i; - end - end -% endif - // load next idma request: if both machines are done! - assign ready_o = r_done & w_done & r_ready_i & w_ready_i & !flush_i; - - - //-------------------------------------- - // State - //-------------------------------------- - `FF(opt_tf_q, opt_tf_d, '0, clk_i, rst_ni) - `FFL(r_tf_q, r_tf_d, r_tf_ena, '0, clk_i, rst_ni) - `FFL(w_tf_q, w_tf_d, w_tf_ena, '0, clk_i, rst_ni) - - - //-------------------------------------- - // Assertions - //-------------------------------------- - // only support the decomposition of incremental bursts - `ASSERT_NEVER(OnlyIncrementalBurstsSRC, (ready_o & valid_i & - req_i.opt.src.burst != axi_pkg::BURST_INCR), clk_i, !rst_ni) - `ASSERT_NEVER(OnlyIncrementalBurstsDST, (ready_o & valid_i & - req_i.opt.dst.burst != axi_pkg::BURST_INCR), clk_i, !rst_ni) - -endmodule : idma_legalizer${name_uniqueifier} diff --git a/src/backend/src/idma_stream_fifo.sv b/src/backend/src/idma_stream_fifo.sv deleted file mode 100644 index 73f7d335..00000000 --- a/src/backend/src/idma_stream_fifo.sv +++ /dev/null @@ -1,128 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz - -`include "common_cells/assertions.svh" -`include "idma/guard.svh" - -/// Optimal implementation of a stream FIFO based on the common cells modules. -module idma_stream_fifo #( - /// Depth can be arbitrary from 2 to 2**32 - parameter int unsigned Depth = 32'd8, - /// Type of the FIFO - parameter type type_t = logic, - /// Print information when the simulation launches - parameter bit PrintInfo = 1'b0, - // DO NOT OVERWRITE THIS PARAMETER - parameter int unsigned AddrDepth = (Depth > 32'd1) ? $clog2(Depth) : 32'd1 -) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic flush_i, // flush the fifo - input logic testmode_i, // test_mode to bypass clock gating - output logic [AddrDepth-1:0] usage_o, // fill pointer - // input interface - input type_t data_i, // data to push into the fifo - input logic valid_i, // input data valid - output logic ready_o, // fifo is not full - // output interface - output type_t data_o, // output data - output logic valid_o, // fifo is not empty - input logic ready_i // pop head from fifo -); - - //-------------------------------------- - // Prevent Depth 0 and 1 - //-------------------------------------- - // Throw an error if depth is 0 or 1 - `IDMA_NONSYNTH_BLOCK( - if (Depth < 32'd2) begin : gen_fatal - initial begin - $fatal(1, "FIFO of depth %d does not make any sense!", Depth); - end - end - ) - - //-------------------------------------- - // Spill register (depth 2) - //-------------------------------------- - // Instantiate a spill register for depth 2 - if (Depth == 32'd2) begin : gen_spill - - // print info - `IDMA_NONSYNTH_BLOCK( - if (PrintInfo) begin : gen_info - initial begin - $display("[%m] Instantiate spill register (of depth %d)", Depth); - end - end - ) - - // spill register - spill_register_flushable #( - .T ( type_t ), - .Bypass ( 1'b0 ) - ) i_spill_register_flushable ( - .clk_i, - .rst_ni, - .flush_i, - .valid_i, - .ready_o, - .data_i, - .valid_o, - .ready_i, - .data_o - ); - - // usage is not supported - assign usage_o = 'x; - - // no full push - `ASSERT_NEVER(CheckFullPush, (!ready_o & valid_i), clk_i, !rst_ni) - // empty pop - `ASSERT_NEVER(CheckEmptyPop, (!valid_o & ready_i), clk_i, !rst_ni) - end - - - //-------------------------------------- - // FIFO register (depth 3+) - //-------------------------------------- - // default to stream fifo - if (Depth > 32'd2) begin : gen_fifo - - // print info - `IDMA_NONSYNTH_BLOCK( - if (PrintInfo) begin : gen_info - initial begin - $info("[%m] Instantiate stream FIFO of depth %d", Depth); - end - end - ) - - // stream fifo - stream_fifo #( - .DEPTH ( Depth ), - .T ( type_t ) - ) i_stream_fifo ( - .clk_i, - .rst_ni, - .flush_i, - .testmode_i, - .usage_o, - .data_i, - .valid_i, - .ready_o, - .data_o, - .valid_o, - .ready_i - ); - - // no full push - `ASSERT_NEVER(CheckFullPush, (!ready_o & valid_i), clk_i, !rst_ni) - // empty pop - `ASSERT_NEVER(CheckEmptyPop, (!valid_o & ready_i), clk_i, !rst_ni) - end - -endmodule : idma_stream_fifo diff --git a/src/backend/src/idma_backend.sv.tpl b/src/backend/tpl/idma_backend.sv.tpl similarity index 76% rename from src/backend/src/idma_backend.sv.tpl rename to src/backend/tpl/idma_backend.sv.tpl index eb5b4445..5d4a6dd8 100644 --- a/src/backend/src/idma_backend.sv.tpl +++ b/src/backend/tpl/idma_backend.sv.tpl @@ -1,60 +1,65 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti `include "axi/typedef.svh" `include "idma/guard.svh" /// The iDMA backend implements an arbitrary 1D copy engine -module idma_backend${name_uniqueifier} #( +module idma_backend_${name_uniqueifier} #( + /// Should both data shifts be done before the dataflow element? + /// If this is enabled, then the data inserted into the dataflow element + /// will no longer be word aligned, but only a single shifter is needed + parameter bit CombinedShifter = 1'b0, /// Data width - parameter int unsigned DataWidth = 32'd16, + parameter int unsigned DataWidth = 32'd16, /// Address width - parameter int unsigned AddrWidth = 32'd24, + parameter int unsigned AddrWidth = 32'd24, /// AXI user width - parameter int unsigned UserWidth = 32'd1, + parameter int unsigned UserWidth = 32'd1, /// AXI ID width - parameter int unsigned AxiIdWidth = 32'd1, + parameter int unsigned AxiIdWidth = 32'd1, /// Number of transaction that can be in-flight concurrently - parameter int unsigned NumAxInFlight = 32'd2, + parameter int unsigned NumAxInFlight = 32'd2, /// The depth of the internal reorder buffer: /// - '2': minimal possible configuration /// - '3': efficiently handle misaligned transfers (recommended) - parameter int unsigned BufferDepth = 32'd2, + parameter int unsigned BufferDepth = 32'd2, /// With of a transfer: max transfer size is `2**TFLenWidth` bytes - parameter int unsigned TFLenWidth = 32'd24, + parameter int unsigned TFLenWidth = 32'd24, /// The depth of the memory system the backend is attached to - parameter int unsigned MemSysDepth = 32'd0, + parameter int unsigned MemSysDepth = 32'd0, /// Should the `R`-`AW` coupling hardware be present? (recommended) - parameter bit RAWCouplingAvail = 1'b\ + parameter bit RAWCouplingAvail = 1'b\ % if one_read_port and one_write_port and ('axi' in used_read_protocols) and ('axi' in used_write_protocols): 1, % else: 0, %endif /// Mask invalid data on the manager interface - parameter bit MaskInvalidData = 1'b1, + parameter bit MaskInvalidData = 1'b1, /// Should hardware legalization be present? (recommended) /// If not, software legalization is required to ensure the transfers are /// AXI4-conformal - parameter bit HardwareLegalizer = 1'b1, + parameter bit HardwareLegalizer = 1'b1, /// Reject zero-length transfers - parameter bit RejectZeroTransfers = 1'b1, + parameter bit RejectZeroTransfers = 1'b1, /// Should the error handler be present? parameter idma_pkg::error_cap_e ErrorCap = idma_pkg::NO_ERROR_HANDLING, /// Print the info of the FIFO configuration - parameter bit PrintFifoInfo = 1'b0, + parameter bit PrintFifoInfo = 1'b0, /// 1D iDMA request type - parameter type idma_req_t = logic, + parameter type idma_req_t = logic, /// iDMA response type - parameter type idma_rsp_t = logic, + parameter type idma_rsp_t = logic, /// Error Handler request type - parameter type idma_eh_req_t = logic, + parameter type idma_eh_req_t = logic, /// iDMA busy signal - parameter type idma_busy_t = logic\ + parameter type idma_busy_t = logic\ % for protocol in used_protocols: , /// ${database[protocol]['full_name']} Request and Response channel type @@ -81,11 +86,11 @@ module idma_backend${name_uniqueifier} #( /// Address Write Channel type parameter type write_meta_channel_t = logic, /// Address Read Channel type - parameter type read_meta_channel_t = logic, + parameter type read_meta_channel_t = logic, /// Strobe Width (do not override!) - parameter int unsigned StrbWidth = DataWidth / 8, + parameter int unsigned StrbWidth = DataWidth / 8, /// Offset Width (do not override!) - parameter int unsigned OffsetWidth = $clog2(StrbWidth) + parameter int unsigned OffsetWidth = $clog2(StrbWidth) )( /// Clock input logic clk_i, @@ -274,10 +279,10 @@ _rsp_t ${protocol}_write_rsp_i, /// The mutable transfer type holds important information that is mutated by the /// `legalizer` block. typedef struct packed { - tf_len_t length; - addr_t addr; - logic valid; - addr_t base_addr; + tf_len_t length; + addr_t addr; + logic valid; + addr_t base_addr; } idma_mut_tf_t; @@ -308,7 +313,7 @@ _rsp_t ${protocol}_write_rsp_i, logic w_super_last; // Datapath FIFO signals -> used to decouple legalizer and datapath - logic r_dp_req_in_ready , w_dp_req_in_ready; + logic r_dp_req_in_ready, w_dp_req_in_ready; logic r_dp_req_out_valid, w_dp_req_out_valid; logic r_dp_req_out_ready, w_dp_req_out_ready; r_dp_req_t r_dp_req_out; @@ -321,8 +326,8 @@ _rsp_t ${protocol}_write_rsp_i, logic r_dp_rsp_ready, w_dp_rsp_ready; // Ax handshaking - logic ar_ready, ar_ready_dp; - logic aw_ready, aw_ready_dp; + logic ar_ready, ar_ready_dp; + logic aw_ready, aw_ready_dp; logic aw_valid_dp, ar_valid_dp; // Ax request from R-AW coupler to datapath @@ -397,30 +402,31 @@ _rsp_t ${protocol}_write_rsp_i, //-------------------------------------- if (HardwareLegalizer) begin : gen_hw_legalizer // hardware legalizer is present - idma_legalizer${name_uniqueifier} #( - .DataWidth ( DataWidth ), - .AddrWidth ( AddrWidth ), - .idma_req_t ( idma_req_t ), - .idma_r_req_t ( idma_r_req_t ), - .idma_w_req_t ( idma_w_req_t ), - .idma_mut_tf_t ( idma_mut_tf_t ), - .idma_mut_tf_opt_t ( idma_mut_tf_opt_t ) + idma_legalizer_${name_uniqueifier} #( + .CombinedShifter ( CombinedShifter ), + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .idma_req_t ( idma_req_t ), + .idma_r_req_t ( idma_r_req_t ), + .idma_w_req_t ( idma_w_req_t ), + .idma_mut_tf_t ( idma_mut_tf_t ), + .idma_mut_tf_opt_t ( idma_mut_tf_opt_t ) ) i_idma_legalizer ( - .clk_i, - .rst_ni, - .req_i ( idma_req_i ), - .valid_i ( req_valid ), - .ready_o ( req_ready_o ), - .r_req_o ( r_req ), - .w_req_o ( w_req ), - .r_valid_o ( r_valid ), - .w_valid_o ( w_valid ), - .r_ready_i ( r_ready ), - .w_ready_i ( w_ready ), - .flush_i ( legalizer_flush ), - .kill_i ( legalizer_kill ), - .r_busy_o ( busy_o.r_leg_busy ), - .w_busy_o ( busy_o.w_leg_busy ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( idma_req_i ), + .valid_i ( req_valid ), + .ready_o ( req_ready_o ), + .r_req_o ( r_req ), + .w_req_o ( w_req ), + .r_valid_o ( r_valid ), + .w_valid_o ( w_valid ), + .r_ready_i ( r_ready ), + .w_ready_i ( w_ready ), + .flush_i ( legalizer_flush ), + .kill_i ( legalizer_kill ), + .r_busy_o ( busy_o.r_leg_busy ), + .w_busy_o ( busy_o.w_leg_busy ) ); end else begin : gen_no_hw_legalizer @@ -429,8 +435,8 @@ _rsp_t ${protocol}_write_rsp_i, stream_fork #( .N_OUP ( 32'd2 ) ) i_stream_fork ( - .clk_i, - .rst_ni, + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .valid_i ( req_valid ), .ready_o ( req_ready_o ), .valid_o ( { r_valid, w_valid } ), @@ -442,68 +448,6 @@ _rsp_t ${protocol}_write_rsp_i, assign len = ((idma_req_i.length + idma_req_i.src_addr[OffsetWidth-1:0] - 'd1) >> OffsetWidth); - - // if (Protocol1 == idma_pkg::AXI) begin : gen_axi_ar_req - // // assemble AR request - // assign r_req.ar_req = '{ - // id: idma_req_i.opt.axi_id, - // addr: { idma_req_i.src_addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - // len: len, - // size: axi_pkg::size_t'(OffsetWidth), - // burst: idma_req_i.opt.src.burst, - // lock: idma_req_i.opt.src.lock, - // cache: idma_req_i.opt.src.cache, - // prot: idma_req_i.opt.src.prot, - // qos: idma_req_i.opt.src.qos, - // region: idma_req_i.opt.src.region, - // user: '0 - // }; - // end else if (Protocol1 == idma_pkg::AXI_LITE) begin : gen_axi_lite_ar_req - // // assemble AR request - // assign r_req.ar_req = '{ - // addr: { idma_req_i.src_addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - // prot: idma_req_i.opt.src.prot - // }; - // end else begin : gen_ar_req_error - // `IDMA_NONSYNTH_BLOCK( - // initial begin - // $fatal(1, "Backend: legalizer bypass ar req not implemented for requested ", - // "protocol!"); - // end - // ) - // end - - // if (Protocol2 == idma_pkg::AXI) begin : gen_axi_aw_req - // // assemble AW request - // assign w_req.aw_req = '{ - // id: idma_req_i.opt.axi_id, - // addr: { idma_req_i.dst_addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - // len: len, - // size: axi_pkg::size_t'(OffsetWidth), - // burst: idma_req_i.opt.dst.burst, - // lock: idma_req_i.opt.dst.lock, - // cache: idma_req_i.opt.dst.cache, - // prot: idma_req_i.opt.dst.prot, - // qos: idma_req_i.opt.dst.qos, - // region: idma_req_i.opt.dst.region, - // user: '0, - // atop: '0 - // }; - // end else if (Protocol2 == idma_pkg::AXI_LITE) begin : gen_axi_lite_aw_req - // // assemble AW request - // assign w_req.aw_req = '{ - // addr: { idma_req_i.dst_addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, - // prot: idma_req_i.opt.dst.prot - // }; - // end else begin : gen_aw_req_error - // `IDMA_NONSYNTH_BLOCK( - // initial begin - // $fatal(1, "Backend: legalizer bypass aw req not implemented for requested ", - // "protocol!"); - // end - // ) - // end - // assemble read datapath request assign r_req.r_dp_req = '{ offset: idma_req_i.src_addr[OffsetWidth-1:0], @@ -546,43 +490,43 @@ _rsp_t ${protocol}_write_rsp_i, if (ErrorCap == idma_pkg::ERROR_HANDLING) begin : gen_error_handler % if one_read_port and one_write_port and ('axi' in used_read_protocols) and ('axi' in used_write_protocols): idma_error_handler #( - .MetaFifoDepth ( MetaFifoDepth ), - .PrintFifoInfo ( PrintFifoInfo ), - .idma_rsp_t ( idma_rsp_t ), - .idma_eh_req_t ( idma_eh_req_t ), - .addr_t ( addr_t ), - .r_dp_rsp_t ( r_dp_rsp_t ), - .w_dp_rsp_t ( w_dp_rsp_t ) + .MetaFifoDepth ( MetaFifoDepth ), + .PrintFifoInfo ( PrintFifoInfo ), + .idma_rsp_t ( idma_rsp_t ), + .idma_eh_req_t ( idma_eh_req_t ), + .addr_t ( addr_t ), + .r_dp_rsp_t ( r_dp_rsp_t ), + .w_dp_rsp_t ( w_dp_rsp_t ) ) i_idma_error_handler ( - .clk_i, - .rst_ni, - .testmode_i, - .rsp_o ( idma_rsp ), - .rsp_valid_o ( rsp_valid ), - .rsp_ready_i ( rsp_ready ), - .req_valid_i ( req_valid ), - .req_ready_i ( req_ready_o ), - .eh_i ( idma_eh_req_i ), - .eh_valid_i ( eh_req_valid_i ), - .eh_ready_o ( eh_req_ready_o ), - .r_addr_i ( r_req.ar_req.axi.ar_chan.addr ), - .r_consume_i ( r_valid & r_ready ), - .w_addr_i ( w_req.aw_req.axi.aw_chan.addr ), - .w_consume_i ( w_valid & w_ready ), - .legalizer_flush_o ( legalizer_flush ), - .legalizer_kill_o ( legalizer_kill ), - .dp_busy_i ( dp_busy ), - .dp_poison_o ( dp_poison ), - .r_dp_rsp_i ( r_dp_rsp ), - .r_dp_valid_i ( r_dp_rsp_valid ), - .r_dp_ready_o ( r_dp_rsp_ready ), - .w_dp_rsp_i ( w_dp_rsp ), - .w_dp_valid_i ( w_dp_rsp_valid ), - .w_dp_ready_o ( w_dp_rsp_ready ), - .w_last_burst_i ( w_last_burst ), - .w_super_last_i ( w_super_last ), - .fsm_busy_o ( busy_o.eh_fsm_busy ), - .cnt_busy_o ( busy_o.eh_cnt_busy ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( testmode_i ), + .rsp_o ( idma_rsp ), + .rsp_valid_o ( rsp_valid ), + .rsp_ready_i ( rsp_ready ), + .req_valid_i ( req_valid ), + .req_ready_i ( req_ready_o ), + .eh_i ( idma_eh_req_i ), + .eh_valid_i ( eh_req_valid_i ), + .eh_ready_o ( eh_req_ready_o ), + .r_addr_i ( r_req.ar_req.axi.ar_chan.addr ), + .w_addr_i ( w_req.aw_req.axi.aw_chan.addr ), + .r_consume_i ( r_valid & r_ready ), + .w_consume_i ( w_valid & w_ready ), + .legalizer_flush_o ( legalizer_flush ), + .legalizer_kill_o ( legalizer_kill ), + .dp_busy_i ( dp_busy ), + .dp_poison_o ( dp_poison ), + .r_dp_rsp_i ( r_dp_rsp ), + .r_dp_valid_i ( r_dp_rsp_valid ), + .r_dp_ready_o ( r_dp_rsp_ready ), + .w_dp_rsp_i ( w_dp_rsp ), + .w_dp_valid_i ( w_dp_rsp_valid ), + .w_dp_ready_o ( w_dp_rsp_ready ), + .w_last_burst_i ( w_last_burst ), + .w_super_last_i ( w_super_last ), + .fsm_busy_o ( busy_o.eh_fsm_busy ), + .cnt_busy_o ( busy_o.eh_cnt_busy ) ); % else: `IDMA_NONSYNTH_BLOCK( @@ -627,39 +571,39 @@ _rsp_t ${protocol}_write_rsp_i, // Datapath decoupling //-------------------------------------- idma_stream_fifo #( - .Depth ( NumAxInFlight ), - .type_t ( r_dp_req_t ), - .PrintInfo ( PrintFifoInfo ) + .Depth ( NumAxInFlight ), + .type_t ( r_dp_req_t ), + .PrintInfo ( PrintFifoInfo ) ) i_r_dp_req ( - .clk_i, - .rst_ni, - .testmode_i, - .flush_i ( 1'b0 ), - .usage_o ( /* NOT CONNECTED */ ), - .data_i ( r_req.r_dp_req ), - .valid_i ( r_valid ), - .ready_o ( r_dp_req_in_ready ), - .data_o ( r_dp_req_out ), - .valid_o ( r_dp_req_out_valid ), - .ready_i ( r_dp_req_out_ready ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( testmode_i ), + .flush_i ( 1'b0 ), + .usage_o ( /* NOT CONNECTED */ ), + .data_i ( r_req.r_dp_req ), + .valid_i ( r_valid ), + .ready_o ( r_dp_req_in_ready ), + .data_o ( r_dp_req_out ), + .valid_o ( r_dp_req_out_valid ), + .ready_i ( r_dp_req_out_ready ) ); idma_stream_fifo #( - .Depth ( NumAxInFlight ), - .type_t ( w_dp_req_t ), - .PrintInfo ( PrintFifoInfo ) + .Depth ( NumAxInFlight ), + .type_t ( w_dp_req_t ), + .PrintInfo ( PrintFifoInfo ) ) i_w_dp_req ( - .clk_i, - .rst_ni, - .testmode_i, - .flush_i ( 1'b0 ), - .usage_o ( /* NOT CONNECTED */ ), - .data_i ( w_req.w_dp_req ), - .valid_i ( w_valid ), - .ready_o ( w_dp_req_in_ready ), - .data_o ( w_dp_req_out ), - .valid_o ( w_dp_req_out_valid ), - .ready_i ( w_dp_req_out_ready ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( testmode_i ), + .flush_i ( 1'b0 ), + .usage_o ( /* NOT CONNECTED */ ), + .data_i ( w_req.w_dp_req ), + .valid_i ( w_valid ), + .ready_o ( w_dp_req_in_ready ), + .data_o ( w_dp_req_out ), + .valid_o ( w_dp_req_out_valid ), + .ready_i ( w_dp_req_out_ready ) ); // Add fall-through register to allow the input to be ready if the output is not. This @@ -680,9 +624,9 @@ _rsp_t ${protocol}_write_rsp_i, % endif ) ) i_ar_fall_through_register ( - .clk_i, - .rst_ni, - .testmode_i, + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( testmode_i ), .clr_i ( 1'b0 ), .valid_i ( r_valid ), .ready_o ( ar_ready ), @@ -707,23 +651,23 @@ _rsp_t ${protocol}_write_rsp_i, .type_t ( logic [1:0] ), .PrintInfo ( PrintFifoInfo ) ) i_w_last ( - .clk_i, - .rst_ni, - .testmode_i, - .flush_i ( 1'b0 ), - .usage_o ( /* NOT CONNECTED */ ), - .data_i ( {w_req.super_last, w_req.last} ), - .valid_i ( w_valid & w_ready ), - .ready_o ( w_last_ready ), - .data_o ( {w_super_last, w_last_burst} ), - .valid_o ( /* NOT CONNECTED */ ), - .ready_i ( w_dp_rsp_valid & w_dp_rsp_ready ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( testmode_i ), + .flush_i ( 1'b0 ), + .usage_o ( /* NOT CONNECTED */ ), + .data_i ( {w_req.super_last, w_req.last} ), + .valid_i ( w_valid & w_ready ), + .ready_o ( w_last_ready ), + .data_o ( {w_super_last, w_last_burst} ), + .valid_o ( /* NOT CONNECTED */ ), + .ready_i ( w_dp_rsp_valid & w_dp_rsp_ready ) ); //-------------------------------------- // Transport Layer / Datapath //-------------------------------------- - idma_transport_layer${name_uniqueifier} #( + idma_transport_layer_${name_uniqueifier} #( .NumAxInFlight ( NumAxInFlight ), .DataWidth ( DataWidth ), .BufferDepth ( BufferDepth ), @@ -961,4 +905,4 @@ w_req.decouple_aw || (w_req.w_dp_req.dst_protocol inside {\ end ) -endmodule : idma_backend${name_uniqueifier} +endmodule diff --git a/src/backend/src/idma_backend_synth.sv.tpl b/src/backend/tpl/idma_backend_synth.sv.tpl similarity index 88% rename from src/backend/src/idma_backend_synth.sv.tpl rename to src/backend/tpl/idma_backend_synth.sv.tpl index d33beb6b..e6c836a3 100644 --- a/src/backend/src/idma_backend_synth.sv.tpl +++ b/src/backend/tpl/idma_backend_synth.sv.tpl @@ -1,37 +1,47 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti `include "axi/typedef.svh" `include "idma/typedef.svh" /// Synthesis wrapper for the iDMA backend. Unpacks all the interfaces to simple logic vectors -module idma_backend_synth${name_uniqueifier} #( +module idma_backend_synth_${name_uniqueifier} #( + /// Should both data shifts be done before the dataflow element? + /// If this is enabled, then the data inserted into the dataflow element + /// will no longer be word aligned, but only a single shifter is needed + parameter bit CombinedShifter = 1'b\ +% if combined_shifter: +1, +% else: +0, +% endif /// Data width - parameter int unsigned DataWidth = 32'd32, + parameter int unsigned DataWidth = 32'd32, /// Address width - parameter int unsigned AddrWidth = 32'd32, + parameter int unsigned AddrWidth = 32'd32, /// AXI user width - parameter int unsigned UserWidth = 32'd1, + parameter int unsigned UserWidth = 32'd1, /// AXI ID width - parameter int unsigned AxiIdWidth = 32'd1, + parameter int unsigned AxiIdWidth = 32'd1, /// Number of transaction that can be in-flight concurrently - parameter int unsigned NumAxInFlight = 32'd3, + parameter int unsigned NumAxInFlight = 32'd3, /// The depth of the internal reorder buffer: /// - '2': minimal possible configuration /// - '3': efficiently handle misaligned transfers (recommended) - parameter int unsigned BufferDepth = 32'd3, + parameter int unsigned BufferDepth = 32'd3, /// With of a transfer: max transfer size is `2**TFLenWidth` bytes - parameter int unsigned TFLenWidth = 32'd32, + parameter int unsigned TFLenWidth = 32'd32, /// The depth of the memory system the backend is attached to - parameter int unsigned MemSysDepth = 32'd0, + parameter int unsigned MemSysDepth = 32'd0, /// Mask invalid data on the manager interface - parameter bit MaskInvalidData = 1'b1, + parameter bit MaskInvalidData = 1'b1, /// Should the `R`-`AW` coupling hardware be present? (recommended) - parameter bit RAWCouplingAvail = \ + parameter bit RAWCouplingAvail = \ % if one_read_port and one_write_port and ('axi' in used_read_protocols) and ('axi' in used_write_protocols): 1, % else: @@ -40,11 +50,11 @@ module idma_backend_synth${name_uniqueifier} #( /// Should hardware legalization be present? (recommended) /// If not, software legalization is required to ensure the transfers are /// AXI4-conformal - parameter bit HardwareLegalizer = 1'b1, + parameter bit HardwareLegalizer = 1'b1, /// Reject zero-length transfers - parameter bit RejectZeroTransfers = 1'b1, + parameter bit RejectZeroTransfers = 1'b1, /// Should the error handler be present? - parameter bit ErrorHandling = 1'b\ + parameter bit ErrorHandling = 1'b\ % if one_read_port and one_write_port and ('axi' in used_read_protocols) and ('axi' in used_write_protocols): 1, % else: @@ -52,23 +62,23 @@ module idma_backend_synth${name_uniqueifier} #( %endif // Dependent parameters; do not override! /// Strobe Width (do not override!) - parameter int unsigned StrbWidth = DataWidth / 8, + parameter int unsigned StrbWidth = DataWidth / 8, /// Offset Width (do not override!) - parameter int unsigned OffsetWidth = $clog2(StrbWidth), + parameter int unsigned OffsetWidth = $clog2(StrbWidth), /// Address type (do not override!) - parameter type addr_t = logic[AddrWidth-1:0], + parameter type addr_t = logic[AddrWidth-1:0], /// Data type (do not override!) - parameter type data_t = logic[DataWidth-1:0], + parameter type data_t = logic[DataWidth-1:0], /// Strobe type (do not override!) - parameter type strb_t = logic[StrbWidth-1:0], + parameter type strb_t = logic[StrbWidth-1:0], /// User type (do not override!) - parameter type user_t = logic[UserWidth-1:0], + parameter type user_t = logic[UserWidth-1:0], /// ID type (do not override!) - parameter type id_t = logic[AxiIdWidth-1:0], + parameter type id_t = logic[AxiIdWidth-1:0], /// Transfer length type (do not override!) - parameter type tf_len_t = logic[TFLenWidth-1:0], + parameter type tf_len_t = logic[TFLenWidth-1:0], /// Offset type (do not override!) - parameter type offset_t = logic[OffsetWidth-1:0] + parameter type offset_t = logic[OffsetWidth-1:0] )( input logic clk_i, input logic rst_ni, @@ -275,7 +285,8 @@ ${p}_${database[p]['write_meta_channel']}_width\ idma_req_t idma_req; idma_rsp_t idma_rsp; - idma_backend${name_uniqueifier} #( + idma_backend_${name_uniqueifier} #( + .CombinedShifter ( CombinedShifter ), .DataWidth ( DataWidth ), .AddrWidth ( AddrWidth ), .AxiIdWidth ( AxiIdWidth ), @@ -393,4 +404,4 @@ ${database[protocol]['synth_wrapper_assign_write']} % endfor -endmodule : idma_backend_synth${name_uniqueifier} +endmodule diff --git a/src/backend/tpl/idma_legalizer.sv.tpl b/src/backend/tpl/idma_legalizer.sv.tpl new file mode 100644 index 00000000..4d7927a7 --- /dev/null +++ b/src/backend/tpl/idma_legalizer.sv.tpl @@ -0,0 +1,670 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Authors: +// - Thomas Benz +// - Tobias Senti + +`include "common_cells/registers.svh" +`include "common_cells/assertions.svh" +`include "idma/guard.svh" + +/// Legalizes a generic 1D transfer according to the rules given by the +/// used protocol. +module idma_legalizer_${name_uniqueifier} #( + /// Should both data shifts be done before the dataflow element? + /// If this is enabled, then the data inserted into the dataflow element + /// will no longer be word aligned, but only a single shifter is needed + parameter bit CombinedShifter = 1'b0, + /// Data width + parameter int unsigned DataWidth = 32'd16, + /// Address width + parameter int unsigned AddrWidth = 32'd24, + /// 1D iDMA request type: + /// - `length`: the length of the transfer in bytes + /// - `*_addr`: the source / target byte addresses of the transfer + /// - `opt`: the options field + parameter type idma_req_t = logic, + /// Read request type + parameter type idma_r_req_t = logic, + /// Write request type + parameter type idma_w_req_t = logic, + /// Mutable transfer type + parameter type idma_mut_tf_t = logic, + /// Mutable options type + parameter type idma_mut_tf_opt_t = logic +)( + /// Clock + input logic clk_i, + /// Asynchronous reset, active low + input logic rst_ni, + + /// 1D request + input idma_req_t req_i, + /// 1D request valid + input logic valid_i, + /// 1D request ready + output logic ready_o, + + /// Read request; contains datapath and meta information + output idma_r_req_t r_req_o, + /// Read request valid + output logic r_valid_o, + /// Read request ready + input logic r_ready_i, + + /// Write request; contains datapath and meta information + output idma_w_req_t w_req_o, + /// Write request valid + output logic w_valid_o, + /// Write request ready + input logic w_ready_i, + + /// Invalidate the current burst transfer, stops emission of requests + input logic flush_i, + /// Kill the active 1D transfer; reload a new transfer + input logic kill_i, + + /// Read machine of the legalizer is busy + output logic r_busy_o, + /// Write machine of the legalizer is busy + output logic w_busy_o +); +% if len(used_protocols) != 1: + function int unsigned max_size(input int unsigned a, b); + return a > b ? a : b; + endfunction + +% endif + /// Stobe width + localparam int unsigned StrbWidth = DataWidth / 8; + /// Offset width + localparam int unsigned OffsetWidth = $clog2(StrbWidth); + /// The size of a page in byte + localparam int unsigned PageSize = \ +% if len(used_protocols) == 1: + % if database[used_protocols[0]]['bursts'] == 'not_supported': +StrbWidth; + % elif database[used_protocols[0]]['bursts'] == 'only_pow2': +${database[used_protocols[0]]['page_size']}; + % elif database[used_protocols[0]]['bursts'] == 'split_at_page_boundary': +${database[used_read_protocols[0]]['max_beats_per_burst']} * StrbWidth > ${database[used_protocols[0]]['page_size']}\ + ? ${database[used_protocols[0]]['page_size']} : ${database[used_read_protocols[0]]['max_beats_per_burst']} * StrbWidth; + % endif +% else: + % for index, p in enumerate(used_protocols): + % if index < len(used_protocols)-1: +max_size(\ + % if database[p]['bursts'] == 'not_supported': +StrbWidth\ + % elif database[p]['bursts'] == 'only_pow2': +${database[p]['page_size']}\ + % elif database[p]['bursts'] == 'split_at_page_boundary': +${database[p]['max_beats_per_burst']} * StrbWidth > ${database[p]['page_size']}\ + ? ${database[p]['page_size']} : ${database[p]['max_beats_per_burst']} * StrbWidth\ + % endif +, \ + % else: + % if database[p]['bursts'] == 'not_supported': +StrbWidth\ + % elif database[p]['bursts'] == 'only_pow2': +${database[p]['page_size']}\ + % elif database[p]['bursts'] == 'split_at_page_boundary': +${database[p]['max_beats_per_burst']} * StrbWidth > ${database[p]['page_size']}\ + ? ${database[p]['page_size']} : ${database[p]['max_beats_per_burst']} * StrbWidth\ + % endif + % endif + % endfor + % for i in range(0, len(used_protocols)-1): +)\ + % endfor +; +% endif + /// The width of page offset byte addresses + localparam int unsigned PageAddrWidth = $clog2(PageSize); + + /// Offset type + typedef logic [ OffsetWidth-1:0] offset_t; + /// Address type + typedef logic [ AddrWidth-1:0] addr_t; + /// Page address type + typedef logic [PageAddrWidth-1:0] page_addr_t; + /// Page length type + typedef logic [ PageAddrWidth:0] page_len_t; + + + // state: internally hold one transfer, this is mutated + idma_mut_tf_t r_tf_d, r_tf_q; + idma_mut_tf_t w_tf_d, w_tf_q; + idma_mut_tf_opt_t opt_tf_d, opt_tf_q; + + // enable signals for next mutable transfer storage + logic r_tf_ena; + logic w_tf_ena; + + // page boundaries +% if no_read_bursting or has_page_read_bursting: + page_len_t r_page_num_bytes_to_pb; +% endif +% for read_protocol in used_read_protocols: + % if database[read_protocol]['bursts'] == 'only_pow2': + page_len_t r_${database[read_protocol]['prefix']}_num_bytes_to_pb; + % endif +% endfor + page_len_t r_num_bytes_to_pb; +% if no_write_bursting or has_page_write_bursting: + page_len_t w_page_num_bytes_to_pb; +% endif +% for write_protocol in used_write_protocols: + % if database[write_protocol]['bursts'] == 'only_pow2': + page_len_t w_${database[write_protocol]['prefix']}_num_bytes_to_pb; + % endif +% endfor + page_len_t w_num_bytes_to_pb; + page_len_t c_num_bytes_to_pb; + + // read process + page_len_t r_num_bytes_possible; + page_len_t r_num_bytes; + offset_t r_addr_offset; + logic r_done; + + // write process + page_len_t w_num_bytes_possible; + page_len_t w_num_bytes; + offset_t w_addr_offset; + logic w_done; + + + //-------------------------------------- + // read boundary check + //-------------------------------------- +% if no_read_bursting or has_page_read_bursting: + idma_legalizer_page_splitter #( + .OffsetWidth ( OffsetWidth ), + .PageAddrWidth ( PageSize ), + .addr_t ( addr_t ), + .page_len_t ( page_len_t ), + .page_addr_t ( page_addr_t ) + ) i_read_page_splitter ( + % if no_read_bursting: + .not_bursting_i ( 1'b1 ), + % elif len(used_non_bursting_read_protocols) == 0: + .not_bursting_i ( 1'b0 ), + % else: + .not_bursting_i ( opt_tf_q.src_protocol inside {\ + % for index, protocol in enumerate(used_non_bursting_read_protocols): + idma_pkg::${database[protocol]['protocol_enum']}\ + % if index != len(used_non_bursting_read_protocols)-1: +,\ + % endif + % endfor +} ), + % endif + + .reduce_len_i ( opt_tf_q.src_reduce_len ), + .max_llen_i ( opt_tf_q.src_max_llen ), + + .addr_i ( r_tf_q.addr ), + .num_bytes_to_pb_o ( r_page_num_bytes_to_pb ) + ); + +% endif +% for read_protocol in used_read_protocols: + % if database[read_protocol]['bursts'] == 'only_pow2': + idma_legalizer_pow2_splitter #( + .PageAddrWidth ( $clog2(${database[read_protocol]['page_size']}) ), + .OffsetWidth ( OffsetWidth ), + .addr_t ( addr_t ), + .len_t ( page_len_t ) + ) i_read_pow2_splitter ( + .addr_i ( r_tf_q.addr ), + .length_i ( \ + % if database[read_protocol]['tltoaxi4_compatibility_mode'] == "true": +|r_tf_q.length[$bits(r_tf_q.length)-1:PageAddrWidth] ? page_len_t'('d${database[read_protocol]['page_size']} - r_tf_q.addr[PageAddrWidth-1:0]) : r_tf_q.length[PageAddrWidth:0] ), + .length_larger_i ( 1'b0 ), + % else: +r_tf_q.length[PageAddrWidth:0] ), + .length_larger_i ( |r_tf_q.length[$bits(r_tf_q.length)-1:PageAddrWidth+1] ), + % endif + .bytes_to_transfer_o ( r_${database[read_protocol]['prefix']}_num_bytes_to_pb ) + ); + + % endif +% endfor +% if one_read_port: + % if has_pow2_read_bursting: + assign r_num_bytes_to_pb = r_${database[used_read_protocols[0]]['prefix']}_num_bytes_to_pb; + % else: + assign r_num_bytes_to_pb = r_page_num_bytes_to_pb; + % endif +% else: + always_comb begin : gen_read_num_bytes_to_pb_logic + case (opt_tf_q.src_protocol) + % for read_protocol in used_read_protocols: + idma_pkg::${database[read_protocol]['protocol_enum']}: \ + % if database[read_protocol]['bursts'] == 'only_pow2': +r_num_bytes_to_pb = r_${database[read_protocol]['prefix']}_num_bytes_to_pb; + % else: +r_num_bytes_to_pb = r_page_num_bytes_to_pb; + % endif + % endfor + default: r_num_bytes_to_pb = '0; + endcase + end +% endif + + //-------------------------------------- + // write boundary check + //-------------------------------------- +% if no_write_bursting or has_page_write_bursting: + idma_legalizer_page_splitter #( + .OffsetWidth ( OffsetWidth ), + .PageAddrWidth ( PageSize ), + .addr_t ( addr_t ), + .page_len_t ( page_len_t ), + .page_addr_t ( page_addr_t ) + ) i_write_page_splitter ( + % if no_write_bursting: + .not_bursting_i ( 1'b1 ), + % elif len(used_non_bursting_write_protocols) == 0: + .not_bursting_i ( 1'b0 ), + % else: + .not_bursting_i ( opt_tf_q.dst_protocol inside {\ + % for index, protocol in enumerate(used_non_bursting_write_protocols): + idma_pkg::${database[protocol]['protocol_enum']}\ + % if index != len(used_non_bursting_write_protocols)-1: +,\ + % endif + % endfor +} ), + % endif + + .reduce_len_i ( opt_tf_q.dst_reduce_len ), + .max_llen_i ( opt_tf_q.dst_max_llen ), + + .addr_i ( w_tf_q.addr ), + .num_bytes_to_pb_o ( w_page_num_bytes_to_pb ) + ); + +% endif +% for write_protocol in used_write_protocols: + % if database[write_protocol]['bursts'] == 'only_pow2': + idma_legalizer_pow2_splitter #( + .PageAddrWidth ( \ +% if database[write_protocol]['tltoaxi4_compatibility_mode'] == "true": +$clog2((32 * StrbWidth) > ${database[write_protocol]['page_size']} ? ${database[write_protocol]['page_size']} : (32 * StrbWidth)) ), +% else: +$clog2(${database[write_protocol]['page_size']}) ), +% endif + .OffsetWidth ( OffsetWidth ), + .addr_t ( addr_t ), + .len_t ( page_len_t ) + ) i_write_pow2_splitter ( + .addr_i ( w_tf_q.addr ), + .length_i ( \ + % if database[write_protocol]['tltoaxi4_compatibility_mode'] == "true": +|w_tf_q.length[$bits(w_tf_q.length)-1:PageAddrWidth] ? page_len_t'('d${database[write_protocol]['page_size']} - w_tf_q.addr[PageAddrWidth-1:0]) : w_tf_q.length[PageAddrWidth:0] ), + .length_larger_i ( 1'b0 ), + % else: +w_tf_q.length[PageAddrWidth:0] ), + .length_larger_i ( |w_tf_q.length[$bits(w_tf_q.length)-1:PageAddrWidth+1] ), + % endif + .bytes_to_transfer_o ( w_${database[write_protocol]['prefix']}_num_bytes_to_pb ) + ); + + % endif +% endfor +% if one_write_port: + % if has_pow2_write_bursting: + assign w_num_bytes_to_pb = w_${database[used_write_protocols[0]]['prefix']}_num_bytes_to_pb; + % else: + assign w_num_bytes_to_pb = w_page_num_bytes_to_pb; + % endif +% else: + always_comb begin : gen_write_num_bytes_to_pb_logic + case (opt_tf_q.dst_protocol) + % for write_protocol in used_write_protocols: + idma_pkg::${database[write_protocol]['protocol_enum']}: \ + % if database[write_protocol]['bursts'] == 'only_pow2': +w_num_bytes_to_pb = w_${database[write_protocol]['prefix']}_num_bytes_to_pb; + % else: +w_num_bytes_to_pb = w_page_num_bytes_to_pb; + % endif + % endfor + default: w_num_bytes_to_pb = '0; + endcase + end +% endif + + //-------------------------------------- + // page boundary check + //-------------------------------------- + // how many transfers are remaining when concerning both r/w pages? + // take the boundary that is closer + assign c_num_bytes_to_pb = (r_num_bytes_to_pb > w_num_bytes_to_pb) ? + w_num_bytes_to_pb : r_num_bytes_to_pb; + + + //-------------------------------------- + // Synchronized R/W process + //-------------------------------------- + always_comb begin : proc_num_bytes_possible + // Default: Coupled + r_num_bytes_possible = c_num_bytes_to_pb; + w_num_bytes_possible = c_num_bytes_to_pb; + + if (opt_tf_q.decouple_rw\ + % if len(used_non_bursting_or_force_decouple_read_protocols) != 0: + + || (opt_tf_q.src_protocol inside {\ + % for index, protocol in enumerate(used_non_bursting_or_force_decouple_read_protocols): + idma_pkg::${database[protocol]['protocol_enum']}\ + % if index != len(used_non_bursting_or_force_decouple_read_protocols)-1: +,\ + % endif + % endfor + })\ + % endif + % if len(used_non_bursting_or_force_decouple_write_protocols) != 0: + + || (opt_tf_q.dst_protocol inside {\ + % for index, protocol in enumerate(used_non_bursting_or_force_decouple_write_protocols): + idma_pkg::${database[protocol]['protocol_enum']}\ + % if index != len(used_non_bursting_or_force_decouple_write_protocols)-1: +,\ + % endif + % endfor + })\ + % endif +) begin + r_num_bytes_possible = r_num_bytes_to_pb; + w_num_bytes_possible = w_num_bytes_to_pb; + end + end + + assign r_addr_offset = r_tf_q.addr[OffsetWidth-1:0]; + assign w_addr_offset = w_tf_q.addr[OffsetWidth-1:0]; + + // legalization process -> read and write is coupled together + always_comb begin : proc_read_write_transaction + + // default: keep state + r_tf_d = r_tf_q; + w_tf_d = w_tf_q; + opt_tf_d = opt_tf_q; + + // default: not done + r_done = 1'b0; + w_done = 1'b0; + + //-------------------------------------- + // Legalize read transaction + //-------------------------------------- + // more bytes remaining than we can read + if (r_tf_q.length > r_num_bytes_possible) begin + r_num_bytes = r_num_bytes_possible; + // calculate remainder + r_tf_d.length = r_tf_q.length - r_num_bytes_possible; + // next address + r_tf_d.addr = r_tf_q.addr + r_num_bytes; + + // remaining bytes fit in one burst + end else begin + r_num_bytes = r_tf_q.length[PageAddrWidth:0]; + // finished + r_tf_d.valid = 1'b0; + r_done = 1'b1; + end + + //-------------------------------------- + // Legalize write transaction + //-------------------------------------- + // more bytes remaining than we can write + if (w_tf_q.length > w_num_bytes_possible) begin + w_num_bytes = w_num_bytes_possible; + // calculate remainder + w_tf_d.length = w_tf_q.length - w_num_bytes_possible; + // next address + w_tf_d.addr = w_tf_q.addr + w_num_bytes; + + // remaining bytes fit in one burst + end else begin + w_num_bytes = w_tf_q.length[PageAddrWidth:0]; + // finished + w_tf_d.valid = 1'b0; + w_done = 1'b1; + end + + //-------------------------------------- + // Kill + //-------------------------------------- + if (kill_i) begin + // kill the current state + r_tf_d = '0; + w_tf_d = '0; + r_done = 1'b1; + w_done = 1'b1; + end + + //-------------------------------------- + // Refill + //-------------------------------------- + // new request is taken in if both r and w machines are ready. + if (ready_o & valid_i) begin + + // load all three mutable objects (source, destination, option) + // source or read + r_tf_d = '{ + length: req_i.length, + addr: req_i.src_addr, + valid: 1'b1, + base_addr: req_i.src_addr + }; + // destination or write + w_tf_d = '{ + length: req_i.length, + addr: req_i.dst_addr, + valid: 1'b1, + base_addr: req_i.dst_addr + }; + // options + opt_tf_d = '{ + src_protocol: req_i.opt.src_protocol, + dst_protocol: req_i.opt.dst_protocol, + read_shift: '0, + write_shift: '0, + decouple_rw: req_i.opt.beo.decouple_rw, + decouple_aw: req_i.opt.beo.decouple_aw, + src_max_llen: req_i.opt.beo.src_max_llen, + dst_max_llen: req_i.opt.beo.dst_max_llen, + src_reduce_len: req_i.opt.beo.src_reduce_len, + dst_reduce_len: req_i.opt.beo.dst_reduce_len, + axi_id: req_i.opt.axi_id, + src_axi_opt: req_i.opt.src, + dst_axi_opt: req_i.opt.dst, + super_last: req_i.opt.last + }; + // determine shift amount + if (CombinedShifter) begin + opt_tf_d.read_shift = req_i.src_addr[OffsetWidth-1:0] - req_i.dst_addr[OffsetWidth-1:0]; + opt_tf_d.write_shift = '0; + end else begin + opt_tf_d.read_shift = req_i.src_addr[OffsetWidth-1:0]; + opt_tf_d.write_shift = - req_i.dst_addr[OffsetWidth-1:0]; + end + end + end + + + //-------------------------------------- + // Connect outputs + //-------------------------------------- + + // Read meta channel +% if one_read_port: + always_comb begin +${database[used_read_protocols[0]]['legalizer_read_meta_channel']} + end +% else: + always_comb begin : gen_read_meta_channel + r_req_o.ar_req = '0; + case(opt_tf_q.src_protocol) + % for protocol in used_read_protocols: + idma_pkg::${database[protocol]['protocol_enum']}: begin +${database[protocol]['legalizer_read_meta_channel']} + end + % endfor + default: + r_req_o.ar_req = '0; + endcase + end +% endif + + // assign the signals needed to set-up the read data path + assign r_req_o.r_dp_req = '{ + src_protocol: opt_tf_q.src_protocol, + offset: r_addr_offset, + tailer: OffsetWidth'(r_num_bytes + r_addr_offset), + shift: opt_tf_q.read_shift, + decouple_aw: opt_tf_q.decouple_aw, + is_single: r_num_bytes <= StrbWidth + }; + + // Write meta channel and data path +% if one_write_port: + always_comb begin +${database[used_write_protocols[0]]['legalizer_write_meta_channel']} + % if 'legalizer_write_data_path' in database[used_write_protocols[0]]: +${database[used_write_protocols[0]]['legalizer_write_data_path']} + % else: + w_req_o.w_dp_req = '{ + dst_protocol: opt_tf_q.dst_protocol, + offset: w_addr_offset, + tailer: OffsetWidth'(w_num_bytes + w_addr_offset), + shift: opt_tf_q.write_shift, + num_beats: 'd0, + is_single: 1'b1 + }; + % endif + end +% else: + always_comb begin : gen_write_meta_channel + w_req_o.aw_req = '0; + case(opt_tf_q.dst_protocol) + % for protocol in used_write_protocols: + idma_pkg::${database[protocol]['protocol_enum']}: begin +${database[protocol]['legalizer_write_meta_channel']} + end + % endfor + default: + w_req_o.aw_req = '0; + endcase + end + + // assign the signals needed to set-up the write data path + always_comb begin : gen_write_data_path + case (opt_tf_q.dst_protocol) + % for protocol in used_write_protocols: + % if 'legalizer_write_data_path' in database[protocol]: + idma_pkg::${database[protocol]['protocol_enum']}: +${database[protocol]['legalizer_write_data_path']} + % endif + % endfor + default: + w_req_o.w_dp_req = '{ + dst_protocol: opt_tf_q.dst_protocol, + offset: w_addr_offset, + tailer: OffsetWidth'(w_num_bytes + w_addr_offset), + shift: opt_tf_q.write_shift, + num_beats: 'd0, + is_single: 1'b1 + }; + endcase + end + +% endif + + // last burst in generic 1D transfer? + assign w_req_o.last = w_done; + + // last burst indicated by midend + assign w_req_o.super_last = opt_tf_q.super_last; + + // assign aw decouple flag + assign w_req_o.decouple_aw = opt_tf_q.decouple_aw; + + // busy output + assign r_busy_o = r_tf_q.valid; + assign w_busy_o = w_tf_q.valid; + + + //-------------------------------------- + // Flow Control + //-------------------------------------- + // only advance to next state if: + // * rw_coupled: both machines advance + // * rw_decoupled: either machine advances + + always_comb begin : proc_legalizer_flow_control + if ( opt_tf_q.decouple_rw\ + % if len(used_non_bursting_or_force_decouple_read_protocols) != 0: + + || (opt_tf_q.src_protocol inside {\ + % for index, protocol in enumerate(used_non_bursting_or_force_decouple_read_protocols): + idma_pkg::${database[protocol]['protocol_enum']}\ + % if index != len(used_non_bursting_or_force_decouple_read_protocols)-1: +,\ + % endif + % endfor + })\ + % endif + % if len(used_non_bursting_or_force_decouple_write_protocols) != 0: + + || (opt_tf_q.dst_protocol inside {\ + % for index, protocol in enumerate(used_non_bursting_or_force_decouple_write_protocols): + idma_pkg::${database[protocol]['protocol_enum']}\ + % if index != len(used_non_bursting_or_force_decouple_write_protocols)-1: +,\ + % endif + % endfor + })\ + % endif +) begin + r_tf_ena = (r_ready_i & !flush_i) | kill_i; + w_tf_ena = (w_ready_i & !flush_i) | kill_i; + + r_valid_o = r_tf_q.valid & r_ready_i & !flush_i; + w_valid_o = w_tf_q.valid & w_ready_i & !flush_i; + end else begin + r_tf_ena = (r_ready_i & w_ready_i & !flush_i) | kill_i; + w_tf_ena = (r_ready_i & w_ready_i & !flush_i) | kill_i; + + r_valid_o = r_tf_q.valid & w_ready_i & r_ready_i & !flush_i; + w_valid_o = w_tf_q.valid & r_ready_i & w_ready_i & !flush_i; + end + end + + // load next idma request: if both machines are done! + assign ready_o = r_done & w_done & r_ready_i & w_ready_i & !flush_i; + + + //-------------------------------------- + // State + //-------------------------------------- + `FF (opt_tf_q, opt_tf_d, '0, clk_i, rst_ni) + `FFL(r_tf_q, r_tf_d, r_tf_ena, '0, clk_i, rst_ni) + `FFL(w_tf_q, w_tf_d, w_tf_ena, '0, clk_i, rst_ni) + + + //-------------------------------------- + // Assertions + //-------------------------------------- + // only support the decomposition of incremental bursts + `ASSERT_NEVER(OnlyIncrementalBurstsSRC, (ready_o & valid_i & + req_i.opt.src.burst != axi_pkg::BURST_INCR), clk_i, !rst_ni) + `ASSERT_NEVER(OnlyIncrementalBurstsDST, (ready_o & valid_i & + req_i.opt.dst.burst != axi_pkg::BURST_INCR), clk_i, !rst_ni) + +endmodule diff --git a/src/backend/src/idma_transport_layer.sv.tpl b/src/backend/tpl/idma_transport_layer.sv.tpl similarity index 89% rename from src/backend/src/idma_transport_layer.sv.tpl rename to src/backend/tpl/idma_transport_layer.sv.tpl index 54de8150..a249a0b0 100644 --- a/src/backend/src/idma_transport_layer.sv.tpl +++ b/src/backend/tpl/idma_transport_layer.sv.tpl @@ -1,14 +1,16 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti `include "idma/guard.svh" `include "common_cells/registers.svh" /// Implementing the transport layer in the iDMA backend. -module idma_transport_layer${name_uniqueifier} #( +module idma_transport_layer_${name_uniqueifier} #( /// Number of transaction that can be in-flight concurrently parameter int unsigned NumAxInFlight = 32'd2, /// Data width @@ -187,12 +189,7 @@ _rsp_t ${protocol}_write_rsp_i, strb_t buffer_in_ready; // outbound control signals of the buffer: controlled by the write process - strb_t buffer_out_valid\ -% if combined_shifter: -; -% else: - , buffer_out_valid_shifted; -% endif + strb_t buffer_out_valid, buffer_out_valid_shifted; strb_t\ % if not one_write_port: % for p in used_write_protocols: @@ -200,12 +197,7 @@ _rsp_t ${protocol}_write_rsp_i, % endfor % endif - buffer_out_ready\ -% if combined_shifter: -; -% else: -, buffer_out_ready_shifted; -% endif + buffer_out_ready, buffer_out_ready_shifted; // shifted data flowing into the buffer byte_t [StrbWidth-1:0]\ @@ -217,12 +209,7 @@ _rsp_t ${protocol}_write_rsp_i, buffer_in, buffer_in_shifted; // aligned and coalesced data leaving the buffer - byte_t [StrbWidth-1:0] buffer_out\ -% if combined_shifter: -; -% else: -, buffer_out_shifted; -% endif + byte_t [StrbWidth-1:0] buffer_out, buffer_out_shifted; % if not one_read_port: // Read multiplexed signals @@ -413,23 +400,17 @@ ${rendered_read_ports[read_port]} .strb_t ( strb_t ), .byte_t ( byte_t ) ) i_dataflow_element ( - .clk_i, - .rst_ni, - .testmode_i, - .data_i ( buffer_in_shifted ), - .valid_i ( buffer_in_valid ), - .ready_o ( buffer_in_ready ), - .data_o ( buffer_out ), - .valid_o ( buffer_out_valid ), - .ready_i ( \ -% if combined_shifter: -buffer_out_ready ) -% else: -buffer_out_ready_shifted ) -% endif + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( testmode_i ), + .data_i ( buffer_in_shifted ), + .valid_i ( buffer_in_valid ), + .ready_o ( buffer_in_ready ), + .data_o ( buffer_out ), + .valid_o ( buffer_out_valid ), + .ready_i ( buffer_out_ready_shifted ) ); -% if not combined_shifter: //-------------------------------------- // Write Barrel shifter //-------------------------------------- @@ -438,7 +419,6 @@ buffer_out_ready_shifted ) assign buffer_out_valid_shifted = {buffer_out_valid, buffer_out_valid} >> w_dp_req_i.shift; assign buffer_out_ready_shifted = {buffer_out_ready, buffer_out_ready} >> - w_dp_req_i.shift; -% endif % if not one_write_port: //-------------------------------------- // Write Request Demultiplexer @@ -448,10 +428,10 @@ buffer_out_ready_shifted ) stream_fork #( .N_OUP ( 2 ) ) i_write_stream_fork ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( w_dp_valid_i ), - .ready_o ( w_dp_ready_o ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .valid_i ( w_dp_valid_i ), + .ready_o ( w_dp_ready_o ), .valid_o ( { w_resp_fifo_in_valid, w_dp_req_valid } ), .ready_i ( { w_resp_fifo_in_ready, w_dp_req_ready } ) ); @@ -504,16 +484,16 @@ ${rendered_write_ports[write_port]} .type_t ( idma_pkg::protocol_e ), .PrintInfo ( PrintFifoInfo ) ) i_write_response_fifo ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .testmode_i ( testmode_i ), - .flush_i ( 1'b0 ), - .usage_o ( /* NOT CONNECTED */ ), - .data_i ( w_dp_req_i.dst_protocol ), - .valid_i ( w_resp_fifo_in_valid && w_resp_fifo_in_ready ), - .ready_o ( w_resp_fifo_in_ready ), - .data_o ( w_resp_fifo_out_protocol ), - .valid_o ( w_resp_fifo_out_valid ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .testmode_i ( testmode_i ), + .flush_i ( 1'b0 ), + .usage_o ( /* NOT CONNECTED */ ), + .data_i ( w_dp_req_i.dst_protocol ), + .valid_i ( w_resp_fifo_in_valid && w_resp_fifo_in_ready ), + .ready_o ( w_resp_fifo_in_ready ), + .data_o ( w_resp_fifo_out_protocol ), + .valid_o ( w_resp_fifo_out_valid ), .ready_i ( w_resp_fifo_out_ready && w_resp_fifo_out_valid ) ); @@ -549,18 +529,18 @@ ${rendered_write_ports[write_port]} fall_through_register #( .T ( w_dp_rsp_t ) ) i_write_rsp_channel_reg ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clr_i ( 1'b0 ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), .testmode_i ( testmode_i ), .valid_i ( w_dp_rsp_mux_valid ), .ready_o ( w_dp_rsp_mux_ready ), - .data_i ( w_dp_rsp_mux ), + .data_i ( w_dp_rsp_mux ), .valid_o ( w_dp_rsp_valid ), .ready_i ( w_dp_rsp_ready ), - .data_o ( w_dp_rsp_o ) + .data_o ( w_dp_rsp_o ) ); // Join write response fifo and write port responses @@ -582,4 +562,4 @@ ${rendered_write_ports[write_port]} assign w_dp_busy_o = w_dp_valid_i | w_dp_ready_o; assign buffer_busy_o = |buffer_out_valid; -endmodule : idma_transport_layer${name_uniqueifier} +endmodule diff --git a/src/backend/database/idma_axi.yaml b/src/db/idma_axi.yml similarity index 81% rename from src/backend/database/idma_axi.yaml rename to src/db/idma_axi.yml index e1b971cd..cb20f3d5 100644 --- a/src/backend/database/idma_axi.yaml +++ b/src/db/idma_axi.yml @@ -1,16 +1,21 @@ # Copyright 2022 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# -# Tobias Senti -prefix: "axi" -protocol_enum: "AXI" -full_name: "AXI4+ATOP" -bursts: "split_at_page_boundary" + +# Authors: +# - Tobias Senti + +prefix: "axi" +protocol_enum: "AXI" +full_name: "AXI4+ATOP" +bursts: "split_at_page_boundary" page_size: 4096 max_beats_per_burst: 256 -read_meta_channel: "ar_chan" +legalizer_force_decouple: "false" +read_meta_channel: "ar_chan" write_meta_channel: "aw_chan" +combined_aw_and_w: "false" +read_slave: "false" read_meta_channel_width: "localparam int unsigned axi_ar_chan_width = axi_pkg::ar_width(AddrWidth, AxiIdWidth, UserWidth);" write_meta_channel_width: "localparam int unsigned axi_aw_chan_width = axi_pkg::aw_width(AddrWidth, AxiIdWidth, UserWidth);" typedefs: | @@ -23,6 +28,44 @@ typedefs: | `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_chan_t, axi_w_chan_t, axi_ar_chan_t) `AXI_TYPEDEF_RESP_T(axi_rsp_t, axi_b_chan_t, axi_r_chan_t) +legalizer_read_meta_channel: | + r_req_o.ar_req.axi.ar_chan = '{ + id: opt_tf_q.axi_id, + addr: { r_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, + len: ((r_num_bytes + r_addr_offset - 'd1) >> OffsetWidth), + size: axi_pkg::size_t'(OffsetWidth), + burst: opt_tf_q.src_axi_opt.burst, + lock: opt_tf_q.src_axi_opt.lock, + cache: opt_tf_q.src_axi_opt.cache, + prot: opt_tf_q.src_axi_opt.prot, + qos: opt_tf_q.src_axi_opt.qos, + region: opt_tf_q.src_axi_opt.region, + user: '0 + }; +legalizer_write_meta_channel: | + w_req_o.aw_req.axi.aw_chan = '{ + id: opt_tf_q.axi_id, + addr: { w_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, + len: ((w_num_bytes + w_addr_offset - 'd1) >> OffsetWidth), + size: axi_pkg::size_t'(OffsetWidth), + burst: opt_tf_q.dst_axi_opt.burst, + lock: opt_tf_q.dst_axi_opt.lock, + cache: opt_tf_q.dst_axi_opt.cache, + prot: opt_tf_q.dst_axi_opt.prot, + qos: opt_tf_q.dst_axi_opt.qos, + region: opt_tf_q.dst_axi_opt.region, + user: '0, + atop: '0 + }; +legalizer_write_data_path: | + w_req_o.w_dp_req = '{ + dst_protocol: opt_tf_q.dst_protocol, + offset: w_addr_offset, + tailer: OffsetWidth'(w_num_bytes + w_addr_offset), + shift: opt_tf_q.write_shift, + num_beats: w_req_o.aw_req.axi.aw_chan.len, + is_single: w_req_o.aw_req.axi.aw_chan.len == '0 + }; read_template: | idma_axi_read #( .StrbWidth ( StrbWidth ), @@ -80,8 +123,8 @@ write_template: | .aw_ready_o ( ${write_meta_ready} ), .write_req_o ( ${write_request} ), .write_rsp_i ( ${write_response} ), - .buffer_out_i ( ${buffer_out} ), - .buffer_out_valid_i ( ${buffer_out_valid} ), + .buffer_out_i ( buffer_out_shifted ), + .buffer_out_valid_i ( buffer_out_valid_shifted ), .buffer_out_ready_o ( ${buffer_out_ready} ) ); synth_wrapper_ports_write: | @@ -179,4 +222,4 @@ synth_wrapper_assign_read: | assign axi_read_rsp.r.resp = axi_r_resp_i; assign axi_read_rsp.r.last = axi_r_last_i; assign axi_read_rsp.r.user = axi_r_user_i; - assign axi_read_rsp.r_valid = axi_r_valid_i; \ No newline at end of file + assign axi_read_rsp.r_valid = axi_r_valid_i; diff --git a/src/backend/database/idma_axi_lite.yaml b/src/db/idma_axi_lite.yml similarity index 83% rename from src/backend/database/idma_axi_lite.yaml rename to src/db/idma_axi_lite.yml index 29e70fd9..6d7099df 100644 --- a/src/backend/database/idma_axi_lite.yaml +++ b/src/db/idma_axi_lite.yml @@ -1,16 +1,23 @@ # Copyright 2022 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# -# Tobias Senti -prefix: "axi_lite" -protocol_enum: "AXI_LITE" -full_name: "AXI-Lite" -bursts: "not_supported" -read_meta_channel: "ar_chan" + +# Authors: +# - Tobias Senti + +prefix: "axil" +protocol_enum: "AXI_LITE" +full_name: "AXI-Lite" +bursts: "not_supported" +legalizer_force_decouple: "false" +read_meta_channel: "ar_chan" write_meta_channel: "aw_chan" -read_meta_channel_width: "localparam int unsigned axi_lite_ar_chan_width = $bits(axi_lite_ar_chan_t);" -write_meta_channel_width: "localparam int unsigned axi_lite_aw_chan_width = $bits(axi_lite_aw_chan_t);" +combined_aw_and_w: "false" +read_slave: "false" +read_meta_channel_width: | + "localparam int unsigned axi_lite_ar_chan_width = $bits(axi_lite_ar_chan_t);" +write_meta_channel_width: | + "localparam int unsigned axi_lite_aw_chan_width = $bits(axi_lite_aw_chan_t);" typedefs: | `AXI_LITE_TYPEDEF_AW_CHAN_T(axi_lite_aw_chan_t, addr_t) `AXI_LITE_TYPEDEF_W_CHAN_T(axi_lite_w_chan_t, data_t, strb_t) @@ -28,7 +35,7 @@ bridge_template: | .resp_lite_t ( axi_lite_rsp_t ), .axi_req_t ( axi_req_t ), .axi_resp_t ( axi_rsp_t ) - ) i_axi_lite_to_axi_${port} ( + ) i_axil_to_axi_${port} ( .slv_req_lite_i ( axi_lite_${port}_req ), .slv_resp_lite_o ( axi_lite_${port}_rsp ), .slv_aw_cache_i ( axi_pkg::CACHE_MODIFIABLE ), @@ -36,8 +43,18 @@ bridge_template: | .mst_req_o ( axi_lite_axi_${port}_req ), .mst_resp_i ( axi_lite_axi_${port}_rsp ) ); +legalizer_read_meta_channel: | + r_req_o.ar_req.axi_lite.ar_chan = '{ + addr: { r_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, + prot: opt_tf_q.src_axi_opt.prot + }; +legalizer_write_meta_channel: | + w_req_o.aw_req.axi_lite.aw_chan = '{ + addr: { w_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, + prot: opt_tf_q.dst_axi_opt.prot + }; read_template: | - idma_axi_lite_read #( + idma_axil_read #( .StrbWidth ( StrbWidth ), .byte_t ( byte_t ), .strb_t ( strb_t ), @@ -46,7 +63,7 @@ read_template: | .ar_chan_t ( read_meta_channel_t ), .read_req_t ( ${req_t} ), .read_rsp_t ( ${rsp_t} ) - ) i_idma_axi_lite_read ( + ) i_idma_axil_read ( .r_dp_req_i ( r_dp_req_i ), .r_dp_valid_i ( ${r_dp_valid_i} ), .r_dp_ready_o ( ${r_dp_ready_o} ), @@ -65,7 +82,7 @@ read_template: | .buffer_in_ready_i ( buffer_in_ready ) ); write_template: | - idma_axi_lite_write #( + idma_axil_write #( .StrbWidth ( StrbWidth ), .MaskInvalidData ( MaskInvalidData ), .byte_t ( byte_t ), @@ -76,7 +93,7 @@ write_template: | .aw_chan_t ( write_meta_channel_t ), .write_req_t ( ${req_t} ), .write_rsp_t ( ${rsp_t} ) - ) i_idma_axi_lite_write ( + ) i_idma_axil_write ( .w_dp_req_i ( w_dp_req_i ), .w_dp_valid_i ( ${w_dp_valid_i} ), .w_dp_ready_o ( ${w_dp_ready_o} ), @@ -89,8 +106,8 @@ write_template: | .aw_ready_o ( ${write_meta_ready} ), .write_req_o ( ${write_request} ), .write_rsp_i ( ${write_response} ), - .buffer_out_i ( ${buffer_out} ), - .buffer_out_valid_i ( ${buffer_out_valid} ), + .buffer_out_i ( buffer_out_shifted ), + .buffer_out_valid_i ( buffer_out_valid_shifted ), .buffer_out_ready_o ( ${buffer_out_ready} ) ); synth_wrapper_ports_write: | @@ -138,4 +155,4 @@ synth_wrapper_assign_read: | assign axi_lite_read_rsp.ar_ready = axi_lite_ar_ready_i; assign axi_lite_read_rsp.r.data = axi_lite_r_data_i; assign axi_lite_read_rsp.r.resp = axi_lite_r_resp_i; - assign axi_lite_read_rsp.r_valid = axi_lite_r_valid_i; \ No newline at end of file + assign axi_lite_read_rsp.r_valid = axi_lite_r_valid_i; diff --git a/src/backend/database/idma_axi_stream.yaml b/src/db/idma_axi_stream.yml similarity index 92% rename from src/backend/database/idma_axi_stream.yaml rename to src/db/idma_axi_stream.yml index dc7de682..2a6ac290 100644 --- a/src/backend/database/idma_axi_stream.yaml +++ b/src/db/idma_axi_stream.yml @@ -1,16 +1,19 @@ # Copyright 2022 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# -# Tobias Senti -prefix: "axi_stream" -protocol_enum: "AXI_STREAM" -full_name: "AXI Stream" -bursts: "not_supported" + +# Authors: +# - Tobias Senti + +prefix: "axis" +protocol_enum: "AXI_STREAM" +full_name: "AXI Stream" +bursts: "not_supported" +legalizer_force_decouple: "false" write_meta_channel: "t_chan" -read_meta_channel: "t_chan" -combined_aw_and_w: "true" -read_slave: "true" +read_meta_channel: "t_chan" +combined_aw_and_w: "true" +read_slave: "true" meta_channel_width: "localparam int unsigned axi_stream_t_chan_width = $bits(axi_stream_t_chan_t);" typedefs: | `IDMA_AXI_STREAM_TYPEDEF_S_CHAN_T(axi_stream_t_chan_t, data_t, strb_t, strb_t, id_t, id_t, user_t) @@ -201,8 +204,20 @@ write_bridge_template: | .axi_req_o ( axi_stream_axi_write_req ), .axi_rsp_i ( axi_stream_axi_write_rsp ) ); +legalizer_read_meta_channel: | + r_req_o.ar_req = '0; +legalizer_write_meta_channel: | + w_req_o.aw_req.axi_stream.t_chan = '{ + data: '0, + strb: '1, + keep: '0, + last: w_tf_q.length == w_num_bytes, + id: opt_tf_q.axi_id, + dest: w_tf_q.base_addr[$bits(w_req_o.aw_req.axi_stream.t_chan.dest)-1:0], + user: w_tf_q.base_addr[$bits(w_req_o.aw_req.axi_stream.t_chan.user)-1+:$bits(w_req_o.aw_req.axi_stream.t_chan.dest)] + }; read_template: | - idma_axi_stream_read #( + idma_axis_read #( .StrbWidth ( StrbWidth ), .byte_t ( byte_t ), .strb_t ( strb_t ), @@ -211,7 +226,7 @@ read_template: | .read_meta_chan_t ( read_meta_channel_t ), .read_req_t ( ${req_t} ), .read_rsp_t ( ${rsp_t} ) - ) i_idma_axi_stream_read ( + ) i_idma_axis_read ( .r_dp_req_i ( r_dp_req_i ), .r_dp_req_valid_i ( ${r_dp_valid_i} ), .r_dp_req_ready_o ( ${r_dp_ready_o} ), @@ -230,7 +245,7 @@ read_template: | .buffer_in_ready_i ( buffer_in_ready ) ); write_template: | - idma_axi_stream_write #( + idma_axis_write #( .StrbWidth ( StrbWidth ), .MaskInvalidData ( MaskInvalidData ), .byte_t ( byte_t ), @@ -241,7 +256,7 @@ write_template: | .write_meta_channel_t ( write_meta_channel_t ), .write_req_t ( ${req_t} ), .write_rsp_t ( ${rsp_t} ) - ) i_idma_axi_stream_write ( + ) i_idma_axis_write ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .w_dp_req_i ( w_dp_req_i ), @@ -256,8 +271,8 @@ write_template: | .aw_ready_o ( ${write_meta_ready} ), .write_req_o ( ${write_request} ), .write_rsp_i ( ${write_response} ), - .buffer_out_i ( ${buffer_out} ), - .buffer_out_valid_i ( ${buffer_out_valid} ), + .buffer_out_i ( buffer_out_shifted ), + .buffer_out_valid_i ( buffer_out_valid_shifted ), .buffer_out_ready_o ( ${buffer_out_ready} ) ); synth_wrapper_ports_read: | diff --git a/src/backend/database/idma_init.yaml b/src/db/idma_init.yml similarity index 90% rename from src/backend/database/idma_init.yaml rename to src/db/idma_init.yml index 3052e793..cde9b09a 100644 --- a/src/backend/database/idma_init.yaml +++ b/src/db/idma_init.yml @@ -1,14 +1,19 @@ # Copyright 2022 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# -# Tobias Senti -prefix: "init" -protocol_enum: "INIT" -full_name: "Initialisation Protocol" -bursts: "not_supported" -read_meta_channel: "req_chan" + +# Authors: +# - Tobias Senti + +prefix: "init" +protocol_enum: "INIT" +full_name: "Memory Init" +bursts: "not_supported" +legalizer_force_decouple: "false" +read_meta_channel: "req_chan" read_meta_channel_width: "localparam int unsigned init_req_chan_width = $bits(init_req_chan_t);" +combined_aw_and_w: "false" +read_slave: "false" typedefs: | typedef struct packed { logic [AddrWidth-1:0] cfg; @@ -46,6 +51,10 @@ read_bridge_template: | assign init_read_rsp.rsp_chan.init_value = {StrbWidth{8'h42}}; assign init_axi_read_req = '0; +legalizer_read_meta_channel: | + r_req_o.ar_req.init.req_chan = '{ + cfg: r_tf_q.base_addr + }; read_template: | idma_init_read #( .StrbWidth ( StrbWidth ), diff --git a/src/backend/database/idma_obi.yaml b/src/db/idma_obi.yml similarity index 88% rename from src/backend/database/idma_obi.yaml rename to src/db/idma_obi.yml index cef7b46c..4584b8f5 100644 --- a/src/backend/database/idma_obi.yaml +++ b/src/db/idma_obi.yml @@ -1,15 +1,19 @@ # Copyright 2022 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# -# Tobias Senti -prefix: "obi" -protocol_enum: "OBI" -full_name: "OBI" -bursts: "not_supported" -read_meta_channel: "a_chan" + +# Authors: +# - Tobias Senti + +prefix: "obi" +protocol_enum: "OBI" +full_name: "OBI" +bursts: "not_supported" +legalizer_force_decouple: "false" +read_meta_channel: "a_chan" write_meta_channel: "a_chan" -combined_aw_and_w: "true" +combined_aw_and_w: "true" +read_slave: "false" meta_channel_width: "localparam int unsigned obi_a_chan_width = $bits(obi_a_chan_t);" typedefs: | `IDMA_OBI_TYPEDEF_A_CHAN_T(obi_a_chan_t, addr_t, data_t, strb_t, id_t) @@ -35,6 +39,22 @@ bridge_template: | .axi_req_o ( obi_axi_${port}_req ), .axi_rsp_i ( obi_axi_${port}_rsp ) ); +legalizer_read_meta_channel: | + r_req_o.ar_req.obi.a_chan = '{ + addr: { r_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, + be: '1, + we: 1'b0, + wdata: '0, + aid: opt_tf_q.axi_id + }; +legalizer_write_meta_channel: | + w_req_o.aw_req.obi.a_chan = '{ + addr: { w_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, + be: '0, + we: 1, + wdata: '0, + aid: opt_tf_q.axi_id + }; read_template: | idma_obi_read #( .StrbWidth ( StrbWidth ), @@ -88,8 +108,8 @@ write_template: | .aw_ready_o ( ${write_meta_ready} ), .write_req_o ( ${write_request} ), .write_rsp_i ( ${write_response} ), - .buffer_out_i ( ${buffer_out} ), - .buffer_out_valid_i ( ${buffer_out_valid} ), + .buffer_out_i ( buffer_out_shifted ), + .buffer_out_valid_i ( buffer_out_valid_shifted ), .buffer_out_ready_o ( ${buffer_out_ready} ) ); synth_wrapper_ports_write: | diff --git a/src/backend/database/idma_tilelink.yaml b/src/db/idma_tilelink.yml similarity index 85% rename from src/backend/database/idma_tilelink.yaml rename to src/db/idma_tilelink.yml index 97620039..f5709576 100644 --- a/src/backend/database/idma_tilelink.yaml +++ b/src/db/idma_tilelink.yml @@ -1,18 +1,22 @@ # Copyright 2022 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# -# Tobias Senti -prefix: "tilelink" -protocol_enum: "TILELINK" -full_name: "TileLink-UH" -bursts: "only_pow2" -page_size: 2048 # limited by TLToAXI4 Bridge -> To be AXI compliant -> Less than 256 beats + +# Authors: +# - Tobias Senti + +prefix: "tilelink" +protocol_enum: "TILELINK" +full_name: "TileLink-UH" +bursts: "only_pow2" +page_size: 2048 # limited by TLToAXI4 Bridge -> To be AXI compliant -> Less than 256 beats tltoaxi4_compatibility_mode: "true" # If this is true burst will never cross a page boundary and only 32 beat write bursts -> Needed for TLToAXI4 Bridge -read_meta_channel: "a_chan" +legalizer_force_decouple: "true" # Forces the legalizer to decouple +read_meta_channel: "a_chan" write_meta_channel: "a_chan" meta_channel_width: "localparam int unsigned tilelink_a_chan_width = $bits(tilelink_a_chan_t);" -combined_aw_and_w: "true" +combined_aw_and_w: "true" +read_slave: "false" # logic[3:0] is the size field, is 4 bit as we're limited by the TLToAXI4 Bridge typedefs: | `IDMA_TILELINK_TYPEDEF_A_CHAN_T(tilelink_a_chan_t, addr_t, data_t, strb_t, logic[3:0], logic[4:0]) @@ -37,6 +41,49 @@ bridge_template: | .axi_req_o ( tilelink_axi_${port}_req ), .axi_rsp_i ( tilelink_axi_${port}_rsp ) ); +legalizer_read_meta_channel: | + r_req_o.ar_req.tilelink.a_chan = '{ + opcode: 3'd4, + param: 3'd0, + size: '0, + source: opt_tf_q.axi_id, + address: { r_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, + mask: '1, + data: '0, + corrupt: 1'b0 + }; + + for (int i = 0; i <= PageAddrWidth; i++) begin + if ((1 << i) == r_num_bytes) begin + r_req_o.ar_req.tilelink.a_chan.size = i; + end + end +legalizer_write_meta_channel: | + w_req_o.aw_req.tilelink.a_chan = '{ + opcode: 3'd1, + param: 3'd0, + size: '0, + source: opt_tf_q.axi_id, + address: { w_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} }, + mask: '0, + data: '0, + corrupt: 1'b0 + }; + + for (int i = 0; i < PageAddrWidth; i++) begin + if ((1 << i) == w_num_bytes) begin + w_req_o.aw_req.tilelink.a_chan.size = i; + end + end +legalizer_write_data_path: | + w_req_o.w_dp_req = '{ + dst_protocol: opt_tf_q.dst_protocol, + offset: w_addr_offset, + tailer: OffsetWidth'(w_num_bytes + w_addr_offset), + shift: opt_tf_q.write_shift, + num_beats: 'd0, + is_single: w_num_bytes <= StrbWidth + }; read_template: | idma_tilelink_read #( .BurstLength ( ${database['tilelink']['page_size']} ), @@ -101,8 +148,8 @@ write_template: | .write_meta_ready_o ( ${write_meta_ready} ), .write_req_o ( ${write_request} ), .write_rsp_i ( ${write_response} ), - .buffer_out_i ( ${buffer_out} ), - .buffer_out_valid_i ( ${buffer_out_valid} ), + .buffer_out_i ( buffer_out_shifted ), + .buffer_out_valid_i ( buffer_out_valid_shifted ), .buffer_out_ready_o ( ${buffer_out_ready} ) ); synth_wrapper_ports_write: | diff --git a/src/frontends/desc64/idma_desc64_frontend.hjson b/src/frontends/desc64/idma_desc64.hjson similarity index 91% rename from src/frontends/desc64/idma_desc64_frontend.hjson rename to src/frontends/desc64/idma_desc64.hjson index 5266c290..44218f2a 100644 --- a/src/frontends/desc64/idma_desc64_frontend.hjson +++ b/src/frontends/desc64/idma_desc64.hjson @@ -1,9 +1,9 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Licensed under Solderpad Hardware License, Version 0.51 -// Axel Vanoni +// Authors: +// - Axel Vanoni { name: idma_desc64 diff --git a/src/frontends/desc64/idma_desc64_frontend.h b/src/frontends/desc64/idma_desc64_frontend.h deleted file mode 100644 index 01b536b4..00000000 --- a/src/frontends/desc64/idma_desc64_frontend.h +++ /dev/null @@ -1,31 +0,0 @@ -// Generated register defines for idma_desc64 - -// Copyright information found in source file: -// Copyright 2022 ETH Zurich and University of Bologna. - -// Licensing information found in source file: -// Licensed under Solderpad Hardware License, Version 0.51 -// SPDX-License-Identifier: SHL-0.51 - -#ifndef _IDMA_DESC64_REG_DEFS_ -#define _IDMA_DESC64_REG_DEFS_ - -#ifdef __cplusplus -extern "C" { -#endif -// Register width -#define IDMA_DESC64_PARAM_REG_WIDTH 64 - -// This register specifies the bus address at which the first transfer -#define IDMA_DESC64_DESC_ADDR_REG_OFFSET 0x0 - -// This register contains status information for the DMA. -#define IDMA_DESC64_STATUS_REG_OFFSET 0x8 -#define IDMA_DESC64_STATUS_BUSY_BIT 0 -#define IDMA_DESC64_STATUS_FIFO_FULL_BIT 1 - -#ifdef __cplusplus -} // extern "C" -#endif -#endif // _IDMA_DESC64_REG_DEFS_ -// End generated register defines for idma_desc64 \ No newline at end of file diff --git a/src/frontends/desc64/idma_desc64_frontend.html b/src/frontends/desc64/idma_desc64_frontend.html deleted file mode 100644 index 9689429a..00000000 --- a/src/frontends/desc64/idma_desc64_frontend.html +++ /dev/null @@ -1,46 +0,0 @@ - - - - - - - - - - -
-
idma_desc64.desc_addr @ 0x0
-

This register specifies the bus address at which the first transfer -descriptor can be found. A write to this register starts the transfer.

-
Reset default = 0xffffffffffffffff, mask 0xffffffffffffffff
-
- - - - - - -
63626160595857565554535251504948
desc_addr...
47464544434241403938373635343332
...desc_addr...
31302928272625242322212019181716
...desc_addr...
1514131211109876543210
...desc_addr
BitsTypeResetNameDescription
63:0wo0xffffffffffffffffdesc_addr
-
- - - - - -
-
idma_desc64.status @ 0x8
-

This register contains status information for the DMA.

-
Reset default = 0x0, mask 0x3
-
- - - - - - - - -
63626160595857565554535251504948
 
47464544434241403938373635343332
 
31302928272625242322212019181716
 
1514131211109876543210
 fifo_fullbusy
BitsTypeResetNameDescription
0ro0x0busy

The DMA is busy

1ro0x0fifo_full

If this bit is set, the buffers of the DMA are full. Any further submissions via the -desc_addr register may overwrite previously submitted jobs or get lost.

-
- diff --git a/src/frontends/desc64/idma_desc64_reg_pkg.sv b/src/frontends/desc64/idma_desc64_reg_pkg.sv deleted file mode 100644 index cb0408b0..00000000 --- a/src/frontends/desc64/idma_desc64_reg_pkg.sv +++ /dev/null @@ -1,59 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Package auto-generated by `reggen` containing data structure - -package idma_desc64_reg_pkg; - - // Address widths within the block - parameter int BlockAw = 4; - - //////////////////////////// - // Typedefs for registers // - //////////////////////////// - - typedef struct packed { - logic [63:0] q; - logic qe; - } idma_desc64_reg2hw_desc_addr_reg_t; - - typedef struct packed { - struct packed { - logic d; - logic de; - } busy; - struct packed { - logic d; - logic de; - } fifo_full; - } idma_desc64_hw2reg_status_reg_t; - - // Register -> HW type - typedef struct packed { - idma_desc64_reg2hw_desc_addr_reg_t desc_addr; // [64:0] - } idma_desc64_reg2hw_t; - - // HW -> register type - typedef struct packed { - idma_desc64_hw2reg_status_reg_t status; // [3:0] - } idma_desc64_hw2reg_t; - - // Register offsets - parameter logic [BlockAw-1:0] IDMA_DESC64_DESC_ADDR_OFFSET = 4'h 0; - parameter logic [BlockAw-1:0] IDMA_DESC64_STATUS_OFFSET = 4'h 8; - - // Register index - typedef enum int { - IDMA_DESC64_DESC_ADDR, - IDMA_DESC64_STATUS - } idma_desc64_id_e; - - // Register width information to check illegal writes - parameter logic [3:0] IDMA_DESC64_PERMIT [2] = '{ - 4'b 1111, // index[0] IDMA_DESC64_DESC_ADDR - 4'b 0001 // index[1] IDMA_DESC64_STATUS - }; - -endpackage - diff --git a/src/frontends/desc64/idma_desc64_reg_top.sv b/src/frontends/desc64/idma_desc64_reg_top.sv deleted file mode 100644 index 9461431b..00000000 --- a/src/frontends/desc64/idma_desc64_reg_top.sv +++ /dev/null @@ -1,207 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Top module auto-generated by `reggen` - - -`include "common_cells/assertions.svh" - -module idma_desc64_reg_top #( - parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic, - parameter int AW = 4 -) ( - input clk_i, - input rst_ni, - input reg_req_t reg_req_i, - output reg_rsp_t reg_rsp_o, - // To HW - output idma_desc64_reg_pkg::idma_desc64_reg2hw_t reg2hw, // Write - input idma_desc64_reg_pkg::idma_desc64_hw2reg_t hw2reg, // Read - - - // Config - input devmode_i // If 1, explicit error return for unmapped register access -); - - import idma_desc64_reg_pkg::* ; - - localparam int DW = 64; - localparam int DBW = DW/8; // Byte Width - - // register signals - logic reg_we; - logic reg_re; - logic [AW-1:0] reg_addr; - logic [DW-1:0] reg_wdata; - logic [DBW-1:0] reg_be; - logic [DW-1:0] reg_rdata; - logic reg_error; - - logic addrmiss, wr_err; - - logic [DW-1:0] reg_rdata_next; - - // Below register interface can be changed - reg_req_t reg_intf_req; - reg_rsp_t reg_intf_rsp; - - - assign reg_intf_req = reg_req_i; - assign reg_rsp_o = reg_intf_rsp; - - - assign reg_we = reg_intf_req.valid & reg_intf_req.write; - assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; - assign reg_addr = reg_intf_req.addr; - assign reg_wdata = reg_intf_req.wdata; - assign reg_be = reg_intf_req.wstrb; - assign reg_intf_rsp.rdata = reg_rdata; - assign reg_intf_rsp.error = reg_error; - assign reg_intf_rsp.ready = 1'b1; - - assign reg_rdata = reg_rdata_next ; - assign reg_error = (devmode_i & addrmiss) | wr_err; - - - // Define SW related signals - // Format: __{wd|we|qs} - // or _{wd|we|qs} if field == 1 or 0 - logic [63:0] desc_addr_wd; - logic desc_addr_we; - logic status_busy_qs; - logic status_fifo_full_qs; - - // Register instances - // R[desc_addr]: V(False) - - prim_subreg #( - .DW (64), - .SWACCESS("WO"), - .RESVAL (64'hffffffffffffffff) - ) u_desc_addr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (desc_addr_we), - .wd (desc_addr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (reg2hw.desc_addr.qe), - .q (reg2hw.desc_addr.q ), - - .qs () - ); - - - // R[status]: V(False) - - // F[busy]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RO"), - .RESVAL (1'h0) - ) u_status_busy ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (hw2reg.status.busy.de), - .d (hw2reg.status.busy.d ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (status_busy_qs) - ); - - - // F[fifo_full]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RO"), - .RESVAL (1'h0) - ) u_status_fifo_full ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (hw2reg.status.fifo_full.de), - .d (hw2reg.status.fifo_full.d ), - - // to internal hardware - .qe (), - .q (), - - // to register interface (read) - .qs (status_fifo_full_qs) - ); - - - - - logic [1:0] addr_hit; - always_comb begin - addr_hit = '0; - addr_hit[0] = (reg_addr == IDMA_DESC64_DESC_ADDR_OFFSET); - addr_hit[1] = (reg_addr == IDMA_DESC64_STATUS_OFFSET); - end - - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - - // Check sub-word write is permitted - always_comb begin - wr_err = (reg_we & - ((addr_hit[0] & (|(IDMA_DESC64_PERMIT[0] & ~reg_be))) | - (addr_hit[1] & (|(IDMA_DESC64_PERMIT[1] & ~reg_be))))); - end - - assign desc_addr_we = addr_hit[0] & reg_we & !reg_error; - assign desc_addr_wd = reg_wdata[63:0]; - - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[63:0] = '0; - end - - addr_hit[1]: begin - reg_rdata_next[0] = status_busy_qs; - reg_rdata_next[1] = status_fifo_full_qs; - end - - default: begin - reg_rdata_next = '1; - end - endcase - end - - // Unused signal tieoff - - // wdata / byte enable are not always fully used - // add a blanket unused statement to handle lint waivers - logic unused_wdata; - logic unused_be; - assign unused_wdata = ^reg_wdata; - assign unused_be = ^reg_be; - - // Assertions for Register Interface - `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) - -endmodule diff --git a/src/frontends/desc64/idma_desc64_reg_wrapper.sv b/src/frontends/desc64/idma_desc64_reg_wrapper.sv index 24457b24..0a1e61af 100644 --- a/src/frontends/desc64/idma_desc64_reg_wrapper.sv +++ b/src/frontends/desc64/idma_desc64_reg_wrapper.sv @@ -2,12 +2,11 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Axel Vanoni +// Authors: +// - Axel Vanoni `include "common_cells/registers.svh" - - /// This module implements backpressure via ready/valid handshakes /// for the regbus registers and exposes it to the descriptor fifo module idma_desc64_reg_wrapper diff --git a/src/frontends/desc64/idma_desc64_shared_counter.sv b/src/frontends/desc64/idma_desc64_shared_counter.sv index 52da6481..31d3a7ad 100644 --- a/src/frontends/desc64/idma_desc64_shared_counter.sv +++ b/src/frontends/desc64/idma_desc64_shared_counter.sv @@ -2,7 +2,8 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Axel Vanoni +// Authors: +// - Axel Vanoni `include "common_cells/registers.svh" /// This module allows two domains to share a counter diff --git a/src/frontends/desc64/idma_desc64_synth.sv b/src/frontends/desc64/idma_desc64_synth.sv index 1488d310..a7b556ae 100644 --- a/src/frontends/desc64/idma_desc64_synth.sv +++ b/src/frontends/desc64/idma_desc64_synth.sv @@ -2,9 +2,10 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Axel Vanoni +// Authors: +// - Axel Vanoni -// synth wrapper +/// synth wrapper module idma_desc64_synth #( parameter int unsigned AddrWidth = idma_desc64_synth_pkg::AddrWidth, parameter type burst_req_t = idma_desc64_synth_pkg::burst_req_t, diff --git a/src/frontends/desc64/idma_desc64_synth_pkg.sv b/src/frontends/desc64/idma_desc64_synth_pkg.sv index ba08d9a4..1e6b48de 100644 --- a/src/frontends/desc64/idma_desc64_synth_pkg.sv +++ b/src/frontends/desc64/idma_desc64_synth_pkg.sv @@ -2,9 +2,10 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Axel Vanoni +// Authors: +// - Axel Vanoni -// synth package +/// synth package package idma_desc64_synth_pkg; `include "register_interface/typedef.svh" diff --git a/src/frontends/desc64/idma_desc64_top.sv b/src/frontends/desc64/idma_desc64_top.sv index fdda4570..03ee42b7 100644 --- a/src/frontends/desc64/idma_desc64_top.sv +++ b/src/frontends/desc64/idma_desc64_top.sv @@ -2,7 +2,8 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Axel Vanoni +// Authors: +// - Axel Vanoni `include "common_cells/registers.svh" @@ -194,17 +195,18 @@ module idma_desc64_top #( // }}} descriptor addr input to fifo // {{{ submitter FSM - assign desc_addr_from_input_fifo_ready = submitter_q == SubmitterIdle; - assign submitter_input_fifo_valid = desc_addr_from_input_fifo_valid; - - assign pending_descriptor_to_fifo_valid = submitter_pending_fifo_valid_q; - assign submitter_master_req.addr = submitter_current_addr_q + (submitter_fetch_counter_q << 3); - assign submitter_master_req.write = '0; - assign submitter_master_req.wdata = '0; - assign submitter_master_req.wstrb = '0; - assign submitter_master_req.valid = submitter_q == SubmitterFetchDescriptor; - - assign pending_descriptor_to_fifo_data.do_irq = submitter_current_descriptor_q.flags[0]; + assign desc_addr_from_input_fifo_ready = submitter_q == SubmitterIdle; + assign submitter_input_fifo_valid = desc_addr_from_input_fifo_valid; + + assign pending_descriptor_to_fifo_valid = submitter_pending_fifo_valid_q; + assign submitter_master_req.addr = submitter_current_addr_q + + (submitter_fetch_counter_q << 3); + assign submitter_master_req.write = '0; + assign submitter_master_req.wdata = '0; + assign submitter_master_req.wstrb = '0; + assign submitter_master_req.valid = submitter_q == SubmitterFetchDescriptor; + + assign pending_descriptor_to_fifo_data.do_irq = submitter_current_descriptor_q.flags[0]; assign pending_descriptor_to_fifo_data.descriptor_addr = submitter_current_addr_q; always_comb begin : proc_submitter_burst_req @@ -271,8 +273,8 @@ module idma_desc64_top #( submitter_fetch_counter_d = submitter_fetch_counter_q + 1; unique case (submitter_fetch_counter_q) 2'b00: begin - submitter_current_descriptor_d.flags = submitter_master_rsp.rdata[63:32]; - submitter_current_descriptor_d.length = submitter_master_rsp.rdata[31:0]; + submitter_current_descriptor_d.flags = submitter_master_rsp.rdata[63:32]; + submitter_current_descriptor_d.length = submitter_master_rsp.rdata[31:0]; end 2'b01: begin submitter_current_descriptor_d.next = submitter_master_rsp.rdata; diff --git a/src/frontends/desc64/reg_html.css b/src/frontends/desc64/reg_html.css deleted file mode 100644 index 4cb48edb..00000000 --- a/src/frontends/desc64/reg_html.css +++ /dev/null @@ -1,74 +0,0 @@ -/* Stylesheet for reggen HTML register output */ -/* Copyright lowRISC contributors. */ -/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ -/* SPDX-License-Identifier: Apache-2.0 */ - -table.regpic { - width: 95%; - border-collapse: collapse; - margin-left:auto; - margin-right:auto; - table-layout:fixed; -} - -table.regdef { - border: 1px solid black; - width: 80%; - border-collapse: collapse; - margin-left:auto; - margin-right:auto; - table-layout:auto; -} - -table.regdef th { - border: 1px solid black; - font-family: sans-serif; - -} - -td.bitnum { - font-size: 60%; - text-align: center; -} - -td.unused { - border: 1px solid black; - background-color: gray; -} - -td.fname { - border: 1px solid black; - text-align: center; - font-family: sans-serif; -} - - -td.regbits, td.regperm, td.regrv { - border: 1px solid black; - text-align: center; - font-family: sans-serif; -} - -td.regde, td.regfn { - border: 1px solid black; -} - -table.cfgtable { - border: 1px solid black; - width: 80%; - border-collapse: collapse; - margin-left:auto; - margin-right:auto; - table-layout:auto; -} - -table.cfgtable th { - border: 1px solid black; - font-family: sans-serif; - font-weight: bold; -} - -table.cfgtable td { - border: 1px solid black; - font-family: sans-serif; -} diff --git a/src/frontends/idma_transfer_id_gen.sv b/src/frontends/idma_transfer_id_gen.sv index 5a801dd3..8656e354 100644 --- a/src/frontends/idma_transfer_id_gen.sv +++ b/src/frontends/idma_transfer_id_gen.sv @@ -2,7 +2,8 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Author: Thomas Benz +// Authors: +// - Thomas Benz /// DMA transaction id generator. Increases the transaction id on every request. diff --git a/src/frontends/snitch/axi_dma_error_handler.sv b/src/frontends/inst64/axi_dma_error_handler.sv similarity index 97% rename from src/frontends/snitch/axi_dma_error_handler.sv rename to src/frontends/inst64/axi_dma_error_handler.sv index 5a9fab2e..a11bf3db 100644 --- a/src/frontends/snitch/axi_dma_error_handler.sv +++ b/src/frontends/inst64/axi_dma_error_handler.sv @@ -2,11 +2,11 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Thomas Benz - -// Sample implementation to report errors from the AXI bus. -// This module provides the address of errors on a handshaked interface +// Authors: +// - Thomas Benz +/// Sample implementation to report errors from the AXI bus. +/// This module provides the address of errors on a handshaked interface module axi_dma_error_handler #( parameter int unsigned ADDR_WIDTH = -1, parameter int unsigned BUFFER_DEPTH = -1, diff --git a/src/frontends/snitch/axi_dma_perf_counters.sv b/src/frontends/inst64/axi_dma_perf_counters.sv similarity index 98% rename from src/frontends/snitch/axi_dma_perf_counters.sv rename to src/frontends/inst64/axi_dma_perf_counters.sv index e46e9c78..c28c9668 100644 --- a/src/frontends/snitch/axi_dma_perf_counters.sv +++ b/src/frontends/inst64/axi_dma_perf_counters.sv @@ -2,11 +2,12 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Thomas Benz +// Authors: +// - Thomas Benz `include "common_cells/registers.svh" -// Sample implementation of performance counters. +/// Sample implementation of performance counters. module axi_dma_perf_counters #( parameter int unsigned TRANSFER_ID_WIDTH = -1, parameter int unsigned DATA_WIDTH = -1, diff --git a/src/frontends/snitch/axi_dma_pkg.sv b/src/frontends/inst64/axi_dma_pkg.sv similarity index 82% rename from src/frontends/snitch/axi_dma_pkg.sv rename to src/frontends/inst64/axi_dma_pkg.sv index 06cdd0a1..a45ec7d1 100644 --- a/src/frontends/snitch/axi_dma_pkg.sv +++ b/src/frontends/inst64/axi_dma_pkg.sv @@ -2,12 +2,13 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Thomas Benz +// Authors: +// - Thomas Benz `include "axi/typedef.svh" -// for now this is an extended copy of the axi_pkg -// eventually the DMA specific parts should be moved in axi_pkg aswell +/// for now this is an extended copy of the axi_pkg +/// eventually the DMA specific parts should be moved in axi_pkg aswell package axi_dma_pkg; typedef struct packed { diff --git a/src/frontends/snitch/axi_dma_tc_snitch_fe.sv b/src/frontends/inst64/axi_dma_tc_snitch_fe.sv similarity index 98% rename from src/frontends/snitch/axi_dma_tc_snitch_fe.sv rename to src/frontends/inst64/axi_dma_tc_snitch_fe.sv index 1ee35d20..73b9158b 100644 --- a/src/frontends/snitch/axi_dma_tc_snitch_fe.sv +++ b/src/frontends/inst64/axi_dma_tc_snitch_fe.sv @@ -2,13 +2,13 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Thomas Benz - -// Implements the tightly-coupled frontend. This module can directly be connected -// to an accelerator bus in the snitch system +// Authors: +// - Thomas Benz `include "common_cells/registers.svh" +/// Implements the tightly-coupled frontend. This module can directly be connected +/// to an accelerator bus in the snitch system module axi_dma_tc_snitch_fe #( parameter int unsigned AddrWidth = 0, parameter int unsigned DataWidth = 0, diff --git a/src/frontends/snitch/sdma_synth_wrapper.sv b/src/frontends/inst64/sdma_synth_wrapper.sv similarity index 94% rename from src/frontends/snitch/sdma_synth_wrapper.sv rename to src/frontends/inst64/sdma_synth_wrapper.sv index cb90c38b..20af4249 100644 --- a/src/frontends/snitch/sdma_synth_wrapper.sv +++ b/src/frontends/inst64/sdma_synth_wrapper.sv @@ -2,10 +2,10 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Thomas Benz - -// defines a type for the axi bus to allow a ooc synthesis +// Authors: +// - Thomas Benz +/// defines a type for the axi bus to allow a ooc synthesis module sdma_synth_wrapper ( input logic clk_i, diff --git a/src/frontends/register_32bit_2d/idma_reg32_2d_frontend.hjson b/src/frontends/reg32_2d/idma_reg32_2d.hjson similarity index 97% rename from src/frontends/register_32bit_2d/idma_reg32_2d_frontend.hjson rename to src/frontends/reg32_2d/idma_reg32_2d.hjson index 9e7c8b73..9f6aefde 100644 --- a/src/frontends/register_32bit_2d/idma_reg32_2d_frontend.hjson +++ b/src/frontends/reg32_2d/idma_reg32_2d.hjson @@ -1,10 +1,12 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Licensed under Solderpad Hardware License, Version 0.51 + +// Authors: +// - Michael Rogenmoser -// -// Description: DMA frontend module that includes 32bit config and status reg handling for 2d transfers -module idma_reg32_2d_frontend #( +// Authors: +// - Michael Rogenmoser + +/// Description: DMA frontend module that includes 32bit config and status reg handling for 2d transfers +module idma_reg32_2d #( /// Number of configuration register ports parameter int unsigned NumRegs = 1, /// address width of the DMA Transfer ID counter @@ -33,8 +33,8 @@ module idma_reg32_2d_frontend #( localparam int unsigned DmaRegisterWidth = 32; - idma_reg32_2d_frontend_reg_pkg::idma_reg32_2d_frontend_reg2hw_t [NumRegs-1:0] dma_reg2hw; - idma_reg32_2d_frontend_reg_pkg::idma_reg32_2d_frontend_hw2reg_t [NumRegs-1:0] dma_hw2reg; + idma_reg32_2d_reg_pkg::idma_reg32_2d_reg2hw_t [NumRegs-1:0] dma_reg2hw; + idma_reg32_2d_reg_pkg::idma_reg32_2d_hw2reg_t [NumRegs-1:0] dma_hw2reg; logic [IdCounterWidth-1:0] next_id, done_id; logic issue; @@ -47,7 +47,7 @@ module idma_reg32_2d_frontend #( for (genvar i = 0; i < NumRegs; i++) begin : gen_core_regs - idma_reg32_2d_frontend_reg_top #( + idma_reg32_2d_reg_top #( .reg_req_t ( dma_regs_req_t ), .reg_rsp_t ( dma_regs_rsp_t ) ) i_dma_conf_regs ( diff --git a/src/frontends/register_64bit/idma_reg64_frontend.hjson b/src/frontends/reg64/idma_reg64.hjson similarity index 96% rename from src/frontends/register_64bit/idma_reg64_frontend.hjson rename to src/frontends/reg64/idma_reg64.hjson index 8ad337d3..eb0fc843 100644 --- a/src/frontends/register_64bit/idma_reg64_frontend.hjson +++ b/src/frontends/reg64/idma_reg64.hjson @@ -1,10 +1,12 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Licensed under Solderpad Hardware License, Version 0.51 + +// Authors: +// - Michael Rogenmoser -// -// Description: DMA frontend module that includes 64bit config and status reg handling -module idma_reg64_frontend #( +// Authors: +// - Michael Rogenmoser -// -// Description: 2D DMA frontend module that includes 64bit config and status reg handling -module idma_reg64_2d_frontend #( +// Authors: +// - Michael Rogenmoser + +/// 2D DMA frontend module that includes 64bit config and status reg handling +module idma_reg64_2d #( /// register_interface request type parameter type dma_regs_req_t = logic, /// register_interface response type @@ -33,8 +33,8 @@ module idma_reg64_2d_frontend #( /* * Signal and register definitions */ - idma_reg64_2d_frontend_reg_pkg::idma_reg64_2d_frontend_reg2hw_t dma_reg2hw; - idma_reg64_2d_frontend_reg_pkg::idma_reg64_2d_frontend_hw2reg_t dma_hw2reg; + idma_reg64_2d_reg_pkg::idma_reg64_2d_reg2hw_t dma_reg2hw; + idma_reg64_2d_reg_pkg::idma_reg64_2d_hw2reg_t dma_hw2reg; // transaction id logic [DmaRegisterWidth-1:0] next_id, done_id; @@ -47,7 +47,7 @@ module idma_reg64_2d_frontend #( /* * DMA registers */ - idma_reg64_2d_frontend_reg_top #( + idma_reg64_2d_reg_top #( .reg_req_t( dma_regs_req_t ), .reg_rsp_t( dma_regs_rsp_t ) ) i_dma_conf_regs ( @@ -160,4 +160,4 @@ module idma_reg64_2d_frontend #( .completed_o ( done_id ) ); -endmodule : idma_reg64_2d_frontend +endmodule diff --git a/src/frontends/register_32bit_2d/idma_reg32_2d_frontend.h b/src/frontends/register_32bit_2d/idma_reg32_2d_frontend.h deleted file mode 100644 index 8554cc05..00000000 --- a/src/frontends/register_32bit_2d/idma_reg32_2d_frontend.h +++ /dev/null @@ -1,75 +0,0 @@ -// Generated register defines for idma_reg32_2d_frontend - -// Copyright information found in source file: -// Copyright 2022 ETH Zurich and University of Bologna. - -// Licensing information found in source file: -// Licensed under Solderpad Hardware License, Version 0.51 -// SPDX-License-Identifier: SHL-0.51 - -#ifndef _IDMA_REG32_2D_FRONTEND_REG_DEFS_ -#define _IDMA_REG32_2D_FRONTEND_REG_DEFS_ - -#ifdef __cplusplus -extern "C" { -#endif -// Register width -#define IDMA_REG32_2D_FRONTEND_PARAM_REG_WIDTH 32 - -// Source Protocol -#define IDMA_REG32_2D_FRONTEND_SRC_PROTOCOL_REG_OFFSET 0x0 -#define IDMA_REG32_2D_FRONTEND_SRC_PROTOCOL_SRC_PROTOCOL_MASK 0x3 -#define IDMA_REG32_2D_FRONTEND_SRC_PROTOCOL_SRC_PROTOCOL_OFFSET 0 -#define IDMA_REG32_2D_FRONTEND_SRC_PROTOCOL_SRC_PROTOCOL_FIELD \ - ((bitfield_field32_t) { .mask = IDMA_REG32_2D_FRONTEND_SRC_PROTOCOL_SRC_PROTOCOL_MASK, .index = IDMA_REG32_2D_FRONTEND_SRC_PROTOCOL_SRC_PROTOCOL_OFFSET }) - -// Destination Protocol -#define IDMA_REG32_2D_FRONTEND_DST_PROTOCOL_REG_OFFSET 0x4 -#define IDMA_REG32_2D_FRONTEND_DST_PROTOCOL_DST_PROTOCOL_MASK 0x3 -#define IDMA_REG32_2D_FRONTEND_DST_PROTOCOL_DST_PROTOCOL_OFFSET 0 -#define IDMA_REG32_2D_FRONTEND_DST_PROTOCOL_DST_PROTOCOL_FIELD \ - ((bitfield_field32_t) { .mask = IDMA_REG32_2D_FRONTEND_DST_PROTOCOL_DST_PROTOCOL_MASK, .index = IDMA_REG32_2D_FRONTEND_DST_PROTOCOL_DST_PROTOCOL_OFFSET }) - -// Source Address -#define IDMA_REG32_2D_FRONTEND_SRC_ADDR_REG_OFFSET 0x8 - -// Destination Address -#define IDMA_REG32_2D_FRONTEND_DST_ADDR_REG_OFFSET 0xc - -// Number of bytes -#define IDMA_REG32_2D_FRONTEND_NUM_BYTES_REG_OFFSET 0x10 - -// Configuration Register for DMA settings -#define IDMA_REG32_2D_FRONTEND_CONF_REG_OFFSET 0x14 -#define IDMA_REG32_2D_FRONTEND_CONF_DECOUPLE_BIT 0 -#define IDMA_REG32_2D_FRONTEND_CONF_DEBURST_BIT 1 -#define IDMA_REG32_2D_FRONTEND_CONF_SERIALIZE_BIT 2 -#define IDMA_REG32_2D_FRONTEND_CONF_TWOD_BIT 3 - -// Source Stride -#define IDMA_REG32_2D_FRONTEND_STRIDE_SRC_REG_OFFSET 0x18 - -// Destination Stride -#define IDMA_REG32_2D_FRONTEND_STRIDE_DST_REG_OFFSET 0x1c - -// Number of 2D repetitions -#define IDMA_REG32_2D_FRONTEND_NUM_REPETITIONS_REG_OFFSET 0x20 - -// DMA Status -#define IDMA_REG32_2D_FRONTEND_STATUS_REG_OFFSET 0x24 -#define IDMA_REG32_2D_FRONTEND_STATUS_BUSY_MASK 0xffff -#define IDMA_REG32_2D_FRONTEND_STATUS_BUSY_OFFSET 0 -#define IDMA_REG32_2D_FRONTEND_STATUS_BUSY_FIELD \ - ((bitfield_field32_t) { .mask = IDMA_REG32_2D_FRONTEND_STATUS_BUSY_MASK, .index = IDMA_REG32_2D_FRONTEND_STATUS_BUSY_OFFSET }) - -// Next ID, launches transfer, returns 0 if transfer not set up properly. -#define IDMA_REG32_2D_FRONTEND_NEXT_ID_REG_OFFSET 0x28 - -// Get ID of finished transactions. -#define IDMA_REG32_2D_FRONTEND_DONE_REG_OFFSET 0x2c - -#ifdef __cplusplus -} // extern "C" -#endif -#endif // _IDMA_REG32_2D_FRONTEND_REG_DEFS_ -// End generated register defines for idma_reg32_2d_frontend \ No newline at end of file diff --git a/src/frontends/register_32bit_2d/idma_reg32_2d_frontend.html b/src/frontends/register_32bit_2d/idma_reg32_2d_frontend.html deleted file mode 100644 index 744549fd..00000000 --- a/src/frontends/register_32bit_2d/idma_reg32_2d_frontend.html +++ /dev/null @@ -1,180 +0,0 @@ - - - - - - - - - - -
-
idma_reg32_2d_frontend.src_protocol @ 0x0
-

Source Protocol

-
Reset default = 0x0, mask 0x3
-
- - - -
31302928272625242322212019181716
 
1514131211109876543210
 src_protocol
BitsTypeResetNameDescription
1:0rwxsrc_protocol

Source Protocol

-
- - - - - -
-
idma_reg32_2d_frontend.dst_protocol @ 0x4
-

Destination Protocol

-
Reset default = 0x0, mask 0x3
-
- - - -
31302928272625242322212019181716
 
1514131211109876543210
 dst_protocol
BitsTypeResetNameDescription
1:0rwxdst_protocol

Destination Protocol

-
- - - - - -
-
idma_reg32_2d_frontend.src_addr @ 0x8
-

Source Address

-
Reset default = 0x0, mask 0xffffffff
-
- - -
31302928272625242322212019181716
src_addr...
1514131211109876543210
...src_addr
BitsTypeResetNameDescription
31:0rwxsrc_addr

Source Address

-
- - - - - -
-
idma_reg32_2d_frontend.dst_addr @ 0xc
-

Destination Address

-
Reset default = 0x0, mask 0xffffffff
-
- - -
31302928272625242322212019181716
dst_addr...
1514131211109876543210
...dst_addr
BitsTypeResetNameDescription
31:0rwxdst_addr

Destination Address

-
- - - - - -
-
idma_reg32_2d_frontend.num_bytes @ 0x10
-

Number of bytes

-
Reset default = 0x0, mask 0xffffffff
-
- - -
31302928272625242322212019181716
num_bytes...
1514131211109876543210
...num_bytes
BitsTypeResetNameDescription
31:0rwxnum_bytes

Number of bytes

-
- - - - - -
-
idma_reg32_2d_frontend.conf @ 0x14
-

Configuration Register for DMA settings

-
Reset default = 0x0, mask 0xf
-
- - - - - - -
31302928272625242322212019181716
 
1514131211109876543210
 twodserializedeburstdecouple
BitsTypeResetNameDescription
0rwxdecouple

Decouple enable

1rwxdeburst

Deburst enable

2rwxserialize

Serialize enable

3rwxtwod

2D transfer

-
- - - - - -
-
idma_reg32_2d_frontend.stride_src @ 0x18
-

Source Stride

-
Reset default = 0x0, mask 0xffffffff
-
- - -
31302928272625242322212019181716
stride_src...
1514131211109876543210
...stride_src
BitsTypeResetNameDescription
31:0rwxstride_src

Source Stride

-
- - - - - -
-
idma_reg32_2d_frontend.stride_dst @ 0x1c
-

Destination Stride

-
Reset default = 0x0, mask 0xffffffff
-
- - -
31302928272625242322212019181716
stride_dst...
1514131211109876543210
...stride_dst
BitsTypeResetNameDescription
31:0rwxstride_dst

Destination Stride

-
- - - - - -
-
idma_reg32_2d_frontend.num_repetitions @ 0x20
-

Number of 2D repetitions

-
Reset default = 0x1, mask 0xffffffff
-
- - -
31302928272625242322212019181716
num_repetitions...
1514131211109876543210
...num_repetitions
BitsTypeResetNameDescription
31:0rw0x1num_repetitions

Number of 2D repetitions

-
- - - - - -
-
idma_reg32_2d_frontend.status @ 0x24
-

DMA Status

-
Reset default = 0x0, mask 0xffff
-
- - -
31302928272625242322212019181716
 
1514131211109876543210
busy
BitsTypeResetNameDescription
15:0roxbusy

DMA busy

-
- - - - - -
-
idma_reg32_2d_frontend.next_id @ 0x28
-

Next ID, launches transfer, returns 0 if transfer not set up properly.

-
Reset default = 0x0, mask 0xffffffff
-
- - -
31302928272625242322212019181716
next_id...
1514131211109876543210
...next_id
BitsTypeResetNameDescription
31:0roxnext_id

Next ID, launches transfer, returns 0 if transfer not set up properly.

-
- - - - - -
-
idma_reg32_2d_frontend.done @ 0x2c
-

Get ID of finished transactions.

-
Reset default = 0x0, mask 0xffffffff
-
- - -
31302928272625242322212019181716
done...
1514131211109876543210
...done
BitsTypeResetNameDescription
31:0roxdone

Get ID of finished transactions.

-
- diff --git a/src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_pkg.sv b/src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_pkg.sv deleted file mode 100644 index e3e5da7e..00000000 --- a/src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_pkg.sv +++ /dev/null @@ -1,159 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Package auto-generated by `reggen` containing data structure - -package idma_reg32_2d_frontend_reg_pkg; - - // Address widths within the block - parameter int BlockAw = 6; - - //////////////////////////// - // Typedefs for registers // - //////////////////////////// - - typedef struct packed { - logic [1:0] q; - } idma_reg32_2d_frontend_reg2hw_src_protocol_reg_t; - - typedef struct packed { - logic [1:0] q; - } idma_reg32_2d_frontend_reg2hw_dst_protocol_reg_t; - - typedef struct packed { - logic [31:0] q; - } idma_reg32_2d_frontend_reg2hw_src_addr_reg_t; - - typedef struct packed { - logic [31:0] q; - } idma_reg32_2d_frontend_reg2hw_dst_addr_reg_t; - - typedef struct packed { - logic [31:0] q; - } idma_reg32_2d_frontend_reg2hw_num_bytes_reg_t; - - typedef struct packed { - struct packed { - logic q; - } decouple; - struct packed { - logic q; - } deburst; - struct packed { - logic q; - } serialize; - struct packed { - logic q; - } twod; - } idma_reg32_2d_frontend_reg2hw_conf_reg_t; - - typedef struct packed { - logic [31:0] q; - } idma_reg32_2d_frontend_reg2hw_stride_src_reg_t; - - typedef struct packed { - logic [31:0] q; - } idma_reg32_2d_frontend_reg2hw_stride_dst_reg_t; - - typedef struct packed { - logic [31:0] q; - } idma_reg32_2d_frontend_reg2hw_num_repetitions_reg_t; - - typedef struct packed { - logic [31:0] q; - logic re; - } idma_reg32_2d_frontend_reg2hw_next_id_reg_t; - - typedef struct packed { - logic [31:0] q; - logic re; - } idma_reg32_2d_frontend_reg2hw_done_reg_t; - - typedef struct packed { - logic [15:0] d; - } idma_reg32_2d_frontend_hw2reg_status_reg_t; - - typedef struct packed { - logic [31:0] d; - } idma_reg32_2d_frontend_hw2reg_next_id_reg_t; - - typedef struct packed { - logic [31:0] d; - } idma_reg32_2d_frontend_hw2reg_done_reg_t; - - // Register -> HW type - typedef struct packed { - idma_reg32_2d_frontend_reg2hw_src_protocol_reg_t src_protocol; // [265:264] - idma_reg32_2d_frontend_reg2hw_dst_protocol_reg_t dst_protocol; // [263:262] - idma_reg32_2d_frontend_reg2hw_src_addr_reg_t src_addr; // [261:230] - idma_reg32_2d_frontend_reg2hw_dst_addr_reg_t dst_addr; // [229:198] - idma_reg32_2d_frontend_reg2hw_num_bytes_reg_t num_bytes; // [197:166] - idma_reg32_2d_frontend_reg2hw_conf_reg_t conf; // [165:162] - idma_reg32_2d_frontend_reg2hw_stride_src_reg_t stride_src; // [161:130] - idma_reg32_2d_frontend_reg2hw_stride_dst_reg_t stride_dst; // [129:98] - idma_reg32_2d_frontend_reg2hw_num_repetitions_reg_t num_repetitions; // [97:66] - idma_reg32_2d_frontend_reg2hw_next_id_reg_t next_id; // [65:33] - idma_reg32_2d_frontend_reg2hw_done_reg_t done; // [32:0] - } idma_reg32_2d_frontend_reg2hw_t; - - // HW -> register type - typedef struct packed { - idma_reg32_2d_frontend_hw2reg_status_reg_t status; // [79:64] - idma_reg32_2d_frontend_hw2reg_next_id_reg_t next_id; // [63:32] - idma_reg32_2d_frontend_hw2reg_done_reg_t done; // [31:0] - } idma_reg32_2d_frontend_hw2reg_t; - - // Register offsets - parameter logic [BlockAw-1:0] IDMA_REG32_2D_FRONTEND_SRC_PROTOCOL_OFFSET = 6'h 0; - parameter logic [BlockAw-1:0] IDMA_REG32_2D_FRONTEND_DST_PROTOCOL_OFFSET = 6'h 4; - parameter logic [BlockAw-1:0] IDMA_REG32_2D_FRONTEND_SRC_ADDR_OFFSET = 6'h 8; - parameter logic [BlockAw-1:0] IDMA_REG32_2D_FRONTEND_DST_ADDR_OFFSET = 6'h c; - parameter logic [BlockAw-1:0] IDMA_REG32_2D_FRONTEND_NUM_BYTES_OFFSET = 6'h 10; - parameter logic [BlockAw-1:0] IDMA_REG32_2D_FRONTEND_CONF_OFFSET = 6'h 14; - parameter logic [BlockAw-1:0] IDMA_REG32_2D_FRONTEND_STRIDE_SRC_OFFSET = 6'h 18; - parameter logic [BlockAw-1:0] IDMA_REG32_2D_FRONTEND_STRIDE_DST_OFFSET = 6'h 1c; - parameter logic [BlockAw-1:0] IDMA_REG32_2D_FRONTEND_NUM_REPETITIONS_OFFSET = 6'h 20; - parameter logic [BlockAw-1:0] IDMA_REG32_2D_FRONTEND_STATUS_OFFSET = 6'h 24; - parameter logic [BlockAw-1:0] IDMA_REG32_2D_FRONTEND_NEXT_ID_OFFSET = 6'h 28; - parameter logic [BlockAw-1:0] IDMA_REG32_2D_FRONTEND_DONE_OFFSET = 6'h 2c; - - // Reset values for hwext registers and their fields - parameter logic [15:0] IDMA_REG32_2D_FRONTEND_STATUS_RESVAL = 16'h 0; - parameter logic [31:0] IDMA_REG32_2D_FRONTEND_NEXT_ID_RESVAL = 32'h 0; - parameter logic [31:0] IDMA_REG32_2D_FRONTEND_DONE_RESVAL = 32'h 0; - - // Register index - typedef enum int { - IDMA_REG32_2D_FRONTEND_SRC_PROTOCOL, - IDMA_REG32_2D_FRONTEND_DST_PROTOCOL, - IDMA_REG32_2D_FRONTEND_SRC_ADDR, - IDMA_REG32_2D_FRONTEND_DST_ADDR, - IDMA_REG32_2D_FRONTEND_NUM_BYTES, - IDMA_REG32_2D_FRONTEND_CONF, - IDMA_REG32_2D_FRONTEND_STRIDE_SRC, - IDMA_REG32_2D_FRONTEND_STRIDE_DST, - IDMA_REG32_2D_FRONTEND_NUM_REPETITIONS, - IDMA_REG32_2D_FRONTEND_STATUS, - IDMA_REG32_2D_FRONTEND_NEXT_ID, - IDMA_REG32_2D_FRONTEND_DONE - } idma_reg32_2d_frontend_id_e; - - // Register width information to check illegal writes - parameter logic [3:0] IDMA_REG32_2D_FRONTEND_PERMIT [12] = '{ - 4'b 0001, // index[ 0] IDMA_REG32_2D_FRONTEND_SRC_PROTOCOL - 4'b 0001, // index[ 1] IDMA_REG32_2D_FRONTEND_DST_PROTOCOL - 4'b 1111, // index[ 2] IDMA_REG32_2D_FRONTEND_SRC_ADDR - 4'b 1111, // index[ 3] IDMA_REG32_2D_FRONTEND_DST_ADDR - 4'b 1111, // index[ 4] IDMA_REG32_2D_FRONTEND_NUM_BYTES - 4'b 0001, // index[ 5] IDMA_REG32_2D_FRONTEND_CONF - 4'b 1111, // index[ 6] IDMA_REG32_2D_FRONTEND_STRIDE_SRC - 4'b 1111, // index[ 7] IDMA_REG32_2D_FRONTEND_STRIDE_DST - 4'b 1111, // index[ 8] IDMA_REG32_2D_FRONTEND_NUM_REPETITIONS - 4'b 0011, // index[ 9] IDMA_REG32_2D_FRONTEND_STATUS - 4'b 1111, // index[10] IDMA_REG32_2D_FRONTEND_NEXT_ID - 4'b 1111 // index[11] IDMA_REG32_2D_FRONTEND_DONE - }; - -endpackage - diff --git a/src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_top.sv b/src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_top.sv deleted file mode 100644 index 7a083d76..00000000 --- a/src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_top.sv +++ /dev/null @@ -1,638 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Top module auto-generated by `reggen` - - -`include "common_cells/assertions.svh" - -module idma_reg32_2d_frontend_reg_top #( - parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic, - parameter int AW = 6 -) ( - input clk_i, - input rst_ni, - input reg_req_t reg_req_i, - output reg_rsp_t reg_rsp_o, - // To HW - output idma_reg32_2d_frontend_reg_pkg::idma_reg32_2d_frontend_reg2hw_t reg2hw, // Write - input idma_reg32_2d_frontend_reg_pkg::idma_reg32_2d_frontend_hw2reg_t hw2reg, // Read - - - // Config - input devmode_i // If 1, explicit error return for unmapped register access -); - - import idma_reg32_2d_frontend_reg_pkg::* ; - - localparam int DW = 32; - localparam int DBW = DW/8; // Byte Width - - // register signals - logic reg_we; - logic reg_re; - logic [AW-1:0] reg_addr; - logic [DW-1:0] reg_wdata; - logic [DBW-1:0] reg_be; - logic [DW-1:0] reg_rdata; - logic reg_error; - - logic addrmiss, wr_err; - - logic [DW-1:0] reg_rdata_next; - - // Below register interface can be changed - reg_req_t reg_intf_req; - reg_rsp_t reg_intf_rsp; - - - assign reg_intf_req = reg_req_i; - assign reg_rsp_o = reg_intf_rsp; - - - assign reg_we = reg_intf_req.valid & reg_intf_req.write; - assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; - assign reg_addr = reg_intf_req.addr; - assign reg_wdata = reg_intf_req.wdata; - assign reg_be = reg_intf_req.wstrb; - assign reg_intf_rsp.rdata = reg_rdata; - assign reg_intf_rsp.error = reg_error; - assign reg_intf_rsp.ready = 1'b1; - - assign reg_rdata = reg_rdata_next ; - assign reg_error = (devmode_i & addrmiss) | wr_err; - - - // Define SW related signals - // Format: __{wd|we|qs} - // or _{wd|we|qs} if field == 1 or 0 - logic [1:0] src_protocol_qs; - logic [1:0] src_protocol_wd; - logic src_protocol_we; - logic [1:0] dst_protocol_qs; - logic [1:0] dst_protocol_wd; - logic dst_protocol_we; - logic [31:0] src_addr_qs; - logic [31:0] src_addr_wd; - logic src_addr_we; - logic [31:0] dst_addr_qs; - logic [31:0] dst_addr_wd; - logic dst_addr_we; - logic [31:0] num_bytes_qs; - logic [31:0] num_bytes_wd; - logic num_bytes_we; - logic conf_decouple_qs; - logic conf_decouple_wd; - logic conf_decouple_we; - logic conf_deburst_qs; - logic conf_deburst_wd; - logic conf_deburst_we; - logic conf_serialize_qs; - logic conf_serialize_wd; - logic conf_serialize_we; - logic conf_twod_qs; - logic conf_twod_wd; - logic conf_twod_we; - logic [31:0] stride_src_qs; - logic [31:0] stride_src_wd; - logic stride_src_we; - logic [31:0] stride_dst_qs; - logic [31:0] stride_dst_wd; - logic stride_dst_we; - logic [31:0] num_repetitions_qs; - logic [31:0] num_repetitions_wd; - logic num_repetitions_we; - logic [15:0] status_qs; - logic status_re; - logic [31:0] next_id_qs; - logic next_id_re; - logic [31:0] done_qs; - logic done_re; - - // Register instances - // R[src_protocol]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_src_protocol ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (src_protocol_we), - .wd (src_protocol_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.src_protocol.q ), - - // to register interface (read) - .qs (src_protocol_qs) - ); - - - // R[dst_protocol]: V(False) - - prim_subreg #( - .DW (2), - .SWACCESS("RW"), - .RESVAL (2'h0) - ) u_dst_protocol ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dst_protocol_we), - .wd (dst_protocol_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.dst_protocol.q ), - - // to register interface (read) - .qs (dst_protocol_qs) - ); - - - // R[src_addr]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_src_addr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (src_addr_we), - .wd (src_addr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.src_addr.q ), - - // to register interface (read) - .qs (src_addr_qs) - ); - - - // R[dst_addr]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_dst_addr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dst_addr_we), - .wd (dst_addr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.dst_addr.q ), - - // to register interface (read) - .qs (dst_addr_qs) - ); - - - // R[num_bytes]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_num_bytes ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (num_bytes_we), - .wd (num_bytes_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.num_bytes.q ), - - // to register interface (read) - .qs (num_bytes_qs) - ); - - - // R[conf]: V(False) - - // F[decouple]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_conf_decouple ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (conf_decouple_we), - .wd (conf_decouple_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.conf.decouple.q ), - - // to register interface (read) - .qs (conf_decouple_qs) - ); - - - // F[deburst]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_conf_deburst ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (conf_deburst_we), - .wd (conf_deburst_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.conf.deburst.q ), - - // to register interface (read) - .qs (conf_deburst_qs) - ); - - - // F[serialize]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_conf_serialize ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (conf_serialize_we), - .wd (conf_serialize_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.conf.serialize.q ), - - // to register interface (read) - .qs (conf_serialize_qs) - ); - - - // F[twod]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_conf_twod ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (conf_twod_we), - .wd (conf_twod_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.conf.twod.q ), - - // to register interface (read) - .qs (conf_twod_qs) - ); - - - // R[stride_src]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_stride_src ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (stride_src_we), - .wd (stride_src_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.stride_src.q ), - - // to register interface (read) - .qs (stride_src_qs) - ); - - - // R[stride_dst]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_stride_dst ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (stride_dst_we), - .wd (stride_dst_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.stride_dst.q ), - - // to register interface (read) - .qs (stride_dst_qs) - ); - - - // R[num_repetitions]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h1) - ) u_num_repetitions ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (num_repetitions_we), - .wd (num_repetitions_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.num_repetitions.q ), - - // to register interface (read) - .qs (num_repetitions_qs) - ); - - - // R[status]: V(True) - - prim_subreg_ext #( - .DW (16) - ) u_status ( - .re (status_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.status.d), - .qre (), - .qe (), - .q (), - .qs (status_qs) - ); - - - // R[next_id]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_next_id ( - .re (next_id_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.next_id.d), - .qre (reg2hw.next_id.re), - .qe (), - .q (reg2hw.next_id.q ), - .qs (next_id_qs) - ); - - - // R[done]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_done ( - .re (done_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.done.d), - .qre (reg2hw.done.re), - .qe (), - .q (reg2hw.done.q ), - .qs (done_qs) - ); - - - - - logic [11:0] addr_hit; - always_comb begin - addr_hit = '0; - addr_hit[ 0] = (reg_addr == IDMA_REG32_2D_FRONTEND_SRC_PROTOCOL_OFFSET); - addr_hit[ 1] = (reg_addr == IDMA_REG32_2D_FRONTEND_DST_PROTOCOL_OFFSET); - addr_hit[ 2] = (reg_addr == IDMA_REG32_2D_FRONTEND_SRC_ADDR_OFFSET); - addr_hit[ 3] = (reg_addr == IDMA_REG32_2D_FRONTEND_DST_ADDR_OFFSET); - addr_hit[ 4] = (reg_addr == IDMA_REG32_2D_FRONTEND_NUM_BYTES_OFFSET); - addr_hit[ 5] = (reg_addr == IDMA_REG32_2D_FRONTEND_CONF_OFFSET); - addr_hit[ 6] = (reg_addr == IDMA_REG32_2D_FRONTEND_STRIDE_SRC_OFFSET); - addr_hit[ 7] = (reg_addr == IDMA_REG32_2D_FRONTEND_STRIDE_DST_OFFSET); - addr_hit[ 8] = (reg_addr == IDMA_REG32_2D_FRONTEND_NUM_REPETITIONS_OFFSET); - addr_hit[ 9] = (reg_addr == IDMA_REG32_2D_FRONTEND_STATUS_OFFSET); - addr_hit[10] = (reg_addr == IDMA_REG32_2D_FRONTEND_NEXT_ID_OFFSET); - addr_hit[11] = (reg_addr == IDMA_REG32_2D_FRONTEND_DONE_OFFSET); - end - - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - - // Check sub-word write is permitted - always_comb begin - wr_err = (reg_we & - ((addr_hit[ 0] & (|(IDMA_REG32_2D_FRONTEND_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(IDMA_REG32_2D_FRONTEND_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(IDMA_REG32_2D_FRONTEND_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(IDMA_REG32_2D_FRONTEND_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(IDMA_REG32_2D_FRONTEND_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(IDMA_REG32_2D_FRONTEND_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(IDMA_REG32_2D_FRONTEND_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(IDMA_REG32_2D_FRONTEND_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(IDMA_REG32_2D_FRONTEND_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(IDMA_REG32_2D_FRONTEND_PERMIT[ 9] & ~reg_be))) | - (addr_hit[10] & (|(IDMA_REG32_2D_FRONTEND_PERMIT[10] & ~reg_be))) | - (addr_hit[11] & (|(IDMA_REG32_2D_FRONTEND_PERMIT[11] & ~reg_be))))); - end - - assign src_protocol_we = addr_hit[0] & reg_we & !reg_error; - assign src_protocol_wd = reg_wdata[1:0]; - - assign dst_protocol_we = addr_hit[1] & reg_we & !reg_error; - assign dst_protocol_wd = reg_wdata[1:0]; - - assign src_addr_we = addr_hit[2] & reg_we & !reg_error; - assign src_addr_wd = reg_wdata[31:0]; - - assign dst_addr_we = addr_hit[3] & reg_we & !reg_error; - assign dst_addr_wd = reg_wdata[31:0]; - - assign num_bytes_we = addr_hit[4] & reg_we & !reg_error; - assign num_bytes_wd = reg_wdata[31:0]; - - assign conf_decouple_we = addr_hit[5] & reg_we & !reg_error; - assign conf_decouple_wd = reg_wdata[0]; - - assign conf_deburst_we = addr_hit[5] & reg_we & !reg_error; - assign conf_deburst_wd = reg_wdata[1]; - - assign conf_serialize_we = addr_hit[5] & reg_we & !reg_error; - assign conf_serialize_wd = reg_wdata[2]; - - assign conf_twod_we = addr_hit[5] & reg_we & !reg_error; - assign conf_twod_wd = reg_wdata[3]; - - assign stride_src_we = addr_hit[6] & reg_we & !reg_error; - assign stride_src_wd = reg_wdata[31:0]; - - assign stride_dst_we = addr_hit[7] & reg_we & !reg_error; - assign stride_dst_wd = reg_wdata[31:0]; - - assign num_repetitions_we = addr_hit[8] & reg_we & !reg_error; - assign num_repetitions_wd = reg_wdata[31:0]; - - assign status_re = addr_hit[9] & reg_re & !reg_error; - - assign next_id_re = addr_hit[10] & reg_re & !reg_error; - - assign done_re = addr_hit[11] & reg_re & !reg_error; - - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[1:0] = src_protocol_qs; - end - - addr_hit[1]: begin - reg_rdata_next[1:0] = dst_protocol_qs; - end - - addr_hit[2]: begin - reg_rdata_next[31:0] = src_addr_qs; - end - - addr_hit[3]: begin - reg_rdata_next[31:0] = dst_addr_qs; - end - - addr_hit[4]: begin - reg_rdata_next[31:0] = num_bytes_qs; - end - - addr_hit[5]: begin - reg_rdata_next[0] = conf_decouple_qs; - reg_rdata_next[1] = conf_deburst_qs; - reg_rdata_next[2] = conf_serialize_qs; - reg_rdata_next[3] = conf_twod_qs; - end - - addr_hit[6]: begin - reg_rdata_next[31:0] = stride_src_qs; - end - - addr_hit[7]: begin - reg_rdata_next[31:0] = stride_dst_qs; - end - - addr_hit[8]: begin - reg_rdata_next[31:0] = num_repetitions_qs; - end - - addr_hit[9]: begin - reg_rdata_next[15:0] = status_qs; - end - - addr_hit[10]: begin - reg_rdata_next[31:0] = next_id_qs; - end - - addr_hit[11]: begin - reg_rdata_next[31:0] = done_qs; - end - - default: begin - reg_rdata_next = '1; - end - endcase - end - - // Unused signal tieoff - - // wdata / byte enable are not always fully used - // add a blanket unused statement to handle lint waivers - logic unused_wdata; - logic unused_be; - assign unused_wdata = ^reg_wdata; - assign unused_be = ^reg_be; - - // Assertions for Register Interface - `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) - -endmodule diff --git a/src/frontends/register_32bit_2d/reg_html.css b/src/frontends/register_32bit_2d/reg_html.css deleted file mode 100644 index 4cb48edb..00000000 --- a/src/frontends/register_32bit_2d/reg_html.css +++ /dev/null @@ -1,74 +0,0 @@ -/* Stylesheet for reggen HTML register output */ -/* Copyright lowRISC contributors. */ -/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ -/* SPDX-License-Identifier: Apache-2.0 */ - -table.regpic { - width: 95%; - border-collapse: collapse; - margin-left:auto; - margin-right:auto; - table-layout:fixed; -} - -table.regdef { - border: 1px solid black; - width: 80%; - border-collapse: collapse; - margin-left:auto; - margin-right:auto; - table-layout:auto; -} - -table.regdef th { - border: 1px solid black; - font-family: sans-serif; - -} - -td.bitnum { - font-size: 60%; - text-align: center; -} - -td.unused { - border: 1px solid black; - background-color: gray; -} - -td.fname { - border: 1px solid black; - text-align: center; - font-family: sans-serif; -} - - -td.regbits, td.regperm, td.regrv { - border: 1px solid black; - text-align: center; - font-family: sans-serif; -} - -td.regde, td.regfn { - border: 1px solid black; -} - -table.cfgtable { - border: 1px solid black; - width: 80%; - border-collapse: collapse; - margin-left:auto; - margin-right:auto; - table-layout:auto; -} - -table.cfgtable th { - border: 1px solid black; - font-family: sans-serif; - font-weight: bold; -} - -table.cfgtable td { - border: 1px solid black; - font-family: sans-serif; -} diff --git a/src/frontends/register_64bit/idma_reg64_frontend.h b/src/frontends/register_64bit/idma_reg64_frontend.h deleted file mode 100644 index 5a622792..00000000 --- a/src/frontends/register_64bit/idma_reg64_frontend.h +++ /dev/null @@ -1,48 +0,0 @@ -// Generated register defines for idma_reg64_frontend - -// Copyright information found in source file: -// Copyright 2022 ETH Zurich and University of Bologna. - -// Licensing information found in source file: -// Licensed under Solderpad Hardware License, Version 0.51 -// SPDX-License-Identifier: SHL-0.51 - -#ifndef _IDMA_REG64_FRONTEND_REG_DEFS_ -#define _IDMA_REG64_FRONTEND_REG_DEFS_ - -#ifdef __cplusplus -extern "C" { -#endif -// Register width -#define IDMA_REG64_FRONTEND_PARAM_REG_WIDTH 64 - -// Source Address -#define IDMA_REG64_FRONTEND_SRC_ADDR_REG_OFFSET 0x0 - -// Destination Address -#define IDMA_REG64_FRONTEND_DST_ADDR_REG_OFFSET 0x8 - -// Number of bytes -#define IDMA_REG64_FRONTEND_NUM_BYTES_REG_OFFSET 0x10 - -// Configuration Register for DMA settings -#define IDMA_REG64_FRONTEND_CONF_REG_OFFSET 0x18 -#define IDMA_REG64_FRONTEND_CONF_DECOUPLE_BIT 0 -#define IDMA_REG64_FRONTEND_CONF_DEBURST_BIT 1 -#define IDMA_REG64_FRONTEND_CONF_SERIALIZE_BIT 2 - -// DMA Status -#define IDMA_REG64_FRONTEND_STATUS_REG_OFFSET 0x20 -#define IDMA_REG64_FRONTEND_STATUS_BUSY_BIT 0 - -// Next ID, launches transfer, returns 0 if transfer not set up properly. -#define IDMA_REG64_FRONTEND_NEXT_ID_REG_OFFSET 0x28 - -// Get ID of finished transactions. -#define IDMA_REG64_FRONTEND_DONE_REG_OFFSET 0x30 - -#ifdef __cplusplus -} // extern "C" -#endif -#endif // _IDMA_REG64_FRONTEND_REG_DEFS_ -// End generated register defines for idma_reg64_frontend \ No newline at end of file diff --git a/src/frontends/register_64bit/idma_reg64_frontend.html b/src/frontends/register_64bit/idma_reg64_frontend.html deleted file mode 100644 index 7df38216..00000000 --- a/src/frontends/register_64bit/idma_reg64_frontend.html +++ /dev/null @@ -1,136 +0,0 @@ - - - - - - - - - - -
-
idma_reg64_frontend.src_addr @ 0x0
-

Source Address

-
Reset default = 0x0, mask 0xffffffffffffffff
-
- - - - - - -
63626160595857565554535251504948
src_addr...
47464544434241403938373635343332
...src_addr...
31302928272625242322212019181716
...src_addr...
1514131211109876543210
...src_addr
BitsTypeResetNameDescription
63:0rwxsrc_addr

Source Address

-
- - - - - -
-
idma_reg64_frontend.dst_addr @ 0x8
-

Destination Address

-
Reset default = 0x0, mask 0xffffffffffffffff
-
- - - - - - -
63626160595857565554535251504948
dst_addr...
47464544434241403938373635343332
...dst_addr...
31302928272625242322212019181716
...dst_addr...
1514131211109876543210
...dst_addr
BitsTypeResetNameDescription
63:0rwxdst_addr

Destination Address

-
- - - - - -
-
idma_reg64_frontend.num_bytes @ 0x10
-

Number of bytes

-
Reset default = 0x0, mask 0xffffffffffffffff
-
- - - - - - -
63626160595857565554535251504948
num_bytes...
47464544434241403938373635343332
...num_bytes...
31302928272625242322212019181716
...num_bytes...
1514131211109876543210
...num_bytes
BitsTypeResetNameDescription
63:0rwxnum_bytes

Number of bytes

-
- - - - - -
-
idma_reg64_frontend.conf @ 0x18
-

Configuration Register for DMA settings

-
Reset default = 0x0, mask 0x7
-
- - - - - - - - - -
63626160595857565554535251504948
 
47464544434241403938373635343332
 
31302928272625242322212019181716
 
1514131211109876543210
 serializedeburstdecouple
BitsTypeResetNameDescription
0rwxdecouple

Decouple enable

1rwxdeburst

Deburst enable

2rwxserialize

Serialize enable

-
- - - - - -
-
idma_reg64_frontend.status @ 0x20
-

DMA Status

-
Reset default = 0x0, mask 0x1
-
- - - - - - - -
63626160595857565554535251504948
 
47464544434241403938373635343332
 
31302928272625242322212019181716
 
1514131211109876543210
 busy
BitsTypeResetNameDescription
0roxbusy

DMA busy

-
- - - - - -
-
idma_reg64_frontend.next_id @ 0x28
-

Next ID, launches transfer, returns 0 if transfer not set up properly.

-
Reset default = 0x0, mask 0xffffffffffffffff
-
- - - - - - -
63626160595857565554535251504948
next_id...
47464544434241403938373635343332
...next_id...
31302928272625242322212019181716
...next_id...
1514131211109876543210
...next_id
BitsTypeResetNameDescription
63:0roxnext_id

Next ID, launches transfer, returns 0 if transfer not set up properly.

-
- - - - - -
-
idma_reg64_frontend.done @ 0x30
-

Get ID of finished transactions.

-
Reset default = 0x0, mask 0xffffffffffffffff
-
- - - - - - -
63626160595857565554535251504948
done...
47464544434241403938373635343332
...done...
31302928272625242322212019181716
...done...
1514131211109876543210
...done
BitsTypeResetNameDescription
63:0roxdone

Get ID of finished transactions.

-
- diff --git a/src/frontends/register_64bit/idma_reg64_frontend_reg_pkg.sv b/src/frontends/register_64bit/idma_reg64_frontend_reg_pkg.sv deleted file mode 100644 index e1ada5a2..00000000 --- a/src/frontends/register_64bit/idma_reg64_frontend_reg_pkg.sv +++ /dev/null @@ -1,116 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Package auto-generated by `reggen` containing data structure - -package idma_reg64_frontend_reg_pkg; - - // Address widths within the block - parameter int BlockAw = 6; - - //////////////////////////// - // Typedefs for registers // - //////////////////////////// - - typedef struct packed { - logic [63:0] q; - } idma_reg64_frontend_reg2hw_src_addr_reg_t; - - typedef struct packed { - logic [63:0] q; - } idma_reg64_frontend_reg2hw_dst_addr_reg_t; - - typedef struct packed { - logic [63:0] q; - } idma_reg64_frontend_reg2hw_num_bytes_reg_t; - - typedef struct packed { - struct packed { - logic q; - } decouple; - struct packed { - logic q; - } deburst; - struct packed { - logic q; - } serialize; - } idma_reg64_frontend_reg2hw_conf_reg_t; - - typedef struct packed { - logic [63:0] q; - logic re; - } idma_reg64_frontend_reg2hw_next_id_reg_t; - - typedef struct packed { - logic [63:0] q; - logic re; - } idma_reg64_frontend_reg2hw_done_reg_t; - - typedef struct packed { - logic d; - } idma_reg64_frontend_hw2reg_status_reg_t; - - typedef struct packed { - logic [63:0] d; - } idma_reg64_frontend_hw2reg_next_id_reg_t; - - typedef struct packed { - logic [63:0] d; - } idma_reg64_frontend_hw2reg_done_reg_t; - - // Register -> HW type - typedef struct packed { - idma_reg64_frontend_reg2hw_src_addr_reg_t src_addr; // [324:261] - idma_reg64_frontend_reg2hw_dst_addr_reg_t dst_addr; // [260:197] - idma_reg64_frontend_reg2hw_num_bytes_reg_t num_bytes; // [196:133] - idma_reg64_frontend_reg2hw_conf_reg_t conf; // [132:130] - idma_reg64_frontend_reg2hw_next_id_reg_t next_id; // [129:65] - idma_reg64_frontend_reg2hw_done_reg_t done; // [64:0] - } idma_reg64_frontend_reg2hw_t; - - // HW -> register type - typedef struct packed { - idma_reg64_frontend_hw2reg_status_reg_t status; // [128:128] - idma_reg64_frontend_hw2reg_next_id_reg_t next_id; // [127:64] - idma_reg64_frontend_hw2reg_done_reg_t done; // [63:0] - } idma_reg64_frontend_hw2reg_t; - - // Register offsets - parameter logic [BlockAw-1:0] IDMA_REG64_FRONTEND_SRC_ADDR_OFFSET = 6'h 0; - parameter logic [BlockAw-1:0] IDMA_REG64_FRONTEND_DST_ADDR_OFFSET = 6'h 8; - parameter logic [BlockAw-1:0] IDMA_REG64_FRONTEND_NUM_BYTES_OFFSET = 6'h 10; - parameter logic [BlockAw-1:0] IDMA_REG64_FRONTEND_CONF_OFFSET = 6'h 18; - parameter logic [BlockAw-1:0] IDMA_REG64_FRONTEND_STATUS_OFFSET = 6'h 20; - parameter logic [BlockAw-1:0] IDMA_REG64_FRONTEND_NEXT_ID_OFFSET = 6'h 28; - parameter logic [BlockAw-1:0] IDMA_REG64_FRONTEND_DONE_OFFSET = 6'h 30; - - // Reset values for hwext registers and their fields - parameter logic [0:0] IDMA_REG64_FRONTEND_STATUS_RESVAL = 1'h 0; - parameter logic [63:0] IDMA_REG64_FRONTEND_NEXT_ID_RESVAL = 64'h 0; - parameter logic [63:0] IDMA_REG64_FRONTEND_DONE_RESVAL = 64'h 0; - - // Register index - typedef enum int { - IDMA_REG64_FRONTEND_SRC_ADDR, - IDMA_REG64_FRONTEND_DST_ADDR, - IDMA_REG64_FRONTEND_NUM_BYTES, - IDMA_REG64_FRONTEND_CONF, - IDMA_REG64_FRONTEND_STATUS, - IDMA_REG64_FRONTEND_NEXT_ID, - IDMA_REG64_FRONTEND_DONE - } idma_reg64_frontend_id_e; - - // Register width information to check illegal writes - parameter logic [3:0] IDMA_REG64_FRONTEND_PERMIT [7] = '{ - 4'b 1111, // index[0] IDMA_REG64_FRONTEND_SRC_ADDR - 4'b 1111, // index[1] IDMA_REG64_FRONTEND_DST_ADDR - 4'b 1111, // index[2] IDMA_REG64_FRONTEND_NUM_BYTES - 4'b 0001, // index[3] IDMA_REG64_FRONTEND_CONF - 4'b 0001, // index[4] IDMA_REG64_FRONTEND_STATUS - 4'b 1111, // index[5] IDMA_REG64_FRONTEND_NEXT_ID - 4'b 1111 // index[6] IDMA_REG64_FRONTEND_DONE - }; - -endpackage - diff --git a/src/frontends/register_64bit/idma_reg64_frontend_reg_top.sv b/src/frontends/register_64bit/idma_reg64_frontend_reg_top.sv deleted file mode 100644 index c01b4aea..00000000 --- a/src/frontends/register_64bit/idma_reg64_frontend_reg_top.sv +++ /dev/null @@ -1,410 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Top module auto-generated by `reggen` - - -`include "common_cells/assertions.svh" - -module idma_reg64_frontend_reg_top #( - parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic, - parameter int AW = 6 -) ( - input clk_i, - input rst_ni, - input reg_req_t reg_req_i, - output reg_rsp_t reg_rsp_o, - // To HW - output idma_reg64_frontend_reg_pkg::idma_reg64_frontend_reg2hw_t reg2hw, // Write - input idma_reg64_frontend_reg_pkg::idma_reg64_frontend_hw2reg_t hw2reg, // Read - - - // Config - input devmode_i // If 1, explicit error return for unmapped register access -); - - import idma_reg64_frontend_reg_pkg::* ; - - localparam int DW = 64; - localparam int DBW = DW/8; // Byte Width - - // register signals - logic reg_we; - logic reg_re; - logic [AW-1:0] reg_addr; - logic [DW-1:0] reg_wdata; - logic [DBW-1:0] reg_be; - logic [DW-1:0] reg_rdata; - logic reg_error; - - logic addrmiss, wr_err; - - logic [DW-1:0] reg_rdata_next; - - // Below register interface can be changed - reg_req_t reg_intf_req; - reg_rsp_t reg_intf_rsp; - - - assign reg_intf_req = reg_req_i; - assign reg_rsp_o = reg_intf_rsp; - - - assign reg_we = reg_intf_req.valid & reg_intf_req.write; - assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; - assign reg_addr = reg_intf_req.addr; - assign reg_wdata = reg_intf_req.wdata; - assign reg_be = reg_intf_req.wstrb; - assign reg_intf_rsp.rdata = reg_rdata; - assign reg_intf_rsp.error = reg_error; - assign reg_intf_rsp.ready = 1'b1; - - assign reg_rdata = reg_rdata_next ; - assign reg_error = (devmode_i & addrmiss) | wr_err; - - - // Define SW related signals - // Format: __{wd|we|qs} - // or _{wd|we|qs} if field == 1 or 0 - logic [63:0] src_addr_qs; - logic [63:0] src_addr_wd; - logic src_addr_we; - logic [63:0] dst_addr_qs; - logic [63:0] dst_addr_wd; - logic dst_addr_we; - logic [63:0] num_bytes_qs; - logic [63:0] num_bytes_wd; - logic num_bytes_we; - logic conf_decouple_qs; - logic conf_decouple_wd; - logic conf_decouple_we; - logic conf_deburst_qs; - logic conf_deburst_wd; - logic conf_deburst_we; - logic conf_serialize_qs; - logic conf_serialize_wd; - logic conf_serialize_we; - logic status_qs; - logic status_re; - logic [63:0] next_id_qs; - logic next_id_re; - logic [63:0] done_qs; - logic done_re; - - // Register instances - // R[src_addr]: V(False) - - prim_subreg #( - .DW (64), - .SWACCESS("RW"), - .RESVAL (64'h0) - ) u_src_addr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (src_addr_we), - .wd (src_addr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.src_addr.q ), - - // to register interface (read) - .qs (src_addr_qs) - ); - - - // R[dst_addr]: V(False) - - prim_subreg #( - .DW (64), - .SWACCESS("RW"), - .RESVAL (64'h0) - ) u_dst_addr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dst_addr_we), - .wd (dst_addr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.dst_addr.q ), - - // to register interface (read) - .qs (dst_addr_qs) - ); - - - // R[num_bytes]: V(False) - - prim_subreg #( - .DW (64), - .SWACCESS("RW"), - .RESVAL (64'h0) - ) u_num_bytes ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (num_bytes_we), - .wd (num_bytes_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.num_bytes.q ), - - // to register interface (read) - .qs (num_bytes_qs) - ); - - - // R[conf]: V(False) - - // F[decouple]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_conf_decouple ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (conf_decouple_we), - .wd (conf_decouple_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.conf.decouple.q ), - - // to register interface (read) - .qs (conf_decouple_qs) - ); - - - // F[deburst]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_conf_deburst ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (conf_deburst_we), - .wd (conf_deburst_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.conf.deburst.q ), - - // to register interface (read) - .qs (conf_deburst_qs) - ); - - - // F[serialize]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_conf_serialize ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (conf_serialize_we), - .wd (conf_serialize_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.conf.serialize.q ), - - // to register interface (read) - .qs (conf_serialize_qs) - ); - - - // R[status]: V(True) - - prim_subreg_ext #( - .DW (1) - ) u_status ( - .re (status_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.status.d), - .qre (), - .qe (), - .q (), - .qs (status_qs) - ); - - - // R[next_id]: V(True) - - prim_subreg_ext #( - .DW (64) - ) u_next_id ( - .re (next_id_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.next_id.d), - .qre (reg2hw.next_id.re), - .qe (), - .q (reg2hw.next_id.q ), - .qs (next_id_qs) - ); - - - // R[done]: V(True) - - prim_subreg_ext #( - .DW (64) - ) u_done ( - .re (done_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.done.d), - .qre (reg2hw.done.re), - .qe (), - .q (reg2hw.done.q ), - .qs (done_qs) - ); - - - - - logic [6:0] addr_hit; - always_comb begin - addr_hit = '0; - addr_hit[0] = (reg_addr == IDMA_REG64_FRONTEND_SRC_ADDR_OFFSET); - addr_hit[1] = (reg_addr == IDMA_REG64_FRONTEND_DST_ADDR_OFFSET); - addr_hit[2] = (reg_addr == IDMA_REG64_FRONTEND_NUM_BYTES_OFFSET); - addr_hit[3] = (reg_addr == IDMA_REG64_FRONTEND_CONF_OFFSET); - addr_hit[4] = (reg_addr == IDMA_REG64_FRONTEND_STATUS_OFFSET); - addr_hit[5] = (reg_addr == IDMA_REG64_FRONTEND_NEXT_ID_OFFSET); - addr_hit[6] = (reg_addr == IDMA_REG64_FRONTEND_DONE_OFFSET); - end - - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - - // Check sub-word write is permitted - always_comb begin - wr_err = (reg_we & - ((addr_hit[0] & (|(IDMA_REG64_FRONTEND_PERMIT[0] & ~reg_be))) | - (addr_hit[1] & (|(IDMA_REG64_FRONTEND_PERMIT[1] & ~reg_be))) | - (addr_hit[2] & (|(IDMA_REG64_FRONTEND_PERMIT[2] & ~reg_be))) | - (addr_hit[3] & (|(IDMA_REG64_FRONTEND_PERMIT[3] & ~reg_be))) | - (addr_hit[4] & (|(IDMA_REG64_FRONTEND_PERMIT[4] & ~reg_be))) | - (addr_hit[5] & (|(IDMA_REG64_FRONTEND_PERMIT[5] & ~reg_be))) | - (addr_hit[6] & (|(IDMA_REG64_FRONTEND_PERMIT[6] & ~reg_be))))); - end - - assign src_addr_we = addr_hit[0] & reg_we & !reg_error; - assign src_addr_wd = reg_wdata[63:0]; - - assign dst_addr_we = addr_hit[1] & reg_we & !reg_error; - assign dst_addr_wd = reg_wdata[63:0]; - - assign num_bytes_we = addr_hit[2] & reg_we & !reg_error; - assign num_bytes_wd = reg_wdata[63:0]; - - assign conf_decouple_we = addr_hit[3] & reg_we & !reg_error; - assign conf_decouple_wd = reg_wdata[0]; - - assign conf_deburst_we = addr_hit[3] & reg_we & !reg_error; - assign conf_deburst_wd = reg_wdata[1]; - - assign conf_serialize_we = addr_hit[3] & reg_we & !reg_error; - assign conf_serialize_wd = reg_wdata[2]; - - assign status_re = addr_hit[4] & reg_re & !reg_error; - - assign next_id_re = addr_hit[5] & reg_re & !reg_error; - - assign done_re = addr_hit[6] & reg_re & !reg_error; - - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[63:0] = src_addr_qs; - end - - addr_hit[1]: begin - reg_rdata_next[63:0] = dst_addr_qs; - end - - addr_hit[2]: begin - reg_rdata_next[63:0] = num_bytes_qs; - end - - addr_hit[3]: begin - reg_rdata_next[0] = conf_decouple_qs; - reg_rdata_next[1] = conf_deburst_qs; - reg_rdata_next[2] = conf_serialize_qs; - end - - addr_hit[4]: begin - reg_rdata_next[0] = status_qs; - end - - addr_hit[5]: begin - reg_rdata_next[63:0] = next_id_qs; - end - - addr_hit[6]: begin - reg_rdata_next[63:0] = done_qs; - end - - default: begin - reg_rdata_next = '1; - end - endcase - end - - // Unused signal tieoff - - // wdata / byte enable are not always fully used - // add a blanket unused statement to handle lint waivers - logic unused_wdata; - logic unused_be; - assign unused_wdata = ^reg_wdata; - assign unused_be = ^reg_be; - - // Assertions for Register Interface - `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) - -endmodule diff --git a/src/frontends/register_64bit/reg_html.css b/src/frontends/register_64bit/reg_html.css deleted file mode 100644 index 4cb48edb..00000000 --- a/src/frontends/register_64bit/reg_html.css +++ /dev/null @@ -1,74 +0,0 @@ -/* Stylesheet for reggen HTML register output */ -/* Copyright lowRISC contributors. */ -/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ -/* SPDX-License-Identifier: Apache-2.0 */ - -table.regpic { - width: 95%; - border-collapse: collapse; - margin-left:auto; - margin-right:auto; - table-layout:fixed; -} - -table.regdef { - border: 1px solid black; - width: 80%; - border-collapse: collapse; - margin-left:auto; - margin-right:auto; - table-layout:auto; -} - -table.regdef th { - border: 1px solid black; - font-family: sans-serif; - -} - -td.bitnum { - font-size: 60%; - text-align: center; -} - -td.unused { - border: 1px solid black; - background-color: gray; -} - -td.fname { - border: 1px solid black; - text-align: center; - font-family: sans-serif; -} - - -td.regbits, td.regperm, td.regrv { - border: 1px solid black; - text-align: center; - font-family: sans-serif; -} - -td.regde, td.regfn { - border: 1px solid black; -} - -table.cfgtable { - border: 1px solid black; - width: 80%; - border-collapse: collapse; - margin-left:auto; - margin-right:auto; - table-layout:auto; -} - -table.cfgtable th { - border: 1px solid black; - font-family: sans-serif; - font-weight: bold; -} - -table.cfgtable td { - border: 1px solid black; - font-family: sans-serif; -} diff --git a/src/frontends/register_64bit_2d/idma_reg64_2d_frontend.h b/src/frontends/register_64bit_2d/idma_reg64_2d_frontend.h deleted file mode 100644 index 7aa43052..00000000 --- a/src/frontends/register_64bit_2d/idma_reg64_2d_frontend.h +++ /dev/null @@ -1,57 +0,0 @@ -// Generated register defines for idma_reg64_2d_frontend - -// Copyright information found in source file: -// Copyright 2022 ETH Zurich and University of Bologna. - -// Licensing information found in source file: -// Licensed under Solderpad Hardware License, Version 0.51 -// SPDX-License-Identifier: SHL-0.51 - -#ifndef _IDMA_REG64_2D_FRONTEND_REG_DEFS_ -#define _IDMA_REG64_2D_FRONTEND_REG_DEFS_ - -#ifdef __cplusplus -extern "C" { -#endif -// Register width -#define IDMA_REG64_2D_FRONTEND_PARAM_REG_WIDTH 64 - -// Source Address -#define IDMA_REG64_2D_FRONTEND_SRC_ADDR_REG_OFFSET 0x0 - -// Destination Address -#define IDMA_REG64_2D_FRONTEND_DST_ADDR_REG_OFFSET 0x8 - -// Number of bytes -#define IDMA_REG64_2D_FRONTEND_NUM_BYTES_REG_OFFSET 0x10 - -// Configuration Register for DMA settings -#define IDMA_REG64_2D_FRONTEND_CONF_REG_OFFSET 0x18 -#define IDMA_REG64_2D_FRONTEND_CONF_DECOUPLE_BIT 0 -#define IDMA_REG64_2D_FRONTEND_CONF_DEBURST_BIT 1 -#define IDMA_REG64_2D_FRONTEND_CONF_SERIALIZE_BIT 2 - -// DMA Status -#define IDMA_REG64_2D_FRONTEND_STATUS_REG_OFFSET 0x20 -#define IDMA_REG64_2D_FRONTEND_STATUS_BUSY_BIT 0 - -// Next ID, launches transfer, returns 0 if transfer not set up properly. -#define IDMA_REG64_2D_FRONTEND_NEXT_ID_REG_OFFSET 0x28 - -// Get ID of finished transactions. -#define IDMA_REG64_2D_FRONTEND_DONE_REG_OFFSET 0x30 - -// Source Stride -#define IDMA_REG64_2D_FRONTEND_STRIDE_SRC_REG_OFFSET 0x38 - -// Destination Stride -#define IDMA_REG64_2D_FRONTEND_STRIDE_DST_REG_OFFSET 0x40 - -// Number of 2D repetitions -#define IDMA_REG64_2D_FRONTEND_NUM_REPETITIONS_REG_OFFSET 0x48 - -#ifdef __cplusplus -} // extern "C" -#endif -#endif // _IDMA_REG64_2D_FRONTEND_REG_DEFS_ -// End generated register defines for idma_reg64_2d_frontend \ No newline at end of file diff --git a/src/frontends/register_64bit_2d/idma_reg64_2d_frontend.html b/src/frontends/register_64bit_2d/idma_reg64_2d_frontend.html deleted file mode 100644 index 7a635d4e..00000000 --- a/src/frontends/register_64bit_2d/idma_reg64_2d_frontend.html +++ /dev/null @@ -1,190 +0,0 @@ - - - - - - - - - - -
-
idma_reg64_2d_frontend.src_addr @ 0x0
-

Source Address

-
Reset default = 0x0, mask 0xffffffffffffffff
-
- - - - - - -
63626160595857565554535251504948
src_addr...
47464544434241403938373635343332
...src_addr...
31302928272625242322212019181716
...src_addr...
1514131211109876543210
...src_addr
BitsTypeResetNameDescription
63:0rwxsrc_addr

Source Address

-
- - - - - -
-
idma_reg64_2d_frontend.dst_addr @ 0x8
-

Destination Address

-
Reset default = 0x0, mask 0xffffffffffffffff
-
- - - - - - -
63626160595857565554535251504948
dst_addr...
47464544434241403938373635343332
...dst_addr...
31302928272625242322212019181716
...dst_addr...
1514131211109876543210
...dst_addr
BitsTypeResetNameDescription
63:0rwxdst_addr

Destination Address

-
- - - - - -
-
idma_reg64_2d_frontend.num_bytes @ 0x10
-

Number of bytes

-
Reset default = 0x0, mask 0xffffffffffffffff
-
- - - - - - -
63626160595857565554535251504948
num_bytes...
47464544434241403938373635343332
...num_bytes...
31302928272625242322212019181716
...num_bytes...
1514131211109876543210
...num_bytes
BitsTypeResetNameDescription
63:0rwxnum_bytes

Number of bytes

-
- - - - - -
-
idma_reg64_2d_frontend.conf @ 0x18
-

Configuration Register for DMA settings

-
Reset default = 0x0, mask 0x7
-
- - - - - - - - - -
63626160595857565554535251504948
 
47464544434241403938373635343332
 
31302928272625242322212019181716
 
1514131211109876543210
 serializedeburstdecouple
BitsTypeResetNameDescription
0rwxdecouple

Decouple enable

1rwxdeburst

Deburst enable

2rwxserialize

Serialize enable

-
- - - - - -
-
idma_reg64_2d_frontend.status @ 0x20
-

DMA Status

-
Reset default = 0x0, mask 0x1
-
- - - - - - - -
63626160595857565554535251504948
 
47464544434241403938373635343332
 
31302928272625242322212019181716
 
1514131211109876543210
 busy
BitsTypeResetNameDescription
0roxbusy

DMA busy

-
- - - - - -
-
idma_reg64_2d_frontend.next_id @ 0x28
-

Next ID, launches transfer, returns 0 if transfer not set up properly.

-
Reset default = 0x0, mask 0xffffffffffffffff
-
- - - - - - -
63626160595857565554535251504948
next_id...
47464544434241403938373635343332
...next_id...
31302928272625242322212019181716
...next_id...
1514131211109876543210
...next_id
BitsTypeResetNameDescription
63:0roxnext_id

Next ID, launches transfer, returns 0 if transfer not set up properly.

-
- - - - - -
-
idma_reg64_2d_frontend.done @ 0x30
-

Get ID of finished transactions.

-
Reset default = 0x0, mask 0xffffffffffffffff
-
- - - - - - -
63626160595857565554535251504948
done...
47464544434241403938373635343332
...done...
31302928272625242322212019181716
...done...
1514131211109876543210
...done
BitsTypeResetNameDescription
63:0roxdone

Get ID of finished transactions.

-
- - - - - -
-
idma_reg64_2d_frontend.stride_src @ 0x38
-

Source Stride

-
Reset default = 0x0, mask 0xffffffffffffffff
-
- - - - - - -
63626160595857565554535251504948
stride_src...
47464544434241403938373635343332
...stride_src...
31302928272625242322212019181716
...stride_src...
1514131211109876543210
...stride_src
BitsTypeResetNameDescription
63:0rwxstride_src

Source Stride

-
- - - - - -
-
idma_reg64_2d_frontend.stride_dst @ 0x40
-

Destination Stride

-
Reset default = 0x0, mask 0xffffffffffffffff
-
- - - - - - -
63626160595857565554535251504948
stride_dst...
47464544434241403938373635343332
...stride_dst...
31302928272625242322212019181716
...stride_dst...
1514131211109876543210
...stride_dst
BitsTypeResetNameDescription
63:0rwxstride_dst

Destination Stride

-
- - - - - -
-
idma_reg64_2d_frontend.num_repetitions @ 0x48
-

Number of 2D repetitions

-
Reset default = 0x0, mask 0xffffffffffffffff
-
- - - - - - -
63626160595857565554535251504948
num_repetitions...
47464544434241403938373635343332
...num_repetitions...
31302928272625242322212019181716
...num_repetitions...
1514131211109876543210
...num_repetitions
BitsTypeResetNameDescription
63:0rw0x0num_repetitions

Number of 2D repetitions

-
- diff --git a/src/frontends/register_64bit_2d/idma_reg64_2d_frontend_reg_pkg.sv b/src/frontends/register_64bit_2d/idma_reg64_2d_frontend_reg_pkg.sv deleted file mode 100644 index 7131af8e..00000000 --- a/src/frontends/register_64bit_2d/idma_reg64_2d_frontend_reg_pkg.sv +++ /dev/null @@ -1,140 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Package auto-generated by `reggen` containing data structure - -package idma_reg64_2d_frontend_reg_pkg; - - // Address widths within the block - parameter int BlockAw = 7; - - //////////////////////////// - // Typedefs for registers // - //////////////////////////// - - typedef struct packed { - logic [63:0] q; - } idma_reg64_2d_frontend_reg2hw_src_addr_reg_t; - - typedef struct packed { - logic [63:0] q; - } idma_reg64_2d_frontend_reg2hw_dst_addr_reg_t; - - typedef struct packed { - logic [63:0] q; - } idma_reg64_2d_frontend_reg2hw_num_bytes_reg_t; - - typedef struct packed { - struct packed { - logic q; - } decouple; - struct packed { - logic q; - } deburst; - struct packed { - logic q; - } serialize; - } idma_reg64_2d_frontend_reg2hw_conf_reg_t; - - typedef struct packed { - logic [63:0] q; - logic re; - } idma_reg64_2d_frontend_reg2hw_next_id_reg_t; - - typedef struct packed { - logic [63:0] q; - logic re; - } idma_reg64_2d_frontend_reg2hw_done_reg_t; - - typedef struct packed { - logic [63:0] q; - } idma_reg64_2d_frontend_reg2hw_stride_src_reg_t; - - typedef struct packed { - logic [63:0] q; - } idma_reg64_2d_frontend_reg2hw_stride_dst_reg_t; - - typedef struct packed { - logic [63:0] q; - } idma_reg64_2d_frontend_reg2hw_num_repetitions_reg_t; - - typedef struct packed { - logic d; - } idma_reg64_2d_frontend_hw2reg_status_reg_t; - - typedef struct packed { - logic [63:0] d; - } idma_reg64_2d_frontend_hw2reg_next_id_reg_t; - - typedef struct packed { - logic [63:0] d; - } idma_reg64_2d_frontend_hw2reg_done_reg_t; - - // Register -> HW type - typedef struct packed { - idma_reg64_2d_frontend_reg2hw_src_addr_reg_t src_addr; // [516:453] - idma_reg64_2d_frontend_reg2hw_dst_addr_reg_t dst_addr; // [452:389] - idma_reg64_2d_frontend_reg2hw_num_bytes_reg_t num_bytes; // [388:325] - idma_reg64_2d_frontend_reg2hw_conf_reg_t conf; // [324:322] - idma_reg64_2d_frontend_reg2hw_next_id_reg_t next_id; // [321:257] - idma_reg64_2d_frontend_reg2hw_done_reg_t done; // [256:192] - idma_reg64_2d_frontend_reg2hw_stride_src_reg_t stride_src; // [191:128] - idma_reg64_2d_frontend_reg2hw_stride_dst_reg_t stride_dst; // [127:64] - idma_reg64_2d_frontend_reg2hw_num_repetitions_reg_t num_repetitions; // [63:0] - } idma_reg64_2d_frontend_reg2hw_t; - - // HW -> register type - typedef struct packed { - idma_reg64_2d_frontend_hw2reg_status_reg_t status; // [128:128] - idma_reg64_2d_frontend_hw2reg_next_id_reg_t next_id; // [127:64] - idma_reg64_2d_frontend_hw2reg_done_reg_t done; // [63:0] - } idma_reg64_2d_frontend_hw2reg_t; - - // Register offsets - parameter logic [BlockAw-1:0] IDMA_REG64_2D_FRONTEND_SRC_ADDR_OFFSET = 7'h 0; - parameter logic [BlockAw-1:0] IDMA_REG64_2D_FRONTEND_DST_ADDR_OFFSET = 7'h 8; - parameter logic [BlockAw-1:0] IDMA_REG64_2D_FRONTEND_NUM_BYTES_OFFSET = 7'h 10; - parameter logic [BlockAw-1:0] IDMA_REG64_2D_FRONTEND_CONF_OFFSET = 7'h 18; - parameter logic [BlockAw-1:0] IDMA_REG64_2D_FRONTEND_STATUS_OFFSET = 7'h 20; - parameter logic [BlockAw-1:0] IDMA_REG64_2D_FRONTEND_NEXT_ID_OFFSET = 7'h 28; - parameter logic [BlockAw-1:0] IDMA_REG64_2D_FRONTEND_DONE_OFFSET = 7'h 30; - parameter logic [BlockAw-1:0] IDMA_REG64_2D_FRONTEND_STRIDE_SRC_OFFSET = 7'h 38; - parameter logic [BlockAw-1:0] IDMA_REG64_2D_FRONTEND_STRIDE_DST_OFFSET = 7'h 40; - parameter logic [BlockAw-1:0] IDMA_REG64_2D_FRONTEND_NUM_REPETITIONS_OFFSET = 7'h 48; - - // Reset values for hwext registers and their fields - parameter logic [0:0] IDMA_REG64_2D_FRONTEND_STATUS_RESVAL = 1'h 0; - parameter logic [63:0] IDMA_REG64_2D_FRONTEND_NEXT_ID_RESVAL = 64'h 0; - parameter logic [63:0] IDMA_REG64_2D_FRONTEND_DONE_RESVAL = 64'h 0; - - // Register index - typedef enum int { - IDMA_REG64_2D_FRONTEND_SRC_ADDR, - IDMA_REG64_2D_FRONTEND_DST_ADDR, - IDMA_REG64_2D_FRONTEND_NUM_BYTES, - IDMA_REG64_2D_FRONTEND_CONF, - IDMA_REG64_2D_FRONTEND_STATUS, - IDMA_REG64_2D_FRONTEND_NEXT_ID, - IDMA_REG64_2D_FRONTEND_DONE, - IDMA_REG64_2D_FRONTEND_STRIDE_SRC, - IDMA_REG64_2D_FRONTEND_STRIDE_DST, - IDMA_REG64_2D_FRONTEND_NUM_REPETITIONS - } idma_reg64_2d_frontend_id_e; - - // Register width information to check illegal writes - parameter logic [3:0] IDMA_REG64_2D_FRONTEND_PERMIT [10] = '{ - 4'b 1111, // index[0] IDMA_REG64_2D_FRONTEND_SRC_ADDR - 4'b 1111, // index[1] IDMA_REG64_2D_FRONTEND_DST_ADDR - 4'b 1111, // index[2] IDMA_REG64_2D_FRONTEND_NUM_BYTES - 4'b 0001, // index[3] IDMA_REG64_2D_FRONTEND_CONF - 4'b 0001, // index[4] IDMA_REG64_2D_FRONTEND_STATUS - 4'b 1111, // index[5] IDMA_REG64_2D_FRONTEND_NEXT_ID - 4'b 1111, // index[6] IDMA_REG64_2D_FRONTEND_DONE - 4'b 1111, // index[7] IDMA_REG64_2D_FRONTEND_STRIDE_SRC - 4'b 1111, // index[8] IDMA_REG64_2D_FRONTEND_STRIDE_DST - 4'b 1111 // index[9] IDMA_REG64_2D_FRONTEND_NUM_REPETITIONS - }; - -endpackage - diff --git a/src/frontends/register_64bit_2d/idma_reg64_2d_frontend_reg_top.sv b/src/frontends/register_64bit_2d/idma_reg64_2d_frontend_reg_top.sv deleted file mode 100644 index f19a37ea..00000000 --- a/src/frontends/register_64bit_2d/idma_reg64_2d_frontend_reg_top.sv +++ /dev/null @@ -1,527 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Top module auto-generated by `reggen` - - -`include "common_cells/assertions.svh" - -module idma_reg64_2d_frontend_reg_top #( - parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic, - parameter int AW = 7 -) ( - input clk_i, - input rst_ni, - input reg_req_t reg_req_i, - output reg_rsp_t reg_rsp_o, - // To HW - output idma_reg64_2d_frontend_reg_pkg::idma_reg64_2d_frontend_reg2hw_t reg2hw, // Write - input idma_reg64_2d_frontend_reg_pkg::idma_reg64_2d_frontend_hw2reg_t hw2reg, // Read - - - // Config - input devmode_i // If 1, explicit error return for unmapped register access -); - - import idma_reg64_2d_frontend_reg_pkg::* ; - - localparam int DW = 64; - localparam int DBW = DW/8; // Byte Width - - // register signals - logic reg_we; - logic reg_re; - logic [AW-1:0] reg_addr; - logic [DW-1:0] reg_wdata; - logic [DBW-1:0] reg_be; - logic [DW-1:0] reg_rdata; - logic reg_error; - - logic addrmiss, wr_err; - - logic [DW-1:0] reg_rdata_next; - - // Below register interface can be changed - reg_req_t reg_intf_req; - reg_rsp_t reg_intf_rsp; - - - assign reg_intf_req = reg_req_i; - assign reg_rsp_o = reg_intf_rsp; - - - assign reg_we = reg_intf_req.valid & reg_intf_req.write; - assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; - assign reg_addr = reg_intf_req.addr; - assign reg_wdata = reg_intf_req.wdata; - assign reg_be = reg_intf_req.wstrb; - assign reg_intf_rsp.rdata = reg_rdata; - assign reg_intf_rsp.error = reg_error; - assign reg_intf_rsp.ready = 1'b1; - - assign reg_rdata = reg_rdata_next ; - assign reg_error = (devmode_i & addrmiss) | wr_err; - - - // Define SW related signals - // Format: __{wd|we|qs} - // or _{wd|we|qs} if field == 1 or 0 - logic [63:0] src_addr_qs; - logic [63:0] src_addr_wd; - logic src_addr_we; - logic [63:0] dst_addr_qs; - logic [63:0] dst_addr_wd; - logic dst_addr_we; - logic [63:0] num_bytes_qs; - logic [63:0] num_bytes_wd; - logic num_bytes_we; - logic conf_decouple_qs; - logic conf_decouple_wd; - logic conf_decouple_we; - logic conf_deburst_qs; - logic conf_deburst_wd; - logic conf_deburst_we; - logic conf_serialize_qs; - logic conf_serialize_wd; - logic conf_serialize_we; - logic status_qs; - logic status_re; - logic [63:0] next_id_qs; - logic next_id_re; - logic [63:0] done_qs; - logic done_re; - logic [63:0] stride_src_qs; - logic [63:0] stride_src_wd; - logic stride_src_we; - logic [63:0] stride_dst_qs; - logic [63:0] stride_dst_wd; - logic stride_dst_we; - logic [63:0] num_repetitions_qs; - logic [63:0] num_repetitions_wd; - logic num_repetitions_we; - - // Register instances - // R[src_addr]: V(False) - - prim_subreg #( - .DW (64), - .SWACCESS("RW"), - .RESVAL (64'h0) - ) u_src_addr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (src_addr_we), - .wd (src_addr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.src_addr.q ), - - // to register interface (read) - .qs (src_addr_qs) - ); - - - // R[dst_addr]: V(False) - - prim_subreg #( - .DW (64), - .SWACCESS("RW"), - .RESVAL (64'h0) - ) u_dst_addr ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (dst_addr_we), - .wd (dst_addr_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.dst_addr.q ), - - // to register interface (read) - .qs (dst_addr_qs) - ); - - - // R[num_bytes]: V(False) - - prim_subreg #( - .DW (64), - .SWACCESS("RW"), - .RESVAL (64'h0) - ) u_num_bytes ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (num_bytes_we), - .wd (num_bytes_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.num_bytes.q ), - - // to register interface (read) - .qs (num_bytes_qs) - ); - - - // R[conf]: V(False) - - // F[decouple]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_conf_decouple ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (conf_decouple_we), - .wd (conf_decouple_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.conf.decouple.q ), - - // to register interface (read) - .qs (conf_decouple_qs) - ); - - - // F[deburst]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_conf_deburst ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (conf_deburst_we), - .wd (conf_deburst_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.conf.deburst.q ), - - // to register interface (read) - .qs (conf_deburst_qs) - ); - - - // F[serialize]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_conf_serialize ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (conf_serialize_we), - .wd (conf_serialize_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.conf.serialize.q ), - - // to register interface (read) - .qs (conf_serialize_qs) - ); - - - // R[status]: V(True) - - prim_subreg_ext #( - .DW (1) - ) u_status ( - .re (status_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.status.d), - .qre (), - .qe (), - .q (), - .qs (status_qs) - ); - - - // R[next_id]: V(True) - - prim_subreg_ext #( - .DW (64) - ) u_next_id ( - .re (next_id_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.next_id.d), - .qre (reg2hw.next_id.re), - .qe (), - .q (reg2hw.next_id.q ), - .qs (next_id_qs) - ); - - - // R[done]: V(True) - - prim_subreg_ext #( - .DW (64) - ) u_done ( - .re (done_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.done.d), - .qre (reg2hw.done.re), - .qe (), - .q (reg2hw.done.q ), - .qs (done_qs) - ); - - - // R[stride_src]: V(False) - - prim_subreg #( - .DW (64), - .SWACCESS("RW"), - .RESVAL (64'h0) - ) u_stride_src ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (stride_src_we), - .wd (stride_src_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.stride_src.q ), - - // to register interface (read) - .qs (stride_src_qs) - ); - - - // R[stride_dst]: V(False) - - prim_subreg #( - .DW (64), - .SWACCESS("RW"), - .RESVAL (64'h0) - ) u_stride_dst ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (stride_dst_we), - .wd (stride_dst_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.stride_dst.q ), - - // to register interface (read) - .qs (stride_dst_qs) - ); - - - // R[num_repetitions]: V(False) - - prim_subreg #( - .DW (64), - .SWACCESS("RW"), - .RESVAL (64'h0) - ) u_num_repetitions ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (num_repetitions_we), - .wd (num_repetitions_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.num_repetitions.q ), - - // to register interface (read) - .qs (num_repetitions_qs) - ); - - - - - logic [9:0] addr_hit; - always_comb begin - addr_hit = '0; - addr_hit[0] = (reg_addr == IDMA_REG64_2D_FRONTEND_SRC_ADDR_OFFSET); - addr_hit[1] = (reg_addr == IDMA_REG64_2D_FRONTEND_DST_ADDR_OFFSET); - addr_hit[2] = (reg_addr == IDMA_REG64_2D_FRONTEND_NUM_BYTES_OFFSET); - addr_hit[3] = (reg_addr == IDMA_REG64_2D_FRONTEND_CONF_OFFSET); - addr_hit[4] = (reg_addr == IDMA_REG64_2D_FRONTEND_STATUS_OFFSET); - addr_hit[5] = (reg_addr == IDMA_REG64_2D_FRONTEND_NEXT_ID_OFFSET); - addr_hit[6] = (reg_addr == IDMA_REG64_2D_FRONTEND_DONE_OFFSET); - addr_hit[7] = (reg_addr == IDMA_REG64_2D_FRONTEND_STRIDE_SRC_OFFSET); - addr_hit[8] = (reg_addr == IDMA_REG64_2D_FRONTEND_STRIDE_DST_OFFSET); - addr_hit[9] = (reg_addr == IDMA_REG64_2D_FRONTEND_NUM_REPETITIONS_OFFSET); - end - - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - - // Check sub-word write is permitted - always_comb begin - wr_err = (reg_we & - ((addr_hit[0] & (|(IDMA_REG64_2D_FRONTEND_PERMIT[0] & ~reg_be))) | - (addr_hit[1] & (|(IDMA_REG64_2D_FRONTEND_PERMIT[1] & ~reg_be))) | - (addr_hit[2] & (|(IDMA_REG64_2D_FRONTEND_PERMIT[2] & ~reg_be))) | - (addr_hit[3] & (|(IDMA_REG64_2D_FRONTEND_PERMIT[3] & ~reg_be))) | - (addr_hit[4] & (|(IDMA_REG64_2D_FRONTEND_PERMIT[4] & ~reg_be))) | - (addr_hit[5] & (|(IDMA_REG64_2D_FRONTEND_PERMIT[5] & ~reg_be))) | - (addr_hit[6] & (|(IDMA_REG64_2D_FRONTEND_PERMIT[6] & ~reg_be))) | - (addr_hit[7] & (|(IDMA_REG64_2D_FRONTEND_PERMIT[7] & ~reg_be))) | - (addr_hit[8] & (|(IDMA_REG64_2D_FRONTEND_PERMIT[8] & ~reg_be))) | - (addr_hit[9] & (|(IDMA_REG64_2D_FRONTEND_PERMIT[9] & ~reg_be))))); - end - - assign src_addr_we = addr_hit[0] & reg_we & !reg_error; - assign src_addr_wd = reg_wdata[63:0]; - - assign dst_addr_we = addr_hit[1] & reg_we & !reg_error; - assign dst_addr_wd = reg_wdata[63:0]; - - assign num_bytes_we = addr_hit[2] & reg_we & !reg_error; - assign num_bytes_wd = reg_wdata[63:0]; - - assign conf_decouple_we = addr_hit[3] & reg_we & !reg_error; - assign conf_decouple_wd = reg_wdata[0]; - - assign conf_deburst_we = addr_hit[3] & reg_we & !reg_error; - assign conf_deburst_wd = reg_wdata[1]; - - assign conf_serialize_we = addr_hit[3] & reg_we & !reg_error; - assign conf_serialize_wd = reg_wdata[2]; - - assign status_re = addr_hit[4] & reg_re & !reg_error; - - assign next_id_re = addr_hit[5] & reg_re & !reg_error; - - assign done_re = addr_hit[6] & reg_re & !reg_error; - - assign stride_src_we = addr_hit[7] & reg_we & !reg_error; - assign stride_src_wd = reg_wdata[63:0]; - - assign stride_dst_we = addr_hit[8] & reg_we & !reg_error; - assign stride_dst_wd = reg_wdata[63:0]; - - assign num_repetitions_we = addr_hit[9] & reg_we & !reg_error; - assign num_repetitions_wd = reg_wdata[63:0]; - - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[63:0] = src_addr_qs; - end - - addr_hit[1]: begin - reg_rdata_next[63:0] = dst_addr_qs; - end - - addr_hit[2]: begin - reg_rdata_next[63:0] = num_bytes_qs; - end - - addr_hit[3]: begin - reg_rdata_next[0] = conf_decouple_qs; - reg_rdata_next[1] = conf_deburst_qs; - reg_rdata_next[2] = conf_serialize_qs; - end - - addr_hit[4]: begin - reg_rdata_next[0] = status_qs; - end - - addr_hit[5]: begin - reg_rdata_next[63:0] = next_id_qs; - end - - addr_hit[6]: begin - reg_rdata_next[63:0] = done_qs; - end - - addr_hit[7]: begin - reg_rdata_next[63:0] = stride_src_qs; - end - - addr_hit[8]: begin - reg_rdata_next[63:0] = stride_dst_qs; - end - - addr_hit[9]: begin - reg_rdata_next[63:0] = num_repetitions_qs; - end - - default: begin - reg_rdata_next = '1; - end - endcase - end - - // Unused signal tieoff - - // wdata / byte enable are not always fully used - // add a blanket unused statement to handle lint waivers - logic unused_wdata; - logic unused_be; - assign unused_wdata = ^reg_wdata; - assign unused_be = ^reg_be; - - // Assertions for Register Interface - `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) - -endmodule diff --git a/src/frontends/register_64bit_2d/reg_html.css b/src/frontends/register_64bit_2d/reg_html.css deleted file mode 100644 index 4cb48edb..00000000 --- a/src/frontends/register_64bit_2d/reg_html.css +++ /dev/null @@ -1,74 +0,0 @@ -/* Stylesheet for reggen HTML register output */ -/* Copyright lowRISC contributors. */ -/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ -/* SPDX-License-Identifier: Apache-2.0 */ - -table.regpic { - width: 95%; - border-collapse: collapse; - margin-left:auto; - margin-right:auto; - table-layout:fixed; -} - -table.regdef { - border: 1px solid black; - width: 80%; - border-collapse: collapse; - margin-left:auto; - margin-right:auto; - table-layout:auto; -} - -table.regdef th { - border: 1px solid black; - font-family: sans-serif; - -} - -td.bitnum { - font-size: 60%; - text-align: center; -} - -td.unused { - border: 1px solid black; - background-color: gray; -} - -td.fname { - border: 1px solid black; - text-align: center; - font-family: sans-serif; -} - - -td.regbits, td.regperm, td.regrv { - border: 1px solid black; - text-align: center; - font-family: sans-serif; -} - -td.regde, td.regfn { - border: 1px solid black; -} - -table.cfgtable { - border: 1px solid black; - width: 80%; - border-collapse: collapse; - margin-left:auto; - margin-right:auto; - table-layout:auto; -} - -table.cfgtable th { - border: 1px solid black; - font-family: sans-serif; - font-weight: bold; -} - -table.cfgtable td { - border: 1px solid black; - font-family: sans-serif; -} diff --git a/src/backend/src/idma_improved_fifo.sv b/src/future/idma_improved_fifo.sv similarity index 74% rename from src/backend/src/idma_improved_fifo.sv rename to src/future/idma_improved_fifo.sv index 427e5883..8c1202bd 100644 --- a/src/backend/src/idma_improved_fifo.sv +++ b/src/future/idma_improved_fifo.sv @@ -1,9 +1,10 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti `include "common_cells/assertions.svh" `include "common_cells/registers.svh" @@ -12,30 +13,38 @@ /// Optimal implementation of a stream FIFO module idma_improved_fifo #( /// Depth can be arbitrary from 2 to 2**32 - parameter int unsigned Depth = 32'd8, - /// Type of the FIFO - parameter type type_t = logic, + parameter int unsigned Depth = 32'd8, /// Print information when the simulation launches - parameter bit PrintInfo = 1'b0, + parameter bit PrintInfo = 1'b0, /// If the FIFO is full, allow reading and writing in the same cycle - parameter bit SameCycleRW = 1'b1 + parameter bit SameCycleRW = 1'b1, + /// Type of the FIFO + parameter type type_t = logic ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic flush_i, // flush the fifo - input logic testmode_i, // test_mode to bypass clock gating - // input interface - input type_t data_i, // data to push into the fifo - input logic valid_i, // input data valid - output logic ready_o, // fifo is not full - // output interface - output type_t data_o, // output data - output logic valid_o, // fifo is not empty - input logic ready_i // pop head from fifo + /// Clock + input logic clk_i, + /// Asynchronous reset active low + input logic rst_ni, + /// Fifo flush + input logic flush_i, + /// Bypass clock gate + input logic testmode_i, + /// data to push into the fifo + input type_t data_i, + /// input data valid + input logic valid_i, + /// fifo is not full + output logic ready_o, + /// output data + output type_t data_o, + /// fifo is not empty + output logic valid_o, + /// pop head from fifo + input logic ready_i ); - // Bit Width of the read and write pointers - // One additional bit to detect overflows - localparam PointerWidth = $clog2(Depth) + 1; + /// Bit Width of the read and write pointers + /// One additional bit to detect overflows + localparam int unsigned PointerWidth = $clog2(Depth) + 1; //-------------------------------------- // Prevent Depth 0 @@ -86,7 +95,7 @@ module idma_improved_fifo #( end else begin // Read valid_o = read_ptr_q[PointerWidth-1] == write_ptr_q[PointerWidth-1] - ? read_ptr_q[PointerWidth-2:0] != write_ptr_q[PointerWidth-2:0] : 1'b1; + ? read_ptr_q[PointerWidth-2:0] != write_ptr_q[PointerWidth-2:0] : 1'b1; if (ready_i) begin if (read_ptr_q[PointerWidth-2:0] == (Depth-1)) begin // On overflow reset pointer to zero and flip imaginary bit @@ -99,20 +108,20 @@ module idma_improved_fifo #( end // Write -> Also able to write if we read in the same cycle - ready_o = (read_ptr_q[PointerWidth-1] == write_ptr_q[PointerWidth-1] + ready_o = (read_ptr_q[PointerWidth-1] == write_ptr_q[PointerWidth-1] ? 1'b1 : write_ptr_q[PointerWidth-2:0] != read_ptr_q[PointerWidth-2:0]) || (SameCycleRW && ready_i && valid_o); if (valid_i) begin clock_gate = 1'b1; data_d[write_ptr_q[PointerWidth-2:0]] = data_i; - + if (write_ptr_q[PointerWidth-2:0] == (Depth-1)) begin // On overflow reset pointer to zero and flip imaginary bit write_ptr_d[PointerWidth-2:0] = '0; write_ptr_d[PointerWidth-1] = !write_ptr_q[PointerWidth-1]; end else begin - // Increment pointer + // Increment pointer write_ptr_d = write_ptr_q + 'd1; end end @@ -122,11 +131,12 @@ module idma_improved_fifo #( // Flip Flops `FF( read_ptr_q, read_ptr_d, '0, clk_i, rst_ni) `FF(write_ptr_q, write_ptr_d, '0, clk_i, rst_ni) - + `FFL(data_q, data_d, clock_gate || testmode_i, '0, clk_i, rst_ni) // no full push `ASSERT_NEVER(CheckFullPush, (!ready_o & valid_i), clk_i, !rst_ni) // empty pop `ASSERT_NEVER(CheckEmptyPop, (!valid_o & ready_i), clk_i, !rst_ni) -endmodule : idma_improved_fifo + +endmodule diff --git a/src/backend/src/idma_legalizer_page_splitter.sv b/src/future/idma_legalizer_page_splitter.sv similarity index 76% rename from src/backend/src/idma_legalizer_page_splitter.sv rename to src/future/idma_legalizer_page_splitter.sv index 87e4e06e..30accee3 100644 --- a/src/backend/src/idma_legalizer_page_splitter.sv +++ b/src/future/idma_legalizer_page_splitter.sv @@ -1,21 +1,27 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Tobias Senti + +/// Legalizer module implementing a page splitter module idma_legalizer_page_splitter #( - parameter int unsigned OffsetWidth = 2, - parameter int unsigned PageAddrWidth = 5, - parameter type addr_t = logic, - parameter type page_len_t = logic, - parameter type page_addr_t = logic + parameter int unsigned OffsetWidth = 32'd2, + parameter int unsigned PageAddrWidth = 32'd5, + parameter type addr_t = logic, + parameter type page_len_t = logic, + parameter type page_addr_t = logic ) ( + /// current address + input addr_t addr_i, + /// Burst enabled? input logic not_bursting_i, - + /// User-given constraints enabled ? input logic reduce_len_i, + /// User-given constraints input logic [2:0] max_llen_i, - input addr_t addr_i, - + /// number of bytes to end of page output page_len_t num_bytes_to_pb_o ); logic [3:0] page_addr_width; @@ -52,4 +58,4 @@ module idma_legalizer_page_splitter #( // we reach the page boundary (bp) assign num_bytes_to_pb_o = page_size - page_offset; -endmodule : idma_legalizer_page_splitter +endmodule diff --git a/src/backend/src/idma_legalizer_pow2_splitter.sv b/src/future/idma_legalizer_pow2_splitter.sv similarity index 83% rename from src/backend/src/idma_legalizer_pow2_splitter.sv rename to src/future/idma_legalizer_pow2_splitter.sv index 3239606d..0d6a05c2 100644 --- a/src/backend/src/idma_legalizer_pow2_splitter.sv +++ b/src/future/idma_legalizer_pow2_splitter.sv @@ -1,20 +1,23 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Tobias Senti + +/// Legalizer module implementing a power of 2 splitter module idma_legalizer_pow2_splitter #( - parameter int unsigned PageAddrWidth = 3, - parameter int unsigned OffsetWidth = 2, - parameter type addr_t = logic, - parameter type len_t = logic + parameter int unsigned OffsetWidth = 32'd2, + parameter int unsigned PageAddrWidth = 32'd3, + parameter type addr_t = logic, + parameter type len_t = logic )( // Current address input addr_t addr_i, // Number of bytes left to transfer input len_t length_i, - // Set if the remaining transfer length is larger + // Set if the remaining transfer length is larger // than what can be represented in len_t input logic length_larger_i, @@ -27,7 +30,8 @@ module idma_legalizer_pow2_splitter #( // How many bytes are left inside the word and transfer logic [OffsetWidth:0] bytes_in_world_left_to_transfer; - assign bytes_in_world_left_to_transfer = (!length_larger_i && bytes_in_word_left > length_i) ? length_i : bytes_in_word_left; + assign bytes_in_world_left_to_transfer = (!length_larger_i && bytes_in_word_left > length_i) ? + length_i : bytes_in_word_left; // Find largest power of 2 that fits inside word -> For subword transfers len_t subword_bytes_to_transfer; @@ -60,7 +64,7 @@ module idma_legalizer_pow2_splitter #( if (aligned_address) begin // Aligned address -> Burst if (length_larger_i) begin - // Length is larger than a full burst -> Full burst + // Length is larger than a full burst -> Full burst bytes_to_transfer_o = 'd1 << PageAddrWidth; end else begin // Burst @@ -71,4 +75,4 @@ module idma_legalizer_pow2_splitter #( bytes_to_transfer_o = subword_bytes_to_transfer; end end -endmodule : idma_legalizer_pow2_splitter +endmodule diff --git a/src/package/idma_pkg.sv b/src/idma_pkg.sv similarity index 97% rename from src/package/idma_pkg.sv rename to src/idma_pkg.sv index 054efab3..3564b87f 100644 --- a/src/package/idma_pkg.sv +++ b/src/idma_pkg.sv @@ -1,9 +1,10 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz -// Tobias Senti + +// Authors: +// - Thomas Benz +// - Tobias Senti /// iDMA Package /// Contains all static type definitions diff --git a/src/include/idma/guard.svh b/src/include/idma/guard.svh index cddea6ad..b2896be1 100644 --- a/src/include/idma/guard.svh +++ b/src/include/idma/guard.svh @@ -1,8 +1,9 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz + +// Authors: +// - Thomas Benz // Guard macros for non-synthesizable code diff --git a/src/include/idma/typedef.svh b/src/include/idma/typedef.svh index e37757a2..b39a6157 100644 --- a/src/include/idma/typedef.svh +++ b/src/include/idma/typedef.svh @@ -1,8 +1,9 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz + +// Authors: +// - Thomas Benz // Macros to define iDMA structs diff --git a/src/legacy/axi_dma_backend.sv b/src/legacy/axi_dma_backend.sv index 20cce510..18f080e6 100644 --- a/src/legacy/axi_dma_backend.sv +++ b/src/legacy/axi_dma_backend.sv @@ -1,8 +1,9 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Michael Rogenmoser + +// Authors: +// - Michael Rogenmoser `include "idma/typedef.svh" `include "idma/guard.svh" diff --git a/src/legacy/midends/idma_2D_midend.sv b/src/legacy/midends/idma_2D_midend.sv index 46f8bd3c..e747bf82 100644 --- a/src/legacy/midends/idma_2D_midend.sv +++ b/src/legacy/midends/idma_2D_midend.sv @@ -1,8 +1,9 @@ // Copyright 2020 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz + +// Authors: +// - Thomas Benz `include "common_cells/registers.svh" diff --git a/src/midends/idma_nd_midend.sv b/src/midends/idma_nd_midend.sv index c7b47956..8a291e28 100644 --- a/src/midends/idma_nd_midend.sv +++ b/src/midends/idma_nd_midend.sv @@ -1,8 +1,9 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz + +// Authors: +// - Thomas Benz `include "common_cells/registers.svh" `include "idma/guard.svh" diff --git a/src/package/Bender.yml b/src/package/Bender.yml deleted file mode 100644 index dfbbbe02..00000000 --- a/src/package/Bender.yml +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51package: -package: - name: idma_pkg - authors: - - "Tobias Senti " - -dependencies: - axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0-beta.3 } - -sources: - - idma_pkg.sv \ No newline at end of file diff --git a/src/systems/cva6_desc/dma_desc_wrap.sv b/src/systems/cva6_desc/dma_desc_wrap.sv index 7d3b86cc..de1441ff 100644 --- a/src/systems/cva6_desc/dma_desc_wrap.sv +++ b/src/systems/cva6_desc/dma_desc_wrap.sv @@ -2,7 +2,8 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Axel Vanoni +// Authors: +// - Axel Vanoni `include "axi/assign.svh" `include "axi/typedef.svh" diff --git a/src/systems/cva6_desc/dma_reg_to_axi.sv b/src/systems/cva6_desc/dma_reg_to_axi.sv index 10d199c1..a66aeab3 100644 --- a/src/systems/cva6_desc/dma_reg_to_axi.sv +++ b/src/systems/cva6_desc/dma_reg_to_axi.sv @@ -2,7 +2,8 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Axel Vanoni +// Authors: +// - Axel Vanoni `include "common_cells/registers.svh" `include "idma/guard.svh" diff --git a/src/systems/cva6_reg/dma_core_wrap.sv b/src/systems/cva6_reg/dma_core_wrap.sv index 622100a0..320b962d 100644 --- a/src/systems/cva6_reg/dma_core_wrap.sv +++ b/src/systems/cva6_reg/dma_core_wrap.sv @@ -1,18 +1,18 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Author: Thomas Benz -// Author: Andreas Kuster -// Author: Paul Scheffler -// -// Description: DMA core wrapper for the CVA6 integration + +// Authors: +// - Thomas Benz +// - Andreas Kuster +// - Paul Scheffler `include "axi/assign.svh" `include "axi/typedef.svh" `include "idma/typedef.svh" `include "register_interface/typedef.svh" +/// DMA core wrapper for the CVA6 integration module dma_core_wrap #( parameter int unsigned AxiAddrWidth = 32'd0, parameter int unsigned AxiDataWidth = 32'd0, diff --git a/src/systems/cva6_reg/driver/cva6_idma.h b/src/systems/cva6_reg/driver/cva6_idma.h index b90ab32c..24438dc7 100644 --- a/src/systems/cva6_reg/driver/cva6_idma.h +++ b/src/systems/cva6_reg/driver/cva6_idma.h @@ -2,10 +2,10 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 // -//Author: Andreas Kuster -// -//Description: Generated register defines for dma_frontend +// Authors: +// - Andreas Kuster +// Description: Generated register defines for dma_frontend #ifndef _DMA_FRONTEND_REG_DEFS_ #define _DMA_FRONTEND_REG_DEFS_ @@ -48,6 +48,6 @@ extern "C" { #define DMA_FRONTEND_DONE_REG_RESVAL 0x0 #ifdef __cplusplus -} // extern "C" +} // extern "C" #endif -#endif // _DMA_FRONTEND_REG_DEFS_ +#endif // _DMA_FRONTEND_REG_DEFS_ diff --git a/src/systems/cva6_reg/driver/encoding.h b/src/systems/cva6_reg/driver/encoding.h index 42a7cb41..823732fc 100644 --- a/src/systems/cva6_reg/driver/encoding.h +++ b/src/systems/cva6_reg/driver/encoding.h @@ -28,114 +28,114 @@ #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H -#define MSTATUS_UIE 0x00000001 -#define MSTATUS_SIE 0x00000002 -#define MSTATUS_HIE 0x00000004 -#define MSTATUS_MIE 0x00000008 -#define MSTATUS_UPIE 0x00000010 -#define MSTATUS_SPIE 0x00000020 -#define MSTATUS_HPIE 0x00000040 -#define MSTATUS_MPIE 0x00000080 -#define MSTATUS_SPP 0x00000100 -#define MSTATUS_VS 0x00000600 -#define MSTATUS_MPP 0x00001800 -#define MSTATUS_FS 0x00006000 -#define MSTATUS_XS 0x00018000 -#define MSTATUS_MPRV 0x00020000 -#define MSTATUS_SUM 0x00040000 -#define MSTATUS_MXR 0x00080000 -#define MSTATUS_TVM 0x00100000 -#define MSTATUS_TW 0x00200000 -#define MSTATUS_TSR 0x00400000 -#define MSTATUS32_SD 0x80000000 -#define MSTATUS_UXL 0x0000000300000000 -#define MSTATUS_SXL 0x0000000C00000000 -#define MSTATUS64_SD 0x8000000000000000 +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_VS 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS64_SD 0x8000000000000000 -#define SSTATUS_UIE 0x00000001 -#define SSTATUS_SIE 0x00000002 -#define SSTATUS_UPIE 0x00000010 -#define SSTATUS_SPIE 0x00000020 -#define SSTATUS_SPP 0x00000100 -#define SSTATUS_VS 0x00000600 -#define SSTATUS_FS 0x00006000 -#define SSTATUS_XS 0x00018000 -#define SSTATUS_SUM 0x00040000 -#define SSTATUS_MXR 0x00080000 -#define SSTATUS32_SD 0x80000000 -#define SSTATUS_UXL 0x0000000300000000 -#define SSTATUS64_SD 0x8000000000000000 +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_VS 0x00000600 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 -#define USTATUS_UIE 0x00000001 -#define USTATUS_UPIE 0x00000010 +#define USTATUS_UIE 0x00000001 +#define USTATUS_UPIE 0x00000010 -#define DCSR_XDEBUGVER (3U<<30) -#define DCSR_NDRESET (1<<29) -#define DCSR_FULLRESET (1<<28) -#define DCSR_EBREAKM (1<<15) -#define DCSR_EBREAKH (1<<14) -#define DCSR_EBREAKS (1<<13) -#define DCSR_EBREAKU (1<<12) -#define DCSR_STOPCYCLE (1<<10) -#define DCSR_STOPTIME (1<<9) -#define DCSR_CAUSE (7<<6) -#define DCSR_DEBUGINT (1<<5) -#define DCSR_HALT (1<<3) -#define DCSR_STEP (1<<2) -#define DCSR_PRV (3<<0) +#define DCSR_XDEBUGVER (3U << 30) +#define DCSR_NDRESET (1 << 29) +#define DCSR_FULLRESET (1 << 28) +#define DCSR_EBREAKM (1 << 15) +#define DCSR_EBREAKH (1 << 14) +#define DCSR_EBREAKS (1 << 13) +#define DCSR_EBREAKU (1 << 12) +#define DCSR_STOPCYCLE (1 << 10) +#define DCSR_STOPTIME (1 << 9) +#define DCSR_CAUSE (7 << 6) +#define DCSR_DEBUGINT (1 << 5) +#define DCSR_HALT (1 << 3) +#define DCSR_STEP (1 << 2) +#define DCSR_PRV (3 << 0) -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 #define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEP 4 -#define DCSR_CAUSE_HALT 5 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 -#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) -#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) -#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) +#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL << ((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11)) -#define MCONTROL_SELECT (1<<19) -#define MCONTROL_TIMING (1<<18) -#define MCONTROL_ACTION (0x3f<<12) -#define MCONTROL_CHAIN (1<<11) -#define MCONTROL_MATCH (0xf<<7) -#define MCONTROL_M (1<<6) -#define MCONTROL_H (1<<5) -#define MCONTROL_S (1<<4) -#define MCONTROL_U (1<<3) -#define MCONTROL_EXECUTE (1<<2) -#define MCONTROL_STORE (1<<1) -#define MCONTROL_LOAD (1<<0) +#define MCONTROL_SELECT (1 << 19) +#define MCONTROL_TIMING (1 << 18) +#define MCONTROL_ACTION (0x3f << 12) +#define MCONTROL_CHAIN (1 << 11) +#define MCONTROL_MATCH (0xf << 7) +#define MCONTROL_M (1 << 6) +#define MCONTROL_H (1 << 5) +#define MCONTROL_S (1 << 4) +#define MCONTROL_U (1 << 3) +#define MCONTROL_EXECUTE (1 << 2) +#define MCONTROL_STORE (1 << 1) +#define MCONTROL_LOAD (1 << 0) -#define MCONTROL_TYPE_NONE 0 -#define MCONTROL_TYPE_MATCH 2 +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 -#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 -#define MCONTROL_ACTION_DEBUG_MODE 1 -#define MCONTROL_ACTION_TRACE_START 2 -#define MCONTROL_ACTION_TRACE_STOP 3 -#define MCONTROL_ACTION_TRACE_EMIT 4 +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 -#define MCONTROL_MATCH_EQUAL 0 -#define MCONTROL_MATCH_NAPOT 1 -#define MCONTROL_MATCH_GE 2 -#define MCONTROL_MATCH_LT 3 -#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 #define MCONTROL_MATCH_MASK_HIGH 5 -#define MIP_USIP (1 << IRQ_U_SOFT) -#define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_HSIP (1 << IRQ_H_SOFT) -#define MIP_MSIP (1 << IRQ_M_SOFT) -#define MIP_UTIP (1 << IRQ_U_TIMER) -#define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_HTIP (1 << IRQ_H_TIMER) -#define MIP_MTIP (1 << IRQ_M_TIMER) -#define MIP_UEIP (1 << IRQ_U_EXT) -#define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_HEIP (1 << IRQ_H_EXT) -#define MIP_MEIP (1 << IRQ_M_EXT) +#define MIP_USIP (1 << IRQ_U_SOFT) +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_UTIP (1 << IRQ_U_TIMER) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_UEIP (1 << IRQ_U_EXT) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP @@ -147,12 +147,12 @@ #define SATP32_MODE 0x80000000 #define SATP32_ASID 0x7FC00000 -#define SATP32_PPN 0x003FFFFF +#define SATP32_PPN 0x003FFFFF #define SATP64_MODE 0xF000000000000000 #define SATP64_ASID 0x0FFFF00000000000 -#define SATP64_PPN 0x00000FFFFFFFFFFF +#define SATP64_PPN 0x00000FFFFFFFFFFF -#define SATP_MODE_OFF 0 +#define SATP_MODE_OFF 0 #define SATP_MODE_SV32 1 #define SATP_MODE_SV39 8 #define SATP_MODE_SV48 9 @@ -160,52 +160,52 @@ #define SATP_MODE_SV64 11 #define PMP_NO_ACCESS 0x00 -#define PMP_R 0x01 -#define PMP_W 0x02 -#define PMP_X 0x04 -#define PMP_A 0x18 -#define PMP_L 0x80 -#define PMP_SHIFT 2 +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 -#define PMP_TOR 0x08 -#define PMP_NA4 0x10 +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 #define PMP_NAPOT 0x18 -#define IRQ_U_SOFT 0 -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_U_TIMER 4 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_U_EXT 8 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 +#define IRQ_U_SOFT 0 +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_U_TIMER 4 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_U_EXT 8 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 -#define DEFAULT_RSTVEC 0x00001000 -#define CLINT_BASE 0x02000000 -#define CLINT_SIZE 0x000c0000 -#define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 /* page table entry (PTE) fields */ -#define PTE_V 0x001 /* Valid */ -#define PTE_R 0x002 /* Read */ -#define PTE_W 0x004 /* Write */ -#define PTE_X 0x008 /* Execute */ -#define PTE_U 0x010 /* User */ -#define PTE_G 0x020 /* Global */ -#define PTE_A 0x040 /* Accessed */ -#define PTE_D 0x080 /* Dirty */ -#define PTE_SOFT 0x300 /* Reserved for Software */ -#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ -#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ -#define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ -#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ +#define PTE_V 0x001 /* Valid */ +#define PTE_R 0x002 /* Read */ +#define PTE_W 0x004 /* Write */ +#define PTE_X 0x008 /* Execute */ +#define PTE_U 0x010 /* User */ +#define PTE_G 0x020 /* Global */ +#define PTE_A 0x040 /* Accessed */ +#define PTE_D 0x080 /* Dirty */ +#define PTE_SOFT 0x300 /* Reserved for Software */ +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ +#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ +#define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ +#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ #define PTE_PPN_SHIFT 10 @@ -214,15 +214,15 @@ #ifdef __riscv #if __riscv_xlen == 64 -# define MSTATUS_SD MSTATUS64_SD -# define SSTATUS_SD SSTATUS64_SD -# define RISCV_PGLEVEL_BITS 9 -# define SATP_MODE SATP64_MODE +#define MSTATUS_SD MSTATUS64_SD +#define SSTATUS_SD SSTATUS64_SD +#define RISCV_PGLEVEL_BITS 9 +#define SATP_MODE SATP64_MODE #else -# define MSTATUS_SD MSTATUS32_SD -# define SSTATUS_SD SSTATUS32_SD -# define RISCV_PGLEVEL_BITS 10 -# define SATP_MODE SATP32_MODE +#define MSTATUS_SD MSTATUS32_SD +#define SSTATUS_SD SSTATUS32_SD +#define RISCV_PGLEVEL_BITS 10 +#define SATP_MODE SATP32_MODE #endif #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) @@ -231,24 +231,35 @@ #ifdef __GNUC__ -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) +#define read_csr(reg) \ + ({ \ + unsigned long __tmp; \ + asm volatile("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; \ + }) -#define write_csr(reg, val) ({ \ - asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) +#define write_csr(reg, val) ({ asm volatile("csrw " #reg ", %0" ::"rK"(val)); }) -#define swap_csr(reg, val) ({ unsigned long __tmp; \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ - __tmp; }) +#define swap_csr(reg, val) \ + ({ \ + unsigned long __tmp; \ + asm volatile("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; \ + }) -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) +#define set_csr(reg, bit) \ + ({ \ + unsigned long __tmp; \ + asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; \ + }) -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) +#define clear_csr(reg, bit) \ + ({ \ + unsigned long __tmp; \ + asm volatile("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; \ + }) #define rdtime() read_csr(time) #define rdcycle() read_csr(cycle) @@ -265,1347 +276,1347 @@ #ifndef RISCV_ENCODING_H #define RISCV_ENCODING_H #define MATCH_SLLI_RV32 0x1013 -#define MASK_SLLI_RV32 0xfe00707f +#define MASK_SLLI_RV32 0xfe00707f #define MATCH_SRLI_RV32 0x5013 -#define MASK_SRLI_RV32 0xfe00707f +#define MASK_SRLI_RV32 0xfe00707f #define MATCH_SRAI_RV32 0x40005013 -#define MASK_SRAI_RV32 0xfe00707f +#define MASK_SRAI_RV32 0xfe00707f #define MATCH_FRFLAGS 0x102073 -#define MASK_FRFLAGS 0xfffff07f +#define MASK_FRFLAGS 0xfffff07f #define MATCH_FSFLAGS 0x101073 -#define MASK_FSFLAGS 0xfff0707f +#define MASK_FSFLAGS 0xfff0707f #define MATCH_FSFLAGSI 0x105073 -#define MASK_FSFLAGSI 0xfff0707f +#define MASK_FSFLAGSI 0xfff0707f #define MATCH_FRRM 0x202073 -#define MASK_FRRM 0xfffff07f +#define MASK_FRRM 0xfffff07f #define MATCH_FSRM 0x201073 -#define MASK_FSRM 0xfff0707f +#define MASK_FSRM 0xfff0707f #define MATCH_FSRMI 0x205073 -#define MASK_FSRMI 0xfff0707f +#define MASK_FSRMI 0xfff0707f #define MATCH_FSCSR 0x301073 -#define MASK_FSCSR 0xfff0707f +#define MASK_FSCSR 0xfff0707f #define MATCH_FRCSR 0x302073 -#define MASK_FRCSR 0xfffff07f +#define MASK_FRCSR 0xfffff07f #define MATCH_RDCYCLE 0xc0002073 -#define MASK_RDCYCLE 0xfffff07f +#define MASK_RDCYCLE 0xfffff07f #define MATCH_RDTIME 0xc0102073 -#define MASK_RDTIME 0xfffff07f +#define MASK_RDTIME 0xfffff07f #define MATCH_RDINSTRET 0xc0202073 -#define MASK_RDINSTRET 0xfffff07f +#define MASK_RDINSTRET 0xfffff07f #define MATCH_RDCYCLEH 0xc8002073 -#define MASK_RDCYCLEH 0xfffff07f +#define MASK_RDCYCLEH 0xfffff07f #define MATCH_RDTIMEH 0xc8102073 -#define MASK_RDTIMEH 0xfffff07f +#define MASK_RDTIMEH 0xfffff07f #define MATCH_RDINSTRETH 0xc8202073 -#define MASK_RDINSTRETH 0xfffff07f +#define MASK_RDINSTRETH 0xfffff07f #define MATCH_SCALL 0x73 -#define MASK_SCALL 0xffffffff +#define MASK_SCALL 0xffffffff #define MATCH_SBREAK 0x100073 -#define MASK_SBREAK 0xffffffff +#define MASK_SBREAK 0xffffffff #define MATCH_FMV_X_S 0xe0000053 -#define MASK_FMV_X_S 0xfff0707f +#define MASK_FMV_X_S 0xfff0707f #define MATCH_FMV_S_X 0xf0000053 -#define MASK_FMV_S_X 0xfff0707f +#define MASK_FMV_S_X 0xfff0707f #define MATCH_FENCE_TSO 0x8330000f -#define MASK_FENCE_TSO 0xfff0707f +#define MASK_FENCE_TSO 0xfff0707f #define MATCH_PAUSE 0x100000f -#define MASK_PAUSE 0xffffffff +#define MASK_PAUSE 0xffffffff #define MATCH_BEQ 0x63 -#define MASK_BEQ 0x707f +#define MASK_BEQ 0x707f #define MATCH_BNE 0x1063 -#define MASK_BNE 0x707f +#define MASK_BNE 0x707f #define MATCH_BLT 0x4063 -#define MASK_BLT 0x707f +#define MASK_BLT 0x707f #define MATCH_BGE 0x5063 -#define MASK_BGE 0x707f +#define MASK_BGE 0x707f #define MATCH_BLTU 0x6063 -#define MASK_BLTU 0x707f +#define MASK_BLTU 0x707f #define MATCH_BGEU 0x7063 -#define MASK_BGEU 0x707f +#define MASK_BGEU 0x707f #define MATCH_JALR 0x67 -#define MASK_JALR 0x707f +#define MASK_JALR 0x707f #define MATCH_JAL 0x6f -#define MASK_JAL 0x7f +#define MASK_JAL 0x7f #define MATCH_LUI 0x37 -#define MASK_LUI 0x7f +#define MASK_LUI 0x7f #define MATCH_AUIPC 0x17 -#define MASK_AUIPC 0x7f +#define MASK_AUIPC 0x7f #define MATCH_ADDI 0x13 -#define MASK_ADDI 0x707f +#define MASK_ADDI 0x707f #define MATCH_SLLI 0x1013 -#define MASK_SLLI 0xfc00707f +#define MASK_SLLI 0xfc00707f #define MATCH_SLTI 0x2013 -#define MASK_SLTI 0x707f +#define MASK_SLTI 0x707f #define MATCH_SLTIU 0x3013 -#define MASK_SLTIU 0x707f +#define MASK_SLTIU 0x707f #define MATCH_XORI 0x4013 -#define MASK_XORI 0x707f +#define MASK_XORI 0x707f #define MATCH_SRLI 0x5013 -#define MASK_SRLI 0xfc00707f +#define MASK_SRLI 0xfc00707f #define MATCH_SRAI 0x40005013 -#define MASK_SRAI 0xfc00707f +#define MASK_SRAI 0xfc00707f #define MATCH_ORI 0x6013 -#define MASK_ORI 0x707f +#define MASK_ORI 0x707f #define MATCH_ANDI 0x7013 -#define MASK_ANDI 0x707f +#define MASK_ANDI 0x707f #define MATCH_ADD 0x33 -#define MASK_ADD 0xfe00707f +#define MASK_ADD 0xfe00707f #define MATCH_SUB 0x40000033 -#define MASK_SUB 0xfe00707f +#define MASK_SUB 0xfe00707f #define MATCH_SLL 0x1033 -#define MASK_SLL 0xfe00707f +#define MASK_SLL 0xfe00707f #define MATCH_SLT 0x2033 -#define MASK_SLT 0xfe00707f +#define MASK_SLT 0xfe00707f #define MATCH_SLTU 0x3033 -#define MASK_SLTU 0xfe00707f +#define MASK_SLTU 0xfe00707f #define MATCH_XOR 0x4033 -#define MASK_XOR 0xfe00707f +#define MASK_XOR 0xfe00707f #define MATCH_SRL 0x5033 -#define MASK_SRL 0xfe00707f +#define MASK_SRL 0xfe00707f #define MATCH_SRA 0x40005033 -#define MASK_SRA 0xfe00707f +#define MASK_SRA 0xfe00707f #define MATCH_OR 0x6033 -#define MASK_OR 0xfe00707f +#define MASK_OR 0xfe00707f #define MATCH_AND 0x7033 -#define MASK_AND 0xfe00707f +#define MASK_AND 0xfe00707f #define MATCH_LB 0x3 -#define MASK_LB 0x707f +#define MASK_LB 0x707f #define MATCH_LH 0x1003 -#define MASK_LH 0x707f +#define MASK_LH 0x707f #define MATCH_LW 0x2003 -#define MASK_LW 0x707f +#define MASK_LW 0x707f #define MATCH_LBU 0x4003 -#define MASK_LBU 0x707f +#define MASK_LBU 0x707f #define MATCH_LHU 0x5003 -#define MASK_LHU 0x707f +#define MASK_LHU 0x707f #define MATCH_SB 0x23 -#define MASK_SB 0x707f +#define MASK_SB 0x707f #define MATCH_SH 0x1023 -#define MASK_SH 0x707f +#define MASK_SH 0x707f #define MATCH_SW 0x2023 -#define MASK_SW 0x707f +#define MASK_SW 0x707f #define MATCH_FENCE 0xf -#define MASK_FENCE 0x707f +#define MASK_FENCE 0x707f #define MATCH_FENCE_I 0x100f -#define MASK_FENCE_I 0x707f +#define MASK_FENCE_I 0x707f #define MATCH_ADDIW 0x1b -#define MASK_ADDIW 0x707f +#define MASK_ADDIW 0x707f #define MATCH_SLLIW 0x101b -#define MASK_SLLIW 0xfe00707f +#define MASK_SLLIW 0xfe00707f #define MATCH_SRLIW 0x501b -#define MASK_SRLIW 0xfe00707f +#define MASK_SRLIW 0xfe00707f #define MATCH_SRAIW 0x4000501b -#define MASK_SRAIW 0xfe00707f +#define MASK_SRAIW 0xfe00707f #define MATCH_ADDW 0x3b -#define MASK_ADDW 0xfe00707f +#define MASK_ADDW 0xfe00707f #define MATCH_SUBW 0x4000003b -#define MASK_SUBW 0xfe00707f +#define MASK_SUBW 0xfe00707f #define MATCH_SLLW 0x103b -#define MASK_SLLW 0xfe00707f +#define MASK_SLLW 0xfe00707f #define MATCH_SRLW 0x503b -#define MASK_SRLW 0xfe00707f +#define MASK_SRLW 0xfe00707f #define MATCH_SRAW 0x4000503b -#define MASK_SRAW 0xfe00707f +#define MASK_SRAW 0xfe00707f #define MATCH_LD 0x3003 -#define MASK_LD 0x707f +#define MASK_LD 0x707f #define MATCH_LWU 0x6003 -#define MASK_LWU 0x707f +#define MASK_LWU 0x707f #define MATCH_SD 0x3023 -#define MASK_SD 0x707f +#define MASK_SD 0x707f #define MATCH_MUL 0x2000033 -#define MASK_MUL 0xfe00707f +#define MASK_MUL 0xfe00707f #define MATCH_MULH 0x2001033 -#define MASK_MULH 0xfe00707f +#define MASK_MULH 0xfe00707f #define MATCH_MULHSU 0x2002033 -#define MASK_MULHSU 0xfe00707f +#define MASK_MULHSU 0xfe00707f #define MATCH_MULHU 0x2003033 -#define MASK_MULHU 0xfe00707f +#define MASK_MULHU 0xfe00707f #define MATCH_DIV 0x2004033 -#define MASK_DIV 0xfe00707f +#define MASK_DIV 0xfe00707f #define MATCH_DIVU 0x2005033 -#define MASK_DIVU 0xfe00707f +#define MASK_DIVU 0xfe00707f #define MATCH_REM 0x2006033 -#define MASK_REM 0xfe00707f +#define MASK_REM 0xfe00707f #define MATCH_REMU 0x2007033 -#define MASK_REMU 0xfe00707f +#define MASK_REMU 0xfe00707f #define MATCH_MULW 0x200003b -#define MASK_MULW 0xfe00707f +#define MASK_MULW 0xfe00707f #define MATCH_DIVW 0x200403b -#define MASK_DIVW 0xfe00707f +#define MASK_DIVW 0xfe00707f #define MATCH_DIVUW 0x200503b -#define MASK_DIVUW 0xfe00707f +#define MASK_DIVUW 0xfe00707f #define MATCH_REMW 0x200603b -#define MASK_REMW 0xfe00707f +#define MASK_REMW 0xfe00707f #define MATCH_REMUW 0x200703b -#define MASK_REMUW 0xfe00707f +#define MASK_REMUW 0xfe00707f #define MATCH_AMOADD_W 0x202f -#define MASK_AMOADD_W 0xf800707f +#define MASK_AMOADD_W 0xf800707f #define MATCH_AMOXOR_W 0x2000202f -#define MASK_AMOXOR_W 0xf800707f +#define MASK_AMOXOR_W 0xf800707f #define MATCH_AMOOR_W 0x4000202f -#define MASK_AMOOR_W 0xf800707f +#define MASK_AMOOR_W 0xf800707f #define MATCH_AMOAND_W 0x6000202f -#define MASK_AMOAND_W 0xf800707f +#define MASK_AMOAND_W 0xf800707f #define MATCH_AMOMIN_W 0x8000202f -#define MASK_AMOMIN_W 0xf800707f +#define MASK_AMOMIN_W 0xf800707f #define MATCH_AMOMAX_W 0xa000202f -#define MASK_AMOMAX_W 0xf800707f +#define MASK_AMOMAX_W 0xf800707f #define MATCH_AMOMINU_W 0xc000202f -#define MASK_AMOMINU_W 0xf800707f +#define MASK_AMOMINU_W 0xf800707f #define MATCH_AMOMAXU_W 0xe000202f -#define MASK_AMOMAXU_W 0xf800707f +#define MASK_AMOMAXU_W 0xf800707f #define MATCH_AMOSWAP_W 0x800202f -#define MASK_AMOSWAP_W 0xf800707f +#define MASK_AMOSWAP_W 0xf800707f #define MATCH_LR_W 0x1000202f -#define MASK_LR_W 0xf9f0707f +#define MASK_LR_W 0xf9f0707f #define MATCH_SC_W 0x1800202f -#define MASK_SC_W 0xf800707f +#define MASK_SC_W 0xf800707f #define MATCH_AMOADD_D 0x302f -#define MASK_AMOADD_D 0xf800707f +#define MASK_AMOADD_D 0xf800707f #define MATCH_AMOXOR_D 0x2000302f -#define MASK_AMOXOR_D 0xf800707f +#define MASK_AMOXOR_D 0xf800707f #define MATCH_AMOOR_D 0x4000302f -#define MASK_AMOOR_D 0xf800707f +#define MASK_AMOOR_D 0xf800707f #define MATCH_AMOAND_D 0x6000302f -#define MASK_AMOAND_D 0xf800707f +#define MASK_AMOAND_D 0xf800707f #define MATCH_AMOMIN_D 0x8000302f -#define MASK_AMOMIN_D 0xf800707f +#define MASK_AMOMIN_D 0xf800707f #define MATCH_AMOMAX_D 0xa000302f -#define MASK_AMOMAX_D 0xf800707f +#define MASK_AMOMAX_D 0xf800707f #define MATCH_AMOMINU_D 0xc000302f -#define MASK_AMOMINU_D 0xf800707f +#define MASK_AMOMINU_D 0xf800707f #define MATCH_AMOMAXU_D 0xe000302f -#define MASK_AMOMAXU_D 0xf800707f +#define MASK_AMOMAXU_D 0xf800707f #define MATCH_AMOSWAP_D 0x800302f -#define MASK_AMOSWAP_D 0xf800707f +#define MASK_AMOSWAP_D 0xf800707f #define MATCH_LR_D 0x1000302f -#define MASK_LR_D 0xf9f0707f +#define MASK_LR_D 0xf9f0707f #define MATCH_SC_D 0x1800302f -#define MASK_SC_D 0xf800707f +#define MASK_SC_D 0xf800707f #define MATCH_FADD_S 0x53 -#define MASK_FADD_S 0xfe00007f +#define MASK_FADD_S 0xfe00007f #define MATCH_FSUB_S 0x8000053 -#define MASK_FSUB_S 0xfe00007f +#define MASK_FSUB_S 0xfe00007f #define MATCH_FMUL_S 0x10000053 -#define MASK_FMUL_S 0xfe00007f +#define MASK_FMUL_S 0xfe00007f #define MATCH_FDIV_S 0x18000053 -#define MASK_FDIV_S 0xfe00007f +#define MASK_FDIV_S 0xfe00007f #define MATCH_FSGNJ_S 0x20000053 -#define MASK_FSGNJ_S 0xfe00707f +#define MASK_FSGNJ_S 0xfe00707f #define MATCH_FSGNJN_S 0x20001053 -#define MASK_FSGNJN_S 0xfe00707f +#define MASK_FSGNJN_S 0xfe00707f #define MATCH_FSGNJX_S 0x20002053 -#define MASK_FSGNJX_S 0xfe00707f +#define MASK_FSGNJX_S 0xfe00707f #define MATCH_FMIN_S 0x28000053 -#define MASK_FMIN_S 0xfe00707f +#define MASK_FMIN_S 0xfe00707f #define MATCH_FMAX_S 0x28001053 -#define MASK_FMAX_S 0xfe00707f +#define MASK_FMAX_S 0xfe00707f #define MATCH_FSQRT_S 0x58000053 -#define MASK_FSQRT_S 0xfff0007f +#define MASK_FSQRT_S 0xfff0007f #define MATCH_FLE_S 0xa0000053 -#define MASK_FLE_S 0xfe00707f +#define MASK_FLE_S 0xfe00707f #define MATCH_FLT_S 0xa0001053 -#define MASK_FLT_S 0xfe00707f +#define MASK_FLT_S 0xfe00707f #define MATCH_FEQ_S 0xa0002053 -#define MASK_FEQ_S 0xfe00707f +#define MASK_FEQ_S 0xfe00707f #define MATCH_FCVT_W_S 0xc0000053 -#define MASK_FCVT_W_S 0xfff0007f +#define MASK_FCVT_W_S 0xfff0007f #define MATCH_FCVT_WU_S 0xc0100053 -#define MASK_FCVT_WU_S 0xfff0007f +#define MASK_FCVT_WU_S 0xfff0007f #define MATCH_FMV_X_W 0xe0000053 -#define MASK_FMV_X_W 0xfff0707f +#define MASK_FMV_X_W 0xfff0707f #define MATCH_FCLASS_S 0xe0001053 -#define MASK_FCLASS_S 0xfff0707f +#define MASK_FCLASS_S 0xfff0707f #define MATCH_FCVT_S_W 0xd0000053 -#define MASK_FCVT_S_W 0xfff0007f +#define MASK_FCVT_S_W 0xfff0007f #define MATCH_FCVT_S_WU 0xd0100053 -#define MASK_FCVT_S_WU 0xfff0007f +#define MASK_FCVT_S_WU 0xfff0007f #define MATCH_FMV_W_X 0xf0000053 -#define MASK_FMV_W_X 0xfff0707f +#define MASK_FMV_W_X 0xfff0707f #define MATCH_FLW 0x2007 -#define MASK_FLW 0x707f +#define MASK_FLW 0x707f #define MATCH_FSW 0x2027 -#define MASK_FSW 0x707f +#define MASK_FSW 0x707f #define MATCH_FMADD_S 0x43 -#define MASK_FMADD_S 0x600007f +#define MASK_FMADD_S 0x600007f #define MATCH_FMSUB_S 0x47 -#define MASK_FMSUB_S 0x600007f +#define MASK_FMSUB_S 0x600007f #define MATCH_FNMSUB_S 0x4b -#define MASK_FNMSUB_S 0x600007f +#define MASK_FNMSUB_S 0x600007f #define MATCH_FNMADD_S 0x4f -#define MASK_FNMADD_S 0x600007f +#define MASK_FNMADD_S 0x600007f #define MATCH_FCVT_L_S 0xc0200053 -#define MASK_FCVT_L_S 0xfff0007f +#define MASK_FCVT_L_S 0xfff0007f #define MATCH_FCVT_LU_S 0xc0300053 -#define MASK_FCVT_LU_S 0xfff0007f +#define MASK_FCVT_LU_S 0xfff0007f #define MATCH_FCVT_S_L 0xd0200053 -#define MASK_FCVT_S_L 0xfff0007f +#define MASK_FCVT_S_L 0xfff0007f #define MATCH_FCVT_S_LU 0xd0300053 -#define MASK_FCVT_S_LU 0xfff0007f +#define MASK_FCVT_S_LU 0xfff0007f #define MATCH_FADD_D 0x2000053 -#define MASK_FADD_D 0xfe00007f +#define MASK_FADD_D 0xfe00007f #define MATCH_FSUB_D 0xa000053 -#define MASK_FSUB_D 0xfe00007f +#define MASK_FSUB_D 0xfe00007f #define MATCH_FMUL_D 0x12000053 -#define MASK_FMUL_D 0xfe00007f +#define MASK_FMUL_D 0xfe00007f #define MATCH_FDIV_D 0x1a000053 -#define MASK_FDIV_D 0xfe00007f +#define MASK_FDIV_D 0xfe00007f #define MATCH_FSGNJ_D 0x22000053 -#define MASK_FSGNJ_D 0xfe00707f +#define MASK_FSGNJ_D 0xfe00707f #define MATCH_FSGNJN_D 0x22001053 -#define MASK_FSGNJN_D 0xfe00707f +#define MASK_FSGNJN_D 0xfe00707f #define MATCH_FSGNJX_D 0x22002053 -#define MASK_FSGNJX_D 0xfe00707f +#define MASK_FSGNJX_D 0xfe00707f #define MATCH_FMIN_D 0x2a000053 -#define MASK_FMIN_D 0xfe00707f +#define MASK_FMIN_D 0xfe00707f #define MATCH_FMAX_D 0x2a001053 -#define MASK_FMAX_D 0xfe00707f +#define MASK_FMAX_D 0xfe00707f #define MATCH_FCVT_S_D 0x40100053 -#define MASK_FCVT_S_D 0xfff0007f +#define MASK_FCVT_S_D 0xfff0007f #define MATCH_FCVT_D_S 0x42000053 -#define MASK_FCVT_D_S 0xfff0007f +#define MASK_FCVT_D_S 0xfff0007f #define MATCH_FSQRT_D 0x5a000053 -#define MASK_FSQRT_D 0xfff0007f +#define MASK_FSQRT_D 0xfff0007f #define MATCH_FLE_D 0xa2000053 -#define MASK_FLE_D 0xfe00707f +#define MASK_FLE_D 0xfe00707f #define MATCH_FLT_D 0xa2001053 -#define MASK_FLT_D 0xfe00707f +#define MASK_FLT_D 0xfe00707f #define MATCH_FEQ_D 0xa2002053 -#define MASK_FEQ_D 0xfe00707f +#define MASK_FEQ_D 0xfe00707f #define MATCH_FCVT_W_D 0xc2000053 -#define MASK_FCVT_W_D 0xfff0007f +#define MASK_FCVT_W_D 0xfff0007f #define MATCH_FCVT_WU_D 0xc2100053 -#define MASK_FCVT_WU_D 0xfff0007f +#define MASK_FCVT_WU_D 0xfff0007f #define MATCH_FCLASS_D 0xe2001053 -#define MASK_FCLASS_D 0xfff0707f +#define MASK_FCLASS_D 0xfff0707f #define MATCH_FCVT_D_W 0xd2000053 -#define MASK_FCVT_D_W 0xfff0007f +#define MASK_FCVT_D_W 0xfff0007f #define MATCH_FCVT_D_WU 0xd2100053 -#define MASK_FCVT_D_WU 0xfff0007f +#define MASK_FCVT_D_WU 0xfff0007f #define MATCH_FLD 0x3007 -#define MASK_FLD 0x707f +#define MASK_FLD 0x707f #define MATCH_FSD 0x3027 -#define MASK_FSD 0x707f +#define MASK_FSD 0x707f #define MATCH_FMADD_D 0x2000043 -#define MASK_FMADD_D 0x600007f +#define MASK_FMADD_D 0x600007f #define MATCH_FMSUB_D 0x2000047 -#define MASK_FMSUB_D 0x600007f +#define MASK_FMSUB_D 0x600007f #define MATCH_FNMSUB_D 0x200004b -#define MASK_FNMSUB_D 0x600007f +#define MASK_FNMSUB_D 0x600007f #define MATCH_FNMADD_D 0x200004f -#define MASK_FNMADD_D 0x600007f +#define MASK_FNMADD_D 0x600007f #define MATCH_FCVT_L_D 0xc2200053 -#define MASK_FCVT_L_D 0xfff0007f +#define MASK_FCVT_L_D 0xfff0007f #define MATCH_FCVT_LU_D 0xc2300053 -#define MASK_FCVT_LU_D 0xfff0007f +#define MASK_FCVT_LU_D 0xfff0007f #define MATCH_FMV_X_D 0xe2000053 -#define MASK_FMV_X_D 0xfff0707f +#define MASK_FMV_X_D 0xfff0707f #define MATCH_FCVT_D_L 0xd2200053 -#define MASK_FCVT_D_L 0xfff0007f +#define MASK_FCVT_D_L 0xfff0007f #define MATCH_FCVT_D_LU 0xd2300053 -#define MASK_FCVT_D_LU 0xfff0007f +#define MASK_FCVT_D_LU 0xfff0007f #define MATCH_FMV_D_X 0xf2000053 -#define MASK_FMV_D_X 0xfff0707f +#define MASK_FMV_D_X 0xfff0707f #define MATCH_FADD_Q 0x6000053 -#define MASK_FADD_Q 0xfe00007f +#define MASK_FADD_Q 0xfe00007f #define MATCH_FSUB_Q 0xe000053 -#define MASK_FSUB_Q 0xfe00007f +#define MASK_FSUB_Q 0xfe00007f #define MATCH_FMUL_Q 0x16000053 -#define MASK_FMUL_Q 0xfe00007f +#define MASK_FMUL_Q 0xfe00007f #define MATCH_FDIV_Q 0x1e000053 -#define MASK_FDIV_Q 0xfe00007f +#define MASK_FDIV_Q 0xfe00007f #define MATCH_FSGNJ_Q 0x26000053 -#define MASK_FSGNJ_Q 0xfe00707f +#define MASK_FSGNJ_Q 0xfe00707f #define MATCH_FSGNJN_Q 0x26001053 -#define MASK_FSGNJN_Q 0xfe00707f +#define MASK_FSGNJN_Q 0xfe00707f #define MATCH_FSGNJX_Q 0x26002053 -#define MASK_FSGNJX_Q 0xfe00707f +#define MASK_FSGNJX_Q 0xfe00707f #define MATCH_FMIN_Q 0x2e000053 -#define MASK_FMIN_Q 0xfe00707f +#define MASK_FMIN_Q 0xfe00707f #define MATCH_FMAX_Q 0x2e001053 -#define MASK_FMAX_Q 0xfe00707f +#define MASK_FMAX_Q 0xfe00707f #define MATCH_FCVT_S_Q 0x40300053 -#define MASK_FCVT_S_Q 0xfff0007f +#define MASK_FCVT_S_Q 0xfff0007f #define MATCH_FCVT_Q_S 0x46000053 -#define MASK_FCVT_Q_S 0xfff0007f +#define MASK_FCVT_Q_S 0xfff0007f #define MATCH_FCVT_D_Q 0x42300053 -#define MASK_FCVT_D_Q 0xfff0007f +#define MASK_FCVT_D_Q 0xfff0007f #define MATCH_FCVT_Q_D 0x46100053 -#define MASK_FCVT_Q_D 0xfff0007f +#define MASK_FCVT_Q_D 0xfff0007f #define MATCH_FSQRT_Q 0x5e000053 -#define MASK_FSQRT_Q 0xfff0007f +#define MASK_FSQRT_Q 0xfff0007f #define MATCH_FLE_Q 0xa6000053 -#define MASK_FLE_Q 0xfe00707f +#define MASK_FLE_Q 0xfe00707f #define MATCH_FLT_Q 0xa6001053 -#define MASK_FLT_Q 0xfe00707f +#define MASK_FLT_Q 0xfe00707f #define MATCH_FEQ_Q 0xa6002053 -#define MASK_FEQ_Q 0xfe00707f +#define MASK_FEQ_Q 0xfe00707f #define MATCH_FCVT_W_Q 0xc6000053 -#define MASK_FCVT_W_Q 0xfff0007f +#define MASK_FCVT_W_Q 0xfff0007f #define MATCH_FCVT_WU_Q 0xc6100053 -#define MASK_FCVT_WU_Q 0xfff0007f +#define MASK_FCVT_WU_Q 0xfff0007f #define MATCH_FCLASS_Q 0xe6001053 -#define MASK_FCLASS_Q 0xfff0707f +#define MASK_FCLASS_Q 0xfff0707f #define MATCH_FCVT_Q_W 0xd6000053 -#define MASK_FCVT_Q_W 0xfff0007f +#define MASK_FCVT_Q_W 0xfff0007f #define MATCH_FCVT_Q_WU 0xd6100053 -#define MASK_FCVT_Q_WU 0xfff0007f +#define MASK_FCVT_Q_WU 0xfff0007f #define MATCH_FLQ 0x4007 -#define MASK_FLQ 0x707f +#define MASK_FLQ 0x707f #define MATCH_FSQ 0x4027 -#define MASK_FSQ 0x707f +#define MASK_FSQ 0x707f #define MATCH_FMADD_Q 0x6000043 -#define MASK_FMADD_Q 0x600007f +#define MASK_FMADD_Q 0x600007f #define MATCH_FMSUB_Q 0x6000047 -#define MASK_FMSUB_Q 0x600007f +#define MASK_FMSUB_Q 0x600007f #define MATCH_FNMSUB_Q 0x600004b -#define MASK_FNMSUB_Q 0x600007f +#define MASK_FNMSUB_Q 0x600007f #define MATCH_FNMADD_Q 0x600004f -#define MASK_FNMADD_Q 0x600007f +#define MASK_FNMADD_Q 0x600007f #define MATCH_FCVT_L_Q 0xc6200053 -#define MASK_FCVT_L_Q 0xfff0007f +#define MASK_FCVT_L_Q 0xfff0007f #define MATCH_FCVT_LU_Q 0xc6300053 -#define MASK_FCVT_LU_Q 0xfff0007f +#define MASK_FCVT_LU_Q 0xfff0007f #define MATCH_FCVT_Q_L 0xd6200053 -#define MASK_FCVT_Q_L 0xfff0007f +#define MASK_FCVT_Q_L 0xfff0007f #define MATCH_FCVT_Q_LU 0xd6300053 -#define MASK_FCVT_Q_LU 0xfff0007f +#define MASK_FCVT_Q_LU 0xfff0007f #define MATCH_FMV_X_Q 0xe6000053 -#define MASK_FMV_X_Q 0xfff0707f +#define MASK_FMV_X_Q 0xfff0707f #define MATCH_FMV_Q_X 0xf6000053 -#define MASK_FMV_Q_X 0xfff0707f +#define MASK_FMV_Q_X 0xfff0707f #define MATCH_ECALL 0x73 -#define MASK_ECALL 0xffffffff +#define MASK_ECALL 0xffffffff #define MATCH_EBREAK 0x100073 -#define MASK_EBREAK 0xffffffff +#define MASK_EBREAK 0xffffffff #define MATCH_URET 0x200073 -#define MASK_URET 0xffffffff +#define MASK_URET 0xffffffff #define MATCH_SRET 0x10200073 -#define MASK_SRET 0xffffffff +#define MASK_SRET 0xffffffff #define MATCH_MRET 0x30200073 -#define MASK_MRET 0xffffffff +#define MASK_MRET 0xffffffff #define MATCH_DRET 0x7b200073 -#define MASK_DRET 0xffffffff +#define MASK_DRET 0xffffffff #define MATCH_SFENCE_VMA 0x12000073 -#define MASK_SFENCE_VMA 0xfe007fff +#define MASK_SFENCE_VMA 0xfe007fff #define MATCH_WFI 0x10500073 -#define MASK_WFI 0xffffffff +#define MASK_WFI 0xffffffff #define MATCH_CSRRW 0x1073 -#define MASK_CSRRW 0x707f +#define MASK_CSRRW 0x707f #define MATCH_CSRRS 0x2073 -#define MASK_CSRRS 0x707f +#define MASK_CSRRS 0x707f #define MATCH_CSRRC 0x3073 -#define MASK_CSRRC 0x707f +#define MASK_CSRRC 0x707f #define MATCH_CSRRWI 0x5073 -#define MASK_CSRRWI 0x707f +#define MASK_CSRRWI 0x707f #define MATCH_CSRRSI 0x6073 -#define MASK_CSRRSI 0x707f +#define MASK_CSRRSI 0x707f #define MATCH_CSRRCI 0x7073 -#define MASK_CSRRCI 0x707f +#define MASK_CSRRCI 0x707f #define MATCH_HFENCE_VVMA 0x22000073 -#define MASK_HFENCE_VVMA 0xfe007fff +#define MASK_HFENCE_VVMA 0xfe007fff #define MATCH_HFENCE_GVMA 0x62000073 -#define MASK_HFENCE_GVMA 0xfe007fff +#define MASK_HFENCE_GVMA 0xfe007fff #define MATCH_C_NOP 0x1 -#define MASK_C_NOP 0xffff +#define MASK_C_NOP 0xffff #define MATCH_C_ADDI16SP 0x6101 -#define MASK_C_ADDI16SP 0xef83 +#define MASK_C_ADDI16SP 0xef83 #define MATCH_C_JR 0x8002 -#define MASK_C_JR 0xf07f +#define MASK_C_JR 0xf07f #define MATCH_C_JALR 0x9002 -#define MASK_C_JALR 0xf07f +#define MASK_C_JALR 0xf07f #define MATCH_C_EBREAK 0x9002 -#define MASK_C_EBREAK 0xffff +#define MASK_C_EBREAK 0xffff #define MATCH_C_ADDI4SPN 0x0 -#define MASK_C_ADDI4SPN 0xe003 +#define MASK_C_ADDI4SPN 0xe003 #define MATCH_C_FLD 0x2000 -#define MASK_C_FLD 0xe003 +#define MASK_C_FLD 0xe003 #define MATCH_C_LW 0x4000 -#define MASK_C_LW 0xe003 +#define MASK_C_LW 0xe003 #define MATCH_C_FLW 0x6000 -#define MASK_C_FLW 0xe003 +#define MASK_C_FLW 0xe003 #define MATCH_C_FSD 0xa000 -#define MASK_C_FSD 0xe003 +#define MASK_C_FSD 0xe003 #define MATCH_C_SW 0xc000 -#define MASK_C_SW 0xe003 +#define MASK_C_SW 0xe003 #define MATCH_C_FSW 0xe000 -#define MASK_C_FSW 0xe003 +#define MASK_C_FSW 0xe003 #define MATCH_C_ADDI 0x1 -#define MASK_C_ADDI 0xe003 +#define MASK_C_ADDI 0xe003 #define MATCH_C_JAL 0x2001 -#define MASK_C_JAL 0xe003 +#define MASK_C_JAL 0xe003 #define MATCH_C_LI 0x4001 -#define MASK_C_LI 0xe003 +#define MASK_C_LI 0xe003 #define MATCH_C_LUI 0x6001 -#define MASK_C_LUI 0xe003 +#define MASK_C_LUI 0xe003 #define MATCH_C_SRLI 0x8001 -#define MASK_C_SRLI 0xec03 +#define MASK_C_SRLI 0xec03 #define MATCH_C_SRAI 0x8401 -#define MASK_C_SRAI 0xec03 +#define MASK_C_SRAI 0xec03 #define MATCH_C_ANDI 0x8801 -#define MASK_C_ANDI 0xec03 +#define MASK_C_ANDI 0xec03 #define MATCH_C_SUB 0x8c01 -#define MASK_C_SUB 0xfc63 +#define MASK_C_SUB 0xfc63 #define MATCH_C_XOR 0x8c21 -#define MASK_C_XOR 0xfc63 +#define MASK_C_XOR 0xfc63 #define MATCH_C_OR 0x8c41 -#define MASK_C_OR 0xfc63 +#define MASK_C_OR 0xfc63 #define MATCH_C_AND 0x8c61 -#define MASK_C_AND 0xfc63 +#define MASK_C_AND 0xfc63 #define MATCH_C_J 0xa001 -#define MASK_C_J 0xe003 +#define MASK_C_J 0xe003 #define MATCH_C_BEQZ 0xc001 -#define MASK_C_BEQZ 0xe003 +#define MASK_C_BEQZ 0xe003 #define MATCH_C_BNEZ 0xe001 -#define MASK_C_BNEZ 0xe003 +#define MASK_C_BNEZ 0xe003 #define MATCH_C_SLLI 0x2 -#define MASK_C_SLLI 0xe003 +#define MASK_C_SLLI 0xe003 #define MATCH_C_FLDSP 0x2002 -#define MASK_C_FLDSP 0xe003 +#define MASK_C_FLDSP 0xe003 #define MATCH_C_LWSP 0x4002 -#define MASK_C_LWSP 0xe003 +#define MASK_C_LWSP 0xe003 #define MATCH_C_FLWSP 0x6002 -#define MASK_C_FLWSP 0xe003 +#define MASK_C_FLWSP 0xe003 #define MATCH_C_MV 0x8002 -#define MASK_C_MV 0xf003 +#define MASK_C_MV 0xf003 #define MATCH_C_ADD 0x9002 -#define MASK_C_ADD 0xf003 +#define MASK_C_ADD 0xf003 #define MATCH_C_FSDSP 0xa002 -#define MASK_C_FSDSP 0xe003 +#define MASK_C_FSDSP 0xe003 #define MATCH_C_SWSP 0xc002 -#define MASK_C_SWSP 0xe003 +#define MASK_C_SWSP 0xe003 #define MATCH_C_FSWSP 0xe002 -#define MASK_C_FSWSP 0xe003 +#define MASK_C_FSWSP 0xe003 #define MATCH_C_SRLI_RV32 0x8001 -#define MASK_C_SRLI_RV32 0xfc03 +#define MASK_C_SRLI_RV32 0xfc03 #define MATCH_C_SRAI_RV32 0x8401 -#define MASK_C_SRAI_RV32 0xfc03 +#define MASK_C_SRAI_RV32 0xfc03 #define MATCH_C_SLLI_RV32 0x2 -#define MASK_C_SLLI_RV32 0xf003 +#define MASK_C_SLLI_RV32 0xf003 #define MATCH_C_LD 0x6000 -#define MASK_C_LD 0xe003 +#define MASK_C_LD 0xe003 #define MATCH_C_SD 0xe000 -#define MASK_C_SD 0xe003 +#define MASK_C_SD 0xe003 #define MATCH_C_SUBW 0x9c01 -#define MASK_C_SUBW 0xfc63 +#define MASK_C_SUBW 0xfc63 #define MATCH_C_ADDW 0x9c21 -#define MASK_C_ADDW 0xfc63 +#define MASK_C_ADDW 0xfc63 #define MATCH_C_ADDIW 0x2001 -#define MASK_C_ADDIW 0xe003 +#define MASK_C_ADDIW 0xe003 #define MATCH_C_LDSP 0x6002 -#define MASK_C_LDSP 0xe003 +#define MASK_C_LDSP 0xe003 #define MATCH_C_SDSP 0xe002 -#define MASK_C_SDSP 0xe003 +#define MASK_C_SDSP 0xe003 #define MATCH_C_LQ 0x2000 -#define MASK_C_LQ 0xe003 +#define MASK_C_LQ 0xe003 #define MATCH_C_SQ 0xa000 -#define MASK_C_SQ 0xe003 +#define MASK_C_SQ 0xe003 #define MATCH_C_LQSP 0x2002 -#define MASK_C_LQSP 0xe003 +#define MASK_C_LQSP 0xe003 #define MATCH_C_SQSP 0xa002 -#define MASK_C_SQSP 0xe003 +#define MASK_C_SQSP 0xe003 #define MATCH_CUSTOM0 0xb -#define MASK_CUSTOM0 0x707f +#define MASK_CUSTOM0 0x707f #define MATCH_CUSTOM0_RS1 0x200b -#define MASK_CUSTOM0_RS1 0x707f +#define MASK_CUSTOM0_RS1 0x707f #define MATCH_CUSTOM0_RS1_RS2 0x300b -#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MASK_CUSTOM0_RS1_RS2 0x707f #define MATCH_CUSTOM0_RD 0x400b -#define MASK_CUSTOM0_RD 0x707f +#define MASK_CUSTOM0_RD 0x707f #define MATCH_CUSTOM0_RD_RS1 0x600b -#define MASK_CUSTOM0_RD_RS1 0x707f +#define MASK_CUSTOM0_RD_RS1 0x707f #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b -#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f #define MATCH_CUSTOM1 0x2b -#define MASK_CUSTOM1 0x707f +#define MASK_CUSTOM1 0x707f #define MATCH_CUSTOM1_RS1 0x202b -#define MASK_CUSTOM1_RS1 0x707f +#define MASK_CUSTOM1_RS1 0x707f #define MATCH_CUSTOM1_RS1_RS2 0x302b -#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MASK_CUSTOM1_RS1_RS2 0x707f #define MATCH_CUSTOM1_RD 0x402b -#define MASK_CUSTOM1_RD 0x707f +#define MASK_CUSTOM1_RD 0x707f #define MATCH_CUSTOM1_RD_RS1 0x602b -#define MASK_CUSTOM1_RD_RS1 0x707f +#define MASK_CUSTOM1_RD_RS1 0x707f #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b -#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f #define MATCH_CUSTOM2 0x5b -#define MASK_CUSTOM2 0x707f +#define MASK_CUSTOM2 0x707f #define MATCH_CUSTOM2_RS1 0x205b -#define MASK_CUSTOM2_RS1 0x707f +#define MASK_CUSTOM2_RS1 0x707f #define MATCH_CUSTOM2_RS1_RS2 0x305b -#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MASK_CUSTOM2_RS1_RS2 0x707f #define MATCH_CUSTOM2_RD 0x405b -#define MASK_CUSTOM2_RD 0x707f +#define MASK_CUSTOM2_RD 0x707f #define MATCH_CUSTOM2_RD_RS1 0x605b -#define MASK_CUSTOM2_RD_RS1 0x707f +#define MASK_CUSTOM2_RD_RS1 0x707f #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b -#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f #define MATCH_CUSTOM3 0x7b -#define MASK_CUSTOM3 0x707f +#define MASK_CUSTOM3 0x707f #define MATCH_CUSTOM3_RS1 0x207b -#define MASK_CUSTOM3_RS1 0x707f +#define MASK_CUSTOM3_RS1 0x707f #define MATCH_CUSTOM3_RS1_RS2 0x307b -#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MASK_CUSTOM3_RS1_RS2 0x707f #define MATCH_CUSTOM3_RD 0x407b -#define MASK_CUSTOM3_RD 0x707f +#define MASK_CUSTOM3_RD 0x707f #define MATCH_CUSTOM3_RD_RS1 0x607b -#define MASK_CUSTOM3_RD_RS1 0x707f +#define MASK_CUSTOM3_RD_RS1 0x707f #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b -#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f #define MATCH_VSETVLI 0x7057 -#define MASK_VSETVLI 0x8000707f +#define MASK_VSETVLI 0x8000707f #define MATCH_VSETVL 0x80007057 -#define MASK_VSETVL 0xfe00707f +#define MASK_VSETVL 0xfe00707f #define MATCH_VLB_V 0x10000007 -#define MASK_VLB_V 0x1df0707f +#define MASK_VLB_V 0x1df0707f #define MATCH_VLH_V 0x10005007 -#define MASK_VLH_V 0x1df0707f +#define MASK_VLH_V 0x1df0707f #define MATCH_VLW_V 0x10006007 -#define MASK_VLW_V 0x1df0707f +#define MASK_VLW_V 0x1df0707f #define MATCH_VLE_V 0x7007 -#define MASK_VLE_V 0x1df0707f +#define MASK_VLE_V 0x1df0707f #define MATCH_VLBU_V 0x7 -#define MASK_VLBU_V 0x1df0707f +#define MASK_VLBU_V 0x1df0707f #define MATCH_VLHU_V 0x5007 -#define MASK_VLHU_V 0x1df0707f +#define MASK_VLHU_V 0x1df0707f #define MATCH_VLWU_V 0x6007 -#define MASK_VLWU_V 0x1df0707f +#define MASK_VLWU_V 0x1df0707f #define MATCH_VSB_V 0x27 -#define MASK_VSB_V 0x1df0707f +#define MASK_VSB_V 0x1df0707f #define MATCH_VSH_V 0x5027 -#define MASK_VSH_V 0x1df0707f +#define MASK_VSH_V 0x1df0707f #define MATCH_VSW_V 0x6027 -#define MASK_VSW_V 0x1df0707f +#define MASK_VSW_V 0x1df0707f #define MATCH_VSE_V 0x7027 -#define MASK_VSE_V 0x1df0707f +#define MASK_VSE_V 0x1df0707f #define MATCH_VLSB_V 0x18000007 -#define MASK_VLSB_V 0x1c00707f +#define MASK_VLSB_V 0x1c00707f #define MATCH_VLSH_V 0x18005007 -#define MASK_VLSH_V 0x1c00707f +#define MASK_VLSH_V 0x1c00707f #define MATCH_VLSW_V 0x18006007 -#define MASK_VLSW_V 0x1c00707f +#define MASK_VLSW_V 0x1c00707f #define MATCH_VLSE_V 0x8007007 -#define MASK_VLSE_V 0x1c00707f +#define MASK_VLSE_V 0x1c00707f #define MATCH_VLSBU_V 0x8000007 -#define MASK_VLSBU_V 0x1c00707f +#define MASK_VLSBU_V 0x1c00707f #define MATCH_VLSHU_V 0x8005007 -#define MASK_VLSHU_V 0x1c00707f +#define MASK_VLSHU_V 0x1c00707f #define MATCH_VLSWU_V 0x8006007 -#define MASK_VLSWU_V 0x1c00707f +#define MASK_VLSWU_V 0x1c00707f #define MATCH_VSSB_V 0x8000027 -#define MASK_VSSB_V 0x1c00707f +#define MASK_VSSB_V 0x1c00707f #define MATCH_VSSH_V 0x8005027 -#define MASK_VSSH_V 0x1c00707f +#define MASK_VSSH_V 0x1c00707f #define MATCH_VSSW_V 0x8006027 -#define MASK_VSSW_V 0x1c00707f +#define MASK_VSSW_V 0x1c00707f #define MATCH_VSSE_V 0x8007027 -#define MASK_VSSE_V 0x1c00707f +#define MASK_VSSE_V 0x1c00707f #define MATCH_VLXB_V 0x1c000007 -#define MASK_VLXB_V 0x1c00707f +#define MASK_VLXB_V 0x1c00707f #define MATCH_VLXH_V 0x1c005007 -#define MASK_VLXH_V 0x1c00707f +#define MASK_VLXH_V 0x1c00707f #define MATCH_VLXW_V 0x1c006007 -#define MASK_VLXW_V 0x1c00707f +#define MASK_VLXW_V 0x1c00707f #define MATCH_VLXE_V 0xc007007 -#define MASK_VLXE_V 0x1c00707f +#define MASK_VLXE_V 0x1c00707f #define MATCH_VLXBU_V 0xc000007 -#define MASK_VLXBU_V 0x1c00707f +#define MASK_VLXBU_V 0x1c00707f #define MATCH_VLXHU_V 0xc005007 -#define MASK_VLXHU_V 0x1c00707f +#define MASK_VLXHU_V 0x1c00707f #define MATCH_VLXWU_V 0xc006007 -#define MASK_VLXWU_V 0x1c00707f +#define MASK_VLXWU_V 0x1c00707f #define MATCH_VSXB_V 0xc000027 -#define MASK_VSXB_V 0x1c00707f +#define MASK_VSXB_V 0x1c00707f #define MATCH_VSXH_V 0xc005027 -#define MASK_VSXH_V 0x1c00707f +#define MASK_VSXH_V 0x1c00707f #define MATCH_VSXW_V 0xc006027 -#define MASK_VSXW_V 0x1c00707f +#define MASK_VSXW_V 0x1c00707f #define MATCH_VSXE_V 0xc007027 -#define MASK_VSXE_V 0x1c00707f +#define MASK_VSXE_V 0x1c00707f #define MATCH_VSUXB_V 0x1c000027 -#define MASK_VSUXB_V 0xfc00707f +#define MASK_VSUXB_V 0xfc00707f #define MATCH_VSUXH_V 0x1c005027 -#define MASK_VSUXH_V 0xfc00707f +#define MASK_VSUXH_V 0xfc00707f #define MATCH_VSUXW_V 0x1c006027 -#define MASK_VSUXW_V 0xfc00707f +#define MASK_VSUXW_V 0xfc00707f #define MATCH_VSUXE_V 0x1c007027 -#define MASK_VSUXE_V 0xfc00707f +#define MASK_VSUXE_V 0xfc00707f #define MATCH_VLBFF_V 0x11000007 -#define MASK_VLBFF_V 0x1df0707f +#define MASK_VLBFF_V 0x1df0707f #define MATCH_VLHFF_V 0x11005007 -#define MASK_VLHFF_V 0x1df0707f +#define MASK_VLHFF_V 0x1df0707f #define MATCH_VLWFF_V 0x11006007 -#define MASK_VLWFF_V 0x1df0707f +#define MASK_VLWFF_V 0x1df0707f #define MATCH_VLEFF_V 0x1007007 -#define MASK_VLEFF_V 0x1df0707f +#define MASK_VLEFF_V 0x1df0707f #define MATCH_VLBUFF_V 0x1000007 -#define MASK_VLBUFF_V 0x1df0707f +#define MASK_VLBUFF_V 0x1df0707f #define MATCH_VLHUFF_V 0x1005007 -#define MASK_VLHUFF_V 0x1df0707f +#define MASK_VLHUFF_V 0x1df0707f #define MATCH_VLWUFF_V 0x1006007 -#define MASK_VLWUFF_V 0x1df0707f +#define MASK_VLWUFF_V 0x1df0707f #define MATCH_VL1R_V 0x2807007 -#define MASK_VL1R_V 0xfff0707f +#define MASK_VL1R_V 0xfff0707f #define MATCH_VS1R_V 0x2807027 -#define MASK_VS1R_V 0xfff0707f +#define MASK_VS1R_V 0xfff0707f #define MATCH_VFADD_VF 0x5057 -#define MASK_VFADD_VF 0xfc00707f +#define MASK_VFADD_VF 0xfc00707f #define MATCH_VFSUB_VF 0x8005057 -#define MASK_VFSUB_VF 0xfc00707f +#define MASK_VFSUB_VF 0xfc00707f #define MATCH_VFMIN_VF 0x10005057 -#define MASK_VFMIN_VF 0xfc00707f +#define MASK_VFMIN_VF 0xfc00707f #define MATCH_VFMAX_VF 0x18005057 -#define MASK_VFMAX_VF 0xfc00707f +#define MASK_VFMAX_VF 0xfc00707f #define MATCH_VFSGNJ_VF 0x20005057 -#define MASK_VFSGNJ_VF 0xfc00707f +#define MASK_VFSGNJ_VF 0xfc00707f #define MATCH_VFSGNJN_VF 0x24005057 -#define MASK_VFSGNJN_VF 0xfc00707f +#define MASK_VFSGNJN_VF 0xfc00707f #define MATCH_VFSGNJX_VF 0x28005057 -#define MASK_VFSGNJX_VF 0xfc00707f +#define MASK_VFSGNJX_VF 0xfc00707f #define MATCH_VFSLIDE1UP_VF 0x38005057 -#define MASK_VFSLIDE1UP_VF 0xfc00707f +#define MASK_VFSLIDE1UP_VF 0xfc00707f #define MATCH_VFSLIDE1DOWN_VF 0x3c005057 -#define MASK_VFSLIDE1DOWN_VF 0xfc00707f +#define MASK_VFSLIDE1DOWN_VF 0xfc00707f #define MATCH_VFMV_S_F 0x42005057 -#define MASK_VFMV_S_F 0xfff0707f +#define MASK_VFMV_S_F 0xfff0707f #define MATCH_VFMERGE_VFM 0x5c005057 -#define MASK_VFMERGE_VFM 0xfe00707f +#define MASK_VFMERGE_VFM 0xfe00707f #define MATCH_VFMV_V_F 0x5e005057 -#define MASK_VFMV_V_F 0xfff0707f +#define MASK_VFMV_V_F 0xfff0707f #define MATCH_VMFEQ_VF 0x60005057 -#define MASK_VMFEQ_VF 0xfc00707f +#define MASK_VMFEQ_VF 0xfc00707f #define MATCH_VMFLE_VF 0x64005057 -#define MASK_VMFLE_VF 0xfc00707f +#define MASK_VMFLE_VF 0xfc00707f #define MATCH_VMFLT_VF 0x6c005057 -#define MASK_VMFLT_VF 0xfc00707f +#define MASK_VMFLT_VF 0xfc00707f #define MATCH_VMFNE_VF 0x70005057 -#define MASK_VMFNE_VF 0xfc00707f +#define MASK_VMFNE_VF 0xfc00707f #define MATCH_VMFGT_VF 0x74005057 -#define MASK_VMFGT_VF 0xfc00707f +#define MASK_VMFGT_VF 0xfc00707f #define MATCH_VMFGE_VF 0x7c005057 -#define MASK_VMFGE_VF 0xfc00707f +#define MASK_VMFGE_VF 0xfc00707f #define MATCH_VFDIV_VF 0x80005057 -#define MASK_VFDIV_VF 0xfc00707f +#define MASK_VFDIV_VF 0xfc00707f #define MATCH_VFRDIV_VF 0x84005057 -#define MASK_VFRDIV_VF 0xfc00707f +#define MASK_VFRDIV_VF 0xfc00707f #define MATCH_VFMUL_VF 0x90005057 -#define MASK_VFMUL_VF 0xfc00707f +#define MASK_VFMUL_VF 0xfc00707f #define MATCH_VFRSUB_VF 0x9c005057 -#define MASK_VFRSUB_VF 0xfc00707f +#define MASK_VFRSUB_VF 0xfc00707f #define MATCH_VFMADD_VF 0xa0005057 -#define MASK_VFMADD_VF 0xfc00707f +#define MASK_VFMADD_VF 0xfc00707f #define MATCH_VFNMADD_VF 0xa4005057 -#define MASK_VFNMADD_VF 0xfc00707f +#define MASK_VFNMADD_VF 0xfc00707f #define MATCH_VFMSUB_VF 0xa8005057 -#define MASK_VFMSUB_VF 0xfc00707f +#define MASK_VFMSUB_VF 0xfc00707f #define MATCH_VFNMSUB_VF 0xac005057 -#define MASK_VFNMSUB_VF 0xfc00707f +#define MASK_VFNMSUB_VF 0xfc00707f #define MATCH_VFMACC_VF 0xb0005057 -#define MASK_VFMACC_VF 0xfc00707f +#define MASK_VFMACC_VF 0xfc00707f #define MATCH_VFNMACC_VF 0xb4005057 -#define MASK_VFNMACC_VF 0xfc00707f +#define MASK_VFNMACC_VF 0xfc00707f #define MATCH_VFMSAC_VF 0xb8005057 -#define MASK_VFMSAC_VF 0xfc00707f +#define MASK_VFMSAC_VF 0xfc00707f #define MATCH_VFNMSAC_VF 0xbc005057 -#define MASK_VFNMSAC_VF 0xfc00707f +#define MASK_VFNMSAC_VF 0xfc00707f #define MATCH_VFWADD_VF 0xc0005057 -#define MASK_VFWADD_VF 0xfc00707f +#define MASK_VFWADD_VF 0xfc00707f #define MATCH_VFWSUB_VF 0xc8005057 -#define MASK_VFWSUB_VF 0xfc00707f +#define MASK_VFWSUB_VF 0xfc00707f #define MATCH_VFWADD_WF 0xd0005057 -#define MASK_VFWADD_WF 0xfc00707f +#define MASK_VFWADD_WF 0xfc00707f #define MATCH_VFWSUB_WF 0xd8005057 -#define MASK_VFWSUB_WF 0xfc00707f +#define MASK_VFWSUB_WF 0xfc00707f #define MATCH_VFWMUL_VF 0xe0005057 -#define MASK_VFWMUL_VF 0xfc00707f +#define MASK_VFWMUL_VF 0xfc00707f #define MATCH_VFWMACC_VF 0xf0005057 -#define MASK_VFWMACC_VF 0xfc00707f +#define MASK_VFWMACC_VF 0xfc00707f #define MATCH_VFWNMACC_VF 0xf4005057 -#define MASK_VFWNMACC_VF 0xfc00707f +#define MASK_VFWNMACC_VF 0xfc00707f #define MATCH_VFWMSAC_VF 0xf8005057 -#define MASK_VFWMSAC_VF 0xfc00707f +#define MASK_VFWMSAC_VF 0xfc00707f #define MATCH_VFWNMSAC_VF 0xfc005057 -#define MASK_VFWNMSAC_VF 0xfc00707f +#define MASK_VFWNMSAC_VF 0xfc00707f #define MATCH_VFADD_VV 0x1057 -#define MASK_VFADD_VV 0xfc00707f +#define MASK_VFADD_VV 0xfc00707f #define MATCH_VFREDSUM_VS 0x4001057 -#define MASK_VFREDSUM_VS 0xfc00707f +#define MASK_VFREDSUM_VS 0xfc00707f #define MATCH_VFSUB_VV 0x8001057 -#define MASK_VFSUB_VV 0xfc00707f +#define MASK_VFSUB_VV 0xfc00707f #define MATCH_VFREDOSUM_VS 0xc001057 -#define MASK_VFREDOSUM_VS 0xfc00707f +#define MASK_VFREDOSUM_VS 0xfc00707f #define MATCH_VFMIN_VV 0x10001057 -#define MASK_VFMIN_VV 0xfc00707f +#define MASK_VFMIN_VV 0xfc00707f #define MATCH_VFREDMIN_VS 0x14001057 -#define MASK_VFREDMIN_VS 0xfc00707f +#define MASK_VFREDMIN_VS 0xfc00707f #define MATCH_VFMAX_VV 0x18001057 -#define MASK_VFMAX_VV 0xfc00707f +#define MASK_VFMAX_VV 0xfc00707f #define MATCH_VFREDMAX_VS 0x1c001057 -#define MASK_VFREDMAX_VS 0xfc00707f +#define MASK_VFREDMAX_VS 0xfc00707f #define MATCH_VFSGNJ_VV 0x20001057 -#define MASK_VFSGNJ_VV 0xfc00707f +#define MASK_VFSGNJ_VV 0xfc00707f #define MATCH_VFSGNJN_VV 0x24001057 -#define MASK_VFSGNJN_VV 0xfc00707f +#define MASK_VFSGNJN_VV 0xfc00707f #define MATCH_VFSGNJX_VV 0x28001057 -#define MASK_VFSGNJX_VV 0xfc00707f +#define MASK_VFSGNJX_VV 0xfc00707f #define MATCH_VFMV_F_S 0x42001057 -#define MASK_VFMV_F_S 0xfe0ff07f +#define MASK_VFMV_F_S 0xfe0ff07f #define MATCH_VMFEQ_VV 0x60001057 -#define MASK_VMFEQ_VV 0xfc00707f +#define MASK_VMFEQ_VV 0xfc00707f #define MATCH_VMFLE_VV 0x64001057 -#define MASK_VMFLE_VV 0xfc00707f +#define MASK_VMFLE_VV 0xfc00707f #define MATCH_VMFLT_VV 0x6c001057 -#define MASK_VMFLT_VV 0xfc00707f +#define MASK_VMFLT_VV 0xfc00707f #define MATCH_VMFNE_VV 0x70001057 -#define MASK_VMFNE_VV 0xfc00707f +#define MASK_VMFNE_VV 0xfc00707f #define MATCH_VFDIV_VV 0x80001057 -#define MASK_VFDIV_VV 0xfc00707f +#define MASK_VFDIV_VV 0xfc00707f #define MATCH_VFMUL_VV 0x90001057 -#define MASK_VFMUL_VV 0xfc00707f +#define MASK_VFMUL_VV 0xfc00707f #define MATCH_VFMADD_VV 0xa0001057 -#define MASK_VFMADD_VV 0xfc00707f +#define MASK_VFMADD_VV 0xfc00707f #define MATCH_VFNMADD_VV 0xa4001057 -#define MASK_VFNMADD_VV 0xfc00707f +#define MASK_VFNMADD_VV 0xfc00707f #define MATCH_VFMSUB_VV 0xa8001057 -#define MASK_VFMSUB_VV 0xfc00707f +#define MASK_VFMSUB_VV 0xfc00707f #define MATCH_VFNMSUB_VV 0xac001057 -#define MASK_VFNMSUB_VV 0xfc00707f +#define MASK_VFNMSUB_VV 0xfc00707f #define MATCH_VFMACC_VV 0xb0001057 -#define MASK_VFMACC_VV 0xfc00707f +#define MASK_VFMACC_VV 0xfc00707f #define MATCH_VFNMACC_VV 0xb4001057 -#define MASK_VFNMACC_VV 0xfc00707f +#define MASK_VFNMACC_VV 0xfc00707f #define MATCH_VFMSAC_VV 0xb8001057 -#define MASK_VFMSAC_VV 0xfc00707f +#define MASK_VFMSAC_VV 0xfc00707f #define MATCH_VFNMSAC_VV 0xbc001057 -#define MASK_VFNMSAC_VV 0xfc00707f +#define MASK_VFNMSAC_VV 0xfc00707f #define MATCH_VFCVT_XU_F_V 0x88001057 -#define MASK_VFCVT_XU_F_V 0xfc0ff07f +#define MASK_VFCVT_XU_F_V 0xfc0ff07f #define MATCH_VFCVT_X_F_V 0x88009057 -#define MASK_VFCVT_X_F_V 0xfc0ff07f +#define MASK_VFCVT_X_F_V 0xfc0ff07f #define MATCH_VFCVT_F_XU_V 0x88011057 -#define MASK_VFCVT_F_XU_V 0xfc0ff07f +#define MASK_VFCVT_F_XU_V 0xfc0ff07f #define MATCH_VFCVT_F_X_V 0x88019057 -#define MASK_VFCVT_F_X_V 0xfc0ff07f +#define MASK_VFCVT_F_X_V 0xfc0ff07f #define MATCH_VFCVT_RTZ_XU_F_V 0x88031057 -#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f +#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f #define MATCH_VFCVT_RTZ_X_F_V 0x88039057 -#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f +#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f #define MATCH_VFWCVT_XU_F_V 0x88041057 -#define MASK_VFWCVT_XU_F_V 0xfc0ff07f +#define MASK_VFWCVT_XU_F_V 0xfc0ff07f #define MATCH_VFWCVT_X_F_V 0x88049057 -#define MASK_VFWCVT_X_F_V 0xfc0ff07f +#define MASK_VFWCVT_X_F_V 0xfc0ff07f #define MATCH_VFWCVT_F_XU_V 0x88051057 -#define MASK_VFWCVT_F_XU_V 0xfc0ff07f +#define MASK_VFWCVT_F_XU_V 0xfc0ff07f #define MATCH_VFWCVT_F_X_V 0x88059057 -#define MASK_VFWCVT_F_X_V 0xfc0ff07f +#define MASK_VFWCVT_F_X_V 0xfc0ff07f #define MATCH_VFWCVT_F_F_V 0x88061057 -#define MASK_VFWCVT_F_F_V 0xfc0ff07f +#define MASK_VFWCVT_F_F_V 0xfc0ff07f #define MATCH_VFWCVT_RTZ_XU_F_V 0x88071057 -#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f +#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f #define MATCH_VFWCVT_RTZ_X_F_V 0x88079057 -#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f +#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f #define MATCH_VFNCVT_XU_F_W 0x88081057 -#define MASK_VFNCVT_XU_F_W 0xfc0ff07f +#define MASK_VFNCVT_XU_F_W 0xfc0ff07f #define MATCH_VFNCVT_X_F_W 0x88089057 -#define MASK_VFNCVT_X_F_W 0xfc0ff07f +#define MASK_VFNCVT_X_F_W 0xfc0ff07f #define MATCH_VFNCVT_F_XU_W 0x88091057 -#define MASK_VFNCVT_F_XU_W 0xfc0ff07f +#define MASK_VFNCVT_F_XU_W 0xfc0ff07f #define MATCH_VFNCVT_F_X_W 0x88099057 -#define MASK_VFNCVT_F_X_W 0xfc0ff07f +#define MASK_VFNCVT_F_X_W 0xfc0ff07f #define MATCH_VFNCVT_F_F_W 0x880a1057 -#define MASK_VFNCVT_F_F_W 0xfc0ff07f +#define MASK_VFNCVT_F_F_W 0xfc0ff07f #define MATCH_VFNCVT_ROD_F_F_W 0x880a9057 -#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f +#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f #define MATCH_VFNCVT_RTZ_XU_F_W 0x880b1057 -#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f +#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f #define MATCH_VFNCVT_RTZ_X_F_W 0x880b9057 -#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f +#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f #define MATCH_VFSQRT_V 0x8c001057 -#define MASK_VFSQRT_V 0xfc0ff07f +#define MASK_VFSQRT_V 0xfc0ff07f #define MATCH_VFCLASS_V 0x8c081057 -#define MASK_VFCLASS_V 0xfc0ff07f +#define MASK_VFCLASS_V 0xfc0ff07f #define MATCH_VFWADD_VV 0xc0001057 -#define MASK_VFWADD_VV 0xfc00707f +#define MASK_VFWADD_VV 0xfc00707f #define MATCH_VFWREDSUM_VS 0xc4001057 -#define MASK_VFWREDSUM_VS 0xfc00707f +#define MASK_VFWREDSUM_VS 0xfc00707f #define MATCH_VFWSUB_VV 0xc8001057 -#define MASK_VFWSUB_VV 0xfc00707f +#define MASK_VFWSUB_VV 0xfc00707f #define MATCH_VFWREDOSUM_VS 0xcc001057 -#define MASK_VFWREDOSUM_VS 0xfc00707f +#define MASK_VFWREDOSUM_VS 0xfc00707f #define MATCH_VFWADD_WV 0xd0001057 -#define MASK_VFWADD_WV 0xfc00707f +#define MASK_VFWADD_WV 0xfc00707f #define MATCH_VFWSUB_WV 0xd8001057 -#define MASK_VFWSUB_WV 0xfc00707f +#define MASK_VFWSUB_WV 0xfc00707f #define MATCH_VFWMUL_VV 0xe0001057 -#define MASK_VFWMUL_VV 0xfc00707f +#define MASK_VFWMUL_VV 0xfc00707f #define MATCH_VFDOT_VV 0xe4001057 -#define MASK_VFDOT_VV 0xfc00707f +#define MASK_VFDOT_VV 0xfc00707f #define MATCH_VFWMACC_VV 0xf0001057 -#define MASK_VFWMACC_VV 0xfc00707f +#define MASK_VFWMACC_VV 0xfc00707f #define MATCH_VFWNMACC_VV 0xf4001057 -#define MASK_VFWNMACC_VV 0xfc00707f +#define MASK_VFWNMACC_VV 0xfc00707f #define MATCH_VFWMSAC_VV 0xf8001057 -#define MASK_VFWMSAC_VV 0xfc00707f +#define MASK_VFWMSAC_VV 0xfc00707f #define MATCH_VFWNMSAC_VV 0xfc001057 -#define MASK_VFWNMSAC_VV 0xfc00707f +#define MASK_VFWNMSAC_VV 0xfc00707f #define MATCH_VADD_VX 0x4057 -#define MASK_VADD_VX 0xfc00707f +#define MASK_VADD_VX 0xfc00707f #define MATCH_VSUB_VX 0x8004057 -#define MASK_VSUB_VX 0xfc00707f +#define MASK_VSUB_VX 0xfc00707f #define MATCH_VRSUB_VX 0xc004057 -#define MASK_VRSUB_VX 0xfc00707f +#define MASK_VRSUB_VX 0xfc00707f #define MATCH_VMINU_VX 0x10004057 -#define MASK_VMINU_VX 0xfc00707f +#define MASK_VMINU_VX 0xfc00707f #define MATCH_VMIN_VX 0x14004057 -#define MASK_VMIN_VX 0xfc00707f +#define MASK_VMIN_VX 0xfc00707f #define MATCH_VMAXU_VX 0x18004057 -#define MASK_VMAXU_VX 0xfc00707f +#define MASK_VMAXU_VX 0xfc00707f #define MATCH_VMAX_VX 0x1c004057 -#define MASK_VMAX_VX 0xfc00707f +#define MASK_VMAX_VX 0xfc00707f #define MATCH_VAND_VX 0x24004057 -#define MASK_VAND_VX 0xfc00707f +#define MASK_VAND_VX 0xfc00707f #define MATCH_VOR_VX 0x28004057 -#define MASK_VOR_VX 0xfc00707f +#define MASK_VOR_VX 0xfc00707f #define MATCH_VXOR_VX 0x2c004057 -#define MASK_VXOR_VX 0xfc00707f +#define MASK_VXOR_VX 0xfc00707f #define MATCH_VRGATHER_VX 0x30004057 -#define MASK_VRGATHER_VX 0xfc00707f +#define MASK_VRGATHER_VX 0xfc00707f #define MATCH_VSLIDEUP_VX 0x38004057 -#define MASK_VSLIDEUP_VX 0xfc00707f +#define MASK_VSLIDEUP_VX 0xfc00707f #define MATCH_VSLIDEDOWN_VX 0x3c004057 -#define MASK_VSLIDEDOWN_VX 0xfc00707f +#define MASK_VSLIDEDOWN_VX 0xfc00707f #define MATCH_VADC_VXM 0x40004057 -#define MASK_VADC_VXM 0xfe00707f +#define MASK_VADC_VXM 0xfe00707f #define MATCH_VMADC_VXM 0x44004057 -#define MASK_VMADC_VXM 0xfc00707f +#define MASK_VMADC_VXM 0xfc00707f #define MATCH_VSBC_VXM 0x48004057 -#define MASK_VSBC_VXM 0xfe00707f +#define MASK_VSBC_VXM 0xfe00707f #define MATCH_VMSBC_VXM 0x4c004057 -#define MASK_VMSBC_VXM 0xfc00707f +#define MASK_VMSBC_VXM 0xfc00707f #define MATCH_VMERGE_VXM 0x5c004057 -#define MASK_VMERGE_VXM 0xfe00707f +#define MASK_VMERGE_VXM 0xfe00707f #define MATCH_VMV_V_X 0x5e004057 -#define MASK_VMV_V_X 0xfff0707f +#define MASK_VMV_V_X 0xfff0707f #define MATCH_VMSEQ_VX 0x60004057 -#define MASK_VMSEQ_VX 0xfc00707f +#define MASK_VMSEQ_VX 0xfc00707f #define MATCH_VMSNE_VX 0x64004057 -#define MASK_VMSNE_VX 0xfc00707f +#define MASK_VMSNE_VX 0xfc00707f #define MATCH_VMSLTU_VX 0x68004057 -#define MASK_VMSLTU_VX 0xfc00707f +#define MASK_VMSLTU_VX 0xfc00707f #define MATCH_VMSLT_VX 0x6c004057 -#define MASK_VMSLT_VX 0xfc00707f +#define MASK_VMSLT_VX 0xfc00707f #define MATCH_VMSLEU_VX 0x70004057 -#define MASK_VMSLEU_VX 0xfc00707f +#define MASK_VMSLEU_VX 0xfc00707f #define MATCH_VMSLE_VX 0x74004057 -#define MASK_VMSLE_VX 0xfc00707f +#define MASK_VMSLE_VX 0xfc00707f #define MATCH_VMSGTU_VX 0x78004057 -#define MASK_VMSGTU_VX 0xfc00707f +#define MASK_VMSGTU_VX 0xfc00707f #define MATCH_VMSGT_VX 0x7c004057 -#define MASK_VMSGT_VX 0xfc00707f +#define MASK_VMSGT_VX 0xfc00707f #define MATCH_VSADDU_VX 0x80004057 -#define MASK_VSADDU_VX 0xfc00707f +#define MASK_VSADDU_VX 0xfc00707f #define MATCH_VSADD_VX 0x84004057 -#define MASK_VSADD_VX 0xfc00707f +#define MASK_VSADD_VX 0xfc00707f #define MATCH_VSSUBU_VX 0x88004057 -#define MASK_VSSUBU_VX 0xfc00707f +#define MASK_VSSUBU_VX 0xfc00707f #define MATCH_VSSUB_VX 0x8c004057 -#define MASK_VSSUB_VX 0xfc00707f +#define MASK_VSSUB_VX 0xfc00707f #define MATCH_VSLL_VX 0x94004057 -#define MASK_VSLL_VX 0xfc00707f +#define MASK_VSLL_VX 0xfc00707f #define MATCH_VSMUL_VX 0x9c004057 -#define MASK_VSMUL_VX 0xfc00707f +#define MASK_VSMUL_VX 0xfc00707f #define MATCH_VSRL_VX 0xa0004057 -#define MASK_VSRL_VX 0xfc00707f +#define MASK_VSRL_VX 0xfc00707f #define MATCH_VSRA_VX 0xa4004057 -#define MASK_VSRA_VX 0xfc00707f +#define MASK_VSRA_VX 0xfc00707f #define MATCH_VSSRL_VX 0xa8004057 -#define MASK_VSSRL_VX 0xfc00707f +#define MASK_VSSRL_VX 0xfc00707f #define MATCH_VSSRA_VX 0xac004057 -#define MASK_VSSRA_VX 0xfc00707f +#define MASK_VSSRA_VX 0xfc00707f #define MATCH_VNSRL_WX 0xb0004057 -#define MASK_VNSRL_WX 0xfc00707f +#define MASK_VNSRL_WX 0xfc00707f #define MATCH_VNSRA_WX 0xb4004057 -#define MASK_VNSRA_WX 0xfc00707f +#define MASK_VNSRA_WX 0xfc00707f #define MATCH_VNCLIPU_WX 0xb8004057 -#define MASK_VNCLIPU_WX 0xfc00707f +#define MASK_VNCLIPU_WX 0xfc00707f #define MATCH_VNCLIP_WX 0xbc004057 -#define MASK_VNCLIP_WX 0xfc00707f +#define MASK_VNCLIP_WX 0xfc00707f #define MATCH_VQMACCU_VX 0xf0004057 -#define MASK_VQMACCU_VX 0xfc00707f +#define MASK_VQMACCU_VX 0xfc00707f #define MATCH_VQMACC_VX 0xf4004057 -#define MASK_VQMACC_VX 0xfc00707f +#define MASK_VQMACC_VX 0xfc00707f #define MATCH_VQMACCUS_VX 0xf8004057 -#define MASK_VQMACCUS_VX 0xfc00707f +#define MASK_VQMACCUS_VX 0xfc00707f #define MATCH_VQMACCSU_VX 0xfc004057 -#define MASK_VQMACCSU_VX 0xfc00707f +#define MASK_VQMACCSU_VX 0xfc00707f #define MATCH_VADD_VV 0x57 -#define MASK_VADD_VV 0xfc00707f +#define MASK_VADD_VV 0xfc00707f #define MATCH_VSUB_VV 0x8000057 -#define MASK_VSUB_VV 0xfc00707f +#define MASK_VSUB_VV 0xfc00707f #define MATCH_VMINU_VV 0x10000057 -#define MASK_VMINU_VV 0xfc00707f +#define MASK_VMINU_VV 0xfc00707f #define MATCH_VMIN_VV 0x14000057 -#define MASK_VMIN_VV 0xfc00707f +#define MASK_VMIN_VV 0xfc00707f #define MATCH_VMAXU_VV 0x18000057 -#define MASK_VMAXU_VV 0xfc00707f +#define MASK_VMAXU_VV 0xfc00707f #define MATCH_VMAX_VV 0x1c000057 -#define MASK_VMAX_VV 0xfc00707f +#define MASK_VMAX_VV 0xfc00707f #define MATCH_VAND_VV 0x24000057 -#define MASK_VAND_VV 0xfc00707f +#define MASK_VAND_VV 0xfc00707f #define MATCH_VOR_VV 0x28000057 -#define MASK_VOR_VV 0xfc00707f +#define MASK_VOR_VV 0xfc00707f #define MATCH_VXOR_VV 0x2c000057 -#define MASK_VXOR_VV 0xfc00707f +#define MASK_VXOR_VV 0xfc00707f #define MATCH_VRGATHER_VV 0x30000057 -#define MASK_VRGATHER_VV 0xfc00707f +#define MASK_VRGATHER_VV 0xfc00707f #define MATCH_VADC_VVM 0x40000057 -#define MASK_VADC_VVM 0xfe00707f +#define MASK_VADC_VVM 0xfe00707f #define MATCH_VMADC_VVM 0x44000057 -#define MASK_VMADC_VVM 0xfc00707f +#define MASK_VMADC_VVM 0xfc00707f #define MATCH_VSBC_VVM 0x48000057 -#define MASK_VSBC_VVM 0xfe00707f +#define MASK_VSBC_VVM 0xfe00707f #define MATCH_VMSBC_VVM 0x4c000057 -#define MASK_VMSBC_VVM 0xfc00707f +#define MASK_VMSBC_VVM 0xfc00707f #define MATCH_VMERGE_VVM 0x5c000057 -#define MASK_VMERGE_VVM 0xfe00707f +#define MASK_VMERGE_VVM 0xfe00707f #define MATCH_VMV_V_V 0x5e000057 -#define MASK_VMV_V_V 0xfff0707f +#define MASK_VMV_V_V 0xfff0707f #define MATCH_VMSEQ_VV 0x60000057 -#define MASK_VMSEQ_VV 0xfc00707f +#define MASK_VMSEQ_VV 0xfc00707f #define MATCH_VMSNE_VV 0x64000057 -#define MASK_VMSNE_VV 0xfc00707f +#define MASK_VMSNE_VV 0xfc00707f #define MATCH_VMSLTU_VV 0x68000057 -#define MASK_VMSLTU_VV 0xfc00707f +#define MASK_VMSLTU_VV 0xfc00707f #define MATCH_VMSLT_VV 0x6c000057 -#define MASK_VMSLT_VV 0xfc00707f +#define MASK_VMSLT_VV 0xfc00707f #define MATCH_VMSLEU_VV 0x70000057 -#define MASK_VMSLEU_VV 0xfc00707f +#define MASK_VMSLEU_VV 0xfc00707f #define MATCH_VMSLE_VV 0x74000057 -#define MASK_VMSLE_VV 0xfc00707f +#define MASK_VMSLE_VV 0xfc00707f #define MATCH_VSADDU_VV 0x80000057 -#define MASK_VSADDU_VV 0xfc00707f +#define MASK_VSADDU_VV 0xfc00707f #define MATCH_VSADD_VV 0x84000057 -#define MASK_VSADD_VV 0xfc00707f +#define MASK_VSADD_VV 0xfc00707f #define MATCH_VSSUBU_VV 0x88000057 -#define MASK_VSSUBU_VV 0xfc00707f +#define MASK_VSSUBU_VV 0xfc00707f #define MATCH_VSSUB_VV 0x8c000057 -#define MASK_VSSUB_VV 0xfc00707f +#define MASK_VSSUB_VV 0xfc00707f #define MATCH_VSLL_VV 0x94000057 -#define MASK_VSLL_VV 0xfc00707f +#define MASK_VSLL_VV 0xfc00707f #define MATCH_VSMUL_VV 0x9c000057 -#define MASK_VSMUL_VV 0xfc00707f +#define MASK_VSMUL_VV 0xfc00707f #define MATCH_VSRL_VV 0xa0000057 -#define MASK_VSRL_VV 0xfc00707f +#define MASK_VSRL_VV 0xfc00707f #define MATCH_VSRA_VV 0xa4000057 -#define MASK_VSRA_VV 0xfc00707f +#define MASK_VSRA_VV 0xfc00707f #define MATCH_VSSRL_VV 0xa8000057 -#define MASK_VSSRL_VV 0xfc00707f +#define MASK_VSSRL_VV 0xfc00707f #define MATCH_VSSRA_VV 0xac000057 -#define MASK_VSSRA_VV 0xfc00707f +#define MASK_VSSRA_VV 0xfc00707f #define MATCH_VNSRL_WV 0xb0000057 -#define MASK_VNSRL_WV 0xfc00707f +#define MASK_VNSRL_WV 0xfc00707f #define MATCH_VNSRA_WV 0xb4000057 -#define MASK_VNSRA_WV 0xfc00707f +#define MASK_VNSRA_WV 0xfc00707f #define MATCH_VNCLIPU_WV 0xb8000057 -#define MASK_VNCLIPU_WV 0xfc00707f +#define MASK_VNCLIPU_WV 0xfc00707f #define MATCH_VNCLIP_WV 0xbc000057 -#define MASK_VNCLIP_WV 0xfc00707f +#define MASK_VNCLIP_WV 0xfc00707f #define MATCH_VWREDSUMU_VS 0xc0000057 -#define MASK_VWREDSUMU_VS 0xfc00707f +#define MASK_VWREDSUMU_VS 0xfc00707f #define MATCH_VWREDSUM_VS 0xc4000057 -#define MASK_VWREDSUM_VS 0xfc00707f +#define MASK_VWREDSUM_VS 0xfc00707f #define MATCH_VDOTU_VV 0xe0000057 -#define MASK_VDOTU_VV 0xfc00707f +#define MASK_VDOTU_VV 0xfc00707f #define MATCH_VDOT_VV 0xe4000057 -#define MASK_VDOT_VV 0xfc00707f +#define MASK_VDOT_VV 0xfc00707f #define MATCH_VQMACCU_VV 0xf0000057 -#define MASK_VQMACCU_VV 0xfc00707f +#define MASK_VQMACCU_VV 0xfc00707f #define MATCH_VQMACC_VV 0xf4000057 -#define MASK_VQMACC_VV 0xfc00707f +#define MASK_VQMACC_VV 0xfc00707f #define MATCH_VQMACCSU_VV 0xfc000057 -#define MASK_VQMACCSU_VV 0xfc00707f +#define MASK_VQMACCSU_VV 0xfc00707f #define MATCH_VADD_VI 0x3057 -#define MASK_VADD_VI 0xfc00707f +#define MASK_VADD_VI 0xfc00707f #define MATCH_VRSUB_VI 0xc003057 -#define MASK_VRSUB_VI 0xfc00707f +#define MASK_VRSUB_VI 0xfc00707f #define MATCH_VAND_VI 0x24003057 -#define MASK_VAND_VI 0xfc00707f +#define MASK_VAND_VI 0xfc00707f #define MATCH_VOR_VI 0x28003057 -#define MASK_VOR_VI 0xfc00707f +#define MASK_VOR_VI 0xfc00707f #define MATCH_VXOR_VI 0x2c003057 -#define MASK_VXOR_VI 0xfc00707f +#define MASK_VXOR_VI 0xfc00707f #define MATCH_VRGATHER_VI 0x30003057 -#define MASK_VRGATHER_VI 0xfc00707f +#define MASK_VRGATHER_VI 0xfc00707f #define MATCH_VSLIDEUP_VI 0x38003057 -#define MASK_VSLIDEUP_VI 0xfc00707f +#define MASK_VSLIDEUP_VI 0xfc00707f #define MATCH_VSLIDEDOWN_VI 0x3c003057 -#define MASK_VSLIDEDOWN_VI 0xfc00707f +#define MASK_VSLIDEDOWN_VI 0xfc00707f #define MATCH_VADC_VIM 0x40003057 -#define MASK_VADC_VIM 0xfe00707f +#define MASK_VADC_VIM 0xfe00707f #define MATCH_VMADC_VIM 0x44003057 -#define MASK_VMADC_VIM 0xfc00707f +#define MASK_VMADC_VIM 0xfc00707f #define MATCH_VMERGE_VIM 0x5c003057 -#define MASK_VMERGE_VIM 0xfe00707f +#define MASK_VMERGE_VIM 0xfe00707f #define MATCH_VMV_V_I 0x5e003057 -#define MASK_VMV_V_I 0xfff0707f +#define MASK_VMV_V_I 0xfff0707f #define MATCH_VMSEQ_VI 0x60003057 -#define MASK_VMSEQ_VI 0xfc00707f +#define MASK_VMSEQ_VI 0xfc00707f #define MATCH_VMSNE_VI 0x64003057 -#define MASK_VMSNE_VI 0xfc00707f +#define MASK_VMSNE_VI 0xfc00707f #define MATCH_VMSLEU_VI 0x70003057 -#define MASK_VMSLEU_VI 0xfc00707f +#define MASK_VMSLEU_VI 0xfc00707f #define MATCH_VMSLE_VI 0x74003057 -#define MASK_VMSLE_VI 0xfc00707f +#define MASK_VMSLE_VI 0xfc00707f #define MATCH_VMSGTU_VI 0x78003057 -#define MASK_VMSGTU_VI 0xfc00707f +#define MASK_VMSGTU_VI 0xfc00707f #define MATCH_VMSGT_VI 0x7c003057 -#define MASK_VMSGT_VI 0xfc00707f +#define MASK_VMSGT_VI 0xfc00707f #define MATCH_VSADDU_VI 0x80003057 -#define MASK_VSADDU_VI 0xfc00707f +#define MASK_VSADDU_VI 0xfc00707f #define MATCH_VSADD_VI 0x84003057 -#define MASK_VSADD_VI 0xfc00707f +#define MASK_VSADD_VI 0xfc00707f #define MATCH_VSLL_VI 0x94003057 -#define MASK_VSLL_VI 0xfc00707f +#define MASK_VSLL_VI 0xfc00707f #define MATCH_VMV1R_V 0x9e003057 -#define MASK_VMV1R_V 0xfe0ff07f +#define MASK_VMV1R_V 0xfe0ff07f #define MATCH_VMV2R_V 0x9e00b057 -#define MASK_VMV2R_V 0xfe0ff07f +#define MASK_VMV2R_V 0xfe0ff07f #define MATCH_VMV4R_V 0x9e01b057 -#define MASK_VMV4R_V 0xfe0ff07f +#define MASK_VMV4R_V 0xfe0ff07f #define MATCH_VMV8R_V 0x9e03b057 -#define MASK_VMV8R_V 0xfe0ff07f +#define MASK_VMV8R_V 0xfe0ff07f #define MATCH_VSRL_VI 0xa0003057 -#define MASK_VSRL_VI 0xfc00707f +#define MASK_VSRL_VI 0xfc00707f #define MATCH_VSRA_VI 0xa4003057 -#define MASK_VSRA_VI 0xfc00707f +#define MASK_VSRA_VI 0xfc00707f #define MATCH_VSSRL_VI 0xa8003057 -#define MASK_VSSRL_VI 0xfc00707f +#define MASK_VSSRL_VI 0xfc00707f #define MATCH_VSSRA_VI 0xac003057 -#define MASK_VSSRA_VI 0xfc00707f +#define MASK_VSSRA_VI 0xfc00707f #define MATCH_VNSRL_WI 0xb0003057 -#define MASK_VNSRL_WI 0xfc00707f +#define MASK_VNSRL_WI 0xfc00707f #define MATCH_VNSRA_WI 0xb4003057 -#define MASK_VNSRA_WI 0xfc00707f +#define MASK_VNSRA_WI 0xfc00707f #define MATCH_VNCLIPU_WI 0xb8003057 -#define MASK_VNCLIPU_WI 0xfc00707f +#define MASK_VNCLIPU_WI 0xfc00707f #define MATCH_VNCLIP_WI 0xbc003057 -#define MASK_VNCLIP_WI 0xfc00707f +#define MASK_VNCLIP_WI 0xfc00707f #define MATCH_VREDSUM_VS 0x2057 -#define MASK_VREDSUM_VS 0xfc00707f +#define MASK_VREDSUM_VS 0xfc00707f #define MATCH_VREDAND_VS 0x4002057 -#define MASK_VREDAND_VS 0xfc00707f +#define MASK_VREDAND_VS 0xfc00707f #define MATCH_VREDOR_VS 0x8002057 -#define MASK_VREDOR_VS 0xfc00707f +#define MASK_VREDOR_VS 0xfc00707f #define MATCH_VREDXOR_VS 0xc002057 -#define MASK_VREDXOR_VS 0xfc00707f +#define MASK_VREDXOR_VS 0xfc00707f #define MATCH_VREDMINU_VS 0x10002057 -#define MASK_VREDMINU_VS 0xfc00707f +#define MASK_VREDMINU_VS 0xfc00707f #define MATCH_VREDMIN_VS 0x14002057 -#define MASK_VREDMIN_VS 0xfc00707f +#define MASK_VREDMIN_VS 0xfc00707f #define MATCH_VREDMAXU_VS 0x18002057 -#define MASK_VREDMAXU_VS 0xfc00707f +#define MASK_VREDMAXU_VS 0xfc00707f #define MATCH_VREDMAX_VS 0x1c002057 -#define MASK_VREDMAX_VS 0xfc00707f +#define MASK_VREDMAX_VS 0xfc00707f #define MATCH_VAADDU_VV 0x20002057 -#define MASK_VAADDU_VV 0xfc00707f +#define MASK_VAADDU_VV 0xfc00707f #define MATCH_VAADD_VV 0x24002057 -#define MASK_VAADD_VV 0xfc00707f +#define MASK_VAADD_VV 0xfc00707f #define MATCH_VASUBU_VV 0x28002057 -#define MASK_VASUBU_VV 0xfc00707f +#define MASK_VASUBU_VV 0xfc00707f #define MATCH_VASUB_VV 0x2c002057 -#define MASK_VASUB_VV 0xfc00707f +#define MASK_VASUB_VV 0xfc00707f #define MATCH_VMV_X_S 0x42002057 -#define MASK_VMV_X_S 0xfe0ff07f +#define MASK_VMV_X_S 0xfe0ff07f #define MATCH_VCOMPRESS_VM 0x5e002057 -#define MASK_VCOMPRESS_VM 0xfe00707f +#define MASK_VCOMPRESS_VM 0xfe00707f #define MATCH_VMANDNOT_MM 0x60002057 -#define MASK_VMANDNOT_MM 0xfc00707f +#define MASK_VMANDNOT_MM 0xfc00707f #define MATCH_VMAND_MM 0x64002057 -#define MASK_VMAND_MM 0xfc00707f +#define MASK_VMAND_MM 0xfc00707f #define MATCH_VMOR_MM 0x68002057 -#define MASK_VMOR_MM 0xfc00707f +#define MASK_VMOR_MM 0xfc00707f #define MATCH_VMXOR_MM 0x6c002057 -#define MASK_VMXOR_MM 0xfc00707f +#define MASK_VMXOR_MM 0xfc00707f #define MATCH_VMORNOT_MM 0x70002057 -#define MASK_VMORNOT_MM 0xfc00707f +#define MASK_VMORNOT_MM 0xfc00707f #define MATCH_VMNAND_MM 0x74002057 -#define MASK_VMNAND_MM 0xfc00707f +#define MASK_VMNAND_MM 0xfc00707f #define MATCH_VMNOR_MM 0x78002057 -#define MASK_VMNOR_MM 0xfc00707f +#define MASK_VMNOR_MM 0xfc00707f #define MATCH_VMXNOR_MM 0x7c002057 -#define MASK_VMXNOR_MM 0xfc00707f +#define MASK_VMXNOR_MM 0xfc00707f #define MATCH_VMSBF_M 0x5000a057 -#define MASK_VMSBF_M 0xfc0ff07f +#define MASK_VMSBF_M 0xfc0ff07f #define MATCH_VMSOF_M 0x50012057 -#define MASK_VMSOF_M 0xfc0ff07f +#define MASK_VMSOF_M 0xfc0ff07f #define MATCH_VMSIF_M 0x5001a057 -#define MASK_VMSIF_M 0xfc0ff07f +#define MASK_VMSIF_M 0xfc0ff07f #define MATCH_VIOTA_M 0x50082057 -#define MASK_VIOTA_M 0xfc0ff07f +#define MASK_VIOTA_M 0xfc0ff07f #define MATCH_VID_V 0x5008a057 -#define MASK_VID_V 0xfdfff07f +#define MASK_VID_V 0xfdfff07f #define MATCH_VPOPC_M 0x40082057 -#define MASK_VPOPC_M 0xfc0ff07f +#define MASK_VPOPC_M 0xfc0ff07f #define MATCH_VFIRST_M 0x4008a057 -#define MASK_VFIRST_M 0xfc0ff07f +#define MASK_VFIRST_M 0xfc0ff07f #define MATCH_VDIVU_VV 0x80002057 -#define MASK_VDIVU_VV 0xfc00707f +#define MASK_VDIVU_VV 0xfc00707f #define MATCH_VDIV_VV 0x84002057 -#define MASK_VDIV_VV 0xfc00707f +#define MASK_VDIV_VV 0xfc00707f #define MATCH_VREMU_VV 0x88002057 -#define MASK_VREMU_VV 0xfc00707f +#define MASK_VREMU_VV 0xfc00707f #define MATCH_VREM_VV 0x8c002057 -#define MASK_VREM_VV 0xfc00707f +#define MASK_VREM_VV 0xfc00707f #define MATCH_VMULHU_VV 0x90002057 -#define MASK_VMULHU_VV 0xfc00707f +#define MASK_VMULHU_VV 0xfc00707f #define MATCH_VMUL_VV 0x94002057 -#define MASK_VMUL_VV 0xfc00707f +#define MASK_VMUL_VV 0xfc00707f #define MATCH_VMULHSU_VV 0x98002057 -#define MASK_VMULHSU_VV 0xfc00707f +#define MASK_VMULHSU_VV 0xfc00707f #define MATCH_VMULH_VV 0x9c002057 -#define MASK_VMULH_VV 0xfc00707f +#define MASK_VMULH_VV 0xfc00707f #define MATCH_VMADD_VV 0xa4002057 -#define MASK_VMADD_VV 0xfc00707f +#define MASK_VMADD_VV 0xfc00707f #define MATCH_VNMSUB_VV 0xac002057 -#define MASK_VNMSUB_VV 0xfc00707f +#define MASK_VNMSUB_VV 0xfc00707f #define MATCH_VMACC_VV 0xb4002057 -#define MASK_VMACC_VV 0xfc00707f +#define MASK_VMACC_VV 0xfc00707f #define MATCH_VNMSAC_VV 0xbc002057 -#define MASK_VNMSAC_VV 0xfc00707f +#define MASK_VNMSAC_VV 0xfc00707f #define MATCH_VWADDU_VV 0xc0002057 -#define MASK_VWADDU_VV 0xfc00707f +#define MASK_VWADDU_VV 0xfc00707f #define MATCH_VWADD_VV 0xc4002057 -#define MASK_VWADD_VV 0xfc00707f +#define MASK_VWADD_VV 0xfc00707f #define MATCH_VWSUBU_VV 0xc8002057 -#define MASK_VWSUBU_VV 0xfc00707f +#define MASK_VWSUBU_VV 0xfc00707f #define MATCH_VWSUB_VV 0xcc002057 -#define MASK_VWSUB_VV 0xfc00707f +#define MASK_VWSUB_VV 0xfc00707f #define MATCH_VWADDU_WV 0xd0002057 -#define MASK_VWADDU_WV 0xfc00707f +#define MASK_VWADDU_WV 0xfc00707f #define MATCH_VWADD_WV 0xd4002057 -#define MASK_VWADD_WV 0xfc00707f +#define MASK_VWADD_WV 0xfc00707f #define MATCH_VWSUBU_WV 0xd8002057 -#define MASK_VWSUBU_WV 0xfc00707f +#define MASK_VWSUBU_WV 0xfc00707f #define MATCH_VWSUB_WV 0xdc002057 -#define MASK_VWSUB_WV 0xfc00707f +#define MASK_VWSUB_WV 0xfc00707f #define MATCH_VWMULU_VV 0xe0002057 -#define MASK_VWMULU_VV 0xfc00707f +#define MASK_VWMULU_VV 0xfc00707f #define MATCH_VWMULSU_VV 0xe8002057 -#define MASK_VWMULSU_VV 0xfc00707f +#define MASK_VWMULSU_VV 0xfc00707f #define MATCH_VWMUL_VV 0xec002057 -#define MASK_VWMUL_VV 0xfc00707f +#define MASK_VWMUL_VV 0xfc00707f #define MATCH_VWMACCU_VV 0xf0002057 -#define MASK_VWMACCU_VV 0xfc00707f +#define MASK_VWMACCU_VV 0xfc00707f #define MATCH_VWMACC_VV 0xf4002057 -#define MASK_VWMACC_VV 0xfc00707f +#define MASK_VWMACC_VV 0xfc00707f #define MATCH_VWMACCSU_VV 0xfc002057 -#define MASK_VWMACCSU_VV 0xfc00707f +#define MASK_VWMACCSU_VV 0xfc00707f #define MATCH_VAADDU_VX 0x20006057 -#define MASK_VAADDU_VX 0xfc00707f +#define MASK_VAADDU_VX 0xfc00707f #define MATCH_VAADD_VX 0x24006057 -#define MASK_VAADD_VX 0xfc00707f +#define MASK_VAADD_VX 0xfc00707f #define MATCH_VASUBU_VX 0x28006057 -#define MASK_VASUBU_VX 0xfc00707f +#define MASK_VASUBU_VX 0xfc00707f #define MATCH_VASUB_VX 0x2c006057 -#define MASK_VASUB_VX 0xfc00707f +#define MASK_VASUB_VX 0xfc00707f #define MATCH_VMV_S_X 0x42006057 -#define MASK_VMV_S_X 0xfff0707f +#define MASK_VMV_S_X 0xfff0707f #define MATCH_VSLIDE1UP_VX 0x38006057 -#define MASK_VSLIDE1UP_VX 0xfc00707f +#define MASK_VSLIDE1UP_VX 0xfc00707f #define MATCH_VSLIDE1DOWN_VX 0x3c006057 -#define MASK_VSLIDE1DOWN_VX 0xfc00707f +#define MASK_VSLIDE1DOWN_VX 0xfc00707f #define MATCH_VDIVU_VX 0x80006057 -#define MASK_VDIVU_VX 0xfc00707f +#define MASK_VDIVU_VX 0xfc00707f #define MATCH_VDIV_VX 0x84006057 -#define MASK_VDIV_VX 0xfc00707f +#define MASK_VDIV_VX 0xfc00707f #define MATCH_VREMU_VX 0x88006057 -#define MASK_VREMU_VX 0xfc00707f +#define MASK_VREMU_VX 0xfc00707f #define MATCH_VREM_VX 0x8c006057 -#define MASK_VREM_VX 0xfc00707f +#define MASK_VREM_VX 0xfc00707f #define MATCH_VMULHU_VX 0x90006057 -#define MASK_VMULHU_VX 0xfc00707f +#define MASK_VMULHU_VX 0xfc00707f #define MATCH_VMUL_VX 0x94006057 -#define MASK_VMUL_VX 0xfc00707f +#define MASK_VMUL_VX 0xfc00707f #define MATCH_VMULHSU_VX 0x98006057 -#define MASK_VMULHSU_VX 0xfc00707f +#define MASK_VMULHSU_VX 0xfc00707f #define MATCH_VMULH_VX 0x9c006057 -#define MASK_VMULH_VX 0xfc00707f +#define MASK_VMULH_VX 0xfc00707f #define MATCH_VMADD_VX 0xa4006057 -#define MASK_VMADD_VX 0xfc00707f +#define MASK_VMADD_VX 0xfc00707f #define MATCH_VNMSUB_VX 0xac006057 -#define MASK_VNMSUB_VX 0xfc00707f +#define MASK_VNMSUB_VX 0xfc00707f #define MATCH_VMACC_VX 0xb4006057 -#define MASK_VMACC_VX 0xfc00707f +#define MASK_VMACC_VX 0xfc00707f #define MATCH_VNMSAC_VX 0xbc006057 -#define MASK_VNMSAC_VX 0xfc00707f +#define MASK_VNMSAC_VX 0xfc00707f #define MATCH_VWADDU_VX 0xc0006057 -#define MASK_VWADDU_VX 0xfc00707f +#define MASK_VWADDU_VX 0xfc00707f #define MATCH_VWADD_VX 0xc4006057 -#define MASK_VWADD_VX 0xfc00707f +#define MASK_VWADD_VX 0xfc00707f #define MATCH_VWSUBU_VX 0xc8006057 -#define MASK_VWSUBU_VX 0xfc00707f +#define MASK_VWSUBU_VX 0xfc00707f #define MATCH_VWSUB_VX 0xcc006057 -#define MASK_VWSUB_VX 0xfc00707f +#define MASK_VWSUB_VX 0xfc00707f #define MATCH_VWADDU_WX 0xd0006057 -#define MASK_VWADDU_WX 0xfc00707f +#define MASK_VWADDU_WX 0xfc00707f #define MATCH_VWADD_WX 0xd4006057 -#define MASK_VWADD_WX 0xfc00707f +#define MASK_VWADD_WX 0xfc00707f #define MATCH_VWSUBU_WX 0xd8006057 -#define MASK_VWSUBU_WX 0xfc00707f +#define MASK_VWSUBU_WX 0xfc00707f #define MATCH_VWSUB_WX 0xdc006057 -#define MASK_VWSUB_WX 0xfc00707f +#define MASK_VWSUB_WX 0xfc00707f #define MATCH_VWMULU_VX 0xe0006057 -#define MASK_VWMULU_VX 0xfc00707f +#define MASK_VWMULU_VX 0xfc00707f #define MATCH_VWMULSU_VX 0xe8006057 -#define MASK_VWMULSU_VX 0xfc00707f +#define MASK_VWMULSU_VX 0xfc00707f #define MATCH_VWMUL_VX 0xec006057 -#define MASK_VWMUL_VX 0xfc00707f +#define MASK_VWMUL_VX 0xfc00707f #define MATCH_VWMACCU_VX 0xf0006057 -#define MASK_VWMACCU_VX 0xfc00707f +#define MASK_VWMACCU_VX 0xfc00707f #define MATCH_VWMACC_VX 0xf4006057 -#define MASK_VWMACC_VX 0xfc00707f +#define MASK_VWMACC_VX 0xfc00707f #define MATCH_VWMACCUS_VX 0xf8006057 -#define MASK_VWMACCUS_VX 0xfc00707f +#define MASK_VWMACCUS_VX 0xfc00707f #define MATCH_VWMACCSU_VX 0xfc006057 -#define MASK_VWMACCSU_VX 0xfc00707f +#define MASK_VWMACCSU_VX 0xfc00707f #define MATCH_VAMOSWAPW_V 0x800602f -#define MASK_VAMOSWAPW_V 0xf800707f +#define MASK_VAMOSWAPW_V 0xf800707f #define MATCH_VAMOADDW_V 0x602f -#define MASK_VAMOADDW_V 0xf800707f +#define MASK_VAMOADDW_V 0xf800707f #define MATCH_VAMOXORW_V 0x2000602f -#define MASK_VAMOXORW_V 0xf800707f +#define MASK_VAMOXORW_V 0xf800707f #define MATCH_VAMOANDW_V 0x6000602f -#define MASK_VAMOANDW_V 0xf800707f +#define MASK_VAMOANDW_V 0xf800707f #define MATCH_VAMOORW_V 0x4000602f -#define MASK_VAMOORW_V 0xf800707f +#define MASK_VAMOORW_V 0xf800707f #define MATCH_VAMOMINW_V 0x8000602f -#define MASK_VAMOMINW_V 0xf800707f +#define MASK_VAMOMINW_V 0xf800707f #define MATCH_VAMOMAXW_V 0xa000602f -#define MASK_VAMOMAXW_V 0xf800707f +#define MASK_VAMOMAXW_V 0xf800707f #define MATCH_VAMOMINUW_V 0xc000602f -#define MASK_VAMOMINUW_V 0xf800707f +#define MASK_VAMOMINUW_V 0xf800707f #define MATCH_VAMOMAXUW_V 0xe000602f -#define MASK_VAMOMAXUW_V 0xf800707f +#define MASK_VAMOMAXUW_V 0xf800707f #define MATCH_VAMOSWAPE_V 0x800702f -#define MASK_VAMOSWAPE_V 0xf800707f +#define MASK_VAMOSWAPE_V 0xf800707f #define MATCH_VAMOADDE_V 0x702f -#define MASK_VAMOADDE_V 0xf800707f +#define MASK_VAMOADDE_V 0xf800707f #define MATCH_VAMOXORE_V 0x2000702f -#define MASK_VAMOXORE_V 0xf800707f +#define MASK_VAMOXORE_V 0xf800707f #define MATCH_VAMOANDE_V 0x6000702f -#define MASK_VAMOANDE_V 0xf800707f +#define MASK_VAMOANDE_V 0xf800707f #define MATCH_VAMOORE_V 0x4000702f -#define MASK_VAMOORE_V 0xf800707f +#define MASK_VAMOORE_V 0xf800707f #define MATCH_VAMOMINE_V 0x8000702f -#define MASK_VAMOMINE_V 0xf800707f +#define MASK_VAMOMINE_V 0xf800707f #define MATCH_VAMOMAXE_V 0xa000702f -#define MASK_VAMOMAXE_V 0xf800707f +#define MASK_VAMOMAXE_V 0xf800707f #define MATCH_VAMOMINUE_V 0xc000702f -#define MASK_VAMOMINUE_V 0xf800707f +#define MASK_VAMOMINUE_V 0xf800707f #define MATCH_VAMOMAXUE_V 0xe000702f -#define MASK_VAMOMAXUE_V 0xf800707f +#define MASK_VAMOMAXUE_V 0xf800707f #define MATCH_VMVNFR_V 0x9e003057 -#define MASK_VMVNFR_V 0xfe00707f +#define MASK_VMVNFR_V 0xfe00707f #define CSR_FFLAGS 0x1 #define CSR_FRM 0x2 #define CSR_FCSR 0x3 diff --git a/src/systems/cva6_reg/driver/main.c b/src/systems/cva6_reg/driver/main.c index 9e099dbe..efa749f0 100644 --- a/src/systems/cva6_reg/driver/main.c +++ b/src/systems/cva6_reg/driver/main.c @@ -16,17 +16,17 @@ #include "cva6_idma.h" -#define DMA_BASE 0x50000000 // dma base address +#define DMA_BASE 0x50000000 // dma base address -#define DMA_SRC_ADDR (DMA_BASE + DMA_FRONTEND_SRC_ADDR_REG_OFFSET) -#define DMA_DST_ADDR (DMA_BASE + DMA_FRONTEND_DST_ADDR_REG_OFFSET) +#define DMA_SRC_ADDR (DMA_BASE + DMA_FRONTEND_SRC_ADDR_REG_OFFSET) +#define DMA_DST_ADDR (DMA_BASE + DMA_FRONTEND_DST_ADDR_REG_OFFSET) #define DMA_NUMBYTES_ADDR (DMA_BASE + DMA_FRONTEND_NUM_BYTES_REG_OFFSET) -#define DMA_CONF_ADDR (DMA_BASE + DMA_FRONTEND_CONF_REG_OFFSET) -#define DMA_STATUS_ADDR (DMA_BASE + DMA_FRONTEND_STATUS_REG_OFFSET) -#define DMA_NEXTID_ADDR (DMA_BASE + DMA_FRONTEND_NEXT_ID_REG_OFFSET) -#define DMA_DONE_ADDR (DMA_BASE + DMA_FRONTEND_DONE_REG_OFFSET) +#define DMA_CONF_ADDR (DMA_BASE + DMA_FRONTEND_CONF_REG_OFFSET) +#define DMA_STATUS_ADDR (DMA_BASE + DMA_FRONTEND_STATUS_REG_OFFSET) +#define DMA_NEXTID_ADDR (DMA_BASE + DMA_FRONTEND_NEXT_ID_REG_OFFSET) +#define DMA_DONE_ADDR (DMA_BASE + DMA_FRONTEND_DONE_REG_OFFSET) -#define DMA_TRANSFER_SIZE (2*8) // data transfer size in bytes +#define DMA_TRANSFER_SIZE (2 * 8) // data transfer size in bytes #define DMA_CONF_DECOUPLE 0 #define DMA_CONF_DEBURST 0 @@ -35,14 +35,13 @@ #define TEST_SRC 0 #define VERBOSE 1 -#define ASSERT(expr, msg) \ -if (!(expr)) { \ - print_uart("assertion failed: "); \ - print_uart(msg); \ - print_uart("\n"); \ - return -1; \ -} - +#define ASSERT(expr, msg) \ + if (!(expr)) { \ + print_uart("assertion failed: "); \ + print_uart(msg); \ + print_uart("\n"); \ + return -1; \ + } int main(int argc, char const *argv[]) { @@ -55,13 +54,14 @@ int main(int argc, char const *argv[]) { /* * Setup relevant configuration registers */ - volatile uint64_t *dma_src = (volatile uint64_t *) DMA_SRC_ADDR; - volatile uint64_t *dma_dst = (volatile uint64_t *) DMA_DST_ADDR; - volatile uint64_t *dma_num_bytes = (volatile uint64_t *) DMA_NUMBYTES_ADDR; - volatile uint64_t *dma_conf = (volatile uint64_t *) DMA_CONF_ADDR; - // volatile uint64_t* dma_status = (volatile uint64_t*)DMA_STATUS_ADDR; // not used in current implementation - volatile uint64_t *dma_nextid = (volatile uint64_t *) DMA_NEXTID_ADDR; - volatile uint64_t *dma_done = (volatile uint64_t *) DMA_DONE_ADDR; + volatile uint64_t *dma_src = (volatile uint64_t *)DMA_SRC_ADDR; + volatile uint64_t *dma_dst = (volatile uint64_t *)DMA_DST_ADDR; + volatile uint64_t *dma_num_bytes = (volatile uint64_t *)DMA_NUMBYTES_ADDR; + volatile uint64_t *dma_conf = (volatile uint64_t *)DMA_CONF_ADDR; + // volatile uint64_t* dma_status = (volatile uint64_t*)DMA_STATUS_ADDR; // not used in current + // implementation + volatile uint64_t *dma_nextid = (volatile uint64_t *)DMA_NEXTID_ADDR; + volatile uint64_t *dma_done = (volatile uint64_t *)DMA_DONE_ADDR; /* * Prepare data @@ -71,7 +71,7 @@ int main(int argc, char const *argv[]) { if (VERBOSE) { // print array stack address print_uart("Source array @0x"); - print_uart_addr((uint64_t) & src); + print_uart_addr((uint64_t)&src); print_uart("\n"); } @@ -80,7 +80,7 @@ int main(int argc, char const *argv[]) { if (VERBOSE) { // print array stack address print_uart("Destination array @0x"); - print_uart_addr((uint64_t) & dst); + print_uart_addr((uint64_t)&dst); print_uart("\n"); } @@ -101,7 +101,7 @@ int main(int argc, char const *argv[]) { *dma_src = 42; *dma_dst = 42; *dma_num_bytes = 0; - *dma_conf = 7; // 0b111 + *dma_conf = 7; // 0b111 ASSERT(*dma_src == 42, "dma_src"); ASSERT(*dma_dst == 42, "dma_dst"); @@ -114,8 +114,8 @@ int main(int argc, char const *argv[]) { print_uart("Initiate dma request\n"); // setup src to dst memory transfer - *dma_src = (uint64_t) & src; - *dma_dst = (uint64_t) & dst; + *dma_src = (uint64_t)&src; + *dma_dst = (uint64_t)&dst; *dma_num_bytes = DMA_TRANSFER_SIZE; *dma_conf = (DMA_CONF_DECOUPLE << DMA_FRONTEND_CONF_DECOUPLE_BIT) | (DMA_CONF_DEBURST << DMA_FRONTEND_CONF_DEBURST_BIT) | @@ -126,9 +126,10 @@ int main(int argc, char const *argv[]) { // launch transfer: read id uint64_t transfer_id = *dma_nextid; - // CVA6 node interconnect work-around: add delay to free axi bus (axi_node does not allow parallel transactions -> need to upgrade axi xbar) + // CVA6 node interconnect work-around: add delay to free axi bus (axi_node does not allow + // parallel transactions -> need to upgrade axi xbar) for (int i = 0; i < 16 * DMA_TRANSFER_SIZE; i++) { - asm volatile ("nop" : : ); // nop operation + asm volatile("nop" : :); // nop operation } // poll wait for transfer to finish @@ -161,7 +162,6 @@ int main(int argc, char const *argv[]) { print_uart_int(src_val); print_uart("\n"); } - } print_uart("Transfer successfully validated.\n"); diff --git a/src/systems/cva6_reg/driver/trap.c b/src/systems/cva6_reg/driver/trap.c index 16672886..1b1660d2 100644 --- a/src/systems/cva6_reg/driver/trap.c +++ b/src/systems/cva6_reg/driver/trap.c @@ -6,7 +6,6 @@ // // Description: Simple trap handler - #include "trap.h" #include "uart.h" #include "encoding.h" @@ -14,11 +13,11 @@ void setup_trap() { // set interrupt function (direct mode) - asm volatile ("csrw mtvec, %[reg]" : : [reg] "r"(trap_entry)); + asm volatile("csrw mtvec, %[reg]" : : [reg] "r"(trap_entry)); // enable machine mode interrupts - asm volatile ("csrs mstatus, 0x8"); - asm volatile ("csrs mie, 0x8"); + asm volatile("csrs mstatus, 0x8"); + asm volatile("csrs mie, 0x8"); } void handle_trap() { @@ -29,56 +28,56 @@ void handle_trap() { // switch between causes switch (cause) { - case CAUSE_MISALIGNED_FETCH: - print_uart("Trap CAUSE_MISALIGNED_FETCH\n"); - break; - case CAUSE_FETCH_ACCESS: - print_uart("Trap CAUSE_FETCH_ACCESS\n"); - break; - case CAUSE_ILLEGAL_INSTRUCTION: - print_uart("Trap CAUSE_ILLEGAL_INSTRUCTION\n"); - break; - case CAUSE_BREAKPOINT: - print_uart("Trap CAUSE_BREAKPOINT\n"); - break; - case CAUSE_MISALIGNED_LOAD: - print_uart("Trap CAUSE_MISALIGNED_LOAD\n"); - break; - case CAUSE_LOAD_ACCESS: - print_uart("Trap CAUSE_LOAD_ACCESS\n"); - break; - case CAUSE_MISALIGNED_STORE: - print_uart("Trap CAUSE_MISALIGNED_STORE\n"); - break; - case CAUSE_STORE_ACCESS: - print_uart("Trap CAUSE_STORE_ACCESS\n"); - break; - case CAUSE_USER_ECALL: - print_uart("Trap CAUSE_USER_ECALL\n"); - break; - case CAUSE_SUPERVISOR_ECALL: - print_uart("Trap CAUSE_SUPERVISOR_ECALL\n"); - break; - case CAUSE_HYPERVISOR_ECALL: - print_uart("Trap CAUSE_HYPERVISOR_ECALL\n"); - break; - case CAUSE_MACHINE_ECALL: - print_uart("Trap CAUSE_MACHINE_ECALL\n"); - break; - case CAUSE_FETCH_PAGE_FAULT: - print_uart("Trap CAUSE_FETCH_PAGE_FAULT\n"); - break; - case CAUSE_LOAD_PAGE_FAULT: - print_uart("Trap CAUSE_LOAD_PAGE_FAULT\n"); - break; - case CAUSE_STORE_PAGE_FAULT: - print_uart("Trap CAUSE_STORE_PAGE_FAULT\n"); - break; - default: - print_uart("Trap OTHER: "); - print_uart_addr(cause); - print_uart("\n"); - break; + case CAUSE_MISALIGNED_FETCH: + print_uart("Trap CAUSE_MISALIGNED_FETCH\n"); + break; + case CAUSE_FETCH_ACCESS: + print_uart("Trap CAUSE_FETCH_ACCESS\n"); + break; + case CAUSE_ILLEGAL_INSTRUCTION: + print_uart("Trap CAUSE_ILLEGAL_INSTRUCTION\n"); + break; + case CAUSE_BREAKPOINT: + print_uart("Trap CAUSE_BREAKPOINT\n"); + break; + case CAUSE_MISALIGNED_LOAD: + print_uart("Trap CAUSE_MISALIGNED_LOAD\n"); + break; + case CAUSE_LOAD_ACCESS: + print_uart("Trap CAUSE_LOAD_ACCESS\n"); + break; + case CAUSE_MISALIGNED_STORE: + print_uart("Trap CAUSE_MISALIGNED_STORE\n"); + break; + case CAUSE_STORE_ACCESS: + print_uart("Trap CAUSE_STORE_ACCESS\n"); + break; + case CAUSE_USER_ECALL: + print_uart("Trap CAUSE_USER_ECALL\n"); + break; + case CAUSE_SUPERVISOR_ECALL: + print_uart("Trap CAUSE_SUPERVISOR_ECALL\n"); + break; + case CAUSE_HYPERVISOR_ECALL: + print_uart("Trap CAUSE_HYPERVISOR_ECALL\n"); + break; + case CAUSE_MACHINE_ECALL: + print_uart("Trap CAUSE_MACHINE_ECALL\n"); + break; + case CAUSE_FETCH_PAGE_FAULT: + print_uart("Trap CAUSE_FETCH_PAGE_FAULT\n"); + break; + case CAUSE_LOAD_PAGE_FAULT: + print_uart("Trap CAUSE_LOAD_PAGE_FAULT\n"); + break; + case CAUSE_STORE_PAGE_FAULT: + print_uart("Trap CAUSE_STORE_PAGE_FAULT\n"); + break; + default: + print_uart("Trap OTHER: "); + print_uart_addr(cause); + print_uart("\n"); + break; } // spin-loop diff --git a/src/systems/cva6_reg/driver/uart.c b/src/systems/cva6_reg/driver/uart.c index 491e0016..4cc1675b 100644 --- a/src/systems/cva6_reg/driver/uart.c +++ b/src/systems/cva6_reg/driver/uart.c @@ -4,67 +4,58 @@ #include "uart.h" -void write_reg_u8(uintptr_t addr, uint8_t value) -{ +void write_reg_u8(uintptr_t addr, uint8_t value) { volatile uint8_t *loc_addr = (volatile uint8_t *)addr; *loc_addr = value; } -uint8_t read_reg_u8(uintptr_t addr) -{ +uint8_t read_reg_u8(uintptr_t addr) { return *(volatile uint8_t *)addr; } -int is_transmit_empty() -{ +int is_transmit_empty() { return read_reg_u8(UART_LINE_STATUS) & 0x20; } -void write_serial(char a) -{ - while (is_transmit_empty() == 0) {}; +void write_serial(char a) { + while (is_transmit_empty() == 0) { + }; write_reg_u8(UART_THR, a); } -void init_uart(uint32_t freq, uint32_t baud) -{ +void init_uart(uint32_t freq, uint32_t baud) { uint32_t divisor = freq / (baud << 4); - write_reg_u8(UART_INTERRUPT_ENABLE, 0x00); // Disable all interrupts - write_reg_u8(UART_LINE_CONTROL, 0x80); // Enable DLAB (set baud rate divisor) - write_reg_u8(UART_DLAB_LSB, divisor); // divisor (lo byte) - write_reg_u8(UART_DLAB_MSB, (divisor >> 8) & 0xFF); // divisor (hi byte) - write_reg_u8(UART_LINE_CONTROL, 0x03); // 8 bits, no parity, one stop bit - write_reg_u8(UART_FIFO_CONTROL, 0xC7); // Enable FIFO, clear them, with 14-byte threshold - write_reg_u8(UART_MODEM_CONTROL, 0x20); // Autoflow mode + write_reg_u8(UART_INTERRUPT_ENABLE, 0x00); // Disable all interrupts + write_reg_u8(UART_LINE_CONTROL, 0x80); // Enable DLAB (set baud rate divisor) + write_reg_u8(UART_DLAB_LSB, divisor); // divisor (lo byte) + write_reg_u8(UART_DLAB_MSB, (divisor >> 8) & 0xFF); // divisor (hi byte) + write_reg_u8(UART_LINE_CONTROL, 0x03); // 8 bits, no parity, one stop bit + write_reg_u8(UART_FIFO_CONTROL, 0xC7); // Enable FIFO, clear them, with 14-byte threshold + write_reg_u8(UART_MODEM_CONTROL, 0x20); // Autoflow mode } -void print_uart(const char *str) -{ +void print_uart(const char *str) { const char *cur = &str[0]; - while (*cur != '\0') - { + while (*cur != '\0') { write_serial((uint8_t)*cur); ++cur; } } -uint8_t bin_to_hex_table[16] = { - '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; +uint8_t bin_to_hex_table[16] = {'0', '1', '2', '3', '4', '5', '6', '7', + '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; -void bin_to_hex(uint8_t inp, uint8_t res[2]) -{ +void bin_to_hex(uint8_t inp, uint8_t res[2]) { res[1] = bin_to_hex_table[inp & 0xf]; res[0] = bin_to_hex_table[(inp >> 4) & 0xf]; return; } -void print_uart_int(uint32_t addr) -{ +void print_uart_int(uint32_t addr) { int i; - for (i = 3; i > -1; i--) - { + for (i = 3; i > -1; i--) { uint8_t cur = (addr >> (i * 8)) & 0xff; uint8_t hex[2]; bin_to_hex(cur, hex); @@ -73,11 +64,9 @@ void print_uart_int(uint32_t addr) } } -void print_uart_addr(uint64_t addr) -{ +void print_uart_addr(uint64_t addr) { int i; - for (i = 7; i > -1; i--) - { + for (i = 7; i > -1; i--) { uint8_t cur = (addr >> (i * 8)) & 0xff; uint8_t hex[2]; bin_to_hex(cur, hex); @@ -86,8 +75,7 @@ void print_uart_addr(uint64_t addr) } } -void print_uart_byte(uint8_t byte) -{ +void print_uart_byte(uint8_t byte) { uint8_t hex[2]; bin_to_hex(byte, hex); write_serial(hex[0]); diff --git a/src/systems/cva6_reg/driver/uart.h b/src/systems/cva6_reg/driver/uart.h index 0bb974d6..23a118cc 100644 --- a/src/systems/cva6_reg/driver/uart.h +++ b/src/systems/cva6_reg/driver/uart.h @@ -22,7 +22,7 @@ void init_uart(); -void print_uart(const char* str); +void print_uart(const char *str); void print_uart_int(uint32_t addr); diff --git a/src/systems/pulpopen/dmac_wrap.sv b/src/systems/pulpopen/dmac_wrap.sv index 4994d0df..b5675d28 100644 --- a/src/systems/pulpopen/dmac_wrap.sv +++ b/src/systems/pulpopen/dmac_wrap.sv @@ -1,21 +1,18 @@ -// Copyright 2022 ETH Zurich and University of Bologna. +// Copyright 2023 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 - -/* - * dmac_wrap.sv - * Thomas Benz - * Michael Rogenmoser - * Tobias Senti - */ - -// DMA Core wrapper +// +// Authors: +// - Thomas Benz +// - Michael Rogenmoser +// - Tobias Senti `include "axi/assign.svh" `include "axi/typedef.svh" `include "idma/typedef.svh" `include "register_interface/typedef.svh" +/// DMA Core wrapper module dmac_wrap #( parameter int unsigned NB_CORES = 4, parameter int unsigned AXI_ADDR_WIDTH = 32, diff --git a/src/systems/pulpopen/driver/archi/idma_v1.h b/src/systems/pulpopen/driver/archi/idma_v1.h index 1f85ccd5..ef428347 100644 --- a/src/systems/pulpopen/driver/archi/idma_v1.h +++ b/src/systems/pulpopen/driver/archi/idma_v1.h @@ -46,7 +46,8 @@ extern "C" { #define IDMA_REG32_2D_FRONTEND_STATUS_BUSY_MASK 0xffff #define IDMA_REG32_2D_FRONTEND_STATUS_BUSY_OFFSET 0 #define IDMA_REG32_2D_FRONTEND_STATUS_BUSY_FIELD \ - ((bitfield_field32_t) { .mask = IDMA_REG32_2D_FRONTEND_STATUS_BUSY_MASK, .index = IDMA_REG32_2D_FRONTEND_STATUS_BUSY_OFFSET }) + ((bitfield_field32_t){.mask = IDMA_REG32_2D_FRONTEND_STATUS_BUSY_MASK, \ + .index = IDMA_REG32_2D_FRONTEND_STATUS_BUSY_OFFSET}) // Next ID, launches transfer, returns 0 if transfer not set up properly. #define IDMA_REG32_2D_FRONTEND_NEXT_ID_REG_OFFSET 0x20 @@ -55,9 +56,9 @@ extern "C" { #define IDMA_REG32_2D_FRONTEND_DONE_REG_OFFSET 0x24 #ifdef __cplusplus -} // extern "C" +} // extern "C" #endif -#endif // _IDMA_REG32_2D_FRONTEND_REG_DEFS_ +#endif // _IDMA_REG32_2D_FRONTEND_REG_DEFS_ // End generated register defines for idma_reg32_2d_frontend #endif // __ARCHI_IDMA_V1_H__ diff --git a/src/systems/pulpopen/driver/hal/idma_v1.h b/src/systems/pulpopen/driver/hal/idma_v1.h index a02c4048..194f6072 100644 --- a/src/systems/pulpopen/driver/hal/idma_v1.h +++ b/src/systems/pulpopen/driver/hal/idma_v1.h @@ -25,77 +25,103 @@ typedef unsigned int dma_ext_t; typedef unsigned int dma_loc_t; /** @name High-level DMA memory copy functions - * The following functions can be used to trigger DMA transfers to copy data between the cluster memory (L1) and another memory outside the cluster (another cluster L1 or L2). - * The DMA supports the following features: - * - Transfers are event-based. With event-based transfers the core can call a wait function to block execution until the transfer is done. - * - The DMA supports 2D transfers which allows transfering a 2D tile in one command. Additional information must then be given to specify the width of the tile and the number of bytes between 2 lines of the tile. + * The following functions can be used to trigger DMA transfers to copy data between the cluster + * memory (L1) and another memory outside the cluster (another cluster L1 or L2). The DMA supports + * the following features: + * - Transfers are event-based. With event-based transfers the core can call a wait function to + * block execution until the transfer is done. + * - The DMA supports 2D transfers which allows transfering a 2D tile in one command. Additional + * information must then be given to specify the width of the tile and the number of bytes between 2 + * lines of the tile. * - The event sent at the end of the transfer is broadcasted to all cluster cores. * - To identify specific transfers, the DMA provides a transfer identifier. - * - Multiple transfers can be launched simultaneously, with them being executed 2-4 in parallel, with more waiting in a queue. + * - Multiple transfers can be launched simultaneously, with them being executed 2-4 in parallel, + * with more waiting in a queue. */ /**@{*/ -/** Memory transfer with event-based completion. - * - \param ext Address in the external memory where to access the data. There is no restriction on memory alignment. - \param loc Address in the cluster memory where to access the data. There is no restriction on memory alignment. - \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. - \param ext2loc If 1, the transfer is loading data from external memory and storing to cluster memory. If 0, it is the contrary - \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. +/** Memory transfer with event-based completion. + * + \param ext Address in the external memory where to access the data. There is no restriction + on memory alignment. \param loc Address in the cluster memory where to access the data. There + is no restriction on memory alignment. \param size Number of bytes to be transfered. The only + restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. \param ext2loc If + 1, the transfer is loading data from external memory and storing to cluster memory. If 0, it is the + contrary \return The identifier of the transfer. This can be used with plp_dma_wait to + wait for the completion of this transfer. */ static inline int plp_dma_memcpy(dma_ext_t ext, unsigned int loc, unsigned int size, int ext2loc); -/** Cluster memory to external memory transfer with event-based completion. - * - \param ext Address in the external memory where to store the data. There is no restriction on memory alignment. - \param loc Address in the cluster memory where to load the data. There is no restriction on memory alignment. - \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. - \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. +/** Cluster memory to external memory transfer with event-based completion. + * + \param ext Address in the external memory where to store the data. There is no restriction on + memory alignment. \param loc Address in the cluster memory where to load the data. There is no + restriction on memory alignment. \param size Number of bytes to be transfered. The only + restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. \return The + identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this + transfer. */ static inline int plp_dma_l1ToExt(dma_ext_t ext, unsigned int loc, unsigned short size); -/** External memory to cluster memory transfer with event-based completion. - * - \param loc Address in the cluster memory where to store the data. There is no restriction on memory alignment. - \param ext Address in the external memory where to load the data. There is no restriction on memory alignment. - \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. - \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. +/** External memory to cluster memory transfer with event-based completion. + * + \param loc Address in the cluster memory where to store the data. There is no restriction on + memory alignment. \param ext Address in the external memory where to load the data. There is no + restriction on memory alignment. \param size Number of bytes to be transfered. The only + restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. \return The + identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this + transfer. */ static inline int plp_dma_extToL1(unsigned int loc, dma_ext_t ext, unsigned short size); -/** 2-dimensional memory transfer with event-based completion. - * - \param ext Address in the external memory where to access the data. There is no restriction on memory alignment. - \param loc Address in the cluster memory where to access the data. There is no restriction on memory alignment. - \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. - \param stride 2D stride, which is the number of bytes which are added to the beginning of the current line to switch to the next one. Must fit 16 bits, i.e. must be inferior to 65536. - \param length 2D length, which is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. - \param ext2loc If 1, the transfer is loading data from external memory and storing to cluster memory. If 0, it is the contrary - \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. +/** 2-dimensional memory transfer with event-based completion. + * + \param ext Address in the external memory where to access the data. There is no restriction + on memory alignment. \param loc Address in the cluster memory where to access the data. There + is no restriction on memory alignment. \param size Number of bytes to be transfered. The only + restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. \param stride 2D + stride, which is the number of bytes which are added to the beginning of the current line to switch + to the next one. Must fit 16 bits, i.e. must be inferior to 65536. \param length 2D length, which + is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 + bits, i.e. must be inferior to 65536. \param ext2loc If 1, the transfer is loading data from + external memory and storing to cluster memory. If 0, it is the contrary \return The + identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this + transfer. */ -static inline int plp_dma_memcpy_2d(dma_ext_t ext, unsigned int loc, unsigned int size, unsigned int stride, unsigned int length, int ext2loc); - -/** Cluster memory to external memory 2-dimensional transfer with event-based completion. - * - \param ext Address in the external memory where to store the data. There is no restriction on memory alignment. - \param loc Address in the cluster memory where to load the data. There is no restriction on memory alignment. - \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. - \param stride 2D stride, which is the number of bytes which are added to the beginning of the current line to switch to the next one. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. - \param length 2D length, which is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. - \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer. +static inline int plp_dma_memcpy_2d(dma_ext_t ext, unsigned int loc, unsigned int size, + unsigned int stride, unsigned int length, int ext2loc); + +/** Cluster memory to external memory 2-dimensional transfer with event-based completion. + * + \param ext Address in the external memory where to store the data. There is no restriction on + memory alignment. \param loc Address in the cluster memory where to load the data. There is no + restriction on memory alignment. \param size Number of bytes to be transfered. The only + restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. \param stride 2D + stride, which is the number of bytes which are added to the beginning of the current line to switch + to the next one. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the + external memory. \param length 2D length, which is the number of transfered bytes after which the + DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. This applies + only to the external memory. \return The identifier of the transfer. This can be used with + plp_dma_wait to wait for the completion of this transfer. */ -static inline int plp_dma_l1ToExt_2d(dma_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length); - -/** External memory to cluster memory 2-dimensional transfer with event-based completion. - * - \param loc Address in the cluster memory where to store the data. There is no restriction on memory alignment. - \param ext Address in the external memory where to load the data. There is no restriction on memory alignment. - \param size Number of bytes to be transfered. The only restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. - \param stride 2D stride, which is the number of bytes which are added to the beginning of the current line to switch to the next one. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. - \param length 2D length, which is the number of transfered bytes after which the DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the external memory. - \return The identifier of the transfer. This can be used with plp_dma_wait to wait for the completion of this transfer +static inline int plp_dma_l1ToExt_2d(dma_ext_t ext, unsigned int loc, unsigned short size, + unsigned short stride, unsigned short length); + +/** External memory to cluster memory 2-dimensional transfer with event-based completion. + * + \param loc Address in the cluster memory where to store the data. There is no restriction on + memory alignment. \param ext Address in the external memory where to load the data. There is + no restriction on memory alignment. \param size Number of bytes to be transfered. The only + restriction is that this size must fit 16 bits, i.e. must be inferior to 65536. \param stride 2D + stride, which is the number of bytes which are added to the beginning of the current line to switch + to the next one. Must fit 16 bits, i.e. must be inferior to 65536. This applies only to the + external memory. \param length 2D length, which is the number of transfered bytes after which the + DMA will switch to the next line. Must fit 16 bits, i.e. must be inferior to 65536. This applies + only to the external memory. \return The identifier of the transfer. This can be used with + plp_dma_wait to wait for the completion of this transfer */ -static inline int plp_dma_extToL1_2d(unsigned int loc, dma_ext_t ext, unsigned short size, unsigned short stride, unsigned short length); +static inline int plp_dma_extToL1_2d(unsigned int loc, dma_ext_t ext, unsigned short size, + unsigned short stride, unsigned short length); //!@} @@ -103,22 +129,23 @@ static inline int plp_dma_extToL1_2d(unsigned int loc, dma_ext_t ext, unsigned s */ /** DMA barrier. - * This blocks the core until no transfer is on-going in the DMA. + * This blocks the core until no transfer is on-going in the DMA. */ static inline void plp_dma_barrier(); /** DMA wait. - * This blocks the core until the specified transfer is finished. + * This blocks the core until the specified transfer is finished. * - \param counter The counter ID identifying the transfer. This has been returned from an enqueued transfer (e.g. plp_dma_extToL1_2d) + \param counter The counter ID identifying the transfer. This has been returned from an enqueued + transfer (e.g. plp_dma_extToL1_2d) */ static inline void plp_dma_wait(unsigned int dma_tx_id); //!@} - /** @name iDMA low-level functions. - * This can be used instead of the high-level ones in order to have more control over the DMA features. + * This can be used instead of the high-level ones in order to have more control over the DMA + * features. */ /** @@ -126,16 +153,15 @@ static inline void plp_dma_wait(unsigned int dma_tx_id); * A standard memcpy will set all of these values to 0. * \param decouple if set to true, there is no longer exactly one AXI write_request issued for - every read request. This mode can improve performance of unaligned transfers when crossing - the AXI page boundaries. - \param deburst if set, the DMA will split all bursts in single transfers - \param serialize if set, the DMA will only send AX belonging to a given Arbitrary 1D burst request - at a time. This is default behavior to prevent deadlocks. Setting `serialize` to - zero violates the AXI4+ATOP specification. - \param twod if set, the DMA will execute a 2D transfer. - \return The generated configuration + every read request. This mode can improve performance of unaligned transfers + when crossing the AXI page boundaries. \param deburst if set, the DMA will split all bursts in + single transfers \param serialize if set, the DMA will only send AX belonging to a given + Arbitrary 1D burst request at a time. This is default behavior to prevent deadlocks. Setting + `serialize` to zero violates the AXI4+ATOP specification. \param twod if set, the DMA will + execute a 2D transfer. \return The generated configuration */ -static inline unsigned int pulp_idma_get_conf(unsigned int decouple, unsigned int deburst, unsigned int serialize, unsigned int twod); +static inline unsigned int pulp_idma_get_conf(unsigned int decouple, unsigned int deburst, + unsigned int serialize, unsigned int twod); /** * iDMA transfer status @@ -154,7 +180,8 @@ static inline unsigned int pulp_idma_tx_cplt(unsigned int dma_tx_id); \param num_bytes The number bytes \return The dma transfer identifier */ -static inline unsigned int pulp_idma_memcpy(unsigned int const dst_addr, unsigned int const src_addr, unsigned int num_bytes); +static inline unsigned int pulp_idma_memcpy(unsigned int const dst_addr, + unsigned int const src_addr, unsigned int num_bytes); /** * iDMA 2D memory transfer @@ -168,8 +195,10 @@ static inline unsigned int pulp_idma_memcpy(unsigned int const dst_addr, unsigne \param num_reps The number of repetitions \return The dma transfer identifier */ -static inline unsigned int pulp_idma_memcpy_2d(unsigned int const dst_addr, unsigned int const src_addr, unsigned int num_bytes, unsigned int dst_stride, unsigned int src_stride, unsigned int num_reps); - +static inline unsigned int pulp_idma_memcpy_2d(unsigned int const dst_addr, + unsigned int const src_addr, unsigned int num_bytes, + unsigned int dst_stride, unsigned int src_stride, + unsigned int num_reps); /** * iDMA advanced memory transfer @@ -179,30 +208,30 @@ static inline unsigned int pulp_idma_memcpy_2d(unsigned int const dst_addr, unsi \param src_addr The source address \param num_bytes The number bytes \param decouple if set to true, there is no longer exactly one AXI write_request issued for - every read request. This mode can improve performance of unaligned transfers when crossing - the AXI page boundaries. - \param deburst if set, the DMA will split all bursts in single transfers - \param serialize if set, the DMA will only send AX belonging to a given Arbitrary 1D burst request - at a time. This is default behavior to prevent deadlocks. Setting `serialize` to - zero violates the AXI4+ATOP specification. - \param twod if set, the DMA will execute a 2D transfer - \param dst_stride if 2D, the stride at the destination - \param src_stride if 2D, the stride at the source - \param num_reps if 2D, the number of repetitions - \return The dma trasfer identifier + every read request. This mode can improve performance of unaligned transfers + when crossing the AXI page boundaries. \param deburst if set, the DMA will split all bursts in + single transfers \param serialize if set, the DMA will only send AX belonging to a given + Arbitrary 1D burst request at a time. This is default behavior to prevent deadlocks. Setting + `serialize` to zero violates the AXI4+ATOP specification. \param twod if set, the DMA will + execute a 2D transfer \param dst_stride if 2D, the stride at the destination \param src_stride if + 2D, the stride at the source \param num_reps if 2D, the number of repetitions \return The dma + trasfer identifier */ -static inline unsigned int pulp_idma_memcpy_advanced(unsigned int const dst_addr, unsigned int const src_addr, unsigned int num_bytes, unsigned int decouple, unsigned int deburst, unsigned int serialize, unsigned int twod, unsigned int dst_stride, unsigned int src_stride, unsigned int num_reps); +static inline unsigned int +pulp_idma_memcpy_advanced(unsigned int const dst_addr, unsigned int const src_addr, + unsigned int num_bytes, unsigned int decouple, unsigned int deburst, + unsigned int serialize, unsigned int twod, unsigned int dst_stride, + unsigned int src_stride, unsigned int num_reps); /** Return the DMA status. - * - \return DMA status. 1 means there are still on-going transfers, 0 means nothing is on-going. - */ + * + \return DMA status. 1 means there are still on-going transfers, 0 means nothing is + on-going. + */ static inline unsigned int plp_dma_status(); - //!@} - /// @cond IMPLEM #if ARCHI_HAS_DMA_DEMUX @@ -218,126 +247,140 @@ static inline unsigned int plp_dma_status(); #define DMA_READ(offset) pulp_read32(DMA_ADDR + (offset)) #endif -static inline unsigned int pulp_idma_get_conf(unsigned int decouple, unsigned int deburst, unsigned int serialize, unsigned int twod) { - unsigned int conf; +static inline unsigned int pulp_idma_get_conf(unsigned int decouple, unsigned int deburst, + unsigned int serialize, unsigned int twod) { + unsigned int conf; #if defined(__riscv__) - conf = __builtin_bitinsert(0, decouple, 1, IDMA_REG32_2D_FRONTEND_CONF_DECOUPLE_BIT); - conf = __builtin_bitinsert(conf, deburst, 1, IDMA_REG32_2D_FRONTEND_CONF_DEBURST_BIT); - conf = __builtin_bitinsert(conf, serialize, 1, IDMA_REG32_2D_FRONTEND_CONF_SERIALIZE_BIT); - conf = __builtin_bitinsert(conf, twod, 1, IDMA_REG32_2D_FRONTEND_CONF_TWOD_BIT); + conf = __builtin_bitinsert(0, decouple, 1, IDMA_REG32_2D_FRONTEND_CONF_DECOUPLE_BIT); + conf = __builtin_bitinsert(conf, deburst, 1, IDMA_REG32_2D_FRONTEND_CONF_DEBURST_BIT); + conf = __builtin_bitinsert(conf, serialize, 1, IDMA_REG32_2D_FRONTEND_CONF_SERIALIZE_BIT); + conf = __builtin_bitinsert(conf, twod, 1, IDMA_REG32_2D_FRONTEND_CONF_TWOD_BIT); #else - conf = (((decouple & 0x1)<> (IDMA_ID_COUNTER_WIDTH-1) == my_id >> (IDMA_ID_COUNTER_WIDTH-1)) { - return my_id <= done_id; - } else { - return ((done_id & (IDMA_ID_MASK - (1<<(IDMA_ID_COUNTER_WIDTH-1))) < (1<<(IDMA_ID_COUNTER_WIDTH-2)))); - } + unsigned int done_id = DMA_READ(IDMA_REG32_2D_FRONTEND_DONE_REG_OFFSET); + unsigned int my_id = dma_tx_id & IDMA_ID_MASK; + if (done_id >> (IDMA_ID_COUNTER_WIDTH - 1) == my_id >> (IDMA_ID_COUNTER_WIDTH - 1)) { + return my_id <= done_id; + } else { + return ((done_id & (IDMA_ID_MASK - (1 << (IDMA_ID_COUNTER_WIDTH - 1))) < + (1 << (IDMA_ID_COUNTER_WIDTH - 2)))); + } } +static inline unsigned int pulp_idma_memcpy(unsigned int const dst_addr, + unsigned int const src_addr, unsigned int num_bytes) { + DMA_WRITE(src_addr, IDMA_REG32_2D_FRONTEND_SRC_ADDR_REG_OFFSET); + DMA_WRITE(dst_addr, IDMA_REG32_2D_FRONTEND_DST_ADDR_REG_OFFSET); + DMA_WRITE(num_bytes, IDMA_REG32_2D_FRONTEND_NUM_BYTES_REG_OFFSET); + DMA_WRITE(IDMA_DEFAULT_CONFIG, IDMA_REG32_2D_FRONTEND_CONF_REG_OFFSET); + asm volatile("" : : : "memory"); -static inline unsigned int pulp_idma_memcpy(unsigned int const dst_addr, unsigned int const src_addr, unsigned int num_bytes) { - DMA_WRITE(src_addr, IDMA_REG32_2D_FRONTEND_SRC_ADDR_REG_OFFSET); - DMA_WRITE(dst_addr, IDMA_REG32_2D_FRONTEND_DST_ADDR_REG_OFFSET); - DMA_WRITE(num_bytes, IDMA_REG32_2D_FRONTEND_NUM_BYTES_REG_OFFSET); - DMA_WRITE(IDMA_DEFAULT_CONFIG, IDMA_REG32_2D_FRONTEND_CONF_REG_OFFSET); - asm volatile("" : : : "memory"); - - // Launch TX - unsigned int dma_tx_id = DMA_READ(IDMA_REG32_2D_FRONTEND_NEXT_ID_REG_OFFSET); + // Launch TX + unsigned int dma_tx_id = DMA_READ(IDMA_REG32_2D_FRONTEND_NEXT_ID_REG_OFFSET); - return dma_tx_id; + return dma_tx_id; } -static inline unsigned int pulp_idma_memcpy_2d(unsigned int const dst_addr, unsigned int const src_addr, unsigned int num_bytes, unsigned int dst_stride, unsigned int src_stride, unsigned int num_reps) { - DMA_WRITE(src_addr, IDMA_REG32_2D_FRONTEND_SRC_ADDR_REG_OFFSET); - DMA_WRITE(dst_addr, IDMA_REG32_2D_FRONTEND_DST_ADDR_REG_OFFSET); - DMA_WRITE(num_bytes, IDMA_REG32_2D_FRONTEND_NUM_BYTES_REG_OFFSET); - DMA_WRITE(IDMA_DEFAULT_CONFIG_2D, IDMA_REG32_2D_FRONTEND_CONF_REG_OFFSET); - DMA_WRITE(src_stride, IDMA_REG32_2D_FRONTEND_STRIDE_SRC_REG_OFFSET); - DMA_WRITE(dst_stride, IDMA_REG32_2D_FRONTEND_STRIDE_DST_REG_OFFSET); - DMA_WRITE(num_reps, IDMA_REG32_2D_FRONTEND_NUM_REPETITIONS_REG_OFFSET); - asm volatile("" : : : "memory"); - - // Launch TX - unsigned int dma_tx_id = DMA_READ(IDMA_REG32_2D_FRONTEND_NEXT_ID_REG_OFFSET); - - return dma_tx_id; -} - - -static inline unsigned int pulp_idma_memcpy_advanced(unsigned int const dst_addr, unsigned int const src_addr, unsigned int num_bytes, unsigned int decouple, unsigned int deburst, unsigned int serialize, unsigned int twod, unsigned int dst_stride, unsigned int src_stride, unsigned int num_reps) { - DMA_WRITE(src_addr, IDMA_REG32_2D_FRONTEND_SRC_ADDR_REG_OFFSET); - DMA_WRITE(dst_addr, IDMA_REG32_2D_FRONTEND_DST_ADDR_REG_OFFSET); - DMA_WRITE(num_bytes, IDMA_REG32_2D_FRONTEND_NUM_BYTES_REG_OFFSET); - unsigned int conf = pulp_idma_get_conf(decouple, deburst, serialize, twod); - DMA_WRITE(conf, IDMA_REG32_2D_FRONTEND_CONF_REG_OFFSET); - if (twod) { +static inline unsigned int pulp_idma_memcpy_2d(unsigned int const dst_addr, + unsigned int const src_addr, unsigned int num_bytes, + unsigned int dst_stride, unsigned int src_stride, + unsigned int num_reps) { + DMA_WRITE(src_addr, IDMA_REG32_2D_FRONTEND_SRC_ADDR_REG_OFFSET); + DMA_WRITE(dst_addr, IDMA_REG32_2D_FRONTEND_DST_ADDR_REG_OFFSET); + DMA_WRITE(num_bytes, IDMA_REG32_2D_FRONTEND_NUM_BYTES_REG_OFFSET); + DMA_WRITE(IDMA_DEFAULT_CONFIG_2D, IDMA_REG32_2D_FRONTEND_CONF_REG_OFFSET); DMA_WRITE(src_stride, IDMA_REG32_2D_FRONTEND_STRIDE_SRC_REG_OFFSET); DMA_WRITE(dst_stride, IDMA_REG32_2D_FRONTEND_STRIDE_DST_REG_OFFSET); DMA_WRITE(num_reps, IDMA_REG32_2D_FRONTEND_NUM_REPETITIONS_REG_OFFSET); - } - asm volatile("" : : : "memory"); + asm volatile("" : : : "memory"); - // Launch TX - unsigned int dma_tx_id = DMA_READ(IDMA_REG32_2D_FRONTEND_NEXT_ID_REG_OFFSET); + // Launch TX + unsigned int dma_tx_id = DMA_READ(IDMA_REG32_2D_FRONTEND_NEXT_ID_REG_OFFSET); - return dma_tx_id; + return dma_tx_id; +} + +static inline unsigned int +pulp_idma_memcpy_advanced(unsigned int const dst_addr, unsigned int const src_addr, + unsigned int num_bytes, unsigned int decouple, unsigned int deburst, + unsigned int serialize, unsigned int twod, unsigned int dst_stride, + unsigned int src_stride, unsigned int num_reps) { + DMA_WRITE(src_addr, IDMA_REG32_2D_FRONTEND_SRC_ADDR_REG_OFFSET); + DMA_WRITE(dst_addr, IDMA_REG32_2D_FRONTEND_DST_ADDR_REG_OFFSET); + DMA_WRITE(num_bytes, IDMA_REG32_2D_FRONTEND_NUM_BYTES_REG_OFFSET); + unsigned int conf = pulp_idma_get_conf(decouple, deburst, serialize, twod); + DMA_WRITE(conf, IDMA_REG32_2D_FRONTEND_CONF_REG_OFFSET); + if (twod) { + DMA_WRITE(src_stride, IDMA_REG32_2D_FRONTEND_STRIDE_SRC_REG_OFFSET); + DMA_WRITE(dst_stride, IDMA_REG32_2D_FRONTEND_STRIDE_DST_REG_OFFSET); + DMA_WRITE(num_reps, IDMA_REG32_2D_FRONTEND_NUM_REPETITIONS_REG_OFFSET); + } + asm volatile("" : : : "memory"); + + // Launch TX + unsigned int dma_tx_id = DMA_READ(IDMA_REG32_2D_FRONTEND_NEXT_ID_REG_OFFSET); + + return dma_tx_id; } static inline unsigned int plp_dma_status() { - return DMA_READ(IDMA_REG32_2D_FRONTEND_STATUS_REG_OFFSET); + return DMA_READ(IDMA_REG32_2D_FRONTEND_STATUS_REG_OFFSET); } static inline void plp_dma_wait(unsigned int dma_tx_id) { - while(!pulp_idma_tx_cplt(dma_tx_id)) { - eu_evt_maskWaitAndClr(1 << IDMA_EVENT); - } - return; + while (!pulp_idma_tx_cplt(dma_tx_id)) { + eu_evt_maskWaitAndClr(1 << IDMA_EVENT); + } + return; } static inline int plp_dma_memcpy(dma_ext_t ext, unsigned int loc, unsigned int size, int ext2loc) { - if (ext2loc) { - return pulp_idma_memcpy(loc, ext, size); - } else { - return pulp_idma_memcpy(ext, loc, size); - } + if (ext2loc) { + return pulp_idma_memcpy(loc, ext, size); + } else { + return pulp_idma_memcpy(ext, loc, size); + } } static inline int plp_dma_l1ToExt(dma_ext_t ext, unsigned int loc, unsigned short size) { - return pulp_idma_memcpy(ext, loc, size); + return pulp_idma_memcpy(ext, loc, size); } static inline int plp_dma_extToL1(unsigned int loc, dma_ext_t ext, unsigned short size) { - return pulp_idma_memcpy(loc, ext, size); + return pulp_idma_memcpy(loc, ext, size); } -static inline int plp_dma_memcpy_2d(dma_ext_t ext, unsigned int loc, unsigned int size, unsigned int stride, unsigned int length, int ext2loc) { - if (ext2loc) { - return pulp_idma_memcpy_2d(loc, ext, length, length, stride, size/length); - } else { - return pulp_idma_memcpy_2d(ext, loc, length, stride, length, size/length); - } +static inline int plp_dma_memcpy_2d(dma_ext_t ext, unsigned int loc, unsigned int size, + unsigned int stride, unsigned int length, int ext2loc) { + if (ext2loc) { + return pulp_idma_memcpy_2d(loc, ext, length, length, stride, size / length); + } else { + return pulp_idma_memcpy_2d(ext, loc, length, stride, length, size / length); + } } -static inline int plp_dma_l1ToExt_2d(dma_ext_t ext, unsigned int loc, unsigned short size, unsigned short stride, unsigned short length) { - return pulp_idma_memcpy_2d(ext, loc, length, stride, length, size/length); +static inline int plp_dma_l1ToExt_2d(dma_ext_t ext, unsigned int loc, unsigned short size, + unsigned short stride, unsigned short length) { + return pulp_idma_memcpy_2d(ext, loc, length, stride, length, size / length); } -static inline int plp_dma_extToL1_2d(unsigned int loc, dma_ext_t ext, unsigned short size, unsigned short stride, unsigned short length) { - return pulp_idma_memcpy_2d(loc, ext, length, length, stride, size/length); +static inline int plp_dma_extToL1_2d(unsigned int loc, dma_ext_t ext, unsigned short size, + unsigned short stride, unsigned short length) { + return pulp_idma_memcpy_2d(loc, ext, length, length, stride, size / length); } static inline void plp_dma_barrier() { - while(plp_dma_status()) { - eu_evt_maskWaitAndClr(1 << IDMA_EVENT); - } + while (plp_dma_status()) { + eu_evt_maskWaitAndClr(1 << IDMA_EVENT); + } } #endif // __HAL_IDMA_V1_H__ diff --git a/src/systems/pulpopen/synth_dmac_wrap.sv b/src/systems/pulpopen/synth_dmac_wrap.sv index bd112520..5a26c460 100644 --- a/src/systems/pulpopen/synth_dmac_wrap.sv +++ b/src/systems/pulpopen/synth_dmac_wrap.sv @@ -1,3 +1,13 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Authors: +// - Thomas Benz +// - Michael Rogenmoser +// - Tobias Senti + +/// Synthesis wrapper for DMAC module synth_dmac_wrap #( parameter int unsigned DualBackend = 0, parameter int unsigned NumAx = 2, diff --git a/target/.gitignore b/target/.gitignore new file mode 100644 index 00000000..76f779fa --- /dev/null +++ b/target/.gitignore @@ -0,0 +1,2 @@ +doc +morty \ No newline at end of file diff --git a/target/rtl/.gitignore b/target/rtl/.gitignore new file mode 100644 index 00000000..26a89ae3 --- /dev/null +++ b/target/rtl/.gitignore @@ -0,0 +1,2 @@ +Bender.yml +*.sv diff --git a/target/rtl/tpl/Bender.yml.tpl b/target/rtl/tpl/Bender.yml.tpl new file mode 100644 index 00000000..641a5295 --- /dev/null +++ b/target/rtl/tpl/Bender.yml.tpl @@ -0,0 +1,42 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +package: + name: idma_gen + authors: + - "Thomas Benz " + - "Tobias Senti " + +dependencies: + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.31.1 } + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0 } + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.2 } + +export_include_dirs: + - ../../src/include + +sources: + # Source files grouped in levels. Files in level 0 have no dependencies on files in this + # package. Files in level 1 only depend on files in level 0, files in level 2 on files in + # levels 1 and 0, etc. Files within a level are ordered alphabetically. + - target: rtl + files: + # Level 0 + - idma_desc64_reg_pkg.sv + - idma_reg32_2d_reg_pkg.sv + - idma_reg64_reg_pkg.sv + - idma_reg64_2d_reg_pkg.sv + - idma_desc64_reg_top.sv + - idma_reg32_2d_reg_top.sv + - idma_reg64_reg_top.sv + - idma_reg64_2d_reg_top.sv +${rtl_sources} + - target: test + files: + # Level 0 +${test_sources} + - target: synthesis + files: + # Level 0 +${synth_sources} diff --git a/scripts/start_vcs b/target/sim/vcs/start similarity index 83% rename from scripts/start_vcs rename to target/sim/vcs/start index 241ac00e..b54ca299 100755 --- a/scripts/start_vcs +++ b/target/sim/vcs/start @@ -3,4 +3,7 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 +# Authors: +# - Thomas Benz + bin/$1.vcs +vcs+lic+wait +job_file=$2 | tee logs/$3.vcs.log diff --git a/target/sim/vsim/.gitignore b/target/sim/vsim/.gitignore new file mode 100644 index 00000000..df5e57ab --- /dev/null +++ b/target/sim/vsim/.gitignore @@ -0,0 +1,2 @@ +compile.tcl +wave/*.do diff --git a/scripts/start_vsim.tcl b/target/sim/vsim/start.tcl similarity index 81% rename from scripts/start_vsim.tcl rename to target/sim/vsim/start.tcl index 173d56a2..5d8a22c4 100644 --- a/scripts/start_vsim.tcl +++ b/target/sim/vsim/start.tcl @@ -2,7 +2,8 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# Author: Thomas Benz +# Authors: +# - Thomas Benz set StdArithNoWarnings 1 set NumericStdNoWarnings 1 diff --git a/target/sim/vsim/wave/tpl/backend.do.tpl b/target/sim/vsim/wave/tpl/backend.do.tpl new file mode 100644 index 00000000..2532b53c --- /dev/null +++ b/target/sim/vsim/wave/tpl/backend.do.tpl @@ -0,0 +1,177 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/clk_i +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/rst_ni +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/testmode_i +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/idma_req_i +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/req_valid_i +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/req_ready_o +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/idma_rsp_o +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/rsp_valid_o +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/rsp_ready_i +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/idma_eh_req_i +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/eh_req_valid_i +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/eh_req_ready_o +% for protocol in used_read_protocols: +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/${protocol}_read_req_o +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/${protocol}_read_rsp_i +% endfor +% for protocol in used_write_protocols: +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/${protocol}_write_req_o +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/${protocol}_write_rsp_i +% endfor +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/busy_o +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/dp_busy +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/dp_poison +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/r_req +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/w_req +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/r_valid +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/w_valid +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/r_ready +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/w_ready +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/w_last_burst +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/w_last_ready +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/w_super_last +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/r_dp_req_in_ready +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/w_dp_req_in_ready +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/r_dp_req_out_valid +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/w_dp_req_out_valid +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/r_dp_req_out_ready +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/w_dp_req_out_ready +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/r_dp_req_out +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/w_dp_req_out +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/r_dp_rsp +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/w_dp_rsp +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/r_dp_rsp_valid +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/w_dp_rsp_valid +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/r_dp_rsp_ready +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/w_dp_rsp_ready +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/ar_ready +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/aw_ready +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/aw_ready_dp +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/aw_valid_dp +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/aw_req_dp +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/legalizer_flush +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/legalizer_kill +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/is_length_zero +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/req_valid +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/idma_rsp +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/rsp_valid +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/rsp_ready +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/clk_i +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/rst_ni +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/req_i +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/valid_i +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/ready_o +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_req_o +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_valid_o +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_ready_i +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_req_o +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_valid_o +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_ready_i +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/flush_i +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/kill_i +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_busy_o +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_busy_o +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_tf_q +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_tf_q +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/opt_tf_q +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_tf_ena +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_tf_ena +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_num_bytes_to_pb +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_num_bytes_to_pb +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/c_num_bytes_to_pb +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_num_bytes_possible +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_num_bytes +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_addr_offset +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/r_done +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_num_bytes_possible +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_num_bytes +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_addr_offset +add wave -noupdate -group Legalizer /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_hw_legalizer/i_idma_legalizer/w_done +add wave -noupdate -group {Transport Layer} /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/clk_i +add wave -noupdate -group {Transport Layer} /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/rst_ni +add wave -noupdate -group {Transport Layer} /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/testmode_i +% for protocol in used_read_protocols: +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/${protocol}_read_req_o +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/${protocol}_read_rsp_i +% endfor +% for protocol in used_write_protocols: +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/${protocol}_write_req_o +add wave -noupdate -expand -group Backend /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/${protocol}_write_rsp_i +% endfor +add wave -noupdate -group {Transport Layer} /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/* +% for protocol in used_read_protocols: +add wave -noupdate -group {${database[protocol]['full_name']} Read} -expand /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/i_idma_${protocol}_read/* +% endfor +% for protocol in used_write_protocols: +add wave -noupdate -group {${database[protocol]['full_name']} Write} -expand /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/i_idma_${protocol}_write/* +% endfor +% if not one_write_port: +add wave -noupdate -group {Write Response FIFO} -expand /tb_idma_backend_${name_uniqueifier}/i_idma_backend/i_idma_transport_layer/i_write_response_fifo/* +% endif +% if one_read_port and one_write_port and ('axi' in used_read_protocols) and ('axi' in used_write_protocols): +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/clk_i +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/rst_ni +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/testmode_i +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/r_rsp_valid_i +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/r_rsp_ready_i +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/r_rsp_first_i +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/r_decouple_aw_i +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_decouple_aw_i +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_req_i +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_valid_i +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_ready_o +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_req_o +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_valid_o +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_ready_i +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_req_in +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_req_out +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_ready +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_valid +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/first +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_sent +add wave -noupdate -group R-AW-Coupler /tb_idma_backend_${name_uniqueifier}/i_idma_backend/gen_r_aw_coupler/i_idma_channel_coupler/aw_to_send_q +% endif +add wave -noupdate -divider BUS +% for protocol in used_protocols: + % if protocol == 'axi': +add wave -noupdate -group {${database[protocol]['full_name']} IF} -label AW /tb_idma_backend_${name_uniqueifier}/i_aw_hl/in_wave +add wave -noupdate -group {${database[protocol]['full_name']} IF} -label AR /tb_idma_backend_${name_uniqueifier}/i_ar_hl/in_wave +add wave -noupdate -group {${database[protocol]['full_name']} IF} -label W /tb_idma_backend_${name_uniqueifier}/i_w_hl/in_wave +add wave -noupdate -group {${database[protocol]['full_name']} IF} -label R /tb_idma_backend_${name_uniqueifier}/i_r_hl/in_wave +add wave -noupdate -group {${database[protocol]['full_name']} IF} -label B /tb_idma_backend_${name_uniqueifier}/i_b_hl/in_wave + % else: +add wave -noupdate -group {${database[protocol]['full_name']} ${database['axi']['full_name']} IF} -label AW /tb_idma_backend_${name_uniqueifier}/i_${protocol}_aw_hl/in_wave +add wave -noupdate -group {${database[protocol]['full_name']} ${database['axi']['full_name']} IF} -label AR /tb_idma_backend_${name_uniqueifier}/i_${protocol}_ar_hl/in_wave +add wave -noupdate -group {${database[protocol]['full_name']} ${database['axi']['full_name']} IF} -label W /tb_idma_backend_${name_uniqueifier}/i_${protocol}_w_hl/in_wave +add wave -noupdate -group {${database[protocol]['full_name']} ${database['axi']['full_name']} IF} -label R /tb_idma_backend_${name_uniqueifier}/i_${protocol}_r_hl/in_wave +add wave -noupdate -group {${database[protocol]['full_name']} ${database['axi']['full_name']} IF} -label B /tb_idma_backend_${name_uniqueifier}/i_${protocol}_b_hl/in_wave + % endif +% endfor +add wave -noupdate -group {iDMA IF} -label {iDMA REQ} /tb_idma_backend_${name_uniqueifier}/i_req_hl/in_wave +add wave -noupdate -group {iDMA IF} -label {iDMA RSP} -expand -subitemconfig {/tb_idma_backend_${name_uniqueifier}/i_rsp_hl/in_wave.pld -expand} /tb_idma_backend_${name_uniqueifier}/i_rsp_hl/in_wave +add wave -noupdate -group {iDMA IF} -label {iDMA EH} /tb_idma_backend_${name_uniqueifier}/i_eh_hl/in_wave +add wave -noupdate -group Busy -expand /tb_idma_backend_${name_uniqueifier}/i_idma_backend/busy_o +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 150 +configure wave -valuecolwidth 427 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {1121282 ps} {1235722 ps} diff --git a/test/Bender.yml b/test/Bender.yml deleted file mode 100644 index 90200e1e..00000000 --- a/test/Bender.yml +++ /dev/null @@ -1,42 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -package: - name: tb_idma_backend - authors: - - "Tobias Senti " - -dependencies: - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.26.0 } - axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0-beta.3 } - register_interface: { git: "https://github.com/TheMightyDuckOfDoom/register_interface.git", rev: master } - idma_pkg: { path: ../src/package } - -export_include_dirs: - - include - -sources: - - target: test - defines: - TARGET_SIMULATION: ~ - include_dirs: - - ../src/include - files: - # Level 0: - - idma_intf.sv - - idma_tb_per2axi.sv - - idma_obi_asserter.sv - - TLToAXI4.v - # Level 1: - - idma_test.sv - - idma_obi2axi_bridge.sv - - idma_tilelink2axi_bridge.sv - - - target: test # 64bit descriptor frontend - include_dirs: - - ../src/include - files: - # Level 0 - - ../src/frontends/desc64/idma_desc64_reg_pkg.sv - # Level 1 - - frontends/tb_idma_desc64_top.sv diff --git a/test/frontends/tb_idma_desc64_top.sv b/test/frontends/tb_idma_desc64_top.sv index c4714ef1..1ddfbf3b 100644 --- a/test/frontends/tb_idma_desc64_top.sv +++ b/test/frontends/tb_idma_desc64_top.sv @@ -2,7 +2,8 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// Axel Vanoni +// Authors: +// - Axel Vanoni `include "register_interface/typedef.svh" `include "register_interface/assign.svh" diff --git a/test/idma_intf.sv b/test/idma_intf.sv index 8df84d38..b3f06b5e 100644 --- a/test/idma_intf.sv +++ b/test/idma_intf.sv @@ -1,8 +1,9 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz + +// Authors: +// - Thomas Benz `include "idma/typedef.svh" diff --git a/test/idma_obi2axi_bridge.sv b/test/idma_obi2axi_bridge.sv index a3bce89c..c0b07686 100644 --- a/test/idma_obi2axi_bridge.sv +++ b/test/idma_obi2axi_bridge.sv @@ -1,8 +1,9 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Tobias Senti module idma_obi2axi_bridge #( parameter int unsigned DataWidth = 32, diff --git a/test/idma_obi_asserter.sv b/test/idma_obi_asserter.sv index cf01dbfd..ff42e21f 100644 --- a/test/idma_obi_asserter.sv +++ b/test/idma_obi_asserter.sv @@ -1,8 +1,9 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Tobias Senti `include "common_cells/assertions.svh" diff --git a/test/idma_tb_per2axi.sv b/test/idma_tb_per2axi.sv index 472f3cf8..4487068a 100644 --- a/test/idma_tb_per2axi.sv +++ b/test/idma_tb_per2axi.sv @@ -527,8 +527,8 @@ module idma_tb_per2axi_req_channel #( input logic per_slave_req_i, input logic [PER_ADDR_WIDTH-1:0] per_slave_add_i, input logic per_slave_we_i, - input logic [ 31:0] per_slave_wdata_i, - input logic [ 3:0] per_slave_be_i, + input logic [AXI_DATA_WIDTH-1:0] per_slave_wdata_i, + input logic [AXI_STRB_WIDTH-1:0] per_slave_be_i, input logic [ PER_ID_WIDTH-1:0] per_slave_id_i, output logic per_slave_gnt_o, output logic axi_master_aw_valid_o, @@ -590,22 +590,20 @@ module idma_tb_per2axi_req_channel #( axi_master_ar_valid_o = 1'b1; end end - assign axi_master_aw_addr_o = per_slave_add_i; - assign axi_master_ar_addr_o = per_slave_add_i; - assign axi_master_aw_id_o = per_slave_id_i; - assign axi_master_ar_id_o = per_slave_id_i; - assign axi_master_w_data_o = per_slave_wdata_i; - assign axi_master_w_strb_o = per_slave_be_i; - assign per_slave_gnt_o = axi_master_aw_ready_i && axi_master_ar_ready_i && axi_master_w_ready_i; - always_comb begin - axi_master_ar_size_o = 3'b010; - axi_master_aw_size_o = 3'b010; - end - assign axi_master_aw_burst_o = 2'b01; - assign axi_master_ar_burst_o = 2'b01; - assign trans_req_o = axi_master_ar_valid_o; - assign trans_id_o = axi_master_ar_id_o; - assign trans_add_o = axi_master_ar_addr_o; + assign axi_master_aw_addr_o = per_slave_add_i; + assign axi_master_ar_addr_o = per_slave_add_i; + assign axi_master_aw_id_o = per_slave_id_i; + assign axi_master_ar_id_o = per_slave_id_i; + assign axi_master_w_data_o = per_slave_wdata_i; + assign axi_master_w_strb_o = per_slave_be_i; + assign per_slave_gnt_o = axi_master_aw_ready_i && axi_master_ar_ready_i && axi_master_w_ready_i; + assign axi_master_ar_size_o = $clog2(AXI_STRB_WIDTH); + assign axi_master_aw_size_o = $clog2(AXI_STRB_WIDTH); + assign axi_master_aw_burst_o = 2'b01; + assign axi_master_ar_burst_o = 2'b01; + assign trans_req_o = axi_master_ar_valid_o; + assign trans_id_o = axi_master_ar_id_o; + assign trans_add_o = axi_master_ar_addr_o; assign axi_master_aw_prot_o = '0; assign axi_master_aw_region_o = '0; assign axi_master_aw_len_o = '0; @@ -630,13 +628,13 @@ module idma_tb_per2axi_res_channel #( parameter AXI_USER_WIDTH = 6, parameter AXI_ID_WIDTH = 3 ) ( - input logic clk_i, - input logic rst_ni, - output logic per_slave_r_valid_o, - output logic per_slave_r_opc_o, - output logic [PER_ID_WIDTH-1:0] per_slave_r_id_o, - output logic [ 31:0] per_slave_r_rdata_o, - input logic per_slave_r_ready_i, + input logic clk_i, + input logic rst_ni, + output logic per_slave_r_valid_o, + output logic per_slave_r_opc_o, + output logic [ PER_ID_WIDTH-1:0] per_slave_r_id_o, + output logic [AXI_DATA_WIDTH-1:0] per_slave_r_rdata_o, + input logic per_slave_r_ready_i, input logic axi_master_r_valid_i, input logic [AXI_DATA_WIDTH-1:0] axi_master_r_data_i, input logic [ 1:0] axi_master_r_resp_i, @@ -649,9 +647,9 @@ module idma_tb_per2axi_res_channel #( input logic [ AXI_ID_WIDTH-1:0] axi_master_b_id_i, input logic [AXI_USER_WIDTH-1:0] axi_master_b_user_i, output logic axi_master_b_ready_o, - input logic trans_req_i, - input logic [ AXI_ID_WIDTH-1:0] trans_id_i, - input logic [AXI_ADDR_WIDTH-1:0] trans_add_i + input logic trans_req_i, + input logic [ AXI_ID_WIDTH-1:0] trans_id_i, + input logic [AXI_ADDR_WIDTH-1:0] trans_add_i ); always_comb begin per_slave_r_valid_o = '0; @@ -688,15 +686,15 @@ module idma_tb_per2axi #( input logic per_slave_req_i, input logic [PER_ADDR_WIDTH-1:0] per_slave_add_i, input logic per_slave_we_i, - input logic [ 31:0] per_slave_wdata_i, - input logic [ 3:0] per_slave_be_i, + input logic [AXI_DATA_WIDTH-1:0] per_slave_wdata_i, + input logic [AXI_STRB_WIDTH-1:0] per_slave_be_i, input logic [ PER_ID_WIDTH-1:0] per_slave_id_i, output logic per_slave_gnt_o, - output logic per_slave_r_valid_o, - output logic per_slave_r_opc_o, - output logic [PER_ID_WIDTH-1:0] per_slave_r_id_o, - output logic [ 31:0] per_slave_r_rdata_o, - input logic per_slave_r_ready_i, + output logic per_slave_r_valid_o, + output logic per_slave_r_opc_o, + output logic [ PER_ID_WIDTH-1:0] per_slave_r_id_o, + output logic [AXI_DATA_WIDTH-1:0] per_slave_r_rdata_o, + input logic per_slave_r_ready_i, output logic axi_master_aw_valid_o, output logic [AXI_ADDR_WIDTH-1:0] axi_master_aw_addr_o, output logic [ 2:0] axi_master_aw_prot_o, diff --git a/test/idma_test.sv b/test/idma_test.sv index b59d8dc6..6a03d3f3 100644 --- a/test/idma_test.sv +++ b/test/idma_test.sv @@ -1,8 +1,9 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz + +// Authors: +// - Thomas Benz `include "idma/typedef.svh" diff --git a/test/idma_tilelink2axi_bridge.sv b/test/idma_tilelink2axi_bridge.sv index c0645bd9..bbcd6b76 100644 --- a/test/idma_tilelink2axi_bridge.sv +++ b/test/idma_tilelink2axi_bridge.sv @@ -1,8 +1,9 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Tobias Senti `include "idma/guard.svh" module idma_tilelink2axi_bridge #( diff --git a/test/include/tb_tasks.svh b/test/include/tb_tasks.svh index 998687df..8a344266 100644 --- a/test/include/tb_tasks.svh +++ b/test/include/tb_tasks.svh @@ -1,8 +1,9 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz + +// Authors: +// - Thomas Benz // write a byte to the AXI-attached memory diff --git a/test/tb_idma_improved_fifo.sv b/test/tb_idma_improved_fifo.sv index c6263595..307d0483 100644 --- a/test/tb_idma_improved_fifo.sv +++ b/test/tb_idma_improved_fifo.sv @@ -1,8 +1,9 @@ // Copyright 2022 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -// -// Tobias Senti + +// Authors: +// - Tobias Senti `timescale 1ns/1ns module tb_idma_improved_fifo #( diff --git a/test/tb_idma_backend.sv.tpl b/test/tpl/tb_idma_backend.sv.tpl similarity index 99% rename from test/tb_idma_backend.sv.tpl rename to test/tpl/tb_idma_backend.sv.tpl index 8fd453dc..e6d93961 100644 --- a/test/tb_idma_backend.sv.tpl +++ b/test/tpl/tb_idma_backend.sv.tpl @@ -33,6 +33,12 @@ module tb_idma_backend${name_uniqueifier} import idma_pkg::*; #( parameter int unsigned ${database[protocol]['protocol_enum']}_MemNumReqOutst = 1, parameter int unsigned ${database[protocol]['protocol_enum']}_MemLatency = 0, % endfor + parameter bit CombinedShifter = 1'b\ +% if combined_shifter: +1, +% else: +0, +% endif parameter int unsigned WatchDogNumCycles = 100, parameter bit MaskInvalidData = 1, parameter bit RAWCouplingAvail = \ @@ -511,6 +517,7 @@ ${p}_${database[p]['write_meta_channel']}_width\ //-------------------------------------- idma_backend${name_uniqueifier} #( + .CombinedShifter ( CombinedShifter ), .DataWidth ( DataWidth ), .AddrWidth ( AddrWidth ), .AxiIdWidth ( AxiIdWidth ), diff --git a/util/.gitignore b/util/.gitignore new file mode 100644 index 00000000..bee8a64b --- /dev/null +++ b/util/.gitignore @@ -0,0 +1 @@ +__pycache__ diff --git a/util/gen_ci.py b/util/gen_ci.py index 9cc88327..bdc58b20 100644 --- a/util/gen_ci.py +++ b/util/gen_ci.py @@ -3,7 +3,8 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# Author: Thomas Benz +# Authors: +# - Thomas Benz """Generates the main CI pipeline.""" import sys diff --git a/util/gen_idma.py b/util/gen_idma.py new file mode 100644 index 00000000..57e344a4 --- /dev/null +++ b/util/gen_idma.py @@ -0,0 +1,77 @@ +#!/usr/env python3 +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Authors: +# - Tobias Senti +# - Thomas Benz + + +"""Responsible for code generation""" +import argparse +import sys + +from mario.util import prepare_ids +from mario.database import read_database +from mario.bender import render_bender +from mario.transport_layer import render_transport_layer +from mario.legalizer import render_legalizer +from mario.backend import render_backend +from mario.wave import render_vsim_wave +from mario.synth import render_synth_wrapper +from mario.testbench import render_testbench + +GENABLE_ENTITIES = ['transport', 'legalizer', 'backend', 'vsim_wave', 'testbench', 'synth_wrapper', + 'bender'] + +EPILOG = ''' +The iDMA configuration ID is composed of a underscore-separated list of specifiers and protocols. +Valid specifiers are 'r', 'w', and 'rw' indicating read, write, and bidirectional protocol +capabilities. The specifiers need to be alphabetically ordered, 'rw' is exclusive to 'r' or 'w'. +Protocols follow the specifiers and must be alphabetically ordered within the specifier class. +''' + + +def main(): + # Parse Arguments + parser = argparse.ArgumentParser( + prog='gen_idma', + description='Mario, our trusty plumber: creates parts of the iDMA given a configuration ID', + epilog=EPILOG + ) + parser.add_argument('--entity', choices=sorted(GENABLE_ENTITIES), dest='entity', required=True, + help='The entity to generate from a given configuration.') + parser.add_argument('--ids', dest='ids', nargs='*', help='configuration IDs') + parser.add_argument('--db', dest='db', nargs='*', required=True, help='Database files') + parser.add_argument('--tpl', dest='tpl', required=True, help='Template file') + args = parser.parse_args() + + # prepare database and ids + protocol_ids = prepare_ids(args.ids) + protocol_db = read_database(args.db) + + # decide what to render + if args.entity == 'bender': + print(render_bender(protocol_ids, protocol_db, args.tpl)) + elif args.entity == 'transport': + print(render_transport_layer(protocol_ids, protocol_db, args.tpl)) + elif args.entity == 'legalizer': + print(render_legalizer(protocol_ids, protocol_db, args.tpl)) + elif args.entity == 'backend': + print(render_backend(protocol_ids, protocol_db, args.tpl)) + elif args.entity == 'vsim_wave': + print(render_vsim_wave(protocol_ids, protocol_db, args.tpl)) + elif args.entity == 'synth_wrapper': + print(render_synth_wrapper(protocol_ids, protocol_db, args.tpl)) + elif args.entity == 'testbench': + print(render_testbench(protocol_ids, protocol_db, args.tpl)) + else: + return 1 + + # done + return 0 + + +if __name__ == '__main__': + sys.exit(main()) diff --git a/util/gen_jobs.py b/util/gen_jobs.py index c68873b2..12c08db2 100644 --- a/util/gen_jobs.py +++ b/util/gen_jobs.py @@ -3,7 +3,8 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# Author: Thomas Benz +# Authors: +# - Thomas Benz """Randomly generates job files.""" import sys @@ -43,13 +44,11 @@ # generate max transfer sizes src_tf_size = 2**random.randrange( math.log(jobs[job]['min_src_tf_len'], 2), - math.log(jobs[job]['max_src_tf_len'], 2) + 1 - ) + math.log(jobs[job]['max_src_tf_len'], 2) + 1) dst_tf_size = 2**random.randrange( math.log(jobs[job]['min_dst_tf_len'], 2), - math.log(jobs[job]['max_dst_tf_len'], 2) + 1 - ) + math.log(jobs[job]['max_dst_tf_len'], 2) + 1) # generate decoupled rw_decoupled = random.randrange(0, jobs[job]['ena_rw_decoupled'] + 1) @@ -95,7 +94,6 @@ dst_errs = sorted(random.sample(range(dst_addr, dst_addr + length + 1), k=num_dst_err)) - # assemble job file job_str += str(length) + '\n' job_str += str(hex(src_addr)) + '\n' diff --git a/util/idma_gen.py b/util/idma_gen.py deleted file mode 100644 index f22df9ba..00000000 --- a/util/idma_gen.py +++ /dev/null @@ -1,585 +0,0 @@ -#!/usr/env python3 -# Copyright 2022 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 - -# Author: Tobias Senti - -"""Responsible for code generation""" -import argparse -import os -from functools import reduce -import yaml -from yaml.loader import SafeLoader -from mako.template import Template - -database_directory='src/backend/database/' -template_directory='src/backend/src/' - -# Parse Databases -# yaml=YAML() -database={} -available_protocols=[] -available_read_protocols=[] -available_write_protocols=[] -for filename in os.listdir(database_directory): - if filename.endswith('.yaml'): - # Load Database File - print('Found database: ', filename) - with open(database_directory + filename, 'r', encoding='utf-8') as f: - file = yaml.load(f, Loader=SafeLoader) - - # Check if required fields are available - if 'prefix' not in file: - raise Exception(filename, ': "prefix" not found!') - - if 'protocol_enum' not in file: - raise Exception(filename, ': "protocol_enum" not found!') - - if 'full_name' not in file: - raise Exception(filename, ': "full_name" not found!') - - if 'bursts' not in file: - raise Exception(filename, ': "bursts" not found!') - - if (file['bursts'] != 'not_supported') and (file['bursts'] != 'split_at_page_boundary') and (file['bursts'] != 'only_pow2'): - raise Exception(filename, '"bursts" must either be "not_supported"\ - "split_at_page_boundary" or "only_pow2"') - - if (file['bursts'] == 'split_at_page_boundary') and ('max_beats_per_burst' not in file): - raise Exception(filename, 'if "bursts" != "not_supported",\ - then the "max_beats_per_burst" is needed!') - - if (file['bursts'] != 'not_supported') and ('page_size' not in file): - raise Exception(filename, '"page_size" not found!') - - if 'typedefs' not in file: - raise Exception(filename, ': "typedefs" not found!') - - if ('read_template' not in file) and ('write_template' not in file): - raise Exception(filename, 'Database must atleast include a\ - "read_template" or a "write_template"') - - if ('read_template' in file) and ('read_meta_channel' not in file): - raise Exception(filename, ': "read_meta_channel" not found!') - - if ('read_template' in file) and ('meta_channel_width' not in file) and ('read_meta_channel_width' not in file): - raise Exception(filename, ': "read_meta_channel_width" not found!') - - if ('read_template' in file) and ('synth_wrapper_ports_read' not in file): - raise Exception(filename, ': "synth_wrapper_ports_read" not found!') - - if ('read_template' in file) and ('synth_wrapper_assign_read' not in file): - raise Exception(filename, ': "synth_wrapper_assign_read" not found!') - - if ('write_template' in file) and ('write_meta_channel' not in file): - raise Exception(filename, ': "write_meta_channel" not found!') - - if ('write_template' in file) and ('meta_channel_width' not in file) and ('write_meta_channel_width' not in file): - raise Exception(filename, ': "write_meta_channel_width" not found!') - - if ('write_template' in file) and ('synth_wrapper_ports_write' not in file): - raise Exception(filename, ': "synth_wrapper_ports_write" not found!') - - if ('write_template' in file) and ('synth_wrapper_assign_write' not in file): - raise Exception(filename, ': "synth_wrapper_assign_write" not found!') - - prefix = file['prefix'] - - if (prefix != 'axi') and ('write_template' in file) and ('bridge_template' not in file) and ('write_bridge_template' not in file): - raise Exception(filename, ': "write_bridge_template" or "bridge_template" not found!') - - if (prefix != 'axi') and ('read_template' in file) and ('bridge_template' not in file) and ('read_bridge_template' not in file): - raise Exception(filename, ': "read_bridge_template" or "bridge_template" not found!') - - database[prefix] = file - if 'read_slave' not in file: - database[prefix]['read_slave'] = "false"; - database[prefix]['typedefs'] = ' '\ - + database[prefix]['typedefs'].replace('\n', '\n ') - if 'read_template' in file: - available_read_protocols.append(prefix) - if 'write_template' in file: - available_write_protocols.append(prefix) - - available_protocols.append(prefix) - -def generate_transport_layer(): - """Generate Transport Layer""" - # Render Read Ports - print('Generating Read Ports...') - rendered_read_ports={} - for rp in used_read_protocols: - read_port_context={ - 'database': database, - 'req_t': rp + '_read_req_t' if database[rp]['read_slave'] == 'true' else rp + '_req_t', - 'rsp_t': rp + '_read_rsp_t' if database[rp]['read_slave'] == 'true' else rp + '_rsp_t', - 'r_dp_valid_i': 'r_dp_valid_i' if one_read_port else '(r_dp_req_i.src_protocol\ - == idma_pkg::' + database[rp]['protocol_enum'] + ') && r_dp_valid_i', - 'r_dp_ready_o': 'r_dp_ready_o' if one_read_port else rp + '_r_dp_ready', - 'r_dp_rsp_o': 'r_dp_rsp_o' if one_read_port else rp + '_r_dp_rsp', - 'r_dp_valid_o': 'r_dp_valid_o' if one_read_port else rp + '_r_dp_valid', - 'r_dp_ready_i': 'r_dp_ready_i' if one_read_port else '(r_dp_req_i.src_protocol\ - == idma_pkg::' + database[rp]['protocol_enum'] + ') && r_dp_ready_i', - 'read_meta_request': 'ar_req_i' if one_read_port else 'ar_req_i.ar_req', - 'read_meta_valid': 'ar_valid_i' if one_read_port else '(ar_req_i.src_protocol\ - == idma_pkg::' + database[rp]['protocol_enum'] + ') && ar_valid_i', - 'read_meta_ready': 'ar_ready_o' if one_read_port else rp + '_ar_ready', - 'read_request': rp + '_read_req_o', - 'read_response': rp + '_read_rsp_i', - 'r_chan_valid': 'r_chan_valid_o' if one_read_port else rp + '_r_chan_valid', - 'r_chan_ready': 'r_chan_ready_o' if one_read_port else rp + '_r_chan_ready', - 'buffer_in': 'buffer_in' if one_read_port else rp + '_buffer_in', - 'buffer_in_valid': 'buffer_in_valid' if one_read_port else rp + '_buffer_in_valid', - } - database[rp]['read_template'] = ' '\ - + database[rp]['read_template'].replace('\n', '\n ') - database[rp]['read_template'] = database[rp]['read_template'][:-5] - rp_template = Template(database[rp]['read_template']) - rendered_read_ports[rp] = rp_template.render(**read_port_context) - - # Render Write Ports - print('Generating Write Ports...') - rendered_write_ports={} - for wp in used_write_protocols: - write_port_context={ - 'database': database, - 'req_t': wp + '_write_req_t' if database[wp]['read_slave'] == 'true' else wp + '_req_t', - 'rsp_t': wp + '_write_rsp_t' if database[wp]['read_slave'] == 'true' else wp + '_rsp_t', - 'w_dp_valid_i': 'w_dp_valid_i' if one_write_port else 'w_dp_req_valid &&\n \ - (w_dp_req_i.dst_protocol == idma_pkg::' + database[wp]['protocol_enum'] + ')', - 'w_dp_ready_o': 'w_dp_ready_o' if one_write_port else wp + '_w_dp_ready', - 'w_dp_rsp_o': 'w_dp_rsp_o' if one_write_port else wp + '_w_dp_rsp', - 'w_dp_valid_o': 'w_dp_valid_o' if one_write_port else wp + '_w_dp_rsp_valid', - 'w_dp_ready_i': 'w_dp_ready_i' if one_write_port else wp + '_w_dp_rsp_ready', - 'write_meta_request': 'aw_req_i' if one_write_port else 'aw_req_i.aw_req', - 'write_meta_valid': 'aw_valid_i' if one_write_port else '(aw_req_i.dst_protocol\ - == idma_pkg::' + database[wp]['protocol_enum'] + ') && aw_valid_i', - 'write_meta_ready': 'aw_ready_o' if one_write_port else wp + '_aw_ready', - 'write_request': wp + '_write_req_o', - 'write_response': wp + '_write_rsp_i', - 'buffer_out': 'buffer_out' if combined_shifter else 'buffer_out_shifted', - 'buffer_out_valid': 'buffer_out_valid' if combined_shifter - else 'buffer_out_valid_shifted', - 'buffer_out_ready': 'buffer_out_ready' if one_write_port - else wp + '_buffer_out_ready' - } - database[wp]['write_template'] = ' '\ - + database[wp]['write_template'].replace('\n', '\n ') - database[wp]['write_template'] = database[wp]['write_template'][:-5] - wp_template = Template(database[wp]['write_template']) - rendered_write_ports[wp] = wp_template.render(**write_port_context) - - # Render Transport Layer - print('Generating Transport Layer...') - tl_context={ - 'name_uniqueifier': name_uniqueifier, - 'database': database, - 'used_read_protocols': used_read_protocols, - 'used_write_protocols': used_write_protocols, - 'used_protocols': used_protocols, - 'one_read_port': one_read_port, - 'one_write_port': one_write_port, - 'rendered_read_ports': rendered_read_ports, - 'rendered_write_ports': rendered_write_ports, - 'combined_shifter': combined_shifter - } - tl_template = Template(filename=template_directory + 'idma_transport_layer.sv.tpl') - rendered_tl = tl_template.render(**tl_context) - - tl_filename = 'src/backend/backend' + name_uniqueifier - tl_filename += '/idma_transport_layer' + name_uniqueifier + '.sv' - - with open(tl_filename, 'w', encoding='utf-8') as tl_file: - tl_file.write(rendered_tl) - - print('Generated ' + tl_filename + '!') - -def generate_legalizer(): - """Generate Legalizer""" - # Render Legalizer - print('Generating Legalizer...') - le_context={ - 'name_uniqueifier': name_uniqueifier, - 'database': database, - 'used_read_protocols': used_read_protocols, - 'used_write_protocols': used_write_protocols, - 'used_protocols': used_protocols, - 'one_read_port': one_read_port, - 'one_write_port': one_write_port, - 'no_read_bursting': reduce(lambda a, b: a and b, - map(lambda p: database[p]['bursts'] == 'not_supported', used_read_protocols)), - 'no_write_bursting': reduce(lambda a, b: a and b, - map(lambda p: database[p]['bursts'] == 'not_supported', used_write_protocols)), - 'used_non_bursting_write_protocols' : list(filter( - lambda a: database[a]['bursts'] == 'not_supported', used_write_protocols)), - 'used_non_bursting_read_protocols' : list(filter( - lambda a: database[a]['bursts'] == 'not_supported', used_read_protocols)), - 'combined_shifter': combined_shifter - } - le_template = Template(filename=template_directory + 'idma_legalizer.sv.tpl') - rendered_le = le_template.render(**le_context) - - le_filename = 'src/backend/backend' + name_uniqueifier - le_filename += '/idma_legalizer' + name_uniqueifier + '.sv' - - with open(le_filename, 'w', encoding='utf-8') as le_file: - le_file.write(rendered_le) - - print('Generated ' + le_filename + '!') - -def generate_backend(): - """Generate Backend""" - # Render Backend - print('Generating Backend...') - be_context={ - 'name_uniqueifier': name_uniqueifier, - 'database': database, - 'used_read_protocols': used_read_protocols, - 'used_write_protocols': used_write_protocols, - 'used_protocols': used_protocols, - 'one_read_port': one_read_port, - 'one_write_port': one_write_port, - 'no_write_bursting': reduce(lambda a, b: a and b, - map(lambda p: database[p]['bursts'] == 'not_supported', used_write_protocols)), - 'used_non_bursting_write_protocols' : list(filter( - lambda a: database[a]['bursts'] == 'not_supported', used_write_protocols)), - 'combined_aw_and_w': len(list(filter( - lambda a: ('combined_aw_and_w' in database[a]) - and (database[a]['combined_aw_and_w'] == 'true'), used_write_protocols))) == 1 - } - be_template = Template(filename=template_directory + 'idma_backend.sv.tpl') - rendered_be = be_template.render(**be_context) - - be_filename ='src/backend/backend' + name_uniqueifier - be_filename += '/idma_backend' + name_uniqueifier + '.sv' - - with open(be_filename, 'w', encoding='utf-8') as be_file: - be_file.write(rendered_be) - - print('Generated ' + be_filename + '!') - -def generate_wave_file(): - """Generate Wave File""" - # Render Wave File - print('Generating Wave File...') - wf_context={ - 'name_uniqueifier': name_uniqueifier, - 'database': database, - 'used_read_protocols': used_read_protocols, - 'used_write_protocols': used_write_protocols, - 'used_protocols': used_protocols, - 'one_read_port': one_read_port, - 'one_write_port': one_write_port - } - wf_template = Template(filename='./scripts/waves/vsim_backend.do.tpl') - rendered_wf = wf_template.render(**wf_context) - - wf_filename = './scripts/waves/vsim_backend' + name_uniqueifier + '.do' - - with open(wf_filename, 'w', encoding='utf-8') as wf_file: - wf_file.write(rendered_wf) - - print('Generated ' + wf_filename + '!') - -def generate_testbench(): - """Generate Testbench""" - # Render Bridges - for protocol in used_protocols: - if protocol != 'axi': - if 'bridge_template' in database[protocol]: - database[protocol]['bridge_template'] = ' '\ - + database[protocol]['bridge_template'].replace('\n', '\n ') - if 'write_bridge_template' in database[protocol]: - database[protocol]['write_bridge_template'] = ' '\ - + database[protocol]['write_bridge_template'].replace('\n', '\n ') - if 'read_bridge_template' in database[protocol]: - database[protocol]['read_bridge_template'] = ' '\ - + database[protocol]['read_bridge_template'].replace('\n', '\n ') - - print('Generating read bridges...') - rendered_read_bridges={} - for protocol in used_read_protocols: - if protocol != 'axi': - bridge_context={ - 'port': 'read', - 'database': database, - 'used_read_protocols': used_read_protocols - } - if 'read_bridge_template' in database[protocol]: - bridge_template=Template(database[protocol]['read_bridge_template']) - else: - bridge_template=Template(database[protocol]['bridge_template']) - rendered_read_bridges[protocol]=bridge_template.render(**bridge_context) - - print('Generating write bridges...') - rendered_write_bridges={} - for protocol in used_write_protocols: - if protocol != 'axi': - bridge_context={ - 'port': 'write', - 'database': database, - 'used_write_protocols': used_write_protocols - } - if 'write_bridge_template' in database[protocol]: - bridge_template=Template(database[protocol]['write_bridge_template']) - else: - bridge_template=Template(database[protocol]['bridge_template']) - rendered_write_bridges[protocol]=bridge_template.render(**bridge_context) - - # Render Testbench - - print('Generating Testbench...') - tb_context={ - 'name_uniqueifier': name_uniqueifier, - 'database': database, - 'used_read_protocols': used_read_protocols, - 'used_write_protocols': used_write_protocols, - 'used_protocols': used_protocols, - 'unused_protocols': list(set(available_protocols) - set(used_protocols)), - 'one_read_port': one_read_port, - 'one_write_port': one_write_port, - 'rendered_read_bridges': rendered_read_bridges, - 'rendered_write_bridges': rendered_write_bridges - } - tb_template = Template(filename='test/tb_idma_backend.sv.tpl') - rendered_tb = tb_template.render(**tb_context) - - tb_filename = 'src/backend/backend' + name_uniqueifier - tb_filename += '/tb_idma_backend' + name_uniqueifier + '.sv' - - with open(tb_filename, 'w', encoding='utf-8') as tb_file: - tb_file.write(rendered_tb) - - print('Generated ' + tb_filename + '!') - -def generate_synth_wrapper(): - """Generate Synth Wrapper""" - # Render Wave File - print('Generating Synth Wrapper...') - sw_context={ - 'name_uniqueifier': name_uniqueifier, - 'database': database, - 'used_read_protocols': used_read_protocols, - 'used_write_protocols': used_write_protocols, - 'used_protocols': used_protocols, - 'one_read_port': one_read_port, - 'one_write_port': one_write_port - } - for protocol in used_protocols: - if protocol in used_read_protocols: - database[protocol]['synth_wrapper_ports_read'] = ' '\ - + database[protocol]['synth_wrapper_ports_read'].replace('\n', '\n ') - database[protocol]['synth_wrapper_assign_read'] = ' '\ - + database[protocol]['synth_wrapper_assign_read'].replace('\n', '\n ') - if protocol in used_write_protocols: - database[protocol]['synth_wrapper_ports_write'] = ' '\ - + database[protocol]['synth_wrapper_ports_write'].replace('\n', '\n ') - database[protocol]['synth_wrapper_assign_write'] = ' '\ - + database[protocol]['synth_wrapper_assign_write'].replace('\n', '\n ') - sw_template = Template(filename='src/backend/src/idma_backend_synth.sv.tpl') - rendered_sw = sw_template.render(**sw_context) - - sw_filename = 'src/backend/backend' + name_uniqueifier - sw_filename += '/idma_backend_synth' + name_uniqueifier + '.sv' - - with open(sw_filename, 'w', encoding='utf-8') as sw_file: - sw_file.write(rendered_sw) - - print('Generated ' + sw_filename + '!') - -def generate_folder(): - """Generates the folder where all generated files will live""" - try: - os.mkdir('src/backend/backend' + name_uniqueifier) - except FileExistsError: - pass - -def generate_bender(): - """Generates src/backend/Bender.yml""" - # Check if file exists - if not os.path.isfile('src/backend/Bender.yml'): - # If not -> Write template into it - with open('src/backend/Bender.yml.tpl', 'r', encoding='utf-8') as template_file: - content = template_file.read() - else: - # Read contents of bender file - with open('src/backend/Bender.yml', 'r', encoding='utf-8') as bender_file: - content = bender_file.read() - - # Check if backend is already in bender file - if name_uniqueifier not in content: - # Add new backend - content += '\n # backend' + name_uniqueifier + '\n' - content += ' - files:\n' - content += ' - backend' + name_uniqueifier - content += '/idma_transport_layer' + name_uniqueifier + '.sv\n' - content += ' - backend' + name_uniqueifier + '/idma_legalizer' + name_uniqueifier + '.sv\n' - content += ' - backend' + name_uniqueifier + '/idma_backend' + name_uniqueifier + '.sv\n' - content += ' - target: test\n' - content += ' defines:\n' - content += ' TARGET_SIMULATION: ~\n' - content += ' include_dirs:\n' - content += ' - ../../test\n' - content += ' files:\n' - content += ' - backend' + name_uniqueifier + '/tb_idma_backend' + name_uniqueifier + '.sv\n' - content += ' - target: synthesis\n' - content += ' files:\n' - content += ' - backend' + name_uniqueifier + '/idma_backend_synth' - content += name_uniqueifier + '.sv\n' - - # Write bender file - with open('src/backend/Bender.yml', 'w', encoding='utf-8') as bender_file: - bender_file.write(content) - -# Parse Arguments -parser = argparse.ArgumentParser( - prog='idma_gen', - description='Generates a wanted iDMA configuration' -) -subparser = parser.add_subparsers(dest='command') - -gen_tl = subparser.add_parser('transportlayer', description='Generates the transport layer') -gen_tl.add_argument('-r', '--read-protocols', choices=available_read_protocols, - type=str, required=True, nargs='+', dest='read_protocols') -gen_tl.add_argument('-w', '--write-protocols', choices=available_write_protocols, - type=str, required=True, nargs='+', dest='write_protocols') -gen_tl.add_argument('-s', '--shifter', choices=['combined', 'split'], - type=str, required=False, default='split', dest='shifter') - -gen_le = subparser.add_parser('legalizer', description='Generates the legalizer') -gen_le.add_argument('-r', '--read-protocols', choices=available_read_protocols, - type=str, required=True, nargs='+', dest='read_protocols') -gen_le.add_argument('-w', '--write-protocols', choices=available_write_protocols, - type=str, required=True, nargs='+', dest='write_protocols') -gen_le.add_argument('-s', '--shifter', choices=['combined', 'split'], - type=str, required=False, default='split', dest='shifter') - -gen_be = subparser.add_parser('backend', description='Generates the backend') -gen_be.add_argument('-r', '--read-protocols', choices=available_read_protocols, - type=str, required=True, nargs='+', dest='read_protocols') -gen_be.add_argument('-w', '--write-protocols', choices=available_write_protocols, - type=str, required=True, nargs='+', dest='write_protocols') -gen_be.add_argument('-s', '--shifter', choices=['combined', 'split'], - type=str, required=False, default='split', dest='shifter') - -gen_wf = subparser.add_parser('wavefile', description='Generates a .do wavefile for debugging in vsim') -gen_wf.add_argument('-r', '--read-protocols', choices=available_read_protocols, - type=str, required=True, nargs='+', dest='read_protocols') -gen_wf.add_argument('-w', '--write-protocols', choices=available_write_protocols, - type=str, required=True, nargs='+', dest='write_protocols') -gen_wf.add_argument('-s', '--shifter', choices=['combined', 'split'], - type=str, required=False, default='split', dest='shifter') - -gen_tb = subparser.add_parser('testbench', description='Generates the testbench') -gen_tb.add_argument('-r', '--read-protocols', choices=available_read_protocols, - type=str, required=True, nargs='+', dest='read_protocols') -gen_tb.add_argument('-w', '--write-protocols', choices=available_write_protocols, - type=str, required=True, nargs='+', dest='write_protocols') -gen_tb.add_argument('-s', '--shifter', choices=['combined', 'split'], - type=str, required=False, default='split', dest='shifter') - -gen_sw = subparser.add_parser('synth_wrapper', description='Generates the synthesis wrapper') -gen_sw.add_argument('-r', '--read-protocols', choices=available_read_protocols, - type=str, required=True, nargs='+', dest='read_protocols') -gen_sw.add_argument('-w', '--write-protocols', choices=available_write_protocols, - type=str, required=True, nargs='+', dest='write_protocols') -gen_sw.add_argument('-s', '--shifter', choices=['combined', 'split'], - type=str, required=False, default='split', dest='shifter') - -gen_bd = subparser.add_parser('bender', description='Generates the bender file') -gen_bd.add_argument('-r', '--read-protocols', choices=available_read_protocols, - type=str, required=True, nargs='+', dest='read_protocols') -gen_bd.add_argument('-w', '--write-protocols', choices=available_write_protocols, - type=str, required=True, nargs='+', dest='write_protocols') -gen_bd.add_argument('-s', '--shifter', choices=['combined', 'split'], - type=str, required=False, default='split', dest='shifter') - -gen_all = subparser.add_parser('debug', description='Generates all required file for debugging: TransportLayer, Legalizer, Backend, Testbench, Bender, Wavefile') -gen_all.add_argument('-r', '--read-protocols', choices=available_read_protocols, - type=str, required=True, nargs='+', dest='read_protocols') -gen_all.add_argument('-w', '--write-protocols', choices=available_write_protocols, - type=str, required=True, nargs='+', dest='write_protocols') -gen_all.add_argument('-s', '--shifter', choices=['combined', 'split'], - type=str, required=False, default='split', dest='shifter') - - -args = parser.parse_args() - -used_read_protocols=[] -used_write_protocols=[] -if 'read_protocols' in args: - args.read_protocols.sort() - used_read_protocols=list(set(args.read_protocols)) -if 'write_protocols' in args: - args.write_protocols.sort() - used_write_protocols=list(set(args.write_protocols)) - -used_protocols=list(set(used_read_protocols + used_write_protocols)) - -used_read_protocols.sort() -used_write_protocols.sort() -used_protocols.sort() - -print('Read Protocols: ', used_read_protocols) -print('Write Protocols: ', used_write_protocols) -print('Used Protocols: ', used_protocols) - -one_read_port = len(used_read_protocols) == 1 -one_write_port = len(used_write_protocols) == 1 - -# Create Unique name -name_uniqueifier='' -for up in used_protocols: - name_uniqueifier += '_' - if up in used_read_protocols: - name_uniqueifier += 'r' - if up in used_write_protocols: - name_uniqueifier += 'w' - name_uniqueifier += '_' + up -name_uniqueifier += '_' -if ('shifter' in args) and ('split' in args.shifter): - name_uniqueifier += 'split' -else: - name_uniqueifier += 'combined' - -if args.command == 'transportlayer': - combined_shifter=args.shifter == 'combined' - generate_folder() - generate_transport_layer() - -if args.command == 'legalizer': - combined_shifter=args.shifter == 'combined' - generate_folder() - generate_legalizer() - -if args.command == 'backend': - combined_shifter=args.shifter == 'combined' - generate_folder() - generate_backend() - -if args.command == 'wavefile': - generate_wave_file() - -if args.command == 'testbench': - combined_shifter=args.shifter == 'combined' - generate_folder() - generate_testbench() - -if args.command == 'synth_wrapper': - generate_folder() - generate_synth_wrapper() - -if args.command == 'bender': - combined_shifter=args.shifter == 'combined' - generate_bender() - -if args.command == 'debug': - combined_shifter=args.shifter == 'combined' - generate_bender() - generate_folder() - generate_transport_layer() - generate_legalizer() - generate_backend() - generate_testbench() - generate_wave_file() \ No newline at end of file diff --git a/util/licence-checker.hjson b/util/licence-checker.hjson deleted file mode 100644 index c29b08f3..00000000 --- a/util/licence-checker.hjson +++ /dev/null @@ -1,27 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -{ - // We cover ETH Zurich and lowRISC licenses and Apache 2.0 (mostly for SW) - // and Solderpad for the hardware. - licence: - ''' - Copyright (\d{4}(-\d{4})?\s)?(ETH Zurich and University of Bologna|lowRISC contributors). - (Solderpad Hardware License, Version 0.51|Licensed under the Apache License, Version 2.0), see LICENSE for details. - SPDX-License-Identifier: (SHL-0.51|Apache-2.0) - ''', - match_regex: 'true', - exclude_paths: [ - # Exclude anything in vendored directories - 'util/lowrisc_misc-linters/*', - // Generated by reggen - 'src/frontends/register_32bit_2d/idma_reg32_2d_frontend.h', - 'src/frontends/register_32bit_2d/idma_reg32_2d_frontend.sv', - 'src/frontends/register_64bit/idma_reg64_frontend.h', - 'src/frontends/register_64bit/idma_reg64_frontend.sv', - 'src/frontends/register_64bit_2d/idma_reg64_2d_frontend.h', - 'src/frontends/desc64/idma_desc64_frontend.h', - 'src/systems/cva6_reg/driver/encoding.h', - 'scripts/waves/*' - ], -} diff --git a/util/list-contributors.py b/util/list-contributors.py index 5c7d9c0a..794e048c 100644 --- a/util/list-contributors.py +++ b/util/list-contributors.py @@ -2,6 +2,9 @@ # Copyright 2022 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 +# +# Authors: +# - Thomas Benz """List the amount of lines every contributor adds, and their files""" import sys diff --git a/util/list-todos.py b/util/list-todos.py index aabc25f7..3a14eccd 100644 --- a/util/list-todos.py +++ b/util/list-todos.py @@ -3,6 +3,9 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 +# Authors: +# - Thomas Benz + """List the amount of lines every contributor adds, and their files""" import sys import glob @@ -51,7 +54,7 @@ if re.search(to_check, line, re.IGNORECASE): todo_present |= True global_todo_present |= True - if not author in num_todos: + if author not in num_todos: num_todos[author] = 1 else: num_todos[author] += 1 diff --git a/util/lowrisc_misc-linters/CONTRIBUTING.md b/util/lowrisc_misc-linters/CONTRIBUTING.md deleted file mode 100644 index fa837d9d..00000000 --- a/util/lowrisc_misc-linters/CONTRIBUTING.md +++ /dev/null @@ -1,48 +0,0 @@ -# Contributing code to the misc-linters repository - -## Contributor License Agreement - -Contributions to misc-linters must be accompanied by sign-off text that indicates -acceptance of the Contributor License Agreement (see [CLA](CLA) for full -text), which is closely derived from the Apache Individual Contributor License -Agreement. The sign-off text must be included once per commit, in the commit -message. The sign-off can be automatically inserted using a command such as -`git commit -s`, which will generate the text in the form: -`Signed-off-by: Random J Developer ` - -By adding this sign-off, you are certifying: - -_By signing-off on this submission, I agree to be bound by the terms of the -Contributor License Agreement located at the root of the project repository, -and I agree that this submission constitutes a "Contribution" under that -Agreement._ - -Please note that this project and any contributions to it are public and that -a record of all contributions (including any personal information submitted -with it, including a sign-off) is maintained indefinitely and may be -redistributed consistent with this project or the open source license(s) -involved. - -## Quick guidelines - -* Keep a clean commit history. This means no merge commits, and no long series - of "fixup" patches (rebase or squash as appropriate). Structure work as a - series of logically ordered, atomic patches. `git rebase -i` is your friend. -* Changes should be made via pull request, with review. Do not commit until - you've had an explicit "looks good to me". We don't yet have, but plan to - create a policy describing code owners and the like. In the meantime use your - best judgement. If you're submitting a change against something that was 90% - authored by a single person, you'll want to get their ACK before committing. -* When changes are restricted to a specific area, you are recommended to add a - tag to the beginning of the first line of the commit message in square - brackets. e.g. "[UART] Fix bug #157". -* Code review is not design review and doesn't remove the need for discussing - implementation options. If you would like to make a large-scale change or - discuss multiple implementation options, discuss on the mailing list. -* Create pull requests from a fork rather than making new branches in - `github.com/lowrisc/misc-linters`. -* Do not force push. -* Do not attempt to commit code with a non-Apache license without discussing - first. -* If a relevant bug or tracking issue exists, reference it in the pull request - and commits. diff --git a/util/lowrisc_misc-linters/LICENSE b/util/lowrisc_misc-linters/LICENSE deleted file mode 100644 index d6456956..00000000 --- a/util/lowrisc_misc-linters/LICENSE +++ /dev/null @@ -1,202 +0,0 @@ - - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. Definitions. - - "License" shall mean the terms and conditions for use, reproduction, - and distribution as defined by Sections 1 through 9 of this document. - - "Licensor" shall mean the copyright owner or entity authorized by - the copyright owner that is granting the License. - - "Legal Entity" shall mean the union of the acting entity and all - other entities that control, are controlled by, or are under common - control with that entity. For the purposes of this definition, - "control" means (i) the power, direct or indirect, to cause the - direction or management of such entity, whether by contract or - otherwise, or (ii) ownership of fifty percent (50%) or more of the - outstanding shares, or (iii) beneficial ownership of such entity. - - "You" (or "Your") shall mean an individual or Legal Entity - exercising permissions granted by this License. - - "Source" form shall mean the preferred form for making modifications, - including but not limited to software source code, documentation - source, and configuration files. - - "Object" form shall mean any form resulting from mechanical - transformation or translation of a Source form, including but - not limited to compiled object code, generated documentation, - and conversions to other media types. - - "Work" shall mean the work of authorship, whether in Source or - Object form, made available under the License, as indicated by a - copyright notice that is included in or attached to the work - (an example is provided in the Appendix below). - - "Derivative Works" shall mean any work, whether in Source or Object - form, that is based on (or derived from) the Work and for which the - editorial revisions, annotations, elaborations, or other modifications - represent, as a whole, an original work of authorship. For the purposes - of this License, Derivative Works shall not include works that remain - separable from, or merely link (or bind by name) to the interfaces of, - the Work and Derivative Works thereof. - - "Contribution" shall mean any work of authorship, including - the original version of the Work and any modifications or additions - to that Work or Derivative Works thereof, that is intentionally - submitted to Licensor for inclusion in the Work by the copyright owner - or by an individual or Legal Entity authorized to submit on behalf of - the copyright owner. For the purposes of this definition, "submitted" - means any form of electronic, verbal, or written communication sent - to the Licensor or its representatives, including but not limited to - communication on electronic mailing lists, source code control systems, - and issue tracking systems that are managed by, or on behalf of, the - Licensor for the purpose of discussing and improving the Work, but - excluding communication that is conspicuously marked or otherwise - designated in writing by the copyright owner as "Not a Contribution." - - "Contributor" shall mean Licensor and any individual or Legal Entity - on behalf of whom a Contribution has been received by Licensor and - subsequently incorporated within the Work. - - 2. Grant of Copyright License. Subject to the terms and conditions of - this License, each Contributor hereby grants to You a perpetual, - worldwide, non-exclusive, no-charge, royalty-free, irrevocable - copyright license to reproduce, prepare Derivative Works of, - publicly display, publicly perform, sublicense, and distribute the - Work and such Derivative Works in Source or Object form. - - 3. Grant of Patent License. Subject to the terms and conditions of - this License, each Contributor hereby grants to You a perpetual, - worldwide, non-exclusive, no-charge, royalty-free, irrevocable - (except as stated in this section) patent license to make, have made, - use, offer to sell, sell, import, and otherwise transfer the Work, - where such license applies only to those patent claims licensable - by such Contributor that are necessarily infringed by their - Contribution(s) alone or by combination of their Contribution(s) - with the Work to which such Contribution(s) was submitted. If You - institute patent litigation against any entity (including a - cross-claim or counterclaim in a lawsuit) alleging that the Work - or a Contribution incorporated within the Work constitutes direct - or contributory patent infringement, then any patent licenses - granted to You under this License for that Work shall terminate - as of the date such litigation is filed. - - 4. Redistribution. You may reproduce and distribute copies of the - Work or Derivative Works thereof in any medium, with or without - modifications, and in Source or Object form, provided that You - meet the following conditions: - - (a) You must give any other recipients of the Work or - Derivative Works a copy of this License; and - - (b) You must cause any modified files to carry prominent notices - stating that You changed the files; and - - (c) You must retain, in the Source form of any Derivative Works - that You distribute, all copyright, patent, trademark, and - attribution notices from the Source form of the Work, - excluding those notices that do not pertain to any part of - the Derivative Works; and - - (d) If the Work includes a "NOTICE" text file as part of its - distribution, then any Derivative Works that You distribute must - include a readable copy of the attribution notices contained - within such NOTICE file, excluding those notices that do not - pertain to any part of the Derivative Works, in at least one - of the following places: within a NOTICE text file distributed - as part of the Derivative Works; within the Source form or - documentation, if provided along with the Derivative Works; or, - within a display generated by the Derivative Works, if and - wherever such third-party notices normally appear. The contents - of the NOTICE file are for informational purposes only and - do not modify the License. You may add Your own attribution - notices within Derivative Works that You distribute, alongside - or as an addendum to the NOTICE text from the Work, provided - that such additional attribution notices cannot be construed - as modifying the License. - - You may add Your own copyright statement to Your modifications and - may provide additional or different license terms and conditions - for use, reproduction, or distribution of Your modifications, or - for any such Derivative Works as a whole, provided Your use, - reproduction, and distribution of the Work otherwise complies with - the conditions stated in this License. - - 5. Submission of Contributions. Unless You explicitly state otherwise, - any Contribution intentionally submitted for inclusion in the Work - by You to the Licensor shall be under the terms and conditions of - this License, without any additional terms or conditions. - Notwithstanding the above, nothing herein shall supersede or modify - the terms of any separate license agreement you may have executed - with Licensor regarding such Contributions. - - 6. Trademarks. This License does not grant permission to use the trade - names, trademarks, service marks, or product names of the Licensor, - except as required for reasonable and customary use in describing the - origin of the Work and reproducing the content of the NOTICE file. - - 7. Disclaimer of Warranty. Unless required by applicable law or - agreed to in writing, Licensor provides the Work (and each - Contributor provides its Contributions) on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or - implied, including, without limitation, any warranties or conditions - of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A - PARTICULAR PURPOSE. You are solely responsible for determining the - appropriateness of using or redistributing the Work and assume any - risks associated with Your exercise of permissions under this License. - - 8. Limitation of Liability. In no event and under no legal theory, - whether in tort (including negligence), contract, or otherwise, - unless required by applicable law (such as deliberate and grossly - negligent acts) or agreed to in writing, shall any Contributor be - liable to You for damages, including any direct, indirect, special, - incidental, or consequential damages of any character arising as a - result of this License or out of the use or inability to use the - Work (including but not limited to damages for loss of goodwill, - work stoppage, computer failure or malfunction, or any and all - other commercial damages or losses), even if such Contributor - has been advised of the possibility of such damages. - - 9. Accepting Warranty or Additional Liability. While redistributing - the Work or Derivative Works thereof, You may choose to offer, - and charge a fee for, acceptance of support, warranty, indemnity, - or other liability obligations and/or rights consistent with this - License. However, in accepting such obligations, You may act only - on Your own behalf and on Your sole responsibility, not on behalf - of any other Contributor, and only if You agree to indemnify, - defend, and hold each Contributor harmless for any liability - incurred by, or claims asserted against, such Contributor by reason - of your accepting any such warranty or additional liability. - - END OF TERMS AND CONDITIONS - - APPENDIX: How to apply the Apache License to your work. - - To apply the Apache License to your work, attach the following - boilerplate notice, with the fields enclosed by brackets "[]" - replaced with your own identifying information. (Don't include - the brackets!) The text should be enclosed in the appropriate - comment syntax for the file format. We also recommend that a - file or class name and description of purpose be included on the - same "printed page" as the copyright notice for easier - identification within third-party archives. - - Copyright [yyyy] [name of copyright owner] - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. diff --git a/util/lowrisc_misc-linters/README.md b/util/lowrisc_misc-linters/README.md deleted file mode 100644 index 09391eda..00000000 --- a/util/lowrisc_misc-linters/README.md +++ /dev/null @@ -1,21 +0,0 @@ -# lowRISC's Miscellaneous Linters - -## About the project - -These are linters and checkers, usually for source code, which we have written -for various lowRISC projects. - -They include -* `licence-checker/licence-checker.py` which will ensure source code in your - repository contains correctly formatted licence headers. This is designed to - be reused: it is configured with `licence-checker.hjson`. - -## How to contribute - -Have a look at [CONTRIBUTING](./CONTRIBUTING.md) for guidelines on how to -contribute code to this repository. - -## Licensing - -Unless otherwise noted, everything in this repository is covered by the Apache -License, Version 2.0 (see [LICENSE](./LICENSE) for full text). diff --git a/util/lowrisc_misc-linters/licence-checker/README.md b/util/lowrisc_misc-linters/licence-checker/README.md deleted file mode 100644 index c0a2befa..00000000 --- a/util/lowrisc_misc-linters/licence-checker/README.md +++ /dev/null @@ -1,45 +0,0 @@ -# Licence Checker - -This script can check most text file formats that we have checked our -repositories, though it has some limitations. It ensures the entire licence -appears on consecutive lines in the first comment in the file, and those lines -contain nothing else. - -The primary limitation of the checker is that each file suffix can only match -one comment style, which is used for checking for the licence header. In text -formats which accept multiple comment styles, there is now a canonical one that -the licence must use. Where available, the licence should use a line comment -style. - -The other limitation is for files where the canonical style is block comments, -like `/* */`, each line must be wrapped in the comment prefix and suffix, rather -than the whole licence header being wrapped in a single comment prefix and -suffix. This is an artefact of how the checker searches for the licence. - -The checker is configured using a hjson file, which contains the exact licence -header, and a list of file patterns to exclude from checking the licence for, -which is used to exclude vendored and other externally sourced files. -Additionally, the licence checker can be configured to use regex matching using -the `match_regex` key set to "true". - -# Configuration Example - -``` -{ - // Licence to check against. - licence: - ''' - Copyright lowRISC contributors. - Licensed under the Apache License, Version 2.0, see LICENSE for details. - SPDX-License-Identifier: Apache-2.0 - ''', - // Optionally match the licence using regex (can be left off). - // The default is not to use regex. - match_regex: 'false', - // Don't consider those paths and files when checking - // for the licence (can contain wildcards such as `*`). - exclude_paths: [ - '.style.yapf', - ], -} -``` diff --git a/util/lowrisc_misc-linters/licence-checker/licence-checker.py b/util/lowrisc_misc-linters/licence-checker/licence-checker.py deleted file mode 100755 index f830b6a9..00000000 --- a/util/lowrisc_misc-linters/licence-checker/licence-checker.py +++ /dev/null @@ -1,518 +0,0 @@ -#!/usr/bin/env python3 -# -# Copyright lowRISC contributors. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -import argparse -import fnmatch -import logging -import re -import subprocess -from pathlib import Path -from types import SimpleNamespace - -import hjson -from tabulate import tabulate - - -class LicenceHeader(object): - """Represents the licence header we want to insert""" - def __init__(self, text): - self._lines = text.strip().splitlines() - - def __getitem__(self, idx): - return self._lines.__getitem__(idx) - - def __len__(self): - return self._lines.__len__() - - def numbered_lines(self, skip=0): - """Returns an iterator of (line_no, line_text). - - `line_no` counts from 1, and is for humans to count line numbers with. - use `skip_lines` to skip enumerating the first few lines. - """ - return enumerate(self._lines[skip:], start=1 + skip) - - @property - def first_word(self): - (first_word, _) = self._lines[0].split(' ', 1) - return first_word - - -class CommentStyle: - '''Base class for comment style objects''' - def __init__(self, first_line_prefix, comment_prefix): - self.first_line_prefix = first_line_prefix - self.comment_prefix = comment_prefix - - def search_line_pattern(self, licence_first_word): - return re.compile( - re.escape(self.comment_prefix + ' ' + licence_first_word)) - - def full_line_parts(self, licence_line): - return [re.escape(self.comment_prefix), licence_line] - - def full_line_pattern(self, licence_line): - '''Returns a regex pattern which matches one line of licence text.''' - return re.compile(' '.join(self.full_line_parts(licence_line))) - - -class LineCommentStyle(CommentStyle): - """Helpers for line-style comments.""" - def __init__(self, prefix): - super().__init__(prefix, prefix) - - -class DifferentFirstLineCommentStyle(CommentStyle): - """Some files have a different allowable prefix for their first line.""" - def __init__(self, first_line_prefix, prefix): - super().__init__(first_line_prefix, prefix) - - -class BlockCommentStyle(CommentStyle): - """Helpers for block-style comments.""" - def __init__(self, prefix, suffix): - super().__init__(prefix, prefix) - self.comment_suffix = str(suffix) - - def full_line_parts(self, licence_line): - return [ - re.escape(self.comment_prefix), licence_line, - re.escape(self.comment_suffix) - ] - - -SLASH_SLASH = '//' -HASH = '#' -SLASH_STAR = '/*' - -COMMENT_STYLES = { - SLASH_SLASH: LineCommentStyle("//"), - HASH: LineCommentStyle("#"), - SLASH_STAR: BlockCommentStyle("/*", "*/"), - 'corefile': DifferentFirstLineCommentStyle("CAPI=2", "#") -} - -# (Prioritised) Mapping of file name suffixes to comment style. If the suffix -# of your file does not match one of these, it will not be checked. -# -# Each entry is a pair (suffixes, styles). suffixes is a list of file suffixes: -# if a filename matches one of these suffixes, we'll use the styles in styles. -# styles is either a string or a list of strings. If there is one or more -# strings, these strings must all be keys of COMMENT_STYLES and they give the -# different comment styles that are acceptable for the file type. -# -# These rules are given in priority order. Tuples higher in the list are -# matched before those later in the list, on purpose. -# -# Files that either do not match any extension or that have an empty list of -# styles are not checked for a licence. -COMMENT_CHARS = [ - # Hardware Files - ([".svh", ".sv", ".sv.tpl"], SLASH_SLASH), # SystemVerilog - - # Hardware Build Systems - ([".tcl", ".sdc"], HASH), # tcl - ([".core", ".core.tpl"], 'corefile'), # FuseSoC Core Files - (["Makefile", ".mk"], HASH), # Makefiles - ([".ys"], HASH), # Yosys script - ([".waiver"], HASH), # AscentLint waiver files - ([".vlt"], SLASH_SLASH), # Verilator configuration (waiver) files - ([".vbl"], HASH), # Verible configuration files - ([".el", ".el.tpl"], SLASH_SLASH), # Exclusion list - ([".cfg", ".cfg.tpl"], [SLASH_SLASH, - HASH]), # Kinds of configuration files - ([".f"], []), # File lists (not checked) - - # The following two rules will inevitably bite us. - (["riviera_run.do"], HASH), # Riviera dofile - ([".do"], SLASH_SLASH), # Cadence LEC dofile - - # Software Files - ([".c", ".c.tpl", ".h", ".h.tpl", ".cc", ".cpp", ".cc.tpl", - ".cpp.tpl"], SLASH_SLASH), # C, C++ - ([".def"], SLASH_SLASH), # C, C++ X-Include List Declaration Files - ([".S"], [SLASH_SLASH, SLASH_STAR, HASH]), # Assembly (With Preprocessing) - ([".s"], [SLASH_STAR, HASH]), # Assembly (Without Preprocessing) - ([".ld", ".ld.tpl"], SLASH_STAR), # Linker Scripts - ([".rs", ".rs.tpl"], SLASH_SLASH), # Rust - - # Software Build Systems - (["meson.build", "toolchain.txt", "meson_options.txt"], HASH), # Meson - - # General Tooling - ([".py"], HASH), # Python - ([".sh"], HASH), # Shell Scripts - (["Dockerfile"], HASH), # Dockerfiles - - # Configuration - ([".hjson", ".hjson.tpl"], SLASH_SLASH), # hjson - ([".yml", ".yaml"], HASH), # YAML - ([".toml"], HASH), # TOML - (["-requirements.txt"], HASH), # Apt and Python requirements files - (["redirector.conf"], HASH), # nginx config - - # Documentation - ([".md", ".md.tpl", ".html"], []), # Markdown and HTML (not checked) - ([".css"], SLASH_STAR), # CSS - ([".scss"], SLASH_SLASH), # SCSS - - # Templates (Last because there are overlaps with extensions above) - ([".tpl"], HASH), # Mako templates -] - - -class LicenceMatcher: - '''An object to match a given licence at the start of a file''' - def __init__(self, comment_style, licence, match_regex): - self.style = comment_style - self.expected_lines = list() - # In case we are using regex matching we can pass the full line "as is" - if match_regex: - for i, ll in enumerate(licence): - try: - self.expected_lines.append( - comment_style.full_line_pattern(ll)) - # Catch any regex error here and raise a runtime error. - except re.error as e: - raise RuntimeError( - "Can't compile line {} of the licence as a regular expression. Saw `{}`: {}" - .format(i, e.pattern[e.pos], e.msg)) - # use the "first line" as a licence marker - self.search_marker = self.expected_lines[0] - # For non-regex matching we need to escape everything. - # This can never throw an exception as everything has been escaped and - # therefore is always a legal regex. - else: - self.search_marker = comment_style.search_line_pattern( - licence.first_word) - self.expected_lines = [ - comment_style.full_line_pattern(re.escape(ll)) - for ll in licence - ] - - self.lines_left = [] - - def looks_like_first_line_comment(self, line): - return line.startswith(self.style.first_line_prefix) - - def looks_like_comment(self, line): - return line.startswith(self.style.comment_prefix) - - def looks_like_first_line(self, line): - return self.search_marker.match(line) is not None - - def start(self): - '''Reset lines_left, to match at the start of the licence''' - self.lines_left = self.expected_lines - - def take_line(self, line): - '''Check whether line matches the next line of the licence. - - Returns a pair (matched, done). matched is true if the line matched. If - this was the last line of the licence, done is true. On a match, this - increments an internal counter, so the next call to take_line will - match against the next line of the licence. - - ''' - # If we have no more lines to match, claim a match and that we're done. - # This shouldn't happen in practice, except if the configuration has an - # empty licence. - if not self.lines_left: - return (True, True) - - next_expected = self.lines_left[0] - matched = next_expected.fullmatch(line) - - if not matched: - return (False, False) - - if matched: - self.lines_left = self.lines_left[1:] - return (True, not self.lines_left) - - -def detect_comment_char(all_matchers, filename): - '''Find zero or more LicenceMatcher objects for filename - - all_matchers should be a dict like COMMENT_STYLES, but where the values are - the corresponding LicenceMatcher objects. - - ''' - found = None - for (suffixes, keys) in COMMENT_CHARS: - if found is not None: - break - for suffix in suffixes: - if filename.endswith(suffix): - found = keys - break - - if found is None: - return [] - - if not isinstance(found, list): - assert isinstance(found, str) - found = [found] - - return [all_matchers[key] for key in found] - - -def git_find_repo_toplevel(): - git_output = subprocess.check_output( - ['git', 'rev-parse', '--show-toplevel']) - return Path(git_output.decode().strip()).resolve() - - -def git_find_all_file_paths(top_level, search_paths): - git_output = subprocess.check_output( - ["git", "-C", - str(top_level), "ls-files", "-z", "--", *search_paths]) - for path in git_output.rstrip(b"\0").split(b"\0"): - yield Path(top_level, path.decode()) - - -class ResultsTracker(object): - """Helper for tracking results""" - def __init__(self, base_dir): - self.base_dir = base_dir - - passed_count = 0 - failed_count = 0 - excluded_count = 0 - skipped_count = 0 - - failing_paths = set() - - @property - def total_count(self): - return (self.passed_count + self.failed_count + self.skipped_count + - self.excluded_count) - - def passed(self, path, line_no, reason): - rel_path = path.relative_to(self.base_dir) - logging.debug("%s:%d PASSED: %s", str(rel_path), line_no, reason) - self.passed_count += 1 - - def failed(self, path, line_no, reason): - rel_path = path.relative_to(self.base_dir) - logging.error("%s:%d FAILED: %s", str(rel_path), line_no, reason) - self.failing_paths.add(rel_path) - self.failed_count += 1 - - def skipped(self, path, reason): - rel_path = path.relative_to(self.base_dir) - logging.info("%s: SKIPPED: %s", str(rel_path), reason) - self.skipped_count += 1 - - def excluded(self, path, reason): - rel_path = path.relative_to(self.base_dir) - logging.debug("%s: EXCLUDED: %s", str(rel_path), reason) - self.excluded_count += 1 - - def any_failed(self): - return self.failed_count > 0 - - def display_nicely(self): - headers = ["Results:", "Files"] - results = [["Passed", self.passed_count], - ["Failed", self.failed_count], - ["Skipped", self.skipped_count], - ["Excluded", self.excluded_count], - ["Total", self.total_count]] - - return tabulate(results, headers, tablefmt="simple") - - -def matches_exclude_pattern(config, file_path): - rel_path = str(file_path.relative_to(config.base_dir)) - for exclude_pattern in config.exclude_paths: - if fnmatch.fnmatch(rel_path, exclude_pattern): - return True - return False - - -def check_paths(config, git_paths): - results = ResultsTracker(config.base_dir) - try: - all_matchers = { - key: LicenceMatcher(style, config.licence, config.match_regex) - for key, style in COMMENT_STYLES.items() - } - except RuntimeError as e: - exit(e) - - for filepath in git_find_all_file_paths(config.base_dir, git_paths): - # Skip symlinks (with message) - if filepath.is_symlink(): - results.excluded(filepath, "File is a symlink") - continue - - # Skip non-file - if not filepath.is_file(): - continue - - # Skip exclude patterns - if matches_exclude_pattern(config, filepath): - results.excluded(filepath, "Path matches exclude pattern") - continue - - check_file_for_licence(all_matchers, results, filepath) - - return results - - -def check_file_for_licence(all_matchers, results, filepath): - matchers = detect_comment_char(all_matchers, filepath.name) - - if not matchers: - results.skipped(filepath, "Unknown comment style") - return - - if filepath.stat().st_size == 0: - results.skipped(filepath, "Empty file") - return - - problems = [] - for matcher in matchers: - good, line_num, msg = check_file_with_matcher(matcher, filepath) - if good: - results.passed(filepath, line_num, msg) - return - else: - problems.append((line_num, msg)) - - # If we get here, we didn't find a matching licence - for line_num, msg in problems: - results.failed(filepath, line_num, msg) - - -def check_file_with_matcher(matcher, filepath): - '''Check the file at filepath against matcher. - - Returns a tuple (is_good, line_number, msg). is_good is True on success; - False on failure. line_number is the position where the licence was found - (on success) or where we gave up searching for it (on failure). msg is the - associated success or error message. - - ''' - def next_line(file, line_no): - return (next(file).rstrip(), line_no + 1) - - with filepath.open() as f: - licence_assumed_start = None - - # Get first line - try: - line, line_no = next_line(f, 0) - except StopIteration: - return (False, 1, "Empty file") - - # Check first line against the first word of licence, or against a - # possible different first line. - if not matcher.looks_like_first_line(line): - if not matcher.looks_like_first_line_comment(line): - return (False, line_no, "File does not start with comment") - - try: - line, line_no = next_line(f, line_no) - except StopIteration: - return (False, line_no, - "Reached end of file before finding licence") - - # Skip lines that don't seem to be the first line of the licence - while not matcher.looks_like_first_line(line): - try: - line, line_no = next_line(f, line_no) - except StopIteration: - return (False, line_no, - "Reached end of file before finding licence") - - if not matcher.looks_like_comment(line): - return (False, line_no, - "First comment ended before licence notice") - - # We found the marker, so we found the first line of the licence. The - # current line is in the first comment, so check the line matches the - # expected first line: - licence_assumed_start = line_no - matcher.start() - matched, done = matcher.take_line(line) - if not matched: - return (False, line_no, "Licence does not match") - - while not done: - try: - line, line_no = next_line(f, line_no) - except StopIteration: - return (False, line_no, - "Reached end of file before finding licence") - - # Check against full expected line. - matched, done = matcher.take_line(line) - if not matched: - return (False, line_no, "Licence did not match") - - return (True, licence_assumed_start, "Licence found") - - -def main(): - desc = "A tool to check the lowRISC licence header is in each source file" - parser = argparse.ArgumentParser(description=desc) - parser.add_argument("--config", - metavar="config.hjson", - type=argparse.FileType('r', encoding='UTF-8'), - required=True, - help="HJSON file to read for licence configuration.") - parser.add_argument("paths", - metavar="path", - nargs='*', - default=["."], - help="Paths to check for licence headers.") - parser.add_argument('-v', - "--verbose", - action='store_true', - dest='verbose', - help="Verbose output") - - options = parser.parse_args() - - if options.verbose: - logging.basicConfig(format="%(levelname)s: %(message)s", - level=logging.INFO) - else: - logging.basicConfig(format="%(levelname)s: %(message)s") - - config = SimpleNamespace() - config.base_dir = git_find_repo_toplevel() - - parsed_config = hjson.load(options.config) - - config.licence = LicenceHeader(parsed_config['licence']) - config.exclude_paths = set(parsed_config['exclude_paths']) - # Check whether we should use regex matching or full string matching. - match_regex = parsed_config.get('match_regex', 'false') - if match_regex not in ['true', 'false']: - print('Invalid value for match_regex: {!r}. ' - 'Should be "true" or "false".'.format(match_regex)) - exit(1) - config.match_regex = match_regex == 'true' - - results = check_paths(config, options.paths) - - print(results.display_nicely()) - - if results.any_failed(): - print("Failed:") - for path in results.failing_paths: - print(" {}".format(str(path))) - print("") - exit(1) - else: - exit(0) - - -if __name__ == '__main__': - main() diff --git a/util/lowrisc_misc-linters/requirements.txt b/util/lowrisc_misc-linters/requirements.txt deleted file mode 100644 index 306d4604..00000000 --- a/util/lowrisc_misc-linters/requirements.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright lowRISC contributors. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -hjson -tabulate -yapf - diff --git a/util/make_multiprotocol.py b/util/make_multiprotocol.py index 81659bd9..5d6cbbaf 100644 --- a/util/make_multiprotocol.py +++ b/util/make_multiprotocol.py @@ -3,7 +3,8 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# Author: Tobias Senti +# Authors: +# - Tobias Senti """Makes a legacy job file multiprotocol\ by adding random read and write protocol""" @@ -28,7 +29,7 @@ output.append(str(random.randrange(0, 6)) + '\n') index += 2 - for i in range(0,8): + for i in range(0, 8): if index >= len(lines): break output.append(lines[index]) diff --git a/util/mario/backend.py b/util/mario/backend.py new file mode 100644 index 00000000..690d17e1 --- /dev/null +++ b/util/mario/backend.py @@ -0,0 +1,51 @@ +#!/usr/env python3 +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Authors: +# - Tobias Senti +# - Thomas Benz + +""" MARIO backend interaction""" +from mako.template import Template +from mario.util import eval_key, prot_key + + +def render_backend(prot_ids: dict, db: dict, tpl_file: str) -> str: + """Generate backend""" + backend_rendered = '' + + with open(tpl_file, 'r', encoding='utf-8') as templ_file: + backend_tpl = templ_file.read() + + # render for every is + for prot_id in prot_ids: + + # get ports used + used_read_prots = prot_ids[prot_id]['ar'] + used_write_prots = prot_ids[prot_id]['aw'] + + # single port IPs? + srp = len(used_read_prots) == 1 + swp = len(used_write_prots) == 1 + + # create context + context = { + 'name_uniqueifier': prot_id, + 'database': db, + 'used_read_protocols': used_read_prots, + 'used_write_protocols': used_write_prots, + 'used_protocols': prot_ids[prot_id]['used'], + 'one_read_port': srp, + 'one_write_port': swp, + 'used_non_bursting_write_protocols': + prot_key(used_write_prots, 'bursts', 'not_supported', db), + 'combined_aw_and_w': + eval_key(used_write_prots, 'combined_aw_and_w', 'true', db) + } + + # render + backend_rendered += Template(backend_tpl).render(**context) + + return backend_rendered diff --git a/util/mario/bender.py b/util/mario/bender.py new file mode 100644 index 00000000..500d0662 --- /dev/null +++ b/util/mario/bender.py @@ -0,0 +1,36 @@ +#!/usr/env python3 +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Authors: +# - Tobias Senti +# - Thomas Benz + +"""Bender utils for MARIO""" +from mako.template import Template + + +def render_bender(prot_ids: dict, prot_db: dict, tpl_file: str) -> str: + """Generates and returns the Bender.yml file""" + + # assemble all sources + rtl_sources = '' + test_sources = '' + synth_sources = '' + + # assemble sources + for id in prot_ids: + rtl_sources += f' - idma_legalizer_{id}.sv\n' + rtl_sources += f' - idma_transport_layer_{id}.sv\n' + rtl_sources += f' - idma_backend_{id}.sv\n' + # test and synth sources + test_sources += f' - tb_idma_backend_{id}.sv\n' + synth_sources += f' - idma_backend_synth_{id}.sv\n' + + # create context and render + bender_context = { + 'rtl_sources': rtl_sources, 'test_sources': test_sources, 'synth_sources': synth_sources} + + with open(tpl_file, 'r', encoding='utf-8') as bender_template_content: + return Template(bender_template_content.read()).render(**bender_context) diff --git a/util/mario/database.py b/util/mario/database.py new file mode 100644 index 00000000..984427e7 --- /dev/null +++ b/util/mario/database.py @@ -0,0 +1,25 @@ +#!/usr/env python3 +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Authors: +# - Tobias Senti +# - Thomas Benz + +""" MARIO database interaction""" +import yaml + + +def read_database(db_files: list) -> dict: + """ Read the protocol database""" + prot_db = {} + + # get database entries + for prot_file in sorted(db_files): + with open(prot_file, 'r', encoding='utf-8') as content: + # read yml content + prot = yaml.load(content, Loader=yaml.SafeLoader) + # print(f'[MARIO] Found protocol: {prot["full_name"]}', file=sys.stderr) + prot_db[prot['prefix']] = prot + return prot_db diff --git a/util/mario/legalizer.py b/util/mario/legalizer.py new file mode 100644 index 00000000..23b42f56 --- /dev/null +++ b/util/mario/legalizer.py @@ -0,0 +1,93 @@ +#!/usr/env python3 +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Authors: +# - Tobias Senti +# - Thomas Benz + +""" MARIO legalizer interaction""" +from mako.template import Template +from mario.util import indent_block, eval_key, prot_key + + +def prot_force_decouple(used_prots: list, db: dict) -> list: + """Determine the prots supports a feature""" + res = [] + for prot in used_prots: + if db[prot]['bursts'] == 'not_supported' or db[prot]['legalizer_force_decouple'] == 'true': + res.append(prot) + return res + + +def render_legalizer(prot_ids: dict, db: dict, tpl_file: str) -> str: + """Generate legalizer""" + legalizer_rendered = '' + + with open(tpl_file, 'r', encoding='utf-8') as templ_file: + legalizer_tpl = templ_file.read() + + # render for every is + for prot_id in prot_ids: + + # get ports used + used_read_prots = prot_ids[prot_id]['ar'] + used_write_prots = prot_ids[prot_id]['aw'] + + # single port IPs? + srp = len(used_read_prots) == 1 + swp = len(used_write_prots) == 1 + + # Indent read meta channel + for rp in used_read_prots: + # format DB entry + read_meta = indent_block(db[rp]['legalizer_read_meta_channel'], 3 - srp, 4) + db[rp]['legalizer_read_meta_channel'] = read_meta + + # Indent write meta channel and data path + for wp in used_write_prots: + # format DB entry + write_meta = indent_block(db[wp]['legalizer_write_meta_channel'], 3 - swp, 4) + db[wp]['legalizer_write_meta_channel'] = write_meta + # if datapath exists + if 'legalizer_write_data_path' in db[wp]: + # format DB entry + data_path = indent_block(db[wp]['legalizer_write_data_path'], 3 - swp, 4) + db[wp]['legalizer_write_data_path'] = data_path + + # assemble context + context = { + 'name_uniqueifier': prot_id, + 'database': db, + 'used_read_protocols': used_read_prots, + 'used_write_protocols': used_write_prots, + 'used_protocols': prot_ids[prot_id]['used'], + 'one_read_port': srp, + 'one_write_port': swp, + 'no_read_bursting': + eval_key(used_read_prots, 'bursts', 'not_supported', db), + 'has_page_read_bursting': + eval_key(used_read_prots, 'bursts', 'split_at_page_boundary', db), + 'has_pow2_read_bursting': + eval_key(used_read_prots, 'bursts', 'only_pow2', db), + 'no_write_bursting': + eval_key(used_write_prots, 'bursts', 'not_supported', db), + 'has_page_write_bursting': + eval_key(used_write_prots, 'bursts', 'split_at_page_boundary', db), + 'has_pow2_write_bursting': + eval_key(used_write_prots, 'bursts', 'only_pow2', db), + 'used_non_bursting_write_protocols': + prot_key(used_read_prots, 'bursts', 'not_supported', db), + 'used_non_bursting_read_protocols': + prot_key(used_write_prots, 'bursts', 'not_supported', db), + 'used_non_bursting_or_force_decouple_read_protocols': + prot_force_decouple(used_read_prots, db), + 'used_non_bursting_or_force_decouple_write_protocols': + prot_force_decouple(used_write_prots, db) + } + + # render + legalizer_rendered += Template(legalizer_tpl).render(**context) + + return legalizer_rendered diff --git a/util/mario/synth.py b/util/mario/synth.py new file mode 100644 index 00000000..b83479f9 --- /dev/null +++ b/util/mario/synth.py @@ -0,0 +1,58 @@ +#!/usr/env python3 +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Authors: +# - Tobias Senti +# - Thomas Benz + +""" MARIO synth wrapper interaction""" +from mako.template import Template + + +def render_synth_wrapper(prot_ids: dict, db: dict, tpl_file: str) -> str: + """Generate synth wrapper""" + synth_rendered = '' + + with open(tpl_file, 'r', encoding='utf-8') as templ_file: + synth_tpl = templ_file.read() + + # render for every is + for prot_id in prot_ids: + + # get ports used + used_read_prots = prot_ids[prot_id]['ar'] + used_write_prots = prot_ids[prot_id]['aw'] + + # single port IPs? + srp = len(used_read_prots) == 1 + swp = len(used_write_prots) == 1 + + # formatting + for rp in used_read_prots: + db[rp]['synth_wrapper_ports_read'] =\ + ' ' + db[rp]['synth_wrapper_ports_read'].replace('\n', '\n ') + db[rp]['synth_wrapper_assign_read'] =\ + ' ' + db[rp]['synth_wrapper_assign_read'].replace('\n', '\n ') + + for wp in used_read_prots: + db[wp]['synth_wrapper_ports_write'] =\ + ' ' + db[wp]['synth_wrapper_ports_write'].replace('\n', '\n ') + db[wp]['synth_wrapper_assign_write'] =\ + ' ' + db[wp]['synth_wrapper_assign_write'].replace('\n', '\n ') + + context = { + 'name_uniqueifier': prot_id, + 'database': db, + 'used_read_protocols': used_read_prots, + 'used_write_protocols': used_write_prots, + 'used_protocols': prot_ids[prot_id]['used'], + 'one_read_port': srp, + 'one_write_port': swp + } + + # render + synth_rendered += Template(synth_tpl).render(**context) + + return synth_rendered diff --git a/util/mario/testbench.py b/util/mario/testbench.py new file mode 100644 index 00000000..ba3313ca --- /dev/null +++ b/util/mario/testbench.py @@ -0,0 +1,95 @@ +#!/usr/env python3 +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Authors: +# - Tobias Senti +# - Thomas Benz + +""" MARIO backend interaction""" +from mako.template import Template + + +def render_testbench(prot_ids: dict, db: dict, tpl_file: str) -> str: + """Generate testbench""" + testbench_rendered = '' + + with open(tpl_file, 'r', encoding='utf-8') as templ_file: + testbench_tpl = templ_file.read() + + # render for every is + for prot_id in prot_ids: + + read_bridges = {} + write_bridges = {} + + # iterate over the protocols in use + for up in prot_ids[prot_id]['used']: + + # format bridge instantiation + if up != 'axi': + if 'bridge_template' in db[up]: + db[up]['bridge_template'] =\ + ' ' + db[up]['bridge_template'].replace('\n', '\n ') + if 'write_bridge_template' in db[up]: + db[up]['write_bridge_template'] =\ + ' ' + db[up]['write_bridge_template'].replace('\n', '\n ') + if 'read_bridge_template' in db[up]: + db[up]['read_bridge_template'] =\ + ' ' + db[up]['read_bridge_template'].replace('\n', '\n ') + + # iterate over the protocols in use + for rp in prot_ids[prot_id]['ar']: + + # format bridge instantiation + if rp != 'axi': + context = { + 'port': 'read', + 'database': db, + 'used_read_protocols': prot_ids[prot_id]['ar'] + } + + # render + if 'read_bridge_template' in db[rp]: + bridge_template = Template(db[rp]['read_bridge_template']) + else: + bridge_template = Template(db[rp]['bridge_template']) + read_bridges[rp] = bridge_template.render(**context) + + # iterate over the protocols in use + for wp in prot_ids[prot_id]['aw']: + + # format bridge instantiation + if wp != 'axi': + context = { + 'port': 'write', + 'database': db, + 'used_write_protocols': prot_ids[prot_id]['aw'] + } + + # render + if 'write_bridge_template' in db[wp]: + bridge_template = Template(db[wp]['write_bridge_template']) + else: + bridge_template = Template(db[wp]['bridge_template']) + write_bridges[wp] = bridge_template.render(**context) + + # render + context = { + 'name_uniqueifier': prot_id, + 'database': db, + 'used_read_protocols': prot_ids[prot_id]['ar'], + 'used_write_protocols': prot_ids[prot_id]['aw'], + 'used_protocols': prot_ids[prot_id]['used'], + 'unused_protocols': set(list(db.keys())) - set(prot_ids[prot_id]['used']), + 'one_read_port': len(prot_ids[prot_id]['ar']) == 1, + 'one_write_port': len(prot_ids[prot_id]['aw']) == 1, + 'rendered_read_bridges': read_bridges, + 'rendered_write_bridges': write_bridges + } + + # render + testbench_rendered += Template(testbench_tpl).render(**context) + + return testbench_rendered diff --git a/util/mario/transport_layer.py b/util/mario/transport_layer.py new file mode 100644 index 00000000..c3a3b7ce --- /dev/null +++ b/util/mario/transport_layer.py @@ -0,0 +1,191 @@ +#!/usr/env python3 +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Authors: +# - Tobias Senti +# - Thomas Benz + +""" MARIO transport layer interaction""" +from mako.template import Template + + +def render_read_mgr_inst(prot_id: str, prot_ids: dict, db: dict) -> dict: + """Renders the port instantiations of the read managers""" + + res = {} + + # single read port + srp = len(prot_ids[prot_id]['ar']) == 1 + + # Render read ports + for rp in prot_ids[prot_id]['ar']: + + # template cleanup + db[rp]['read_template'] = ' ' + db[rp]['read_template'].replace('\n', '\n ') + db[rp]['read_template'] = db[rp]['read_template'][:-5] + + if db[rp]['read_slave'] == 'true': + read_req_str = f'{rp}_read_req_t' + read_rsp_str = f'{rp}_read_rsp_t' + else: + read_req_str = f'{rp}_req_t' + read_rsp_str = f'{rp}_rsp_t' + + if srp: + read_dp_valid_in = 'r_dp_valid_i' + read_dp_ready_out = 'r_dp_ready_o' + read_dp_response = 'r_dp_rsp_o' + read_dp_valid_out = 'r_dp_valid_o' + read_dp_ready_in = 'r_dp_ready_i' + read_meta_request = 'ar_req_i' + read_meta_valid = 'ar_valid_i' + read_meta_ready = 'ar_ready_o' + r_chan_valid = 'r_chan_valid_o' + r_chan_ready = 'r_chan_ready_o' + buffer_in = 'buffer_in' + buffer_in_valid = 'buffer_in_valid' + else: + read_dp_valid_in = f'''\ +(r_dp_req_i.src_protocol == idma_pkg::{db[rp]["protocol_enum"]}) & r_dp_valid_i\ +''' + read_dp_ready_out = f'{rp}_r_dp_ready' + read_dp_response = f'{rp}_r_dp_rsp' + read_dp_valid_out = f'{rp}_r_dp_valid' + read_dp_ready_in = f'''\ +(r_dp_req_i.src_protocol == idma_pkg::{db[rp]["protocol_enum"]}) & r_dp_ready_i\ +''' + read_meta_request = 'ar_req_i.ar_req' + read_meta_valid = f'''\ +(ar_req_i.src_protocol == idma_pkg::{db[rp]["protocol_enum"]}) & ar_valid_i\ +''' + read_meta_ready = f'{rp}_ar_ready' + r_chan_valid = f'{rp}_r_chan_valid' + r_chan_ready = f'{rp}_r_chan_ready' + buffer_in = f'{rp}_buffer_in' + buffer_in_valid = f'{rp}_buffer_in_valid' + + read_port_context = { + 'database': db, + 'req_t': read_req_str, + 'rsp_t': read_rsp_str, + 'r_dp_valid_i': read_dp_valid_in, + 'r_dp_ready_o': read_dp_ready_out, + 'r_dp_rsp_o': read_dp_response, + 'r_dp_valid_o': read_dp_valid_out, + 'r_dp_ready_i': read_dp_ready_in, + 'read_meta_request': read_meta_request, + 'read_meta_valid': read_meta_valid, + 'read_meta_ready': read_meta_ready, + 'read_request': f'{rp}_read_req_o', + 'read_response': f'{rp}_read_rsp_i', + 'r_chan_valid': r_chan_valid, + 'r_chan_ready': r_chan_ready, + 'buffer_in': buffer_in, + 'buffer_in_valid': buffer_in_valid + } + + # render + res[rp] = Template(db[rp]['read_template']).render(**read_port_context) + + return res + + +def render_write_mgr_inst(prot_id: str, prot_ids: dict, db: dict) -> dict: + """Renders the port instantiations of the write managers""" + + res = {} + + # single read port + swp = len(prot_ids[prot_id]['aw']) == 1 + + # Render read ports + for wp in prot_ids[prot_id]['aw']: + + # template cleanup + db[wp]['write_template'] = ' ' + db[wp]['write_template'].replace('\n', '\n ') + db[wp]['write_template'] = db[wp]['write_template'][:-5] + + if db[wp]['read_slave'] == 'true': + write_req_str = f'{wp}_write_req_t' + write_rsp_str = f'{wp}_write_rsp_t' + else: + write_req_str = f'{wp}_req_t' + write_rsp_str = f'{wp}_rsp_t' + + if swp: + write_dp_valid_in = 'w_dp_valid_i' + write_dp_ready_out = 'w_dp_ready_o' + write_dp_response = 'w_dp_rsp_o' + write_dp_valid_out = 'w_dp_valid_o' + write_dp_ready_in = 'w_dp_ready_i' + write_meta_request = 'aw_req_i' + write_meta_valid = 'aw_valid_i' + write_meta_ready = 'aw_ready_o' + buffer_out_ready = 'buffer_out_ready' + else: + write_dp_valid_in = f'''\ +(w_dp_req_i.dst_protocol == idma_pkg::{db[wp]["protocol_enum"]}) & w_dp_req_valid\ +''' + write_dp_ready_out = f'{wp}_w_dp_ready' + write_dp_response = f'{wp}_w_dp_rsp' + write_dp_valid_out = f'{wp}_w_dp_rsp_valid' + write_dp_ready_in = f'{wp}_w_dp_rsp_ready' + write_meta_request = 'aw_req_i.aw_req' + write_meta_valid = f'''\ +(aw_req_i.dst_protocol == idma_pkg::{db[wp]["protocol_enum"]}) & aw_valid_i\ +''' + write_meta_ready = f'{wp}_aw_ready' + buffer_out_ready = f'{wp}_buffer_out_ready' + + write_port_context = { + 'database': db, + 'req_t': write_req_str, + 'rsp_t': write_rsp_str, + 'w_dp_valid_i': write_dp_valid_in, + 'w_dp_ready_o': write_dp_ready_out, + 'w_dp_rsp_o': write_dp_response, + 'w_dp_valid_o': write_dp_valid_out, + 'w_dp_ready_i': write_dp_ready_in, + 'write_meta_request': write_meta_request, + 'write_meta_valid': write_meta_valid, + 'write_meta_ready': write_meta_ready, + 'write_request': f'{wp}_write_req_o', + 'write_response': f'{wp}_write_rsp_i', + 'buffer_out_ready': buffer_out_ready + } + + # render + res[wp] = Template(db[wp]['write_template']).render(**write_port_context) + + return res + + +def render_transport_layer(prot_ids: dict, db: dict, tpl_file: str) -> str: + """Generate Transport Layer""" + transport_rendered = '' + + with open(tpl_file, 'r', encoding='utf-8') as templ_file: + transport_tpl = templ_file.read() + + # render for every is + for prot_id in prot_ids: + + # Render Transport Layer + context = { + 'name_uniqueifier': prot_id, + 'database': db, + 'used_read_protocols': prot_ids[prot_id]['ar'], + 'used_write_protocols': prot_ids[prot_id]['aw'], + 'used_protocols': prot_ids[prot_id]['used'], + 'one_read_port': len(prot_ids[prot_id]['ar']) == 1, + 'one_write_port': len(prot_ids[prot_id]['aw']) == 1, + 'rendered_read_ports': render_read_mgr_inst(prot_id, prot_ids, db), + 'rendered_write_ports': render_write_mgr_inst(prot_id, prot_ids, db) + } + + # render + transport_rendered += Template(transport_tpl).render(**context) + + return transport_rendered diff --git a/util/mario/util.py b/util/mario/util.py new file mode 100644 index 00000000..a7834900 --- /dev/null +++ b/util/mario/util.py @@ -0,0 +1,115 @@ +#!/usr/env python3 +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Authors: +# - Tobias Senti +# - Thomas Benz + +"""Util functions for MARIO""" +import sys + + +def indent_block(block: str, level: int, num_spaces: int) -> str: + """Indents a block """ + indented_block = '' + split_block = block.split('\n') + + for line in split_block: + if indented_block != '': + indented_block += '\n' + indented_block += level * num_spaces * " " + line + + return indented_block + + +def eval_key(used_prots: list, key: str, feature: str, db: dict) -> bool: + """Determine if one prot supports a feature""" + res = False + for prot in used_prots: + res |= db[prot][key] == feature + return res + + +def prot_key(used_prots: list, key: str, feature: str, db: dict) -> list: + """Determine the prots supports a feature""" + res = [] + for prot in used_prots: + if db[prot][key] == feature: + res.append(prot) + return res + + +def prepare_ids(id_strs: list) -> dict: + """Parses and validates the IDs """ + # resulting dict + res = {} + # go over all IDs + for id_str in id_strs: + # decompose ID + id = id_str.split('_') + + # check specifier ordering + specifiers = id[::2] + if not specifiers == sorted(specifiers): + print(f'[MARIO] Specifier order not corrected in {id_str}', file=sys.stderr) + sys.exit(1) + + # get protocols + r_prots = [] + w_prots = [] + rw_prots = [] + for idx in range(0, len(id), 2): + if id[idx] == 'r': + r_prots.append(id[idx + 1]) + elif id[idx] == 'w': + w_prots.append(id[idx + 1]) + elif id[idx] == 'rw': + rw_prots.append(id[idx + 1]) + else: + print(f'[MARIO] {id[idx]} is non-supported specifier', file=sys.stderr) + sys.exit(1) + + # check protocol ordering + specifiers = id[::2] + if not r_prots == sorted(r_prots): + print('[MARIO] Read protocols order not correct', file=sys.stderr) + sys.exit(1) + + if not w_prots == sorted(w_prots): + print('[MARIO] Write protocols order not correct', file=sys.stderr) + sys.exit(1) + + if not rw_prots == sorted(rw_prots): + print('[MARIO] Bidir protocols order not correct', file=sys.stderr) + sys.exit(1) + + # create all_read and all_write + ar_prots = [] + [ar_prots.append(rp) for rp in r_prots] + [ar_prots.append(rwp) for rwp in rw_prots] + + aw_prots = [] + [aw_prots.append(wp) for wp in w_prots] + [aw_prots.append(rwp) for rwp in rw_prots] + + # for now: check if a port only appears once + if not sorted(ar_prots) == sorted(list(set(ar_prots))): + print('[MARIO] Protocol can only appear once', file=sys.stderr) + sys.exit(1) + + if not sorted(aw_prots) == sorted(list(set(aw_prots))): + print('[MARIO] Protocol can only appear once', file=sys.stderr) + sys.exit(1) + + # used protocols + used_prots = [] + [used_prots.append(arps) for arps in ar_prots] + [used_prots.append(awps) for awps in aw_prots] + + # append protocols + res[id_str] = {'r': r_prots, 'w': w_prots, 'rw': rw_prots, 'ar': sorted(ar_prots), + 'aw': sorted(aw_prots), 'used': sorted(list(set(used_prots)))} + + return res diff --git a/util/mario/wave.py b/util/mario/wave.py new file mode 100644 index 00000000..818d3d9b --- /dev/null +++ b/util/mario/wave.py @@ -0,0 +1,47 @@ +#!/usr/env python3 +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Authors: +# - Tobias Senti +# - Thomas Benz + +""" MARIO wave interaction""" +from mako.template import Template + + +def render_vsim_wave(prot_ids: dict, db: dict, tpl_file: str) -> str: + """Generate questa wave""" + wave_rendered = '' + + with open(tpl_file, 'r', encoding='utf-8') as templ_file: + wave_tpl = templ_file.read() + + # render for every is + for prot_id in prot_ids: + + # get ports used + used_read_prots = prot_ids[prot_id]['ar'] + used_write_prots = prot_ids[prot_id]['aw'] + + # single port IPs? + srp = len(used_read_prots) == 1 + swp = len(used_write_prots) == 1 + + context = { + 'name_uniqueifier': prot_id, + 'database': db, + 'used_read_protocols': used_read_prots, + 'used_write_protocols': used_write_prots, + 'used_protocols': prot_ids[prot_id]['used'], + 'one_read_port': srp, + 'one_write_port': swp + } + + print(context) + + # render + wave_rendered += Template(wave_tpl).render(**context) + + return wave_rendered diff --git a/util/waiver.verible b/util/waiver.verible deleted file mode 100644 index a04df7c0..00000000 --- a/util/waiver.verible +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# waiver file for the iDMA repo - -# 2D 32-bit frontend register file -waive --rule=typedef-structs-unions --location="src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_pkg.sv" -waive --rule=line-length --location="src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_pkg.sv" - -# 64-bit frontend register file -waive --rule=typedef-structs-unions --location="src/frontends/register_64bit/idma_reg64_frontend_reg_pkg.sv" -waive --rule=line-length --location="src/frontends/register_64bit/idma_reg64_frontend_reg_pkg.sv" -waive --rule=typedef-structs-unions --location="src/frontends/register_64bit_2d/idma_reg64_2d_frontend_reg_pkg.sv" -waive --rule=line-length --location="src/frontends/register_64bit_2d/idma_reg64_2d_frontend_reg_pkg.sv" - -# 64-bit descriptor-based register file -waive --rule=typedef-structs-unions --location="src/frontends/desc64/idma_desc64_reg_pkg.sv" -waive --rule=line-length --location="src/frontends/desc64/idma_desc64_reg_pkg.sv" -waive --rule=line-length --location="src/frontends/desc64/idma_desc64_top.sv" - -# Declare zero-based big-endian unpacked dimensions sized as [N] -> legacy PULP code :S -waive --rule=unpacked-dimensions-range-ordering --location="src/systems/pulpopen/dmac_wrap.sv" diff --git a/verilator/scripts/preprocess.py b/verilator/scripts/preprocess.py deleted file mode 100644 index 39068385..00000000 --- a/verilator/scripts/preprocess.py +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env python3 -# Copyright 2022 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 - -# Author: Thomas Benz - -"""Only filters modules required for the DMA to make verilator work properly.""" -import sys - -WHITE_LIST = ['fifo_v3', 'stream_fifo', 'spill_register', 'popcount', 'stream_fork', 'fifo_v2', - 'axi_pkg', 'cf_math', 'fall_through_register', 'stream_join', 'idma_', '+define+', '+incdir+'] - -_, inp_file = sys.argv - -with open(inp_file, 'r', encoding='utf-8') as f: - for line in f.read().split('\n'): - if line == '': - print() - if any(map(line.__contains__, WHITE_LIST)): - print(line) diff --git a/working_dir/axi b/working_dir/axi deleted file mode 160000 index 96f749dc..00000000 --- a/working_dir/axi +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 96f749dc4ae62ed6b90e44aabb5d9460f1b0d858