From 8de1915adaa73049612aec4d835c616e31d3ec76 Mon Sep 17 00:00:00 2001
From: Thomas Benz <65011851+thommythomaso@users.noreply.github.com>
Date: Tue, 26 Apr 2022 18:00:38 +0200
Subject: [PATCH] occamy: Add interleaved mode to HBM crossbar
 (pulp-platform/snitch#391)

---
 Bender.yml                                    |  2 +
 .../occamy_hbm_xbar_reg.hjson.tpl             | 29 +++++++++++++
 hw/occamy/occamy_soc.sv.tpl                   | 11 ++++-
 hw/occamy/occamy_top.sv.tpl                   | 43 ++++++++++++++++++-
 target/sim/Makefile                           |  1 +
 util/occamygen/occamygen.py                   |  1 +
 util/solder/solder.py                         | 10 ++++-
 7 files changed, 94 insertions(+), 3 deletions(-)
 create mode 100644 hw/occamy/hbm_xbar_ctrl/occamy_hbm_xbar_reg.hjson.tpl

diff --git a/Bender.yml b/Bender.yml
index c214d4a37..5f1e044d4 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -29,6 +29,8 @@ sources:
 - src/occamy_soc_ctrl/occamy_soc_reg_top.sv
 - src/occamy_quadrant_s1_ctrl/occamy_quadrant_s1_reg_pkg.sv
 - src/occamy_quadrant_s1_ctrl/occamy_quadrant_s1_reg_top.sv
+- src/occamy_hbm_xbar_ctrl/occamy_hbm_xbar_reg_pkg.sv
+- src/occamy_hbm_xbar_ctrl/occamy_hbm_xbar_reg_top.sv
 - src/rv_plic/rv_plic_reg_pkg.sv
 - src/rv_plic/rv_plic_reg_top.sv
 - src/rv_plic/rv_plic.sv
diff --git a/hw/occamy/hbm_xbar_ctrl/occamy_hbm_xbar_reg.hjson.tpl b/hw/occamy/hbm_xbar_ctrl/occamy_hbm_xbar_reg.hjson.tpl
new file mode 100644
index 000000000..1e532b7d6
--- /dev/null
+++ b/hw/occamy/hbm_xbar_ctrl/occamy_hbm_xbar_reg.hjson.tpl
@@ -0,0 +1,29 @@
+// Copyright 2020 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
+{
+  name: "${name}_HBM_xbar"
+  clock_primary: "clk_i"
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device" }
+  ],
+  regwidth: 32
+  registers: [
+    { name: "INTERLEAVED_ENA"
+      desc: "Interleaved mode of the x-bar is enabled."
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        {
+          bits: "0:0"
+          resval: "0"
+          name: "INTERLEAVED_ENA"
+          desc: '''
+                Interleaved mode of the x-bar is enabled.
+                '''
+        }
+      ]
+    }
+  ]
+}
diff --git a/hw/occamy/occamy_soc.sv.tpl b/hw/occamy/occamy_soc.sv.tpl
index bec28db66..fcf58a274 100644
--- a/hw/occamy/occamy_soc.sv.tpl
+++ b/hw/occamy/occamy_soc.sv.tpl
@@ -106,9 +106,18 @@ module ${name}_soc
   input  logic [0:0] debug_req_i,
 
   /// SRAM configuration
-  input sram_cfgs_t sram_cfgs_i
+  input sram_cfgs_t sram_cfgs_i,
+
+  /// HBM XBAR configuration
+  input logic hbm_xbar_interleaved_mode_ena_i
 );
 
+  ///////////////////
+  // HBM XBAR CTRL //
+  ///////////////////
+  logic       hbm_xbar_interleaved_mode_ena;
+  assign hbm_xbar_interleaved_mode_ena  = hbm_xbar_interleaved_mode_ena_i;
+
   ///////////////
   // Crossbars //
   ///////////////
diff --git a/hw/occamy/occamy_top.sv.tpl b/hw/occamy/occamy_top.sv.tpl
index 9736eabf6..876fc6463 100644
--- a/hw/occamy/occamy_top.sv.tpl
+++ b/hw/occamy/occamy_top.sv.tpl
@@ -153,6 +153,46 @@ module ${name}_top
 
   ${module}
 
+  //////////////////////////
+  //   HBM XBAR CFG       //
+  //////////////////////////
+
+  ${soc_regbus_periph_xbar.out_hbm_xbar_cfg.req_type()} reg_hbm_xbar_cfg_req;
+  ${soc_regbus_periph_xbar.out_hbm_xbar_cfg.rsp_type()} reg_hbm_xbar_cfg_rsp;
+
+  occamy_hbm_xbar_reg_pkg::occamy_hbm_xbar_reg2hw_t hbm_xbar_reg2hw;
+
+  reg_cdc #(
+    .req_t  ( ${soc_regbus_periph_xbar.out_hbm_xbar_cfg.req_type()} ),
+    .rsp_t  ( ${soc_regbus_periph_xbar.out_hbm_xbar_cfg.rsp_type()} )
+  ) i_reg_cdc_hbm_xbar_cfg (
+    .src_clk_i  ( clk_periph_i                                          ),
+    .src_rst_ni ( rst_periph_ni                                         ),
+    .src_req_i  ( ${soc_regbus_periph_xbar.out_hbm_xbar_cfg.req_name()} ),
+    .src_rsp_o  ( ${soc_regbus_periph_xbar.out_hbm_xbar_cfg.rsp_name()} ),
+
+    .dst_clk_i  ( clk_i                 ),
+    .dst_rst_ni ( rst_ni                ),
+    .dst_req_o  ( reg_hbm_xbar_cfg_req  ),
+    .dst_rsp_i  ( reg_hbm_xbar_cfg_rsp  )
+  );
+
+  occamy_hbm_xbar_reg_top #(
+    .reg_req_t ( ${soc_regbus_periph_xbar.out_hbm_xbar_cfg.req_type()}  ),
+    .reg_rsp_t ( ${soc_regbus_periph_xbar.out_hbm_xbar_cfg.rsp_type()}  )
+  ) i_occamy_hbm_xbar_reg_top (
+    .clk_i     ( clk_i                ),
+    .rst_ni    ( rst_ni               ),
+    .reg_req_i ( reg_hbm_xbar_cfg_req ),
+    .reg_rsp_o ( reg_hbm_xbar_cfg_rsp ),
+    .reg2hw    ( hbm_xbar_reg2hw      ),
+    `ifndef SYNTHESIS
+    .devmode_i ( 1'b1 )
+    `else
+    .devmode_i ( 1'b0 )
+    `endif
+  );
+
   ///////////////////////////////
   //   Synchronous top level   //
   ///////////////////////////////
@@ -204,7 +244,8 @@ module ${name}_top
     .msip_i ( msip ),
     .eip_i ( eip ),
     .debug_req_i ( debug_req ),
-    .sram_cfgs_i
+    .sram_cfgs_i,
+    .hbm_xbar_interleaved_mode_ena_i (hbm_xbar_reg2hw.interleaved_ena.q )
   );
 
   // Connect AXI-lite master
diff --git a/target/sim/Makefile b/target/sim/Makefile
index 82183068f..7996d7086 100644
--- a/target/sim/Makefile
+++ b/target/sim/Makefile
@@ -104,6 +104,7 @@ endef
 
 update-socreg:
 	$(call update_ctrl_regs,SOCREGS,src/occamy_soc_ctrl,occamy_soc_reg.hjson,occamy_soc_peripheral,1)
+	$(call update_ctrl_regs,HBMXBARREGS,src/occamy_hbm_xbar_ctrl,occamy_hbm_xbar_reg.hjson,occamy_hbm_xbar_peripheral,1)
 
 update-quadreg:
 	$(call update_ctrl_regs,QUADREGS,src/occamy_quadrant_s1_ctrl,occamy_quadrant_s1_reg.hjson,occamy_quad_peripheral,1)
diff --git a/util/occamygen/occamygen.py b/util/occamygen/occamygen.py
index 39d93b131..6b0a6aec7 100755
--- a/util/occamygen/occamygen.py
+++ b/util/occamygen/occamygen.py
@@ -605,6 +605,7 @@ def main():
         fall_through=occamy.cfg["hbm_xbar"]["fall_through"],
         no_loopback=True,
         atop_support=False,
+        interleaved_ena=True,
         context="soc",
         node=am_hbm_xbar)
 
diff --git a/util/solder/solder.py b/util/solder/solder.py
index b654551bf..fce9c478e 100644
--- a/util/solder/solder.py
+++ b/util/solder/solder.py
@@ -1338,6 +1338,7 @@ def __init__(self,
                  no_loopback=False,
                  atop_support=True,
                  latency_mode=None,
+                 interleaved_ena=False,
                  **kwargs):
         super().__init__(**kwargs)
         self.aw = aw
@@ -1351,6 +1352,7 @@ def __init__(self,
         self.symbolic_addrmap = list()
         self.symbolic_addrmap_multi = list()
         self.atop_support = atop_support
+        self.interleaved_ena = interleaved_ena
         self.addrmap = list()
         self.connections = dict()
         self.latency_mode = latency_mode or "axi_pkg::CUT_ALL_PORTS"
@@ -1546,7 +1548,10 @@ def emit(self):
             self.__dict__["out_" + name] = bus
 
         # Emit the crossbar instance itself.
-        code = "axi_xbar #(\n"
+        if not self.interleaved_ena:
+            code = "axi_xbar #(\n"
+        else:
+            code = "axi_interleaved_xbar #(\n"
         code += "  .Cfg           ( {cfg_name} ),\n".format(
             cfg_name=self.cfg_name)
         code += "  .Connectivity  ( {} ), \n".format(self.connectivity())
@@ -1585,6 +1590,9 @@ def emit(self):
             name=self.name)
         code += "  .addr_map_i       ( {addrmap_name} ),\n".format(
             addrmap_name=addrmap_name)
+        if self.interleaved_ena:
+            code += "  .interleaved_mode_ena_i ( {name}_interleaved_mode_ena ),\n".format(
+                name=self.name)
         code += "  .en_default_mst_port_i ( '1 ),\n"
         code += "  .default_mst_port_i    ( '0 )\n"
         code += ");\n"