SPI Host: FSM Bug CSAAT

[crsystems]

The OpenTitan SPI host FSM contains a bug as it uses the command_i.segment.csaat signal instead of the latched csaat_q from the command that is currently being executed to decide how the chip select will be handled.

See OpenTitans Fix

Patch to rectify the problem:

diff --git a/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv b/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv
index 4fb1360d..e50d0e7e 100644
--- a/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv
+++ b/hw/vendor/lowrisc_opentitan/spi_host/rtl/spi_host_fsm.sv
@@ -250,7 +250,7 @@ module spi_host_fsm
           // and of CSAAT is asserted, the details of the subsequent command.
           if (!last_bit || !last_byte) begin
             prestall_st_d = InternalClkLow;
-          end else if (!command_i.segment.csaat) begin
+          end else if (!csaat_q) begin
             prestall_st_d = WaitTrail;
           end else if (!command_valid_i) begin
             prestall_st_d = IdleCSBActive;