diff --git a/arch/arm64/boot/dts/rockchip/overlays/Makefile b/arch/arm64/boot/dts/rockchip/overlays/Makefile
index ac3c04d9..b07e6d98 100644
--- a/arch/arm64/boot/dts/rockchip/overlays/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlays/Makefile
@@ -48,6 +48,7 @@ dtb-$(CONFIG_CLK_RK3308) += \
 	rk3308-spi1-spidev.dtbo \
 	rk3308-spi2-spidev.dtbo \
 	rk3308-uart0.dtbo \
+	rk3308-uart1-full.dtbo \
 	rk3308-uart1.dtbo \
 	rk3308-uart2-m0.dtbo \
 	rk3308-uart3.dtbo \
diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3308-uart1-full.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3308-uart1-full.dts
new file mode 100644
index 00000000..450cd6a4
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlays/rk3308-uart1-full.dts
@@ -0,0 +1,28 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	metadata {
+		title = "Enable UART1 with Hardware Flow Control";
+		compatible = "radxa,rockpis", "radxa,rock-s0";
+		category = "misc";
+		exclusive = "GPIO1_C6", "GPIO1_C7", "GPIO1_D0", "GPIO1_D1", "uart1", "i2c0", "spi2";
+		description = "Enable UART1 with Hardware Flow Control.
+On ROCK Pi S, this uses RTSN pin 19, CTSN pin 21, RX pin 23, and TX pin 24.
+On ROCK S0, this uses RTSN pin 19, CTSN pin 21, RX pin 23, and TX pin 24.";
+	};
+};
+
+&uart1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
+};
+
+&spi2 {
+	status = "disabled";
+};
+
+&i2c0 {
+	status = "disabled";
+};