feat: add spi1 to rock2

arch/arm64/boot/dts/rockchip/overlays/Makefile

@@ -136,6 +136,11 @@ dtb-$(CONFIG_CLK_RK3528) += \
 	rk3528-spi0-cs1-enc28j60.dtbo \
 	rk3528-spi0-cs1-mcp2515.dtbo \
 	rk3528-spi0-cs1-spidev.dtbo \
+	rk3528-spi0-cs1-w5500.dtbo \
+	rk3528-spi1-cs-gpio-enc28j60.dtbo \
+	rk3528-spi1-cs-gpio-mcp2515.dtbo \
+	rk3528-spi1-cs-gpio-spidev.dtbo \
+	rk3528-spi1-cs-gpio-w5500.dtbo \
 	rk3528-uart0-m0.dtbo \
 	rk3528-uart1-m0.dtbo \
 	rk3528-uart2-m1.dtbo \

arch/arm64/boot/dts/rockchip/overlays/enc28j60.dtsi

@@ -0,0 +1,28 @@
+#ifndef __ENC28J60_DTSI__
+#define __ENC28J60_DTSI__
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/dts-v1/;
+/plugin/;
+
+#if !defined(ENC28J60_SPI) && !defined(SPIDEV_NUM)
+#error "Required macros are undefined: ENC28J60_SPI and SPIDEV_NUM."
+#endif
+
+&ENC28J60_SPI {
+	status = "okay";
+	max-freq = <10000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	ethernet: enc28j60@SPIDEV_NUM {
+		compatible = "microchip,enc28j60";
+		reg = <SPIDEV_NUM>;
+		spi-max-frequency = <20000000>;
+	};
+};
+
+#endif // __ENC28J60_DTSI__

arch/arm64/boot/dts/rockchip/overlays/mcp2515.dtsi

@@ -0,0 +1,40 @@
+#ifndef __MCP2515_DTSI__
+#define __MCP2515_DTSI__
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+	can_mcp2515_osc: can-mcp2515-osc {
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+		#clock-cells = <0>;
+	};
+};
+
+#if !defined(MCP2515_SPI) && !defined(SPIDEV_NUM)
+#error "Required macros are undefined: MCP2515_SPI and SPIDEV_NUM."
+#endif
+
+&MCP2515_SPI {
+	status = "okay";
+	max-freq = <10000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	can_mcp2515: can-mcp2515@SPIDEV_NUM {
+		status = "okay";
+		compatible = "microchip,mcp2515";
+		reg = <SPIDEV_NUM>;
+		clocks = <&can_mcp2515_osc>;
+		vdd-supply = <&vcc_3v3_s3>;
+		xceiver-supply = <&vcc_3v3_s3>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+#endif // __MCP2515_DTSI__

arch/arm64/boot/dts/rockchip/overlays/rk3528-spi0-cs1-enc28j60.dts

@@ -1,9 +1,6 @@
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/interrupt-controller/irq.h>
+#define ENC28J60_SPI spi0
+#define SPIDEV_NUM 1
+#include "enc28j60.dtsi"
 
 / {
 	metadata {
@@ -16,31 +13,17 @@ INT=15";
 	};
 };
 
-&spi0 {
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-	pinctrl-names = "default";
-	max-freq = <50000000>;
-	num-cs = <2>;
-
-	ethernet: enc28j60@1 {
-		compatible = "microchip,enc28j60";
-		reg = <1>;
-		spi-max-frequency = <20000000>;
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&enc28j60_int_pins>;
-
-		interrupt-parent = <&gpio4>;
-		interrupts = <RK_PC6 IRQ_TYPE_EDGE_FALLING>;
-	};
-};
-
 &pinctrl {
 	enc28j60 {
 		enc28j60_int_pins: enc28j60-int-pins {
 			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
 };
+
+&ethernet {
+	pinctrl-names = "default";
+	pinctrl-0 = <&enc28j60_int_pins>;
+	interrupt-parent = <&gpio4>;
+	interrupts = <RK_PC6 IRQ_TYPE_EDGE_FALLING>;
+};

arch/arm64/boot/dts/rockchip/overlays/rk3528-spi0-cs1-mcp2515.dts

@@ -25,32 +25,10 @@ INT=15";
 	};
 };
 
-&{/} {
-	can_mcp2515_osc: can-mcp2515-osc {
-		compatible = "fixed-clock";
-		clock-frequency = <12000000>;
-		#clock-cells = <0>;
-	};
-};
-
-&spi0 {
-	status = "okay";
-	max-freq = <10000000>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	num-cs = <2>;
-
-	can_mcp2515: can-mcp2515@1 {
-		status = "okay";
-		compatible = "microchip,mcp2515";
-		reg = <1>;
-		interrupt-parent = <&gpio4>;
-		interrupts = <RK_PC6 IRQ_TYPE_EDGE_FALLING>;
-		spi-max-frequency = <10000000>;
-		clocks = <&can_mcp2515_osc>;
-		vdd-supply = <&vcc_3v3_s3>;
-		xceiver-supply = <&vcc_3v3_s3>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&mcp2515_int_pin>;
-	};
+&can_mcp2515 {
+	interrupt-parent = <&gpio4>;
+	interrupts = <RK_PC6 IRQ_TYPE_EDGE_FALLING>;
+	spi-max-frequency = <10000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcp2515_int_pin>;
 };

arch/arm64/boot/dts/rockchip/overlays/rk3528-spi0-cs1-w5500.dts

@@ -0,0 +1,29 @@
+#define W5500_SPI spi0
+#define SPIDEV_NUM 1
+#include "w5500.dtsi"
+
+/ {
+	metadata {
+		title = "Enable W5500 on SPI0 CS1";
+		compatible = "radxa,rock-2a", "radxa,rock-2f", "radxa,medge-rk3528a-io";
+		category = "misc";
+		exclusive = "GPIO4_B2", "GPIO4_B3", "GPIO4_B4", "GPIO4_C1", "GPIO4_C6";
+		description = "Enable Microchip W5500 SPI Ethernet controller on SPI0 CS1.
+INT=15";
+	};
+};
+
+&pinctrl {
+	w5500 {
+		w5500_int_pins: w5500-int-pins {
+			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&eth_w5500 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&W5500_int_pins>;
+	interrupt-parent = <&gpio4>;
+	interrupts = <RK_PC6 IRQ_TYPE_EDGE_FALLING>;
+};

arch/arm64/boot/dts/rockchip/overlays/rk3528-spi1-cs-gpio-enc28j60.dts

@@ -0,0 +1,34 @@
+#define ENC28J60_SPI spi1
+#define SPIDEV_NUM 0
+#include "enc28j60.dtsi"
+
+/ {
+	metadata {
+		title = "Enable ENC28J60 on SPI1";
+		compatible = "radxa,rock-2a", "radxa,rock-2f", "radxa,medge-rk3528a-io";
+		category = "misc";
+		exclusive = "GPIO1_B4", "GPIO1_B6", "GPIO1_B7", "GPIO1_C0", "GPIO4_B6";
+		description = "Enable Microchip ENC28J60 SPI Ethernet controller on SPI1.
+INT=36";
+	};
+};
+
+&pinctrl {
+	enc28j60 {
+		enc28j60_int_pins: enc28j60-int-pins {
+			rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&ENC28J60_SPI {
+	cs-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi1_pins>;
+};
+
+&ethernet {
+	pinctrl-names = "default";
+	pinctrl-0 = <&enc28j60_int_pins>;
+	interrupt-parent = <&gpio1>;
+	interrupts = <RK_PB4 IRQ_TYPE_EDGE_FALLING>;
+};

arch/arm64/boot/dts/rockchip/overlays/rk3528-spi1-cs-gpio-mcp2515.dts

@@ -0,0 +1,35 @@
+#define MCP2515_SPI spi1
+#define SPIDEV_NUM 0
+#include "mcp2515.dtsi"
+
+/ {
+	metadata {
+		title = "Enable MCP2515 on SPI1";
+		compatible = "radxa,rock-2a", "radxa,rock-2f", "radxa,medge-rk3528a-io";
+		category = "misc";
+		exclusive = "GPIO1_B4", "GPIO1_B6", "GPIO1_B7", "GPIO1_C0", "GPIO4_B6";
+		description = "Enable MCP2515 on SPI1 Over pin 36 with 12 MHz Crystal Oscillator.
+INT=36";
+	};
+};
+
+&pinctrl {
+	mcp2515_int_pin {
+		mcp2515_int_pin: mcp2515_int_pin {
+			rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&MCP2515_SPI {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1_pins>;
+	cs-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
+};
+
+&can_mcp2515 {
+	interrupt-parent = <&gpio1>;
+	interrupts = <RK_PB4 IRQ_TYPE_EDGE_FALLING>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcp2515_int_pin>;
+};

arch/arm64/boot/dts/rockchip/overlays/rk3528-spi1-cs-gpio-spidev.dts

@@ -0,0 +1,31 @@
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+	metadata {
+		title = "Enable spidev on SPI1";
+		compatible = "radxa,rock-2a", "radxa,rock-2f", "radxa,medge-rk3528a-io";
+		category = "misc";
+		exclusive = "GPIO1_B6", "GPIO1_B7", "GPIO1_C0", "GPIO4_B6";
+		description = "Enable spidev on SPI1.
+CS pin is located on pin 24.";
+	};
+};
+
+&spi1 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	max-freq = <50000000>;
+	cs-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi1_pins>;
+
+	spidev@0 {
+		compatible = "rockchip,spidev";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+	};
+};

arch/arm64/boot/dts/rockchip/overlays/rk3528-spi1-cs-gpio-w5500.dts

@@ -0,0 +1,34 @@
+#define W5500_SPI spi0
+#define SPIDEV_NUM 1
+#include "w5500.dtsi"
+
+/ {
+	metadata {
+		title = "Enable W5500 on SPI1";
+		compatible = "radxa,rock-2a", "radxa,rock-2f", "radxa,medge-rk3528a-io";
+		category = "misc";
+		exclusive = "GPIO1_B4", "GPIO1_B6", "GPIO1_B7", "GPIO1_C0", "GPIO4_B6";
+		description = "Enable Microchip W5500 SPI Ethernet controller on SPI1.
+INT=15";
+	};
+};
+
+&pinctrl {
+	w5500 {
+		w5500_int_pins: w5500-int-pins {
+			rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&W5500_SPI {
+	cs-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi1_pins>;   
+};
+
+&eth_w5500 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&w5500_int_pins>;
+	interrupt-parent = <&gpio1>;
+	interrupts = <RK_PB4 IRQ_TYPE_EDGE_FALLING>;
+};

arch/arm64/boot/dts/rockchip/overlays/w5500.dtsi

@@ -0,0 +1,28 @@
+#ifndef __W5500_DTSI__
+#define __W5500_DTSI__
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/dts-v1/;
+/plugin/;
+
+#if !defined(W5500_SPI) && !defined(SPIDEV_NUM)
+#error "Required macros are undefined: W5500_SPI and SPIDEV_NUM."
+#endif
+
+&W5500_SPI{
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;   
+
+	eth_w5500: eth-w5500@0 {
+		status = "okay";
+		compatible = "wiznet,w5500";
+		reg = <0>;
+		spi-max-frequency = <30000000>;
+	};
+};
+
+#endif // __W5500_DTSI__