NOC_VDF

OUR VDF project, from RTL to GDS complete VLSI design flow of NOC (network on Chip)

!! It is an Advance 2 x 2 NOC chip design Which also contains very smart Processing Units !!

Note-> v2 (in second branch is much more scalable version of v1.. though it's GDS Flow is pending)

Name		Name	Last commit message	Last commit date
Latest commit History 73 Commits
Master_new.v		Master_new.v
P_unit.v		P_unit.v
README.md		README.md
VDF_Project1_Group18.pdf		VDF_Project1_Group18.pdf
VDF_Project2_Group18.pdf		VDF_Project2_Group18.pdf
VDF_Project_Part1.pdf		VDF_Project_Part1.pdf
VDF_Project_Part2.pdf		VDF_Project_Part2.pdf
graph.cpp		graph.cpp
main.v		main.v
master.v		master.v
mesh_tb.v		mesh_tb.v
mesh_tb_2.v		mesh_tb_2.v
mesh_tb_3.v		mesh_tb_3.v
path.txt		path.txt
router.v		router.v
tb_noc.v		tb_noc.v
tb_noc1.v		tb_noc1.v
tb_noc2.v		tb_noc2.v
tb_noc3.v		tb_noc3.v

Provide feedback