diff --git a/tests/binary/gold/concat.v b/tests/binary/gold/concat.v index ca8f88796..6498c7448 100644 --- a/tests/binary/gold/concat.v +++ b/tests/binary/gold/concat.v @@ -1,18 +1,56 @@ -module coreir_slice #(parameter hi = 1, parameter lo = 0, parameter width = 1) (input [width-1:0] in, output [hi-lo-1:0] out); +module coreir_slice #( + parameter hi = 1, + parameter lo = 0, + parameter width = 1 +) ( + input [width-1:0] in, + output [hi-lo-1:0] out +); assign out = in[hi-1:lo]; endmodule -module coreir_concat #(parameter width0 = 1, parameter width1 = 1) (input [width0-1:0] in0, input [width1-1:0] in1, output [width0+width1-1:0] out); +module coreir_concat #( + parameter width0 = 1, + parameter width1 = 1 +) ( + input [width0-1:0] in0, + input [width1-1:0] in1, + output [width0+width1-1:0] out +); assign out = {in1,in0}; endmodule -module concats (input [15:0] in, output [15:0] out); +module concats ( + input [15:0] in, + output [15:0] out +); wire [15:0] cc0_out; wire [3:0] s0_out; wire [11:0] s1_out; -coreir_concat #(.width0(4), .width1(12)) cc0(.in0(s0_out), .in1(s1_out), .out(cc0_out)); -coreir_slice #(.hi(16), .lo(12), .width(16)) s0(.in(in), .out(s0_out)); -coreir_slice #(.hi(15), .lo(3), .width(16)) s1(.in(in), .out(s1_out)); +coreir_concat #( + .width0(4), + .width1(12) +) cc0 ( + .in0(s0_out), + .in1(s1_out), + .out(cc0_out) +); +coreir_slice #( + .hi(16), + .lo(12), + .width(16) +) s0 ( + .in(in), + .out(s0_out) +); +coreir_slice #( + .hi(15), + .lo(3), + .width(16) +) s1 ( + .in(in), + .out(s1_out) +); assign out = cc0_out; endmodule diff --git a/tests/gtest/add_golden.v b/tests/gtest/add_golden.v index d0d44bc84..1b3350410 100644 --- a/tests/gtest/add_golden.v +++ b/tests/gtest/add_golden.v @@ -1,4 +1,8 @@ -module Top (input [7:0] I0, input [7:0] I1, output [7:0] O); +module Top ( + input [7:0] I0, + input [7:0] I1, + output [7:0] O +); assign O = I0 + I1; endmodule diff --git a/tests/gtest/array_select_golden.v b/tests/gtest/array_select_golden.v index 9cb5ad958..06f59a8a6 100644 --- a/tests/gtest/array_select_golden.v +++ b/tests/gtest/array_select_golden.v @@ -2,11 +2,20 @@ module foo (input [3:0] I, output [3:0] O); assign O = I; endmodule -module top (input [3:0] self_I, output [3:0] O); +module top ( + input [3:0] self_I, + output [3:0] O +); wire [3:0] inst0_O; wire [3:0] inst1_O; -foo inst0(.I({self_I[2],self_I[1],self_I[0],self_I[0]}), .O(inst0_O)); -foo inst1(.I({self_I[1],inst0_O[1],inst0_O[1],inst0_O[0]}), .O(inst1_O)); +foo inst0 ( + .I({self_I[2],self_I[1],self_I[0],self_I[0]}), + .O(inst0_O) +); +foo inst1 ( + .I({self_I[1],inst0_O[1],inst0_O[1],inst0_O[0]}), + .O(inst1_O) +); assign O = {self_I[1],self_I[0],inst1_O[0],inst1_O[0]}; endmodule diff --git a/tests/gtest/blackbox_verilog_golden.v b/tests/gtest/blackbox_verilog_golden.v index 464c2024f..dbded3474 100644 --- a/tests/gtest/blackbox_verilog_golden.v +++ b/tests/gtest/blackbox_verilog_golden.v @@ -2,7 +2,13 @@ module foo (input I, output O); assign O = I; endmodule -module top (input I, output O); -foo inst0(.I(I), .O(O)); +module top ( + input I, + output O +); +foo inst0 ( + .I(I), + .O(O) +); endmodule diff --git a/tests/gtest/debug_info_golden.v b/tests/gtest/debug_info_golden.v index 246062c18..14191319e 100644 --- a/tests/gtest/debug_info_golden.v +++ b/tests/gtest/debug_info_golden.v @@ -1,6 +1,10 @@ // Module `Term2` defined externally // Module `And2` defined externally -module main (input [1:0] I, output O, output [1:0] O1); +module main ( + input [1:0] I, + output O, + output [1:0] O1 +); // Module `main` defined at tests/test_circuit/test_define.py:57 wire and2_0_O; wire and2_1_O; @@ -9,23 +13,41 @@ wire and2_3_O; // Instance `and2_0` created at tests/test_circuit/test_define.py:61 // Connection `(and2_0.I0, I[0])` created at tests/test_circuit/test_define.py:63 // Connection `(and2_0.I1, I[1])` created at tests/test_circuit/test_define.py:64 -And2 and2_0(.I0(I[0]), .I1(I[1]), .O(and2_0_O)); +And2 and2_0 ( + .I0(I[0]), + .I1(I[1]), + .O(and2_0_O) +); // Instance `and2_1` created at tests/test_circuit/test_define.py:61 // Connection `(and2_1.I0, and2_0_O)` created at tests/test_circuit/test_define.py:66 // Connection `(and2_1.I1, I[1])` created at tests/test_circuit/test_define.py:67 -And2 and2_1(.I0(and2_0_O), .I1(I[1]), .O(and2_1_O)); +And2 and2_1 ( + .I0(and2_0_O), + .I1(I[1]), + .O(and2_1_O) +); // Instance `and2_2` created at tests/test_circuit/test_define.py:61 // Connection `(and2_2.I0, and2_1_O)` created at tests/test_circuit/test_define.py:66 // Connection `(and2_2.I1, I[1])` created at tests/test_circuit/test_define.py:67 -And2 and2_2(.I0(and2_1_O), .I1(I[1]), .O(and2_2_O)); +And2 and2_2 ( + .I0(and2_1_O), + .I1(I[1]), + .O(and2_2_O) +); // Instance `and2_3` created at tests/test_circuit/test_define.py:61 // Connection `(and2_3.I0, and2_2_O)` created at tests/test_circuit/test_define.py:66 // Connection `(and2_3.I1, I[1])` created at tests/test_circuit/test_define.py:67 -And2 and2_3(.I0(and2_2_O), .I1(I[1]), .O(and2_3_O)); +And2 and2_3 ( + .I0(and2_2_O), + .I1(I[1]), + .O(and2_3_O) +); // Instance `term0` created at tests/test_circuit/test_define.py:77 // Connection `(term0.I[1], and2_2_O)` created at tests/test_circuit/test_define.py:103 // Connection `(term0.I[0], and2_3_O)` created at tests/test_circuit/test_define.py:99 -Term2 term0(.I({and2_2_O,and2_3_O})); +Term2 term0 ( + .I({and2_2_O,and2_3_O}) +); // Connection `(O, and2_3_O)` created at tests/test_circuit/test_define.py:70 assign O = and2_3_O; // Connection `(O1[0], and2_2_O)` created at tests/test_circuit/test_define.py:77 diff --git a/tests/gtest/inline_verilog_golden.v b/tests/gtest/inline_verilog_golden.v index 4da31b5b4..4804233a7 100644 --- a/tests/gtest/inline_verilog_golden.v +++ b/tests/gtest/inline_verilog_golden.v @@ -3,8 +3,16 @@ always @(posedge CLK) begin O <= I; end endmodule -module Main (input I, output O, input CLK); -FF FF_inst0(.I(I), .O(O), .CLK(CLK)); +module Main ( + input I, + output O, + input CLK +); +FF FF_inst0 ( + .I(I), + .O(O), + .CLK(CLK) +); assert property { @(posedge CLK) I |-> ##1 O }; diff --git a/tests/gtest/inline_verilog_top_golden.v b/tests/gtest/inline_verilog_top_golden.v index 4c858001e..7daa4de98 100644 --- a/tests/gtest/inline_verilog_top_golden.v +++ b/tests/gtest/inline_verilog_top_golden.v @@ -1,4 +1,21 @@ -module Monitor (input CLK, input handshake_arr_0_ready, input handshake_arr_0_valid, input handshake_arr_1_ready, input handshake_arr_1_valid, input handshake_arr_2_ready, input handshake_arr_2_valid, input handshake_ready, input handshake_valid, input [3:0] in1, input [3:0] in2, input intermediate_tuple__0, input intermediate_tuple__1, input mon_temp1, input mon_temp2, input out); +module Monitor ( + input CLK, + input handshake_arr_0_ready, + input handshake_arr_0_valid, + input handshake_arr_1_ready, + input handshake_arr_1_valid, + input handshake_arr_2_ready, + input handshake_arr_2_valid, + input handshake_ready, + input handshake_valid, + input [3:0] in1, + input [3:0] in2, + input intermediate_tuple__0, + input intermediate_tuple__1, + input mon_temp1, + input mon_temp2, + input out +); logic temp1, temp2; assign temp1 = |(in1); diff --git a/tests/gtest/intermediate_connection_golden.v b/tests/gtest/intermediate_connection_golden.v index e0bb1a310..2fa1e5865 100644 --- a/tests/gtest/intermediate_connection_golden.v +++ b/tests/gtest/intermediate_connection_golden.v @@ -3,12 +3,25 @@ module foo (input I, inout IO, output O); assign O = I; assign IO = I; endmodule -module top (input I, inout IO0, inout IO1, output O); +module top ( + input I, + inout IO0, + inout IO1, + output O +); wire inst0_IO; wire inst0_O; wire inst1_IO; -foo inst0(.I(I), .IO(inst0_IO), .O(inst0_O)); -foo inst1(.I(inst0_O), .IO(inst1_IO), .O(O)); +foo inst0 ( + .I(I), + .IO(inst0_IO), + .O(inst0_O) +); +foo inst1 ( + .I(inst0_O), + .IO(inst1_IO), + .O(O) +); assign inst0_IO = inst1_IO; assign IO0 = inst0_IO; assign inst0_IO = IO1; diff --git a/tests/gtest/mux_golden.v b/tests/gtest/mux_golden.v index b698fb2f9..b8c40c1ab 100644 --- a/tests/gtest/mux_golden.v +++ b/tests/gtest/mux_golden.v @@ -1,24 +1,93 @@ -module commonlib_muxn__N2__width8 (input [7:0] in_data_0, input [7:0] in_data_1, input [0:0] in_sel, output [7:0] out); +module commonlib_muxn__N2__width8 ( + input [7:0] in_data_0, + input [7:0] in_data_1, + input [0:0] in_sel, + output [7:0] out +); assign out = in_sel[0] ? in_data_1 : in_data_0; endmodule -module commonlib_muxn__N4__width8 (input [7:0] in_data_0, input [7:0] in_data_1, input [7:0] in_data_2, input [7:0] in_data_3, input [1:0] in_sel, output [7:0] out); +module commonlib_muxn__N4__width8 ( + input [7:0] in_data_0, + input [7:0] in_data_1, + input [7:0] in_data_2, + input [7:0] in_data_3, + input [1:0] in_sel, + output [7:0] out +); wire [7:0] muxN_0_out; wire [7:0] muxN_1_out; -commonlib_muxn__N2__width8 muxN_0(.in_data_0(in_data_0), .in_data_1(in_data_1), .in_sel(in_sel[1 - 1:0]), .out(muxN_0_out)); -commonlib_muxn__N2__width8 muxN_1(.in_data_0(in_data_2), .in_data_1(in_data_3), .in_sel(in_sel[1 - 1:0]), .out(muxN_1_out)); +commonlib_muxn__N2__width8 muxN_0 ( + .in_data_0(in_data_0), + .in_data_1(in_data_1), + .in_sel(in_sel[1 - 1:0]), + .out(muxN_0_out) +); +commonlib_muxn__N2__width8 muxN_1 ( + .in_data_0(in_data_2), + .in_data_1(in_data_3), + .in_sel(in_sel[1 - 1:0]), + .out(muxN_1_out) +); assign out = in_sel[1] ? muxN_1_out : muxN_0_out; endmodule -module commonlib_muxn__N8__width8 (input [7:0] in_data_0, input [7:0] in_data_1, input [7:0] in_data_2, input [7:0] in_data_3, input [7:0] in_data_4, input [7:0] in_data_5, input [7:0] in_data_6, input [7:0] in_data_7, input [2:0] in_sel, output [7:0] out); +module commonlib_muxn__N8__width8 ( + input [7:0] in_data_0, + input [7:0] in_data_1, + input [7:0] in_data_2, + input [7:0] in_data_3, + input [7:0] in_data_4, + input [7:0] in_data_5, + input [7:0] in_data_6, + input [7:0] in_data_7, + input [2:0] in_sel, + output [7:0] out +); wire [7:0] muxN_0_out; wire [7:0] muxN_1_out; -commonlib_muxn__N4__width8 muxN_0(.in_data_0(in_data_0), .in_data_1(in_data_1), .in_data_2(in_data_2), .in_data_3(in_data_3), .in_sel(in_sel[2 - 1:0]), .out(muxN_0_out)); -commonlib_muxn__N4__width8 muxN_1(.in_data_0(in_data_4), .in_data_1(in_data_5), .in_data_2(in_data_6), .in_data_3(in_data_7), .in_sel(in_sel[2 - 1:0]), .out(muxN_1_out)); +commonlib_muxn__N4__width8 muxN_0 ( + .in_data_0(in_data_0), + .in_data_1(in_data_1), + .in_data_2(in_data_2), + .in_data_3(in_data_3), + .in_sel(in_sel[2 - 1:0]), + .out(muxN_0_out) +); +commonlib_muxn__N4__width8 muxN_1 ( + .in_data_0(in_data_4), + .in_data_1(in_data_5), + .in_data_2(in_data_6), + .in_data_3(in_data_7), + .in_sel(in_sel[2 - 1:0]), + .out(muxN_1_out) +); assign out = in_sel[2] ? muxN_1_out : muxN_0_out; endmodule -module Mux8x8 (input [7:0] I0, input [7:0] I1, input [7:0] I2, input [7:0] I3, input [7:0] I4, input [7:0] I5, input [7:0] I6, input [7:0] I7, input [2:0] S, output [7:0] O); -commonlib_muxn__N8__width8 coreir_commonlib_mux8x8_inst0(.in_data_0(I0), .in_data_1(I1), .in_data_2(I2), .in_data_3(I3), .in_data_4(I4), .in_data_5(I5), .in_data_6(I6), .in_data_7(I7), .in_sel(S), .out(O)); +module Mux8x8 ( + input [7:0] I0, + input [7:0] I1, + input [7:0] I2, + input [7:0] I3, + input [7:0] I4, + input [7:0] I5, + input [7:0] I6, + input [7:0] I7, + input [2:0] S, + output [7:0] O +); +commonlib_muxn__N8__width8 coreir_commonlib_mux8x8_inst0 ( + .in_data_0(I0), + .in_data_1(I1), + .in_data_2(I2), + .in_data_3(I3), + .in_data_4(I4), + .in_data_5(I5), + .in_data_6(I6), + .in_data_7(I7), + .in_sel(S), + .out(O) +); endmodule diff --git a/tests/gtest/port_order_golden.v b/tests/gtest/port_order_golden.v index 221412319..be1ba69c3 100644 --- a/tests/gtest/port_order_golden.v +++ b/tests/gtest/port_order_golden.v @@ -1,12 +1,34 @@ -module Add8_cin (input [7:0] z, input [7:0] x, output [7:0] a, input CIN); +module Add8_cin ( + input [7:0] z, + input [7:0] x, + output [7:0] a, + input CIN +); assign a = (({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CIN}) + z) + x; endmodule -module Sub8 (input [7:0] z, input [7:0] x, output [7:0] a); -Add8_cin inst1(.z(z), .x(~ x), .a(a), .CIN(1'b1)); +module Sub8 ( + input [7:0] z, + input [7:0] x, + output [7:0] a +); +Add8_cin inst1 ( + .z(z), + .x(~ x), + .a(a), + .CIN(1'b1) +); endmodule -module test_two_ops (input [7:0] z, input [7:0] x, output [7:0] a); -Sub8 inst1(.z(z + x), .x(z), .a(a)); +module test_two_ops ( + input [7:0] z, + input [7:0] x, + output [7:0] a +); +Sub8 inst1 ( + .z(z + x), + .x(z), + .a(a) +); endmodule diff --git a/tests/gtest/register_mode_golden.v b/tests/gtest/register_mode_golden.v index c755601db..37175085c 100644 --- a/tests/gtest/register_mode_golden.v +++ b/tests/gtest/register_mode_golden.v @@ -1,4 +1,12 @@ -module coreir_reg #(parameter width = 1, parameter clk_posedge = 1, parameter init = 1) (input clk, input [width-1:0] in, output [width-1:0] out); +module coreir_reg #( + parameter width = 1, + parameter clk_posedge = 1, + parameter init = 1 +) ( + input clk, + input [width-1:0] in, + output [width-1:0] out +); reg [width-1:0] outReg=init; wire real_clk; assign real_clk = clk_posedge ? clk : ~clk; @@ -8,37 +16,109 @@ module coreir_reg #(parameter width = 1, parameter clk_posedge = 1, parameter in assign out = outReg; endmodule -module commonlib_muxn__N2__width4 (input [3:0] in_data_0, input [3:0] in_data_1, input [0:0] in_sel, output [3:0] out); +module commonlib_muxn__N2__width4 ( + input [3:0] in_data_0, + input [3:0] in_data_1, + input [0:0] in_sel, + output [3:0] out +); assign out = in_sel[0] ? in_data_1 : in_data_0; endmodule -module commonlib_muxn__N2__width1 (input [0:0] in_data_0, input [0:0] in_data_1, input [0:0] in_sel, output [0:0] out); +module commonlib_muxn__N2__width1 ( + input [0:0] in_data_0, + input [0:0] in_data_1, + input [0:0] in_sel, + output [0:0] out +); assign out = in_sel[0] ? in_data_1 : in_data_0; endmodule -module Mux2xOutBits4 (input [3:0] I0, input [3:0] I1, input S, output [3:0] O); -commonlib_muxn__N2__width4 coreir_commonlib_mux2x4_inst0(.in_data_0(I0), .in_data_1(I1), .in_sel(S), .out(O)); +module Mux2xOutBits4 ( + input [3:0] I0, + input [3:0] I1, + input S, + output [3:0] O +); +commonlib_muxn__N2__width4 coreir_commonlib_mux2x4_inst0 ( + .in_data_0(I0), + .in_data_1(I1), + .in_sel(S), + .out(O) +); endmodule -module Register_comb (input [3:0] value, input en, input [3:0] self_value_O, output [3:0] O0, output [3:0] O1); -Mux2xOutBits4 Mux2xOutBits4_inst0(.I0(self_value_O), .I1(value), .S(en), .O(O0)); +module Register_comb ( + input [3:0] value, + input en, + input [3:0] self_value_O, + output [3:0] O0, + output [3:0] O1 +); +Mux2xOutBits4 Mux2xOutBits4_inst0 ( + .I0(self_value_O), + .I1(value), + .S(en), + .O(O0) +); assign O1 = self_value_O; endmodule -module Register (input [3:0] value, input en, input CLK, output [3:0] O); +module Register ( + input [3:0] value, + input en, + input CLK, + output [3:0] O +); wire [3:0] Register_comb_inst0_O0; wire [3:0] reg_P_inst0_out; -Register_comb Register_comb_inst0(.value(value), .en(en), .self_value_O(reg_P_inst0_out), .O0(Register_comb_inst0_O0), .O1(O)); -coreir_reg #(.clk_posedge(1'b1), .init(4'h0), .width(4)) reg_P_inst0(.clk(CLK), .in(Register_comb_inst0_O0), .out(reg_P_inst0_out)); +Register_comb Register_comb_inst0 ( + .value(value), + .en(en), + .self_value_O(reg_P_inst0_out), + .O0(Register_comb_inst0_O0), + .O1(O) +); +coreir_reg #( + .clk_posedge(1'b1), + .init(4'h0), + .width(4) +) reg_P_inst0 ( + .clk(CLK), + .in(Register_comb_inst0_O0), + .out(reg_P_inst0_out) +); endmodule -module Mux2xOutBit (input I0, input I1, input S, output O); +module Mux2xOutBit ( + input I0, + input I1, + input S, + output O +); wire [0:0] coreir_commonlib_mux2x1_inst0_out; -commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0(.in_data_0(I0), .in_data_1(I1), .in_sel(S), .out(coreir_commonlib_mux2x1_inst0_out)); +commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 ( + .in_data_0(I0), + .in_data_1(I1), + .in_sel(S), + .out(coreir_commonlib_mux2x1_inst0_out) +); assign O = coreir_commonlib_mux2x1_inst0_out[0]; endmodule -module RegisterMode_comb (input [1:0] mode, input [3:0] const_, input [3:0] value, input clk_en, input config_we, input [3:0] config_data, input [3:0] self_register_O, output [3:0] O0, output O1, output [3:0] O2, output [3:0] O3); +module RegisterMode_comb ( + input [1:0] mode, + input [3:0] const_, + input [3:0] value, + input clk_en, + input config_we, + input [3:0] config_data, + input [3:0] self_register_O, + output [3:0] O0, + output O1, + output [3:0] O2, + output [3:0] O3 +); wire Mux2xOutBit_inst0_O; wire Mux2xOutBit_inst1_O; wire Mux2xOutBit_inst2_O; @@ -56,34 +136,166 @@ wire [3:0] Mux2xOutBits4_inst6_O; wire [3:0] Mux2xOutBits4_inst7_O; wire [3:0] Mux2xOutBits4_inst8_O; wire [3:0] Mux2xOutBits4_inst9_O; -Mux2xOutBit Mux2xOutBit_inst0(.I0(clk_en), .I1(1'b0), .S(mode == 2'h1), .O(Mux2xOutBit_inst0_O)); -Mux2xOutBit Mux2xOutBit_inst1(.I0(Mux2xOutBit_inst0_O), .I1(1'b0), .S(mode == 2'h0), .O(Mux2xOutBit_inst1_O)); -Mux2xOutBit Mux2xOutBit_inst2(.I0(Mux2xOutBit_inst1_O), .I1(1'b1), .S(~ (config_we ^ 1'b1)), .O(Mux2xOutBit_inst2_O)); -Mux2xOutBit Mux2xOutBit_inst3(.I0(clk_en), .I1(1'b0), .S(mode == 2'h1), .O(Mux2xOutBit_inst3_O)); -Mux2xOutBit Mux2xOutBit_inst4(.I0(Mux2xOutBit_inst3_O), .I1(1'b0), .S(mode == 2'h0), .O(Mux2xOutBit_inst4_O)); -Mux2xOutBit Mux2xOutBit_inst5(.I0(Mux2xOutBit_inst4_O), .I1(1'b1), .S(~ (config_we ^ 1'b1)), .O(O1)); -Mux2xOutBits4 Mux2xOutBits4_inst0(.I0(value), .I1(value), .S(mode == 2'h1), .O(Mux2xOutBits4_inst0_O)); -Mux2xOutBits4 Mux2xOutBits4_inst1(.I0(self_register_O), .I1(self_register_O), .S(mode == 2'h1), .O(Mux2xOutBits4_inst1_O)); -Mux2xOutBits4 Mux2xOutBits4_inst10(.I0(Mux2xOutBits4_inst7_O), .I1(const_), .S(mode == 2'h0), .O(Mux2xOutBits4_inst10_O)); -Mux2xOutBits4 Mux2xOutBits4_inst11(.I0(Mux2xOutBits4_inst8_O), .I1(self_register_O), .S(mode == 2'h0), .O(Mux2xOutBits4_inst11_O)); -Mux2xOutBits4 Mux2xOutBits4_inst12(.I0(Mux2xOutBits4_inst9_O), .I1(config_data), .S(~ (config_we ^ 1'b1)), .O(O0)); -Mux2xOutBits4 Mux2xOutBits4_inst13(.I0(Mux2xOutBits4_inst10_O), .I1(self_register_O), .S(~ (config_we ^ 1'b1)), .O(O2)); -Mux2xOutBits4 Mux2xOutBits4_inst14(.I0(Mux2xOutBits4_inst11_O), .I1(self_register_O), .S(~ (config_we ^ 1'b1)), .O(O3)); -Mux2xOutBits4 Mux2xOutBits4_inst2(.I0(Mux2xOutBits4_inst0_O), .I1(value), .S(mode == 2'h0), .O(Mux2xOutBits4_inst2_O)); -Mux2xOutBits4 Mux2xOutBits4_inst3(.I0(Mux2xOutBits4_inst1_O), .I1(self_register_O), .S(mode == 2'h0), .O(Mux2xOutBits4_inst3_O)); -Mux2xOutBits4 Mux2xOutBits4_inst4(.I0(Mux2xOutBits4_inst2_O), .I1(config_data), .S(~ (config_we ^ 1'b1)), .O(Mux2xOutBits4_inst4_O)); -Mux2xOutBits4 Mux2xOutBits4_inst5(.I0(Mux2xOutBits4_inst3_O), .I1(self_register_O), .S(~ (config_we ^ 1'b1)), .O(Mux2xOutBits4_inst5_O)); -Mux2xOutBits4 Mux2xOutBits4_inst6(.I0(value), .I1(value), .S(mode == 2'h1), .O(Mux2xOutBits4_inst6_O)); -Mux2xOutBits4 Mux2xOutBits4_inst7(.I0(self_register_O), .I1(value), .S(mode == 2'h1), .O(Mux2xOutBits4_inst7_O)); -Mux2xOutBits4 Mux2xOutBits4_inst8(.I0(self_register_O), .I1(self_register_O), .S(mode == 2'h1), .O(Mux2xOutBits4_inst8_O)); -Mux2xOutBits4 Mux2xOutBits4_inst9(.I0(Mux2xOutBits4_inst6_O), .I1(value), .S(mode == 2'h0), .O(Mux2xOutBits4_inst9_O)); +Mux2xOutBit Mux2xOutBit_inst0 ( + .I0(clk_en), + .I1(1'b0), + .S(mode == 2'h1), + .O(Mux2xOutBit_inst0_O) +); +Mux2xOutBit Mux2xOutBit_inst1 ( + .I0(Mux2xOutBit_inst0_O), + .I1(1'b0), + .S(mode == 2'h0), + .O(Mux2xOutBit_inst1_O) +); +Mux2xOutBit Mux2xOutBit_inst2 ( + .I0(Mux2xOutBit_inst1_O), + .I1(1'b1), + .S(~ (config_we ^ 1'b1)), + .O(Mux2xOutBit_inst2_O) +); +Mux2xOutBit Mux2xOutBit_inst3 ( + .I0(clk_en), + .I1(1'b0), + .S(mode == 2'h1), + .O(Mux2xOutBit_inst3_O) +); +Mux2xOutBit Mux2xOutBit_inst4 ( + .I0(Mux2xOutBit_inst3_O), + .I1(1'b0), + .S(mode == 2'h0), + .O(Mux2xOutBit_inst4_O) +); +Mux2xOutBit Mux2xOutBit_inst5 ( + .I0(Mux2xOutBit_inst4_O), + .I1(1'b1), + .S(~ (config_we ^ 1'b1)), + .O(O1) +); +Mux2xOutBits4 Mux2xOutBits4_inst0 ( + .I0(value), + .I1(value), + .S(mode == 2'h1), + .O(Mux2xOutBits4_inst0_O) +); +Mux2xOutBits4 Mux2xOutBits4_inst1 ( + .I0(self_register_O), + .I1(self_register_O), + .S(mode == 2'h1), + .O(Mux2xOutBits4_inst1_O) +); +Mux2xOutBits4 Mux2xOutBits4_inst10 ( + .I0(Mux2xOutBits4_inst7_O), + .I1(const_), + .S(mode == 2'h0), + .O(Mux2xOutBits4_inst10_O) +); +Mux2xOutBits4 Mux2xOutBits4_inst11 ( + .I0(Mux2xOutBits4_inst8_O), + .I1(self_register_O), + .S(mode == 2'h0), + .O(Mux2xOutBits4_inst11_O) +); +Mux2xOutBits4 Mux2xOutBits4_inst12 ( + .I0(Mux2xOutBits4_inst9_O), + .I1(config_data), + .S(~ (config_we ^ 1'b1)), + .O(O0) +); +Mux2xOutBits4 Mux2xOutBits4_inst13 ( + .I0(Mux2xOutBits4_inst10_O), + .I1(self_register_O), + .S(~ (config_we ^ 1'b1)), + .O(O2) +); +Mux2xOutBits4 Mux2xOutBits4_inst14 ( + .I0(Mux2xOutBits4_inst11_O), + .I1(self_register_O), + .S(~ (config_we ^ 1'b1)), + .O(O3) +); +Mux2xOutBits4 Mux2xOutBits4_inst2 ( + .I0(Mux2xOutBits4_inst0_O), + .I1(value), + .S(mode == 2'h0), + .O(Mux2xOutBits4_inst2_O) +); +Mux2xOutBits4 Mux2xOutBits4_inst3 ( + .I0(Mux2xOutBits4_inst1_O), + .I1(self_register_O), + .S(mode == 2'h0), + .O(Mux2xOutBits4_inst3_O) +); +Mux2xOutBits4 Mux2xOutBits4_inst4 ( + .I0(Mux2xOutBits4_inst2_O), + .I1(config_data), + .S(~ (config_we ^ 1'b1)), + .O(Mux2xOutBits4_inst4_O) +); +Mux2xOutBits4 Mux2xOutBits4_inst5 ( + .I0(Mux2xOutBits4_inst3_O), + .I1(self_register_O), + .S(~ (config_we ^ 1'b1)), + .O(Mux2xOutBits4_inst5_O) +); +Mux2xOutBits4 Mux2xOutBits4_inst6 ( + .I0(value), + .I1(value), + .S(mode == 2'h1), + .O(Mux2xOutBits4_inst6_O) +); +Mux2xOutBits4 Mux2xOutBits4_inst7 ( + .I0(self_register_O), + .I1(value), + .S(mode == 2'h1), + .O(Mux2xOutBits4_inst7_O) +); +Mux2xOutBits4 Mux2xOutBits4_inst8 ( + .I0(self_register_O), + .I1(self_register_O), + .S(mode == 2'h1), + .O(Mux2xOutBits4_inst8_O) +); +Mux2xOutBits4 Mux2xOutBits4_inst9 ( + .I0(Mux2xOutBits4_inst6_O), + .I1(value), + .S(mode == 2'h0), + .O(Mux2xOutBits4_inst9_O) +); endmodule -module RegisterMode (input [1:0] mode, input [3:0] const_, input [3:0] value, input clk_en, input config_we, input [3:0] config_data, input CLK, output [3:0] O0, output [3:0] O1); +module RegisterMode ( + input [1:0] mode, + input [3:0] const_, + input [3:0] value, + input clk_en, + input config_we, + input [3:0] config_data, + input CLK, + output [3:0] O0, + output [3:0] O1 +); wire [3:0] RegisterMode_comb_inst0_O0; wire RegisterMode_comb_inst0_O1; wire [3:0] Register_inst0_O; -RegisterMode_comb RegisterMode_comb_inst0(.mode(mode), .const_(const_), .value(value), .clk_en(clk_en), .config_we(config_we), .config_data(config_data), .self_register_O(Register_inst0_O), .O0(RegisterMode_comb_inst0_O0), .O1(RegisterMode_comb_inst0_O1), .O2(O0), .O3(O1)); -Register Register_inst0(.value(RegisterMode_comb_inst0_O0), .en(RegisterMode_comb_inst0_O1), .CLK(CLK), .O(Register_inst0_O)); +RegisterMode_comb RegisterMode_comb_inst0 ( + .mode(mode), + .const_(const_), + .value(value), + .clk_en(clk_en), + .config_we(config_we), + .config_data(config_data), + .self_register_O(Register_inst0_O), + .O0(RegisterMode_comb_inst0_O0), + .O1(RegisterMode_comb_inst0_O1), + .O2(O0), + .O3(O1) +); +Register Register_inst0 ( + .value(RegisterMode_comb_inst0_O0), + .en(RegisterMode_comb_inst0_O1), + .CLK(CLK), + .O(Register_inst0_O) +); endmodule diff --git a/tests/gtest/two_ops_bit_golden.v b/tests/gtest/two_ops_bit_golden.v index 55dc4e9b0..8e688d0b9 100644 --- a/tests/gtest/two_ops_bit_golden.v +++ b/tests/gtest/two_ops_bit_golden.v @@ -1,4 +1,11 @@ -module Top (input I, input I1, input I2, input I3, output O, output O1); +module Top ( + input I, + input I1, + input I2, + input I3, + output O, + output O1 +); assign O = (I ^ I) | ((~ I) & 1'b1); assign O1 = I3 ? I2 : I1; endmodule diff --git a/tests/gtest/two_ops_golden.v b/tests/gtest/two_ops_golden.v index 6af2cc7f8..e255f1a3e 100644 --- a/tests/gtest/two_ops_golden.v +++ b/tests/gtest/two_ops_golden.v @@ -1,12 +1,34 @@ -module Add8_cin (input [7:0] I0, input [7:0] I1, output [7:0] O, input CIN); +module Add8_cin ( + input [7:0] I0, + input [7:0] I1, + output [7:0] O, + input CIN +); assign O = (({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CIN}) + I0) + I1; endmodule -module Sub8 (input [7:0] I0, input [7:0] I1, output [7:0] O); -Add8_cin inst1(.I0(I0), .I1(~ I1), .O(O), .CIN(1'b1)); +module Sub8 ( + input [7:0] I0, + input [7:0] I1, + output [7:0] O +); +Add8_cin inst1 ( + .I0(I0), + .I1(~ I1), + .O(O), + .CIN(1'b1) +); endmodule -module test_two_ops (input [7:0] I0, input [7:0] I1, output [7:0] O); -Sub8 inst1(.I0(I0 + I1), .I1(I0), .O(O)); +module test_two_ops ( + input [7:0] I0, + input [7:0] I1, + output [7:0] O +); +Sub8 inst1 ( + .I0(I0 + I1), + .I1(I0), + .O(O) +); endmodule diff --git a/tests/gtest/undriven_golden.v b/tests/gtest/undriven_golden.v index 1deaa6160..be82b05f4 100644 --- a/tests/gtest/undriven_golden.v +++ b/tests/gtest/undriven_golden.v @@ -1,13 +1,28 @@ -module coreir_undriven #(parameter width = 1) (output [width-1:0] out); +module coreir_undriven #( + parameter width = 1 +) ( + output [width-1:0] out +); endmodule -module corebit_undriven (output out); +module corebit_undriven ( + output out +); endmodule -module Top (output O0, output [7:0] O1); -corebit_undriven inst0(.out(O0)); -coreir_undriven #(.width(8)) inst1(.out(O1)); +module Top ( + output O0, + output [7:0] O1 +); +corebit_undriven inst0 ( + .out(O0) +); +coreir_undriven #( + .width(8) +) inst1 ( + .out(O1) +); endmodule diff --git a/tests/gtest/verilator_debug_inline_golden.v b/tests/gtest/verilator_debug_inline_golden.v index a5a23db45..66ed6bb54 100644 --- a/tests/gtest/verilator_debug_inline_golden.v +++ b/tests/gtest/verilator_debug_inline_golden.v @@ -1,8 +1,15 @@ -module Top_comb (output O_A/*verilator public*/); +module Top_comb ( + output O_A/*verilator public*/ +); assign O_A = 1'b0; endmodule -module Top (input CLK/*verilator public*/, output O_A/*verilator public*/); -Top_comb Top_comb_inst0(.O_A(O_A)); +module Top ( + input CLK/*verilator public*/, + output O_A/*verilator public*/ +); +Top_comb Top_comb_inst0 ( + .O_A(O_A) +); endmodule diff --git a/tests/unit/gold/ice40_pll_verilog.v b/tests/unit/gold/ice40_pll_verilog.v index 75056839b..567c3964a 100644 --- a/tests/unit/gold/ice40_pll_verilog.v +++ b/tests/unit/gold/ice40_pll_verilog.v @@ -1,8 +1,27 @@ // Module `SB_PLL40_CORE` defined externally -module top (input clk, input reset, input in, output out, output outClk); +module top ( + input clk, + input reset, + input in, + output out, + output outClk +); wire pll_PLLOUTCORE; wire pll_PLLOUTGLOBAL; -SB_PLL40_CORE #(.DIVF(7'h21), .DIVQ(3'h4), .DIVR(4'h0), .FEEDBACK_PATH("SIMPLE"), .FILTER_RANGE(3'h1), .PLLOUT_SELECT("GENCLK")) pll(.BYPASS(in), .PLLOUTCORE(pll_PLLOUTCORE), .PLLOUTGLOBAL(pll_PLLOUTGLOBAL), .REFERENCECLK(clk), .RESETB(reset)); +SB_PLL40_CORE #( + .DIVF(7'h21), + .DIVQ(3'h4), + .DIVR(4'h0), + .FEEDBACK_PATH("SIMPLE"), + .FILTER_RANGE(3'h1), + .PLLOUT_SELECT("GENCLK") +) pll ( + .BYPASS(in), + .PLLOUTCORE(pll_PLLOUTCORE), + .PLLOUTGLOBAL(pll_PLLOUTGLOBAL), + .REFERENCECLK(clk), + .RESETB(reset) +); assign out = pll_PLLOUTCORE; assign outClk = pll_PLLOUTGLOBAL; endmodule diff --git a/tests/unit/gold/ice40_ram_verilog.v b/tests/unit/gold/ice40_ram_verilog.v index fcc801e2f..fc8e350c3 100644 --- a/tests/unit/gold/ice40_ram_verilog.v +++ b/tests/unit/gold/ice40_ram_verilog.v @@ -1,7 +1,50 @@ // Module `SB_RAM40_4K` defined externally -module top (input [15:0] MASK, input [10:0] RADDR, input RCLK, input RCLKE, output [15:0] RDATA, input RE, input [10:0] WADDR, input WCLK, input WCLKE, input [15:0] WDATA, input WE); +module top ( + input [15:0] MASK, + input [10:0] RADDR, + input RCLK, + input RCLKE, + output [15:0] RDATA, + input RE, + input [10:0] WADDR, + input WCLK, + input WCLKE, + input [15:0] WDATA, + input WE +); wire [15:0] SB_RAM40_4K_inst0_RDATA; -SB_RAM40_4K #(.INIT_0(256'h0000000000000000000000000000000000000000000000000000000000ff00fe), .INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000), .READ_MODE(0), .WRITE_MODE(0)) SB_RAM40_4K_inst0(.RDATA(SB_RAM40_4K_inst0_RDATA), .RADDR(RADDR), .RCLK(RCLK), .RCLKE(RCLKE), .RE(RE), .WCLK(WCLK), .WCLKE(WCLKE), .WE(WE), .WADDR(WADDR), .MASK(MASK), .WDATA(WDATA)); +SB_RAM40_4K #( + .INIT_0(256'h0000000000000000000000000000000000000000000000000000000000ff00fe), + .INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .READ_MODE(0), + .WRITE_MODE(0) +) SB_RAM40_4K_inst0 ( + .RDATA(SB_RAM40_4K_inst0_RDATA), + .RADDR(RADDR), + .RCLK(RCLK), + .RCLKE(RCLKE), + .RE(RE), + .WCLK(WCLK), + .WCLKE(WCLKE), + .WE(WE), + .WADDR(WADDR), + .MASK(MASK), + .WDATA(WDATA) +); assign RDATA = SB_RAM40_4K_inst0_RDATA; endmodule