From 4d710f2b128ff511d6d4b2389dd9fc4f7be70acc Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 21 Feb 2020 15:13:44 -0800 Subject: [PATCH] Update RAM gold --- tests/unit/gold/ice40_ram_verilog.v | 47 +++++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/tests/unit/gold/ice40_ram_verilog.v b/tests/unit/gold/ice40_ram_verilog.v index fcc801e2f..fc8e350c3 100644 --- a/tests/unit/gold/ice40_ram_verilog.v +++ b/tests/unit/gold/ice40_ram_verilog.v @@ -1,7 +1,50 @@ // Module `SB_RAM40_4K` defined externally -module top (input [15:0] MASK, input [10:0] RADDR, input RCLK, input RCLKE, output [15:0] RDATA, input RE, input [10:0] WADDR, input WCLK, input WCLKE, input [15:0] WDATA, input WE); +module top ( + input [15:0] MASK, + input [10:0] RADDR, + input RCLK, + input RCLKE, + output [15:0] RDATA, + input RE, + input [10:0] WADDR, + input WCLK, + input WCLKE, + input [15:0] WDATA, + input WE +); wire [15:0] SB_RAM40_4K_inst0_RDATA; -SB_RAM40_4K #(.INIT_0(256'h0000000000000000000000000000000000000000000000000000000000ff00fe), .INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000), .READ_MODE(0), .WRITE_MODE(0)) SB_RAM40_4K_inst0(.RDATA(SB_RAM40_4K_inst0_RDATA), .RADDR(RADDR), .RCLK(RCLK), .RCLKE(RCLKE), .RE(RE), .WCLK(WCLK), .WCLKE(WCLKE), .WE(WE), .WADDR(WADDR), .MASK(MASK), .WDATA(WDATA)); +SB_RAM40_4K #( + .INIT_0(256'h0000000000000000000000000000000000000000000000000000000000ff00fe), + .INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000), + .INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000), + .READ_MODE(0), + .WRITE_MODE(0) +) SB_RAM40_4K_inst0 ( + .RDATA(SB_RAM40_4K_inst0_RDATA), + .RADDR(RADDR), + .RCLK(RCLK), + .RCLKE(RCLKE), + .RE(RE), + .WCLK(WCLK), + .WCLKE(WCLKE), + .WE(WE), + .WADDR(WADDR), + .MASK(MASK), + .WDATA(WDATA) +); assign RDATA = SB_RAM40_4K_inst0_RDATA; endmodule