From 6cb5980d6b58bab1936c2f4b563ad215c894671a Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 13 Jan 2020 07:06:55 -0800 Subject: [PATCH] Test bit mux inline --- tests/gtest/two_ops_bit.json | 53 ++++++++++++++++++++++++++++++++ tests/gtest/two_ops_bit_golden.v | 5 +++ 2 files changed, 58 insertions(+) create mode 100644 tests/gtest/two_ops_bit.json create mode 100644 tests/gtest/two_ops_bit_golden.v diff --git a/tests/gtest/two_ops_bit.json b/tests/gtest/two_ops_bit.json new file mode 100644 index 000000000..c509c8579 --- /dev/null +++ b/tests/gtest/two_ops_bit.json @@ -0,0 +1,53 @@ +{"top":"global.Top", +"namespaces":{ + "global":{ + "modules":{ + "Top":{ + "type":["Record",[ + ["I","BitIn"], + ["I1","BitIn"], + ["I2","BitIn"], + ["I3","BitIn"], + ["O","Bit"], + ["O1","Bit"] + ]], + "instances":{ + "bit_const_1_None":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "magma_Bit_and_inst0":{ + "modref":"corebit.and" + }, + "magma_Bit_not_inst0":{ + "modref":"corebit.not" + }, + "magma_Bit_or_inst0":{ + "modref":"corebit.or" + }, + "magma_Bit_xor_inst0":{ + "modref":"corebit.xor" + }, + "test_mux":{ + "modref":"corebit.mux" + } + }, + "connections":[ + ["magma_Bit_and_inst0.in1","bit_const_1_None.out"], + ["magma_Bit_not_inst0.out","magma_Bit_and_inst0.in0"], + ["magma_Bit_or_inst0.in1","magma_Bit_and_inst0.out"], + ["self.I","magma_Bit_not_inst0.in"], + ["magma_Bit_xor_inst0.out","magma_Bit_or_inst0.in0"], + ["self.O","magma_Bit_or_inst0.out"], + ["self.I","magma_Bit_xor_inst0.in0"], + ["self.I","magma_Bit_xor_inst0.in1"], + ["self.I1","test_mux.in0"], + ["self.I2","test_mux.in1"], + ["self.I3","test_mux.sel"], + ["self.O1","test_mux.out"] + ] + } + } + } +} +} diff --git a/tests/gtest/two_ops_bit_golden.v b/tests/gtest/two_ops_bit_golden.v new file mode 100644 index 000000000..55dc4e9b0 --- /dev/null +++ b/tests/gtest/two_ops_bit_golden.v @@ -0,0 +1,5 @@ +module Top (input I, input I1, input I2, input I3, output O, output O1); +assign O = (I ^ I) | ((~ I) & 1'b1); +assign O1 = I3 ? I2 : I1; +endmodule +