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Syntroids

A game synthesized for FPGAs from Temporal Stream Logic

Requirements

TSL-tools

You need the TSL-toolchain to convert TSL specifications to the Temporal Logic Synthesis Format (TLSF) and to convert the control flow model to code of a FRP-framework.

Synthesis tool

You need a TLSF-compatible LTL-synthesis tool. We used the following ones

Note that different synthesis tools might vary in recource usage and the size of the outputed control flow model.

Clash

You need the Clash HDL used as the FRP-Framework, generating verilog code:

Due to active development of Clash, we recommend to git checkout fff460634d80db6f4add2b887cea22c2d937fc35 before building the compiler.

Hardware

You may not need the following tools depending on whether you want work on generated verilog code or rebuild the whole physical system.

Yosys

You need the Yosys Open SYnthesis Suite to synthesize the generated verilog code.

Nextpnr

You need nextpnr a vendor neutral, timing driven, FOSS FPGA place and route tool.

Icestorm

You need the IceStorm tools.

Icotools

You need the icoprog programming tool for IcoBoards.

Usage

We include a Makefile, be sure to configure a build.cfg. It features the following functionality:

  • make tlsf converts all TSL specifications to TLSF
  • make check executes tslcheck on all TSL specifications
  • make <filename>.aag synthsizes the specification <filename>.tsl using strix
  • make strix/<filename>.hs generates corresponding Clash code, plus the above if not already synthesized
  • make <filename>.bosy synthsizes the specification <filename>.tsl using bosy
  • make bosy/<filename>.hs generates corresponding Clash code, plus the above if not already synthesized

After acquiring a .hs file for every specification, copy them to the clash folder. You can then compile the game to Verilog code using a simple make.