Zce architecture tests #6

jjscheel · 2023-03-16T20:19:07Z

jjscheel · 2023-04-13T11:48:56Z

Per 4/11 email from Prasanna:

Code size reduction: First set of test cases are written, they are being tested against Spike, dei run is in progress until the tests are pass - in progress

ptprasanna · 2023-04-25T04:19:55Z

No progress made since last Call. Was busy on Zfinx.

jjscheel · 2023-05-01T23:31:07Z

Ok. Please keep this as a focus item. We need to start showing progress here.

ptprasanna · 2023-05-09T14:08:41Z

The dry of the tests designed was resumed against SPIKE, still seeing few failures. Fixing/Modifying the tests/frameworks is underway.

jjscheel · 2023-05-09T17:00:33Z

Glad we are once again making progress!

jjscheel · 2023-05-23T14:23:18Z

@ptprasanna, any update?

jjscheel · 2023-05-23T14:45:58Z

@pz9115, raising this to your attention as @ptprasanna is working a possible toolchain issue.

ptprasanna · 2023-05-23T14:51:33Z

Possibly an issue, but discussing with @Abdulwadoodd to get different point of view, before we conclude the issue with the tool chain. Also discussing with @pz9115 as well.

jjscheel · 2023-05-23T20:27:30Z

Feed back from @Abdulwadoodd:

Toolchain works fine for Zce.
The error you are getting is because of illegal operands of instructions: The immediate offset of the instructions in the generated tests are incorrect.
If you look at the spec, c.lb* , c.lh* instructions only allowed to have 2-bit unsigned immediate offset (at max) which is not the case for your tests and hence the compilation error.
Do look the reserved lsb of unimm as well

You can try compiling the instruction like:
c.lh x10, 0(x12)
c.lh x8, 2(x13)

And it would work with the toolchain.

I hope this resolves your issue.

ptprasanna · 2023-06-13T10:23:02Z

Zcf - Tests are generated using CTG, but the execution is not successful. Possibly a tool-chain issue (assuming), or the generated test are wrong. Still investigating.
Zcd - Tests are generated using CTG, but the execution is not successful. Possibly a tool-chain issue (assuming), or the generated test are wrong. Still investigating.
Zcb - Tests are generated, but few cover-points are not meeting up, we are getting them sorted
Zcmp - Yet to start the tests
Zcmt - Yet to start the tests

jjscheel · 2023-06-13T13:29:06Z

Thanks, @ptprasanna! Will remove from Agenda for this week. Please feel free to reach out if you need technical assistance debugging.

jjscheel · 2023-07-19T12:22:12Z

@ptprasanna, please update status here.

anuani21 · 2023-07-20T07:06:29Z

Regarding Zcf and Zcd extension, possibly an toolchain issue(assuming) and discussed with @pz9115.

Got a feedback from @pz9115,

1.Since Zce is not upstream yet,need to checkout gcc and binutils into the downstream repo,

Gcc: https://github.com/openhwgroup/corev-gcc/commits/development-08dd5f65b06
Binutils: https://github.com/openhwgroup/corev-binutils-gdb/commits/development-eddf4096b97

Use compile args -march= rv32imaf_zcf -mabi=ilp32f.
As per specification definition,need to discard zcmb extension.

As per the feedback,I have done all the changes but still I am facing the same issue. @pz9115, Can you give me any suggestions to resolve the issue?

pz9115 · 2023-07-24T14:12:11Z

Regarding Zcf and Zcd extension, possibly an toolchain issue(assuming) and discussed with @pz9115.

Got a feedback from @pz9115,

1.Since Zce is not upstream yet,need to checkout gcc and binutils into the downstream repo,

Gcc: https://github.com/openhwgroup/corev-gcc/commits/development-08dd5f65b06 Binutils: https://github.com/openhwgroup/corev-binutils-gdb/commits/development-eddf4096b97

Use compile args -march= rv32imaf_zcf -mabi=ilp32f.

As per specification definition,need to discard zcmb extension.

As per the feedback,I have done all the changes but still I am facing the same issue. @pz9115, Can you give me any suggestions to resolve the issue?

Hi @anuani21, Can you provide the error log for me to learn more about the cause of the error, thanks.

anuani21 · 2023-07-25T06:10:13Z

Hi @pz9115,

Here I have attached the error log for your reference.

error-log.odt

pz9115 · 2023-07-25T12:53:46Z

Hi @pz9115,

Here I have attached the error log for your reference.

error-log.odt

Hi @anuani21, I found some compressed instructions that used in the log file, such as:

c.flw f15,-0x4(f15)
c.flw f14,0x0(f13)
c.flw f12,0x28(f11)

Where you use fpr as the second operand. As the instruction defination, it load from memory, computes an effective address by adding the zero-extended as offset scaled by 4.

So you should use gpr instead fpr as the second operand and set the offset positive and multiple it 4, such as:

c.flw f15,0x4(x15)
c.flw f14,0x0(x13)
c.flw f12,0x28(x11)

Abdulwadoodd · 2023-08-21T02:53:34Z

Hi @ptprasanna, @jjscheel

RISC-V Config PR is merged which adds support of Code size reduction extension to riscv-config tool
PR link: riscv-software-src/riscv-config#129

This was critical because RISCOF and ISAC use riscv config to run tests and generate coverage reports respectively. One can run Zce ACTs using RISCOF by updating the riscv-config version.

anuani21 · 2024-09-17T04:03:12Z

@jjscheel,

No progress made since last Call. Was busy on Debug ACT for Native Triggers.

anuani21 · 2024-10-01T10:20:23Z

@jjscheel,

Updates from IITM,

There are five sub-extensions in Zce

Zcb -it is already merged.
Zcf -Raised a PR.
Zcd - Raised a PR.
- Riscv-ctg : Add support for Zcf and Zcd extension riscv-software-src/riscv-ctg#122
- Riscv-isac: Add support for Zcf and Zcd extension riscv-software-src/riscv-isac#100
- Riscv-arch-test: [ACT] [CTG] [ISAC] Add support for Zcf and Zcd extension riscv-non-isa/riscv-arch-test#497
Zcmp - popret and popretz instructions are pending.
5.. Zcmt- completed. Need to raise a Pr along with zcmp extension

We will complete Zcmp and raise a PR for Zcmp and Zcmt extension together before the next meeting.

jjscheel · 2024-10-01T12:03:23Z

Great. THANKS!!!

anuani21 · 2024-10-15T03:59:15Z

@jjscheel,

Updates from IITM,

Zcf&Zcd extension:
Re-submiited the PR in riscv-ctg and riscv-isac into riscv-arch-test [ACT] [CTG] [ISAC] Add support for Zcf and Zcd extension riscv-non-isa/riscv-arch-test#497
Zcmp and Zcmt extension: We will raise a PR within this week.

JAYANTH-IITM · 2024-10-29T04:33:16Z

Update :
I am currently working on ACT for Zcmp and Zcmt .

While running the test I am encounter this assembler error which is saying "Zcm* is not compatible with C extension" .
I have raised the same issue in arch-test repo (riscv-non-isa/riscv-arch-test#543) in which allen suggested to include c in ISA ( RV32ICZicsr_Zca_Zcmp ) , but even after that the error was not resolved .

I asked tariq sir also about this error , to which sir suggested it might be toolchain bug.

@pz9115 sir can you please help me here . I have attched ss of the error
Image

pz9115 · 2024-10-29T14:25:12Z

Update : I am currently working on ACT for Zcmp and Zcmt .

While running the test I am encounter this assembler error which is saying "Zcm* is not compatible with C extension" . I have raised the same issue in arch-test repo (riscv-non-isa/riscv-arch-test#543) in which allen suggested to include c in ISA ( RV32ICZicsr_Zca_Zcmp ) , but even after that the error was not resolved .

I asked tariq sir also about this error , to which sir suggested it might be toolchain bug.

@pz9115 sir can you please help me here . I have attched ss of the error Image

@JAYANTH-IITM I think this is cause by the toolchain version issue, we'd better update both gcc and binutils to the latest upstream line.
There is no release version of riscv-gnu-toolchain yet, which means we need to build it manually, here is the steps:

First, use git clone get the riscv-gnu-toolchain

git clone https://github.com/riscv-collab/riscv-gnu-toolchain.git

Then we need to prepare the environment, On Ubuntu, executing the following command should suffice:

$ sudo apt-get install autoconf automake autotools-dev curl python3 python3-pip libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev ninja-build git cmake libglib2.0-dev libslirp-dev

The next step, go into subdir gcc and binutils, update the code to the upstream version:

cd gcc
git fetch origin
git checkout origin/trunk
cd ../binutils
git fetch origin
git checkout origin/trunk

After this, we need to set the toolchain installation directory(in --prefix=, like /opt/riscv) and build it(the time cost based on your CPU performance, usually it takes about half an hour）

./configure --prefix=/opt/riscv --with-arch=rv32ic_zicsr_zca_zcmp --with-abi=ilp32
make -j$(nproc)

If you meet any problems in toolchain, please feel free to ask me at anytime.

IC41558-IITM · 2024-10-29T14:28:57Z

Thank you sir . will update the toolchain and redo the tests .

JAYANTH-IITM · 2024-11-02T10:12:28Z

Hi @pz9115 ,
I need both zcmp and zcmt , so in arch do use (-with-arch=rv32ic_zicsr_zca_zcmp_zcmt ) , or do i need to do it separately ( one with _zcmp and another with _zcmt )

pz9115 · 2024-11-02T10:35:20Z

Hi @pz9115 , I need both zcmp and zcmt , so in arch do use (-with-arch=rv32ic_zicsr_zca_zcmp_zcmt ) , or do i need to do it separately ( one with _zcmp and another with _zcmt )

Hi @JAYANTH-IITM ,it needs to use the first form I think(-with-arch=rv32ic_zicsr_zca_zcmp_zcmt), but currently zcmt haven't merged in upstream yet,. It means that you need to apply the zcmt patch into binutils and then re-build the toolchain, the patch link is

https://patchwork.sourceware.org/project/binutils/patch/[email protected]/

you can click the right up botton mobox to download it, and deploy it using git in the binutils repository.

"""
git am v5-RISC-V-Add-Zcmt-instructions-and-csr..patch
"""

JAYANTH-IITM · 2024-11-04T08:29:36Z

Hi @pz9115 ,
I tried to apply the patch for zcmt , but i am encountering this error

" Applying: RISC-V: Add Zcmt instructions and csr.
error: patch failed: gas/config/tc-riscv.c:3922
error: gas/config/tc-riscv.c: patch does not apply
error: patch failed: include/opcode/riscv-opc.h:2305
error: include/opcode/riscv-opc.h: patch does not apply
error: patch failed: opcodes/riscv-opc.c:362
error: opcodes/riscv-opc.c: patch does not apply
Patch failed at 0001 RISC-V: Add Zcmt instructions and csr. " . I am not sure how to proceed after this . Can you please help here

pz9115 · 2024-11-05T07:20:12Z

Hi @pz9115 , I tried to apply the patch for zcmt , but i am encountering this error

" Applying: RISC-V: Add Zcmt instructions and csr. error: patch failed: gas/config/tc-riscv.c:3922 error: gas/config/tc-riscv.c: patch does not apply error: patch failed: include/opcode/riscv-opc.h:2305 error: include/opcode/riscv-opc.h: patch does not apply error: patch failed: opcodes/riscv-opc.c:362 error: opcodes/riscv-opc.c: patch does not apply Patch failed at 0001 RISC-V: Add Zcmt instructions and csr. " . I am not sure how to proceed after this . Can you please help here

I think this is caused by binutils submodule not updated correctly, please checkout the binutils into the latest master branch,
https://sourceware.org/git/?p=binutils-gdb.git;a=summary

JAYANTH-IITM · 2024-11-06T06:11:28Z

Toolchain working fine @pz9115 . Thank you !

JAYANTH-IITM · 2024-11-07T07:22:36Z

@pz9115 @tariqkurd-repo , for the instruction cm.popret and cm.popretz it is working only for imm_val (spimm) 0 , for imm_val 1 , 2 and 3 it is not working. But cm.push and cm.pop is working fine . Can you please guide here .

@allenjbaum , the test macro that I written for zcmp and zcmt does not append any signature ( but i am able get the expected coverage for all instruction as expected , expect for the above case ) . attached the test_macro for reference

do i need to append signature ?
what is the expected signature ? can you please help here test_macros.zip

sorry , closed by mistake

pz9115 · 2024-11-07T08:48:19Z

@pz9115 @tariqkurd-repo , for the instruction cm.popret and cm.popretz it is working only for imm_val (spimm) 0 , for imm_val 1 , 2 and 3 it is not working. But cm.push and cm.pop is working fine . Can you please guide here .

I tested with a simple example spimm.s and it works fine

target:
        cm.popret {ra}, 16
        cm.popret {ra}, 32
        cm.popret {ra}, 48
        cm.popret {ra}, 64
        cm.popretz {ra}, 16
        cm.popretz {ra}, 32
        cm.popretz {ra}, 48
        cm.popretz {ra}, 64

/opt/riscv/bin/riscv64-unknown-elf-as -march=rv32ima_zcmp -mabi=ilp32 spimm.s -o spimm.o
/opt/riscv/bin/riscv64-unknown-elf-objdump -d spimm.o

spimm.o:     file format elf32-littleriscv


Disassembly of section .text:

00000000 <target>:
   0:   be42                    cm.popret       {ra},16
   2:   be46                    cm.popret       {ra},32
   4:   be4a                    cm.popret       {ra},48
   6:   be4e                    cm.popret       {ra},64
   8:   bc42                    cm.popretz      {ra},16
   a:   bc46                    cm.popretz      {ra},32
   c:   bc4a                    cm.popretz      {ra},48
   e:   bc4e                    cm.popretz      {ra},64

The stack_adj (16|32|48|64) corresponding to the stack_adj_base + 16 * spimm. In this example, the ra set the adj_base equal 16, and when spimm pass form 0~3, total stack_adj comes into (16|32|48|64). It has the same behaviour with cm.pop as expected.

Could you give more detail about this error, thanks.

@allenjbaum , the test macro that I written for zcmp and zcmt does not append any signature ( but i am able get the expected coverage for all instruction as expected , expect for the above case ) . attached the test_macro for reference

do i need to append signature ?

what is the expected signature ? can you please help here test_macros.zip

sorry , closed by mistake

JAYANTH-IITM · 2024-11-07T10:47:12Z

    .section .text
    .global _start

_start:
	cm.popret {ra}, 16
	cm.popret {ra,s0}, 16
	cm.popret {ra,s0-s1}, 16
	cm.popret {ra,s0-s2}, 16

when i try to execute this i am encountering ( I tried the same by using x register , but the same ) inside of using (ra , s0-s1) if (ra,s0,s1) is used it working ( which does not match with the spec )

$ riscv64-unknown-elf-as -march=rv64imac_zcmp -o test.o spimm.s
spimm.s: Assembler messages:
spimm.s:7: Error: illegal operands `cm.popret {ra,s0-s1},16'
spimm.s:8: Error: illegal operands `cm.popret {ra,s0-s2},16'

pz9115 · 2024-11-07T11:53:27Z

    .section .text
    .global _start

_start:
	cm.popret {ra}, 16
	cm.popret {ra,s0}, 16
	cm.popret {ra,s0-s1}, 16
	cm.popret {ra,s0-s2}, 16
when i try to execute this i am encountering ( I tried the same by using x register , but the same ) inside of using (ra , s0-s1) if (ra,s0,s1) is used it working ( which does not match with the spec )
$ riscv64-unknown-elf-as -march=rv64imac_zcmp -o test.o spimm.s
spimm.s: Assembler messages:
spimm.s:7: Error: illegal operands `cm.popret {ra,s0-s1},16'
spimm.s:8: Error: illegal operands `cm.popret {ra,s0-s2},16'

Let me explain why it's wrong here, in Zcmp, the base of stack_adj will change when using more S-registers as the arguments.

You can find the stack_adj setting in https://github.com/riscvarchive/riscv-code-size-reduction/blob/main/Zc-specification/pushpop_vars.adoc

Using -march=rv64imac_zcmp to compile cm.popret {ra,s0-s1} will match to the case 6 in RV64, sets the stack_adj_base equal to 32, so it should to use cm.popret {ra,s0-s1},32 in this case.

JAYANTH-IITM · 2024-11-12T08:12:10Z

Updates from IIT-M ,

Tests for Zcmp and Zcmt are complete . Not getting expected coverage in cm.popret and cm.popretz . Other than these two , getting expected coverage in all other test.

reg : expected signature for zmp and zcmt test, need some guidance here @allenjbaum

allenjbaum · 2024-11-12T20:06:45Z

I think you need to describe in a bit more detail the coverage you expect, and the coverage that is missing. (and I need to re-read the spec for those.)

…

On Tue, Nov 12, 2024 at 1:21 AM JAYANTH-IITM ***@***.***> wrote: Updates from IIT-M , 1. Tests for Zcmp and Zcmt are complete . Not getting expected coverage in cm.popret and cm.popretz . Other than these two , getting expected coverage in all other test. reg : expected signature for zmp and zcmt test, need some guidance here @allenjbaum <https://github.com/allenjbaum> — Reply to this email directly, view it on GitHub <#6 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AHPXVJS7T4IZ4RQDDVDIM7L2AHCDNAVCNFSM6AAAAAAV5WEWZ6VHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDINRZHA2TMMBTGA> . You are receiving this because you were mentioned.Message ID: ***@***.***>

allenjbaum · 2024-12-03T07:55:33Z

There are multiple problems with this test (and probably the others):

the stack data area is supposed to contain the address that is returned to when executing the instruction - but it is unintialized, so the test will be jumping to a unknown location, which will cause the test to abort (if you're lucky).

That return address entry should be the address of an instruction that follows the POPRET. Preferably, the macro should put noops after the POPRET and point the return address to be after those noops so we can write tests that will trap during the execution (which I'm pretty sure is not part of the coverage that was defined).
The other popped registers should have unique values that we can test for to ensure the correct addresses have been popped (e.g. walking ones)

the instruction performs a RET operation as part of its execution, yet the macro adds another RET after the instruction. This will cause an infinite loop (or would if the stack was actually properly initialized).
no signature is stored. Architectural state that is updated by any test should be stored into the signature (which in this case is every register that is popped off the stack) Furthermore, any register that is popped that is known to contain an address must be converted to an offset from the segments xx_BEGIN label (which in this case is the return address relative to CODE_BEGIN.
If a signature had been stored, the test would abort because no memory was allocated for it

anuani21 · 2024-12-10T11:57:21Z

@jjscheel,

Allen suggested some changes in the test for Zcmp extension.
I have rewriting the test to incorporate the changes for Zcmp extension.

anuani21 · 2025-01-07T10:27:40Z

@jjscheel,

Zcf and Zcd PR is merged to dev.

jjscheel · 2025-01-07T12:16:31Z

Thanks, @anuani21. Can you kindly provide a pointer to the PRs?

anuani21 · 2025-01-07T12:28:53Z

Zcf and Zcf extension PR: riscv-non-isa/riscv-arch-test#497 It is merged.

…

On Tue, 7 Jan, 2025, 5:46 pm Jeff Scheel, ***@***.***> wrote: Thanks, @anuani21 <https://github.com/anuani21>. Can you kindly provide a pointer to the PRs? — Reply to this email directly, view it on GitHub <#6 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/A3G6FFYXP4DAJID6ZX4Z3E32JPATPAVCNFSM6AAAAAAV5WEWZ6VHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDKNZVGEZTSMRVGM> . You are receiving this because you were mentioned.Message ID: ***@***.***>

jjscheel added the Agenda Item label Mar 16, 2023

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jjscheel assigned ptprasanna and unassigned jjscheel Apr 11, 2023

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Abdulwadoodd mentioned this issue Jun 20, 2023

Add Test suites for Zcb sub extension from Code Size Reduction Extension (Zce) riscv-non-isa/riscv-arch-test#364

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Issue from Arch_test.h riscv-non-isa/riscv-arch-test#543

Closed

JAYANTH-IITM closed this as completed Nov 7, 2024

JAYANTH-IITM reopened this Nov 7, 2024

Zce architecture tests #6

Zce architecture tests #6

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