PMP ACT

[jjscheel]

Technical Group

Privileged Spec IC

ratification-pkg

Priv 1.11

Technical Liaison

Greg Favor

Task Category

Arch Tests

Task Sub Category

• gcc
• binutils
• gdb
• intrinsics
• Java
• KVM
• ld
• llvm
• Linux kernel
• QEMU
• Spike

Ratification Target

2021

Statement of Work (SOW)

SOW: link

SOW Signoffs: (delete those not needed)

• Task group liaison sign-off date:
• Development partner sign-off date:
• ACT SIG sign-off date (if ACT work):

Waiver

• Freeze
• Ratification

Pull Request Details

ACT PR #1 (closed)
ACT and Coverpoints PR #2 (merged)
ISAC PR (merged)

[jjscheel]

ACT PR

@UmerShahidengr, what is the status here? It is still marked as being reviewed in your spreadsheet, but the PR seems to have bene closed and re-opened.

[jjscheel]

@UmerShahidengr, would you kindly let me know what github id we have for Abdul as well? THANKS!

[UmerShahidengr]

Thats still in review status. There are conflict issue in the PR which was resolved by reverting a few commits and then re-opening the PR.

[UmerShahidengr]

Update April 25th, 2023 => The PR is still in review. Due to Ramazan and Eid Holidays, no major work was done for this week, thus I am removing it from the agenda items.
Next week task => Work on a test for pseudo-misaligned memory access to check the boundary cases of PMP.

[jjscheel]

Update from Allen:

1. Got the next version of the trap handler working and tested (With help for 10xe folks) and merged.
   It is now possible to write tests of virtual memory, transition between protections mode easily, and write tests that can partition > permissions inside test code and data.
2. continue to partition and Test Format Spec into ACT Developer Spec and ACT User Spec, and continue to get new chair up to speed
3. no
4. I don't have any dates....

[jjscheel]

Oops, previous post was for wrong item. Pls ignore.

[jjscheel]

@Abdulwadoodd, any update here? Thanks.

[UmerShahidengr]

Update ⇾ June 12th, 2023:
No update so far. We will come back to this project in the next week

[jjscheel]

Ok, removing from Agenda for this week. Re-visit in 3 weeks.

[UmerShahidengr]

Update ⇾ July 11th, 2023
Not much work can be done here unless misaligned test cases are added. Coverpoints for PMP are getting developed but they are being tracked on different issue i.e, #13

[UmerShahidengr]

Update ⇾ August 15th, 2023
PMP coverpoints are ready and are available here for review.
Furthermore, misaligned access tests are still missing, which will be added in this quarter.

[UmerShahidengr]

Update ⇾ September 12th, 2023
No update on this.

[UmerShahidengr]

Update ⇾ September 26th, 2023
No update on this.

[UmerShahidengr]

Update ⇾ October 10th, 2023
No update on this.

[UmerShahidengr]

Update ⇾ October 24th, 2023
No update on this.

[UmerShahidengr]

Update ⇾ November 28th, 2023
PMP coverpoints have been added. Here is the link to the PR.

[UmerShahidengr]

Update ⇾ December 12th, 2023
The review process is going on smoothly.

[UmerShahidengr]

Update ⇾ January 30th, 2024
The review process is going on.

[UmerShahidengr]

Update ⇾ March 5th, 2024
@MuhammadHammad001 has added privilege coverpoint support in RISC-V ISAC (PR here), @allenjbaum has been working with @MuhammadHammad001 to write a translator for priv architecture which will help in writing priv arch coverpoints with better readability.
The coverpoint definitions are getting converted according to the new template, it will be completed in this quarter hopefully.

[UmerShahidengr]

Update ⇾ April 2nd, 2024
@MuhammadHammad001 has been working on PMP coverpoints, the PR will be completed before the next meeting

[jjscheel]

@UmerShahidengr, how are the cover points coming along?

[UmerShahidengr]

@jjscheel coverpoints are completed. I will add the PR tonight

[jjscheel]

I see old PR closed. Is this the new one: riscv-non-isa/riscv-arch-test #462?

[UmerShahidengr]

Yes. Thats the new one, and it is now complete with all tests and coverpoint definitions

[UmerShahidengr]

Update June 11th, 2024:
Coverpoint definitions and new template of writing coverpoints for Priv Architecture are still in review process, @allenjbaum has been reviewing this one and @MuhammadHammad001 has been working on it full time

[UmerShahidengr]

Update June 25th, 2024:
This task is still in review. @allenjbaum and @MuhammadHammad001 have been working on it.

[UmerShahidengr]

Update July 23rd, 2024:
This task is in review. @allenjbaum is spending some time reviewing it. Hopefully it will be completed soon

[UmerShahidengr]

Update August 6th, 2024:
The review process is complete, @allenjbaum has reviewed the PR, now it will be merged soon

[jjscheel]

Great news, @UmerShahidengr!

[UmerShahidengr]

Update October 29th, 2024:
Still in merging phase. Will be merged in the next release meeting in SIG ARCH. @allenjbaum has been asked to merge this one

[jjscheel]

ACT and Coverpoints PR merged.

[jjscheel]

SOW marked as "Signoff" stage.

@allenjbaum, @UmerShahidengr, can you folks kindly review the SOW and confirm that we've completed the work?

[jjscheel]

@allenjbaum, @UmerShahidengr, please review and approve completion of this SOW.

[allenjbaum]

There are several issues that have been filed against these tests: It doesn't work for anything except 4 byte granularity (#577, #580) It doesn't work on a model that is M only or M-U only. (#582) It is lacking a fence.i between storing into the instruction stream and branching to it, and has an extra JAL making it test twice (#575) #580 and #575 are being addressed (sic) under development. #582 is new, relatively simple to fix, except there is a WARL behavior configuration requirement that will require Sail changes In general, it shouldn't matter, in the sense that if a test tries to go from M->S with no Smode, it will go to M (for M-only) or either M or U (for M-U), and if tries to go to Umode in an M-only, it will also just stay in M-mode. The tests should still work, but not as intended - they'll be redundant. That's OK But, these tests won't currently compile because they always define rvtest_strap_routine - and that should only be defined if S-mode is supported, so the RVTEST_CASE macro has to be modified (there is an issue filed for that (#584). IF the model doesn't describe the WARL behavior (does it go to M or U if an illegal value is written to MPP in an M-U model) then there will be a mismatch. Fixing that will require both Sail updates and a command line option to define that behavior, though. That should be part of the configuration issue, and I don't think we should solve this now. ----------------------- We should also be creating tests for RV32/64E - there have been announcements of such a part. A separate SOW to re-generate all tests to work with RV32/64E implementations. That (may) require new cgf files, but also need changes in every test.h macro that uses an XREG larger than X15. If we are clever about it, we can make this so that all new tests do this automatically ( which involves ensure that signature base registers and temp registers never go beyond X25, Bottom line: RVTEST_CASE macro instantiation in each test should be replaced ( might be a simple global search/replace), other issues are currently under development.

…

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