additions for 1.12 pric arch spec. Vector spec changes. : v20200312.0

ChangeLog.md

@@ -6,10 +6,36 @@ This CHANGELOG contains information for the riscvOVPsim fixed platform which inc
 
 ---
 
-NOTE: X-commit messages below refer to git commits in the following 
-      Risc-V specification document repositories:                                  
-  I-commit: https://github.com/riscv/riscv-isa-manual                        
-  V-commit: https://github.com/riscv/riscv-v-spec                            
+NOTE: X-commit messages below refer to git commits in the following
+      Risc-V specification document repositories:
+  I-commit: https://github.com/riscv/riscv-isa-manual
+  V-commit: https://github.com/riscv/riscv-v-spec
+
+- Support for Debug mode has been added; see RISCV processor documentation for
+  more details.
+- The priv_version parameter now includes a choice of 'master', which specifies
+  that the evolving 1.12 Privileged Architecture Specification should be used.
+  This has the following changes compared to the ratified 1.11 version:
+  - MRET and SRET instruction clear mstatus.MPRV when leaving M-mode;
+  - For RV32, a new mstatush CSR has been added;
+  - Data endian is now configurable using UBE, SBE and MBE fields in mstatus
+    and the new mstatush CSR.
+- New parameter SEW_min has been added to specify the minimum SEW supported when
+  the Vector Extension is implemented; the default is 8 bits.
+- When the Vector Extension is implemented, the maximum VLEN value supported
+  has increased from 2048 to 65536 bits.
+- Some Vector Extension issues have been corrected:
+  - Behavior of vslidedown has been corrected in cases when vl<vlmax. Previously
+    elements where source element i satisfied vl<=i+offset were being zeroed;
+    now, elements where source element i satisfies vlmax<=i+offset are zeroed.
+- Some Vector Extension specification changes have been implemented:
+  - V-commit 951b64f: Mirrors of fcsr fields have been removed from vcsr.
+  - V-commit 45da90d: segment loads and stores have been restricted to SEW
+    element size only.
+
+Date 2020-February-19
+Release 20200218.0
+===
 
 ---
 

README.md

@@ -4,14 +4,14 @@ A Complete, Fully Functional, Configurable RISC-V Simulator
 ===
 
 Author: Imperas Software, Ltd., using OVP Open Standard APIs  
-Date   : 18 Feb 2020 
-Version: 20200218.0  
+Date   : 12 Mar 2020 
+Version: 20200312.0  
 License: Model source included under Apache 2.0 open source license  
 License: Simulator riscvOVPsim licensed under Open Virtual Platforms (OVP) Fixed Platform Kits license  
 RISC-V Specifications currently supported:
 - RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 20190305-Base-Ratification)
 - RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Privileged Architecture Version 20190405-Priv-MSU-Ratification)
-- RISC-V Instruction Set Manual, RISC-V "V" Vector Extension (with version configurable in the model using the 'vector_version' parameter. 'master' version conforms to specification changes up to 14 December 2019 and is regularly updated to track the evolving specification.)
+- RISC-V Instruction Set Manual, RISC-V "V" Vector Extension (with version configurable in the model using the 'vector_version' parameter. 'master' version conforms to specification changes up to 4 March 2020 and is regularly updated to track the evolving specification.)
 - RISCV Extension B (Bit Manipulation)
   - Run command: riscvOVPsim.exe --override riscvOVPsim/cpu/add_Extensions=B --showoverrides 
   - This will produce a formatted string, similar to 'Info (Bit Manipulation) extB Version(0.92) November 08 2019'

source/riscvAttrs.c

@@ -101,6 +101,7 @@ const vmiIASAttr modelAttrs = {
     .wrAbortExceptCB    = riscvWrAbortExcept,
     .ifetchExceptCB     = riscvIFetchExcept,
     .arithResultCB      = riscvArithResult,
+    .icountExceptCB     = riscvStepExcept,
 
     ////////////////////////////////////////////////////////////////////////
     // PARAMETER SUPPORT ROUTINES