ovpsim vs spike for RISCV

[simdream]

might be a very silly question. Just what is the advantages of using ovpsim vs SPIKE for RISCV? Seems like both trying to help SW/Firmware engineers develop the application code, compile, and debug .

[simon5656]

@simdream It is our policy not to provide detailed benchmarks or comparisons of our simulators with other programs.

However, for your information, there was a paper at the recent DAC20 which stated:

    "spike is the reference simulator of the ISA from Berkeley"

and

    "riscvOVPsim is the official reference simulator for compliance testing"

It went on to compare the simulators in terms of bugs found when testing the RV32GC unprivileged ISA.
It reported the following mismatches (bugs) compared to riscvOVPsim:

    spike       = 7+9+9 = 25
    sail-riscv  = no results, multiple crashes
    grift       = 124+1047+141 = 1,312

They also noted one perceived issue with riscvOVPsim, but on subsequent investigation the authors had it configured wrong with extra logging instructions enabled.

The paper is in the DAC20 proceedings and is titled: "Closing the RISC-V Compliance Gap: Looking from
the Negative Testing Side" by UniBremen, DFKI.

We do know that for detailed analysis of RISC-V ISA configurations riscvOVPsim has many more configuration and usability options than other simulators and so is much more accurate for verification.

There are also a range of commercial simulators from Imperas that build on the capabilities provided in riscvOVPsim. Including full platforms, systems and other ISA processors and virtual peripherals. Also the Imperas SystemVerilog step and compare encapsulation of the reference models is used by many customers for detailed HW DV including asynchronous events verification.

Imperas simulators are very fast, for example they can boot SMP Linux running on multicore RISC-V virtual platforms in under 10 seconds.

I hope that helps.