Skip to content
This repository has been archived by the owner on Sep 19, 2024. It is now read-only.

Imperas Risc-V OVPsim Release v20200526.0
Compare
Choose a tag to compare
@Imperas Imperas released this 27 May 15:26
· 18 commits to master since this release
v20200526.0
cf009a4
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.

riscvOVPsim Change Log

Copyright (c) 2005-2020 Imperas Software Ltd., www.imperas.com

This CHANGELOG contains information for the riscvOVPsim fixed platform which includes information of the OVP Simulator and RISCV processor model

Date 2020-May-26
Release 20200526.0

  • Memory accesses that straddle PMP region boundaries are now disallowed for
    M-mode, even if those regions imply full M-mode access.
Assets 2
Loading