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target/riscv: reg cache entry is initialized before access
Check Code Style (checkpatch) #1032: Pull request #1101 synchronize by en-sc
August 9, 2024 12:15 29s en-sc:en-sc/ref-reg-examine
August 9, 2024 12:15 29s
target/riscv: reg cache entry is initialized before access
Check Code Style (checkpatch) #1031: Pull request #1101 synchronize by en-sc
August 9, 2024 12:11 30s en-sc:en-sc/ref-reg-examine
August 9, 2024 12:11 30s
target/riscv: reg cache entry is initialized before access
Check Code Style (checkpatch) #1030: Pull request #1101 synchronize by en-sc
August 8, 2024 12:24 11m 16s en-sc:en-sc/ref-reg-examine
August 8, 2024 12:24 11m 16s
target/riscv: reg cache entry is initialized before access
Check Code Style (checkpatch) #1029: Pull request #1101 synchronize by en-sc
August 8, 2024 12:15 27s en-sc:en-sc/ref-reg-examine
August 8, 2024 12:15 27s
target/riscv: reg cache entry is initialized before access
Check Code Style (checkpatch) #1027: Pull request #1101 synchronize by en-sc
August 5, 2024 13:50 4m 45s en-sc:en-sc/ref-reg-examine
August 5, 2024 13:50 4m 45s
target/riscv: reg cache entry is initialized before access
Check Code Style (checkpatch) #1026: Pull request #1101 synchronize by en-sc
August 5, 2024 13:50 1m 35s en-sc:en-sc/ref-reg-examine
August 5, 2024 13:50 1m 35s
target/riscv: sys bus v1 fix for sizes greater than 4
Check Code Style (checkpatch) #1025: Pull request #1109 synchronize by aap-sc
August 5, 2024 12:36 43s aap-sc:aap-sc/sbus_fixup
August 5, 2024 12:36 43s
target/riscv: sys bus v1 fix for sizes greater than 4
Check Code Style (checkpatch) #1024: Pull request #1109 synchronize by aap-sc
August 5, 2024 12:35 29s aap-sc:aap-sc/sbus_fixup
August 5, 2024 12:35 29s
target/riscv: sys bus v1 fix for sizes greater than 4
Check Code Style (checkpatch) #1023: Pull request #1109 synchronize by aap-sc
August 5, 2024 12:33 30s aap-sc:aap-sc/sbus_fixup
August 5, 2024 12:33 30s
target/riscv: sys bus v1 fix for sizes greater than 4
Check Code Style (checkpatch) #1022: Pull request #1109 opened by aap-sc
August 5, 2024 12:31 38s aap-sc:aap-sc/sbus_fixup
August 5, 2024 12:31 38s
target/riscv: single DMI accesses via batch
Check Code Style (checkpatch) #1020: Pull request #1100 synchronize by en-sc
July 16, 2024 13:44 32s en-sc:en-sc/single-as-batch
July 16, 2024 13:44 32s
target/riscv: single DMI accesses via batch
Check Code Style (checkpatch) #1019: Pull request #1100 synchronize by en-sc
July 10, 2024 10:41 38s en-sc:en-sc/single-as-batch
July 10, 2024 10:41 38s
target/riscv: write SB address using batch
Check Code Style (checkpatch) #1018: Pull request #1099 synchronize by en-sc
July 10, 2024 10:09 29s en-sc:en-sc/sb-addr-batch
July 10, 2024 10:09 29s
target/riscv: single DMI accesses via batch
Check Code Style (checkpatch) #1017: Pull request #1100 synchronize by en-sc
July 9, 2024 12:13 36s en-sc:en-sc/single-as-batch
July 9, 2024 12:13 36s
target/riscv: write SB address using batch
Check Code Style (checkpatch) #1016: Pull request #1099 synchronize by en-sc
July 9, 2024 12:05 33s en-sc:en-sc/sb-addr-batch
July 9, 2024 12:05 33s
target/riscv: reg cache entry is initialized before access
Check Code Style (checkpatch) #1007: Pull request #1101 synchronize by en-sc
July 4, 2024 18:40 27s en-sc:en-sc/ref-reg-examine
July 4, 2024 18:40 27s