diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 9122d28460..6ae4f8c6f6 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -1897,7 +1897,6 @@ static int examine(struct target *target)
 
 	riscv013_info_t *info = get_info(target);
 
-	info->index = target->coreid;
 	info->abits = get_field(dtmcontrol, DTM_DTMCS_ABITS);
 	info->dtmcs_idle = get_field(dtmcontrol, DTM_DTMCS_IDLE);
 
@@ -2031,6 +2030,10 @@ static int examine(struct target *target)
 		return ERROR_FAIL;
 	}
 
+	/* The RISC-V hartid is sequential, and the index of each hart
+	 * on the Debug Module should start at 0 and be contiguous. */
+	info->index = target->coreid % dm->hart_count;
+
 	/* Don't call any riscv_* functions until after we've counted the number of
 	 * cores and initialized registers. */