From dd753a8c42201269da9934870a2a50aa7e8ec43e Mon Sep 17 00:00:00 2001 From: liangzhen Date: Mon, 28 Aug 2023 14:26:05 +0800 Subject: [PATCH] Support for smp in multiple DMs by dealing with riscv hartid and index of each hart simply --- src/target/riscv/riscv-013.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index f85c91d3bd..901c7d2a8b 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1893,7 +1893,6 @@ static int examine(struct target *target) riscv013_info_t *info = get_info(target); - info->index = target->coreid; info->abits = get_field(dtmcontrol, DTM_DTMCS_ABITS); info->dtmcs_idle = get_field(dtmcontrol, DTM_DTMCS_IDLE); @@ -2027,6 +2026,10 @@ static int examine(struct target *target) return ERROR_FAIL; } + /* The RISC-V hartid is sequential, and the index of each hart + * on the Debug Module should start at 0 and be contiguous. */ + info->index = target->coreid % dm->hart_count; + /* Don't call any riscv_* functions until after we've counted the number of * cores and initialized registers. */