From 5ba40f33231fa7d637b3078170ac2d546a56ede4 Mon Sep 17 00:00:00 2001 From: liweiwei Date: Sat, 18 Dec 2021 12:44:21 +0800 Subject: [PATCH] add support for cbo.zero in cmo extension --- .../device/rv32i_m/cmo/Makefile.include | 42 ++ .../device/rv64i_m/cmo/Makefile.include | 43 ++ riscv-target/sail-riscv-c/model_test.h | 2 +- riscv-test-suite/env/arch_test.h | 7 + riscv-test-suite/rv32i_m/cmo/Makefile | 3 + riscv-test-suite/rv32i_m/cmo/Makefrag | 35 ++ .../references/cbo.zero-01.reference_output | 544 ++++++++++++++++++ .../rv32i_m/cmo/src/cbo.zero-01.S | 250 ++++++++ riscv-test-suite/rv64i_m/cmo/Makefile | 3 + riscv-test-suite/rv64i_m/cmo/Makefrag | 35 ++ .../references/cbo.zero-01.reference_output | 544 ++++++++++++++++++ .../rv64i_m/cmo/src/cbo.zero-01.S | 250 ++++++++ 12 files changed, 1757 insertions(+), 1 deletion(-) create mode 100644 riscv-target/sail-riscv-c/device/rv32i_m/cmo/Makefile.include create mode 100644 riscv-target/sail-riscv-c/device/rv64i_m/cmo/Makefile.include create mode 100644 riscv-test-suite/rv32i_m/cmo/Makefile create mode 100644 riscv-test-suite/rv32i_m/cmo/Makefrag create mode 100644 riscv-test-suite/rv32i_m/cmo/references/cbo.zero-01.reference_output create mode 100644 riscv-test-suite/rv32i_m/cmo/src/cbo.zero-01.S create mode 100644 riscv-test-suite/rv64i_m/cmo/Makefile create mode 100644 riscv-test-suite/rv64i_m/cmo/Makefrag create mode 100644 riscv-test-suite/rv64i_m/cmo/references/cbo.zero-01.reference_output create mode 100644 riscv-test-suite/rv64i_m/cmo/src/cbo.zero-01.S diff --git a/riscv-target/sail-riscv-c/device/rv32i_m/cmo/Makefile.include b/riscv-target/sail-riscv-c/device/rv32i_m/cmo/Makefile.include new file mode 100644 index 000000000..b21db9f76 --- /dev/null +++ b/riscv-target/sail-riscv-c/device/rv32i_m/cmo/Makefile.include @@ -0,0 +1,42 @@ +TARGET_SIM ?= riscv_sim_RV32 -V +TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) +BLOCKSZ ?= 64 +ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) + $(error Target simulator executable '$(TARGET_SIM)` not found) +endif + +RUN_CMD=\ + $(TARGET_SIM) $(TARGET_FLAGS) -B $(BLOCKSZ) \ + --test-signature=$(*).signature.output \ + $(<) + +RISCV_PREFIX ?= riscv32-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump +RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -DBLOCKSZ=$(BLOCKSZ) $(RVTEST_DEFINES) + +COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \ + -I$(ROOTDIR)/riscv-test-suite/env/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \ + $$(<) -o $$@ +OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \ + $$(RISCV_OBJDUMP) $$@ --source > $$@.debug + + +COMPILE_TARGET=\ + $(COMPILE_CMD); \ + if [ $$$$? -ne 0 ] ; \ + then \ + echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \ + exit 1 ; \ + fi ; \ + $(OBJ_CMD); \ + if [ $$$$? -ne 0 ] ; \ + then \ + echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \ + exit 1 ; \ + fi ; + +RUN_TARGET=\ + $(RUN_CMD) diff --git a/riscv-target/sail-riscv-c/device/rv64i_m/cmo/Makefile.include b/riscv-target/sail-riscv-c/device/rv64i_m/cmo/Makefile.include new file mode 100644 index 000000000..79ab4d252 --- /dev/null +++ b/riscv-target/sail-riscv-c/device/rv64i_m/cmo/Makefile.include @@ -0,0 +1,43 @@ +TARGET_SIM ?= riscv_sim_RV64 -V +TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) +BLOCKSZ ?= 64 +ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) + $(error Target simulator executable '$(TARGET_SIM)` not found) +endif + +RUN_CMD=\ + $(TARGET_SIM) $(TARGET_FLAGS) -B $(BLOCKSZ)\ + --test-signature=$(*).signature.output \ + $(<) + +RISCV_PREFIX ?= riscv64-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump +RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -DBLOCKSZ=$(BLOCKSZ) $(RVTEST_DEFINES) + +COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \ + -I$(ROOTDIR)/riscv-test-suite/env/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \ + $$(<) -o $$@ +OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \ + $$(RISCV_OBJDUMP) $$@ --source > $$@.debug + + + +COMPILE_TARGET=\ + $(COMPILE_CMD); \ + if [ $$$$? -ne 0 ] ; \ + then \ + echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \ + exit 1 ; \ + fi ; \ + $(OBJ_CMD); \ + if [ $$$$? -ne 0 ] ; \ + then \ + echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \ + exit 1 ; \ + fi ; + +RUN_TARGET=\ + $(RUN_CMD) diff --git a/riscv-target/sail-riscv-c/model_test.h b/riscv-target/sail-riscv-c/model_test.h index 2c4eb8c14..8d170a716 100644 --- a/riscv-target/sail-riscv-c/model_test.h +++ b/riscv-target/sail-riscv-c/model_test.h @@ -28,7 +28,7 @@ //RV_COMPLIANCE_DATA_BEGIN #define RVMODEL_DATA_BEGIN \ - .align 4 ; .global begin_signature; begin_signature: + .align 12 ; .global begin_signature; begin_signature: //RV_COMPLIANCE_DATA_END #define RVMODEL_DATA_END \ diff --git a/riscv-test-suite/env/arch_test.h b/riscv-test-suite/env/arch_test.h index a4f9d435f..bef73c377 100644 --- a/riscv-test-suite/env/arch_test.h +++ b/riscv-test-suite/env/arch_test.h @@ -860,6 +860,13 @@ nop ;\ csrrs flagreg, fflags, x0 ;\ RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset) +#define TEST_CBO_ZERO(swreg,rs1,inst,imm_val) ;\ +addi rs1,swreg,(imm_val&(BLOCKSZ-1)) ;\ +inst rs1 ;\ +nop ;\ +nop ;\ +addi swreg, swreg, BLOCKSZ + #define TEST_CSR_FIELD(ADDRESS,TEMP_REG,MASK_REG,NEG_MASK_REG,VAL,DEST_REG,OFFSET,BASE_REG) \ LI(TEMP_REG,VAL);\ and TEMP_REG,TEMP_REG,MASK_REG;\ diff --git a/riscv-test-suite/rv32i_m/cmo/Makefile b/riscv-test-suite/rv32i_m/cmo/Makefile new file mode 100644 index 000000000..5e3f7021e --- /dev/null +++ b/riscv-test-suite/rv32i_m/cmo/Makefile @@ -0,0 +1,3 @@ +include ../../Makefile.include + +$(eval $(call compile_template,-march=rv32i -mabi=ilp32 -DXLEN=$(XLEN) -DBLOCKSZ=$(BLOCKSZ))) diff --git a/riscv-test-suite/rv32i_m/cmo/Makefrag b/riscv-test-suite/rv32i_m/cmo/Makefrag new file mode 100644 index 000000000..ace9351fc --- /dev/null +++ b/riscv-test-suite/rv32i_m/cmo/Makefrag @@ -0,0 +1,35 @@ +# RISC-V Architecture Test RV32I Makefrag +# +# Copyright (c) 2017, Codasip Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Codasip Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Description: Makefrag for RV32I architectural tests + +rv32i_sc_tests = \ + cbo.zero-01 + +rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) + +target_tests += $(rv32i_tests) diff --git a/riscv-test-suite/rv32i_m/cmo/references/cbo.zero-01.reference_output b/riscv-test-suite/rv32i_m/cmo/references/cbo.zero-01.reference_output new file mode 100644 index 000000000..14a8dc617 --- /dev/null +++ b/riscv-test-suite/rv32i_m/cmo/references/cbo.zero-01.reference_output @@ -0,0 +1,544 @@ +00000000 +00000000 +00000000 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+00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/riscv-test-suite/rv32i_m/cmo/src/cbo.zero-01.S b/riscv-test-suite/rv32i_m/cmo/src/cbo.zero-01.S new file mode 100644 index 000000000..38d5bd7cb --- /dev/null +++ b/riscv-test-suite/rv32i_m/cmo/src/cbo.zero-01.S @@ -0,0 +1,250 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.6.2 +// timestamp : Wed Mar 30 07:51:11 2022 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /workspace/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /workspace/riscv-ctg/sample_cgfs/rv64i_cbo.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the cbo.zero instruction of the RISC-V RV32 extension for the cbo.zero covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",cbo.zero) + +RVTEST_SIGBASE(x2,signature_x2_1) + +inst_0: +// rs1==x19, rs1_val == 0x4a9 +// opcode: cbo.zero ; op1:x19; op1val:0x4a9 +TEST_CBO_ZERO(x2,x19,cbo.zero,0x4a9) + +inst_1: +// rs1==x29, rs1_val == 2047, +// opcode: cbo.zero ; op1:x29; op1val:0x7ff +TEST_CBO_ZERO(x2,x29,cbo.zero,0x7ff) + +inst_2: +// rs1==x23, rs1_val == 3071, +// opcode: cbo.zero ; op1:x23; op1val:0xbff +TEST_CBO_ZERO(x2,x23,cbo.zero,0xbff) + +inst_3: +// rs1==x20, rs1_val == 3583, +// opcode: cbo.zero ; op1:x20; op1val:0xdff +TEST_CBO_ZERO(x2,x20,cbo.zero,0xdff) + +inst_4: +// rs1==x16, rs1_val == 3839, +// opcode: cbo.zero ; op1:x16; op1val:0xeff +TEST_CBO_ZERO(x2,x16,cbo.zero,0xeff) + +inst_5: +// rs1==x11, rs1_val == 3967, +// opcode: cbo.zero ; op1:x11; op1val:0xf7f +TEST_CBO_ZERO(x2,x11,cbo.zero,0xf7f) + +inst_6: +// rs1==x8, rs1_val == 4031, +// opcode: cbo.zero ; op1:x8; op1val:0xfbf +TEST_CBO_ZERO(x2,x8,cbo.zero,0xfbf) + +inst_7: +// rs1==x1, rs1_val == 4063, +// opcode: cbo.zero ; op1:x1; op1val:0xfdf +TEST_CBO_ZERO(x2,x1,cbo.zero,0xfdf) + +inst_8: +// rs1==x30, rs1_val == 4079, +// opcode: cbo.zero ; op1:x30; op1val:0xfef +TEST_CBO_ZERO(x2,x30,cbo.zero,0xfef) + +inst_9: +// rs1==x18, rs1_val == 4087, +// opcode: cbo.zero ; op1:x18; op1val:0xff7 +TEST_CBO_ZERO(x2,x18,cbo.zero,0xff7) + +inst_10: +// rs1==x4, rs1_val == 4091, +// opcode: cbo.zero ; op1:x4; op1val:0xffb +TEST_CBO_ZERO(x2,x4,cbo.zero,0xffb) + +inst_11: +// rs1==x13, rs1_val == 4093, +// opcode: cbo.zero ; op1:x13; op1val:0xffd +TEST_CBO_ZERO(x2,x13,cbo.zero,0xffd) + +inst_12: +// rs1==x27, rs1_val == 4094, +// opcode: cbo.zero ; op1:x27; op1val:0xffe +TEST_CBO_ZERO(x2,x27,cbo.zero,0xffe) + +inst_13: +// rs1==x22, rs1_val == 2048, +// opcode: cbo.zero ; op1:x22; op1val:0x800 +TEST_CBO_ZERO(x2,x22,cbo.zero,0x800) + +inst_14: +// rs1==x26, rs1_val == 1024, +// opcode: cbo.zero ; op1:x26; op1val:0x400 +TEST_CBO_ZERO(x2,x26,cbo.zero,0x400) + +inst_15: +// rs1==x12, rs1_val == 512, +// opcode: cbo.zero ; op1:x12; op1val:0x200 +TEST_CBO_ZERO(x2,x12,cbo.zero,0x200) + +inst_16: +// rs1==x9, rs1_val == 256, +// opcode: cbo.zero ; op1:x9; op1val:0x100 +TEST_CBO_ZERO(x2,x9,cbo.zero,0x100) + +inst_17: +// rs1==x7, rs1_val == 128, +// opcode: cbo.zero ; op1:x7; op1val:0x80 +TEST_CBO_ZERO(x2,x7,cbo.zero,0x80) + +inst_18: +// rs1==x25, rs1_val == 64, +// opcode: cbo.zero ; op1:x25; op1val:0x40 +TEST_CBO_ZERO(x2,x25,cbo.zero,0x40) + +inst_19: +// rs1==x10, rs1_val == 0xe8e +// opcode: cbo.zero ; op1:x10; op1val:0xe8e +TEST_CBO_ZERO(x2,x10,cbo.zero,0xe8e) + +inst_20: +// rs1==x15, rs1_val == 0xeb4 +// opcode: cbo.zero ; op1:x15; op1val:0xeb4 +TEST_CBO_ZERO(x2,x15,cbo.zero,0xeb4) + +inst_21: +// rs1==x31, rs1_val == 32, +// opcode: cbo.zero ; op1:x31; op1val:0x20 +TEST_CBO_ZERO(x2,x31,cbo.zero,0x20) + +inst_22: +// rs1==x24, rs1_val == 16, +// opcode: cbo.zero ; op1:x24; op1val:0x10 +TEST_CBO_ZERO(x2,x24,cbo.zero,0x10) + +inst_23: +// rs1==x6, rs1_val == 8, +// opcode: cbo.zero ; op1:x6; op1val:0x8 +TEST_CBO_ZERO(x2,x6,cbo.zero,0x8) + +inst_24: +// rs1==x21, rs1_val == 4, +// opcode: cbo.zero ; op1:x21; op1val:0x4 +TEST_CBO_ZERO(x2,x21,cbo.zero,0x4) + +inst_25: +// rs1==x5, rs1_val == 2, +// opcode: cbo.zero ; op1:x5; op1val:0x2 +TEST_CBO_ZERO(x2,x5,cbo.zero,0x2) + +inst_26: +// rs1==x14, rs1_val == 1, +// opcode: cbo.zero ; op1:x14; op1val:0x1 +TEST_CBO_ZERO(x2,x14,cbo.zero,0x1) + +inst_27: +// rs1==x3, rs1_val == 0x290 +// opcode: cbo.zero ; op1:x3; op1val:0x290 +TEST_CBO_ZERO(x2,x3,cbo.zero,0x290) + +inst_28: +// rs1==x28, rs1_val == 0x3e1 +// opcode: cbo.zero ; op1:x28; op1val:0x3e1 +TEST_CBO_ZERO(x2,x28,cbo.zero,0x3e1) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_29: +// rs1==x17, rs1_val == 0x384 +// opcode: cbo.zero ; op1:x17; op1val:0x384 +TEST_CBO_ZERO(x1,x17,cbo.zero,0x384) + +inst_30: +// rs1==x2, rs1_val == 0xddf +// opcode: cbo.zero ; op1:x2; op1val:0xddf +TEST_CBO_ZERO(x1,x2,cbo.zero,0xddf) + +inst_31: +// rs1_val == 0xb31 +// opcode: cbo.zero ; op1:x31; op1val:0xb31 +TEST_CBO_ZERO(x1,x31,cbo.zero,0xb31) + +inst_32: +// rs1_val == 0xc93 +// opcode: cbo.zero ; op1:x31; op1val:0xc93 +TEST_CBO_ZERO(x1,x31,cbo.zero,0xc93) + +inst_33: +// rs1_val == 0x597 +// opcode: cbo.zero ; op1:x31; op1val:0x597 +TEST_CBO_ZERO(x1,x31,cbo.zero,0x597) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + + +signature_x2_0: + .fill 0*(BLOCKSZ/4),4,0xdeadbeef + + +signature_x2_1: + .fill 29*(BLOCKSZ/4),4,0xdeadbeef + + +signature_x1_0: + .fill 5*(BLOCKSZ/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/cmo/Makefile b/riscv-test-suite/rv64i_m/cmo/Makefile new file mode 100644 index 000000000..8b02bc52e --- /dev/null +++ b/riscv-test-suite/rv64i_m/cmo/Makefile @@ -0,0 +1,3 @@ +include ../../Makefile.include + +$(eval $(call compile_template,-march=rv64i -mabi=lp64 -DXLEN=$(XLEN) -DBLOCKSZ=$(BLOCKSZ))) diff --git a/riscv-test-suite/rv64i_m/cmo/Makefrag b/riscv-test-suite/rv64i_m/cmo/Makefrag new file mode 100644 index 000000000..36bf7904f --- /dev/null +++ b/riscv-test-suite/rv64i_m/cmo/Makefrag @@ -0,0 +1,35 @@ +# RISC-V Architecture Test RV64I Makefrag +# +# Copyright (c) 2017, Codasip Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Codasip Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Description: Makefrag for RV64I architectural tests + +rv64i_sc_tests = \ + cbo.zero-01 + +rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests)) + +target_tests += $(rv64i_tests) diff --git a/riscv-test-suite/rv64i_m/cmo/references/cbo.zero-01.reference_output b/riscv-test-suite/rv64i_m/cmo/references/cbo.zero-01.reference_output new file mode 100644 index 000000000..14a8dc617 --- /dev/null +++ b/riscv-test-suite/rv64i_m/cmo/references/cbo.zero-01.reference_output @@ -0,0 +1,544 @@ +00000000 +00000000 +00000000 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+00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/riscv-test-suite/rv64i_m/cmo/src/cbo.zero-01.S b/riscv-test-suite/rv64i_m/cmo/src/cbo.zero-01.S new file mode 100644 index 000000000..6897ed1b0 --- /dev/null +++ b/riscv-test-suite/rv64i_m/cmo/src/cbo.zero-01.S @@ -0,0 +1,250 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.6.2 +// timestamp : Wed Mar 30 07:49:24 2022 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /workspace/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /workspace/riscv-ctg/sample_cgfs/rv64i_cbo.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the cbo.zero instruction of the RISC-V RV64 extension for the cbo.zero covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",cbo.zero) + +RVTEST_SIGBASE(x12,signature_x12_1) + +inst_0: +// rs1==x18, rs1_val == 0x4a9 +// opcode: cbo.zero ; op1:x18; op1val:0x4a9 +TEST_CBO_ZERO(x12,x18,cbo.zero,0x4a9) + +inst_1: +// rs1==x31, rs1_val == 2047, +// opcode: cbo.zero ; op1:x31; op1val:0x7ff +TEST_CBO_ZERO(x12,x31,cbo.zero,0x7ff) + +inst_2: +// rs1==x30, rs1_val == 3071, +// opcode: cbo.zero ; op1:x30; op1val:0xbff +TEST_CBO_ZERO(x12,x30,cbo.zero,0xbff) + +inst_3: +// rs1==x17, rs1_val == 3583, +// opcode: cbo.zero ; op1:x17; op1val:0xdff +TEST_CBO_ZERO(x12,x17,cbo.zero,0xdff) + +inst_4: +// rs1==x23, rs1_val == 3839, +// opcode: cbo.zero ; op1:x23; op1val:0xeff +TEST_CBO_ZERO(x12,x23,cbo.zero,0xeff) + +inst_5: +// rs1==x24, rs1_val == 3967, +// opcode: cbo.zero ; op1:x24; op1val:0xf7f +TEST_CBO_ZERO(x12,x24,cbo.zero,0xf7f) + +inst_6: +// rs1==x11, rs1_val == 4031, +// opcode: cbo.zero ; op1:x11; op1val:0xfbf +TEST_CBO_ZERO(x12,x11,cbo.zero,0xfbf) + +inst_7: +// rs1==x10, rs1_val == 4063, +// opcode: cbo.zero ; op1:x10; op1val:0xfdf +TEST_CBO_ZERO(x12,x10,cbo.zero,0xfdf) + +inst_8: +// rs1==x13, rs1_val == 4079, +// opcode: cbo.zero ; op1:x13; op1val:0xfef +TEST_CBO_ZERO(x12,x13,cbo.zero,0xfef) + +inst_9: +// rs1==x6, rs1_val == 4087, +// opcode: cbo.zero ; op1:x6; op1val:0xff7 +TEST_CBO_ZERO(x12,x6,cbo.zero,0xff7) + +inst_10: +// rs1==x21, rs1_val == 4091, +// opcode: cbo.zero ; op1:x21; op1val:0xffb +TEST_CBO_ZERO(x12,x21,cbo.zero,0xffb) + +inst_11: +// rs1==x1, rs1_val == 4093, +// opcode: cbo.zero ; op1:x1; op1val:0xffd +TEST_CBO_ZERO(x12,x1,cbo.zero,0xffd) + +inst_12: +// rs1==x3, rs1_val == 4094, +// opcode: cbo.zero ; op1:x3; op1val:0xffe +TEST_CBO_ZERO(x12,x3,cbo.zero,0xffe) + +inst_13: +// rs1==x26, rs1_val == 2048, +// opcode: cbo.zero ; op1:x26; op1val:0x800 +TEST_CBO_ZERO(x12,x26,cbo.zero,0x800) + +inst_14: +// rs1==x5, rs1_val == 1024, +// opcode: cbo.zero ; op1:x5; op1val:0x400 +TEST_CBO_ZERO(x12,x5,cbo.zero,0x400) + +inst_15: +// rs1==x7, rs1_val == 512, +// opcode: cbo.zero ; op1:x7; op1val:0x200 +TEST_CBO_ZERO(x12,x7,cbo.zero,0x200) + +inst_16: +// rs1==x29, rs1_val == 256, +// opcode: cbo.zero ; op1:x29; op1val:0x100 +TEST_CBO_ZERO(x12,x29,cbo.zero,0x100) + +inst_17: +// rs1==x20, rs1_val == 128, +// opcode: cbo.zero ; op1:x20; op1val:0x80 +TEST_CBO_ZERO(x12,x20,cbo.zero,0x80) + +inst_18: +// rs1==x28, rs1_val == 64, +// opcode: cbo.zero ; op1:x28; op1val:0x40 +TEST_CBO_ZERO(x12,x28,cbo.zero,0x40) + +inst_19: +// rs1==x16, rs1_val == 0xe8e +// opcode: cbo.zero ; op1:x16; op1val:0xe8e +TEST_CBO_ZERO(x12,x16,cbo.zero,0xe8e) + +inst_20: +// rs1==x19, rs1_val == 0xeb4 +// opcode: cbo.zero ; op1:x19; op1val:0xeb4 +TEST_CBO_ZERO(x12,x19,cbo.zero,0xeb4) + +inst_21: +// rs1==x22, rs1_val == 32, +// opcode: cbo.zero ; op1:x22; op1val:0x20 +TEST_CBO_ZERO(x12,x22,cbo.zero,0x20) + +inst_22: +// rs1==x25, rs1_val == 16, +// opcode: cbo.zero ; op1:x25; op1val:0x10 +TEST_CBO_ZERO(x12,x25,cbo.zero,0x10) + +inst_23: +// rs1==x8, rs1_val == 8, +// opcode: cbo.zero ; op1:x8; op1val:0x8 +TEST_CBO_ZERO(x12,x8,cbo.zero,0x8) + +inst_24: +// rs1==x4, rs1_val == 4, +// opcode: cbo.zero ; op1:x4; op1val:0x4 +TEST_CBO_ZERO(x12,x4,cbo.zero,0x4) + +inst_25: +// rs1==x27, rs1_val == 2, +// opcode: cbo.zero ; op1:x27; op1val:0x2 +TEST_CBO_ZERO(x12,x27,cbo.zero,0x2) + +inst_26: +// rs1==x14, rs1_val == 1, +// opcode: cbo.zero ; op1:x14; op1val:0x1 +TEST_CBO_ZERO(x12,x14,cbo.zero,0x1) + +inst_27: +// rs1==x9, rs1_val == 0x290 +// opcode: cbo.zero ; op1:x9; op1val:0x290 +TEST_CBO_ZERO(x12,x9,cbo.zero,0x290) + +inst_28: +// rs1==x2, rs1_val == 0x3e1 +// opcode: cbo.zero ; op1:x2; op1val:0x3e1 +TEST_CBO_ZERO(x12,x2,cbo.zero,0x3e1) +RVTEST_SIGBASE(x1,signature_x1_0) + +inst_29: +// rs1==x15, rs1_val == 0x384 +// opcode: cbo.zero ; op1:x15; op1val:0x384 +TEST_CBO_ZERO(x1,x15,cbo.zero,0x384) + +inst_30: +// rs1==x12, rs1_val == 0xddf +// opcode: cbo.zero ; op1:x12; op1val:0xddf +TEST_CBO_ZERO(x1,x12,cbo.zero,0xddf) + +inst_31: +// rs1_val == 0xb31 +// opcode: cbo.zero ; op1:x31; op1val:0xb31 +TEST_CBO_ZERO(x1,x31,cbo.zero,0xb31) + +inst_32: +// rs1_val == 0xc93 +// opcode: cbo.zero ; op1:x31; op1val:0xc93 +TEST_CBO_ZERO(x1,x31,cbo.zero,0xc93) + +inst_33: +// rs1_val == 0x597 +// opcode: cbo.zero ; op1:x31; op1val:0x597 +TEST_CBO_ZERO(x1,x31,cbo.zero,0x597) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + + +signature_x12_0: + .fill 0*(BLOCKSZ/4),4,0xdeadbeef + + +signature_x12_1: + .fill 29*(BLOCKSZ/4),4,0xdeadbeef + + +signature_x1_0: + .fill 5*(BLOCKSZ/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END