From 33d1289508c1fc5c60a759557196e1d964d221e4 Mon Sep 17 00:00:00 2001 From: anuani21 <114156183+anuani21@users.noreply.github.com> Date: Mon, 30 Dec 2024 22:31:24 +0530 Subject: [PATCH 01/10] [ACT] [CTG] [ISAC] Add support for Zcf and Zcd extension (#497) * Updated Zcf and Zcd test case * Updated Zcf and Zcd instruction support with respect to riscv-ctg and riscv-isac --------- Signed-off-by: anuani21 <114156183+anuani21@users.noreply.github.com> Co-authored-by: James Shi --- coverage/cgfs_fext/RV32Zcd/fld.cgf | 67 ++++ coverage/cgfs_fext/RV32Zcf/flw.cgf | 65 ++++ coverage/cgfs_fext/RV64Zcd/fld.cgf | 67 ++++ coverage/dataset.cgf | 10 + riscv-ctg/riscv_ctg/data/imc.yaml | 175 +++++++++ riscv-ctg/riscv_ctg/data/template.yaml | 1 + riscv-ctg/riscv_ctg/generator.py | 14 +- riscv-isac/riscv_isac/InstructionObject.py | 2 +- riscv-test-suite/rv32i_m/D_Zcd/src/c.fld-01.S | 173 +++++++++ .../rv32i_m/D_Zcd/src/c.fldsp-01.S | 247 +++++++++++++ riscv-test-suite/rv32i_m/D_Zcd/src/c.fsd-01.S | 213 +++++++++++ .../rv32i_m/D_Zcd/src/c.fsdsp-01.S | 343 ++++++++++++++++++ riscv-test-suite/rv32i_m/F_Zcf/src/c.flw-01.S | 173 +++++++++ .../rv32i_m/F_Zcf/src/c.flwsp-01.S | 249 +++++++++++++ riscv-test-suite/rv32i_m/F_Zcf/src/c.fsw-01.S | 213 +++++++++++ .../rv32i_m/F_Zcf/src/c.fswsp-01.S | 343 ++++++++++++++++++ 16 files changed, 2349 insertions(+), 6 deletions(-) create mode 100644 coverage/cgfs_fext/RV32Zcd/fld.cgf create mode 100644 coverage/cgfs_fext/RV32Zcf/flw.cgf create mode 100644 coverage/cgfs_fext/RV64Zcd/fld.cgf create mode 100644 riscv-test-suite/rv32i_m/D_Zcd/src/c.fld-01.S create mode 100644 riscv-test-suite/rv32i_m/D_Zcd/src/c.fldsp-01.S create mode 100644 riscv-test-suite/rv32i_m/D_Zcd/src/c.fsd-01.S create mode 100644 riscv-test-suite/rv32i_m/D_Zcd/src/c.fsdsp-01.S create mode 100644 riscv-test-suite/rv32i_m/F_Zcf/src/c.flw-01.S create mode 100644 riscv-test-suite/rv32i_m/F_Zcf/src/c.flwsp-01.S create mode 100644 riscv-test-suite/rv32i_m/F_Zcf/src/c.fsw-01.S create mode 100644 riscv-test-suite/rv32i_m/F_Zcf/src/c.fswsp-01.S diff --git a/coverage/cgfs_fext/RV32Zcd/fld.cgf b/coverage/cgfs_fext/RV32Zcd/fld.cgf new file mode 100644 index 000000000..4c42779df --- /dev/null +++ b/coverage/cgfs_fext/RV32Zcd/fld.cgf @@ -0,0 +1,67 @@ +c.fld: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + mnemonics: + c.fld: 0 + rs1: + <<: *c_regs + rd: + <<: *c_fregs + op_comb: + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +c.fsd: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fsd: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_fregs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +c.fldsp: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fldsp: 0 + rd: + <<: *all_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + +c.fsdsp: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fsdsp: 0 + rs2: + <<: *all_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 diff --git a/coverage/cgfs_fext/RV32Zcf/flw.cgf b/coverage/cgfs_fext/RV32Zcf/flw.cgf new file mode 100644 index 000000000..3442d59f0 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zcf/flw.cgf @@ -0,0 +1,65 @@ +c.flw: + config: + - check ISA:=regex(.*I.*F.*C.*) + mnemonics: + c.flw: 0 + rs1: + <<: *c_regs + rd: + <<: *c_fregs + val_comb: + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + +c.flwsp: + config: + - check ISA:=regex(.*I.*F.*C.*) + opcode: + c.flwsp: 0 + rd: + <<: *c_fregs + val_comb: + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 + +c.fsw: + config: + - check ISA:=regex(.*I.*F.*C.*) + opcode: + c.fsw: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_fregs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + +c.fswsp: + config: + - check ISA:=regex(.*I.*F.*C.*) + opcode: + c.fswsp: 0 + rs2: + <<: *c_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 diff --git a/coverage/cgfs_fext/RV64Zcd/fld.cgf b/coverage/cgfs_fext/RV64Zcd/fld.cgf new file mode 100644 index 000000000..4c42779df --- /dev/null +++ b/coverage/cgfs_fext/RV64Zcd/fld.cgf @@ -0,0 +1,67 @@ +c.fld: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + mnemonics: + c.fld: 0 + rs1: + <<: *c_regs + rd: + <<: *c_fregs + op_comb: + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +c.fsd: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fsd: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_fregs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +c.fldsp: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fldsp: 0 + rd: + <<: *all_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + +c.fsdsp: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fsdsp: 0 + rs2: + <<: *all_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 diff --git a/coverage/dataset.cgf b/coverage/dataset.cgf index a1a1a01f4..b84b69dd8 100644 --- a/coverage/dataset.cgf +++ b/coverage/dataset.cgf @@ -180,6 +180,16 @@ datasets: x13: 0 x14: 0 x15: 0 + + c_fregs: &c_fregs + f8: 0 + f9: 0 + f10: 0 + f11: 0 + f12: 0 + f13: 0 + f14: 0 + f15: 0 all_regs_mx2: &all_regs_mx2 x1: 0 diff --git a/riscv-ctg/riscv_ctg/data/imc.yaml b/riscv-ctg/riscv_ctg/data/imc.yaml index d77570efc..14fc7d9a1 100644 --- a/riscv-ctg/riscv_ctg/data/imc.yaml +++ b/riscv-ctg/riscv_ctg/data/imc.yaml @@ -1890,3 +1890,178 @@ c.jalr: // opcode: c.jalr; op1:$rs1 TEST_CJALR_OP($testreg, $rs1, $swreg, $offset) +c.flw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rd_op_data: *c_fregs + xlen: [32] + std_op: + isa: + - IF_Zcf + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'clformat' + ea_align_data: '[0,1,2,3]' + rs1_val_data: '[0]' + imm_val_data: '[x*4 for x in gen_usign_dataset(5)]' + template: |- + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg; fcsr: $fcsr + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + +c.flwsp: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *c_fregs + xlen: [32] + std_op: + isa: + - IF_Zcf + formattype: 'ciformat' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + ea_align_data: '[0,1,2,3]' + imm_val_data: '[x*4 for x in gen_usign_dataset(6)]' + template: |- + // $comment + // opcode: $inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg; fcsr: $fcsr + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + +c.fsw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + rs1_op_data: *c_regs + rs2_op_data: *c_fregs + std_op: + isa: + - IF_Zcf + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'csformat' + ea_align_data: '[0,1,2,3]' + rs1_val_data: '[0]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*4 for x in gen_usign_dataset(5)]' + template: |- + // $comment + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + +c.fswsp: + sig: + stride: 1 + sz: 'XLEN/8' + rs2_op_data: *c_fregs + xlen: [32] + std_op: + isa: + - IF_Zcf + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'cssformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*4 for x in gen_usign_dataset(6)]' + template: |- + // $comment + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + +c.fld: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "''" + load_instr: "fld" + rs1_op_data: *c_regs + rd_op_data: *c_fregs + xlen: [32,64] + std_op: + isa: + - IFD_Zcd + formattype: 'clformat' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + ea_align_data: '[0,1,2,3]' + imm_val_data: '[x*8 for x in gen_usign_dataset(5)]' + template: |- + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + +c.fldsp: + sig: + stride: 2 + sz: 'SIGALIGN' + rd_op_data: *c_fregs + xlen: [32,64] + std_op: + isa: + - IFD_Zcd + formattype: 'ciformat' + imm_val_data: '[x*8 for x in gen_usign_dataset(6)]' + template: |- + // $comment + // opcode: $inst; op1:x2; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:x4 + TEST_LOAD_F($swreg,$testreg,$fcsr,x2,$rd,$imm_val,$inst,$ea_align,x4) + + +c.fsd: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "''" + load_instr: "FLREG" + rs1_op_data: *c_regs + rs2_op_data: *c_fregs + xlen: [32,64] + std_op: + isa: + - IFD_Zcd + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'csformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*8 for x in gen_usign_dataset(5)]' + template: |- + // $comment + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + +c.fsdsp: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "''" + load_instr: "FLREG" + rs2_op_data: *c_fregs + xlen: [32,64] + std_op: + isa: + - IFD_Zcd + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'cssformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*8 for x in gen_usign_dataset(6)]' + template: |- + // $comment + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) diff --git a/riscv-ctg/riscv_ctg/data/template.yaml b/riscv-ctg/riscv_ctg/data/template.yaml index d1f87c8df..40d23c717 100644 --- a/riscv-ctg/riscv_ctg/data/template.yaml +++ b/riscv-ctg/riscv_ctg/data/template.yaml @@ -4,6 +4,7 @@ metadata: all_fregs: &all_fregs "['f'+str(x) for x in range(0,32 if 'e' not in base_isa else 16)]" all_regs_mx0: &all_regs_mx0 "['x'+str(x) for x in range(1,32 if 'e' not in base_isa else 16)]" c_regs: &c_regs "['x'+str(x) for x in range(8,16)]" + c_fregs: &c_fregs "['x'+str(x) for x in range(8,16)]" pair_regs: &pair_regs "['x'+str(x) for x in range(2,32 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]" rv32rv64pair_regs: &rv32rv64pair_regs "['x'+str(x) for x in range(2,30 if 'e' not in base_isa else 16, 2)]" diff --git a/riscv-ctg/riscv_ctg/generator.py b/riscv-ctg/riscv_ctg/generator.py index 5e25cf17e..31e7bd525 100644 --- a/riscv-ctg/riscv_ctg/generator.py +++ b/riscv-ctg/riscv_ctg/generator.py @@ -260,7 +260,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str,inx is_nan_box = False - is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x for x in opnode['isa']]) + is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x or 'Zcf' in x or 'Zcd' in x for x in opnode['isa']]) is_sgn_extd = True if (inxFlag and iflen 0 and fcsr == 0, +// opcode:c.fld; op1:x14; dest:f14; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x14,f14,0xf8,c.fld,0,x4) + +inst_2: +// rs1==x13, rd==f13,imm_val == 168, +// opcode:c.fld; op1:x13; dest:f13; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x13,f13,0xa8,c.fld,0,x4) + +inst_3: +// rs1==x12, rd==f12,imm_val == 80, +// opcode:c.fld; op1:x12; dest:f12; immval:0x50; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x12,f12,0x50,c.fld,0,x4) + +inst_4: +// rs1==x11, rd==f11,imm_val == 8, +// opcode:c.fld; op1:x11; dest:f11; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x11,f11,0x8,c.fld,0,x4) + +inst_5: +// rs1==x10, rd==f10,imm_val == 16, +// opcode:c.fld; op1:x10; dest:f10; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x10,f10,0x10,c.fld,0,x4) + +inst_6: +// rs1==x9, rd==f9,imm_val == 240, +// opcode:c.fld; op1:x9; dest:f9; immval:0xf0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x9,f9,0xf0,c.fld,0,x4) + +inst_7: +// rs1==x8, rd==f8,imm_val == 232, +// opcode:c.fld; op1:x8; dest:f8; immval:0xe8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x8,f8,0xe8,c.fld,0,x4) + +inst_8: +// imm_val == 216, +// opcode:c.fld; op1:x15; dest:f15; immval:0xd8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0xd8,c.fld,0,x4) + +inst_9: +// imm_val == 184, +// opcode:c.fld; op1:x15; dest:f15; immval:0xb8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0xb8,c.fld,0,x4) + +inst_10: +// imm_val == 120, +// opcode:c.fld; op1:x15; dest:f15; immval:0x78; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x78,c.fld,0,x4) + +inst_11: +// imm_val == 32, +// opcode:c.fld; op1:x15; dest:f15; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x20,c.fld,0,x4) + +inst_12: +// imm_val == 64, +// opcode:c.fld; op1:x15; dest:f15; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x40,c.fld,0,x4) + +inst_13: +// imm_val == 128, +// opcode:c.fld; op1:x15; dest:f15; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x80,c.fld,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + + + + + + + + + + + + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fldsp-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fldsp-01.S new file mode 100644 index 000000000..579e37234 --- /dev/null +++ b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fldsp-01.S @@ -0,0 +1,247 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 04:57:10 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fldsp.cgf \ + \ +// -- xlen 64 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fldsp instruction of the RISC-V RV64FDC extension for the c.fldsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fldsp) + +RVTEST_FP_ENABLE() +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rd==f31, imm_val == 0, +// opcode:c.fldsp; op1:x2; dest:f31; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f31,0x0,c.fldsp,0,x4) + +inst_1: +// rd==f30, imm_val > 0, +// opcode:c.fldsp; op1:x2; dest:f30; immval:0x1f8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f30,0x1f8,c.fldsp,0,x4) + +inst_2: +// rd==f29, imm_val == 168, +// opcode:c.fldsp; op1:x2; dest:f29; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f29,0xa8,c.fldsp,0,x4) + +inst_3: +// rd==f28, imm_val == 336, +// opcode:c.fldsp; op1:x2; dest:f28; immval:0x150; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f28,0x150,c.fldsp,0,x4) + +inst_4: +// rd==f27, imm_val == 496, +// opcode:c.fldsp; op1:x2; dest:f27; immval:0x1f0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f27,0x1f0,c.fldsp,0,x4) + +inst_5: +// rd==f26, imm_val == 488, +// opcode:c.fldsp; op1:x2; dest:f26; immval:0x1e8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f26,0x1e8,c.fldsp,0,x4) + +inst_6: +// rd==f25, imm_val == 472, +// opcode:c.fldsp; op1:x2; dest:f25; immval:0x1d8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f25,0x1d8,c.fldsp,0,x4) + +inst_7: +// rd==f24, imm_val == 440, +// opcode:c.fldsp; op1:x2; dest:f24; immval:0x1b8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f24,0x1b8,c.fldsp,0,x4) + +inst_8: +// rd==f23, imm_val == 376, +// opcode:c.fldsp; op1:x2; dest:f23; immval:0x178; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f23,0x178,c.fldsp,0,x4) + +inst_9: +// rd==f22, imm_val == 248, +// opcode:c.fldsp; op1:x2; dest:f22; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f22,0xf8,c.fldsp,0,x4) + +inst_10: +// rd==f21, imm_val == 8, +// opcode:c.fldsp; op1:x2; dest:f21; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f21,0x8,c.fldsp,0,x4) + +inst_11: +// rd==f20, imm_val == 16, +// opcode:c.fldsp; op1:x2; dest:f20; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f20,0x10,c.fldsp,0,x4) + +inst_12: +// rd==f19, imm_val == 32, +// opcode:c.fldsp; op1:x2; dest:f19; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f19,0x20,c.fldsp,0,x4) + +inst_13: +// rd==f18, imm_val == 64, +// opcode:c.fldsp; op1:x2; dest:f18; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f18,0x40,c.fldsp,0,x4) + +inst_14: +// rd==f17, imm_val == 128, +// opcode:c.fldsp; op1:x2; dest:f17; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f17,0x80,c.fldsp,0,x4) + +inst_15: +// rd==f16, imm_val == 256, +// opcode:c.fldsp; op1:x2; dest:f16; immval:0x100; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f16,0x100,c.fldsp,0,x4) + +inst_16: +// rd==f15, +// opcode:c.fldsp; op1:x2; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f15,0x0,c.fldsp,0,x4) + +inst_17: +// rd==f14, +// opcode:c.fldsp; op1:x2; dest:f14; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f14,0x0,c.fldsp,0,x4) + +inst_18: +// rd==f13, +// opcode:c.fldsp; op1:x2; dest:f13; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f13,0x0,c.fldsp,0,x4) + +inst_19: +// rd==f12, +// opcode:c.fldsp; op1:x2; dest:f12; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f12,0x0,c.fldsp,0,x4) + +inst_20: +// rd==f11, +// opcode:c.fldsp; op1:x2; dest:f11; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f11,0x0,c.fldsp,0,x4) + +inst_21: +// rd==f10, +// opcode:c.fldsp; op1:x2; dest:f10; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f10,0x0,c.fldsp,0,x4) + +inst_22: +// rd==f9, +// opcode:c.fldsp; op1:x2; dest:f9; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f9,0x0,c.fldsp,0,x4) + +inst_23: +// rd==f8, +// opcode:c.fldsp; op1:x2; dest:f8; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f8,0x0,c.fldsp,0,x4) + +inst_24: +// rd==f7, +// opcode:c.fldsp; op1:x2; dest:f7; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f7,0x0,c.fldsp,0,x4) + +inst_25: +// rd==f6, +// opcode:c.fldsp; op1:x2; dest:f6; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f6,0x0,c.fldsp,0,x4) + +inst_26: +// rd==f5, +// opcode:c.fldsp; op1:x2; dest:f5; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f5,0x0,c.fldsp,0,x4) + +inst_27: +// rd==f4, +// opcode:c.fldsp; op1:x2; dest:f4; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f4,0x0,c.fldsp,0,x4) + +inst_28: +// rd==f3, +// opcode:c.fldsp; op1:x2; dest:f3; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f3,0x0,c.fldsp,0,x4) + +inst_29: +// rd==f2, +// opcode:c.fldsp; op1:x2; dest:f2; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f2,0x0,c.fldsp,0,x4) + +inst_30: +// rd==f1, +// opcode:c.fldsp; op1:x2; dest:f1; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f1,0x0,c.fldsp,0,x4) + +inst_31: +// rd==f0, +// opcode:c.fldsp; op1:x2; dest:f0; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f0,0x0,c.fldsp,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsd-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsd-01.S new file mode 100644 index 000000000..967a60248 --- /dev/null +++ b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsd-01.S @@ -0,0 +1,213 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Fri Aug 4 07:31:35 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsd instruction of the RISC-V RV32FDC_Zcd,RV64FDC_Zcd extension for the c.fsd covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fsd) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs1 != rs2, rs1==x15, rs2==f15,imm_val == 0, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0x0; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 0*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x0,0*SIGALIGN,c.fsd,0,x4,x3, 0*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_1) + +inst_1:// rs1==x14, rs2==f14,imm_val > 0, +// opcode: c.fsd; op1:x14; op2:f14; op2val:-0x1000001; immval:0xf8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 1*FLEN/8; +TEST_STORE_F(x1,x2,0,x14,f14,0xf8,2*SIGALIGN,c.fsd,0,x4,x3, 1*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_2:// rs1==x13, rs2==f13,imm_val == 168, +// opcode: c.fsd; op1:x13; op2:f13; op2val:-0x1000001; immval:0xa8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 2*FLEN/8; +TEST_STORE_F(x1,x2,0,x13,f13,0xa8,4*SIGALIGN,c.fsd,0,x4,x3, 2*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_3) + +inst_3:// rs1==x12, rs2==f12,imm_val == 80, +// opcode: c.fsd; op1:x12; op2:f12; op2val:-0x1000001; immval:0x50; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 3*FLEN/8; +TEST_STORE_F(x1,x2,0,x12,f12,0x50,6*SIGALIGN,c.fsd,0,x4,x3, 3*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_4) + +inst_4:// rs1==x11, rs2==f11,imm_val == 8, +// opcode: c.fsd; op1:x11; op2:f11; op2val:-0x1000001; immval:0x8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 4*FLEN/8; +TEST_STORE_F(x1,x2,0,x11,f11,0x8,8*SIGALIGN,c.fsd,0,x4,x3, 4*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_5) + +inst_5:// rs1==x10, rs2==f10,imm_val == 16, +// opcode: c.fsd; op1:x10; op2:f10; op2val:-0x1000001; immval:0x10; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 5*FLEN/8; +TEST_STORE_F(x1,x2,0,x10,f10,0x10,10*SIGALIGN,c.fsd,0,x4,x3, 5*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_6) + +inst_6:// rs1==x9, rs2==f9,imm_val == 240, +// opcode: c.fsd; op1:x9; op2:f9; op2val:-0x1000001; immval:0xf0; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 6*FLEN/8; +TEST_STORE_F(x1,x2,0,x9,f9,0xf0,12*SIGALIGN,c.fsd,0,x4,x3, 6*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_7) + +inst_7:// rs1==x8, rs2==f8,imm_val == 232, +// opcode: c.fsd; op1:x8; op2:f8; op2val:-0x1000001; immval:0xe8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 7*FLEN/8; +TEST_STORE_F(x1,x2,0,x8,f8,0xe8,14*SIGALIGN,c.fsd,0,x4,x3, 7*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_8) + +inst_8:// imm_val == 216, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0xd8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 8*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0xd8,16*SIGALIGN,c.fsd,0,x4,x3, 8*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_9) + +inst_9:// imm_val == 184, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0xb8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 9*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0xb8,18*SIGALIGN,c.fsd,0,x4,x3, 9*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_10) + +inst_10:// imm_val == 120, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0x78; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 10*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x78,20*SIGALIGN,c.fsd,0,x4,x3, 10*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_11) + +inst_11:// imm_val == 32, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0x20; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 11*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x20,22*SIGALIGN,c.fsd,0,x4,x3, 11*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_12) + +inst_12:// imm_val == 64, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0x40; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 12*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x40,24*SIGALIGN,c.fsd,0,x4,x3, 12*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_13) + +inst_13:// imm_val == 128, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0x80; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 13*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x80,26*SIGALIGN,c.fsd,0,x4,x3, 13*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + +test_dataset_1: + + +test_dataset_2: + + +test_dataset_3: + + +test_dataset_4: + + +test_dataset_5: + + +test_dataset_6: + + +test_dataset_7: + + +test_dataset_8: + + +test_dataset_9: + + +test_dataset_10: + + +test_dataset_11: + + +test_dataset_12: + + +test_dataset_13: + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsdsp-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsdsp-01.S new file mode 100644 index 000000000..5a044aa7a --- /dev/null +++ b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsdsp-01.S @@ -0,0 +1,343 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 04:41:22 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fsdsp.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsdsp instruction of the RISC-V RV32FDC,RV64FDC extension for the c.fsdsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFDC,RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*C.*);def TEST_CASE_1=True;",c.fsdsp) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs2==f31, imm_val == 0, +// opcode: c.fsdsp; op1:x2; op2:f31; op2val:-0x1000001; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 0*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f31,0x0,0*SIGALIGN,c.fsdsp,0,x5,x4,0*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_1) + +inst_1:// rs2==f30, imm_val > 0, +// opcode: c.fsdsp; op1:x2; op2:f30; op2val:-0x1000001; immval:0x1f8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 1*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f30,0x1f8,2*SIGALIGN,c.fsdsp,0,x5,x4,1*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_2:// rs2==f29, imm_val == 168, +// opcode: c.fsdsp; op1:x2; op2:f29; op2val:-0x1000001; immval:0xa8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 2*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f29,0xa8,4*SIGALIGN,c.fsdsp,0,x5,x4,2*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_3) + +inst_3:// rs2==f28, imm_val == 336, +// opcode: c.fsdsp; op1:x2; op2:f28; op2val:-0x1000001; immval:0x150; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 3*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f28,0x150,6*SIGALIGN,c.fsdsp,0,x5,x4,3*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_4) + +inst_4:// rs2==f27, imm_val == 496, +// opcode: c.fsdsp; op1:x2; op2:f27; op2val:-0x1000001; immval:0x1f0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 4*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f27,0x1f0,8*SIGALIGN,c.fsdsp,0,x5,x4,4*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_5) + +inst_5:// rs2==f26, imm_val == 488, +// opcode: c.fsdsp; op1:x2; op2:f26; op2val:-0x1000001; immval:0x1e8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 5*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f26,0x1e8,10*SIGALIGN,c.fsdsp,0,x5,x4,5*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_6) + +inst_6:// rs2==f25, imm_val == 472, +// opcode: c.fsdsp; op1:x2; op2:f25; op2val:-0x1000001; immval:0x1d8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 6*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f25,0x1d8,12*SIGALIGN,c.fsdsp,0,x5,x4,6*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_7) + +inst_7:// rs2==f24, imm_val == 440, +// opcode: c.fsdsp; op1:x2; op2:f24; op2val:-0x1000001; immval:0x1b8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 7*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f24,0x1b8,14*SIGALIGN,c.fsdsp,0,x5,x4,7*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_8) + +inst_8:// rs2==f23, imm_val == 376, +// opcode: c.fsdsp; op1:x2; op2:f23; op2val:-0x1000001; immval:0x178; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 8*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f23,0x178,16*SIGALIGN,c.fsdsp,0,x5,x4,8*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_9) + +inst_9:// rs2==f22, imm_val == 248, +// opcode: c.fsdsp; op1:x2; op2:f22; op2val:-0x1000001; immval:0xf8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 9*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f22,0xf8,18*SIGALIGN,c.fsdsp,0,x5,x4,9*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_10) + +inst_10:// rs2==f21, imm_val == 8, +// opcode: c.fsdsp; op1:x2; op2:f21; op2val:-0x1000001; immval:0x8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 10*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f21,0x8,20*SIGALIGN,c.fsdsp,0,x5,x4,10*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_11) + +inst_11:// rs2==f20, imm_val == 16, +// opcode: c.fsdsp; op1:x2; op2:f20; op2val:-0x1000001; immval:0x10; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 11*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f20,0x10,22*SIGALIGN,c.fsdsp,0,x5,x4,11*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_12) + +inst_12:// rs2==f19, imm_val == 32, +// opcode: c.fsdsp; op1:x2; op2:f19; op2val:-0x1000001; immval:0x20; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 12*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f19,0x20,24*SIGALIGN,c.fsdsp,0,x5,x4,12*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_13) + +inst_13:// rs2==f18, imm_val == 64, +// opcode: c.fsdsp; op1:x2; op2:f18; op2val:-0x1000001; immval:0x40; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 13*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f18,0x40,26*SIGALIGN,c.fsdsp,0,x5,x4,13*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_14) + +inst_14:// rs2==f17, imm_val == 128, +// opcode: c.fsdsp; op1:x2; op2:f17; op2val:-0x1000001; immval:0x80; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 14*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f17,0x80,28*SIGALIGN,c.fsdsp,0,x5,x4,14*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_15) + +inst_15:// rs2==f16, imm_val == 256, +// opcode: c.fsdsp; op1:x2; op2:f16; op2val:-0x1000001; immval:0x100; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 15*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f16,0x100,30*SIGALIGN,c.fsdsp,0,x5,x4,15*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_16) + +inst_16:// rs2==f15, +// opcode: c.fsdsp; op1:x2; op2:f15; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 16*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f15,0x0,32*SIGALIGN,c.fsdsp,0,x5,x4,16*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_17) + +inst_17:// rs2==f14, +// opcode: c.fsdsp; op1:x2; op2:f14; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 17*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f14,0x0,34*SIGALIGN,c.fsdsp,0,x5,x4,17*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_18) + +inst_18:// rs2==f13, +// opcode: c.fsdsp; op1:x2; op2:f13; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 18*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f13,0x0,36*SIGALIGN,c.fsdsp,0,x5,x4,18*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_19) + +inst_19:// rs2==f12, +// opcode: c.fsdsp; op1:x2; op2:f12; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 19*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f12,0x0,38*SIGALIGN,c.fsdsp,0,x5,x4,19*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_20) + +inst_20:// rs2==f11, +// opcode: c.fsdsp; op1:x2; op2:f11; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 20*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f11,0x0,40*SIGALIGN,c.fsdsp,0,x5,x4,20*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_21) + +inst_21:// rs2==f10, +// opcode: c.fsdsp; op1:x2; op2:f10; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 21*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f10,0x0,42*SIGALIGN,c.fsdsp,0,x5,x4,21*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_22) + +inst_22:// rs2==f9, +// opcode: c.fsdsp; op1:x2; op2:f9; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 22*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f9,0x0,44*SIGALIGN,c.fsdsp,0,x5,x4,22*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_23) + +inst_23:// rs2==f8, +// opcode: c.fsdsp; op1:x2; op2:f8; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 23*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f8,0x0,46*SIGALIGN,c.fsdsp,0,x5,x4,23*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_24) + +inst_24:// rs2==f7, +// opcode: c.fsdsp; op1:x2; op2:f7; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 24*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f7,0x0,48*SIGALIGN,c.fsdsp,0,x5,x4,24*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_25) + +inst_25:// rs2==f6, +// opcode: c.fsdsp; op1:x2; op2:f6; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 25*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f6,0x0,50*SIGALIGN,c.fsdsp,0,x5,x4,25*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_26) + +inst_26:// rs2==f5, +// opcode: c.fsdsp; op1:x2; op2:f5; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 26*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f5,0x0,52*SIGALIGN,c.fsdsp,0,x5,x4,26*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_27) + +inst_27:// rs2==f4, +// opcode: c.fsdsp; op1:x2; op2:f4; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 27*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f4,0x0,54*SIGALIGN,c.fsdsp,0,x5,x4,27*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_28) + +inst_28:// rs2==f3, +// opcode: c.fsdsp; op1:x2; op2:f3; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 28*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f3,0x0,56*SIGALIGN,c.fsdsp,0,x5,x4,28*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_29) + +inst_29:// rs2==f2, +// opcode: c.fsdsp; op1:x2; op2:f2; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 29*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f2,0x0,58*SIGALIGN,c.fsdsp,0,x5,x4,29*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_30) + +inst_30:// rs2==f1, +// opcode: c.fsdsp; op1:x2; op2:f1; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 30*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f1,0x0,60*SIGALIGN,c.fsdsp,0,x5,x4,30*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_31) + +inst_31:// rs2==f0, +// opcode: c.fsdsp; op1:x2; op2:f0; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 31*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f0,0x0,62*SIGALIGN,c.fsdsp,0,x5,x4,31*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + +test_dataset_1: + +test_dataset_2: + +test_dataset_3: + +test_dataset_4: + +test_dataset_5: + +test_dataset_6: + +test_dataset_7: + +test_dataset_8: + +test_dataset_9: + +test_dataset_10: + +test_dataset_11: + +test_dataset_12: + +test_dataset_13: + +test_dataset_14: + +test_dataset_15: + +test_dataset_16: + +test_dataset_17: + +test_dataset_18: + +test_dataset_19: + +test_dataset_20: + +test_dataset_21: + +test_dataset_22: + +test_dataset_23: + +test_dataset_24: + +test_dataset_25: + +test_dataset_26: + +test_dataset_27: + +test_dataset_28: + +test_dataset_29: + +test_dataset_30: + +test_dataset_31: + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.flw-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flw-01.S new file mode 100644 index 000000000..043e33306 --- /dev/null +++ b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flw-01.S @@ -0,0 +1,173 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Thu Aug 3 07:43:25 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/FLW.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.flw instruction of the RISC-V RV32F_Zcf extension for the c.flw covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zcf") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.flw) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1==x15, rd==f15,imm_val == 0 and fcsr == 0, +// opcode:c.flw; op1:x15; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x15,f15,0x0,c.flw,0,x4) + +inst_1: +// rs1==x14, rd==f14,imm_val > 0 and fcsr == 0, +// opcode:c.flw; op1:x14; dest:f14; immval:0x7c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x14,f14,0x7c,c.flw,0,x4) + +inst_2: +// rs1==x13, rd==f13,imm_val == 84, +// opcode:c.flw; op1:x13; dest:f13; immval:0x54; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x13,f13,0x54,c.flw,0,x4) + +inst_3: +// rs1==x12, rd==f12,imm_val == 40, +// opcode:c.flw; op1:x12; dest:f12; immval:0x28; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x12,f12,0x28,c.flw,0,x4) + +inst_4: +// rs1==x11, rd==f11,imm_val == 4, +// opcode:c.flw; op1:x11; dest:f11; immval:0x4; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x11,f11,0x4,c.flw,0,x4) + +inst_5: +// rs1==x10, rd==f10,imm_val == 120, +// opcode:c.flw; op1:x10; dest:f10; immval:0x78; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x10,f10,0x78,c.flw,0,x4) + +inst_6: +// rs1==x9, rd==f9,imm_val == 116, +// opcode:c.flw; op1:x9; dest:f9; immval:0x74; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x9,f9,0x74,c.flw,0,x4) + +inst_7: +// rs1==x8, rd==f8,imm_val == 108, +// opcode:c.flw; op1:x8; dest:f8; immval:0x6c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x8,f8,0x6c,c.flw,0,x4) + +inst_8: +// imm_val == 92, +// opcode:c.flw; op1:x15; dest:f15; immval:0x5c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x5c,c.flw,0,x4) + +inst_9: +// imm_val == 60, +// opcode:c.flw; op1:x15; dest:f15; immval:0x3c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x3c,c.flw,0,x4) + +inst_10: +// imm_val == 8, +// opcode:c.flw; op1:x15; dest:f15; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x8,c.flw,0,x4) + +inst_11: +// imm_val == 16, +// opcode:c.flw; op1:x15; dest:f15; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x10,c.flw,0,x4) + +inst_12: +// imm_val == 32, +// opcode:c.flw; op1:x15; dest:f15; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x20,c.flw,0,x4) + +inst_13: +// imm_val == 64, +// opcode:c.flw; op1:x15; dest:f15; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x40,c.flw,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + + + + + + + + + + + + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.flwsp-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flwsp-01.S new file mode 100644 index 000000000..33806012a --- /dev/null +++ b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flwsp-01.S @@ -0,0 +1,249 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Thu Aug 10 08:04:09 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/flwsp.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.flwsp instruction of the RISC-V RV32F_Zcf extension for the c.flwsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zcf") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.flwsp) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rd==f31, imm_val == 0 and fcsr == 0, +// opcode:c.flwsp; op1:x2; dest:f31; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f31,0x0,c.flwsp,0,x4) + +inst_1: +// rd==f30, imm_val > 0 and fcsr == 0, +// opcode:c.flwsp; op1:x2; dest:f30; immval:0xfc; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f30,0xfc,c.flwsp,0,x4) + +inst_2: +// rd==f29, imm_val == 84, +// opcode:c.flwsp; op1:x2; dest:f29; immval:0x54; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f29,0x54,c.flwsp,0,x4) + +inst_3: +// rd==f28, imm_val == 168, +// opcode:c.flwsp; op1:x2; dest:f28; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f28,0xa8,c.flwsp,0,x4) + +inst_4: +// rd==f27, imm_val == 248, +// opcode:c.flwsp; op1:x2; dest:f27; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f27,0xf8,c.flwsp,0,x4) + +inst_5: +// rd==f26, imm_val == 244, +// opcode:c.flwsp; op1:x2; dest:f26; immval:0xf4; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f26,0xf4,c.flwsp,0,x4) + +inst_6: +// rd==f25, imm_val == 236, +// opcode:c.flwsp; op1:x2; dest:f25; immval:0xec; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f25,0xec,c.flwsp,0,x4) + +inst_7: +// rd==f24, imm_val == 220, +// opcode:c.flwsp; op1:x2; dest:f24; immval:0xdc; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f24,0xdc,c.flwsp,0,x4) + +inst_8: +// rd==f23, imm_val == 188, +// opcode:c.flwsp; op1:x2; dest:f23; immval:0xbc; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f23,0xbc,c.flwsp,0,x4) + +inst_9: +// rd==f22, imm_val == 124, +// opcode:c.flwsp; op1:x2; dest:f22; immval:0x7c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f22,0x7c,c.flwsp,0,x4) + +inst_10: +// rd==f21, imm_val == 4, +// opcode:c.flwsp; op1:x2; dest:f21; immval:0x4; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f21,0x4,c.flwsp,0,x4) + +inst_11: +// rd==f20, imm_val == 8, +// opcode:c.flwsp; op1:x2; dest:f20; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f20,0x8,c.flwsp,0,x4) + +inst_12: +// rd==f19, imm_val == 16, +// opcode:c.flwsp; op1:x2; dest:f19; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f19,0x10,c.flwsp,0,x4) + +inst_13: +// rd==f18, imm_val == 32, +// opcode:c.flwsp; op1:x2; dest:f18; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f18,0x20,c.flwsp,0,x4) + +inst_14: +// rd==f17, imm_val == 64, +// opcode:c.flwsp; op1:x2; dest:f17; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f17,0x40,c.flwsp,0,x4) + +inst_15: +// rd==f16, imm_val == 128, +// opcode:c.flwsp; op1:x2; dest:f16; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f16,0x80,c.flwsp,0,x4) + +inst_16: +// rd==f15, +// opcode:c.flwsp; op1:x2; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f15,0x0,c.flwsp,0,x4) + +inst_17: +// rd==f14, +// opcode:c.flwsp; op1:x2; dest:f14; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f14,0x0,c.flwsp,0,x4) + +inst_18: +// rd==f13, +// opcode:c.flwsp; op1:x2; dest:f13; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f13,0x0,c.flwsp,0,x4) + +inst_19: +// rd==f12, +// opcode:c.flwsp; op1:x2; dest:f12; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f12,0x0,c.flwsp,0,x4) + +inst_20: +// rd==f11, +// opcode:c.flwsp; op1:x2; dest:f11; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f11,0x0,c.flwsp,0,x4) + +inst_21: +// rd==f10, +// opcode:c.flwsp; op1:x2; dest:f10; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f10,0x0,c.flwsp,0,x4) + +inst_22: +// rd==f9, +// opcode:c.flwsp; op1:x2; dest:f9; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f9,0x0,c.flwsp,0,x4) + +inst_23: +// rd==f8, +// opcode:c.flwsp; op1:x2; dest:f8; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f8,0x0,c.flwsp,0,x4) + +inst_24: +// rd==f7, +// opcode:c.flwsp; op1:x2; dest:f7; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f7,0x0,c.flwsp,0,x4) + +inst_25: +// rd==f6, +// opcode:c.flwsp; op1:x2; dest:f6; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f6,0x0,c.flwsp,0,x4) + +inst_26: +// rd==f5, +// opcode:c.flwsp; op1:x2; dest:f5; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f5,0x0,c.flwsp,0,x4) + +inst_27: +// rd==f4, +// opcode:c.flwsp; op1:x2; dest:f4; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f4,0x0,c.flwsp,0,x4) + +inst_28: +// rd==f3, +// opcode:c.flwsp; op1:x2; dest:f3; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f3,0x0,c.flwsp,0,x4) + +inst_29: +// rd==f2, +// opcode:c.flwsp; op1:x2; dest:f2; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f2,0x0,c.flwsp,0,x4) + +inst_30: +// rd==f1, +// opcode:c.flwsp; op1:x2; dest:f1; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f1,0x0,c.flwsp,0,x4) + +inst_31: +// rd==f0, +// opcode:c.flwsp; op1:x2; dest:f0; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f0,0x0,c.flwsp,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.fsw-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fsw-01.S new file mode 100644 index 000000000..7b95fadd6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fsw-01.S @@ -0,0 +1,213 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Thu Aug 3 07:43:25 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/FLW.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsw instruction of the RISC-V RV32F_Zcf extension for the c.fsw covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zcf") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.fsw) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs1 != rs2, rs1==x15, rs2==f15,imm_val == 0, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x0; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 0*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x0,0*SIGALIGN,c.fsw,0,x4,x3, 0*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_1) + +inst_1:// rs1==x14, rs2==f14,imm_val > 0, +// opcode: c.fsw; op1:x14; op2:f14; op2val:-0x1000001; immval:0x7c; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 1*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x14,f14,0x7c,1*SIGALIGN,c.fsw,0,x4,x3, 1*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_2:// rs1==x13, rs2==f13,imm_val == 84, +// opcode: c.fsw; op1:x13; op2:f13; op2val:-0x1000001; immval:0x54; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 2*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x13,f13,0x54,2*SIGALIGN,c.fsw,0,x4,x3, 2*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_3) + +inst_3:// rs1==x12, rs2==f12,imm_val == 40, +// opcode: c.fsw; op1:x12; op2:f12; op2val:-0x1000001; immval:0x28; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 3*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x12,f12,0x28,3*SIGALIGN,c.fsw,0,x4,x3, 3*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_4) + +inst_4:// rs1==x11, rs2==f11,imm_val == 4, +// opcode: c.fsw; op1:x11; op2:f11; op2val:-0x1000001; immval:0x4; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 4*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x11,f11,0x4,4*SIGALIGN,c.fsw,0,x4,x3, 4*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_5) + +inst_5:// rs1==x10, rs2==f10,imm_val == 8, +// opcode: c.fsw; op1:x10; op2:f10; op2val:-0x1000001; immval:0x8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 5*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x10,f10,0x8,5*SIGALIGN,c.fsw,0,x4,x3, 5*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_6) + +inst_6:// rs1==x9, rs2==f9,imm_val == 120, +// opcode: c.fsw; op1:x9; op2:f9; op2val:-0x1000001; immval:0x78; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 6*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x9,f9,0x78,6*SIGALIGN,c.fsw,0,x4,x3, 6*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_7) + +inst_7:// rs1==x8, rs2==f8,imm_val == 116, +// opcode: c.fsw; op1:x8; op2:f8; op2val:-0x1000001; immval:0x74; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 7*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x8,f8,0x74,7*SIGALIGN,c.fsw,0,x4,x3, 7*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_8) + +inst_8:// imm_val == 108, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x6c; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 8*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x6c,8*SIGALIGN,c.fsw,0,x4,x3, 8*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_9) + +inst_9:// imm_val == 92, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x5c; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 9*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x5c,9*SIGALIGN,c.fsw,0,x4,x3, 9*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_10) + +inst_10:// imm_val == 60, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x3c; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 10*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x3c,10*SIGALIGN,c.fsw,0,x4,x3, 10*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_11) + +inst_11:// imm_val == 16, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x10; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 11*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x10,11*SIGALIGN,c.fsw,0,x4,x3, 11*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_12) + +inst_12:// imm_val == 32, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x20; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 12*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x20,12*SIGALIGN,c.fsw,0,x4,x3, 12*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_13) + +inst_13:// imm_val == 64, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x40; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 13*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x40,13*SIGALIGN,c.fsw,0,x4,x3, 13*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + +test_dataset_1: + + +test_dataset_2: + + +test_dataset_3: + + +test_dataset_4: + + +test_dataset_5: + + +test_dataset_6: + + +test_dataset_7: + + +test_dataset_8: + + +test_dataset_9: + + +test_dataset_10: + + +test_dataset_11: + + +test_dataset_12: + + +test_dataset_13: + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 14*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.fswsp-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fswsp-01.S new file mode 100644 index 000000000..7908a2bb8 --- /dev/null +++ b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fswsp-01.S @@ -0,0 +1,343 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 04:45:36 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fswsp.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fswsp instruction of the RISC-V RV32FC extension for the c.fswsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*C.*);def TEST_CASE_1=True;",c.fswsp) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs2==f31, imm_val == 0, +// opcode: c.fswsp; op1:x2; op2:f31; op2val:-0x1000001; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 0*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f31,0x0,0*SIGALIGN,c.fswsp,0,x5,x4,0*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_1) + +inst_1:// rs2==f30, imm_val > 0, +// opcode: c.fswsp; op1:x2; op2:f30; op2val:-0x1000001; immval:0xfc; align:0; flagreg:x5; +// valreg: x4; valoffset: 1*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f30,0xfc,1*SIGALIGN,c.fswsp,0,x5,x4,1*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_2:// rs2==f29, imm_val == 84, +// opcode: c.fswsp; op1:x2; op2:f29; op2val:-0x1000001; immval:0x54; align:0; flagreg:x5; +// valreg: x4; valoffset: 2*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f29,0x54,2*SIGALIGN,c.fswsp,0,x5,x4,2*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_3) + +inst_3:// rs2==f28, imm_val == 168, +// opcode: c.fswsp; op1:x2; op2:f28; op2val:-0x1000001; immval:0xa8; align:0; flagreg:x5; +// valreg: x4; valoffset: 3*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f28,0xa8,3*SIGALIGN,c.fswsp,0,x5,x4,3*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_4) + +inst_4:// rs2==f27, imm_val == 248, +// opcode: c.fswsp; op1:x2; op2:f27; op2val:-0x1000001; immval:0xf8; align:0; flagreg:x5; +// valreg: x4; valoffset: 4*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f27,0xf8,4*SIGALIGN,c.fswsp,0,x5,x4,4*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_5) + +inst_5:// rs2==f26, imm_val == 244, +// opcode: c.fswsp; op1:x2; op2:f26; op2val:-0x1000001; immval:0xf4; align:0; flagreg:x5; +// valreg: x4; valoffset: 5*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f26,0xf4,5*SIGALIGN,c.fswsp,0,x5,x4,5*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_6) + +inst_6:// rs2==f25, imm_val == 236, +// opcode: c.fswsp; op1:x2; op2:f25; op2val:-0x1000001; immval:0xec; align:0; flagreg:x5; +// valreg: x4; valoffset: 6*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f25,0xec,6*SIGALIGN,c.fswsp,0,x5,x4,6*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_7) + +inst_7:// rs2==f24, imm_val == 220, +// opcode: c.fswsp; op1:x2; op2:f24; op2val:-0x1000001; immval:0xdc; align:0; flagreg:x5; +// valreg: x4; valoffset: 7*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f24,0xdc,7*SIGALIGN,c.fswsp,0,x5,x4,7*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_8) + +inst_8:// rs2==f23, imm_val == 188, +// opcode: c.fswsp; op1:x2; op2:f23; op2val:-0x1000001; immval:0xbc; align:0; flagreg:x5; +// valreg: x4; valoffset: 8*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f23,0xbc,8*SIGALIGN,c.fswsp,0,x5,x4,8*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_9) + +inst_9:// rs2==f22, imm_val == 124, +// opcode: c.fswsp; op1:x2; op2:f22; op2val:-0x1000001; immval:0x7c; align:0; flagreg:x5; +// valreg: x4; valoffset: 9*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f22,0x7c,9*SIGALIGN,c.fswsp,0,x5,x4,9*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_10) + +inst_10:// rs2==f21, imm_val == 4, +// opcode: c.fswsp; op1:x2; op2:f21; op2val:-0x1000001; immval:0x4; align:0; flagreg:x5; +// valreg: x4; valoffset: 10*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f21,0x4,10*SIGALIGN,c.fswsp,0,x5,x4,10*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_11) + +inst_11:// rs2==f20, imm_val == 8, +// opcode: c.fswsp; op1:x2; op2:f20; op2val:-0x1000001; immval:0x8; align:0; flagreg:x5; +// valreg: x4; valoffset: 11*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f20,0x8,11*SIGALIGN,c.fswsp,0,x5,x4,11*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_12) + +inst_12:// rs2==f19, imm_val == 16, +// opcode: c.fswsp; op1:x2; op2:f19; op2val:-0x1000001; immval:0x10; align:0; flagreg:x5; +// valreg: x4; valoffset: 12*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f19,0x10,12*SIGALIGN,c.fswsp,0,x5,x4,12*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_13) + +inst_13:// rs2==f18, imm_val == 32, +// opcode: c.fswsp; op1:x2; op2:f18; op2val:-0x1000001; immval:0x20; align:0; flagreg:x5; +// valreg: x4; valoffset: 13*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f18,0x20,13*SIGALIGN,c.fswsp,0,x5,x4,13*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_14) + +inst_14:// rs2==f17, imm_val == 64, +// opcode: c.fswsp; op1:x2; op2:f17; op2val:-0x1000001; immval:0x40; align:0; flagreg:x5; +// valreg: x4; valoffset: 14*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f17,0x40,14*SIGALIGN,c.fswsp,0,x5,x4,14*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_15) + +inst_15:// rs2==f16, imm_val == 128, +// opcode: c.fswsp; op1:x2; op2:f16; op2val:-0x1000001; immval:0x80; align:0; flagreg:x5; +// valreg: x4; valoffset: 15*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f16,0x80,15*SIGALIGN,c.fswsp,0,x5,x4,15*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_16) + +inst_16:// rs2==f15, +// opcode: c.fswsp; op1:x2; op2:f15; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 16*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f15,0x0,16*SIGALIGN,c.fswsp,0,x5,x4,16*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_17) + +inst_17:// rs2==f14, +// opcode: c.fswsp; op1:x2; op2:f14; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 17*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f14,0x0,17*SIGALIGN,c.fswsp,0,x5,x4,17*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_18) + +inst_18:// rs2==f13, +// opcode: c.fswsp; op1:x2; op2:f13; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 18*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f13,0x0,18*SIGALIGN,c.fswsp,0,x5,x4,18*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_19) + +inst_19:// rs2==f12, +// opcode: c.fswsp; op1:x2; op2:f12; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 19*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f12,0x0,19*SIGALIGN,c.fswsp,0,x5,x4,19*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_20) + +inst_20:// rs2==f11, +// opcode: c.fswsp; op1:x2; op2:f11; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 20*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f11,0x0,20*SIGALIGN,c.fswsp,0,x5,x4,20*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_21) + +inst_21:// rs2==f10, +// opcode: c.fswsp; op1:x2; op2:f10; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 21*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f10,0x0,21*SIGALIGN,c.fswsp,0,x5,x4,21*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_22) + +inst_22:// rs2==f9, +// opcode: c.fswsp; op1:x2; op2:f9; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 22*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f9,0x0,22*SIGALIGN,c.fswsp,0,x5,x4,22*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_23) + +inst_23:// rs2==f8, +// opcode: c.fswsp; op1:x2; op2:f8; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 23*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f8,0x0,23*SIGALIGN,c.fswsp,0,x5,x4,23*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_24) + +inst_24:// rs2==f7, +// opcode: c.fswsp; op1:x2; op2:f7; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 24*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f7,0x0,24*SIGALIGN,c.fswsp,0,x5,x4,24*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_25) + +inst_25:// rs2==f6, +// opcode: c.fswsp; op1:x2; op2:f6; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 25*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f6,0x0,25*SIGALIGN,c.fswsp,0,x5,x4,25*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_26) + +inst_26:// rs2==f5, +// opcode: c.fswsp; op1:x2; op2:f5; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 26*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f5,0x0,26*SIGALIGN,c.fswsp,0,x5,x4,26*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_27) + +inst_27:// rs2==f4, +// opcode: c.fswsp; op1:x2; op2:f4; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 27*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f4,0x0,27*SIGALIGN,c.fswsp,0,x5,x4,27*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_28) + +inst_28:// rs2==f3, +// opcode: c.fswsp; op1:x2; op2:f3; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 28*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f3,0x0,28*SIGALIGN,c.fswsp,0,x5,x4,28*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_29) + +inst_29:// rs2==f2, +// opcode: c.fswsp; op1:x2; op2:f2; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 29*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f2,0x0,29*SIGALIGN,c.fswsp,0,x5,x4,29*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_30) + +inst_30:// rs2==f1, +// opcode: c.fswsp; op1:x2; op2:f1; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 30*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f1,0x0,30*SIGALIGN,c.fswsp,0,x5,x4,30*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_31) + +inst_31:// rs2==f0, +// opcode: c.fswsp; op1:x2; op2:f0; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 31*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f0,0x0,31*SIGALIGN,c.fswsp,0,x5,x4,31*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + +test_dataset_1: + +test_dataset_2: + +test_dataset_3: + +test_dataset_4: + +test_dataset_5: + +test_dataset_6: + +test_dataset_7: + +test_dataset_8: + +test_dataset_9: + +test_dataset_10: + +test_dataset_11: + +test_dataset_12: + +test_dataset_13: + +test_dataset_14: + +test_dataset_15: + +test_dataset_16: + +test_dataset_17: + +test_dataset_18: + +test_dataset_19: + +test_dataset_20: + +test_dataset_21: + +test_dataset_22: + +test_dataset_23: + +test_dataset_24: + +test_dataset_25: + +test_dataset_26: + +test_dataset_27: + +test_dataset_28: + +test_dataset_29: + +test_dataset_30: + +test_dataset_31: + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END From fd7add27c2e2953b3f0a8fa934b15c4b63898056 Mon Sep 17 00:00:00 2001 From: anuani21 <114156183+anuani21@users.noreply.github.com> Date: Tue, 31 Dec 2024 12:37:50 +0530 Subject: [PATCH 02/10] [ACT] [CTG] [ISAC] Add support Zcd extension in RV64 (#587) * Updated Zcf and Zcd test case * Updated Zcf and Zcd instruction support with respect to riscv-ctg and riscv-isac * Added test cases for RV64Zcd --------- Signed-off-by: anuani21 <114156183+anuani21@users.noreply.github.com> Co-authored-by: James Shi --- riscv-test-suite/rv64i_m/D_Zcd/src/c.fld-01.S | 173 +++++++++ .../rv64i_m/D_Zcd/src/c.fldsp-01.S | 247 +++++++++++++ riscv-test-suite/rv64i_m/D_Zcd/src/c.fsd-01.S | 213 +++++++++++ .../rv64i_m/D_Zcd/src/c.fsdsp-01.S | 343 ++++++++++++++++++ 4 files changed, 976 insertions(+) create mode 100644 riscv-test-suite/rv64i_m/D_Zcd/src/c.fld-01.S create mode 100644 riscv-test-suite/rv64i_m/D_Zcd/src/c.fldsp-01.S create mode 100644 riscv-test-suite/rv64i_m/D_Zcd/src/c.fsd-01.S create mode 100644 riscv-test-suite/rv64i_m/D_Zcd/src/c.fsdsp-01.S diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fld-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fld-01.S new file mode 100644 index 000000000..905d4833c --- /dev/null +++ b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fld-01.S @@ -0,0 +1,173 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 05:06:00 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 64 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fld instruction of the RISC-V RV64FDC extension for the c.fld covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fld) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==x15, rd==f15,imm_val == 0 and fcsr == 0, +// opcode:c.fld; op1:x15; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x15,f15,0x0,c.fld,0,x4) + +inst_1: +// rs1==x14, rd==f14,imm_val > 0 and fcsr == 0, +// opcode:c.fld; op1:x14; dest:f14; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x14,f14,0xf8,c.fld,0,x4) + +inst_2: +// rs1==x13, rd==f13,imm_val == 168, +// opcode:c.fld; op1:x13; dest:f13; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x13,f13,0xa8,c.fld,0,x4) + +inst_3: +// rs1==x12, rd==f12,imm_val == 80, +// opcode:c.fld; op1:x12; dest:f12; immval:0x50; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x12,f12,0x50,c.fld,0,x4) + +inst_4: +// rs1==x11, rd==f11,imm_val == 8, +// opcode:c.fld; op1:x11; dest:f11; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x11,f11,0x8,c.fld,0,x4) + +inst_5: +// rs1==x10, rd==f10,imm_val == 16, +// opcode:c.fld; op1:x10; dest:f10; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x10,f10,0x10,c.fld,0,x4) + +inst_6: +// rs1==x9, rd==f9,imm_val == 240, +// opcode:c.fld; op1:x9; dest:f9; immval:0xf0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x9,f9,0xf0,c.fld,0,x4) + +inst_7: +// rs1==x8, rd==f8,imm_val == 232, +// opcode:c.fld; op1:x8; dest:f8; immval:0xe8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x8,f8,0xe8,c.fld,0,x4) + +inst_8: +// imm_val == 216, +// opcode:c.fld; op1:x15; dest:f15; immval:0xd8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0xd8,c.fld,0,x4) + +inst_9: +// imm_val == 184, +// opcode:c.fld; op1:x15; dest:f15; immval:0xb8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0xb8,c.fld,0,x4) + +inst_10: +// imm_val == 120, +// opcode:c.fld; op1:x15; dest:f15; immval:0x78; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x78,c.fld,0,x4) + +inst_11: +// imm_val == 32, +// opcode:c.fld; op1:x15; dest:f15; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x20,c.fld,0,x4) + +inst_12: +// imm_val == 64, +// opcode:c.fld; op1:x15; dest:f15; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x40,c.fld,0,x4) + +inst_13: +// imm_val == 128, +// opcode:c.fld; op1:x15; dest:f15; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x80,c.fld,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + + + + + + + + + + + + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fldsp-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fldsp-01.S new file mode 100644 index 000000000..8594fffd0 --- /dev/null +++ b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fldsp-01.S @@ -0,0 +1,247 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 05:06:00 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 64 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fldsp instruction of the RISC-V RV64FDC extension for the c.fldsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fldsp) + +RVTEST_FP_ENABLE() +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rd==f31, imm_val == 0, +// opcode:c.fldsp; op1:x2; dest:f31; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f31,0x0,c.fldsp,0,x4) + +inst_1: +// rd==f30, imm_val > 0, +// opcode:c.fldsp; op1:x2; dest:f30; immval:0x1f8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f30,0x1f8,c.fldsp,0,x4) + +inst_2: +// rd==f29, imm_val == 168, +// opcode:c.fldsp; op1:x2; dest:f29; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f29,0xa8,c.fldsp,0,x4) + +inst_3: +// rd==f28, imm_val == 336, +// opcode:c.fldsp; op1:x2; dest:f28; immval:0x150; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f28,0x150,c.fldsp,0,x4) + +inst_4: +// rd==f27, imm_val == 496, +// opcode:c.fldsp; op1:x2; dest:f27; immval:0x1f0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f27,0x1f0,c.fldsp,0,x4) + +inst_5: +// rd==f26, imm_val == 488, +// opcode:c.fldsp; op1:x2; dest:f26; immval:0x1e8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f26,0x1e8,c.fldsp,0,x4) + +inst_6: +// rd==f25, imm_val == 472, +// opcode:c.fldsp; op1:x2; dest:f25; immval:0x1d8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f25,0x1d8,c.fldsp,0,x4) + +inst_7: +// rd==f24, imm_val == 440, +// opcode:c.fldsp; op1:x2; dest:f24; immval:0x1b8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f24,0x1b8,c.fldsp,0,x4) + +inst_8: +// rd==f23, imm_val == 376, +// opcode:c.fldsp; op1:x2; dest:f23; immval:0x178; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f23,0x178,c.fldsp,0,x4) + +inst_9: +// rd==f22, imm_val == 248, +// opcode:c.fldsp; op1:x2; dest:f22; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f22,0xf8,c.fldsp,0,x4) + +inst_10: +// rd==f21, imm_val == 8, +// opcode:c.fldsp; op1:x2; dest:f21; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f21,0x8,c.fldsp,0,x4) + +inst_11: +// rd==f20, imm_val == 16, +// opcode:c.fldsp; op1:x2; dest:f20; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f20,0x10,c.fldsp,0,x4) + +inst_12: +// rd==f19, imm_val == 32, +// opcode:c.fldsp; op1:x2; dest:f19; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f19,0x20,c.fldsp,0,x4) + +inst_13: +// rd==f18, imm_val == 64, +// opcode:c.fldsp; op1:x2; dest:f18; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f18,0x40,c.fldsp,0,x4) + +inst_14: +// rd==f17, imm_val == 128, +// opcode:c.fldsp; op1:x2; dest:f17; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f17,0x80,c.fldsp,0,x4) + +inst_15: +// rd==f16, imm_val == 256, +// opcode:c.fldsp; op1:x2; dest:f16; immval:0x100; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f16,0x100,c.fldsp,0,x4) + +inst_16: +// rd==f15, +// opcode:c.fldsp; op1:x2; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f15,0x0,c.fldsp,0,x4) + +inst_17: +// rd==f14, +// opcode:c.fldsp; op1:x2; dest:f14; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f14,0x0,c.fldsp,0,x4) + +inst_18: +// rd==f13, +// opcode:c.fldsp; op1:x2; dest:f13; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f13,0x0,c.fldsp,0,x4) + +inst_19: +// rd==f12, +// opcode:c.fldsp; op1:x2; dest:f12; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f12,0x0,c.fldsp,0,x4) + +inst_20: +// rd==f11, +// opcode:c.fldsp; op1:x2; dest:f11; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f11,0x0,c.fldsp,0,x4) + +inst_21: +// rd==f10, +// opcode:c.fldsp; op1:x2; dest:f10; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f10,0x0,c.fldsp,0,x4) + +inst_22: +// rd==f9, +// opcode:c.fldsp; op1:x2; dest:f9; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f9,0x0,c.fldsp,0,x4) + +inst_23: +// rd==f8, +// opcode:c.fldsp; op1:x2; dest:f8; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f8,0x0,c.fldsp,0,x4) + +inst_24: +// rd==f7, +// opcode:c.fldsp; op1:x2; dest:f7; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f7,0x0,c.fldsp,0,x4) + +inst_25: +// rd==f6, +// opcode:c.fldsp; op1:x2; dest:f6; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f6,0x0,c.fldsp,0,x4) + +inst_26: +// rd==f5, +// opcode:c.fldsp; op1:x2; dest:f5; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f5,0x0,c.fldsp,0,x4) + +inst_27: +// rd==f4, +// opcode:c.fldsp; op1:x2; dest:f4; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f4,0x0,c.fldsp,0,x4) + +inst_28: +// rd==f3, +// opcode:c.fldsp; op1:x2; dest:f3; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f3,0x0,c.fldsp,0,x4) + +inst_29: +// rd==f2, +// opcode:c.fldsp; op1:x2; dest:f2; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f2,0x0,c.fldsp,0,x4) + +inst_30: +// rd==f1, +// opcode:c.fldsp; op1:x2; dest:f1; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f1,0x0,c.fldsp,0,x4) + +inst_31: +// rd==f0, +// opcode:c.fldsp; op1:x2; dest:f0; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f0,0x0,c.fldsp,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsd-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsd-01.S new file mode 100644 index 000000000..b09cc9731 --- /dev/null +++ b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsd-01.S @@ -0,0 +1,213 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 05:06:00 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 64 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsd instruction of the RISC-V RV64FDC extension for the c.fsd covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fsd) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs1 != rs2, rs1==x15, rs2==f15,imm_val == 0, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0x0; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 0*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x0,0*SIGALIGN,c.fsd,0,x4,x3, 0*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_1) + +inst_1:// rs1==x14, rs2==f14,imm_val > 0, +// opcode: c.fsd; op1:x14; op2:f14; op2val:-0x1; immval:0xf8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 1*FLEN/8; +TEST_STORE_F(x1,x2,0,x14,f14,0xf8,2*SIGALIGN,c.fsd,0,x4,x3, 1*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_2:// rs1==x13, rs2==f13,imm_val == 168, +// opcode: c.fsd; op1:x13; op2:f13; op2val:-0x1; immval:0xa8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 2*FLEN/8; +TEST_STORE_F(x1,x2,0,x13,f13,0xa8,4*SIGALIGN,c.fsd,0,x4,x3, 2*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_3) + +inst_3:// rs1==x12, rs2==f12,imm_val == 80, +// opcode: c.fsd; op1:x12; op2:f12; op2val:-0x1; immval:0x50; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 3*FLEN/8; +TEST_STORE_F(x1,x2,0,x12,f12,0x50,6*SIGALIGN,c.fsd,0,x4,x3, 3*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_4) + +inst_4:// rs1==x11, rs2==f11,imm_val == 8, +// opcode: c.fsd; op1:x11; op2:f11; op2val:-0x1; immval:0x8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 4*FLEN/8; +TEST_STORE_F(x1,x2,0,x11,f11,0x8,8*SIGALIGN,c.fsd,0,x4,x3, 4*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_5) + +inst_5:// rs1==x10, rs2==f10,imm_val == 16, +// opcode: c.fsd; op1:x10; op2:f10; op2val:-0x1; immval:0x10; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 5*FLEN/8; +TEST_STORE_F(x1,x2,0,x10,f10,0x10,10*SIGALIGN,c.fsd,0,x4,x3, 5*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_6) + +inst_6:// rs1==x9, rs2==f9,imm_val == 240, +// opcode: c.fsd; op1:x9; op2:f9; op2val:-0x1; immval:0xf0; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 6*FLEN/8; +TEST_STORE_F(x1,x2,0,x9,f9,0xf0,12*SIGALIGN,c.fsd,0,x4,x3, 6*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_7) + +inst_7:// rs1==x8, rs2==f8,imm_val == 232, +// opcode: c.fsd; op1:x8; op2:f8; op2val:-0x1; immval:0xe8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 7*FLEN/8; +TEST_STORE_F(x1,x2,0,x8,f8,0xe8,14*SIGALIGN,c.fsd,0,x4,x3, 7*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_8) + +inst_8:// imm_val == 216, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0xd8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 8*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0xd8,16*SIGALIGN,c.fsd,0,x4,x3, 8*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_9) + +inst_9:// imm_val == 184, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0xb8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 9*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0xb8,18*SIGALIGN,c.fsd,0,x4,x3, 9*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_10) + +inst_10:// imm_val == 120, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0x78; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 10*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x78,20*SIGALIGN,c.fsd,0,x4,x3, 10*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_11) + +inst_11:// imm_val == 32, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0x20; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 11*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x20,22*SIGALIGN,c.fsd,0,x4,x3, 11*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_12) + +inst_12:// imm_val == 64, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0x40; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 12*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x40,24*SIGALIGN,c.fsd,0,x4,x3, 12*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_13) + +inst_13:// imm_val == 128, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0x80; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 13*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x80,26*SIGALIGN,c.fsd,0,x4,x3, 13*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + +test_dataset_1: + + +test_dataset_2: + + +test_dataset_3: + + +test_dataset_4: + + +test_dataset_5: + + +test_dataset_6: + + +test_dataset_7: + + +test_dataset_8: + + +test_dataset_9: + + +test_dataset_10: + + +test_dataset_11: + + +test_dataset_12: + + +test_dataset_13: + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsdsp-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsdsp-01.S new file mode 100644 index 000000000..51ba670e0 --- /dev/null +++ b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsdsp-01.S @@ -0,0 +1,343 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 05:06:00 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 64 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsdsp instruction of the RISC-V RV64FDC extension for the c.fsdsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*C.*);def TEST_CASE_1=True;",c.fsdsp) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs2==f31, imm_val == 0, +// opcode: c.fsdsp; op1:x2; op2:f31; op2val:-0x1; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 0*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f31,0x0,0*SIGALIGN,c.fsdsp,0,x5,x4,0*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_1) + +inst_1:// rs2==f30, imm_val > 0, +// opcode: c.fsdsp; op1:x2; op2:f30; op2val:-0x1; immval:0x1f8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 1*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f30,0x1f8,2*SIGALIGN,c.fsdsp,0,x5,x4,1*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_2:// rs2==f29, imm_val == 168, +// opcode: c.fsdsp; op1:x2; op2:f29; op2val:-0x1; immval:0xa8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 2*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f29,0xa8,4*SIGALIGN,c.fsdsp,0,x5,x4,2*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_3) + +inst_3:// rs2==f28, imm_val == 336, +// opcode: c.fsdsp; op1:x2; op2:f28; op2val:-0x1; immval:0x150; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 3*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f28,0x150,6*SIGALIGN,c.fsdsp,0,x5,x4,3*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_4) + +inst_4:// rs2==f27, imm_val == 496, +// opcode: c.fsdsp; op1:x2; op2:f27; op2val:-0x1; immval:0x1f0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 4*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f27,0x1f0,8*SIGALIGN,c.fsdsp,0,x5,x4,4*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_5) + +inst_5:// rs2==f26, imm_val == 488, +// opcode: c.fsdsp; op1:x2; op2:f26; op2val:-0x1; immval:0x1e8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 5*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f26,0x1e8,10*SIGALIGN,c.fsdsp,0,x5,x4,5*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_6) + +inst_6:// rs2==f25, imm_val == 472, +// opcode: c.fsdsp; op1:x2; op2:f25; op2val:-0x1; immval:0x1d8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 6*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f25,0x1d8,12*SIGALIGN,c.fsdsp,0,x5,x4,6*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_7) + +inst_7:// rs2==f24, imm_val == 440, +// opcode: c.fsdsp; op1:x2; op2:f24; op2val:-0x1; immval:0x1b8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 7*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f24,0x1b8,14*SIGALIGN,c.fsdsp,0,x5,x4,7*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_8) + +inst_8:// rs2==f23, imm_val == 376, +// opcode: c.fsdsp; op1:x2; op2:f23; op2val:-0x1; immval:0x178; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 8*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f23,0x178,16*SIGALIGN,c.fsdsp,0,x5,x4,8*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_9) + +inst_9:// rs2==f22, imm_val == 248, +// opcode: c.fsdsp; op1:x2; op2:f22; op2val:-0x1; immval:0xf8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 9*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f22,0xf8,18*SIGALIGN,c.fsdsp,0,x5,x4,9*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_10) + +inst_10:// rs2==f21, imm_val == 8, +// opcode: c.fsdsp; op1:x2; op2:f21; op2val:-0x1; immval:0x8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 10*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f21,0x8,20*SIGALIGN,c.fsdsp,0,x5,x4,10*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_11) + +inst_11:// rs2==f20, imm_val == 16, +// opcode: c.fsdsp; op1:x2; op2:f20; op2val:-0x1; immval:0x10; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 11*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f20,0x10,22*SIGALIGN,c.fsdsp,0,x5,x4,11*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_12) + +inst_12:// rs2==f19, imm_val == 32, +// opcode: c.fsdsp; op1:x2; op2:f19; op2val:-0x1; immval:0x20; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 12*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f19,0x20,24*SIGALIGN,c.fsdsp,0,x5,x4,12*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_13) + +inst_13:// rs2==f18, imm_val == 64, +// opcode: c.fsdsp; op1:x2; op2:f18; op2val:-0x1; immval:0x40; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 13*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f18,0x40,26*SIGALIGN,c.fsdsp,0,x5,x4,13*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_14) + +inst_14:// rs2==f17, imm_val == 128, +// opcode: c.fsdsp; op1:x2; op2:f17; op2val:-0x1; immval:0x80; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 14*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f17,0x80,28*SIGALIGN,c.fsdsp,0,x5,x4,14*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_15) + +inst_15:// rs2==f16, imm_val == 256, +// opcode: c.fsdsp; op1:x2; op2:f16; op2val:-0x1; immval:0x100; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 15*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f16,0x100,30*SIGALIGN,c.fsdsp,0,x5,x4,15*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_16) + +inst_16:// rs2==f15, +// opcode: c.fsdsp; op1:x2; op2:f15; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 16*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f15,0x0,32*SIGALIGN,c.fsdsp,0,x5,x4,16*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_17) + +inst_17:// rs2==f14, +// opcode: c.fsdsp; op1:x2; op2:f14; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 17*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f14,0x0,34*SIGALIGN,c.fsdsp,0,x5,x4,17*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_18) + +inst_18:// rs2==f13, +// opcode: c.fsdsp; op1:x2; op2:f13; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 18*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f13,0x0,36*SIGALIGN,c.fsdsp,0,x5,x4,18*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_19) + +inst_19:// rs2==f12, +// opcode: c.fsdsp; op1:x2; op2:f12; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 19*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f12,0x0,38*SIGALIGN,c.fsdsp,0,x5,x4,19*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_20) + +inst_20:// rs2==f11, +// opcode: c.fsdsp; op1:x2; op2:f11; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 20*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f11,0x0,40*SIGALIGN,c.fsdsp,0,x5,x4,20*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_21) + +inst_21:// rs2==f10, +// opcode: c.fsdsp; op1:x2; op2:f10; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 21*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f10,0x0,42*SIGALIGN,c.fsdsp,0,x5,x4,21*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_22) + +inst_22:// rs2==f9, +// opcode: c.fsdsp; op1:x2; op2:f9; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 22*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f9,0x0,44*SIGALIGN,c.fsdsp,0,x5,x4,22*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_23) + +inst_23:// rs2==f8, +// opcode: c.fsdsp; op1:x2; op2:f8; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 23*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f8,0x0,46*SIGALIGN,c.fsdsp,0,x5,x4,23*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_24) + +inst_24:// rs2==f7, +// opcode: c.fsdsp; op1:x2; op2:f7; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 24*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f7,0x0,48*SIGALIGN,c.fsdsp,0,x5,x4,24*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_25) + +inst_25:// rs2==f6, +// opcode: c.fsdsp; op1:x2; op2:f6; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 25*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f6,0x0,50*SIGALIGN,c.fsdsp,0,x5,x4,25*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_26) + +inst_26:// rs2==f5, +// opcode: c.fsdsp; op1:x2; op2:f5; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 26*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f5,0x0,52*SIGALIGN,c.fsdsp,0,x5,x4,26*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_27) + +inst_27:// rs2==f4, +// opcode: c.fsdsp; op1:x2; op2:f4; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 27*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f4,0x0,54*SIGALIGN,c.fsdsp,0,x5,x4,27*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_28) + +inst_28:// rs2==f3, +// opcode: c.fsdsp; op1:x2; op2:f3; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 28*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f3,0x0,56*SIGALIGN,c.fsdsp,0,x5,x4,28*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_29) + +inst_29:// rs2==f2, +// opcode: c.fsdsp; op1:x2; op2:f2; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 29*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f2,0x0,58*SIGALIGN,c.fsdsp,0,x5,x4,29*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_30) + +inst_30:// rs2==f1, +// opcode: c.fsdsp; op1:x2; op2:f1; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 30*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f1,0x0,60*SIGALIGN,c.fsdsp,0,x5,x4,30*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_31) + +inst_31:// rs2==f0, +// opcode: c.fsdsp; op1:x2; op2:f0; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 31*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f0,0x0,62*SIGALIGN,c.fsdsp,0,x5,x4,31*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + +test_dataset_1: + +test_dataset_2: + +test_dataset_3: + +test_dataset_4: + +test_dataset_5: + +test_dataset_6: + +test_dataset_7: + +test_dataset_8: + +test_dataset_9: + +test_dataset_10: + +test_dataset_11: + +test_dataset_12: + +test_dataset_13: + +test_dataset_14: + +test_dataset_15: + +test_dataset_16: + +test_dataset_17: + +test_dataset_18: + +test_dataset_19: + +test_dataset_20: + +test_dataset_21: + +test_dataset_22: + +test_dataset_23: + +test_dataset_24: + +test_dataset_25: + +test_dataset_26: + +test_dataset_27: + +test_dataset_28: + +test_dataset_29: + +test_dataset_30: + +test_dataset_31: + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END From 0181eb19c09fd6b0880672fdae530731caa32430 Mon Sep 17 00:00:00 2001 From: Pagerd <60070497+Pagerd@users.noreply.github.com> Date: Tue, 31 Dec 2024 17:27:17 +0800 Subject: [PATCH 03/10] add missing zfh testcases (#572) Co-authored-by: Umer Shahid --- .../rv32i_m/Zfh/src/fcvt.d.h_b1-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.d.h_b22-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.d.h_b23-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.d.h_b24-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.d.h_b27-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.d.h_b28-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.d.h_b29-01.S | 729 ++++++++++++++ .../rv32i_m/Zfh/src/fcvt.h.d_b1-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.h.d_b22-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.h.d_b23-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.h.d_b24-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.h.d_b27-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.h.d_b28-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.h.d_b29-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.h.s_b1-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.h.s_b22-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.h.s_b23-01.S | 449 +++++++++ .../rv32i_m/Zfh/src/fcvt.h.s_b24-01.S | 929 ++++++++++++++++++ .../rv32i_m/Zfh/src/fcvt.h.s_b27-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.h.s_b28-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.h.s_b29-01.S | 729 ++++++++++++++ .../rv32i_m/Zfh/src/fcvt.s.h_b22-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.s.h_b23-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.s.h_b24-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.s.h_b27-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.s.h_b28-01.S | 353 +++++++ .../rv32i_m/Zfh/src/fcvt.s.h_b29-01.S | 353 +++++++ 27 files changed, 10955 insertions(+) create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b22-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b23-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b24-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b27-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b28-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b29-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b22-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b23-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b24-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b27-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b28-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b29-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b22-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b23-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b24-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b27-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b28-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b29-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b22-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b23-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b24-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b27-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b28-01.S create mode 100644 riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b29-01.S diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b1-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b1-01.S new file mode 100644 index 000000000..713b9aa20 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b1-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x8000; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0x8001; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x83fe; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x3ff; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0x83ff; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x400; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x8400; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x401; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x8455; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x7bff; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0xfbff; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x7c00; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0xfc00; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0x7e00; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0xfe00; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0x7e01; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0xfe55; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0x7c01; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0xfd55; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x3c00; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0xbc00; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b22-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b22-01.S new file mode 100644 index 000000000..5b5acfff5 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b22-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x3249; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x35b7; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x3a4f; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0x3cd3; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x4340; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x474b; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x07 and fm1 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x9e9d; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x04 and fm1 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0x1023; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(13751,16,FLEN) +NAN_BOXED(14927,16,FLEN) +NAN_BOXED(15571,16,FLEN) +NAN_BOXED(17216,16,FLEN) +NAN_BOXED(18251,16,FLEN) +NAN_BOXED(40605,16,FLEN) +NAN_BOXED(4131,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b23-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b23-01.S new file mode 100644 index 000000000..452d29d44 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b23-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x77fc; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x77fd; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x77fe; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0x77ff; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x7800; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x7801; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x7802; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0x7803; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x7804; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b24-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b24-01.S new file mode 100644 index 000000000..255b71662 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b24-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0xbc0a; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x3c00; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0xa11e; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0xbb33; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0xf0; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x2f0a; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x3c70; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0xbc66; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0xae66; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x3b1e; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x3beb; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x3b33; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0xbc00; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0xbc70; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x211e; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x2e66; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0xaf0a; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x3c66; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0xbbeb; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x3c0a; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0xbb1e; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15339,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b27-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b27-01.S new file mode 100644 index 000000000..46a91fefb --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b27-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x7c01; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0xfc01; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x7d55; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0xfd55; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x7e01; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0xfe01; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x7e55; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0xfe55; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64513,16,FLEN) +NAN_BOXED(32085,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65025,16,FLEN) +NAN_BOXED(32341,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b28-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b28-01.S new file mode 100644 index 000000000..a59b503d8 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b28-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x3892; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x3c00; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0x3d00; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x3e00; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x3f00; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x4000; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0x4080; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x4100; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x4180; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x72dc; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x77ff; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x7c00; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0x7c01; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x7e01; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x8000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x0d and fm1 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0xb6c0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0xbc00; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0xc180; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0xc100; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0xc080; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0xc000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0xbf00; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0xbe00; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0xbd00; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0xf659; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0xf800; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0xfc00; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(14482,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15616,16,FLEN) +NAN_BOXED(15872,16,FLEN) +NAN_BOXED(16128,16,FLEN) +NAN_BOXED(16384,16,FLEN) +NAN_BOXED(16512,16,FLEN) +NAN_BOXED(16640,16,FLEN) +NAN_BOXED(16768,16,FLEN) +NAN_BOXED(29404,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(46784,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49536,16,FLEN) +NAN_BOXED(49408,16,FLEN) +NAN_BOXED(49280,16,FLEN) +NAN_BOXED(49152,16,FLEN) +NAN_BOXED(48896,16,FLEN) +NAN_BOXED(48640,16,FLEN) +NAN_BOXED(48384,16,FLEN) +NAN_BOXED(63065,16,FLEN) +NAN_BOXED(63488,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b29-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b29-01.S new file mode 100644 index 000000000..ed6f6e448 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b29-01.S @@ -0,0 +1,729 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x3248; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x3248; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x3248; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0x3248; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x3248; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x3249; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x3249; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0x3249; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x3249; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x3249; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x324a; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x324a; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x324a; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0x324a; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x324a; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x324b; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0x324b; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x324b; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0x324b; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x324b; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0x324c; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x324c; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x324c; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x324c; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x324c; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x324d; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x324d; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x324d; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x324d; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x324d; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x324e; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x324e; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x324e; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324e; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324e; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324f; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324f; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324f; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324f; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324f; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb248; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb248; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb248; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb248; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb248; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb249; valaddr_reg:x3; +val_offset:45*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb249; valaddr_reg:x3; +val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb249; valaddr_reg:x3; +val_offset:47*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 47*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb249; valaddr_reg:x3; +val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb249; valaddr_reg:x3; +val_offset:49*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 49*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24a; valaddr_reg:x3; +val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24a; valaddr_reg:x3; +val_offset:51*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24a; valaddr_reg:x3; +val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24a; valaddr_reg:x3; +val_offset:53*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 53*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24a; valaddr_reg:x3; +val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24b; valaddr_reg:x3; +val_offset:55*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 55*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24b; valaddr_reg:x3; +val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24b; valaddr_reg:x3; +val_offset:57*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24b; valaddr_reg:x3; +val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24b; valaddr_reg:x3; +val_offset:59*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 59*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24c; valaddr_reg:x3; +val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24c; valaddr_reg:x3; +val_offset:61*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 61*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24c; valaddr_reg:x3; +val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24c; valaddr_reg:x3; +val_offset:63*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24c; valaddr_reg:x3; +val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24d; valaddr_reg:x3; +val_offset:65*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 65*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24d; valaddr_reg:x3; +val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24d; valaddr_reg:x3; +val_offset:67*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 67*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24d; valaddr_reg:x3; +val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24d; valaddr_reg:x3; +val_offset:69*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24e; valaddr_reg:x3; +val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24e; valaddr_reg:x3; +val_offset:71*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 71*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24e; valaddr_reg:x3; +val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24e; valaddr_reg:x3; +val_offset:73*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 73*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24e; valaddr_reg:x3; +val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24f; valaddr_reg:x3; +val_offset:75*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24f; valaddr_reg:x3; +val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24f; valaddr_reg:x3; +val_offset:77*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 77*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24f; valaddr_reg:x3; +val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24f; valaddr_reg:x3; +val_offset:79*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 79*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 160*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b1-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b1-01.S new file mode 100644 index 000000000..68dba6c97 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b1-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x80000000; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x1; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x80000002; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0xfffffffffffff; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x100fffffffffffff; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x800002; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x80800002; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x7fefffffffffffff; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0xffefffffffffffff; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x7ff800000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x7ff8000000000000; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0xfff8000000000000; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x7ff8000000000001; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0xfff8000000000001; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x3ff800001; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x7ff800001; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x1ff800000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x3fc000000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 0; +.dword 2147483648; +.dword 1; +.dword 2147483649; +.dword 2; +.dword 2147483650; +.dword 4503599627370495; +.dword 1157425104234217471; +.dword 8388608; +.dword 2155872256; +.dword 8388610; +.dword 2155872258; +.dword 9218868437227405311; +.dword 18442240474082181119; +.dword 17171480576; +.dword 34351349760; +.dword 9221120237041090560; +.dword 18444492273895866368; +.dword 9221120237041090561; +.dword 18444492273895866369; +.dword 17171480577; +.dword 34351349761; +.dword 8581545984; +.dword 17112760320; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b22-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b22-01.S new file mode 100644 index 000000000..d93c18ef6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b22-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08577924770d3 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x3fc8577924770d3; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x3fd and fm1 == 0x93fdc7b89296c and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x3fd93fdc7b89296c; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 1 and fe1 == 0x3fe and fm1 == 0x766ba34c2da80 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x3ff766ba34c2da80; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xd2d6b7dc59a3a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x3ffd2d6b7dc59a3a; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x400 and fm1 == 0xcf84ba749f9c5 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x400cf84ba749f9c5; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x401 and fm1 == 0x854a908ceac39 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x401854a908ceac39; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x0ff and fm1 == 0x137a953e8eb43 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x3ff37a953e8eb43; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xbedc2f3ebcf12 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x7febedc2f3ebcf12; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 287251224846627027; +.dword 4600778710533613932; +.dword 4609265693572127360; +.dword 4610891533192108602; +.dword 4615336721960794565; +.dword 4618534502842412089; +.dword 288010101571775299; +.dword 9217722483915607826; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b23-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b23-01.S new file mode 100644 index 000000000..5fc00bbce --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b23-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x43dffffffffffffc; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x43dffffffffffffc; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x43dffffffffffffc; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x43dffffffffffffc; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x43dffffffffffffc; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x43dffffffffffffd; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x43dffffffffffffd; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x43dffffffffffffd; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x43dffffffffffffd; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x43dffffffffffffd; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x43dffffffffffffe; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x43dffffffffffffe; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x43dffffffffffffe; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0x43dffffffffffffe; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x43dffffffffffffe; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x43dfffffffffffff; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x43dfffffffffffff; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x43dfffffffffffff; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x43dfffffffffffff; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x43dfffffffffffff; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x21f000000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x21f000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x21f000000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x21f000000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x21f000000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x21f000001; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x21f000001; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x21f000001; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x21f000001; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x21f000001; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x21f000002; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x21f000002; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x21f000002; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 4890909195324358652; +.dword 4890909195324358652; +.dword 4890909195324358652; +.dword 4890909195324358652; +.dword 4890909195324358652; +.dword 4890909195324358653; +.dword 4890909195324358653; +.dword 4890909195324358653; +.dword 4890909195324358653; +.dword 4890909195324358653; +.dword 4890909195324358654; +.dword 4890909195324358654; +.dword 4890909195324358654; +.dword 4890909195324358654; +.dword 4890909195324358654; +.dword 4890909195324358655; +.dword 4890909195324358655; +.dword 4890909195324358655; +.dword 4890909195324358655; +.dword 4890909195324358655; +.dword 9110028288; +.dword 9110028288; +.dword 9110028288; +.dword 9110028288; +.dword 9110028288; +.dword 9110028289; +.dword 9110028289; +.dword 9110028289; +.dword 9110028289; +.dword 9110028289; +.dword 9110028290; +.dword 9110028290; +.dword 9110028290; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b24-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b24-01.S new file mode 100644 index 000000000..586d5b71a --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b24-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x7fec7ae147ae147b; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x7fec7ae147ae147b; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x7fec7ae147ae147b; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x7fec7ae147ae147b; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x7fec7ae147ae147b; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x7fb999999999999a; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x7fb999999999999a; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x7fb999999999999a; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x7fb999999999999a; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x7fb999999999999a; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0xffe8f5c28f5c29; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0xffe8f5c28f5c29; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0xffe8f5c28f5c29; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0xffe8f5c28f5c29; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0xffe8f5c28f5c29; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x1fc47ae147ae147b; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x1fc47ae147ae147b; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x1fc47ae147ae147b; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x1fc47ae147ae147b; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x1fc47ae147ae147b; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x1ff800000; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x1ff800000; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x1ff800000; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 9217877645309383803; +.dword 9217877645309383803; +.dword 9217877645309383803; +.dword 9217877645309383803; +.dword 9217877645309383803; +.dword 9203556198494345626; +.dword 9203556198494345626; +.dword 9203556198494345626; +.dword 9203556198494345626; +.dword 9203556198494345626; +.dword 72032261290023977; +.dword 72032261290023977; +.dword 72032261290023977; +.dword 72032261290023977; +.dword 72032261290023977; +.dword 2289089618599875707; +.dword 2289089618599875707; +.dword 2289089618599875707; +.dword 2289089618599875707; +.dword 2289089618599875707; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 17171480576; +.dword 17171480576; +.dword 17171480576; +.dword 17171480576; +.dword 17171480576; +.dword 8581545984; +.dword 8581545984; +.dword 8581545984; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b27-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b27-01.S new file mode 100644 index 000000000..6fb9ee31c --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b27-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x3ff800001; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x7ff800001; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x3ffcaaaaaaaaaaaa; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x7ffcaaaaaaaaaaaa; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x7ff8000000000001; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0xfff8000000000001; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x7ffc000000000001; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0xfffc000000000001; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 17171480577; +.dword 34351349761; +.dword 4610747768505019050; +.dword 9222433786932406954; +.dword 9221120237041090561; +.dword 18444492273895866369; +.dword 9222246136947933185; +.dword 18445618173802708993; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b28-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b28-01.S new file mode 100644 index 000000000..b79caf4c1 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b28-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x3fe and fm1 == 0x248ee18215dfa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0xffa48ee18215dfa; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x1ff800000; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x1ffc000000000000; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x3ff8000000000000; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x3ffc000000000000; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x200000000; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x1002000000000000; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x2004000000000000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x2006000000000000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x43c and fm1 == 0xb72eb13dc494a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x43cb72eb13dc494a; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x21f000000; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0x3ff800001; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x7ff8000000000001; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x80000000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x3fd and fm1 == 0xb008d57e19f88 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x7fdb008d57e19f88; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x3fc000000; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x6006000000000000; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x6004000000000000; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x3002000000000000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x600000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x7ffc000000000000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x7ff8000000000000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x3ffc000000000000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x43d and fm1 == 0x967a4ae26514c and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0xc3d967a4ae26514c; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x61f000000; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x7ff800000; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 0; +.dword 1151312842190839290; +.dword 8581545984; +.dword 2304717109306851328; +.dword 4609434218613702656; +.dword 4610560118520545280; +.dword 8589934592; +.dword 1153484454560268288; +.dword 2306968909120536576; +.dword 2307531859073957888; +.dword 4885124574789519690; +.dword 9110028288; +.dword 17171480576; +.dword 17171480577; +.dword 9221120237041090561; +.dword 2147483648; +.dword 9212958069781274504; +.dword 17112760320; +.dword 6919217877501345792; +.dword 6918654927547924480; +.dword 3459327463773962240; +.dword 25769803776; +.dword 9222246136947933184; +.dword 9221120237041090560; +.dword 4610560118520545280; +.dword 14112424864336204108; +.dword 26289897472; +.dword 34351349760; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b29-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b29-01.S new file mode 100644 index 000000000..9063584b5 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b29-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x3fc8574923b8698; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x3fc8574923b8698; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x3fc8574923b8698; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x3fc8574923b8698; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x3fc8574923b8698; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x3fc8574923b8699; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x3fc8574923b8699; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x3fc8574923b8699; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x3fc8574923b8699; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x3fc8574923b8699; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x3fc8574923b869a; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x3fc8574923b869a; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x3fc8574923b869a; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0x3fc8574923b869a; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x3fc8574923b869a; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x3fc8574923b869b; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x3fc8574923b869b; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x3fc8574923b869b; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x3fc8574923b869b; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x3fc8574923b869b; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x3fc8574923b869c; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x3fc8574923b869c; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x3fc8574923b869c; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x3fc8574923b869c; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x3fc8574923b869c; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x3fc8574923b869d; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x3fc8574923b869d; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x3fc8574923b869d; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x3fc8574923b869d; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x3fc8574923b869d; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x3fc8574923b869e; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x3fc8574923b869e; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x3fc8574923b869e; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 287251211960944280; +.dword 287251211960944280; +.dword 287251211960944280; +.dword 287251211960944280; +.dword 287251211960944280; +.dword 287251211960944281; +.dword 287251211960944281; +.dword 287251211960944281; +.dword 287251211960944281; +.dword 287251211960944281; +.dword 287251211960944282; +.dword 287251211960944282; +.dword 287251211960944282; +.dword 287251211960944282; +.dword 287251211960944282; +.dword 287251211960944283; +.dword 287251211960944283; +.dword 287251211960944283; +.dword 287251211960944283; +.dword 287251211960944283; +.dword 287251211960944284; +.dword 287251211960944284; +.dword 287251211960944284; +.dword 287251211960944284; +.dword 287251211960944284; +.dword 287251211960944285; +.dword 287251211960944285; +.dword 287251211960944285; +.dword 287251211960944285; +.dword 287251211960944285; +.dword 287251211960944286; +.dword 287251211960944286; +.dword 287251211960944286; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b1-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b1-01.S new file mode 100644 index 000000000..49363d961 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b1-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x80000000; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0x807ffffe; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x7fffff; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0x807fffff; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x800001; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x80855555; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x7f7fffff; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0xff7fffff; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x7f800000; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0xff800000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0x7fc00000; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0xffc00000; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0xffc55555; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x7f800001; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x3f800000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0xbf800000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(2147483649,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(2155872254,32,FLEN) +NAN_BOXED(8388607,32,FLEN) +NAN_BOXED(2155872255,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(2155872256,32,FLEN) +NAN_BOXED(8388609,32,FLEN) +NAN_BOXED(2156221781,32,FLEN) +NAN_BOXED(2139095039,32,FLEN) +NAN_BOXED(4286578687,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(2143289344,32,FLEN) +NAN_BOXED(4290772992,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b22-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b22-01.S new file mode 100644 index 000000000..6d37c239d --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b22-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x7d and fm1 == 0x36e5d6 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x3eb6e5d6; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x7e and fm1 == 0x49fee5 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x3f49fee5; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x7f and fm1 == 0x1a616d and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x3f9a616d; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x80 and fm1 == 0x681ae9 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x40681ae9; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x81 and fm1 == 0x696b5c and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0x40e96b5c; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x67 and fm1 == 0x53a4fc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x33d3a4fc; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0xc4 and fm1 == 0x046756 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0x62046756; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1052173782,32,FLEN) +NAN_BOXED(1061813989,32,FLEN) +NAN_BOXED(1067082093,32,FLEN) +NAN_BOXED(1080564457,32,FLEN) +NAN_BOXED(1089039196,32,FLEN) +NAN_BOXED(869508348,32,FLEN) +NAN_BOXED(1644455766,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b23-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b23-01.S new file mode 100644 index 000000000..f68582b2a --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b23-01.S @@ -0,0 +1,449 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0x4effffff; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0x4effffff; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0x4effffff; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0x4effffff; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0x4effffff; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x4f000000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0x4f000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x4f000000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0x4f000000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x4f000000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x4f000001; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x4f000001; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x4f000001; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x4f000001; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x4f000001; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x4f000002; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x4f000002; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x4f000002; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000002; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000002; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 90*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b24-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b24-01.S new file mode 100644 index 000000000..e7da9dea1 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b24-01.S @@ -0,0 +1,929 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x7f0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x7f0; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x7f0; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x7f0; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x7f0; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:45*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:47*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 47*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:49*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 49*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:51*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:53*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 53*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:55*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 55*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:57*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:59*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 59*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f666666; valaddr_reg:x3; +val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f666666; valaddr_reg:x3; +val_offset:61*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 61*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f666666; valaddr_reg:x3; +val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f666666; valaddr_reg:x3; +val_offset:63*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f666666; valaddr_reg:x3; +val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:65*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 65*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:67*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 67*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:69*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:71*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 71*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:73*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 73*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:75*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:77*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 77*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:79*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 79*FLEN/8, x4, x1, x2) + +inst_80: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:80*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 80*FLEN/8, x4, x1, x2) + +inst_81: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:81*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 81*FLEN/8, x4, x1, x2) + +inst_82: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:82*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 82*FLEN/8, x4, x1, x2) + +inst_83: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:83*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 83*FLEN/8, x4, x1, x2) + +inst_84: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:84*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 84*FLEN/8, x4, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:85*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 85*FLEN/8, x4, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:86*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 86*FLEN/8, x4, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:87*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 87*FLEN/8, x4, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:88*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 88*FLEN/8, x4, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:89*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 89*FLEN/8, x4, x1, x2) + +inst_90: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:90*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 90*FLEN/8, x4, x1, x2) + +inst_91: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:91*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 91*FLEN/8, x4, x1, x2) + +inst_92: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:92*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 92*FLEN/8, x4, x1, x2) + +inst_93: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:93*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 93*FLEN/8, x4, x1, x2) + +inst_94: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:94*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 94*FLEN/8, x4, x1, x2) + +inst_95: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:95*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 95*FLEN/8, x4, x1, x2) + +inst_96: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:96*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 96*FLEN/8, x4, x1, x2) + +inst_97: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:97*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 97*FLEN/8, x4, x1, x2) + +inst_98: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:98*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 98*FLEN/8, x4, x1, x2) + +inst_99: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:99*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 99*FLEN/8, x4, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:100*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 100*FLEN/8, x4, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:101*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 101*FLEN/8, x4, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:102*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 102*FLEN/8, x4, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:103*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 103*FLEN/8, x4, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:104*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 104*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 210*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b27-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b27-01.S new file mode 100644 index 000000000..7f6174289 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b27-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x7f800001; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0xff800001; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x7faaaaaa; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0xffc00001; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x7fc55555; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0xffc55555; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(4286578689,32,FLEN) +NAN_BOXED(2141891242,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(4290772993,32,FLEN) +NAN_BOXED(2143638869,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b28-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b28-01.S new file mode 100644 index 000000000..4c5592ee2 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b28-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x7e and fm1 == 0x124770 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x3f124770; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x3f800000; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x7f and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x3fa00000; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x7f and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x3fc00000; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x7f and fm1 == 0x600000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0x3fe00000; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x80 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x40000000; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x80 and fm1 == 0x100000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0x40100000; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x80 and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x40200000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x80 and fm1 == 0x300000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x40300000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x9c and fm1 == 0x5b9758 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x4e5b9758; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x4effffff; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x7f800000; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x7f800001; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0x80000000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x7d and fm1 == 0x58046a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0xbed8046a; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0xbf800000; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x80 and fm1 == 0x300000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0xc0300000; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x80 and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0xc0200000; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x80 and fm1 == 0x100000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0xc0100000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x80 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0xc0000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x7f and fm1 == 0x600000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0xbfe00000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0xbfc00000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x7f and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0xbfa00000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x9d and fm1 == 0x4b3d25 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0xcecb3d25; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0xcf000000; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0xff800000; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1058162544,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1067450368,32,FLEN) +NAN_BOXED(1069547520,32,FLEN) +NAN_BOXED(1071644672,32,FLEN) +NAN_BOXED(1073741824,32,FLEN) +NAN_BOXED(1074790400,32,FLEN) +NAN_BOXED(1075838976,32,FLEN) +NAN_BOXED(1076887552,32,FLEN) +NAN_BOXED(1314625368,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(3201827946,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3224371200,32,FLEN) +NAN_BOXED(3223322624,32,FLEN) +NAN_BOXED(3222274048,32,FLEN) +NAN_BOXED(3221225472,32,FLEN) +NAN_BOXED(3219128320,32,FLEN) +NAN_BOXED(3217031168,32,FLEN) +NAN_BOXED(3214934016,32,FLEN) +NAN_BOXED(3469425957,32,FLEN) +NAN_BOXED(3472883712,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b29-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b29-01.S new file mode 100644 index 000000000..adfa2f8b2 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b29-01.S @@ -0,0 +1,729 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:45*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:47*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 47*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:49*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 49*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:51*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:53*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 53*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:55*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 55*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:57*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:59*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 59*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:61*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 61*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:63*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:65*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 65*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:67*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 67*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:69*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:71*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 71*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:73*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 73*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:75*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:77*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 77*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:79*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 79*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 160*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b22-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b22-01.S new file mode 100644 index 000000000..8dfc6a638 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b22-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x3249; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0x35b7; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x3a4f; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0x3cd3; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x4340; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0x474b; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x07 and fm1 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0x9e9d; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x04 and fm1 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0x1023; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(13751,16,FLEN) +NAN_BOXED(14927,16,FLEN) +NAN_BOXED(15571,16,FLEN) +NAN_BOXED(17216,16,FLEN) +NAN_BOXED(18251,16,FLEN) +NAN_BOXED(40605,16,FLEN) +NAN_BOXED(4131,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b23-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b23-01.S new file mode 100644 index 000000000..50b7de7b4 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b23-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x77fc; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0x77fc; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x77fc; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0x77fc; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x77fc; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0x77fd; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0x77fd; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0x77fd; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0x77fd; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0x77fd; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x77fe; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x77fe; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x77fe; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x77fe; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x77fe; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0x77ff; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0x77ff; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0x77ff; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0x77ff; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0x77ff; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0x7800; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0x7800; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0x7800; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0x7800; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0x7800; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0x7801; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0x7801; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0x7801; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0x7801; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0x7801; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0x7802; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0x7802; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0x7802; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b24-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b24-01.S new file mode 100644 index 000000000..d11e5d2cf --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b24-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x2e66; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0x2e66; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x2e66; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0x2e66; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x2e66; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0xbc66; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0xbc66; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0xbc66; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0xbc66; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0xbc66; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x3c66; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x3c66; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x3c66; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x3c66; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x3c66; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0xbbeb; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0xbbeb; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0xbbeb; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0xbbeb; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0xbbeb; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0xaf0a; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0xaf0a; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0xaf0a; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0xaf0a; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0xaf0a; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0xf0; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0xf0; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0xf0; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0xf0; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0xf0; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0xa11e; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0xa11e; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0xa11e; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b27-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b27-01.S new file mode 100644 index 000000000..55fd97f01 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b27-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x7c01; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0xfc01; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x7d55; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0xfd55; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x7e01; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0xfe01; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0x7e55; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0xfe55; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64513,16,FLEN) +NAN_BOXED(32085,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65025,16,FLEN) +NAN_BOXED(32341,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b28-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b28-01.S new file mode 100644 index 000000000..a22413aaf --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b28-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0x3892; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x3c00; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0x3d00; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x3e00; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0x3f00; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0x4000; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0x4080; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0x4100; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0x4180; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x72dc; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x77ff; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x7c00; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x7c01; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x7e01; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0x8000; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x0d and fm1 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0xb6c0; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0xbc00; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0xc180; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0xc100; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0xc080; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0xc000; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0xbf00; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0xbe00; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0xbd00; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0xf659; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0xf800; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0xfc00; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(14482,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15616,16,FLEN) +NAN_BOXED(15872,16,FLEN) +NAN_BOXED(16128,16,FLEN) +NAN_BOXED(16384,16,FLEN) +NAN_BOXED(16512,16,FLEN) +NAN_BOXED(16640,16,FLEN) +NAN_BOXED(16768,16,FLEN) +NAN_BOXED(29404,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(46784,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49536,16,FLEN) +NAN_BOXED(49408,16,FLEN) +NAN_BOXED(49280,16,FLEN) +NAN_BOXED(49152,16,FLEN) +NAN_BOXED(48896,16,FLEN) +NAN_BOXED(48640,16,FLEN) +NAN_BOXED(48384,16,FLEN) +NAN_BOXED(63065,16,FLEN) +NAN_BOXED(63488,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b29-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b29-01.S new file mode 100644 index 000000000..18444165b --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b29-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x3248; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0x3248; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x3248; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0x3248; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x3248; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0x3249; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0x3249; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0x3249; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0x3249; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0x3249; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x324a; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x324a; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x324a; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x324a; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x324a; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0x324b; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0x324b; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0x324b; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0x324b; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0x324b; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0x324c; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0x324c; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0x324c; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0x324c; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0x324c; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0x324d; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0x324d; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0x324d; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0x324d; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0x324d; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0x324e; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0x324e; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0x324e; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END From 053d888838bee7698244a2ce074605758028fb1b Mon Sep 17 00:00:00 2001 From: Pagerd <60070497+Pagerd@users.noreply.github.com> Date: Tue, 31 Dec 2024 17:35:10 +0800 Subject: [PATCH 04/10] fix fcvt_d_s testcases (#581) Co-authored-by: Umer Shahid --- .../rv32i_m/D/src/fcvt.d.s_b1-01.S | 66 ++++----- .../rv32i_m/D/src/fcvt.d.s_b22-01.S | 66 ++++----- .../rv32i_m/D/src/fcvt.d.s_b23-01.S | 78 +++++----- .../rv32i_m/D/src/fcvt.d.s_b24-01.S | 138 +++++++++++++----- .../rv32i_m/D/src/fcvt.d.s_b27-01.S | 66 ++++----- .../rv32i_m/D/src/fcvt.d.s_b28-01.S | 66 ++++----- .../rv32i_m/D/src/fcvt.d.s_b29-01.S | 113 +++++++++----- 7 files changed, 362 insertions(+), 231 deletions(-) diff --git a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b1-01.S b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b1-01.S index cab307857..1e1fee401 100644 --- a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b1-01.S +++ b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b1-01.S @@ -279,39 +279,39 @@ rvtest_data: .word 0xbecafeba .word 0xecafebab test_dataset_0: -NAN_BOXED(0,64,FLEN) -NAN_BOXED(1,64,FLEN) -NAN_BOXED(2,64,FLEN) -NAN_BOXED(8388607,64,FLEN) -NAN_BOXED(4503599627370496,64,FLEN) -NAN_BOXED(4503599627370497,64,FLEN) -NAN_BOXED(571957152676052992,64,FLEN) -NAN_BOXED(1143914305360494591,64,FLEN) -NAN_BOXED(1148417904979476480,64,FLEN) -NAN_BOXED(1148417904979476481,64,FLEN) -NAN_BOXED(1148417904983670784,64,FLEN) -NAN_BOXED(1148417904983670785,64,FLEN) -NAN_BOXED(9223372036854775808,64,FLEN) -NAN_BOXED(9223372036854775809,64,FLEN) -NAN_BOXED(9223372036863164414,64,FLEN) -NAN_BOXED(9223372036863164415,64,FLEN) -NAN_BOXED(9227875636482146304,64,FLEN) -NAN_BOXED(9227875636482495829,64,FLEN) -NAN_BOXED(9795329189530828800,64,FLEN) -NAN_BOXED(10367286342215270399,64,FLEN) -NAN_BOXED(10371789941834252288,64,FLEN) -NAN_BOXED(10371789941837048490,64,FLEN) -NAN_BOXED(10371789941838446592,64,FLEN) -NAN_BOXED(10371789941838796117,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(2147483649,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(2155872254,32,FLEN) +NAN_BOXED(8388607,32,FLEN) +NAN_BOXED(2155872255,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(2155872256,32,FLEN) +NAN_BOXED(8388609,32,FLEN) +NAN_BOXED(2156221781,32,FLEN) +NAN_BOXED(2139095039,32,FLEN) +NAN_BOXED(4286578687,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(2143289344,32,FLEN) +NAN_BOXED(4290772992,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) RVTEST_DATA_END RVMODEL_DATA_BEGIN diff --git a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b22-01.S b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b22-01.S index c1ae197ee..df5f88761 100644 --- a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b22-01.S +++ b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b22-01.S @@ -279,39 +279,39 @@ rvtest_data: .word 0xbecafeba .word 0xecafebab test_dataset_0: -NAN_BOXED(463870761624642812,64,FLEN) -NAN_BOXED(558446353798734776,64,FLEN) -NAN_BOXED(562949953424909782,64,FLEN) -NAN_BOXED(567453553053531877,64,FLEN) -NAN_BOXED(571957152677781869,64,FLEN) -NAN_BOXED(576460752310246121,64,FLEN) -NAN_BOXED(580964351937702748,64,FLEN) -NAN_BOXED(882705526964905814,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(463870761624642812,64,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1052173782,32,FLEN) +NAN_BOXED(1061813989,32,FLEN) +NAN_BOXED(1067082093,32,FLEN) +NAN_BOXED(1080564457,32,FLEN) +NAN_BOXED(1089039196,32,FLEN) +NAN_BOXED(869508348,32,FLEN) +NAN_BOXED(1644455766,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) RVTEST_DATA_END RVMODEL_DATA_BEGIN diff --git a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b23-01.S b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b23-01.S index 0cb29ad08..c4c413462 100644 --- a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b23-01.S +++ b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b23-01.S @@ -279,39 +279,51 @@ rvtest_data: .word 0xbecafeba .word 0xecafebab test_dataset_0: -NAN_BOXED(707065141505556476,64,FLEN) -NAN_BOXED(707065141505556477,64,FLEN) -NAN_BOXED(707065141505556478,64,FLEN) -NAN_BOXED(707065141505556479,64,FLEN) -NAN_BOXED(711568741124538368,64,FLEN) -NAN_BOXED(711568741124538369,64,FLEN) -NAN_BOXED(711568741124538370,64,FLEN) -NAN_BOXED(711568741124538371,64,FLEN) -NAN_BOXED(711568741124538372,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(707065141505556476,64,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) RVTEST_DATA_END RVMODEL_DATA_BEGIN diff --git a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b24-01.S b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b24-01.S index b7cea7321..69116e5b6 100644 --- a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b24-01.S +++ b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b24-01.S @@ -279,39 +279,111 @@ rvtest_data: .word 0xbecafeba .word 0xecafebab test_dataset_0: -NAN_BOXED(2032,64,FLEN) -NAN_BOXED(540431955286808330,64,FLEN) -NAN_BOXED(553942754171604172,64,FLEN) -NAN_BOXED(553942754172946350,64,FLEN) -NAN_BOXED(567453553055225610,64,FLEN) -NAN_BOXED(567453553055393382,64,FLEN) -NAN_BOXED(567453553056903331,64,FLEN) -NAN_BOXED(571957152676052992,64,FLEN) -NAN_BOXED(571957152676136878,64,FLEN) -NAN_BOXED(571957152676891852,64,FLEN) -NAN_BOXED(571957152676975738,64,FLEN) -NAN_BOXED(9763803992141584138,64,FLEN) -NAN_BOXED(9777314791026379980,64,FLEN) -NAN_BOXED(9777314791027722158,64,FLEN) -NAN_BOXED(9790825589910001418,64,FLEN) -NAN_BOXED(9790825589910169190,64,FLEN) -NAN_BOXED(9790825589911679139,64,FLEN) -NAN_BOXED(9795329189530828800,64,FLEN) -NAN_BOXED(9795329189530912686,64,FLEN) -NAN_BOXED(9795329189531667660,64,FLEN) -NAN_BOXED(9795329189531751546,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(2032,64,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) RVTEST_DATA_END RVMODEL_DATA_BEGIN diff --git a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b27-01.S b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b27-01.S index d7fee7fdb..1b866af06 100644 --- a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b27-01.S +++ b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b27-01.S @@ -279,39 +279,39 @@ rvtest_data: .word 0xbecafeba .word 0xecafebab test_dataset_0: -NAN_BOXED(1148417904979476481,64,FLEN) -NAN_BOXED(1148417904982272682,64,FLEN) -NAN_BOXED(1148417904983670785,64,FLEN) -NAN_BOXED(1148417904984020309,64,FLEN) -NAN_BOXED(10371789941834252289,64,FLEN) -NAN_BOXED(10371789941837048490,64,FLEN) -NAN_BOXED(10371789941838446593,64,FLEN) -NAN_BOXED(10371789941838796117,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(1148417904979476481,64,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(4286578689,32,FLEN) +NAN_BOXED(2141891242,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(4290772993,32,FLEN) +NAN_BOXED(2143638869,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) RVTEST_DATA_END RVMODEL_DATA_BEGIN diff --git a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b28-01.S b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b28-01.S index 43840720f..852662595 100644 --- a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b28-01.S +++ b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b28-01.S @@ -279,39 +279,39 @@ rvtest_data: .word 0xbecafeba .word 0xecafebab test_dataset_0: -NAN_BOXED(0,64,FLEN) -NAN_BOXED(567453553049880432,64,FLEN) -NAN_BOXED(571957152676052992,64,FLEN) -NAN_BOXED(571957152678150144,64,FLEN) -NAN_BOXED(571957152680247296,64,FLEN) -NAN_BOXED(571957152682344448,64,FLEN) -NAN_BOXED(576460752303423488,64,FLEN) -NAN_BOXED(576460752304472064,64,FLEN) -NAN_BOXED(576460752305520640,64,FLEN) -NAN_BOXED(576460752306569216,64,FLEN) -NAN_BOXED(702561541875799896,64,FLEN) -NAN_BOXED(707065141505556479,64,FLEN) -NAN_BOXED(1148417904979476480,64,FLEN) -NAN_BOXED(1148417904979476481,64,FLEN) -NAN_BOXED(1148417904983670785,64,FLEN) -NAN_BOXED(9223372036854775808,64,FLEN) -NAN_BOXED(9786321990281856106,64,FLEN) -NAN_BOXED(9795329189530828800,64,FLEN) -NAN_BOXED(9795329189532925952,64,FLEN) -NAN_BOXED(9795329189535023104,64,FLEN) -NAN_BOXED(9795329189537120256,64,FLEN) -NAN_BOXED(9799832789158199296,64,FLEN) -NAN_BOXED(9799832789159247872,64,FLEN) -NAN_BOXED(9799832789160296448,64,FLEN) -NAN_BOXED(9799832789161345024,64,FLEN) -NAN_BOXED(9930437178356874533,64,FLEN) -NAN_BOXED(9934940777979314176,64,FLEN) -NAN_BOXED(10371789941834252288,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1058162544,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1067450368,32,FLEN) +NAN_BOXED(1069547520,32,FLEN) +NAN_BOXED(1071644672,32,FLEN) +NAN_BOXED(1073741824,32,FLEN) +NAN_BOXED(1074790400,32,FLEN) +NAN_BOXED(1075838976,32,FLEN) +NAN_BOXED(1076887552,32,FLEN) +NAN_BOXED(1314625368,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(3201827946,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3224371200,32,FLEN) +NAN_BOXED(3223322624,32,FLEN) +NAN_BOXED(3222274048,32,FLEN) +NAN_BOXED(3221225472,32,FLEN) +NAN_BOXED(3219128320,32,FLEN) +NAN_BOXED(3217031168,32,FLEN) +NAN_BOXED(3214934016,32,FLEN) +NAN_BOXED(3469425957,32,FLEN) +NAN_BOXED(3472883712,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) RVTEST_DATA_END RVMODEL_DATA_BEGIN diff --git a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b29-01.S b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b29-01.S index 0033b9c5c..dbb13ac32 100644 --- a/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b29-01.S +++ b/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b29-01.S @@ -279,39 +279,86 @@ rvtest_data: .word 0xbecafeba .word 0xecafebab test_dataset_0: -NAN_BOXED(558446353798734776,64,FLEN) -NAN_BOXED(558446353798734777,64,FLEN) -NAN_BOXED(558446353798734778,64,FLEN) -NAN_BOXED(558446353798734779,64,FLEN) -NAN_BOXED(558446353798734780,64,FLEN) -NAN_BOXED(558446353798734781,64,FLEN) -NAN_BOXED(558446353798734782,64,FLEN) -NAN_BOXED(558446353798734783,64,FLEN) -NAN_BOXED(9781818390653510584,64,FLEN) -NAN_BOXED(9781818390653510585,64,FLEN) -NAN_BOXED(9781818390653510586,64,FLEN) -NAN_BOXED(9781818390653510587,64,FLEN) -NAN_BOXED(9781818390653510588,64,FLEN) -NAN_BOXED(9781818390653510589,64,FLEN) -NAN_BOXED(9781818390653510590,64,FLEN) -NAN_BOXED(9781818390653510591,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(0,64,FLEN) -NAN_BOXED(558446353798734776,64,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) RVTEST_DATA_END RVMODEL_DATA_BEGIN From 655fa85b23b506bb34ee873337b132af90478863 Mon Sep 17 00:00:00 2001 From: MingZhu Yan <69898423+trdthg@users.noreply.github.com> Date: Tue, 31 Dec 2024 17:41:22 +0800 Subject: [PATCH 05/10] Set minimum version of python-constraint (#574) python-constraint 1.3.1 can't handle `AllDifferentConstraint()` correctly, this is a bug from upstream that must be fixed by a version upgrade Co-authored-by: Umer Shahid --- requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/requirements.txt b/requirements.txt index 40b8fe2b0..a8cdfd97c 100755 --- a/requirements.txt +++ b/requirements.txt @@ -26,7 +26,7 @@ Pygments>=2.4.2 pyparsing>=2.4.0 pytablewriter pytest -python-constraint +python-constraint>=1.4.0 python-dateutil>=2.8.0 pytz>=2019.1 pyyaml From dea921779dc7c983c35a9941bdf73a14a1f93a00 Mon Sep 17 00:00:00 2001 From: MingZhu Yan <69898423+trdthg@users.noreply.github.com> Date: Tue, 31 Dec 2024 17:47:17 +0800 Subject: [PATCH 06/10] [CTG] Replace set with OrderedSet (#570) - Add new dependency 'ordered-set' - Replace 'set' with 'OrderedSet', riscv-ctg use set to remove duplicates, but this will cause the unstable ordering of the for loop, and finally the generated tests will be different each time. Co-authored-by: Umer Shahid --- requirements.txt | 1 + riscv-ctg/riscv_ctg/constants.py | 4 +- riscv-ctg/riscv_ctg/cross_comb.py | 16 ++++---- riscv-ctg/riscv_ctg/csr_comb.py | 2 +- riscv-ctg/riscv_ctg/generator.py | 40 ++++++++----------- riscv-isac/riscv_isac/coverage.py | 14 +++---- .../riscv_isac/data/rvopcodesdecoder.py | 5 ++- riscv-isac/riscv_isac/fp_dataset.py | 3 +- .../riscv_isac/plugins/internaldecoder.py | 7 ++-- 9 files changed, 45 insertions(+), 47 deletions(-) diff --git a/requirements.txt b/requirements.txt index a8cdfd97c..7565af294 100755 --- a/requirements.txt +++ b/requirements.txt @@ -17,6 +17,7 @@ Jinja2 m2r2>=0.2.7 MarkupSafe>=1.1.1 mistune>=0.8.4 +ordered-set>=4.1.0 oyaml>=0.9 packaging>=19.0 pbr>=5.3.1 diff --git a/riscv-ctg/riscv_ctg/constants.py b/riscv-ctg/riscv_ctg/constants.py index ccf8e4713..5cff5e542 100644 --- a/riscv-ctg/riscv_ctg/constants.py +++ b/riscv-ctg/riscv_ctg/constants.py @@ -3,6 +3,8 @@ import os from math import * from string import Template + +from ordered_set import OrderedSet from riscv_isac.fp_dataset import * root = os.path.abspath(os.path.dirname(__file__)) @@ -120,7 +122,7 @@ def gen_sign_dataset(bit_width): t1 =( '' if bit_width%2 == 0 else '1') + ''.join(['01']*int(bit_width/2)) t2 =( '' if bit_width%2 == 0 else '0') + ''.join(['10']*int(bit_width/2)) data += [twos(t1,bit_width),twos(t2,bit_width)] - return list(set(data)) + return list(OrderedSet(data)) def gen_usign_dataset(bit_width): ''' diff --git a/riscv-ctg/riscv_ctg/cross_comb.py b/riscv-ctg/riscv_ctg/cross_comb.py index e5a69ae77..23336aad3 100644 --- a/riscv-ctg/riscv_ctg/cross_comb.py +++ b/riscv-ctg/riscv_ctg/cross_comb.py @@ -122,7 +122,7 @@ def cross_comb(self, cgf_node): full_solution = [] if 'cross_comb' in cgf_node: - cross_comb = set(cgf_node['cross_comb']) + cross_comb = OrderedSet(cgf_node['cross_comb']) else: return @@ -210,7 +210,7 @@ def eval_conds(*oprs_lst): opr_lst += get_oprs(assgn) # Remove redundant operands - opr_lst = list(set(opr_lst)) + opr_lst = list(OrderedSet(opr_lst)) # Get possible instructions problem.reset() @@ -293,7 +293,7 @@ def exc_rd_zero(*oprs_lst): opr_lst = get_oprs(cond) opr_lst += get_oprs(assgn) - opr_lst = list(set(opr_lst)) + opr_lst = list(OrderedSet(opr_lst)) if data[i] in self.OP_TEMPLATE: # If single instruction instr = data[i] @@ -363,7 +363,7 @@ def exc_rd_zero(*oprs_lst): full_solution += [solution] - self.isa = list(set(isa_set)) + self.isa = list(OrderedSet(isa_set)) return full_solution def swreg(cross_comb_instrs): @@ -381,10 +381,10 @@ def swreg(cross_comb_instrs): if key != 'instr' and key != 'imm_val': op_vals.add(val) - swreg_sol = set(['x'+str(x) for x in range(0,32 if 'e' not in base_isa else 16)]) - op_vals + swreg_sol = OrderedSet(['x'+str(x) for x in range(0,32 if 'e' not in base_isa else 16)]) - op_vals sreg = random.choice(list(swreg_sol)) - freg_Sol = swreg_sol - set(sreg) + freg_Sol = swreg_sol - OrderedSet(sreg) freg = random.choice(list(freg_Sol)) return (sreg, freg) @@ -401,7 +401,7 @@ def get_reginit_str(cross_comb_instrs, freg): - List of initialization strings ''' - reg_init_lst = set() + reg_init_lst = OrderedSet() for instr_dict in cross_comb_instrs: if 'rd' in instr_dict: @@ -455,7 +455,7 @@ def write_test(self, fprefix, cgf_node, usage_str, cov_label, full_solution): sig_label = "signature_" + sreg + "_" + str(sreg_dict[sreg]) code = code + "\nRVTEST_SIGBASE(" + sreg + ", "+ sig_label + ")\n\n" - rd_lst = set() + rd_lst = OrderedSet() # Generate instruction corresponding to each instruction dictionary # Append signature update statements to store rd value after each instruction code += '// Cross-combination test sequence\n' diff --git a/riscv-ctg/riscv_ctg/csr_comb.py b/riscv-ctg/riscv_ctg/csr_comb.py index ef75d388c..0a6f6c486 100644 --- a/riscv-ctg/riscv_ctg/csr_comb.py +++ b/riscv-ctg/riscv_ctg/csr_comb.py @@ -267,7 +267,7 @@ def __init__(self, base_isa, xlen, randomize): def csr_comb(self, cgf_node): logger.debug('Generating tests for csr_comb') if 'csr_comb' in cgf_node: - csr_comb = set(cgf_node['csr_comb']) + csr_comb = OrderedSet(cgf_node['csr_comb']) else: return diff --git a/riscv-ctg/riscv_ctg/generator.py b/riscv-ctg/riscv_ctg/generator.py index 31e7bd525..0f1066700 100644 --- a/riscv-ctg/riscv_ctg/generator.py +++ b/riscv-ctg/riscv_ctg/generator.py @@ -340,25 +340,17 @@ def opcomb(self, cgf): solutions = [] op_conds = {} opcomb_value = cgf.get("op_comb") - if "op_comb" in cgf: - op_comb = set(cgf["op_comb"]) - else: - op_comb = set([]) + op_comb = OrderedSet(opcomb_value or []) for op in self.op_vars: - if op in cgf: - op_conds[op] = set(cgf[op]) - else: - op_conds[op] = set([]) + op_conds[op] = OrderedSet(cgf.get(op, [])) individual = False nodiff = False construct_constraint = lambda val: (lambda x: bool(x in val)) while any([len(op_conds[x])!=0 for x in op_conds]+[len(op_comb)!=0]): cond_str = '' cond_vars = [] - if self.random: - problem = Problem(MinConflictsSolver()) - else: - problem = Problem() + solver = MinConflictsSolver() if self.random else None + problem = Problem(solver) done = False for var in self.op_vars: @@ -418,7 +410,7 @@ def eval_func(cond): for var,val in zip(self.op_vars,op_tuple): locals()[var] = val return eval(cond) - sat_set = set(filter(eval_func,op_comb)) + sat_set = OrderedSet(filter(eval_func,op_comb)) cond_str += ", ".join([var+"=="+solution[var] for var in cond_vars]+list(sat_set)) op_tuple.append(cond_str) problem.reset() @@ -450,7 +442,7 @@ def valcomb(self, cgf): val_comb = [] conds = list(cgf['val_comb'].keys()) - inds = set(range(len(conds))) + inds = OrderedSet(range(len(conds))) merge = True if 'fcvt' in self.opcode or 'fmv' in self.opcode: if self.opcode.split(".")[-1] in ['x','w','wu','l','lu']: @@ -479,7 +471,7 @@ def valcomb(self, cgf): else: logger.error("Invalid Coverpoint: More than one value of "+ i +" found!") sys.exit(1) - if(set(d.keys()) != set(self.val_vars)): + if(OrderedSet(d.keys()) != OrderedSet(self.val_vars)): logger.warning( "Valcomb skip: Cannot bypass SAT Solver for partially defined coverpoints!"\ + str(req_val_comb)) @@ -525,7 +517,7 @@ def eval_func(cond): for var,val in zip(self.val_vars,val_tuple): locals()[var] = val return eval(cond) - sat_set=set(filter(lambda x: eval_func(conds[x]),inds)) + sat_set=OrderedSet(filter(lambda x: eval_func(conds[x]),inds)) inds = inds - sat_set val_tuple.append(req_val_comb+', '+', '.join([conds[i] for i in sat_set])) problem.reset() @@ -803,7 +795,7 @@ def gen_inst(self,op_comb, val_comb, cgf): for op,val_soln in zip(op_comb,val_comb): val = [x for x in val_soln] - if any([x=='x0' for x in op]) or not (len(op) == len(set(op))): + if any([x=='x0' for x in op]) or not (len(op) == len(OrderedSet(op))): cont.append(val_soln) op_inds = list(ind_dict.keys()) for i,x in enumerate(op_inds): @@ -853,7 +845,7 @@ def gen_inst(self,op_comb, val_comb, cgf): else: instr_dict.append(self.__instr__(op,val)) - hits = defaultdict(lambda:set([])) + hits = defaultdict(lambda:OrderedSet([])) final_instr = [] rm_dict = { @@ -898,29 +890,29 @@ def eval_inst_coverage(coverpoints,instr): var_dict.update(ext_specific_vars) if 'val_comb' in coverpoints: - valcomb_hits = set([]) + valcomb_hits = OrderedSet([]) for coverpoint in coverpoints['val_comb']: if eval(coverpoint,globals(),var_dict): valcomb_hits.add(coverpoint) cover_hits['val_comb']=valcomb_hits if 'op_comb' in coverpoints: - opcomb_hits = set([]) + opcomb_hits = OrderedSet([]) for coverpoint in coverpoints['op_comb']: if eval(coverpoint,globals(),var_dict): opcomb_hits.add(coverpoint) cover_hits['op_comb']=opcomb_hits if 'rs1' in coverpoints: if var_dict['rs1'] in coverpoints['rs1']: - cover_hits['rs1'] = set([var_dict['rs1']]) + cover_hits['rs1'] = OrderedSet([var_dict['rs1']]) if 'rs2' in coverpoints: if var_dict['rs2'] in coverpoints['rs2']: - cover_hits['rs2'] = set([var_dict['rs2']]) + cover_hits['rs2'] = OrderedSet([var_dict['rs2']]) if 'rs3' in coverpoints: if var_dict['rs3'] in coverpoints['rs3']: - cover_hits['rs3'] = set([var_dict['rs3']]) + cover_hits['rs3'] = OrderedSet([var_dict['rs3']]) if 'rd' in coverpoints: if var_dict['rd'] in coverpoints['rd']: - cover_hits['rd'] = set([var_dict['rd']]) + cover_hits['rd'] = OrderedSet([var_dict['rd']]) return cover_hits i = 0 diff --git a/riscv-isac/riscv_isac/coverage.py b/riscv-isac/riscv_isac/coverage.py index b906473de..76866d9e1 100644 --- a/riscv-isac/riscv_isac/coverage.py +++ b/riscv-isac/riscv_isac/coverage.py @@ -188,7 +188,7 @@ def __init__(self,label,coverpoint,xlen,flen,addr_pairs,sig_addrs,window_size,in self.result = 0 self.queue = [] - self.tracked_regs = set() + self.tracked_regs = OrderedSet() self.instr_addr_of_tracked_reg = {} # tracked_reg: instr_addr of instr which triggered its tracking self.instr_stat_meta_at_addr = {} # start_instr_addr: [is_ucovpt, num_exp, num_obs, num_rem, covpts_hit, code_seq, store_addresses, store_vals] @@ -253,7 +253,7 @@ def compute_cross_cov(self): Also perform tracking for generating the data propagation report ''' hit_covpt = False - regs_to_track = set() + regs_to_track = OrderedSet() for index in range(len(self.ops)): instr = self.queue[index] @@ -920,8 +920,8 @@ def compute_per_line(queue, event, cgf_queue, stats_queue, cgf, xlen, flen, addr inxFlg = arch_state.inxFlg # Set of elements to monitor for tracking signature updates - tracked_regs_immutable = set() - tracked_regs_mutable = set() + tracked_regs_immutable = OrderedSet() + tracked_regs_mutable = OrderedSet() tracked_instrs = [] # list of tuples of the type (list_instr_names, triggering_instr_addr) instr_stat_meta_at_addr = {} # Maps an address to the stat metadata of the instruction present at that address [is_ucovpt, num_exp, num_obs, num_rem, covpts_hit, code_seq, store_addresses, store_vals] @@ -1262,7 +1262,7 @@ def get_key_from_value(dictionary, target_value): if hit_csr_covpt: stats.cov_pt_sig += covpt - csr_regs_involved_in_covpt = set() + csr_regs_involved_in_covpt = OrderedSet() for covpt in csr_covpt: for reg in csr_reg_num_to_str.values(): if reg in covpt: @@ -1717,7 +1717,7 @@ def compute(trace_file, test_name, cgf, parser_name, decoder_name, detailed, xle _x = (hex(x[0]), hex(x[1]), str(int((x[1]-x[0])/4)) + ' words') sig_addrs_hex.append(_x) - cov_set = set() + cov_set = OrderedSet() count = 1 for addrs,vals,cover,code in stats.stat1: sig = '' @@ -1753,7 +1753,7 @@ def compute(trace_file, test_name, cgf, parser_name, decoder_name, detailed, xle stat3_log += _l + '\n\n' stat5_log = '' - sig_set = set() + sig_set = OrderedSet() overwrites = 0 for addr, val, cover, code in stats.stat5: if addr in sig_set: diff --git a/riscv-isac/riscv_isac/data/rvopcodesdecoder.py b/riscv-isac/riscv_isac/data/rvopcodesdecoder.py index 8d176fb3e..0c26ff094 100644 --- a/riscv-isac/riscv_isac/data/rvopcodesdecoder.py +++ b/riscv-isac/riscv_isac/data/rvopcodesdecoder.py @@ -3,6 +3,7 @@ from collections import defaultdict import pprint import os +from ordered_set import OrderedSet from constants import * #from riscv_isac.data.constants import * @@ -232,13 +233,13 @@ def build_instr_dict(inst_dict): funct_occ = [funct[0] for ins in funct_list for funct in ins] # Path recoder - funct_path = set() + funct_path = OrderedSet() # Check if there are functions remaining while funct_occ: if (1, 0) in funct_occ: max_funct = (1, 0) else: - max_funct = max(set(funct_occ),key=funct_occ.count) + max_funct = max(OrderedSet(funct_occ),key=funct_occ.count) funct_occ = list(filter(lambda a: a != max_funct, funct_occ)) diff --git a/riscv-isac/riscv_isac/fp_dataset.py b/riscv-isac/riscv_isac/fp_dataset.py index b6b31304b..f05c8702c 100644 --- a/riscv-isac/riscv_isac/fp_dataset.py +++ b/riscv-isac/riscv_isac/fp_dataset.py @@ -4,6 +4,7 @@ import random import sys import math +from ordered_set import OrderedSet from decimal import * # Prasanna @@ -4941,7 +4942,7 @@ def ibm_b24(flen, iflen, opcode, ops, inxFlg=False): t = "{:e}".format(data[0]) b24_comb.append((floatingPoint_tohex(iflen,float(t)),data[1])) - b24_comb = set(b24_comb) + b24_comb = OrderedSet(b24_comb) coverpoints = [] k=0 diff --git a/riscv-isac/riscv_isac/plugins/internaldecoder.py b/riscv-isac/riscv_isac/plugins/internaldecoder.py index 9ab6053fd..3bd6592c5 100644 --- a/riscv-isac/riscv_isac/plugins/internaldecoder.py +++ b/riscv-isac/riscv_isac/plugins/internaldecoder.py @@ -1,3 +1,4 @@ +from ordered_set import OrderedSet import riscv_isac.plugins as plugins class disassembler(): @@ -38,9 +39,9 @@ def __init__(self): self.C_OPCODES = C_OPCODES self.OPCODES = OPCODES self.init_rvp_dictionary() - self.rvp_rs1_is_64bit_set = set('smal add64 radd64 uradd64 kadd64 ukadd64 sub64 rsub64 ursub64 ksub64 uksub64 wext wexti'.split()) - self.rvp_rs2_is_64bit_set = set( 'add64 radd64 uradd64 kadd64 ukadd64 sub64 rsub64 ursub64 ksub64 uksub64'.split()) - self.rvp_rd_is_64bit_set = set('smul16 smulx16 umul16 umulx16 smul8 smulx8 umul8 umulx8 smal add64 radd64 uradd64 kadd64 ukadd64 sub64 rsub64 ursub64 ksub64 uksub64 smar64 smsr64 umar64 umsr64 kmar64 kmsr64 ukmar64 ukmsr64 smalbb smalbt smaltt smalda smalxda smalds smaldrs smalxds smslda smslxda mulr64 mulsr64 wext wexti'.split()) + self.rvp_rs1_is_64bit_set = OrderedSet('smal add64 radd64 uradd64 kadd64 ukadd64 sub64 rsub64 ursub64 ksub64 uksub64 wext wexti'.split()) + self.rvp_rs2_is_64bit_set = OrderedSet( 'add64 radd64 uradd64 kadd64 ukadd64 sub64 rsub64 ursub64 ksub64 uksub64'.split()) + self.rvp_rd_is_64bit_set = OrderedSet('smul16 smulx16 umul16 umulx16 smul8 smulx8 umul8 umulx8 smal add64 radd64 uradd64 kadd64 ukadd64 sub64 rsub64 ursub64 ksub64 uksub64 smar64 smsr64 umar64 umsr64 kmar64 kmsr64 ukmar64 ukmsr64 smalbb smalbt smaltt smalda smalxda smalds smaldrs smalxds smslda smslxda mulr64 mulsr64 wext wexti'.split()) def init_rvp_dictionary(self): # Create RVP Dictiory 0 for instruction: clrs8 clrs16 clrs32 clo8 clo16 clo32 clz8 clz16 clz32 kabs8 kabs16 kabsw sunpkd810 sunpkd820 sunpkd830 sunpkd831 sunpkd832 swap8 zunpkd810 zunpkd820 zunpkd830 zunpkd831 zunpkd832 kabs32 From 083ffaf6d7d769191b2b51c09505cef62a19b125 Mon Sep 17 00:00:00 2001 From: MingZhu Yan <69898423+trdthg@users.noreply.github.com> Date: Tue, 31 Dec 2024 17:53:42 +0800 Subject: [PATCH 07/10] [CTG] Add new cli param '--filter' (#571) Co-authored-by: Umer Shahid --- riscv-ctg/riscv_ctg/ctg.py | 12 +++++++++--- riscv-ctg/riscv_ctg/main.py | 5 +++-- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/riscv-ctg/riscv_ctg/ctg.py b/riscv-ctg/riscv_ctg/ctg.py index 09bc3e34a..2057867a8 100644 --- a/riscv-ctg/riscv_ctg/ctg.py +++ b/riscv-ctg/riscv_ctg/ctg.py @@ -100,7 +100,7 @@ def gen_test(op_node, opcode): logger.info('Writing tests for csr_comb') csr_comb_gen.write_test(fprefix, node, usage_str, label, csr_comb_instr_dict) -def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, max_inst,inxFlag): +def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, max_inst,inxFlag,filter): logger.level(verbose) logger.info('****** RISC-V Compliance Test Generator {0} *******'.format(__version__ )) logger.info('Copyright (c) 2020, InCore Semiconductors Pvt. Ltd.') @@ -134,6 +134,12 @@ def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, ma op_template = utils.load_yaml(const.template_files) cgf = expand_cgf(cgf_file,xlen,flen) pool = mp.Pool(num_procs) - results = pool.starmap(create_test, [(usage_str, node,label,base_isa,max_inst, op_template, - randomize, out_dir, xlen, flen, inxFlag) for label,node in cgf.items()]) + + args_list = [] + for label,node in cgf.items(): + if filter is not None and re.search(filter, label) is None: + continue + args_list.append((usage_str, node,label,base_isa,max_inst, op_template, + randomize, out_dir, xlen, flen, inxFlag)) + results = pool.starmap(create_test, args_list) pool.close() diff --git a/riscv-ctg/riscv_ctg/main.py b/riscv-ctg/riscv_ctg/main.py index 98d172e38..808503904 100644 --- a/riscv-ctg/riscv_ctg/main.py +++ b/riscv-ctg/riscv_ctg/main.py @@ -20,11 +20,12 @@ hardware.",default='32') @click.option("--inst",type=int,help="Maximum number of Macro Instances per test.") @click.option("--z-inx", '-ix', type=bool, default='False', help="If the extension is Z*inx then pass True otherwise defaulted to False") -def cli(verbose, out_dir, randomize , cgf,procs,base_isa, flen,inst,z_inx): +@click.option("--filter", type=str, help="Filtering tests to be generated with regex") +def cli(verbose, out_dir, randomize , cgf,procs,base_isa, flen,inst,z_inx,filter): if not os.path.exists(out_dir): os.mkdir(out_dir) if '32' in base_isa: xlen = 32 elif '64' in base_isa: xlen = 64 - ctg(verbose, out_dir, randomize ,xlen, int(flen), cgf,procs,base_isa,inst,z_inx) + ctg(verbose, out_dir, randomize ,xlen, int(flen), cgf,procs,base_isa,inst,z_inx,filter) From bba2feeb6ea1bcf590396031fb663b8c44d81e25 Mon Sep 17 00:00:00 2001 From: MingZhu Yan <69898423+trdthg@users.noreply.github.com> Date: Tue, 31 Dec 2024 18:20:07 +0800 Subject: [PATCH 08/10] Update sraw test cases (#565) - Add sraw to unsgn_rs2 group - The sraw testcases were very old with a covarage of 98.20% (109/111), this patch regenerate the cases with riscv_ctg (without `-r`), making covarageto 100%. Co-authored-by: Umer Shahid --- riscv-isac/riscv_isac/InstructionObject.py | 2 +- riscv-test-suite/rv64i_m/I/src/sraw-01.S | 856 ++++----------------- 2 files changed, 135 insertions(+), 723 deletions(-) diff --git a/riscv-isac/riscv_isac/InstructionObject.py b/riscv-isac/riscv_isac/InstructionObject.py index 9e24eb600..d12761682 100644 --- a/riscv-isac/riscv_isac/InstructionObject.py +++ b/riscv-isac/riscv_isac/InstructionObject.py @@ -27,7 +27,7 @@ 'sh2add.uw','sh3add.uw','slli.uw','clz','clzw','ctz','ctzw','cpop','cpopw','rev8',\ 'bclri','bexti','binvi','bseti','xperm4','xperm8','zip','unzip','gorci','fcvt.d.wu','fcvt.s.wu','fcvt.d.lu','fcvt.s.lu','c.flwsp','c.fldsp','c.flw','c.fld'\ 'c.not', 'c.sext.b','c.sext.h','c.zext.b','c.zext.h','c.zext.w','sc.w','lr.w','sc.d','lr.d'] -unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra','mulhu',\ +unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra', 'sraw', 'mulhu',\ 'mulhsu','divu','remu','divuw','remuw','aes64ds','aes64dsm','aes64es',\ 'aes64esm','aes64ks2','sm4ed','sm4ks','ror','rol','rorw','rolw','clmul',\ 'clmulh','clmulr','andn','orn','xnor','pack','packh','packu','packuw','packw',\ diff --git a/riscv-test-suite/rv64i_m/I/src/sraw-01.S b/riscv-test-suite/rv64i_m/I/src/sraw-01.S index 003d45517..9e813d4bd 100644 --- a/riscv-test-suite/rv64i_m/I/src/sraw-01.S +++ b/riscv-test-suite/rv64i_m/I/src/sraw-01.S @@ -1,11 +1,13 @@ // ----------- -// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg) -// version : 0.4.1 -// timestamp : Wed Dec 16 03:45:17 2020 GMT +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Tue Nov 19 02:34:25 2024 GMT // usage : riscv_ctg \ -// -- cgf ('/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/dataset.cgf', '/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/rv64i.cgf') \ -// -- xlen 64 \ +// -- cgf // --cgf /workspaces/riscv-arch-test/coverage/dataset.cgf \ +// --cgf /workspaces/riscv-arch-test/coverage/i/rv64i.cgf \ + \ +// -- xlen 64 \ // ----------- // // ----------- @@ -13,7 +15,7 @@ // SPDX-License-Identifier: BSD-3-Clause // ----------- // -// This assembly file tests the sraw instruction of the RISC-V i extension for the sraw covergroup. +// This assembly file tests the sraw instruction of the RISC-V RV64 extension for the sraw covergroup. // #include "model_test.h" #include "arch_test.h" @@ -27,780 +29,190 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*);def TEST_CASE_1=True;",sraw) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*);def TEST_CASE_1=True;",sraw) -RVTEST_SIGBASE( x3,signature_x3_1) +RVTEST_SIGBASE(x1,signature_x1_1) inst_0: -// rs1 == rs2 != rd, rs1==x13, rs2==x13, rd==x2, rs1_val < 0 and rs2_val > 0 and rs2_val < xlen, rs1_val == -257, rs2_val == 1 -// opcode: sraw ; op1:x13; op2:x13; dest:x2; op1val:-0x101; op2val:-0x101 -TEST_RR_OP(sraw, x2, x13, x13, -0x1, -0x101, -0x101, x3, 0, x14) +// rs1 == rs2 != rd, rs1==x30, rs2==x30, rd==x31, rs1_val < 0 and rs2_val == 0, +// opcode: sraw ; op1:x30; op2:x30; dest:x31; op1val:-0xb504f332; op2val:-0xb504f332 +TEST_RR_OP(sraw, x31, x30, x30, 0x12bec, -0xb504f332, -0xb504f332, x1, 0*XLEN/8, x2) inst_1: -// rs2 == rd != rs1, rs1==x5, rs2==x15, rd==x15, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen, rs1_val == 4096 -// opcode: sraw ; op1:x5; op2:x15; dest:x15; op1val:0x1000; op2val:0x1f -TEST_RR_OP(sraw, x15, x5, x15, 0x0, 0x1000, 0x1f, x3, 8, x14) +// rs1 == rd != rs2, rs1==x29, rs2==x31, rd==x29, rs1_val < 0 and rs2_val > 0 and rs2_val < xlen, +// opcode: sraw ; op1:x29; op2:x31; dest:x29; op1val:-0xb504f332; op2val:0x1f +TEST_RR_OP(sraw, x29, x29, x31, 0x0, -0xb504f332, 0x1f, x1, 1*XLEN/8, x2) inst_2: -// rs1 == rs2 == rd, rs1==x6, rs2==x6, rd==x6, rs1_val < 0 and rs2_val == 0, rs1_val == -131073 -// opcode: sraw ; op1:x6; op2:x6; dest:x6; op1val:-0x20001; op2val:-0x20001 -TEST_RR_OP(sraw, x6, x6, x6, -0x1, -0x20001, -0x20001, x3, 16, x14) +// rs1 == rs2 == rd, rs1==x28, rs2==x28, rd==x28, rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen, +// opcode: sraw ; op1:x28; op2:x28; dest:x28; op1val:-0x8000000000000000; op2val:-0x8000000000000000 +TEST_RR_OP(sraw, x28, x28, x28, 0x0, -0x8000000000000000, -0x8000000000000000, x1, 2*XLEN/8, x2) inst_3: -// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x25, rs2==x26, rd==x13, rs1_val > 0 and rs2_val == 0, rs1_val == 524288 -// opcode: sraw ; op1:x25; op2:x26; dest:x13; op1val:0x80000; op2val:0x0 -TEST_RR_OP(sraw, x13, x25, x26, 0x80000, 0x80000, 0x0, x3, 24, x14) +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x31, rs2==x29, rd==x30, rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen +// opcode: sraw ; op1:x31; op2:x29; dest:x30; op1val:0x7fffffffffffffff; op2val:0x1f +TEST_RR_OP(sraw, x30, x31, x29, -0x1, 0x7fffffffffffffff, 0x1f, x1, 3*XLEN/8, x2) inst_4: -// rs1 == rd != rs2, rs1==x23, rs2==x11, rd==x23, rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen, -// opcode: sraw ; op1:x23; op2:x11; dest:x23; op1val:0x9; op2val:0x9 -TEST_RR_OP(sraw, x23, x23, x11, 0x0, 0x9, 0x9, x3, 32, x14) +// rs2 == rd != rs1, rs1==x26, rs2==x27, rd==x27, rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen, +// opcode: sraw ; op1:x26; op2:x27; dest:x27; op1val:0x0; op2val:0x1f +TEST_RR_OP(sraw, x27, x26, x27, 0x0, 0x0, 0x1f, x1, 4*XLEN/8, x2) inst_5: -// rs1==x9, rs2==x18, rd==x0, rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen, rs1_val == -9223372036854775808 -// opcode: sraw ; op1:x9; op2:x18; dest:x0; op1val:-0x8000000000000000; op2val:0xe -TEST_RR_OP(sraw, x0, x9, x18, 0, -0x8000000000000000, 0xe, x3, 40, x14) +// rs1==x27, rs2==x25, rd==x26, rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen, +// opcode: sraw ; op1:x27; op2:x25; dest:x26; op1val:0x1; op2val:0x1f +TEST_RR_OP(sraw, x26, x27, x25, 0x0, 0x1, 0x1f, x1, 5*XLEN/8, x2) inst_6: -// rs1==x11, rs2==x27, rd==x9, rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen, rs1_val==0 -// opcode: sraw ; op1:x11; op2:x27; dest:x9; op1val:0x0; op2val:0x13 -TEST_RR_OP(sraw, x9, x11, x27, 0x0, 0x0, 0x13, x3, 48, x14) +// rs1==x24, rs2==x26, rd==x25, rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen, +// opcode: sraw ; op1:x24; op2:x26; dest:x25; op1val:0x10; op2val:0x10 +TEST_RR_OP(sraw, x25, x24, x26, 0x0, 0x10, 0x10, x1, 6*XLEN/8, x2) inst_7: -// rs1==x30, rs2==x12, rd==x8, rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen, rs1_val == 9223372036854775807, rs2_val == 21 -// opcode: sraw ; op1:x30; op2:x12; dest:x8; op1val:0x7fffffffffffffff; op2val:0x15 -TEST_RR_OP(sraw, x8, x30, x12, -0x1, 0x7fffffffffffffff, 0x15, x3, 56, x14) +// rs1==x25, rs2==x23, rd==x24, rs1_val > 0 and rs2_val == 0, +// opcode: sraw ; op1:x25; op2:x23; dest:x24; op1val:0xb504f334; op2val:0x0 +TEST_RR_OP(sraw, x24, x25, x23, -0x4afb0ccc, 0xb504f334, 0x0, x1, 7*XLEN/8, x2) inst_8: -// rs1==x29, rs2==x7, rd==x21, rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen, rs1_val == 1 -// opcode: sraw ; op1:x29; op2:x7; dest:x21; op1val:0x1; op2val:0x0 -TEST_RR_OP(sraw, x21, x29, x7, 0x1, 0x1, 0x0, x3, 64, x14) +// rs1==x22, rs2==x24, rd==x23, +// opcode: sraw ; op1:x22; op2:x24; dest:x23; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x23, x22, x24, 0x0, 0x0, 0x0, x1, 8*XLEN/8, x2) inst_9: -// rs1==x0, rs2==x24, rd==x5, rs1_val == 2, rs1_val==2, rs2_val == 10 -// opcode: sraw ; op1:x0; op2:x24; dest:x5; op1val:0x0; op2val:0xa -TEST_RR_OP(sraw, x5, x0, x24, 0x0, 0x0, 0xa, x3, 72, x14) +// rs1==x23, rs2==x21, rd==x22, +// opcode: sraw ; op1:x23; op2:x21; dest:x22; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x22, x23, x21, 0x0, 0x0, 0x0, x1, 9*XLEN/8, x2) inst_10: -// rs1==x19, rs2==x22, rd==x27, rs1_val == 4, rs1_val==4 -// opcode: sraw ; op1:x19; op2:x22; dest:x27; op1val:0x4; op2val:0x13 -TEST_RR_OP(sraw, x27, x19, x22, 0x0, 0x4, 0x13, x3, 80, x14) +// rs1==x20, rs2==x22, rd==x21, +// opcode: sraw ; op1:x20; op2:x22; dest:x21; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x21, x20, x22, 0x0, 0x0, 0x0, x1, 10*XLEN/8, x2) inst_11: -// rs1==x17, rs2==x4, rd==x1, rs1_val == 8, -// opcode: sraw ; op1:x17; op2:x4; dest:x1; op1val:0x8; op2val:0x9 -TEST_RR_OP(sraw, x1, x17, x4, 0x0, 0x8, 0x9, x3, 88, x14) +// rs1==x21, rs2==x19, rd==x20, +// opcode: sraw ; op1:x21; op2:x19; dest:x20; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x20, x21, x19, 0x0, 0x0, 0x0, x1, 11*XLEN/8, x2) inst_12: -// rs1==x1, rs2==x25, rd==x31, rs1_val == 16, rs2_val == 23 -// opcode: sraw ; op1:x1; op2:x25; dest:x31; op1val:0x10; op2val:0x17 -TEST_RR_OP(sraw, x31, x1, x25, 0x0, 0x10, 0x17, x3, 96, x14) +// rs1==x18, rs2==x20, rd==x19, +// opcode: sraw ; op1:x18; op2:x20; dest:x19; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x19, x18, x20, 0x0, 0x0, 0x0, x1, 12*XLEN/8, x2) inst_13: -// rs1==x10, rs2==x9, rd==x30, rs1_val == 32, rs2_val == 15 -// opcode: sraw ; op1:x10; op2:x9; dest:x30; op1val:0x20; op2val:0xf -TEST_RR_OP(sraw, x30, x10, x9, 0x0, 0x20, 0xf, x3, 104, x14) +// rs1==x19, rs2==x17, rd==x18, +// opcode: sraw ; op1:x19; op2:x17; dest:x18; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x18, x19, x17, 0x0, 0x0, 0x0, x1, 13*XLEN/8, x2) inst_14: -// rs1==x16, rs2==x23, rd==x26, rs1_val == 64, -// opcode: sraw ; op1:x16; op2:x23; dest:x26; op1val:0x40; op2val:0x17 -TEST_RR_OP(sraw, x26, x16, x23, 0x0, 0x40, 0x17, x3, 112, x14) +// rs1==x16, rs2==x18, rd==x17, +// opcode: sraw ; op1:x16; op2:x18; dest:x17; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x17, x16, x18, 0x0, 0x0, 0x0, x1, 14*XLEN/8, x2) inst_15: -// rs1==x21, rs2==x8, rd==x28, rs1_val == 128, rs2_val == 4 -// opcode: sraw ; op1:x21; op2:x8; dest:x28; op1val:0x80; op2val:0x4 -TEST_RR_OP(sraw, x28, x21, x8, 0x8, 0x80, 0x4, x3, 120, x9) -RVTEST_SIGBASE( x6,signature_x6_0) +// rs1==x17, rs2==x15, rd==x16, +// opcode: sraw ; op1:x17; op2:x15; dest:x16; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x16, x17, x15, 0x0, 0x0, 0x0, x1, 15*XLEN/8, x2) inst_16: -// rs1==x20, rs2==x16, rd==x24, rs1_val == 256, -// opcode: sraw ; op1:x20; op2:x16; dest:x24; op1val:0x100; op2val:0xd -TEST_RR_OP(sraw, x24, x20, x16, 0x0, 0x100, 0xd, x6, 0, x9) +// rs1==x14, rs2==x16, rd==x15, +// opcode: sraw ; op1:x14; op2:x16; dest:x15; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x15, x14, x16, 0x0, 0x0, 0x0, x1, 16*XLEN/8, x2) inst_17: -// rs1==x27, rs2==x2, rd==x17, rs1_val == 512, -// opcode: sraw ; op1:x27; op2:x2; dest:x17; op1val:0x200; op2val:0xe -TEST_RR_OP(sraw, x17, x27, x2, 0x0, 0x200, 0xe, x6, 8, x9) +// rs1==x15, rs2==x13, rd==x14, +// opcode: sraw ; op1:x15; op2:x13; dest:x14; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x14, x15, x13, 0x0, 0x0, 0x0, x1, 17*XLEN/8, x2) inst_18: -// rs1==x15, rs2==x10, rd==x22, rs1_val == 1024, -// opcode: sraw ; op1:x15; op2:x10; dest:x22; op1val:0x400; op2val:0x5 -TEST_RR_OP(sraw, x22, x15, x10, 0x20, 0x400, 0x5, x6, 16, x9) +// rs1==x12, rs2==x14, rd==x13, +// opcode: sraw ; op1:x12; op2:x14; dest:x13; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x13, x12, x14, 0x0, 0x0, 0x0, x1, 18*XLEN/8, x2) inst_19: -// rs1==x7, rs2==x30, rd==x11, rs1_val == 2048, -// opcode: sraw ; op1:x7; op2:x30; dest:x11; op1val:0x800; op2val:0xa -TEST_RR_OP(sraw, x11, x7, x30, 0x2, 0x800, 0xa, x6, 24, x9) +// rs1==x13, rs2==x11, rd==x12, +// opcode: sraw ; op1:x13; op2:x11; dest:x12; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x12, x13, x11, 0x0, 0x0, 0x0, x1, 19*XLEN/8, x2) inst_20: -// rs1==x28, rs2==x1, rd==x25, rs1_val == 8192, rs2_val == 27 -// opcode: sraw ; op1:x28; op2:x1; dest:x25; op1val:0x2000; op2val:0x1b -TEST_RR_OP(sraw, x25, x28, x1, 0x0, 0x2000, 0x1b, x6, 32, x9) +// rs1==x10, rs2==x12, rd==x11, +// opcode: sraw ; op1:x10; op2:x12; dest:x11; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x11, x10, x12, 0x0, 0x0, 0x0, x1, 20*XLEN/8, x2) inst_21: -// rs1==x31, rs2==x0, rd==x12, rs1_val == 16384, rs2_val == 2 -// opcode: sraw ; op1:x31; op2:x0; dest:x12; op1val:0x4000; op2val:0x0 -TEST_RR_OP(sraw, x12, x31, x0, 0x4000, 0x4000, 0x0, x6, 40, x9) +// rs1==x11, rs2==x9, rd==x10, +// opcode: sraw ; op1:x11; op2:x9; dest:x10; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x10, x11, x9, 0x0, 0x0, 0x0, x1, 21*XLEN/8, x2) inst_22: -// rs1==x22, rs2==x29, rd==x20, rs1_val == 32768, -// opcode: sraw ; op1:x22; op2:x29; dest:x20; op1val:0x8000; op2val:0xb -TEST_RR_OP(sraw, x20, x22, x29, 0x10, 0x8000, 0xb, x6, 48, x9) +// rs1==x8, rs2==x10, rd==x9, +// opcode: sraw ; op1:x8; op2:x10; dest:x9; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x9, x8, x10, 0x0, 0x0, 0x0, x1, 22*XLEN/8, x2) inst_23: -// rs1==x14, rs2==x28, rd==x3, rs1_val == 65536, rs2_val == 16 -// opcode: sraw ; op1:x14; op2:x28; dest:x3; op1val:0x10000; op2val:0x10 -TEST_RR_OP(sraw, x3, x14, x28, 0x1, 0x10000, 0x10, x6, 56, x9) +// rs1==x9, rs2==x7, rd==x8, +// opcode: sraw ; op1:x9; op2:x7; dest:x8; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x8, x9, x7, 0x0, 0x0, 0x0, x1, 23*XLEN/8, x2) inst_24: -// rs1==x3, rs2==x21, rd==x29, rs1_val == 131072, -// opcode: sraw ; op1:x3; op2:x21; dest:x29; op1val:0x20000; op2val:0x13 -TEST_RR_OP(sraw, x29, x3, x21, 0x0, 0x20000, 0x13, x6, 64, x9) +// rs1==x6, rs2==x8, rd==x7, +// opcode: sraw ; op1:x6; op2:x8; dest:x7; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x7, x6, x8, 0x0, 0x0, 0x0, x1, 24*XLEN/8, x9) +RVTEST_SIGBASE(x8,signature_x8_0) inst_25: -// rs1==x24, rs2==x20, rd==x14, rs1_val == 262144, -// opcode: sraw ; op1:x24; op2:x20; dest:x14; op1val:0x40000; op2val:0x10 -TEST_RR_OP(sraw, x14, x24, x20, 0x4, 0x40000, 0x10, x6, 72, x9) +// rs1==x7, rs2==x5, rd==x6, +// opcode: sraw ; op1:x7; op2:x5; dest:x6; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x6, x7, x5, 0x0, 0x0, 0x0, x8, 0*XLEN/8, x9) inst_26: -// rs1==x2, rs2==x19, rd==x10, rs1_val == 1048576, rs2_val == 29 -// opcode: sraw ; op1:x2; op2:x19; dest:x10; op1val:0x100000; op2val:0x1d -TEST_RR_OP(sraw, x10, x2, x19, 0x0, 0x100000, 0x1d, x6, 80, x9) +// rs1==x4, rs2==x6, rd==x5, +// opcode: sraw ; op1:x4; op2:x6; dest:x5; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x5, x4, x6, 0x0, 0x0, 0x0, x8, 1*XLEN/8, x9) inst_27: -// rs1==x18, rs2==x14, rd==x16, rs1_val == 2097152, -// opcode: sraw ; op1:x18; op2:x14; dest:x16; op1val:0x200000; op2val:0xe -TEST_RR_OP(sraw, x16, x18, x14, 0x80, 0x200000, 0xe, x6, 88, x9) +// rs1==x5, rs2==x3, rd==x4, +// opcode: sraw ; op1:x5; op2:x3; dest:x4; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x4, x5, x3, 0x0, 0x0, 0x0, x8, 2*XLEN/8, x9) inst_28: -// rs1==x12, rs2==x17, rd==x18, rs1_val == 4194304, -// opcode: sraw ; op1:x12; op2:x17; dest:x18; op1val:0x400000; op2val:0x12 -TEST_RR_OP(sraw, x18, x12, x17, 0x10, 0x400000, 0x12, x6, 96, x9) +// rs1==x2, rs2==x4, rd==x3, +// opcode: sraw ; op1:x2; op2:x4; dest:x3; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x3, x2, x4, 0x0, 0x0, 0x0, x8, 3*XLEN/8, x9) inst_29: -// rs1==x8, rs2==x5, rd==x4, rs1_val == 8388608, -// opcode: sraw ; op1:x8; op2:x5; dest:x4; op1val:0x800000; op2val:0xd -TEST_RR_OP(sraw, x4, x8, x5, 0x400, 0x800000, 0xd, x6, 104, x9) +// rs1==x3, rs2==x1, rd==x2, +// opcode: sraw ; op1:x3; op2:x1; dest:x2; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x2, x3, x1, 0x0, 0x0, 0x0, x8, 4*XLEN/8, x9) inst_30: -// rs1==x4, rs2==x31, rd==x7, rs1_val == 16777216, -// opcode: sraw ; op1:x4; op2:x31; dest:x7; op1val:0x1000000; op2val:0x9 -TEST_RR_OP(sraw, x7, x4, x31, 0x8000, 0x1000000, 0x9, x6, 112, x9) +// rs1==x0, rs2==x2, rd==x1, +// opcode: sraw ; op1:x0; op2:x2; dest:x1; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x1, x0, x2, 0x0, 0x0, 0x0, x8, 5*XLEN/8, x9) inst_31: -// rs1==x26, rs2==x3, rd==x19, rs1_val == 33554432, rs2_val == 8 -// opcode: sraw ; op1:x26; op2:x3; dest:x19; op1val:0x2000000; op2val:0x8 -TEST_RR_OP(sraw, x19, x26, x3, 0x20000, 0x2000000, 0x8, x6, 120, x9) +// rs1==x1, +// opcode: sraw ; op1:x1; op2:x30; dest:x31; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x31, x1, x30, 0x0, 0x0, 0x0, x8, 6*XLEN/8, x9) inst_32: -// rs1_val == 67108864, rs2_val == 30 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x4000000; op2val:0x1e -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x4000000, 0x1e, x6, 128, x1) +// rs2==x0, +// opcode: sraw ; op1:x30; op2:x0; dest:x31; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x31, x30, x0, 0x0, 0x0, 0x0, x8, 7*XLEN/8, x9) inst_33: -// rs1_val == 134217728, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x8000000; op2val:0xc -TEST_RR_OP(sraw, x12, x10, x11, 0x8000, 0x8000000, 0xc, x6, 136, x1) +// rd==x0, +// opcode: sraw ; op1:x31; op2:x30; dest:x0; op1val:0x0; op2val:0x0 +TEST_RR_OP(sraw, x0, x31, x30, 0, 0x0, 0x0, x8, 8*XLEN/8, x9) inst_34: -// rs1_val == 268435456, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x10000000; op2val:0x1e -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x10000000, 0x1e, x6, 144, x1) +// rs1_val < 0 and rs2_val == 0, +// opcode: sraw ; op1:x30; op2:x29; dest:x31; op1val:-0xb504f332; op2val:0x0 +TEST_RR_OP(sraw, x31, x30, x29, 0x4afb0cce, -0xb504f332, 0x0, x8, 9*XLEN/8, x9) inst_35: -// rs1_val == 536870912, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x20000000; op2val:0x0 -TEST_RR_OP(sraw, x12, x10, x11, 0x20000000, 0x20000000, 0x0, x6, 152, x1) - -inst_36: -// rs1_val == 1073741824, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x40000000; op2val:0x1e -TEST_RR_OP(sraw, x12, x10, x11, 0x1, 0x40000000, 0x1e, x6, 160, x1) - -inst_37: -// rs1_val == 2147483648, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x80000000; op2val:0xd -TEST_RR_OP(sraw, x12, x10, x11, -0x40000, 0x80000000, 0xd, x6, 168, x1) - -inst_38: -// rs1_val == 4294967296, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x100000000; op2val:0x4 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x100000000, 0x4, x6, 176, x1) - -inst_39: -// rs1_val == 8589934592, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x200000000; op2val:0x11 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x200000000, 0x11, x6, 184, x1) - -inst_40: -// rs1_val == 17179869184, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x400000000; op2val:0x4 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x400000000, 0x4, x6, 192, x1) - -inst_41: -// rs1_val == 34359738368, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x800000000; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x800000000, 0xa, x6, 200, x1) - -inst_42: -// rs1_val == 68719476736, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x1000000000; op2val:0x5 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x1000000000, 0x5, x6, 208, x1) - -inst_43: -// rs1_val == 137438953472, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000; op2val:0x1f -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x2000000000, 0x1f, x6, 216, x1) - -inst_44: -// rs1_val == 274877906944, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x4000000000, 0xa, x6, 224, x1) - -inst_45: -// rs1_val == 549755813888, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000; op2val:0x1e -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x8000000000, 0x1e, x6, 232, x1) - -inst_46: -// rs1_val == 1099511627776, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x10000000000; op2val:0x1 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x10000000000, 0x1, x6, 240, x1) - -inst_47: -// rs1_val == 2199023255552, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x20000000000; op2val:0x1 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x20000000000, 0x1, x6, 248, x1) - -inst_48: -// rs1_val == 4398046511104, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x40000000000; op2val:0x4 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x40000000000, 0x4, x6, 256, x1) - -inst_49: -// rs1_val == 8796093022208, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x80000000000; op2val:0x2 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x80000000000, 0x2, x6, 264, x1) - -inst_50: -// rs1_val == 17592186044416, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x100000000000; op2val:0x9 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x100000000000, 0x9, x6, 272, x1) - -inst_51: -// rs1_val == 35184372088832, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x200000000000; op2val:0x1f -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x200000000000, 0x1f, x6, 280, x1) - -inst_52: -// rs1_val == 70368744177664, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x400000000000; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x400000000000, 0x17, x6, 288, x1) - -inst_53: -// rs1_val == 140737488355328, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x800000000000; op2val:0x6 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x800000000000, 0x6, x6, 296, x1) - -inst_54: -// rs1_val == 281474976710656, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x1000000000000; op2val:0xc -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x1000000000000, 0xc, x6, 304, x1) - -inst_55: -// rs1_val == 562949953421312, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000; op2val:0xb -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x2000000000000, 0xb, x6, 312, x1) - -inst_56: -// rs1_val == 1125899906842624, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000; op2val:0x8 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x4000000000000, 0x8, x6, 320, x1) - -inst_57: -// rs1_val == 2251799813685248, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000; op2val:0xc -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x8000000000000, 0xc, x6, 328, x1) - -inst_58: -// rs1_val == 4503599627370496, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x10000000000000; op2val:0x1b -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x10000000000000, 0x1b, x6, 336, x1) - -inst_59: -// rs1_val == 9007199254740992, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x20000000000000; op2val:0x0 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x20000000000000, 0x0, x6, 344, x1) - -inst_60: -// rs1_val == 18014398509481984, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x40000000000000; op2val:0x1d -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x40000000000000, 0x1d, x6, 352, x1) - -inst_61: -// rs1_val == 36028797018963968, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x80000000000000; op2val:0x1d -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x80000000000000, 0x1d, x6, 360, x1) - -inst_62: -// rs1_val == 72057594037927936, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x100000000000000; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x100000000000000, 0x17, x6, 368, x1) - -inst_63: -// rs1_val == 144115188075855872, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x200000000000000; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x200000000000000, 0x17, x6, 376, x1) - -inst_64: -// rs1_val == 288230376151711744, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x400000000000000; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x400000000000000, 0xa, x6, 384, x1) - -inst_65: -// rs1_val == 576460752303423488, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x800000000000000; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x800000000000000, 0xa, x6, 392, x1) - -inst_66: -// rs1_val == 1152921504606846976, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x1000000000000000; op2val:0x5 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x1000000000000000, 0x5, x6, 400, x1) - -inst_67: -// rs1_val == 2305843009213693952, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000; op2val:0x3 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x2000000000000000, 0x3, x6, 408, x1) - -inst_68: -// rs1_val == 4611686018427387904, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000; op2val:0x6 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x4000000000000000, 0x6, x6, 416, x1) - -inst_69: -// rs1_val == -2, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x2; op2val:0x1f -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x2, 0x1f, x6, 424, x1) - -inst_70: -// rs1_val == -3, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x3; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x3, 0xa, x6, 432, x1) - -inst_71: -// rs1_val == -5, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x5; op2val:0x1f -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x5, 0x1f, x6, 440, x1) - -inst_72: -// rs1_val == -9, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x9; op2val:0x8 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x9, 0x8, x6, 448, x1) - -inst_73: -// rs1_val == -17, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x11; op2val:0xd -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x11, 0xd, x6, 456, x1) - -inst_74: -// rs1_val == -33, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x21; op2val:0x15 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x21, 0x15, x6, 464, x1) - -inst_75: -// rs1_val == -65, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x41; op2val:0x15 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x41, 0x15, x6, 472, x1) - -inst_76: -// rs1_val == -129, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x81; op2val:0x2 -TEST_RR_OP(sraw, x12, x10, x11, -0x21, -0x81, 0x2, x6, 480, x1) - -inst_77: -// rs1_val == -513, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x201; op2val:0x9 -TEST_RR_OP(sraw, x12, x10, x11, -0x2, -0x201, 0x9, x6, 488, x1) - -inst_78: -// rs1_val == -1025, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x401; op2val:0x15 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x401, 0x15, x6, 496, x1) - -inst_79: -// rs1_val == -2049, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x801; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x801, 0x17, x6, 504, x1) - -inst_80: -// rs1_val == -4097, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x1001; op2val:0x4 -TEST_RR_OP(sraw, x12, x10, x11, -0x101, -0x1001, 0x4, x6, 512, x1) - -inst_81: -// rs1_val == -8193, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x2001; op2val:0x5 -TEST_RR_OP(sraw, x12, x10, x11, -0x101, -0x2001, 0x5, x6, 520, x1) - -inst_82: -// rs1_val == -16385, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x4001; op2val:0x0 -TEST_RR_OP(sraw, x12, x10, x11, -0x4001, -0x4001, 0x0, x6, 528, x1) - -inst_83: -// rs1_val == -32769, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x8001; op2val:0x7 -TEST_RR_OP(sraw, x12, x10, x11, -0x101, -0x8001, 0x7, x6, 536, x1) - -inst_84: -// rs1_val == -65537, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x10001; op2val:0x1f -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x10001, 0x1f, x6, 544, x1) - -inst_85: -// rs1_val == -262145, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x40001; op2val:0xb -TEST_RR_OP(sraw, x12, x10, x11, -0x81, -0x40001, 0xb, x6, 552, x1) - -inst_86: -// rs1_val == -524289, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x80001; op2val:0x6 -TEST_RR_OP(sraw, x12, x10, x11, -0x2001, -0x80001, 0x6, x6, 560, x1) - -inst_87: -// rs1_val == -1048577, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x100001; op2val:0x5 -TEST_RR_OP(sraw, x12, x10, x11, -0x8001, -0x100001, 0x5, x6, 568, x1) - -inst_88: -// rs1_val == -36028797018963969, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000000001; op2val:0xb -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x80000000000001, 0xb, x6, 576, x1) - -inst_89: -// rs1_val == -72057594037927937, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x100000000000001; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x100000000000001, 0x17, x6, 584, x1) - -inst_90: -// rs1_val == -144115188075855873, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x200000000000001; op2val:0x10 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x200000000000001, 0x10, x6, 592, x1) - -inst_91: -// rs1_val == -288230376151711745, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x400000000000001; op2val:0x11 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x400000000000001, 0x11, x6, 600, x1) - -inst_92: -// rs1_val == -576460752303423489, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x800000000000001; op2val:0x0 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x800000000000001, 0x0, x6, 608, x1) - -inst_93: -// rs1_val == -1152921504606846977, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x1000000000000001; op2val:0x0 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x1000000000000001, 0x0, x6, 616, x1) - -inst_94: -// rs1_val == -2305843009213693953, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x2000000000000001; op2val:0x1d -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x2000000000000001, 0x1d, x6, 624, x1) - -inst_95: -// rs1_val == -4611686018427387905, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x4000000000000001; op2val:0x7 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x4000000000000001, 0x7, x6, 632, x1) - -inst_96: -// rs1_val == 6148914691236517205, rs1_val==6148914691236517205 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x5555555555555555; op2val:0x7 -TEST_RR_OP(sraw, x12, x10, x11, 0xaaaaaa, 0x5555555555555555, 0x7, x6, 640, x1) - -inst_97: -// rs1_val == -6148914691236517206, rs1_val==-6148914691236517206 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x5555555555555556; op2val:0x9 -TEST_RR_OP(sraw, x12, x10, x11, -0x2aaaab, -0x5555555555555556, 0x9, x6, 648, x1) - -inst_98: -// rs1_val==3, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x3; op2val:0x12 -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x3, 0x12, x6, 656, x1) - -inst_99: -// rs1_val==5, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x5; op2val:0x1 -TEST_RR_OP(sraw, x12, x10, x11, 0x2, 0x5, 0x1, x6, 664, x1) - -inst_100: -// rs1_val==3689348814741910323, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x3333333333333333; op2val:0x1d -TEST_RR_OP(sraw, x12, x10, x11, 0x1, 0x3333333333333333, 0x1d, x6, 672, x1) - -inst_101: -// rs1_val==7378697629483820646, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x6666666666666666; op2val:0x3 -TEST_RR_OP(sraw, x12, x10, x11, 0xccccccc, 0x6666666666666666, 0x3, x6, 680, x1) - -inst_102: -// rs1_val==-3037000499, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0xb504f333; op2val:0x13 -TEST_RR_OP(sraw, x12, x10, x11, 0x95f, -0xb504f333, 0x13, x6, 688, x1) - -inst_103: -// rs1_val==3037000499, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0xb504f333; op2val:0xc -TEST_RR_OP(sraw, x12, x10, x11, -0x4afb1, 0xb504f333, 0xc, x6, 696, x1) - -inst_104: -// rs1_val==6148914691236517204, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x5555555555555554; op2val:0x1e -TEST_RR_OP(sraw, x12, x10, x11, 0x1, 0x5555555555555554, 0x1e, x6, 704, x1) - -inst_105: -// rs1_val==3689348814741910322, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x3333333333333332; op2val:0x9 -TEST_RR_OP(sraw, x12, x10, x11, 0x199999, 0x3333333333333332, 0x9, x6, 712, x1) - -inst_106: -// rs1_val==7378697629483820645, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x6666666666666665; op2val:0x2 -TEST_RR_OP(sraw, x12, x10, x11, 0x19999999, 0x6666666666666665, 0x2, x6, 720, x1) - -inst_107: -// rs1_val==3037000498, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0xb504f332; op2val:0x15 -TEST_RR_OP(sraw, x12, x10, x11, -0x258, 0xb504f332, 0x15, x6, 728, x1) - -inst_108: -// rs1_val==6148914691236517206, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x5555555555555556; op2val:0x1e -TEST_RR_OP(sraw, x12, x10, x11, 0x1, 0x5555555555555556, 0x1e, x6, 736, x1) - -inst_109: -// rs1_val==-6148914691236517205, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x5555555555555555; op2val:0xe -TEST_RR_OP(sraw, x12, x10, x11, -0x15556, -0x5555555555555555, 0xe, x6, 744, x1) - -inst_110: -// rs1_val==6, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x6; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x6, 0xa, x6, 752, x1) - -inst_111: -// rs1_val==3689348814741910324, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x3333333333333334; op2val:0xe -TEST_RR_OP(sraw, x12, x10, x11, 0xcccc, 0x3333333333333334, 0xe, x6, 760, x1) - -inst_112: -// rs1_val==7378697629483820647, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x6666666666666667; op2val:0x11 -TEST_RR_OP(sraw, x12, x10, x11, 0x3333, 0x6666666666666667, 0x11, x6, 768, x1) - -inst_113: -// rs1_val==-3037000498, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0xb504f332; op2val:0x4 -TEST_RR_OP(sraw, x12, x10, x11, 0x4afb0cc, -0xb504f332, 0x4, x6, 776, x1) - -inst_114: -// rs1_val==3037000500, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0xb504f334; op2val:0x1d -TEST_RR_OP(sraw, x12, x10, x11, -0x3, 0xb504f334, 0x1d, x6, 784, x1) - -inst_115: -// rs1_val == -2097153, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x200001; op2val:0xf -TEST_RR_OP(sraw, x12, x10, x11, -0x41, -0x200001, 0xf, x6, 792, x1) - -inst_116: -// rs1_val == -4194305, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x400001; op2val:0xd -TEST_RR_OP(sraw, x12, x10, x11, -0x201, -0x400001, 0xd, x6, 800, x1) - -inst_117: -// rs1_val == -8388609, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x800001; op2val:0x1e -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x800001, 0x1e, x6, 808, x1) - -inst_118: -// rs1_val == -16777217, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001; op2val:0xe -TEST_RR_OP(sraw, x12, x10, x11, -0x401, -0x1000001, 0xe, x6, 816, x1) - -inst_119: -// rs1_val == -33554433, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001; op2val:0x5 -TEST_RR_OP(sraw, x12, x10, x11, -0x100001, -0x2000001, 0x5, x6, 824, x1) - -inst_120: -// rs1_val == -67108865, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001; op2val:0x8 -TEST_RR_OP(sraw, x12, x10, x11, -0x40001, -0x4000001, 0x8, x6, 832, x1) - -inst_121: -// rs1_val == -134217729, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001; op2val:0x7 -TEST_RR_OP(sraw, x12, x10, x11, -0x100001, -0x8000001, 0x7, x6, 840, x1) - -inst_122: -// rs1_val == -268435457, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001; op2val:0xb -TEST_RR_OP(sraw, x12, x10, x11, -0x20001, -0x10000001, 0xb, x6, 848, x1) - -inst_123: -// rs1_val == -536870913, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001; op2val:0x11 -TEST_RR_OP(sraw, x12, x10, x11, -0x1001, -0x20000001, 0x11, x6, 856, x1) - -inst_124: -// rs1_val == -1073741825, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x40000001; op2val:0x6 -TEST_RR_OP(sraw, x12, x10, x11, -0x1000001, -0x40000001, 0x6, x6, 864, x1) - -inst_125: -// rs1_val == -2147483649, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x80000001; op2val:0xf -TEST_RR_OP(sraw, x12, x10, x11, 0xffff, -0x80000001, 0xf, x6, 872, x1) - -inst_126: -// rs1_val == -4294967297, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x100000001; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x100000001, 0x17, x6, 880, x1) - -inst_127: -// rs1_val == -8589934593, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x200000001; op2val:0x2 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x200000001, 0x2, x6, 888, x1) - -inst_128: -// rs1_val == -17179869185, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x400000001; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x400000001, 0x17, x6, 896, x1) - -inst_129: -// rs1_val == -34359738369, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x800000001; op2val:0x0 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x800000001, 0x0, x6, 904, x1) - -inst_130: -// rs1_val == -68719476737, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x1000000001; op2val:0x11 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x1000000001, 0x11, x6, 912, x1) - -inst_131: -// rs1_val == -137438953473, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x2000000001; op2val:0x1 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x2000000001, 0x1, x6, 920, x1) - -inst_132: -// rs1_val == -274877906945, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x4000000001; op2val:0x1f -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x4000000001, 0x1f, x6, 928, x1) - -inst_133: -// rs1_val == -549755813889, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x8000000001; op2val:0x6 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x8000000001, 0x6, x6, 936, x1) - -inst_134: -// rs1_val == -1099511627777, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x10000000001; op2val:0x1b -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x10000000001, 0x1b, x6, 944, x1) - -inst_135: -// rs1_val == -2199023255553, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x20000000001; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x20000000001, 0xa, x6, 952, x1) - -inst_136: -// rs1_val == -4398046511105, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x40000000001; op2val:0x2 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x40000000001, 0x2, x6, 960, x1) - -inst_137: -// rs1_val == -8796093022209, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000001; op2val:0x8 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x80000000001, 0x8, x6, 968, x1) - -inst_138: -// rs1_val == -17592186044417, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x100000000001; op2val:0xd -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x100000000001, 0xd, x6, 976, x1) - -inst_139: -// rs1_val == -35184372088833, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x200000000001; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x200000000001, 0xa, x6, 984, x1) - -inst_140: -// rs1_val == -70368744177665, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x400000000001; op2val:0x17 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x400000000001, 0x17, x6, 992, x1) - -inst_141: -// rs1_val == -140737488355329, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x800000000001; op2val:0x12 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x800000000001, 0x12, x6, 1000, x1) - -inst_142: -// rs1_val == -281474976710657, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x1000000000001; op2val:0x9 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x1000000000001, 0x9, x6, 1008, x1) - -inst_143: -// rs1_val == -562949953421313, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x2000000000001; op2val:0x13 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x2000000000001, 0x13, x6, 1016, x1) - -inst_144: -// rs1_val == -1125899906842625, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x4000000000001; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x4000000000001, 0xa, x6, 1024, x1) - -inst_145: -// rs1_val == -2251799813685249, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x8000000000001; op2val:0x1 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x8000000000001, 0x1, x6, 1032, x1) - -inst_146: -// rs1_val == -4503599627370497, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x10000000000001; op2val:0x2 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x10000000000001, 0x2, x6, 1040, x1) - -inst_147: -// rs1_val == -9007199254740993, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x20000000000001; op2val:0x1f -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x20000000000001, 0x1f, x6, 1048, x1) - -inst_148: -// rs1_val == -18014398509481985, -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x40000000000001; op2val:0x4 -TEST_RR_OP(sraw, x12, x10, x11, -0x1, -0x40000000000001, 0x4, x6, 1056, x1) - -inst_149: -// rs1_val < 0 and rs2_val > 0 and rs2_val < xlen, rs1_val == -257, rs2_val == 1 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x101; op2val:0x1 -TEST_RR_OP(sraw, x12, x10, x11, -0x81, -0x101, 0x1, x6, 1064, x1) - -inst_150: -// rs1_val < 0 and rs2_val == 0, rs1_val == -131073 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x20001; op2val:0x0 -TEST_RR_OP(sraw, x12, x10, x11, -0x20001, -0x20001, 0x0, x6, 1072, x1) - -inst_151: -// rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen, rs1_val == -9223372036854775808 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:-0x8000000000000000; op2val:0xe -TEST_RR_OP(sraw, x12, x10, x11, 0x0, -0x8000000000000000, 0xe, x6, 1080, x1) - -inst_152: -// rs1_val == 2, rs1_val==2, rs2_val == 10 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x2; op2val:0xa -TEST_RR_OP(sraw, x12, x10, x11, 0x0, 0x2, 0xa, x6, 1088, x1) - -inst_153: -// rs1_val == 16384, rs2_val == 2 -// opcode: sraw ; op1:x10; op2:x11; dest:x12; op1val:0x4000; op2val:0x2 -TEST_RR_OP(sraw, x12, x10, x11, 0x1000, 0x4000, 0x2, x6, 1096, x1) +// rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen, +// opcode: sraw ; op1:x30; op2:x29; dest:x31; op1val:-0x8000000000000000; op2val:0x1f +TEST_RR_OP(sraw, x31, x30, x29, 0x0, -0x8000000000000000, 0x1f, x8, 10*XLEN/8, x9) #endif @@ -809,50 +221,50 @@ RVMODEL_HALT RVTEST_DATA_BEGIN .align 4 - rvtest_data: .word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab RVTEST_DATA_END - RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: CANARY; -signature_x3_0: - .fill 0*(XLEN/32),4,0xdeadbeef +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef -signature_x3_1: - .fill 16*(XLEN/32),4,0xdeadbeef +signature_x1_1: + .fill 25*((XLEN/8)/4),4,0xdeadbeef -signature_x6_0: - .fill 138*(XLEN/32),4,0xdeadbeef -#ifdef rvtest_mtrap_routine +signature_x8_0: + .fill 11*((XLEN/8)/4),4,0xdeadbeef +#ifdef rvtest_mtrap_routine tsig_begin_canary: CANARY; + mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef + .fill 64*XLEN/32,4,0xdeadbeef + tsig_end_canary: CANARY; - #endif #ifdef rvtest_gpr_save gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef + .fill 32*XLEN/32,4,0xdeadbeef #endif + sig_end_canary: CANARY; rvtest_sig_end: From d71c2aab34ec919d8e33e91cf25226e52c004482 Mon Sep 17 00:00:00 2001 From: MingZhu Yan <69898423+trdthg@users.noreply.github.com> Date: Tue, 31 Dec 2024 18:20:39 +0800 Subject: [PATCH 09/10] Update sra test cases (#564) The sra testcases were very old with a covarage of 98.20% (109/111), this patch regenerate the cases with riscv_ctg (without `-r`), making covarage to 100%. Co-authored-by: Umer Shahid --- riscv-test-suite/rv64i_m/I/src/sra-01.S | 857 ++++-------------------- 1 file changed, 137 insertions(+), 720 deletions(-) diff --git a/riscv-test-suite/rv64i_m/I/src/sra-01.S b/riscv-test-suite/rv64i_m/I/src/sra-01.S index 00bc7b446..a40803ed3 100644 --- a/riscv-test-suite/rv64i_m/I/src/sra-01.S +++ b/riscv-test-suite/rv64i_m/I/src/sra-01.S @@ -1,11 +1,13 @@ // ----------- -// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg) -// version : 0.4.1 -// timestamp : Wed Dec 16 03:45:17 2020 GMT +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Mon Nov 18 08:18:47 2024 GMT // usage : riscv_ctg \ -// -- cgf ('/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/dataset.cgf', '/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/rv64i.cgf') \ -// -- xlen 64 \ +// -- cgf // --cgf /workspaces/riscv-arch-test/coverage/dataset.cgf \ +// --cgf /workspaces/riscv-arch-test/coverage/i/rv64i.cgf \ + \ +// -- xlen 64 \ // ----------- // // ----------- @@ -13,7 +15,7 @@ // SPDX-License-Identifier: BSD-3-Clause // ----------- // -// This assembly file tests the sra instruction of the RISC-V i extension for the sra covergroup. +// This assembly file tests the sra instruction of the RISC-V RV64 extension for the sra covergroup. // #include "model_test.h" #include "arch_test.h" @@ -27,780 +29,195 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sra) +RVTEST_CASE(0,"//check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sra) -RVTEST_SIGBASE( x9,signature_x9_1) +RVTEST_SIGBASE(x1,signature_x1_1) inst_0: -// rs1 == rs2 != rd, rs1==x23, rs2==x23, rd==x7, rs1_val < 0 and rs2_val > 0 and rs2_val < xlen, rs1_val == -34359738369 -// opcode: sra ; op1:x23; op2:x23; dest:x7; op1val:-0x800000001; op2val:-0x800000001 -TEST_RR_OP(sra, x7, x23, x23, -0x1, -0x800000001, -0x800000001, x9, 0, x10) +// rs1 == rs2 != rd, rs1==x30, rs2==x30, rd==x31, rs1_val < 0 and rs2_val == 0, +// opcode: sra ; op1:x30; op2:x30; dest:x31; op1val:-0xb504f332; op2val:-0xb504f332 +TEST_RR_OP(sra, x31, x30, x30, -0x2d414, -0xb504f332, -0xb504f332, x1, 0*XLEN/8, x2) inst_1: -// rs2 == rd != rs1, rs1==x15, rs2==x3, rd==x3, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen, rs1_val == 4294967296 -// opcode: sra ; op1:x15; op2:x3; dest:x3; op1val:0x100000000; op2val:0x3 -TEST_RR_OP(sra, x3, x15, x3, 0x20000000, 0x100000000, 0x3, x9, 8, x10) +// rs1 == rs2 == rd, rs1==x29, rs2==x29, rd==x29, rs1_val < 0 and rs2_val > 0 and rs2_val < xlen, +// opcode: sra ; op1:x29; op2:x29; dest:x29; op1val:-0xb504f332; op2val:-0xb504f332 +TEST_RR_OP(sra, x29, x29, x29, -0x2d414, -0xb504f332, -0xb504f332, x1, 1*XLEN/8, x2) inst_2: -// rs1 == rs2 == rd, rs1==x4, rs2==x4, rd==x4, rs1_val < 0 and rs2_val == 0, rs1_val == -4294967297 -// opcode: sra ; op1:x4; op2:x4; dest:x4; op1val:-0x100000001; op2val:-0x100000001 -TEST_RR_OP(sra, x4, x4, x4, -0x1, -0x100000001, -0x100000001, x9, 16, x10) +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x31, rs2==x28, rd==x30, rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen, +// opcode: sra ; op1:x31; op2:x28; dest:x30; op1val:-0x8000000000000000; op2val:0x3f +TEST_RR_OP(sra, x30, x31, x28, -0x1, -0x8000000000000000, 0x3f, x1, 2*XLEN/8, x2) inst_3: -// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==x27, rs2==x24, rd==x30, rs1_val > 0 and rs2_val == 0, rs1_val==3689348814741910323 -// opcode: sra ; op1:x27; op2:x24; dest:x30; op1val:0x3333333333333333; op2val:0x0 -TEST_RR_OP(sra, x30, x27, x24, 0x3333333333333333, 0x3333333333333333, 0x0, x9, 24, x10) +// rs2 == rd != rs1, rs1==x28, rs2==x27, rd==x27, rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen +// opcode: sra ; op1:x28; op2:x27; dest:x27; op1val:0x7fffffffffffffff; op2val:0x3f +TEST_RR_OP(sra, x27, x28, x27, 0x0, 0x7fffffffffffffff, 0x3f, x1, 3*XLEN/8, x2) inst_4: -// rs1 == rd != rs2, rs1==x20, rs2==x18, rd==x20, rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen, rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen, rs1_val == 1, rs2_val == 1 -// opcode: sra ; op1:x20; op2:x18; dest:x20; op1val:0x1; op2val:0x1 -TEST_RR_OP(sra, x20, x20, x18, 0x0, 0x1, 0x1, x9, 32, x10) +// rs1 == rd != rs2, rs1==x26, rs2==x31, rd==x26, rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen, +// opcode: sra ; op1:x26; op2:x31; dest:x26; op1val:0x0; op2val:0x3f +TEST_RR_OP(sra, x26, x26, x31, 0x0, 0x0, 0x3f, x1, 4*XLEN/8, x2) inst_5: -// rs1==x2, rs2==x15, rd==x24, rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen, rs1_val == -9223372036854775808, rs2_val == 2 -// opcode: sra ; op1:x2; op2:x15; dest:x24; op1val:-0x8000000000000000; op2val:0x2 -TEST_RR_OP(sra, x24, x2, x15, -0x2000000000000000, -0x8000000000000000, 0x2, x9, 40, x10) +// rs1==x27, rs2==x26, rd==x28, rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen, +// opcode: sra ; op1:x27; op2:x26; dest:x28; op1val:0x1; op2val:0x3f +TEST_RR_OP(sra, x28, x27, x26, 0x0, 0x1, 0x3f, x1, 5*XLEN/8, x2) inst_6: -// rs1==x13, rs2==x8, rd==x26, rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen, rs1_val==0 -// opcode: sra ; op1:x13; op2:x8; dest:x26; op1val:0x0; op2val:0xe -TEST_RR_OP(sra, x26, x13, x8, 0x0, 0x0, 0xe, x9, 48, x10) +// rs1==x24, rs2==x23, rd==x25, rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen, +// opcode: sra ; op1:x24; op2:x23; dest:x25; op1val:0x20; op2val:0x20 +TEST_RR_OP(sra, x25, x24, x23, 0x0, 0x20, 0x20, x1, 6*XLEN/8, x2) inst_7: -// rs1==x14, rs2==x0, rd==x28, rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen, rs1_val == 9223372036854775807 -// opcode: sra ; op1:x14; op2:x0; dest:x28; op1val:0x7fffffffffffffff; op2val:0x0 -TEST_RR_OP(sra, x28, x14, x0, 0x7fffffffffffffff, 0x7fffffffffffffff, 0x0, x9, 56, x10) +// rs1==x23, rs2==x25, rd==x24, rs1_val > 0 and rs2_val == 0, +// opcode: sra ; op1:x23; op2:x25; dest:x24; op1val:0xb504f334; op2val:0x0 +TEST_RR_OP(sra, x24, x23, x25, 0xb504f334, 0xb504f334, 0x0, x1, 7*XLEN/8, x2) inst_8: -// rs1==x25, rs2==x22, rd==x6, rs1_val == 2, rs1_val==2 -// opcode: sra ; op1:x25; op2:x22; dest:x6; op1val:0x2; op2val:0xa -TEST_RR_OP(sra, x6, x25, x22, 0x0, 0x2, 0xa, x9, 64, x10) +// rs1==x25, rs2==x24, rd==x23, +// opcode: sra ; op1:x25; op2:x24; dest:x23; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x23, x25, x24, 0x0, 0x0, 0x0, x1, 8*XLEN/8, x2) inst_9: -// rs1==x29, rs2==x12, rd==x18, rs1_val == 4, rs1_val==4 -// opcode: sra ; op1:x29; op2:x12; dest:x18; op1val:0x4; op2val:0x7 -TEST_RR_OP(sra, x18, x29, x12, 0x0, 0x4, 0x7, x9, 72, x10) +// rs1==x21, rs2==x20, rd==x22, +// opcode: sra ; op1:x21; op2:x20; dest:x22; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x22, x21, x20, 0x0, 0x0, 0x0, x1, 9*XLEN/8, x2) inst_10: -// rs1==x3, rs2==x28, rd==x11, rs1_val == 8, -// opcode: sra ; op1:x3; op2:x28; dest:x11; op1val:0x8; op2val:0xa -TEST_RR_OP(sra, x11, x3, x28, 0x0, 0x8, 0xa, x9, 80, x10) +// rs1==x20, rs2==x22, rd==x21, +// opcode: sra ; op1:x20; op2:x22; dest:x21; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x21, x20, x22, 0x0, 0x0, 0x0, x1, 10*XLEN/8, x2) inst_11: -// rs1==x0, rs2==x16, rd==x8, rs1_val == 16, -// opcode: sra ; op1:x0; op2:x16; dest:x8; op1val:0x0; op2val:0x6 -TEST_RR_OP(sra, x8, x0, x16, 0x0, 0x0, 0x6, x9, 88, x10) +// rs1==x22, rs2==x21, rd==x20, +// opcode: sra ; op1:x22; op2:x21; dest:x20; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x20, x22, x21, 0x0, 0x0, 0x0, x1, 11*XLEN/8, x2) inst_12: -// rs1==x24, rs2==x5, rd==x12, rs1_val == 32, -// opcode: sra ; op1:x24; op2:x5; dest:x12; op1val:0x20; op2val:0x1 -TEST_RR_OP(sra, x12, x24, x5, 0x10, 0x20, 0x1, x9, 96, x10) +// rs1==x18, rs2==x17, rd==x19, +// opcode: sra ; op1:x18; op2:x17; dest:x19; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x19, x18, x17, 0x0, 0x0, 0x0, x1, 12*XLEN/8, x2) inst_13: -// rs1==x31, rs2==x21, rd==x2, rs1_val == 64, rs2_val == 8 -// opcode: sra ; op1:x31; op2:x21; dest:x2; op1val:0x40; op2val:0x8 -TEST_RR_OP(sra, x2, x31, x21, 0x0, 0x40, 0x8, x9, 104, x10) +// rs1==x17, rs2==x19, rd==x18, +// opcode: sra ; op1:x17; op2:x19; dest:x18; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x18, x17, x19, 0x0, 0x0, 0x0, x1, 13*XLEN/8, x2) inst_14: -// rs1==x8, rs2==x1, rd==x21, rs1_val == 128, -// opcode: sra ; op1:x8; op2:x1; dest:x21; op1val:0x80; op2val:0xe -TEST_RR_OP(sra, x21, x8, x1, 0x0, 0x80, 0xe, x9, 112, x10) +// rs1==x19, rs2==x18, rd==x17, +// opcode: sra ; op1:x19; op2:x18; dest:x17; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x17, x19, x18, 0x0, 0x0, 0x0, x1, 14*XLEN/8, x2) inst_15: -// rs1==x1, rs2==x30, rd==x14, rs1_val == 256, -// opcode: sra ; op1:x1; op2:x30; dest:x14; op1val:0x100; op2val:0x3 -TEST_RR_OP(sra, x14, x1, x30, 0x20, 0x100, 0x3, x9, 120, x4) +// rs1==x15, rs2==x14, rd==x16, +// opcode: sra ; op1:x15; op2:x14; dest:x16; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x16, x15, x14, 0x0, 0x0, 0x0, x1, 15*XLEN/8, x2) inst_16: -// rs1==x16, rs2==x10, rd==x0, rs1_val == 512, -// opcode: sra ; op1:x16; op2:x10; dest:x0; op1val:0x200; op2val:0xb -TEST_RR_OP(sra, x0, x16, x10, 0, 0x200, 0xb, x9, 128, x4) -RVTEST_SIGBASE( x3,signature_x3_0) +// rs1==x14, rs2==x16, rd==x15, +// opcode: sra ; op1:x14; op2:x16; dest:x15; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x15, x14, x16, 0x0, 0x0, 0x0, x1, 16*XLEN/8, x2) inst_17: -// rs1==x26, rs2==x29, rd==x10, rs1_val == 1024, -// opcode: sra ; op1:x26; op2:x29; dest:x10; op1val:0x400; op2val:0xe -TEST_RR_OP(sra, x10, x26, x29, 0x0, 0x400, 0xe, x3, 0, x4) +// rs1==x16, rs2==x15, rd==x14, +// opcode: sra ; op1:x16; op2:x15; dest:x14; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x14, x16, x15, 0x0, 0x0, 0x0, x1, 17*XLEN/8, x2) inst_18: -// rs1==x9, rs2==x27, rd==x31, rs1_val == 2048, rs2_val == 42 -// opcode: sra ; op1:x9; op2:x27; dest:x31; op1val:0x800; op2val:0x2a -TEST_RR_OP(sra, x31, x9, x27, 0x0, 0x800, 0x2a, x3, 8, x4) +// rs1==x12, rs2==x11, rd==x13, +// opcode: sra ; op1:x12; op2:x11; dest:x13; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x13, x12, x11, 0x0, 0x0, 0x0, x1, 18*XLEN/8, x2) inst_19: -// rs1==x22, rs2==x19, rd==x1, rs1_val == 4096, rs2_val == 4 -// opcode: sra ; op1:x22; op2:x19; dest:x1; op1val:0x1000; op2val:0x4 -TEST_RR_OP(sra, x1, x22, x19, 0x100, 0x1000, 0x4, x3, 16, x4) +// rs1==x11, rs2==x13, rd==x12, +// opcode: sra ; op1:x11; op2:x13; dest:x12; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x12, x11, x13, 0x0, 0x0, 0x0, x1, 19*XLEN/8, x2) inst_20: -// rs1==x17, rs2==x13, rd==x9, rs1_val == 8192, -// opcode: sra ; op1:x17; op2:x13; dest:x9; op1val:0x2000; op2val:0x9 -TEST_RR_OP(sra, x9, x17, x13, 0x10, 0x2000, 0x9, x3, 24, x4) +// rs1==x13, rs2==x12, rd==x11, +// opcode: sra ; op1:x13; op2:x12; dest:x11; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x11, x13, x12, 0x0, 0x0, 0x0, x1, 20*XLEN/8, x2) inst_21: -// rs1==x18, rs2==x7, rd==x13, rs1_val == 16384, rs2_val == 31 -// opcode: sra ; op1:x18; op2:x7; dest:x13; op1val:0x4000; op2val:0x1f -TEST_RR_OP(sra, x13, x18, x7, 0x0, 0x4000, 0x1f, x3, 32, x4) +// rs1==x9, rs2==x8, rd==x10, +// opcode: sra ; op1:x9; op2:x8; dest:x10; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x10, x9, x8, 0x0, 0x0, 0x0, x1, 21*XLEN/8, x2) inst_22: -// rs1==x7, rs2==x31, rd==x19, rs1_val == 32768, -// opcode: sra ; op1:x7; op2:x31; dest:x19; op1val:0x8000; op2val:0x9 -TEST_RR_OP(sra, x19, x7, x31, 0x40, 0x8000, 0x9, x3, 40, x4) +// rs1==x8, rs2==x10, rd==x9, +// opcode: sra ; op1:x8; op2:x10; dest:x9; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x9, x8, x10, 0x0, 0x0, 0x0, x1, 22*XLEN/8, x2) inst_23: -// rs1==x21, rs2==x26, rd==x23, rs1_val == 65536, -// opcode: sra ; op1:x21; op2:x26; dest:x23; op1val:0x10000; op2val:0x3 -TEST_RR_OP(sra, x23, x21, x26, 0x2000, 0x10000, 0x3, x3, 48, x4) +// rs1==x10, rs2==x9, rd==x8, +// opcode: sra ; op1:x10; op2:x9; dest:x8; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x8, x10, x9, 0x0, 0x0, 0x0, x1, 23*XLEN/8, x2) inst_24: -// rs1==x10, rs2==x11, rd==x29, rs1_val == 131072, -// opcode: sra ; op1:x10; op2:x11; dest:x29; op1val:0x20000; op2val:0x3 -TEST_RR_OP(sra, x29, x10, x11, 0x4000, 0x20000, 0x3, x3, 56, x4) +// rs1==x6, rs2==x5, rd==x7, +// opcode: sra ; op1:x6; op2:x5; dest:x7; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x7, x6, x5, 0x0, 0x0, 0x0, x1, 24*XLEN/8, x2) +RVTEST_SIGBASE(x8,signature_x8_0) inst_25: -// rs1==x19, rs2==x2, rd==x27, rs1_val == 262144, -// opcode: sra ; op1:x19; op2:x2; dest:x27; op1val:0x40000; op2val:0x8 -TEST_RR_OP(sra, x27, x19, x2, 0x400, 0x40000, 0x8, x3, 64, x4) +// rs1==x5, rs2==x7, rd==x6, +// opcode: sra ; op1:x5; op2:x7; dest:x6; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x6, x5, x7, 0x0, 0x0, 0x0, x8, 0*XLEN/8, x9) inst_26: -// rs1==x12, rs2==x6, rd==x17, rs1_val == 524288, -// opcode: sra ; op1:x12; op2:x6; dest:x17; op1val:0x80000; op2val:0x7 -TEST_RR_OP(sra, x17, x12, x6, 0x1000, 0x80000, 0x7, x3, 72, x4) +// rs1==x7, rs2==x6, rd==x5, +// opcode: sra ; op1:x7; op2:x6; dest:x5; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x5, x7, x6, 0x0, 0x0, 0x0, x8, 1*XLEN/8, x9) inst_27: -// rs1==x5, rs2==x14, rd==x22, rs1_val == 1048576, rs2_val == 32 -// opcode: sra ; op1:x5; op2:x14; dest:x22; op1val:0x100000; op2val:0x20 -TEST_RR_OP(sra, x22, x5, x14, 0x0, 0x100000, 0x20, x3, 80, x4) +// rs1==x3, rs2==x2, rd==x4, +// opcode: sra ; op1:x3; op2:x2; dest:x4; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x4, x3, x2, 0x0, 0x0, 0x0, x8, 2*XLEN/8, x9) inst_28: -// rs1==x6, rs2==x9, rd==x16, rs1_val == 2097152, -// opcode: sra ; op1:x6; op2:x9; dest:x16; op1val:0x200000; op2val:0x4 -TEST_RR_OP(sra, x16, x6, x9, 0x20000, 0x200000, 0x4, x3, 88, x4) +// rs1==x2, rs2==x4, rd==x3, +// opcode: sra ; op1:x2; op2:x4; dest:x3; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x3, x2, x4, 0x0, 0x0, 0x0, x8, 3*XLEN/8, x9) inst_29: -// rs1==x30, rs2==x25, rd==x5, rs1_val == 4194304, -// opcode: sra ; op1:x30; op2:x25; dest:x5; op1val:0x400000; op2val:0x2a -TEST_RR_OP(sra, x5, x30, x25, 0x0, 0x400000, 0x2a, x3, 96, x4) +// rs1==x4, rs2==x3, rd==x2, +// opcode: sra ; op1:x4; op2:x3; dest:x2; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x2, x4, x3, 0x0, 0x0, 0x0, x8, 4*XLEN/8, x9) inst_30: -// rs1==x28, rs2==x20, rd==x15, rs1_val == 8388608, rs2_val == 21 -// opcode: sra ; op1:x28; op2:x20; dest:x15; op1val:0x800000; op2val:0x15 -TEST_RR_OP(sra, x15, x28, x20, 0x4, 0x800000, 0x15, x3, 104, x4) +// rs1==x1, +// opcode: sra ; op1:x1; op2:x30; dest:x31; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x31, x1, x30, 0x0, 0x0, 0x0, x8, 5*XLEN/8, x9) inst_31: -// rs1==x11, rs2==x17, rd==x25, rs1_val == 16777216, -// opcode: sra ; op1:x11; op2:x17; dest:x25; op1val:0x1000000; op2val:0x15 -TEST_RR_OP(sra, x25, x11, x17, 0x8, 0x1000000, 0x15, x3, 112, x1) +// rs1==x0, +// opcode: sra ; op1:x0; op2:x30; dest:x31; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x31, x0, x30, 0x0, 0x0, 0x0, x8, 6*XLEN/8, x9) inst_32: -// rs1_val == 33554432, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2000000; op2val:0x1f -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x2000000, 0x1f, x3, 120, x1) +// rs2==x1, +// opcode: sra ; op1:x30; op2:x1; dest:x31; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x31, x30, x1, 0x0, 0x0, 0x0, x8, 7*XLEN/8, x9) inst_33: -// rs1_val == 67108864, rs2_val == 16 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4000000; op2val:0x10 -TEST_RR_OP(sra, x12, x10, x11, 0x400, 0x4000000, 0x10, x3, 128, x1) +// rs2==x0, +// opcode: sra ; op1:x30; op2:x0; dest:x31; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x31, x30, x0, 0x0, 0x0, 0x0, x8, 8*XLEN/8, x9) inst_34: -// rs1_val == 134217728, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x8000000; op2val:0x2 -TEST_RR_OP(sra, x12, x10, x11, 0x2000000, 0x8000000, 0x2, x3, 136, x1) +// rd==x1, +// opcode: sra ; op1:x31; op2:x30; dest:x1; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x1, x31, x30, 0x0, 0x0, 0x0, x8, 9*XLEN/8, x9) inst_35: -// rs1_val == 268435456, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10000000; op2val:0xd -TEST_RR_OP(sra, x12, x10, x11, 0x8000, 0x10000000, 0xd, x3, 144, x1) +// rd==x0, +// opcode: sra ; op1:x31; op2:x30; dest:x0; op1val:0x0; op2val:0x0 +TEST_RR_OP(sra, x0, x31, x30, 0, 0x0, 0x0, x8, 10*XLEN/8, x9) inst_36: -// rs1_val == 536870912, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x20000000; op2val:0x3 -TEST_RR_OP(sra, x12, x10, x11, 0x4000000, 0x20000000, 0x3, x3, 152, x1) - -inst_37: -// rs1_val == 1073741824, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x40000000; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, 0x40000, 0x40000000, 0xc, x3, 160, x1) - -inst_38: -// rs1_val == 2147483648, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x80000000; op2val:0xb -TEST_RR_OP(sra, x12, x10, x11, 0x100000, 0x80000000, 0xb, x3, 168, x1) - -inst_39: -// rs1_val == 8589934592, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x200000000; op2val:0xa -TEST_RR_OP(sra, x12, x10, x11, 0x800000, 0x200000000, 0xa, x3, 176, x1) - -inst_40: -// rs1_val == 17179869184, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x400000000; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, 0x100000, 0x400000000, 0xe, x3, 184, x1) - -inst_41: -// rs1_val == 34359738368, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x800000000; op2val:0xf -TEST_RR_OP(sra, x12, x10, x11, 0x100000, 0x800000000, 0xf, x3, 192, x1) - -inst_42: -// rs1_val == 68719476736, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x1000000000; op2val:0x20 -TEST_RR_OP(sra, x12, x10, x11, 0x10, 0x1000000000, 0x20, x3, 200, x1) - -inst_43: -// rs1_val == 137438953472, rs2_val == 47 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000; op2val:0x2f -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x2000000000, 0x2f, x3, 208, x1) - -inst_44: -// rs1_val == 274877906944, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000; op2val:0x2a -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x4000000000, 0x2a, x3, 216, x1) - -inst_45: -// rs1_val == 549755813888, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000; op2val:0x10 -TEST_RR_OP(sra, x12, x10, x11, 0x800000, 0x8000000000, 0x10, x3, 224, x1) - -inst_46: -// rs1_val == 1099511627776, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10000000000; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, 0x10000000, 0x10000000000, 0xc, x3, 232, x1) - -inst_47: -// rs1_val == 2199023255552, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x20000000000; op2val:0x2a -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x20000000000, 0x2a, x3, 240, x1) - -inst_48: -// rs1_val == 4398046511104, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x40000000000; op2val:0x5 -TEST_RR_OP(sra, x12, x10, x11, 0x2000000000, 0x40000000000, 0x5, x3, 248, x1) - -inst_49: -// rs1_val == 8796093022208, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x80000000000; op2val:0x8 -TEST_RR_OP(sra, x12, x10, x11, 0x800000000, 0x80000000000, 0x8, x3, 256, x1) - -inst_50: -// rs1_val == 17592186044416, rs2_val == 55 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x100000000000; op2val:0x37 -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x100000000000, 0x37, x3, 264, x1) - -inst_51: -// rs1_val == 35184372088832, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x200000000000; op2val:0x37 -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x200000000000, 0x37, x3, 272, x1) - -inst_52: -// rs1_val == 70368744177664, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x400000000000; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, 0x400000000, 0x400000000000, 0xc, x3, 280, x1) - -inst_53: -// rs1_val == 140737488355328, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x800000000000; op2val:0x2a -TEST_RR_OP(sra, x12, x10, x11, 0x20, 0x800000000000, 0x2a, x3, 288, x1) - -inst_54: -// rs1_val == 281474976710656, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x1000000000000; op2val:0x2a -TEST_RR_OP(sra, x12, x10, x11, 0x40, 0x1000000000000, 0x2a, x3, 296, x1) - -inst_55: -// rs1_val == 562949953421312, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, 0x800000000, 0x2000000000000, 0xe, x3, 304, x1) - -inst_56: -// rs1_val == 1125899906842624, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, 0x4000000000, 0x4000000000000, 0xc, x3, 312, x1) - -inst_57: -// rs1_val == 2251799813685248, rs2_val == 61 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000; op2val:0x3d -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x8000000000000, 0x3d, x3, 320, x1) - -inst_58: -// rs1_val == 4503599627370496, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10000000000000; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, 0x10000000000, 0x10000000000000, 0xc, x3, 328, x1) - -inst_59: -// rs1_val == 9007199254740992, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x20000000000000; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, 0x8000000000, 0x20000000000000, 0xe, x3, 336, x1) - -inst_60: -// rs1_val == 18014398509481984, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x40000000000000; op2val:0x3d -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x40000000000000, 0x3d, x3, 344, x1) - -inst_61: -// rs1_val == 36028797018963968, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x80000000000000; op2val:0x15 -TEST_RR_OP(sra, x12, x10, x11, 0x400000000, 0x80000000000000, 0x15, x3, 352, x1) - -inst_62: -// rs1_val == 72057594037927936, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x100000000000000; op2val:0x4 -TEST_RR_OP(sra, x12, x10, x11, 0x10000000000000, 0x100000000000000, 0x4, x3, 360, x1) - -inst_63: -// rs1_val == 144115188075855872, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x200000000000000; op2val:0x1 -TEST_RR_OP(sra, x12, x10, x11, 0x100000000000000, 0x200000000000000, 0x1, x3, 368, x1) - -inst_64: -// rs1_val == 288230376151711744, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x400000000000000; op2val:0x3d -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x400000000000000, 0x3d, x3, 376, x1) - -inst_65: -// rs1_val == 576460752303423488, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x800000000000000; op2val:0x3 -TEST_RR_OP(sra, x12, x10, x11, 0x100000000000000, 0x800000000000000, 0x3, x3, 384, x1) - -inst_66: -// rs1_val == 1152921504606846976, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x1000000000000000; op2val:0x10 -TEST_RR_OP(sra, x12, x10, x11, 0x100000000000, 0x1000000000000000, 0x10, x3, 392, x1) - -inst_67: -// rs1_val == 2305843009213693952, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000; op2val:0x2f -TEST_RR_OP(sra, x12, x10, x11, 0x4000, 0x2000000000000000, 0x2f, x3, 400, x1) - -inst_68: -// rs1_val == 4611686018427387904, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000; op2val:0x12 -TEST_RR_OP(sra, x12, x10, x11, 0x100000000000, 0x4000000000000000, 0x12, x3, 408, x1) - -inst_69: -// rs1_val == -2, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2; op2val:0x3d -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x2, 0x3d, x3, 416, x1) - -inst_70: -// rs1_val == -3, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x3; op2val:0x10 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x3, 0x10, x3, 424, x1) - -inst_71: -// rs1_val == -5, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x5; op2val:0x15 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x5, 0x15, x3, 432, x1) - -inst_72: -// rs1_val == -9, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x9; op2val:0x2 -TEST_RR_OP(sra, x12, x10, x11, -0x3, -0x9, 0x2, x3, 440, x1) - -inst_73: -// rs1_val == -17, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x11; op2val:0xa -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x11, 0xa, x3, 448, x1) - -inst_74: -// rs1_val == -33, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x21; op2val:0x20 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x21, 0x20, x3, 456, x1) - -inst_75: -// rs1_val == -65, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x41; op2val:0x0 -TEST_RR_OP(sra, x12, x10, x11, -0x41, -0x41, 0x0, x3, 464, x1) - -inst_76: -// rs1_val == -129, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x81; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0x2, -0x81, 0x7, x3, 472, x1) - -inst_77: -// rs1_val == -257, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x101; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0x3, -0x101, 0x7, x3, 480, x1) - -inst_78: -// rs1_val == -513, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x201; op2val:0x3f -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x201, 0x3f, x3, 488, x1) - -inst_79: -// rs1_val == -1025, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x401; op2val:0x37 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x401, 0x37, x3, 496, x1) - -inst_80: -// rs1_val == -2049, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x801; op2val:0x8 -TEST_RR_OP(sra, x12, x10, x11, -0x9, -0x801, 0x8, x3, 504, x1) - -inst_81: -// rs1_val == -4097, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x1001; op2val:0x8 -TEST_RR_OP(sra, x12, x10, x11, -0x11, -0x1001, 0x8, x3, 512, x1) - -inst_82: -// rs1_val == -8193, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2001; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0x41, -0x2001, 0x7, x3, 520, x1) - -inst_83: -// rs1_val == -16385, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x4001; op2val:0x3 -TEST_RR_OP(sra, x12, x10, x11, -0x801, -0x4001, 0x3, x3, 528, x1) - -inst_84: -// rs1_val == -32769, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x8001; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, -0x9, -0x8001, 0xc, x3, 536, x1) - -inst_85: -// rs1_val == -65537, rs2_val == 62 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x10001; op2val:0x3e -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x10001, 0x3e, x3, 544, x1) - -inst_86: -// rs1_val == -131073, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x20001; op2val:0x20 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x20001, 0x20, x3, 552, x1) - -inst_87: -// rs1_val == -262145, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x40001; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, -0x41, -0x40001, 0xc, x3, 560, x1) - -inst_88: -// rs1_val == -36028797018963969, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000000001; op2val:0x6 -TEST_RR_OP(sra, x12, x10, x11, -0x2000000000001, -0x80000000000001, 0x6, x3, 568, x1) - -inst_89: -// rs1_val == -72057594037927937, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x100000000000001; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, -0x40000000001, -0x100000000000001, 0xe, x3, 576, x1) - -inst_90: -// rs1_val == -144115188075855873, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x200000000000001; op2val:0x5 -TEST_RR_OP(sra, x12, x10, x11, -0x10000000000001, -0x200000000000001, 0x5, x3, 584, x1) - -inst_91: -// rs1_val == -288230376151711745, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x400000000000001; op2val:0x2 -TEST_RR_OP(sra, x12, x10, x11, -0x100000000000001, -0x400000000000001, 0x2, x3, 592, x1) - -inst_92: -// rs1_val == -576460752303423489, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x800000000000001; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0x10000000000001, -0x800000000000001, 0x7, x3, 600, x1) - -inst_93: -// rs1_val == -1152921504606846977, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x1000000000000001; op2val:0x4 -TEST_RR_OP(sra, x12, x10, x11, -0x100000000000001, -0x1000000000000001, 0x4, x3, 608, x1) - -inst_94: -// rs1_val == -2305843009213693953, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2000000000000001; op2val:0x3 -TEST_RR_OP(sra, x12, x10, x11, -0x400000000000001, -0x2000000000000001, 0x3, x3, 616, x1) - -inst_95: -// rs1_val == -4611686018427387905, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x4000000000000001; op2val:0x1 -TEST_RR_OP(sra, x12, x10, x11, -0x2000000000000001, -0x4000000000000001, 0x1, x3, 624, x1) - -inst_96: -// rs1_val == 6148914691236517205, rs1_val==6148914691236517205 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x5555555555555555; op2val:0x9 -TEST_RR_OP(sra, x12, x10, x11, 0x2aaaaaaaaaaaaa, 0x5555555555555555, 0x9, x3, 632, x1) - -inst_97: -// rs1_val == -6148914691236517206, rs1_val==-6148914691236517206 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x5555555555555556; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0xaaaaaaaaaaaaab, -0x5555555555555556, 0x7, x3, 640, x1) - -inst_98: -// rs1_val==3, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x3; op2val:0x1 -TEST_RR_OP(sra, x12, x10, x11, 0x1, 0x3, 0x1, x3, 648, x1) - -inst_99: -// rs1_val==5, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x5; op2val:0x20 -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x5, 0x20, x3, 656, x1) - -inst_100: -// rs1_val==7378697629483820646, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x6666666666666666; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, 0x6666666666666, 0x6666666666666666, 0xc, x3, 664, x1) - -inst_101: -// rs1_val==-3037000499, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0xb504f333; op2val:0xb -TEST_RR_OP(sra, x12, x10, x11, -0x16a09f, -0xb504f333, 0xb, x3, 672, x1) - -inst_102: -// rs1_val==3037000499, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0xb504f333; op2val:0x1f -TEST_RR_OP(sra, x12, x10, x11, 0x1, 0xb504f333, 0x1f, x3, 680, x1) - -inst_103: -// rs1_val==6148914691236517204, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x5555555555555554; op2val:0x37 -TEST_RR_OP(sra, x12, x10, x11, 0xaa, 0x5555555555555554, 0x37, x3, 688, x1) - -inst_104: -// rs1_val==3689348814741910322, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x3333333333333332; op2val:0x20 -TEST_RR_OP(sra, x12, x10, x11, 0x33333333, 0x3333333333333332, 0x20, x3, 696, x1) - -inst_105: -// rs1_val==7378697629483820645, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x6666666666666665; op2val:0x9 -TEST_RR_OP(sra, x12, x10, x11, 0x33333333333333, 0x6666666666666665, 0x9, x3, 704, x1) - -inst_106: -// rs1_val==3037000498, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0xb504f332; op2val:0x15 -TEST_RR_OP(sra, x12, x10, x11, 0x5a8, 0xb504f332, 0x15, x3, 712, x1) - -inst_107: -// rs1_val==6148914691236517206, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x5555555555555556; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, 0x1555555555555, 0x5555555555555556, 0xe, x3, 720, x1) - -inst_108: -// rs1_val==-6148914691236517205, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x5555555555555555; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, -0x1555555555556, -0x5555555555555555, 0xe, x3, 728, x1) - -inst_109: -// rs1_val==6, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x6; op2val:0x3e -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x6, 0x3e, x3, 736, x1) - -inst_110: -// rs1_val==3689348814741910324, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x3333333333333334; op2val:0x12 -TEST_RR_OP(sra, x12, x10, x11, 0xccccccccccc, 0x3333333333333334, 0x12, x3, 744, x1) - -inst_111: -// rs1_val==7378697629483820647, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x6666666666666667; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, 0x1999999999999, 0x6666666666666667, 0xe, x3, 752, x1) - -inst_112: -// rs1_val==-3037000498, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0xb504f332; op2val:0x11 -TEST_RR_OP(sra, x12, x10, x11, -0x5a83, -0xb504f332, 0x11, x3, 760, x1) - -inst_113: -// rs1_val==3037000500, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0xb504f334; op2val:0x2a -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0xb504f334, 0x2a, x3, 768, x1) - -inst_114: -// rs2_val == 59, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x800000000000001; op2val:0x3b -TEST_RR_OP(sra, x12, x10, x11, -0x2, -0x800000000000001, 0x3b, x3, 776, x1) - -inst_115: -// rs1_val == -524289, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x80001; op2val:0x20 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x80001, 0x20, x3, 784, x1) - -inst_116: -// rs1_val == -1048577, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x100001; op2val:0x11 -TEST_RR_OP(sra, x12, x10, x11, -0x9, -0x100001, 0x11, x3, 792, x1) - -inst_117: -// rs1_val == -2097153, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x200001; op2val:0x5 -TEST_RR_OP(sra, x12, x10, x11, -0x10001, -0x200001, 0x5, x3, 800, x1) - -inst_118: -// rs1_val == -4194305, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x400001; op2val:0x20 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x400001, 0x20, x3, 808, x1) - -inst_119: -// rs1_val == -8388609, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x800001; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, -0x801, -0x800001, 0xc, x3, 816, x1) - -inst_120: -// rs1_val == -16777217, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001; op2val:0xa -TEST_RR_OP(sra, x12, x10, x11, -0x4001, -0x1000001, 0xa, x3, 824, x1) - -inst_121: -// rs1_val == -33554433, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001; op2val:0xc -TEST_RR_OP(sra, x12, x10, x11, -0x2001, -0x2000001, 0xc, x3, 832, x1) - -inst_122: -// rs1_val == -67108865, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001; op2val:0x3 -TEST_RR_OP(sra, x12, x10, x11, -0x800001, -0x4000001, 0x3, x3, 840, x1) - -inst_123: -// rs1_val == -134217729, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001; op2val:0x3d -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x8000001, 0x3d, x3, 848, x1) - -inst_124: -// rs1_val == -268435457, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001; op2val:0x11 -TEST_RR_OP(sra, x12, x10, x11, -0x801, -0x10000001, 0x11, x3, 856, x1) - -inst_125: -// rs1_val == -536870913, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001; op2val:0x2f -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x20000001, 0x2f, x3, 864, x1) - -inst_126: -// rs1_val == -1073741825, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x40000001; op2val:0x9 -TEST_RR_OP(sra, x12, x10, x11, -0x200001, -0x40000001, 0x9, x3, 872, x1) - -inst_127: -// rs1_val == -2147483649, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x80000001; op2val:0xd -TEST_RR_OP(sra, x12, x10, x11, -0x40001, -0x80000001, 0xd, x3, 880, x1) - -inst_128: -// rs1_val == -8589934593, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x200000001; op2val:0xa -TEST_RR_OP(sra, x12, x10, x11, -0x800001, -0x200000001, 0xa, x3, 888, x1) - -inst_129: -// rs1_val == -17179869185, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x400000001; op2val:0x3b -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x400000001, 0x3b, x3, 896, x1) - -inst_130: -// rs1_val == -68719476737, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x1000000001; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, -0x400001, -0x1000000001, 0xe, x3, 904, x1) - -inst_131: -// rs1_val == -137438953473, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2000000001; op2val:0x2f -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x2000000001, 0x2f, x3, 912, x1) - -inst_132: -// rs1_val == -274877906945, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x4000000001; op2val:0xa -TEST_RR_OP(sra, x12, x10, x11, -0x10000001, -0x4000000001, 0xa, x3, 920, x1) - -inst_133: -// rs1_val == -549755813889, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x8000000001; op2val:0x37 -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x8000000001, 0x37, x3, 928, x1) - -inst_134: -// rs1_val == -1099511627777, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x10000000001; op2val:0x9 -TEST_RR_OP(sra, x12, x10, x11, -0x80000001, -0x10000000001, 0x9, x3, 936, x1) - -inst_135: -// rs1_val == -2199023255553, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x20000000001; op2val:0xd -TEST_RR_OP(sra, x12, x10, x11, -0x10000001, -0x20000000001, 0xd, x3, 944, x1) - -inst_136: -// rs1_val == -4398046511105, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x40000000001; op2val:0x1f -TEST_RR_OP(sra, x12, x10, x11, -0x801, -0x40000000001, 0x1f, x3, 952, x1) - -inst_137: -// rs1_val == -8796093022209, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000001; op2val:0x12 -TEST_RR_OP(sra, x12, x10, x11, -0x2000001, -0x80000000001, 0x12, x3, 960, x1) - -inst_138: -// rs1_val == -17592186044417, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x100000000001; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0x2000000001, -0x100000000001, 0x7, x3, 968, x1) - -inst_139: -// rs1_val == -35184372088833, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x200000000001; op2val:0x1 -TEST_RR_OP(sra, x12, x10, x11, -0x100000000001, -0x200000000001, 0x1, x3, 976, x1) - -inst_140: -// rs1_val == -70368744177665, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x400000000001; op2val:0xf -TEST_RR_OP(sra, x12, x10, x11, -0x80000001, -0x400000000001, 0xf, x3, 984, x1) - -inst_141: -// rs1_val == -140737488355329, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x800000000001; op2val:0xb -TEST_RR_OP(sra, x12, x10, x11, -0x1000000001, -0x800000000001, 0xb, x3, 992, x1) - -inst_142: -// rs1_val == -281474976710657, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x1000000000001; op2val:0x3 -TEST_RR_OP(sra, x12, x10, x11, -0x200000000001, -0x1000000000001, 0x3, x3, 1000, x1) - -inst_143: -// rs1_val == -562949953421313, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2000000000001; op2val:0x3f -TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x2000000000001, 0x3f, x3, 1008, x1) - -inst_144: -// rs1_val == -1125899906842625, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x4000000000001; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0x80000000001, -0x4000000000001, 0x7, x3, 1016, x1) - -inst_145: -// rs1_val == -2251799813685249, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x8000000000001; op2val:0x1 -TEST_RR_OP(sra, x12, x10, x11, -0x4000000000001, -0x8000000000001, 0x1, x3, 1024, x1) - -inst_146: -// rs1_val == -4503599627370497, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x10000000000001; op2val:0xf -TEST_RR_OP(sra, x12, x10, x11, -0x2000000001, -0x10000000000001, 0xf, x3, 1032, x1) - -inst_147: -// rs1_val == -9007199254740993, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x20000000000001; op2val:0xa -TEST_RR_OP(sra, x12, x10, x11, -0x80000000001, -0x20000000000001, 0xa, x3, 1040, x1) - -inst_148: -// rs1_val == -18014398509481985, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x40000000000001; op2val:0xe -TEST_RR_OP(sra, x12, x10, x11, -0x10000000001, -0x40000000000001, 0xe, x3, 1048, x1) - -inst_149: -// rs1_val < 0 and rs2_val > 0 and rs2_val < xlen, rs1_val == -34359738369 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x800000001; op2val:0x7 -TEST_RR_OP(sra, x12, x10, x11, -0x10000001, -0x800000001, 0x7, x3, 1056, x1) - -inst_150: -// rs1_val < 0 and rs2_val == 0, rs1_val == -4294967297 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x100000001; op2val:0x0 -TEST_RR_OP(sra, x12, x10, x11, -0x100000001, -0x100000001, 0x0, x3, 1064, x1) - -inst_151: -// rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen, rs1_val == 9223372036854775807 -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff; op2val:0x3 -TEST_RR_OP(sra, x12, x10, x11, 0xfffffffffffffff, 0x7fffffffffffffff, 0x3, x3, 1072, x1) - -inst_152: -// rs1_val == 16, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10; op2val:0x6 -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x10, 0x6, x3, 1080, x1) - -inst_153: -// rs1_val == 512, -// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x200; op2val:0xb -TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x200, 0xb, x3, 1088, x1) +// rs1_val < 0 and rs2_val == 0, +// opcode: sra ; op1:x30; op2:x29; dest:x31; op1val:-0xb504f332; op2val:0x0 +TEST_RR_OP(sra, x31, x30, x29, -0xb504f332, -0xb504f332, 0x0, x8, 11*XLEN/8, x9) #endif @@ -809,50 +226,50 @@ RVMODEL_HALT RVTEST_DATA_BEGIN .align 4 - rvtest_data: .word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab RVTEST_DATA_END - RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: CANARY; -signature_x9_0: - .fill 0*(XLEN/32),4,0xdeadbeef +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef -signature_x9_1: - .fill 17*(XLEN/32),4,0xdeadbeef +signature_x1_1: + .fill 25*((XLEN/8)/4),4,0xdeadbeef -signature_x3_0: - .fill 137*(XLEN/32),4,0xdeadbeef -#ifdef rvtest_mtrap_routine +signature_x8_0: + .fill 12*((XLEN/8)/4),4,0xdeadbeef +#ifdef rvtest_mtrap_routine tsig_begin_canary: CANARY; + mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef + .fill 64*XLEN/32,4,0xdeadbeef + tsig_end_canary: CANARY; - #endif #ifdef rvtest_gpr_save gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef + .fill 32*XLEN/32,4,0xdeadbeef #endif + sig_end_canary: CANARY; rvtest_sig_end: From 28a5759d966a9a5ee1e99154bc775401e689e023 Mon Sep 17 00:00:00 2001 From: anuani21 <114156183+anuani21@users.noreply.github.com> Date: Thu, 2 Jan 2025 01:17:05 +0530 Subject: [PATCH 10/10] [ACT] [CTG] [ISAC] Add support for Zhinx extension (#496) * Added RV32Zhinx and RV64Zhinx Test Case * Add support for Zhinx extension with respect to riscv-ctg and riscv-isac --------- Signed-off-by: anuani21 <114156183+anuani21@users.noreply.github.com> Co-authored-by: Umer Shahid --- coverage/cgfs_fext/RV32Zhinx/rv32h_fadd.cgf | 188 + coverage/cgfs_fext/RV32Zhinx/rv32h_fclass.cgf | 15 + .../cgfs_fext/RV32Zhinx/rv32h_fcvt.d.h.cgf | 106 + .../cgfs_fext/RV32Zhinx/rv32h_fcvt.h.d.cgf | 106 + .../cgfs_fext/RV32Zhinx/rv32h_fcvt.h.l.cgf | 27 + .../cgfs_fext/RV32Zhinx/rv32h_fcvt.h.lu.cgf | 27 + .../cgfs_fext/RV32Zhinx/rv32h_fcvt.h.s.cgf | 106 + .../cgfs_fext/RV32Zhinx/rv32h_fcvt.h.w.cgf | 14 + .../cgfs_fext/RV32Zhinx/rv32h_fcvt.h.wu.cgf | 15 + .../cgfs_fext/RV32Zhinx/rv32h_fcvt.s.h.cgf | 106 + .../cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf | 92 + .../cgfs_fext/RV32Zhinx/rv32h_fcvt.wu.h.cgf | 92 + coverage/cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf | 188 + coverage/cgfs_fext/RV32Zhinx/rv32h_feq.cgf | 35 + coverage/cgfs_fext/RV32Zhinx/rv32h_fle.cgf | 35 + coverage/cgfs_fext/RV32Zhinx/rv32h_flt.cgf | 35 + coverage/cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf | 229 + coverage/cgfs_fext/RV32Zhinx/rv32h_fmax.cgf | 35 + coverage/cgfs_fext/RV32Zhinx/rv32h_fmin.cgf | 35 + coverage/cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf | 229 + coverage/cgfs_fext/RV32Zhinx/rv32h_fmul.cgf | 155 + coverage/cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf | 229 + coverage/cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf | 229 + coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnj.cgf | 19 + coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjn.cgf | 19 + coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjx.cgf | 19 + coverage/cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf | 136 + coverage/cgfs_fext/RV32Zhinx/rv32h_fsub.cgf | 188 + .../cgfs_fext/RV64Zhinx/rv64h_fcvt.h.l.cgf | 14 + .../cgfs_fext/RV64Zhinx/rv64h_fcvt.h.lu.cgf | 14 + .../cgfs_fext/RV64Zhinx/rv64h_fcvt.l.h.cgf | 104 + .../cgfs_fext/RV64Zhinx/rv64h_fcvt.lu.h.cgf | 104 + riscv-ctg/riscv_ctg/data/inx.yaml | 723 +- riscv-ctg/riscv_ctg/generator.py | 3 +- riscv-ctg/riscv_ctg/helpers.py | 2 +- riscv-isac/riscv_isac/InstructionObject.py | 8 +- riscv-test-suite/env/arch_test.h | 6 + .../rv32i_m/Zhinx/src/fadd_b1-01.S | 5934 + .../rv32i_m/Zhinx/src/fadd_b10-01.S | 464 + .../rv32i_m/Zhinx/src/fadd_b11-01.S | 33864 ++++ .../rv32i_m/Zhinx/src/fadd_b12-01.S | 644 + .../rv32i_m/Zhinx/src/fadd_b13-01.S | 2079 + .../rv32i_m/Zhinx/src/fadd_b2-01.S | 1344 + .../rv32i_m/Zhinx/src/fadd_b3-01.S | 10989 ++ .../rv32i_m/Zhinx/src/fadd_b4-01.S | 1524 + .../rv32i_m/Zhinx/src/fadd_b5-01.S | 2329 + .../rv32i_m/Zhinx/src/fadd_b7-01.S | 706 + .../rv32i_m/Zhinx/src/fadd_b8-01.S | 16656 ++ .../rv32i_m/Zhinx/src/fclass_b1-01.S | 330 + .../rv32i_m/Zhinx/src/fcvt.w.h_b1-01.S | 342 + .../rv32i_m/Zhinx/src/fcvt.w.h_b22-01.S | 391 + .../rv32i_m/Zhinx/src/fcvt.w.h_b23-01.S | 428 + .../rv32i_m/Zhinx/src/fcvt.w.h_b24-01.S | 846 + .../rv32i_m/Zhinx/src/fcvt.w.h_b27-01.S | 321 + .../rv32i_m/Zhinx/src/fcvt.w.h_b28-01.S | 330 + .../rv32i_m/Zhinx/src/fcvt.w.h_b29-01.S | 671 + .../rv32i_m/Zhinx/src/fcvt.wu.h_b1-01.S | 337 + .../rv32i_m/Zhinx/src/fcvt.wu.h_b22-01.S | 393 + .../rv32i_m/Zhinx/src/fcvt.wu.h_b23-01.S | 426 + .../rv32i_m/Zhinx/src/fcvt.wu.h_b24-01.S | 846 + .../rv32i_m/Zhinx/src/fcvt.wu.h_b27-01.S | 328 + .../rv32i_m/Zhinx/src/fcvt.wu.h_b28-01.S | 328 + .../rv32i_m/Zhinx/src/fcvt.wu.h_b29-01.S | 673 + .../rv32i_m/Zhinx/src/fdiv_b1-01.S | 5936 + .../rv32i_m/Zhinx/src/fdiv_b2-01.S | 1324 + .../rv32i_m/Zhinx/src/fdiv_b20-01.S | 519 + .../rv32i_m/Zhinx/src/fdiv_b21-01.S | 6931 + .../rv32i_m/Zhinx/src/fdiv_b3-01.S | 11334 ++ .../rv32i_m/Zhinx/src/fdiv_b4-01.S | 1554 + .../rv32i_m/Zhinx/src/fdiv_b5-01.S | 2359 + .../rv32i_m/Zhinx/src/fdiv_b6-01.S | 444 + .../rv32i_m/Zhinx/src/fdiv_b7-01.S | 694 + .../rv32i_m/Zhinx/src/fdiv_b8-01.S | 16964 ++ .../rv32i_m/Zhinx/src/fdiv_b9-01.S | 1494 + .../rv32i_m/Zhinx/src/feq_b1-01.S | 4764 + .../rv32i_m/Zhinx/src/feq_b19-01.S | 8688 + .../rv32i_m/Zhinx/src/fle_b1-01.S | 4759 + .../rv32i_m/Zhinx/src/fle_b19-01.S | 8688 + .../rv32i_m/Zhinx/src/flt_b1-01.S | 4764 + .../rv32i_m/Zhinx/src/flt_b19-01.S | 8752 + .../rv32i_m/Zhinx/src/fmadd_b1-01.S | 139001 +++++++++++++++ .../rv32i_m/Zhinx/src/fmadd_b14-01.S | 424 + .../rv32i_m/Zhinx/src/fmadd_b16-01.S | 2221 + .../rv32i_m/Zhinx/src/fmadd_b17-01.S | 2219 + .../rv32i_m/Zhinx/src/fmadd_b18-01.S | 3034 + .../rv32i_m/Zhinx/src/fmadd_b2-01.S | 1414 + .../rv32i_m/Zhinx/src/fmadd_b3-01.S | 11466 ++ .../rv32i_m/Zhinx/src/fmadd_b4-01.S | 1614 + .../rv32i_m/Zhinx/src/fmadd_b5-01.S | 2411 + .../rv32i_m/Zhinx/src/fmadd_b6-01.S | 464 + .../rv32i_m/Zhinx/src/fmadd_b7-01.S | 786 + .../rv32i_m/Zhinx/src/fmadd_b8-01.S | 17074 ++ .../rv32i_m/Zhinx/src/fmax_b1-01.S | 5929 + .../rv32i_m/Zhinx/src/fmax_b19-01.S | 10554 ++ .../rv32i_m/Zhinx/src/fmin_b1-01.S | 5929 + .../rv32i_m/Zhinx/src/fmin_b19-01.S | 10469 ++ .../rv32i_m/Zhinx/src/fmsub_b14-01.S | 424 + .../rv32i_m/Zhinx/src/fmsub_b16-01.S | 2229 + .../rv32i_m/Zhinx/src/fmsub_b17-01.S | 2209 + .../rv32i_m/Zhinx/src/fmsub_b18-01.S | 3029 + .../rv32i_m/Zhinx/src/fmsub_b2-01.S | 1406 + .../rv32i_m/Zhinx/src/fmsub_b3-01.S | 11436 ++ .../rv32i_m/Zhinx/src/fmsub_b4-01.S | 1624 + .../rv32i_m/Zhinx/src/fmsub_b5-01.S | 2421 + .../rv32i_m/Zhinx/src/fmsub_b6-01.S | 484 + .../rv32i_m/Zhinx/src/fmsub_b7-01.S | 784 + .../rv32i_m/Zhinx/src/fmsub_b8-01.S | 17086 ++ .../rv32i_m/Zhinx/src/fmul_b1-01.S | 5934 + .../rv32i_m/Zhinx/src/fmul_b2-01.S | 1326 + .../rv32i_m/Zhinx/src/fmul_b3-01.S | 11244 ++ .../rv32i_m/Zhinx/src/fmul_b4-01.S | 1549 + .../rv32i_m/Zhinx/src/fmul_b5-01.S | 2349 + .../rv32i_m/Zhinx/src/fmul_b6-01.S | 474 + .../rv32i_m/Zhinx/src/fmul_b7-01.S | 714 + .../rv32i_m/Zhinx/src/fmul_b8-01.S | 16866 ++ .../rv32i_m/Zhinx/src/fmul_b9-01.S | 1494 + .../rv32i_m/Zhinx/src/fnmadd_b14-01.S | 566 + .../rv32i_m/Zhinx/src/fnmadd_b16-01.S | 2251 + .../rv32i_m/Zhinx/src/fnmadd_b17-01.S | 2219 + .../rv32i_m/Zhinx/src/fnmadd_b18-01.S | 3054 + .../rv32i_m/Zhinx/src/fnmadd_b2-01.S | 1419 + .../rv32i_m/Zhinx/src/fnmadd_b3-01.S | 11466 ++ .../rv32i_m/Zhinx/src/fnmadd_b4-01.S | 1614 + .../rv32i_m/Zhinx/src/fnmadd_b5-01.S | 2419 + .../rv32i_m/Zhinx/src/fnmadd_b6-01.S | 474 + .../rv32i_m/Zhinx/src/fnmadd_b7-01.S | 786 + .../rv32i_m/Zhinx/src/fnmadd_b8-01.S | 17084 ++ .../rv32i_m/Zhinx/src/fnmsub_b14-01.S | 514 + .../rv32i_m/Zhinx/src/fnmsub_b16-01.S | 2231 + .../rv32i_m/Zhinx/src/fnmsub_b17-01.S | 2199 + .../rv32i_m/Zhinx/src/fnmsub_b18-01.S | 3049 + .../rv32i_m/Zhinx/src/fnmsub_b2-01.S | 1394 + .../rv32i_m/Zhinx/src/fnmsub_b3-01.S | 11454 ++ .../rv32i_m/Zhinx/src/fnmsub_b4-01.S | 1626 + .../rv32i_m/Zhinx/src/fnmsub_b5-01.S | 2409 + .../rv32i_m/Zhinx/src/fnmsub_b6-01.S | 476 + .../rv32i_m/Zhinx/src/fnmsub_b7-01.S | 766 + .../rv32i_m/Zhinx/src/fnmsub_b8-01.S | 17079 ++ .../rv32i_m/Zhinx/src/fsgnj_b1-01.S | 5924 + .../rv32i_m/Zhinx/src/fsgnjn_b1-01.S | 5934 + .../rv32i_m/Zhinx/src/fsgnjx_b1-01.S | 5934 + .../rv32i_m/Zhinx/src/fsqrt_b1-01.S | 363 + .../rv32i_m/Zhinx/src/fsqrt_b2-01.S | 353 + .../rv32i_m/Zhinx/src/fsqrt_b20-01.S | 361 + .../rv32i_m/Zhinx/src/fsqrt_b3-01.S | 353 + .../rv32i_m/Zhinx/src/fsqrt_b4-01.S | 353 + .../rv32i_m/Zhinx/src/fsqrt_b5-01.S | 361 + .../rv32i_m/Zhinx/src/fsqrt_b7-01.S | 353 + .../rv32i_m/Zhinx/src/fsqrt_b8-01.S | 363 + .../rv32i_m/Zhinx/src/fsqrt_b9-01.S | 361 + .../rv32i_m/Zhinx/src/fsub_b1-01.S | 5353 + .../rv32i_m/Zhinx/src/fsub_b10-01.S | 401 + .../rv32i_m/Zhinx/src/fsub_b11-01.S | 30861 ++++ .../rv32i_m/Zhinx/src/fsub_b12-01.S | 603 + .../rv32i_m/Zhinx/src/fsub_b13-01.S | 1922 + .../rv32i_m/Zhinx/src/fsub_b2-01.S | 1229 + .../rv32i_m/Zhinx/src/fsub_b3-01.S | 10161 ++ .../rv32i_m/Zhinx/src/fsub_b4-01.S | 1400 + .../rv32i_m/Zhinx/src/fsub_b5-01.S | 2120 + .../rv32i_m/Zhinx/src/fsub_b7-01.S | 653 + .../rv32i_m/Zhinx/src/fsub_b8-01.S | 15032 ++ .../rv64i_m/Zhinx/src/fcvt.l.h_b1-01.S | 328 + .../rv64i_m/Zhinx/src/fcvt.l.h_b22-01.S | 615 + .../rv64i_m/Zhinx/src/fcvt.l.h_b23-01.S | 426 + .../rv64i_m/Zhinx/src/fcvt.l.h_b24-01.S | 848 + .../rv64i_m/Zhinx/src/fcvt.l.h_b27-01.S | 328 + .../rv64i_m/Zhinx/src/fcvt.l.h_b28-01.S | 337 + .../rv64i_m/Zhinx/src/fcvt.l.h_b29-01.S | 671 + .../rv64i_m/Zhinx/src/fcvt.lu.h_b1-01.S | 328 + .../rv64i_m/Zhinx/src/fcvt.lu.h_b22-01.S | 617 + .../rv64i_m/Zhinx/src/fcvt.lu.h_b23-01.S | 428 + .../rv64i_m/Zhinx/src/fcvt.lu.h_b24-01.S | 848 + .../rv64i_m/Zhinx/src/fcvt.lu.h_b27-01.S | 321 + .../rv64i_m/Zhinx/src/fcvt.lu.h_b28-01.S | 335 + .../rv64i_m/Zhinx/src/fcvt.lu.h_b29-01.S | 673 + 175 files changed, 661665 insertions(+), 4 deletions(-) create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fadd.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fclass.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.d.h.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.l.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.lu.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.s.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.w.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.wu.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.s.h.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.wu.h.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_feq.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fle.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_flt.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fmax.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fmin.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fmul.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnj.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjn.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjx.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf create mode 100644 coverage/cgfs_fext/RV32Zhinx/rv32h_fsub.cgf create mode 100644 coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.h.l.cgf create mode 100644 coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.h.lu.cgf create mode 100644 coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.l.h.cgf create mode 100644 coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.lu.h.cgf create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fadd_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fadd_b10-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fadd_b11-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fadd_b12-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fadd_b13-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fadd_b2-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fadd_b3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fadd_b4-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fadd_b5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fadd_b7-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fadd_b8-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fclass_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b22-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b23-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b24-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b27-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b28-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fcvt.w.h_b29-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b22-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b23-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b24-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b27-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b28-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fcvt.wu.h_b29-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b2-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b20-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b21-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b4-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b6-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b7-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b8-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fdiv_b9-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/feq_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/feq_b19-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fle_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fle_b19-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/flt_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/flt_b19-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b14-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b16-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b17-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b18-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b2-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b4-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b6-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b7-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmadd_b8-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmax_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmax_b19-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmin_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmin_b19-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b14-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b16-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b17-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b18-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b2-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b4-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b6-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b7-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmsub_b8-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmul_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmul_b2-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmul_b3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmul_b4-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmul_b5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmul_b6-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmul_b7-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmul_b8-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fmul_b9-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b14-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b16-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b17-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b18-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b2-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b4-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b6-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b7-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmadd_b8-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b14-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b16-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b17-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b18-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b2-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b4-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b6-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b7-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fnmsub_b8-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsgnj_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsgnjn_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsgnjx_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b2-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b20-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b4-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b7-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b8-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsqrt_b9-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsub_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsub_b10-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsub_b11-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsub_b12-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsub_b13-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsub_b2-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsub_b3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsub_b4-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsub_b5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsub_b7-01.S create mode 100644 riscv-test-suite/rv32i_m/Zhinx/src/fsub_b8-01.S create mode 100644 riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b1-01.S create mode 100644 riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b22-01.S create mode 100644 riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b23-01.S create mode 100644 riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b24-01.S create mode 100644 riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b27-01.S create mode 100644 riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b28-01.S create mode 100644 riscv-test-suite/rv64i_m/Zhinx/src/fcvt.l.h_b29-01.S create mode 100644 riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b1-01.S create mode 100644 riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b22-01.S create mode 100644 riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b23-01.S create mode 100644 riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b24-01.S create mode 100644 riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b27-01.S create mode 100644 riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b28-01.S create mode 100644 riscv-test-suite/rv64i_m/Zhinx/src/fcvt.lu.h_b29-01.S diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fadd.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fadd.cgf new file mode 100644 index 000000000..3caa84fed --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fadd.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fadd_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fadd.h", 2,True)': 0 + +fadd_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fadd.h", 2,True)': 0 + +fadd_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fadd.h", 2,True)': 0 + +fadd_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fadd.h", 2,True)': 0 + +fadd_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fadd.h", 2,True)': 0 + +fadd_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fadd.h", 2,True)': 0 + +fadd_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fadd.h", 2,True)': 0 + +fadd_b10: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b10(flen,16, "fadd.h", 2,True)': 0 + +fadd_b11: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b11(flen,16, "fadd.h", 2,True)': 0 + +fadd_b12: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b12(flen,16, "fadd.h", 2,True)': 0 + +fadd_b13: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b13(flen,16, "fadd.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fclass.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fclass.cgf new file mode 100644 index 000000000..07bca6f11 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fclass.cgf @@ -0,0 +1,15 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fclass_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fclass.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fclass.h", 1,True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.d.h.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.d.h.cgf new file mode 100644 index 000000000..1d47c5cfe --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.d.h.cgf @@ -0,0 +1,106 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.d.h_b1: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b22: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b23: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b24: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b27: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b28: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b29: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.d.h", 1)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.d.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.d.cgf new file mode 100644 index 000000000..07af2333d --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.d.cgf @@ -0,0 +1,106 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.d_b1: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b22: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b23: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b24: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b27: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b28: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b29: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fcvt.h.d", 1)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.l.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.l.cgf new file mode 100644 index 000000000..45e9c45fe --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.l.cgf @@ -0,0 +1,27 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.l_b25: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + opcode: + fcvt.h.l: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,16, "fcvt.h.l", 1)': 0 + +fcvt.h.l_b26: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + opcode: + fcvt.h.l: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(16, "fcvt.h.l", 1)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.lu.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.lu.cgf new file mode 100644 index 000000000..886da1506 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.lu.cgf @@ -0,0 +1,27 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.lu_b25: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.lu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,16, "fcvt.h.lu", 1)': 0 + +fcvt.h.lu_b26: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.lu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(16, "fcvt.h.lu", 1)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.s.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.s.cgf new file mode 100644 index 000000000..5ddc2fa50 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.s.cgf @@ -0,0 +1,106 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.s_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b22: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b23: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b24: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b27: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b28: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b29: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,32, "fcvt.h.s", 1)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.w.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.w.cgf new file mode 100644 index 000000000..e6ef94a8a --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.w.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.w_b25: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.h.w: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b25(flen,32, "fcvt.h.w", 1,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.wu.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.wu.cgf new file mode 100644 index 000000000..c34ffa553 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.h.wu.cgf @@ -0,0 +1,15 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.wu_b25: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.h.wu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b25(flen,32, "fcvt.h.wu", 1,True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.s.h.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.s.h.cgf new file mode 100644 index 000000000..ba74626b1 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.s.h.cgf @@ -0,0 +1,106 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.s.h_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b22: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b23: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b24: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b27: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b28: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b29: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.s.h", 1)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf new file mode 100644 index 000000000..f419ba9fd --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.w.h.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.w.h_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.w.h", 1,True)': 0 + +fcvt.w.h_b22: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.w.h", 1,True)': 0 + +fcvt.w.h_b23: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.w.h", 1,True)': 0 + +fcvt.w.h_b24: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.w.h", 1,True)': 0 + +fcvt.w.h_b27: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.w.h", 1,True)': 0 + +fcvt.w.h_b28: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.w.h", 1,True)': 0 + +fcvt.w.h_b29: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.w.h", 1,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.wu.h.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.wu.h.cgf new file mode 100644 index 000000000..99c988d3f --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.wu.h.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.wu.h_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.wu.h", 1,True)': 0 + +fcvt.wu.h_b22: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.wu.h", 1,True)': 0 + +fcvt.wu.h_b23: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.wu.h", 1,True)': 0 + +fcvt.wu.h_b24: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.wu.h", 1,True)': 0 + +fcvt.wu.h_b27: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.wu.h", 1,True)': 0 + +fcvt.wu.h_b28: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.wu.h", 1,True)': 0 + +fcvt.wu.h_b29: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.wu.h", 1,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf new file mode 100644 index 000000000..ab470aa72 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fdiv.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fdiv_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b9: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b20: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b20(flen,16, "fdiv.h", 2,True)': 0 + +fdiv_b21: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b21(flen,16, "fdiv.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_feq.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_feq.cgf new file mode 100644 index 000000000..3b173a2f5 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_feq.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +feq_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + feq.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "feq.h", 2,True)': 0 + +feq_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + feq.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,16, "feq.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fle.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fle.cgf new file mode 100644 index 000000000..ad31c31f6 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fle.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fle_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fle.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fle.h", 2,True)': 0 + +fle_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fle.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,16, "fle.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_flt.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_flt.cgf new file mode 100644 index 000000000..8ec408fb1 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_flt.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +flt_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + flt.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 16, "flt.h", 2,True)': 0 + +flt_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + flt.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,16, "flt.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf new file mode 100644 index 000000000..c80e44013 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmadd.cgf @@ -0,0 +1,229 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmadd_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b14: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b16: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b17: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,16, "fmadd.h", 3,True)': 0 + +fmadd_b18: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,16, "fmadd.h", 3,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fmax.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmax.cgf new file mode 100644 index 000000000..3cf803847 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmax.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmax_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmax.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmax.h", 2,True)': 0 + +fmax_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmax.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,16, "fmax.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fmin.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmin.cgf new file mode 100644 index 000000000..77db040ca --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmin.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmin_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmin.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmin.h", 2,True)': 0 + +fmin_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmin.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,16, "fmin.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf new file mode 100644 index 000000000..de52f5045 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmsub.cgf @@ -0,0 +1,229 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmsub_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b14: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b16: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b17: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,16, "fmsub.h", 3,True)': 0 + +fmsub_b18: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,16, "fmsub.h", 3,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fmul.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmul.cgf new file mode 100644 index 000000000..626248b13 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fmul.cgf @@ -0,0 +1,155 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmul_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmul.h", 2,True)': 0 + +fmul_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fmul.h", 2,True)': 0 + +fmul_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fmul.h", 2,True)': 0 + +fmul_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fmul.h", 2,True)': 0 + +fmul_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fmul.h", 2,True)': 0 + +fmul_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fmul.h", 2,True)': 0 + +fmul_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fmul.h", 2,True)': 0 + +fmul_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fmul.h", 2,True)': 0 + +fmul_b9: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,16, "fmul.h", 2,True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf new file mode 100644 index 000000000..3c435167c --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fnmadd.cgf @@ -0,0 +1,229 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fnmadd_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b14: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b16: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b17: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,16, "fnmadd.h", 3,True)': 0 + +fnmadd_b18: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,16, "fnmadd.h", 3,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf new file mode 100644 index 000000000..c7005ecd2 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fnmsub.cgf @@ -0,0 +1,229 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fnmsub_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b14: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b16: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b17: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,16, "fnmsub.h", 3,True)': 0 + +fnmsub_b18: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,16, "fnmsub.h", 3,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnj.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnj.cgf new file mode 100644 index 000000000..21c89be37 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnj.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnj_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsgnj.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fsgnj.h", 2,True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjn.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjn.cgf new file mode 100644 index 000000000..cc281a311 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjn.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnjn_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsgnjn.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fsgnjn.h", 2,True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjx.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjx.cgf new file mode 100644 index 000000000..07f17b4a2 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsgnjx.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnjx_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsgnjx.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fsgnjx.h", 2,True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf new file mode 100644 index 000000000..3112744d3 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsqrt.cgf @@ -0,0 +1,136 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsqrt_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b9: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,16, "fsqrt.h", 1,True)': 0 + +fsqrt_b20: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b20(flen,16, "fsqrt.h", 1,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zhinx/rv32h_fsub.cgf b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsub.cgf new file mode 100644 index 000000000..1a3a8ecaa --- /dev/null +++ b/coverage/cgfs_fext/RV32Zhinx/rv32h_fsub.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsub_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fsub.h", 2,True)': 0 + +fsub_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fsub.h", 2,True)': 0 + +fsub_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fsub.h", 2,True)': 0 + +fsub_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fsub.h", 2,True)': 0 + +fsub_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fsub.h", 2,True)': 0 + +fsub_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fsub.h", 2,True)': 0 + +fsub_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fsub.h", 2,True)': 0 + +fsub_b10: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b10(flen,16, "fsub.h", 2,True)': 0 + +fsub_b11: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b11(flen,16, "fsub.h", 2,True)': 0 + +fsub_b12: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b12(flen,16, "fsub.h", 2,True)': 0 + +fsub_b13: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b13(flen,16, "fsub.h", 2,True)': 0 diff --git a/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.h.l.cgf b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.h.l.cgf new file mode 100644 index 000000000..13dcae37c --- /dev/null +++ b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.h.l.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.l_b25: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.h.l: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b25(flen,64, "fcvt.h.l", 1,True)': 0 diff --git a/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.h.lu.cgf b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.h.lu.cgf new file mode 100644 index 000000000..b7fbe149f --- /dev/null +++ b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.h.lu.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.lu_b25: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + opcode: + fcvt.h.lu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b25(flen,64, "fcvt.h.lu", 1,True)': 0 diff --git a/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.l.h.cgf b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.l.h.cgf new file mode 100644 index 000000000..54fd6dbc9 --- /dev/null +++ b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.l.h.cgf @@ -0,0 +1,104 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.l.h_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.l.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.l.h", 1,True)': 0 + +fcvt.l.h_b22: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.l.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.l.h", 1, True)': 0 + +fcvt.l.h_b23: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.l.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.l.h", 1, True)': 0 + +fcvt.l.h_b24: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.l.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.l.h", 1, True)': 0 + +fcvt.l.h_b27: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.l.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.l.h", 1, True)': 0 + +fcvt.l.h_b28: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.l.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.l.h", 1, True)': 0 + +fcvt.l.h_b29: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.l.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.l.h", 1, True)': 0 diff --git a/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.lu.h.cgf b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.lu.h.cgf new file mode 100644 index 000000000..ab3cd99b2 --- /dev/null +++ b/coverage/cgfs_fext/RV64Zhinx/rv64h_fcvt.lu.h.cgf @@ -0,0 +1,104 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.lu.h_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.lu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.lu.h", 1,True)': 0 + +fcvt.lu.h_b22: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.lu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.lu.h", 1, True)': 0 + +fcvt.lu.h_b23: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.lu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.lu.h", 1, True)': 0 + +fcvt.lu.h_b24: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.lu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.lu.h", 1, True)': 0 + +fcvt.lu.h_b27: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.lu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.lu.h", 1, True)': 0 + +fcvt.lu.h_b28: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.lu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.lu.h", 1, True)': 0 + +fcvt.lu.h_b29: + config: + - check ISA:=regex(.*I.*Zfinx.*Zhinx.*) + mnemonics: + fcvt.lu.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.lu.h", 1, True)': 0 diff --git a/riscv-ctg/riscv_ctg/data/inx.yaml b/riscv-ctg/riscv_ctg/data/inx.yaml index 867e6a914..20d5e3059 100644 --- a/riscv-ctg/riscv_ctg/data/inx.yaml +++ b/riscv-ctg/riscv_ctg/data/inx.yaml @@ -1527,4 +1527,725 @@ fcvt.s.lu: // $comment /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; - fcsr_val: $fcsr*/ \ No newline at end of file + fcsr_val: $fcsr*/ + +fadd.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32] + std_op: + formattype: 'rformat' + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fclass.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmax.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmin.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +feq.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fle.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +flt.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnj.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnjn.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnjx.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsqrt.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fdiv.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmul.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsub.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg*/ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fcvt.h.w: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "lw" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.h.wu: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "LREGWU" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.w.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.wu.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.s.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fcvt.h.l: + sig: + stride: 1 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [64] + isa: + - I_Zfinx_Zhinx + std_op: + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.l.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [64] + std_op: + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[0,1,2,3,4,7]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.lu.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[0,1,2,3,4,7]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.h.lu: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fmadd.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rs3_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmsub.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rs3_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fnmadd.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rs3_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fnmsub.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - I_Zfinx_Zhinx + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rs3_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) \ No newline at end of file diff --git a/riscv-ctg/riscv_ctg/generator.py b/riscv-ctg/riscv_ctg/generator.py index 0f1066700..c150785e9 100644 --- a/riscv-ctg/riscv_ctg/generator.py +++ b/riscv-ctg/riscv_ctg/generator.py @@ -260,7 +260,8 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str,inx is_nan_box = False - is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x or 'Zcf' in x or 'Zcd' in x for x in opnode['isa']]) + + is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x or 'Zcf' in x or 'Zcd' in x or 'Zhinx' in x for x in opnode['isa']]) is_sgn_extd = True if (inxFlag and iflen iflen: - if inxFlag: + if inxFlag and iflen == 16: + if bin_val[16] == '1' : + sgnd_bin_val = bin(reg_val &((1<