diff --git a/coverage/cgfs_fext/RV32Zcd/fld.cgf b/coverage/cgfs_fext/RV32Zcd/fld.cgf new file mode 100644 index 000000000..4c42779df --- /dev/null +++ b/coverage/cgfs_fext/RV32Zcd/fld.cgf @@ -0,0 +1,67 @@ +c.fld: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + mnemonics: + c.fld: 0 + rs1: + <<: *c_regs + rd: + <<: *c_fregs + op_comb: + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +c.fsd: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fsd: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_fregs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +c.fldsp: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fldsp: 0 + rd: + <<: *all_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + +c.fsdsp: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fsdsp: 0 + rs2: + <<: *all_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 diff --git a/coverage/cgfs_fext/RV32Zcf/flw.cgf b/coverage/cgfs_fext/RV32Zcf/flw.cgf new file mode 100644 index 000000000..3442d59f0 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zcf/flw.cgf @@ -0,0 +1,65 @@ +c.flw: + config: + - check ISA:=regex(.*I.*F.*C.*) + mnemonics: + c.flw: 0 + rs1: + <<: *c_regs + rd: + <<: *c_fregs + val_comb: + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + +c.flwsp: + config: + - check ISA:=regex(.*I.*F.*C.*) + opcode: + c.flwsp: 0 + rd: + <<: *c_fregs + val_comb: + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 + +c.fsw: + config: + - check ISA:=regex(.*I.*F.*C.*) + opcode: + c.fsw: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_fregs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + +c.fswsp: + config: + - check ISA:=regex(.*I.*F.*C.*) + opcode: + c.fswsp: 0 + rs2: + <<: *c_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 diff --git a/coverage/cgfs_fext/RV64Zcd/fld.cgf b/coverage/cgfs_fext/RV64Zcd/fld.cgf new file mode 100644 index 000000000..4c42779df --- /dev/null +++ b/coverage/cgfs_fext/RV64Zcd/fld.cgf @@ -0,0 +1,67 @@ +c.fld: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + mnemonics: + c.fld: 0 + rs1: + <<: *c_regs + rd: + <<: *c_fregs + op_comb: + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +c.fsd: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fsd: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_fregs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +c.fldsp: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fldsp: 0 + rd: + <<: *all_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + +c.fsdsp: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fsdsp: 0 + rs2: + <<: *all_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 diff --git a/coverage/dataset.cgf b/coverage/dataset.cgf index a1a1a01f4..b84b69dd8 100644 --- a/coverage/dataset.cgf +++ b/coverage/dataset.cgf @@ -180,6 +180,16 @@ datasets: x13: 0 x14: 0 x15: 0 + + c_fregs: &c_fregs + f8: 0 + f9: 0 + f10: 0 + f11: 0 + f12: 0 + f13: 0 + f14: 0 + f15: 0 all_regs_mx2: &all_regs_mx2 x1: 0 diff --git a/riscv-ctg/riscv_ctg/data/imc.yaml b/riscv-ctg/riscv_ctg/data/imc.yaml index d77570efc..14fc7d9a1 100644 --- a/riscv-ctg/riscv_ctg/data/imc.yaml +++ b/riscv-ctg/riscv_ctg/data/imc.yaml @@ -1890,3 +1890,178 @@ c.jalr: // opcode: c.jalr; op1:$rs1 TEST_CJALR_OP($testreg, $rs1, $swreg, $offset) +c.flw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rd_op_data: *c_fregs + xlen: [32] + std_op: + isa: + - IF_Zcf + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'clformat' + ea_align_data: '[0,1,2,3]' + rs1_val_data: '[0]' + imm_val_data: '[x*4 for x in gen_usign_dataset(5)]' + template: |- + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg; fcsr: $fcsr + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + +c.flwsp: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *c_fregs + xlen: [32] + std_op: + isa: + - IF_Zcf + formattype: 'ciformat' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + ea_align_data: '[0,1,2,3]' + imm_val_data: '[x*4 for x in gen_usign_dataset(6)]' + template: |- + // $comment + // opcode: $inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg; fcsr: $fcsr + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + +c.fsw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + rs1_op_data: *c_regs + rs2_op_data: *c_fregs + std_op: + isa: + - IF_Zcf + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'csformat' + ea_align_data: '[0,1,2,3]' + rs1_val_data: '[0]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*4 for x in gen_usign_dataset(5)]' + template: |- + // $comment + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + +c.fswsp: + sig: + stride: 1 + sz: 'XLEN/8' + rs2_op_data: *c_fregs + xlen: [32] + std_op: + isa: + - IF_Zcf + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'cssformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*4 for x in gen_usign_dataset(6)]' + template: |- + // $comment + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + +c.fld: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "''" + load_instr: "fld" + rs1_op_data: *c_regs + rd_op_data: *c_fregs + xlen: [32,64] + std_op: + isa: + - IFD_Zcd + formattype: 'clformat' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + ea_align_data: '[0,1,2,3]' + imm_val_data: '[x*8 for x in gen_usign_dataset(5)]' + template: |- + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + +c.fldsp: + sig: + stride: 2 + sz: 'SIGALIGN' + rd_op_data: *c_fregs + xlen: [32,64] + std_op: + isa: + - IFD_Zcd + formattype: 'ciformat' + imm_val_data: '[x*8 for x in gen_usign_dataset(6)]' + template: |- + // $comment + // opcode: $inst; op1:x2; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:x4 + TEST_LOAD_F($swreg,$testreg,$fcsr,x2,$rd,$imm_val,$inst,$ea_align,x4) + + +c.fsd: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "''" + load_instr: "FLREG" + rs1_op_data: *c_regs + rs2_op_data: *c_fregs + xlen: [32,64] + std_op: + isa: + - IFD_Zcd + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'csformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*8 for x in gen_usign_dataset(5)]' + template: |- + // $comment + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + +c.fsdsp: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "''" + load_instr: "FLREG" + rs2_op_data: *c_fregs + xlen: [32,64] + std_op: + isa: + - IFD_Zcd + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'cssformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*8 for x in gen_usign_dataset(6)]' + template: |- + // $comment + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) diff --git a/riscv-ctg/riscv_ctg/data/template.yaml b/riscv-ctg/riscv_ctg/data/template.yaml index d1f87c8df..40d23c717 100644 --- a/riscv-ctg/riscv_ctg/data/template.yaml +++ b/riscv-ctg/riscv_ctg/data/template.yaml @@ -4,6 +4,7 @@ metadata: all_fregs: &all_fregs "['f'+str(x) for x in range(0,32 if 'e' not in base_isa else 16)]" all_regs_mx0: &all_regs_mx0 "['x'+str(x) for x in range(1,32 if 'e' not in base_isa else 16)]" c_regs: &c_regs "['x'+str(x) for x in range(8,16)]" + c_fregs: &c_fregs "['x'+str(x) for x in range(8,16)]" pair_regs: &pair_regs "['x'+str(x) for x in range(2,32 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]" rv32rv64pair_regs: &rv32rv64pair_regs "['x'+str(x) for x in range(2,30 if 'e' not in base_isa else 16, 2)]" diff --git a/riscv-ctg/riscv_ctg/generator.py b/riscv-ctg/riscv_ctg/generator.py index 5e25cf17e..31e7bd525 100644 --- a/riscv-ctg/riscv_ctg/generator.py +++ b/riscv-ctg/riscv_ctg/generator.py @@ -260,7 +260,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str,inx is_nan_box = False - is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x for x in opnode['isa']]) + is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x or 'Zcf' in x or 'Zcd' in x for x in opnode['isa']]) is_sgn_extd = True if (inxFlag and iflen 0 and fcsr == 0, +// opcode:c.fld; op1:x14; dest:f14; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x14,f14,0xf8,c.fld,0,x4) + +inst_2: +// rs1==x13, rd==f13,imm_val == 168, +// opcode:c.fld; op1:x13; dest:f13; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x13,f13,0xa8,c.fld,0,x4) + +inst_3: +// rs1==x12, rd==f12,imm_val == 80, +// opcode:c.fld; op1:x12; dest:f12; immval:0x50; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x12,f12,0x50,c.fld,0,x4) + +inst_4: +// rs1==x11, rd==f11,imm_val == 8, +// opcode:c.fld; op1:x11; dest:f11; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x11,f11,0x8,c.fld,0,x4) + +inst_5: +// rs1==x10, rd==f10,imm_val == 16, +// opcode:c.fld; op1:x10; dest:f10; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x10,f10,0x10,c.fld,0,x4) + +inst_6: +// rs1==x9, rd==f9,imm_val == 240, +// opcode:c.fld; op1:x9; dest:f9; immval:0xf0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x9,f9,0xf0,c.fld,0,x4) + +inst_7: +// rs1==x8, rd==f8,imm_val == 232, +// opcode:c.fld; op1:x8; dest:f8; immval:0xe8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x8,f8,0xe8,c.fld,0,x4) + +inst_8: +// imm_val == 216, +// opcode:c.fld; op1:x15; dest:f15; immval:0xd8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0xd8,c.fld,0,x4) + +inst_9: +// imm_val == 184, +// opcode:c.fld; op1:x15; dest:f15; immval:0xb8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0xb8,c.fld,0,x4) + +inst_10: +// imm_val == 120, +// opcode:c.fld; op1:x15; dest:f15; immval:0x78; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x78,c.fld,0,x4) + +inst_11: +// imm_val == 32, +// opcode:c.fld; op1:x15; dest:f15; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x20,c.fld,0,x4) + +inst_12: +// imm_val == 64, +// opcode:c.fld; op1:x15; dest:f15; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x40,c.fld,0,x4) + +inst_13: +// imm_val == 128, +// opcode:c.fld; op1:x15; dest:f15; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x80,c.fld,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + + + + + + + + + + + + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fldsp-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fldsp-01.S new file mode 100644 index 000000000..579e37234 --- /dev/null +++ b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fldsp-01.S @@ -0,0 +1,247 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 04:57:10 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fldsp.cgf \ + \ +// -- xlen 64 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fldsp instruction of the RISC-V RV64FDC extension for the c.fldsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fldsp) + +RVTEST_FP_ENABLE() +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rd==f31, imm_val == 0, +// opcode:c.fldsp; op1:x2; dest:f31; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f31,0x0,c.fldsp,0,x4) + +inst_1: +// rd==f30, imm_val > 0, +// opcode:c.fldsp; op1:x2; dest:f30; immval:0x1f8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f30,0x1f8,c.fldsp,0,x4) + +inst_2: +// rd==f29, imm_val == 168, +// opcode:c.fldsp; op1:x2; dest:f29; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f29,0xa8,c.fldsp,0,x4) + +inst_3: +// rd==f28, imm_val == 336, +// opcode:c.fldsp; op1:x2; dest:f28; immval:0x150; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f28,0x150,c.fldsp,0,x4) + +inst_4: +// rd==f27, imm_val == 496, +// opcode:c.fldsp; op1:x2; dest:f27; immval:0x1f0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f27,0x1f0,c.fldsp,0,x4) + +inst_5: +// rd==f26, imm_val == 488, +// opcode:c.fldsp; op1:x2; dest:f26; immval:0x1e8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f26,0x1e8,c.fldsp,0,x4) + +inst_6: +// rd==f25, imm_val == 472, +// opcode:c.fldsp; op1:x2; dest:f25; immval:0x1d8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f25,0x1d8,c.fldsp,0,x4) + +inst_7: +// rd==f24, imm_val == 440, +// opcode:c.fldsp; op1:x2; dest:f24; immval:0x1b8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f24,0x1b8,c.fldsp,0,x4) + +inst_8: +// rd==f23, imm_val == 376, +// opcode:c.fldsp; op1:x2; dest:f23; immval:0x178; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f23,0x178,c.fldsp,0,x4) + +inst_9: +// rd==f22, imm_val == 248, +// opcode:c.fldsp; op1:x2; dest:f22; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f22,0xf8,c.fldsp,0,x4) + +inst_10: +// rd==f21, imm_val == 8, +// opcode:c.fldsp; op1:x2; dest:f21; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f21,0x8,c.fldsp,0,x4) + +inst_11: +// rd==f20, imm_val == 16, +// opcode:c.fldsp; op1:x2; dest:f20; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f20,0x10,c.fldsp,0,x4) + +inst_12: +// rd==f19, imm_val == 32, +// opcode:c.fldsp; op1:x2; dest:f19; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f19,0x20,c.fldsp,0,x4) + +inst_13: +// rd==f18, imm_val == 64, +// opcode:c.fldsp; op1:x2; dest:f18; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f18,0x40,c.fldsp,0,x4) + +inst_14: +// rd==f17, imm_val == 128, +// opcode:c.fldsp; op1:x2; dest:f17; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f17,0x80,c.fldsp,0,x4) + +inst_15: +// rd==f16, imm_val == 256, +// opcode:c.fldsp; op1:x2; dest:f16; immval:0x100; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f16,0x100,c.fldsp,0,x4) + +inst_16: +// rd==f15, +// opcode:c.fldsp; op1:x2; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f15,0x0,c.fldsp,0,x4) + +inst_17: +// rd==f14, +// opcode:c.fldsp; op1:x2; dest:f14; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f14,0x0,c.fldsp,0,x4) + +inst_18: +// rd==f13, +// opcode:c.fldsp; op1:x2; dest:f13; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f13,0x0,c.fldsp,0,x4) + +inst_19: +// rd==f12, +// opcode:c.fldsp; op1:x2; dest:f12; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f12,0x0,c.fldsp,0,x4) + +inst_20: +// rd==f11, +// opcode:c.fldsp; op1:x2; dest:f11; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f11,0x0,c.fldsp,0,x4) + +inst_21: +// rd==f10, +// opcode:c.fldsp; op1:x2; dest:f10; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f10,0x0,c.fldsp,0,x4) + +inst_22: +// rd==f9, +// opcode:c.fldsp; op1:x2; dest:f9; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f9,0x0,c.fldsp,0,x4) + +inst_23: +// rd==f8, +// opcode:c.fldsp; op1:x2; dest:f8; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f8,0x0,c.fldsp,0,x4) + +inst_24: +// rd==f7, +// opcode:c.fldsp; op1:x2; dest:f7; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f7,0x0,c.fldsp,0,x4) + +inst_25: +// rd==f6, +// opcode:c.fldsp; op1:x2; dest:f6; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f6,0x0,c.fldsp,0,x4) + +inst_26: +// rd==f5, +// opcode:c.fldsp; op1:x2; dest:f5; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f5,0x0,c.fldsp,0,x4) + +inst_27: +// rd==f4, +// opcode:c.fldsp; op1:x2; dest:f4; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f4,0x0,c.fldsp,0,x4) + +inst_28: +// rd==f3, +// opcode:c.fldsp; op1:x2; dest:f3; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f3,0x0,c.fldsp,0,x4) + +inst_29: +// rd==f2, +// opcode:c.fldsp; op1:x2; dest:f2; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f2,0x0,c.fldsp,0,x4) + +inst_30: +// rd==f1, +// opcode:c.fldsp; op1:x2; dest:f1; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f1,0x0,c.fldsp,0,x4) + +inst_31: +// rd==f0, +// opcode:c.fldsp; op1:x2; dest:f0; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f0,0x0,c.fldsp,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsd-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsd-01.S new file mode 100644 index 000000000..967a60248 --- /dev/null +++ b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsd-01.S @@ -0,0 +1,213 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Fri Aug 4 07:31:35 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsd instruction of the RISC-V RV32FDC_Zcd,RV64FDC_Zcd extension for the c.fsd covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fsd) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs1 != rs2, rs1==x15, rs2==f15,imm_val == 0, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0x0; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 0*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x0,0*SIGALIGN,c.fsd,0,x4,x3, 0*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_1) + +inst_1:// rs1==x14, rs2==f14,imm_val > 0, +// opcode: c.fsd; op1:x14; op2:f14; op2val:-0x1000001; immval:0xf8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 1*FLEN/8; +TEST_STORE_F(x1,x2,0,x14,f14,0xf8,2*SIGALIGN,c.fsd,0,x4,x3, 1*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_2:// rs1==x13, rs2==f13,imm_val == 168, +// opcode: c.fsd; op1:x13; op2:f13; op2val:-0x1000001; immval:0xa8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 2*FLEN/8; +TEST_STORE_F(x1,x2,0,x13,f13,0xa8,4*SIGALIGN,c.fsd,0,x4,x3, 2*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_3) + +inst_3:// rs1==x12, rs2==f12,imm_val == 80, +// opcode: c.fsd; op1:x12; op2:f12; op2val:-0x1000001; immval:0x50; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 3*FLEN/8; +TEST_STORE_F(x1,x2,0,x12,f12,0x50,6*SIGALIGN,c.fsd,0,x4,x3, 3*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_4) + +inst_4:// rs1==x11, rs2==f11,imm_val == 8, +// opcode: c.fsd; op1:x11; op2:f11; op2val:-0x1000001; immval:0x8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 4*FLEN/8; +TEST_STORE_F(x1,x2,0,x11,f11,0x8,8*SIGALIGN,c.fsd,0,x4,x3, 4*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_5) + +inst_5:// rs1==x10, rs2==f10,imm_val == 16, +// opcode: c.fsd; op1:x10; op2:f10; op2val:-0x1000001; immval:0x10; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 5*FLEN/8; +TEST_STORE_F(x1,x2,0,x10,f10,0x10,10*SIGALIGN,c.fsd,0,x4,x3, 5*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_6) + +inst_6:// rs1==x9, rs2==f9,imm_val == 240, +// opcode: c.fsd; op1:x9; op2:f9; op2val:-0x1000001; immval:0xf0; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 6*FLEN/8; +TEST_STORE_F(x1,x2,0,x9,f9,0xf0,12*SIGALIGN,c.fsd,0,x4,x3, 6*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_7) + +inst_7:// rs1==x8, rs2==f8,imm_val == 232, +// opcode: c.fsd; op1:x8; op2:f8; op2val:-0x1000001; immval:0xe8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 7*FLEN/8; +TEST_STORE_F(x1,x2,0,x8,f8,0xe8,14*SIGALIGN,c.fsd,0,x4,x3, 7*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_8) + +inst_8:// imm_val == 216, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0xd8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 8*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0xd8,16*SIGALIGN,c.fsd,0,x4,x3, 8*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_9) + +inst_9:// imm_val == 184, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0xb8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 9*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0xb8,18*SIGALIGN,c.fsd,0,x4,x3, 9*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_10) + +inst_10:// imm_val == 120, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0x78; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 10*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x78,20*SIGALIGN,c.fsd,0,x4,x3, 10*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_11) + +inst_11:// imm_val == 32, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0x20; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 11*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x20,22*SIGALIGN,c.fsd,0,x4,x3, 11*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_12) + +inst_12:// imm_val == 64, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0x40; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 12*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x40,24*SIGALIGN,c.fsd,0,x4,x3, 12*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_13) + +inst_13:// imm_val == 128, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1000001; immval:0x80; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 13*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x80,26*SIGALIGN,c.fsd,0,x4,x3, 13*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + +test_dataset_1: + + +test_dataset_2: + + +test_dataset_3: + + +test_dataset_4: + + +test_dataset_5: + + +test_dataset_6: + + +test_dataset_7: + + +test_dataset_8: + + +test_dataset_9: + + +test_dataset_10: + + +test_dataset_11: + + +test_dataset_12: + + +test_dataset_13: + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsdsp-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsdsp-01.S new file mode 100644 index 000000000..5a044aa7a --- /dev/null +++ b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsdsp-01.S @@ -0,0 +1,343 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 04:41:22 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fsdsp.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsdsp instruction of the RISC-V RV32FDC,RV64FDC extension for the c.fsdsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFDC,RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*C.*);def TEST_CASE_1=True;",c.fsdsp) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs2==f31, imm_val == 0, +// opcode: c.fsdsp; op1:x2; op2:f31; op2val:-0x1000001; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 0*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f31,0x0,0*SIGALIGN,c.fsdsp,0,x5,x4,0*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_1) + +inst_1:// rs2==f30, imm_val > 0, +// opcode: c.fsdsp; op1:x2; op2:f30; op2val:-0x1000001; immval:0x1f8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 1*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f30,0x1f8,2*SIGALIGN,c.fsdsp,0,x5,x4,1*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_2:// rs2==f29, imm_val == 168, +// opcode: c.fsdsp; op1:x2; op2:f29; op2val:-0x1000001; immval:0xa8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 2*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f29,0xa8,4*SIGALIGN,c.fsdsp,0,x5,x4,2*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_3) + +inst_3:// rs2==f28, imm_val == 336, +// opcode: c.fsdsp; op1:x2; op2:f28; op2val:-0x1000001; immval:0x150; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 3*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f28,0x150,6*SIGALIGN,c.fsdsp,0,x5,x4,3*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_4) + +inst_4:// rs2==f27, imm_val == 496, +// opcode: c.fsdsp; op1:x2; op2:f27; op2val:-0x1000001; immval:0x1f0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 4*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f27,0x1f0,8*SIGALIGN,c.fsdsp,0,x5,x4,4*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_5) + +inst_5:// rs2==f26, imm_val == 488, +// opcode: c.fsdsp; op1:x2; op2:f26; op2val:-0x1000001; immval:0x1e8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 5*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f26,0x1e8,10*SIGALIGN,c.fsdsp,0,x5,x4,5*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_6) + +inst_6:// rs2==f25, imm_val == 472, +// opcode: c.fsdsp; op1:x2; op2:f25; op2val:-0x1000001; immval:0x1d8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 6*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f25,0x1d8,12*SIGALIGN,c.fsdsp,0,x5,x4,6*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_7) + +inst_7:// rs2==f24, imm_val == 440, +// opcode: c.fsdsp; op1:x2; op2:f24; op2val:-0x1000001; immval:0x1b8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 7*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f24,0x1b8,14*SIGALIGN,c.fsdsp,0,x5,x4,7*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_8) + +inst_8:// rs2==f23, imm_val == 376, +// opcode: c.fsdsp; op1:x2; op2:f23; op2val:-0x1000001; immval:0x178; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 8*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f23,0x178,16*SIGALIGN,c.fsdsp,0,x5,x4,8*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_9) + +inst_9:// rs2==f22, imm_val == 248, +// opcode: c.fsdsp; op1:x2; op2:f22; op2val:-0x1000001; immval:0xf8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 9*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f22,0xf8,18*SIGALIGN,c.fsdsp,0,x5,x4,9*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_10) + +inst_10:// rs2==f21, imm_val == 8, +// opcode: c.fsdsp; op1:x2; op2:f21; op2val:-0x1000001; immval:0x8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 10*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f21,0x8,20*SIGALIGN,c.fsdsp,0,x5,x4,10*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_11) + +inst_11:// rs2==f20, imm_val == 16, +// opcode: c.fsdsp; op1:x2; op2:f20; op2val:-0x1000001; immval:0x10; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 11*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f20,0x10,22*SIGALIGN,c.fsdsp,0,x5,x4,11*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_12) + +inst_12:// rs2==f19, imm_val == 32, +// opcode: c.fsdsp; op1:x2; op2:f19; op2val:-0x1000001; immval:0x20; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 12*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f19,0x20,24*SIGALIGN,c.fsdsp,0,x5,x4,12*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_13) + +inst_13:// rs2==f18, imm_val == 64, +// opcode: c.fsdsp; op1:x2; op2:f18; op2val:-0x1000001; immval:0x40; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 13*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f18,0x40,26*SIGALIGN,c.fsdsp,0,x5,x4,13*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_14) + +inst_14:// rs2==f17, imm_val == 128, +// opcode: c.fsdsp; op1:x2; op2:f17; op2val:-0x1000001; immval:0x80; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 14*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f17,0x80,28*SIGALIGN,c.fsdsp,0,x5,x4,14*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_15) + +inst_15:// rs2==f16, imm_val == 256, +// opcode: c.fsdsp; op1:x2; op2:f16; op2val:-0x1000001; immval:0x100; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 15*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f16,0x100,30*SIGALIGN,c.fsdsp,0,x5,x4,15*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_16) + +inst_16:// rs2==f15, +// opcode: c.fsdsp; op1:x2; op2:f15; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 16*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f15,0x0,32*SIGALIGN,c.fsdsp,0,x5,x4,16*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_17) + +inst_17:// rs2==f14, +// opcode: c.fsdsp; op1:x2; op2:f14; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 17*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f14,0x0,34*SIGALIGN,c.fsdsp,0,x5,x4,17*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_18) + +inst_18:// rs2==f13, +// opcode: c.fsdsp; op1:x2; op2:f13; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 18*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f13,0x0,36*SIGALIGN,c.fsdsp,0,x5,x4,18*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_19) + +inst_19:// rs2==f12, +// opcode: c.fsdsp; op1:x2; op2:f12; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 19*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f12,0x0,38*SIGALIGN,c.fsdsp,0,x5,x4,19*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_20) + +inst_20:// rs2==f11, +// opcode: c.fsdsp; op1:x2; op2:f11; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 20*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f11,0x0,40*SIGALIGN,c.fsdsp,0,x5,x4,20*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_21) + +inst_21:// rs2==f10, +// opcode: c.fsdsp; op1:x2; op2:f10; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 21*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f10,0x0,42*SIGALIGN,c.fsdsp,0,x5,x4,21*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_22) + +inst_22:// rs2==f9, +// opcode: c.fsdsp; op1:x2; op2:f9; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 22*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f9,0x0,44*SIGALIGN,c.fsdsp,0,x5,x4,22*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_23) + +inst_23:// rs2==f8, +// opcode: c.fsdsp; op1:x2; op2:f8; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 23*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f8,0x0,46*SIGALIGN,c.fsdsp,0,x5,x4,23*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_24) + +inst_24:// rs2==f7, +// opcode: c.fsdsp; op1:x2; op2:f7; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 24*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f7,0x0,48*SIGALIGN,c.fsdsp,0,x5,x4,24*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_25) + +inst_25:// rs2==f6, +// opcode: c.fsdsp; op1:x2; op2:f6; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 25*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f6,0x0,50*SIGALIGN,c.fsdsp,0,x5,x4,25*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_26) + +inst_26:// rs2==f5, +// opcode: c.fsdsp; op1:x2; op2:f5; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 26*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f5,0x0,52*SIGALIGN,c.fsdsp,0,x5,x4,26*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_27) + +inst_27:// rs2==f4, +// opcode: c.fsdsp; op1:x2; op2:f4; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 27*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f4,0x0,54*SIGALIGN,c.fsdsp,0,x5,x4,27*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_28) + +inst_28:// rs2==f3, +// opcode: c.fsdsp; op1:x2; op2:f3; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 28*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f3,0x0,56*SIGALIGN,c.fsdsp,0,x5,x4,28*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_29) + +inst_29:// rs2==f2, +// opcode: c.fsdsp; op1:x2; op2:f2; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 29*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f2,0x0,58*SIGALIGN,c.fsdsp,0,x5,x4,29*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_30) + +inst_30:// rs2==f1, +// opcode: c.fsdsp; op1:x2; op2:f1; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 30*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f1,0x0,60*SIGALIGN,c.fsdsp,0,x5,x4,30*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_31) + +inst_31:// rs2==f0, +// opcode: c.fsdsp; op1:x2; op2:f0; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 31*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f0,0x0,62*SIGALIGN,c.fsdsp,0,x5,x4,31*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + +test_dataset_1: + +test_dataset_2: + +test_dataset_3: + +test_dataset_4: + +test_dataset_5: + +test_dataset_6: + +test_dataset_7: + +test_dataset_8: + +test_dataset_9: + +test_dataset_10: + +test_dataset_11: + +test_dataset_12: + +test_dataset_13: + +test_dataset_14: + +test_dataset_15: + +test_dataset_16: + +test_dataset_17: + +test_dataset_18: + +test_dataset_19: + +test_dataset_20: + +test_dataset_21: + +test_dataset_22: + +test_dataset_23: + +test_dataset_24: + +test_dataset_25: + +test_dataset_26: + +test_dataset_27: + +test_dataset_28: + +test_dataset_29: + +test_dataset_30: + +test_dataset_31: + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.flw-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flw-01.S new file mode 100644 index 000000000..043e33306 --- /dev/null +++ b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flw-01.S @@ -0,0 +1,173 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Thu Aug 3 07:43:25 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/FLW.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.flw instruction of the RISC-V RV32F_Zcf extension for the c.flw covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zcf") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.flw) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1==x15, rd==f15,imm_val == 0 and fcsr == 0, +// opcode:c.flw; op1:x15; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x15,f15,0x0,c.flw,0,x4) + +inst_1: +// rs1==x14, rd==f14,imm_val > 0 and fcsr == 0, +// opcode:c.flw; op1:x14; dest:f14; immval:0x7c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x14,f14,0x7c,c.flw,0,x4) + +inst_2: +// rs1==x13, rd==f13,imm_val == 84, +// opcode:c.flw; op1:x13; dest:f13; immval:0x54; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x13,f13,0x54,c.flw,0,x4) + +inst_3: +// rs1==x12, rd==f12,imm_val == 40, +// opcode:c.flw; op1:x12; dest:f12; immval:0x28; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x12,f12,0x28,c.flw,0,x4) + +inst_4: +// rs1==x11, rd==f11,imm_val == 4, +// opcode:c.flw; op1:x11; dest:f11; immval:0x4; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x11,f11,0x4,c.flw,0,x4) + +inst_5: +// rs1==x10, rd==f10,imm_val == 120, +// opcode:c.flw; op1:x10; dest:f10; immval:0x78; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x10,f10,0x78,c.flw,0,x4) + +inst_6: +// rs1==x9, rd==f9,imm_val == 116, +// opcode:c.flw; op1:x9; dest:f9; immval:0x74; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x9,f9,0x74,c.flw,0,x4) + +inst_7: +// rs1==x8, rd==f8,imm_val == 108, +// opcode:c.flw; op1:x8; dest:f8; immval:0x6c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x8,f8,0x6c,c.flw,0,x4) + +inst_8: +// imm_val == 92, +// opcode:c.flw; op1:x15; dest:f15; immval:0x5c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x5c,c.flw,0,x4) + +inst_9: +// imm_val == 60, +// opcode:c.flw; op1:x15; dest:f15; immval:0x3c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x3c,c.flw,0,x4) + +inst_10: +// imm_val == 8, +// opcode:c.flw; op1:x15; dest:f15; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x8,c.flw,0,x4) + +inst_11: +// imm_val == 16, +// opcode:c.flw; op1:x15; dest:f15; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x10,c.flw,0,x4) + +inst_12: +// imm_val == 32, +// opcode:c.flw; op1:x15; dest:f15; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x20,c.flw,0,x4) + +inst_13: +// imm_val == 64, +// opcode:c.flw; op1:x15; dest:f15; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x40,c.flw,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + + + + + + + + + + + + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.flwsp-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flwsp-01.S new file mode 100644 index 000000000..33806012a --- /dev/null +++ b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flwsp-01.S @@ -0,0 +1,249 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Thu Aug 10 08:04:09 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/flwsp.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.flwsp instruction of the RISC-V RV32F_Zcf extension for the c.flwsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zcf") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.flwsp) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rd==f31, imm_val == 0 and fcsr == 0, +// opcode:c.flwsp; op1:x2; dest:f31; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f31,0x0,c.flwsp,0,x4) + +inst_1: +// rd==f30, imm_val > 0 and fcsr == 0, +// opcode:c.flwsp; op1:x2; dest:f30; immval:0xfc; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f30,0xfc,c.flwsp,0,x4) + +inst_2: +// rd==f29, imm_val == 84, +// opcode:c.flwsp; op1:x2; dest:f29; immval:0x54; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f29,0x54,c.flwsp,0,x4) + +inst_3: +// rd==f28, imm_val == 168, +// opcode:c.flwsp; op1:x2; dest:f28; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f28,0xa8,c.flwsp,0,x4) + +inst_4: +// rd==f27, imm_val == 248, +// opcode:c.flwsp; op1:x2; dest:f27; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f27,0xf8,c.flwsp,0,x4) + +inst_5: +// rd==f26, imm_val == 244, +// opcode:c.flwsp; op1:x2; dest:f26; immval:0xf4; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f26,0xf4,c.flwsp,0,x4) + +inst_6: +// rd==f25, imm_val == 236, +// opcode:c.flwsp; op1:x2; dest:f25; immval:0xec; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f25,0xec,c.flwsp,0,x4) + +inst_7: +// rd==f24, imm_val == 220, +// opcode:c.flwsp; op1:x2; dest:f24; immval:0xdc; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f24,0xdc,c.flwsp,0,x4) + +inst_8: +// rd==f23, imm_val == 188, +// opcode:c.flwsp; op1:x2; dest:f23; immval:0xbc; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f23,0xbc,c.flwsp,0,x4) + +inst_9: +// rd==f22, imm_val == 124, +// opcode:c.flwsp; op1:x2; dest:f22; immval:0x7c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f22,0x7c,c.flwsp,0,x4) + +inst_10: +// rd==f21, imm_val == 4, +// opcode:c.flwsp; op1:x2; dest:f21; immval:0x4; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f21,0x4,c.flwsp,0,x4) + +inst_11: +// rd==f20, imm_val == 8, +// opcode:c.flwsp; op1:x2; dest:f20; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f20,0x8,c.flwsp,0,x4) + +inst_12: +// rd==f19, imm_val == 16, +// opcode:c.flwsp; op1:x2; dest:f19; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f19,0x10,c.flwsp,0,x4) + +inst_13: +// rd==f18, imm_val == 32, +// opcode:c.flwsp; op1:x2; dest:f18; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f18,0x20,c.flwsp,0,x4) + +inst_14: +// rd==f17, imm_val == 64, +// opcode:c.flwsp; op1:x2; dest:f17; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f17,0x40,c.flwsp,0,x4) + +inst_15: +// rd==f16, imm_val == 128, +// opcode:c.flwsp; op1:x2; dest:f16; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,159,x2,f16,0x80,c.flwsp,0,x4) + +inst_16: +// rd==f15, +// opcode:c.flwsp; op1:x2; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f15,0x0,c.flwsp,0,x4) + +inst_17: +// rd==f14, +// opcode:c.flwsp; op1:x2; dest:f14; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f14,0x0,c.flwsp,0,x4) + +inst_18: +// rd==f13, +// opcode:c.flwsp; op1:x2; dest:f13; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f13,0x0,c.flwsp,0,x4) + +inst_19: +// rd==f12, +// opcode:c.flwsp; op1:x2; dest:f12; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f12,0x0,c.flwsp,0,x4) + +inst_20: +// rd==f11, +// opcode:c.flwsp; op1:x2; dest:f11; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f11,0x0,c.flwsp,0,x4) + +inst_21: +// rd==f10, +// opcode:c.flwsp; op1:x2; dest:f10; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f10,0x0,c.flwsp,0,x4) + +inst_22: +// rd==f9, +// opcode:c.flwsp; op1:x2; dest:f9; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f9,0x0,c.flwsp,0,x4) + +inst_23: +// rd==f8, +// opcode:c.flwsp; op1:x2; dest:f8; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f8,0x0,c.flwsp,0,x4) + +inst_24: +// rd==f7, +// opcode:c.flwsp; op1:x2; dest:f7; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f7,0x0,c.flwsp,0,x4) + +inst_25: +// rd==f6, +// opcode:c.flwsp; op1:x2; dest:f6; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f6,0x0,c.flwsp,0,x4) + +inst_26: +// rd==f5, +// opcode:c.flwsp; op1:x2; dest:f5; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f5,0x0,c.flwsp,0,x4) + +inst_27: +// rd==f4, +// opcode:c.flwsp; op1:x2; dest:f4; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f4,0x0,c.flwsp,0,x4) + +inst_28: +// rd==f3, +// opcode:c.flwsp; op1:x2; dest:f3; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f3,0x0,c.flwsp,0,x4) + +inst_29: +// rd==f2, +// opcode:c.flwsp; op1:x2; dest:f2; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f2,0x0,c.flwsp,0,x4) + +inst_30: +// rd==f1, +// opcode:c.flwsp; op1:x2; dest:f1; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f1,0x0,c.flwsp,0,x4) + +inst_31: +// rd==f0, +// opcode:c.flwsp; op1:x2; dest:f0; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f0,0x0,c.flwsp,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.fsw-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fsw-01.S new file mode 100644 index 000000000..7b95fadd6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fsw-01.S @@ -0,0 +1,213 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Thu Aug 3 07:43:25 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/FLW.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsw instruction of the RISC-V RV32F_Zcf extension for the c.fsw covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zcf") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.fsw) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs1 != rs2, rs1==x15, rs2==f15,imm_val == 0, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x0; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 0*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x0,0*SIGALIGN,c.fsw,0,x4,x3, 0*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_1) + +inst_1:// rs1==x14, rs2==f14,imm_val > 0, +// opcode: c.fsw; op1:x14; op2:f14; op2val:-0x1000001; immval:0x7c; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 1*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x14,f14,0x7c,1*SIGALIGN,c.fsw,0,x4,x3, 1*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_2:// rs1==x13, rs2==f13,imm_val == 84, +// opcode: c.fsw; op1:x13; op2:f13; op2val:-0x1000001; immval:0x54; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 2*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x13,f13,0x54,2*SIGALIGN,c.fsw,0,x4,x3, 2*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_3) + +inst_3:// rs1==x12, rs2==f12,imm_val == 40, +// opcode: c.fsw; op1:x12; op2:f12; op2val:-0x1000001; immval:0x28; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 3*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x12,f12,0x28,3*SIGALIGN,c.fsw,0,x4,x3, 3*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_4) + +inst_4:// rs1==x11, rs2==f11,imm_val == 4, +// opcode: c.fsw; op1:x11; op2:f11; op2val:-0x1000001; immval:0x4; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 4*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x11,f11,0x4,4*SIGALIGN,c.fsw,0,x4,x3, 4*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_5) + +inst_5:// rs1==x10, rs2==f10,imm_val == 8, +// opcode: c.fsw; op1:x10; op2:f10; op2val:-0x1000001; immval:0x8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 5*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x10,f10,0x8,5*SIGALIGN,c.fsw,0,x4,x3, 5*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_6) + +inst_6:// rs1==x9, rs2==f9,imm_val == 120, +// opcode: c.fsw; op1:x9; op2:f9; op2val:-0x1000001; immval:0x78; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 6*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x9,f9,0x78,6*SIGALIGN,c.fsw,0,x4,x3, 6*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_7) + +inst_7:// rs1==x8, rs2==f8,imm_val == 116, +// opcode: c.fsw; op1:x8; op2:f8; op2val:-0x1000001; immval:0x74; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 7*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x8,f8,0x74,7*SIGALIGN,c.fsw,0,x4,x3, 7*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_8) + +inst_8:// imm_val == 108, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x6c; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 8*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x6c,8*SIGALIGN,c.fsw,0,x4,x3, 8*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_9) + +inst_9:// imm_val == 92, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x5c; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 9*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x5c,9*SIGALIGN,c.fsw,0,x4,x3, 9*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_10) + +inst_10:// imm_val == 60, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x3c; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 10*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x3c,10*SIGALIGN,c.fsw,0,x4,x3, 10*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_11) + +inst_11:// imm_val == 16, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x10; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 11*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x10,11*SIGALIGN,c.fsw,0,x4,x3, 11*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_12) + +inst_12:// imm_val == 32, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x20; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 12*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x20,12*SIGALIGN,c.fsw,0,x4,x3, 12*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_13) + +inst_13:// imm_val == 64, +// opcode: c.fsw; op1:x15; op2:f15; op2val:-0x1000001; immval:0x40; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 13*FLEN/8 +TEST_STORE_F(x1,x2,$fcsr,x15,f15,0x40,13*SIGALIGN,c.fsw,0,x4,x3, 13*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + +test_dataset_1: + + +test_dataset_2: + + +test_dataset_3: + + +test_dataset_4: + + +test_dataset_5: + + +test_dataset_6: + + +test_dataset_7: + + +test_dataset_8: + + +test_dataset_9: + + +test_dataset_10: + + +test_dataset_11: + + +test_dataset_12: + + +test_dataset_13: + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 14*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.fswsp-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fswsp-01.S new file mode 100644 index 000000000..7908a2bb8 --- /dev/null +++ b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fswsp-01.S @@ -0,0 +1,343 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 04:45:36 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fswsp.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fswsp instruction of the RISC-V RV32FC extension for the c.fswsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*C.*);def TEST_CASE_1=True;",c.fswsp) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs2==f31, imm_val == 0, +// opcode: c.fswsp; op1:x2; op2:f31; op2val:-0x1000001; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 0*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f31,0x0,0*SIGALIGN,c.fswsp,0,x5,x4,0*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_1) + +inst_1:// rs2==f30, imm_val > 0, +// opcode: c.fswsp; op1:x2; op2:f30; op2val:-0x1000001; immval:0xfc; align:0; flagreg:x5; +// valreg: x4; valoffset: 1*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f30,0xfc,1*SIGALIGN,c.fswsp,0,x5,x4,1*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_2:// rs2==f29, imm_val == 84, +// opcode: c.fswsp; op1:x2; op2:f29; op2val:-0x1000001; immval:0x54; align:0; flagreg:x5; +// valreg: x4; valoffset: 2*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f29,0x54,2*SIGALIGN,c.fswsp,0,x5,x4,2*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_3) + +inst_3:// rs2==f28, imm_val == 168, +// opcode: c.fswsp; op1:x2; op2:f28; op2val:-0x1000001; immval:0xa8; align:0; flagreg:x5; +// valreg: x4; valoffset: 3*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f28,0xa8,3*SIGALIGN,c.fswsp,0,x5,x4,3*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_4) + +inst_4:// rs2==f27, imm_val == 248, +// opcode: c.fswsp; op1:x2; op2:f27; op2val:-0x1000001; immval:0xf8; align:0; flagreg:x5; +// valreg: x4; valoffset: 4*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f27,0xf8,4*SIGALIGN,c.fswsp,0,x5,x4,4*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_5) + +inst_5:// rs2==f26, imm_val == 244, +// opcode: c.fswsp; op1:x2; op2:f26; op2val:-0x1000001; immval:0xf4; align:0; flagreg:x5; +// valreg: x4; valoffset: 5*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f26,0xf4,5*SIGALIGN,c.fswsp,0,x5,x4,5*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_6) + +inst_6:// rs2==f25, imm_val == 236, +// opcode: c.fswsp; op1:x2; op2:f25; op2val:-0x1000001; immval:0xec; align:0; flagreg:x5; +// valreg: x4; valoffset: 6*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f25,0xec,6*SIGALIGN,c.fswsp,0,x5,x4,6*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_7) + +inst_7:// rs2==f24, imm_val == 220, +// opcode: c.fswsp; op1:x2; op2:f24; op2val:-0x1000001; immval:0xdc; align:0; flagreg:x5; +// valreg: x4; valoffset: 7*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f24,0xdc,7*SIGALIGN,c.fswsp,0,x5,x4,7*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_8) + +inst_8:// rs2==f23, imm_val == 188, +// opcode: c.fswsp; op1:x2; op2:f23; op2val:-0x1000001; immval:0xbc; align:0; flagreg:x5; +// valreg: x4; valoffset: 8*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f23,0xbc,8*SIGALIGN,c.fswsp,0,x5,x4,8*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_9) + +inst_9:// rs2==f22, imm_val == 124, +// opcode: c.fswsp; op1:x2; op2:f22; op2val:-0x1000001; immval:0x7c; align:0; flagreg:x5; +// valreg: x4; valoffset: 9*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f22,0x7c,9*SIGALIGN,c.fswsp,0,x5,x4,9*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_10) + +inst_10:// rs2==f21, imm_val == 4, +// opcode: c.fswsp; op1:x2; op2:f21; op2val:-0x1000001; immval:0x4; align:0; flagreg:x5; +// valreg: x4; valoffset: 10*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f21,0x4,10*SIGALIGN,c.fswsp,0,x5,x4,10*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_11) + +inst_11:// rs2==f20, imm_val == 8, +// opcode: c.fswsp; op1:x2; op2:f20; op2val:-0x1000001; immval:0x8; align:0; flagreg:x5; +// valreg: x4; valoffset: 11*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f20,0x8,11*SIGALIGN,c.fswsp,0,x5,x4,11*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_12) + +inst_12:// rs2==f19, imm_val == 16, +// opcode: c.fswsp; op1:x2; op2:f19; op2val:-0x1000001; immval:0x10; align:0; flagreg:x5; +// valreg: x4; valoffset: 12*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f19,0x10,12*SIGALIGN,c.fswsp,0,x5,x4,12*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_13) + +inst_13:// rs2==f18, imm_val == 32, +// opcode: c.fswsp; op1:x2; op2:f18; op2val:-0x1000001; immval:0x20; align:0; flagreg:x5; +// valreg: x4; valoffset: 13*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f18,0x20,13*SIGALIGN,c.fswsp,0,x5,x4,13*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_14) + +inst_14:// rs2==f17, imm_val == 64, +// opcode: c.fswsp; op1:x2; op2:f17; op2val:-0x1000001; immval:0x40; align:0; flagreg:x5; +// valreg: x4; valoffset: 14*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f17,0x40,14*SIGALIGN,c.fswsp,0,x5,x4,14*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_15) + +inst_15:// rs2==f16, imm_val == 128, +// opcode: c.fswsp; op1:x2; op2:f16; op2val:-0x1000001; immval:0x80; align:0; flagreg:x5; +// valreg: x4; valoffset: 15*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f16,0x80,15*SIGALIGN,c.fswsp,0,x5,x4,15*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_16) + +inst_16:// rs2==f15, +// opcode: c.fswsp; op1:x2; op2:f15; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 16*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f15,0x0,16*SIGALIGN,c.fswsp,0,x5,x4,16*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_17) + +inst_17:// rs2==f14, +// opcode: c.fswsp; op1:x2; op2:f14; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 17*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f14,0x0,17*SIGALIGN,c.fswsp,0,x5,x4,17*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_18) + +inst_18:// rs2==f13, +// opcode: c.fswsp; op1:x2; op2:f13; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 18*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f13,0x0,18*SIGALIGN,c.fswsp,0,x5,x4,18*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_19) + +inst_19:// rs2==f12, +// opcode: c.fswsp; op1:x2; op2:f12; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 19*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f12,0x0,19*SIGALIGN,c.fswsp,0,x5,x4,19*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_20) + +inst_20:// rs2==f11, +// opcode: c.fswsp; op1:x2; op2:f11; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 20*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f11,0x0,20*SIGALIGN,c.fswsp,0,x5,x4,20*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_21) + +inst_21:// rs2==f10, +// opcode: c.fswsp; op1:x2; op2:f10; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 21*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f10,0x0,21*SIGALIGN,c.fswsp,0,x5,x4,21*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_22) + +inst_22:// rs2==f9, +// opcode: c.fswsp; op1:x2; op2:f9; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 22*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f9,0x0,22*SIGALIGN,c.fswsp,0,x5,x4,22*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_23) + +inst_23:// rs2==f8, +// opcode: c.fswsp; op1:x2; op2:f8; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 23*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f8,0x0,23*SIGALIGN,c.fswsp,0,x5,x4,23*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_24) + +inst_24:// rs2==f7, +// opcode: c.fswsp; op1:x2; op2:f7; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 24*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f7,0x0,24*SIGALIGN,c.fswsp,0,x5,x4,24*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_25) + +inst_25:// rs2==f6, +// opcode: c.fswsp; op1:x2; op2:f6; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 25*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f6,0x0,25*SIGALIGN,c.fswsp,0,x5,x4,25*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_26) + +inst_26:// rs2==f5, +// opcode: c.fswsp; op1:x2; op2:f5; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 26*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f5,0x0,26*SIGALIGN,c.fswsp,0,x5,x4,26*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_27) + +inst_27:// rs2==f4, +// opcode: c.fswsp; op1:x2; op2:f4; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 27*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f4,0x0,27*SIGALIGN,c.fswsp,0,x5,x4,27*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_28) + +inst_28:// rs2==f3, +// opcode: c.fswsp; op1:x2; op2:f3; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 28*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f3,0x0,28*SIGALIGN,c.fswsp,0,x5,x4,28*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_29) + +inst_29:// rs2==f2, +// opcode: c.fswsp; op1:x2; op2:f2; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 29*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f2,0x0,29*SIGALIGN,c.fswsp,0,x5,x4,29*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_30) + +inst_30:// rs2==f1, +// opcode: c.fswsp; op1:x2; op2:f1; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 30*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f1,0x0,30*SIGALIGN,c.fswsp,0,x5,x4,30*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_31) + +inst_31:// rs2==f0, +// opcode: c.fswsp; op1:x2; op2:f0; op2val:-0x80000000; immval:0x0; align:0; flagreg:x5; +// valreg: x4; valoffset: 31*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f0,0x0,31*SIGALIGN,c.fswsp,0,x5,x4,31*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + +test_dataset_1: + +test_dataset_2: + +test_dataset_3: + +test_dataset_4: + +test_dataset_5: + +test_dataset_6: + +test_dataset_7: + +test_dataset_8: + +test_dataset_9: + +test_dataset_10: + +test_dataset_11: + +test_dataset_12: + +test_dataset_13: + +test_dataset_14: + +test_dataset_15: + +test_dataset_16: + +test_dataset_17: + +test_dataset_18: + +test_dataset_19: + +test_dataset_20: + +test_dataset_21: + +test_dataset_22: + +test_dataset_23: + +test_dataset_24: + +test_dataset_25: + +test_dataset_26: + +test_dataset_27: + +test_dataset_28: + +test_dataset_29: + +test_dataset_30: + +test_dataset_31: + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 32*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fld-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fld-01.S new file mode 100644 index 000000000..905d4833c --- /dev/null +++ b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fld-01.S @@ -0,0 +1,173 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 05:06:00 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 64 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fld instruction of the RISC-V RV64FDC extension for the c.fld covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fld) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==x15, rd==f15,imm_val == 0 and fcsr == 0, +// opcode:c.fld; op1:x15; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x15,f15,0x0,c.fld,0,x4) + +inst_1: +// rs1==x14, rd==f14,imm_val > 0 and fcsr == 0, +// opcode:c.fld; op1:x14; dest:f14; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x14,f14,0xf8,c.fld,0,x4) + +inst_2: +// rs1==x13, rd==f13,imm_val == 168, +// opcode:c.fld; op1:x13; dest:f13; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x13,f13,0xa8,c.fld,0,x4) + +inst_3: +// rs1==x12, rd==f12,imm_val == 80, +// opcode:c.fld; op1:x12; dest:f12; immval:0x50; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x12,f12,0x50,c.fld,0,x4) + +inst_4: +// rs1==x11, rd==f11,imm_val == 8, +// opcode:c.fld; op1:x11; dest:f11; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x11,f11,0x8,c.fld,0,x4) + +inst_5: +// rs1==x10, rd==f10,imm_val == 16, +// opcode:c.fld; op1:x10; dest:f10; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x10,f10,0x10,c.fld,0,x4) + +inst_6: +// rs1==x9, rd==f9,imm_val == 240, +// opcode:c.fld; op1:x9; dest:f9; immval:0xf0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x9,f9,0xf0,c.fld,0,x4) + +inst_7: +// rs1==x8, rd==f8,imm_val == 232, +// opcode:c.fld; op1:x8; dest:f8; immval:0xe8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x8,f8,0xe8,c.fld,0,x4) + +inst_8: +// imm_val == 216, +// opcode:c.fld; op1:x15; dest:f15; immval:0xd8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0xd8,c.fld,0,x4) + +inst_9: +// imm_val == 184, +// opcode:c.fld; op1:x15; dest:f15; immval:0xb8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0xb8,c.fld,0,x4) + +inst_10: +// imm_val == 120, +// opcode:c.fld; op1:x15; dest:f15; immval:0x78; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x78,c.fld,0,x4) + +inst_11: +// imm_val == 32, +// opcode:c.fld; op1:x15; dest:f15; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x20,c.fld,0,x4) + +inst_12: +// imm_val == 64, +// opcode:c.fld; op1:x15; dest:f15; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x40,c.fld,0,x4) + +inst_13: +// imm_val == 128, +// opcode:c.fld; op1:x15; dest:f15; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,159,x15,f15,0x80,c.fld,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + + + + + + + + + + + + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fldsp-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fldsp-01.S new file mode 100644 index 000000000..8594fffd0 --- /dev/null +++ b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fldsp-01.S @@ -0,0 +1,247 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 05:06:00 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 64 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fldsp instruction of the RISC-V RV64FDC extension for the c.fldsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fldsp) + +RVTEST_FP_ENABLE() +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rd==f31, imm_val == 0, +// opcode:c.fldsp; op1:x2; dest:f31; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f31,0x0,c.fldsp,0,x4) + +inst_1: +// rd==f30, imm_val > 0, +// opcode:c.fldsp; op1:x2; dest:f30; immval:0x1f8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f30,0x1f8,c.fldsp,0,x4) + +inst_2: +// rd==f29, imm_val == 168, +// opcode:c.fldsp; op1:x2; dest:f29; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f29,0xa8,c.fldsp,0,x4) + +inst_3: +// rd==f28, imm_val == 336, +// opcode:c.fldsp; op1:x2; dest:f28; immval:0x150; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f28,0x150,c.fldsp,0,x4) + +inst_4: +// rd==f27, imm_val == 496, +// opcode:c.fldsp; op1:x2; dest:f27; immval:0x1f0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f27,0x1f0,c.fldsp,0,x4) + +inst_5: +// rd==f26, imm_val == 488, +// opcode:c.fldsp; op1:x2; dest:f26; immval:0x1e8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f26,0x1e8,c.fldsp,0,x4) + +inst_6: +// rd==f25, imm_val == 472, +// opcode:c.fldsp; op1:x2; dest:f25; immval:0x1d8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f25,0x1d8,c.fldsp,0,x4) + +inst_7: +// rd==f24, imm_val == 440, +// opcode:c.fldsp; op1:x2; dest:f24; immval:0x1b8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f24,0x1b8,c.fldsp,0,x4) + +inst_8: +// rd==f23, imm_val == 376, +// opcode:c.fldsp; op1:x2; dest:f23; immval:0x178; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f23,0x178,c.fldsp,0,x4) + +inst_9: +// rd==f22, imm_val == 248, +// opcode:c.fldsp; op1:x2; dest:f22; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f22,0xf8,c.fldsp,0,x4) + +inst_10: +// rd==f21, imm_val == 8, +// opcode:c.fldsp; op1:x2; dest:f21; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f21,0x8,c.fldsp,0,x4) + +inst_11: +// rd==f20, imm_val == 16, +// opcode:c.fldsp; op1:x2; dest:f20; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f20,0x10,c.fldsp,0,x4) + +inst_12: +// rd==f19, imm_val == 32, +// opcode:c.fldsp; op1:x2; dest:f19; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f19,0x20,c.fldsp,0,x4) + +inst_13: +// rd==f18, imm_val == 64, +// opcode:c.fldsp; op1:x2; dest:f18; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f18,0x40,c.fldsp,0,x4) + +inst_14: +// rd==f17, imm_val == 128, +// opcode:c.fldsp; op1:x2; dest:f17; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f17,0x80,c.fldsp,0,x4) + +inst_15: +// rd==f16, imm_val == 256, +// opcode:c.fldsp; op1:x2; dest:f16; immval:0x100; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f16,0x100,c.fldsp,0,x4) + +inst_16: +// rd==f15, +// opcode:c.fldsp; op1:x2; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f15,0x0,c.fldsp,0,x4) + +inst_17: +// rd==f14, +// opcode:c.fldsp; op1:x2; dest:f14; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f14,0x0,c.fldsp,0,x4) + +inst_18: +// rd==f13, +// opcode:c.fldsp; op1:x2; dest:f13; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f13,0x0,c.fldsp,0,x4) + +inst_19: +// rd==f12, +// opcode:c.fldsp; op1:x2; dest:f12; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f12,0x0,c.fldsp,0,x4) + +inst_20: +// rd==f11, +// opcode:c.fldsp; op1:x2; dest:f11; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f11,0x0,c.fldsp,0,x4) + +inst_21: +// rd==f10, +// opcode:c.fldsp; op1:x2; dest:f10; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f10,0x0,c.fldsp,0,x4) + +inst_22: +// rd==f9, +// opcode:c.fldsp; op1:x2; dest:f9; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f9,0x0,c.fldsp,0,x4) + +inst_23: +// rd==f8, +// opcode:c.fldsp; op1:x2; dest:f8; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f8,0x0,c.fldsp,0,x4) + +inst_24: +// rd==f7, +// opcode:c.fldsp; op1:x2; dest:f7; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f7,0x0,c.fldsp,0,x4) + +inst_25: +// rd==f6, +// opcode:c.fldsp; op1:x2; dest:f6; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f6,0x0,c.fldsp,0,x4) + +inst_26: +// rd==f5, +// opcode:c.fldsp; op1:x2; dest:f5; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f5,0x0,c.fldsp,0,x4) + +inst_27: +// rd==f4, +// opcode:c.fldsp; op1:x2; dest:f4; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f4,0x0,c.fldsp,0,x4) + +inst_28: +// rd==f3, +// opcode:c.fldsp; op1:x2; dest:f3; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f3,0x0,c.fldsp,0,x4) + +inst_29: +// rd==f2, +// opcode:c.fldsp; op1:x2; dest:f2; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f2,0x0,c.fldsp,0,x4) + +inst_30: +// rd==f1, +// opcode:c.fldsp; op1:x2; dest:f1; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f1,0x0,c.fldsp,0,x4) + +inst_31: +// rd==f0, +// opcode:c.fldsp; op1:x2; dest:f0; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x3,0,x2,f0,0x0,c.fldsp,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsd-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsd-01.S new file mode 100644 index 000000000..b09cc9731 --- /dev/null +++ b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsd-01.S @@ -0,0 +1,213 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 05:06:00 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 64 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsd instruction of the RISC-V RV64FDC extension for the c.fsd covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fsd) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs1 != rs2, rs1==x15, rs2==f15,imm_val == 0, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0x0; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 0*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x0,0*SIGALIGN,c.fsd,0,x4,x3, 0*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_1) + +inst_1:// rs1==x14, rs2==f14,imm_val > 0, +// opcode: c.fsd; op1:x14; op2:f14; op2val:-0x1; immval:0xf8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 1*FLEN/8; +TEST_STORE_F(x1,x2,0,x14,f14,0xf8,2*SIGALIGN,c.fsd,0,x4,x3, 1*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_2) + +inst_2:// rs1==x13, rs2==f13,imm_val == 168, +// opcode: c.fsd; op1:x13; op2:f13; op2val:-0x1; immval:0xa8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 2*FLEN/8; +TEST_STORE_F(x1,x2,0,x13,f13,0xa8,4*SIGALIGN,c.fsd,0,x4,x3, 2*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_3) + +inst_3:// rs1==x12, rs2==f12,imm_val == 80, +// opcode: c.fsd; op1:x12; op2:f12; op2val:-0x1; immval:0x50; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 3*FLEN/8; +TEST_STORE_F(x1,x2,0,x12,f12,0x50,6*SIGALIGN,c.fsd,0,x4,x3, 3*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_4) + +inst_4:// rs1==x11, rs2==f11,imm_val == 8, +// opcode: c.fsd; op1:x11; op2:f11; op2val:-0x1; immval:0x8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 4*FLEN/8; +TEST_STORE_F(x1,x2,0,x11,f11,0x8,8*SIGALIGN,c.fsd,0,x4,x3, 4*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_5) + +inst_5:// rs1==x10, rs2==f10,imm_val == 16, +// opcode: c.fsd; op1:x10; op2:f10; op2val:-0x1; immval:0x10; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 5*FLEN/8; +TEST_STORE_F(x1,x2,0,x10,f10,0x10,10*SIGALIGN,c.fsd,0,x4,x3, 5*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_6) + +inst_6:// rs1==x9, rs2==f9,imm_val == 240, +// opcode: c.fsd; op1:x9; op2:f9; op2val:-0x1; immval:0xf0; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 6*FLEN/8; +TEST_STORE_F(x1,x2,0,x9,f9,0xf0,12*SIGALIGN,c.fsd,0,x4,x3, 6*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_7) + +inst_7:// rs1==x8, rs2==f8,imm_val == 232, +// opcode: c.fsd; op1:x8; op2:f8; op2val:-0x1; immval:0xe8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 7*FLEN/8; +TEST_STORE_F(x1,x2,0,x8,f8,0xe8,14*SIGALIGN,c.fsd,0,x4,x3, 7*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_8) + +inst_8:// imm_val == 216, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0xd8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 8*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0xd8,16*SIGALIGN,c.fsd,0,x4,x3, 8*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_9) + +inst_9:// imm_val == 184, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0xb8; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 9*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0xb8,18*SIGALIGN,c.fsd,0,x4,x3, 9*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_10) + +inst_10:// imm_val == 120, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0x78; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 10*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x78,20*SIGALIGN,c.fsd,0,x4,x3, 10*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_11) + +inst_11:// imm_val == 32, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0x20; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 11*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x20,22*SIGALIGN,c.fsd,0,x4,x3, 11*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_12) + +inst_12:// imm_val == 64, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0x40; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 12*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x40,24*SIGALIGN,c.fsd,0,x4,x3, 12*FLEN/8) +RVTEST_VALBASEUPD(x3,test_dataset_13) + +inst_13:// imm_val == 128, +// opcode: c.fsd; op1:x15; op2:f15; op2val:-0x1; immval:0x80; align:$ea_align; flagreg:x4; +// valreg: x3; valoffset: 13*FLEN/8; +TEST_STORE_F(x1,x2,0,x15,f15,0x80,26*SIGALIGN,c.fsd,0,x4,x3, 13*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + +test_dataset_1: + + +test_dataset_2: + + +test_dataset_3: + + +test_dataset_4: + + +test_dataset_5: + + +test_dataset_6: + + +test_dataset_7: + + +test_dataset_8: + + +test_dataset_9: + + +test_dataset_10: + + +test_dataset_11: + + +test_dataset_12: + + +test_dataset_13: + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsdsp-01.S b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsdsp-01.S new file mode 100644 index 000000000..51ba670e0 --- /dev/null +++ b/riscv-test-suite/rv64i_m/D_Zcd/src/c.fsdsp-01.S @@ -0,0 +1,343 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Aug 16 05:06:00 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/riscv/riscv-ctg/sample_cgfs/RV32C/fld.cgf \ + \ +// -- xlen 64 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsdsp instruction of the RISC-V RV64FDC extension for the c.fsdsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*C.*);def TEST_CASE_1=True;",c.fsdsp) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x4,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0:// rs2==f31, imm_val == 0, +// opcode: c.fsdsp; op1:x2; op2:f31; op2val:-0x1; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 0*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f31,0x0,0*SIGALIGN,c.fsdsp,0,x5,x4,0*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_1) + +inst_1:// rs2==f30, imm_val > 0, +// opcode: c.fsdsp; op1:x2; op2:f30; op2val:-0x1; immval:0x1f8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 1*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f30,0x1f8,2*SIGALIGN,c.fsdsp,0,x5,x4,1*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_2) + +inst_2:// rs2==f29, imm_val == 168, +// opcode: c.fsdsp; op1:x2; op2:f29; op2val:-0x1; immval:0xa8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 2*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f29,0xa8,4*SIGALIGN,c.fsdsp,0,x5,x4,2*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_3) + +inst_3:// rs2==f28, imm_val == 336, +// opcode: c.fsdsp; op1:x2; op2:f28; op2val:-0x1; immval:0x150; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 3*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f28,0x150,6*SIGALIGN,c.fsdsp,0,x5,x4,3*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_4) + +inst_4:// rs2==f27, imm_val == 496, +// opcode: c.fsdsp; op1:x2; op2:f27; op2val:-0x1; immval:0x1f0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 4*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f27,0x1f0,8*SIGALIGN,c.fsdsp,0,x5,x4,4*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_5) + +inst_5:// rs2==f26, imm_val == 488, +// opcode: c.fsdsp; op1:x2; op2:f26; op2val:-0x1; immval:0x1e8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 5*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f26,0x1e8,10*SIGALIGN,c.fsdsp,0,x5,x4,5*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_6) + +inst_6:// rs2==f25, imm_val == 472, +// opcode: c.fsdsp; op1:x2; op2:f25; op2val:-0x1; immval:0x1d8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 6*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f25,0x1d8,12*SIGALIGN,c.fsdsp,0,x5,x4,6*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_7) + +inst_7:// rs2==f24, imm_val == 440, +// opcode: c.fsdsp; op1:x2; op2:f24; op2val:-0x1; immval:0x1b8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 7*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f24,0x1b8,14*SIGALIGN,c.fsdsp,0,x5,x4,7*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_8) + +inst_8:// rs2==f23, imm_val == 376, +// opcode: c.fsdsp; op1:x2; op2:f23; op2val:-0x1; immval:0x178; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 8*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f23,0x178,16*SIGALIGN,c.fsdsp,0,x5,x4,8*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_9) + +inst_9:// rs2==f22, imm_val == 248, +// opcode: c.fsdsp; op1:x2; op2:f22; op2val:-0x1; immval:0xf8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 9*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f22,0xf8,18*SIGALIGN,c.fsdsp,0,x5,x4,9*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_10) + +inst_10:// rs2==f21, imm_val == 8, +// opcode: c.fsdsp; op1:x2; op2:f21; op2val:-0x1; immval:0x8; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 10*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f21,0x8,20*SIGALIGN,c.fsdsp,0,x5,x4,10*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_11) + +inst_11:// rs2==f20, imm_val == 16, +// opcode: c.fsdsp; op1:x2; op2:f20; op2val:-0x1; immval:0x10; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 11*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f20,0x10,22*SIGALIGN,c.fsdsp,0,x5,x4,11*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_12) + +inst_12:// rs2==f19, imm_val == 32, +// opcode: c.fsdsp; op1:x2; op2:f19; op2val:-0x1; immval:0x20; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 12*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f19,0x20,24*SIGALIGN,c.fsdsp,0,x5,x4,12*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_13) + +inst_13:// rs2==f18, imm_val == 64, +// opcode: c.fsdsp; op1:x2; op2:f18; op2val:-0x1; immval:0x40; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 13*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f18,0x40,26*SIGALIGN,c.fsdsp,0,x5,x4,13*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_14) + +inst_14:// rs2==f17, imm_val == 128, +// opcode: c.fsdsp; op1:x2; op2:f17; op2val:-0x1; immval:0x80; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 14*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f17,0x80,28*SIGALIGN,c.fsdsp,0,x5,x4,14*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_15) + +inst_15:// rs2==f16, imm_val == 256, +// opcode: c.fsdsp; op1:x2; op2:f16; op2val:-0x1; immval:0x100; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 15*FLEN/8 +TEST_STORE_F(x1,x3,159,x2,f16,0x100,30*SIGALIGN,c.fsdsp,0,x5,x4,15*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_16) + +inst_16:// rs2==f15, +// opcode: c.fsdsp; op1:x2; op2:f15; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 16*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f15,0x0,32*SIGALIGN,c.fsdsp,0,x5,x4,16*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_17) + +inst_17:// rs2==f14, +// opcode: c.fsdsp; op1:x2; op2:f14; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 17*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f14,0x0,34*SIGALIGN,c.fsdsp,0,x5,x4,17*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_18) + +inst_18:// rs2==f13, +// opcode: c.fsdsp; op1:x2; op2:f13; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 18*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f13,0x0,36*SIGALIGN,c.fsdsp,0,x5,x4,18*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_19) + +inst_19:// rs2==f12, +// opcode: c.fsdsp; op1:x2; op2:f12; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 19*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f12,0x0,38*SIGALIGN,c.fsdsp,0,x5,x4,19*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_20) + +inst_20:// rs2==f11, +// opcode: c.fsdsp; op1:x2; op2:f11; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 20*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f11,0x0,40*SIGALIGN,c.fsdsp,0,x5,x4,20*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_21) + +inst_21:// rs2==f10, +// opcode: c.fsdsp; op1:x2; op2:f10; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 21*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f10,0x0,42*SIGALIGN,c.fsdsp,0,x5,x4,21*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_22) + +inst_22:// rs2==f9, +// opcode: c.fsdsp; op1:x2; op2:f9; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 22*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f9,0x0,44*SIGALIGN,c.fsdsp,0,x5,x4,22*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_23) + +inst_23:// rs2==f8, +// opcode: c.fsdsp; op1:x2; op2:f8; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 23*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f8,0x0,46*SIGALIGN,c.fsdsp,0,x5,x4,23*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_24) + +inst_24:// rs2==f7, +// opcode: c.fsdsp; op1:x2; op2:f7; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 24*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f7,0x0,48*SIGALIGN,c.fsdsp,0,x5,x4,24*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_25) + +inst_25:// rs2==f6, +// opcode: c.fsdsp; op1:x2; op2:f6; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 25*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f6,0x0,50*SIGALIGN,c.fsdsp,0,x5,x4,25*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_26) + +inst_26:// rs2==f5, +// opcode: c.fsdsp; op1:x2; op2:f5; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 26*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f5,0x0,52*SIGALIGN,c.fsdsp,0,x5,x4,26*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_27) + +inst_27:// rs2==f4, +// opcode: c.fsdsp; op1:x2; op2:f4; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 27*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f4,0x0,54*SIGALIGN,c.fsdsp,0,x5,x4,27*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_28) + +inst_28:// rs2==f3, +// opcode: c.fsdsp; op1:x2; op2:f3; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 28*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f3,0x0,56*SIGALIGN,c.fsdsp,0,x5,x4,28*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_29) + +inst_29:// rs2==f2, +// opcode: c.fsdsp; op1:x2; op2:f2; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 29*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f2,0x0,58*SIGALIGN,c.fsdsp,0,x5,x4,29*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_30) + +inst_30:// rs2==f1, +// opcode: c.fsdsp; op1:x2; op2:f1; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 30*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f1,0x0,60*SIGALIGN,c.fsdsp,0,x5,x4,30*FLEN/8) +RVTEST_VALBASEUPD(x4,test_dataset_31) + +inst_31:// rs2==f0, +// opcode: c.fsdsp; op1:x2; op2:f0; op2val:0x0; immval:0x0; align:0; flagreg:x5; +// valreg: x4 ; valoffset: 31*FLEN/8 +TEST_STORE_F(x1,x3,0,x2,f0,0x0,62*SIGALIGN,c.fsdsp,0,x5,x4,31*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + +test_dataset_1: + +test_dataset_2: + +test_dataset_3: + +test_dataset_4: + +test_dataset_5: + +test_dataset_6: + +test_dataset_7: + +test_dataset_8: + +test_dataset_9: + +test_dataset_10: + +test_dataset_11: + +test_dataset_12: + +test_dataset_13: + +test_dataset_14: + +test_dataset_15: + +test_dataset_16: + +test_dataset_17: + +test_dataset_18: + +test_dataset_19: + +test_dataset_20: + +test_dataset_21: + +test_dataset_22: + +test_dataset_23: + +test_dataset_24: + +test_dataset_25: + +test_dataset_26: + +test_dataset_27: + +test_dataset_28: + +test_dataset_29: + +test_dataset_30: + +test_dataset_31: + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 64*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END