diff --git a/CHANGELOG.md b/CHANGELOG.md
index 2f0e3f5ee..3a3d8e6af 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,4 +1,8 @@
 # CHANGELOG
+
+## [3.6.2] - 2023-02-08
+- Remove RV64IB from ISA list of zext test. 
+
 ## [3.6.1] - 2023-01-28
 - Fix satp restore condition.
 
diff --git a/riscv-test-suite/rv64i_m/B/src/zext.h-01.S b/riscv-test-suite/rv64i_m/B/src/zext.h-01.S
index 00a405377..594d5fbf0 100644
--- a/riscv-test-suite/rv64i_m/B/src/zext.h-01.S
+++ b/riscv-test-suite/rv64i_m/B/src/zext.h-01.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV64IB,RV64IZbb")
+RVTEST_ISA("RV64IZbb")
 
 .section .text.init
 .globl rvtest_entry_point