diff --git a/coverage/pmp32_coverpoint_def_format.cgf b/coverage/pmp32_coverpoint_def_format.cgf deleted file mode 100644 index ee302b954..000000000 --- a/coverage/pmp32_coverpoint_def_format.cgf +++ /dev/null @@ -1,702 +0,0 @@ -#Load access fault --> ${CAUSE_LOAD_ACCESS} -#Store access fault --> ${CAUSE_STORE_ACCESS} -#Fetch access fault --> ${CAUSE_FETCH_ACCESS} -PMP_NAPOT_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - #0x99 & 0xF9 = 0x99 | 0x9A & 0xF9 = 0x98 | 0x9C & 0xF9 = 0x98 - ((pmpcfg0 >> 8) & {0x99, 0x9A, 0x9C}) == (0xF9 & $1): 0 #No write, Execute permission - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - pmpaddr{0 ... 3} != 0 and ((old("pmpaddr$1")) ^ (pmpaddr$1) != 0x00): 0 #pmpaddr have been updated - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #Check the napot region is accessed at least once - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x99) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x99, 0x9A, 0x9C}) == (0xFC & $1): 0 #No Read, Write permission - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - pmpaddr{0 ... 3} != 0 and ((old("pmpaddr$1")) ^ (pmpaddr$1) != 0x00): 0 #pmpaddr have been updated - val_comb: - # Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #read, write fault - #Check the napot region is accessed at least once - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x99, 0x9A, 0x9C}) == (0xFB & $1): 0 #No Execute permission - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - pmpaddr{0 ... 3} != 0 and ((old("pmpaddr$1")) ^ (pmpaddr$1) != 0x00): 0 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #Check the napot region is accessed at least once - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x99, 0x9A, 0x9C}) == (0xFD & $1): 0 #No Write permission - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - pmpaddr{0 ... 3} != 0 and ((old("pmpaddr$1")) ^ (pmpaddr$1) != 0x00): 0 #pmpaddr have been updated - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No read, Execute fault - mode == 'M' and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - #Check the napot region is accessed at least once - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_rwx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x9C, 0x9A, 0x99}) == (0xFF & $1): 0 #All permissions given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write or execute fault - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9F) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_TOR_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 16) & {0x8C, 0x8A, 0x89}) == (0x89 & $1): 0 #Only Read Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - '(mnemonic == "lw" or mnemonic == "sw") and (((pmpcfg0 >> 16) & 0x9F == 0x89) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)))': 0 - -PMP_TOR_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 16) & {0x8C, 0x8A, 0x89}) == (0x8C & $1): 0 #Only Execute Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #Read, Write fault - #check for the read, write access - '(mnemonic == "lw" or mnemonic == "sw") and (((pmpcfg0 >> 16) & 0x9F == 0x8C) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)))': 0 - -PMP_TOR_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 16) & {0x9C, 0x9A, 0x99}) == (0x8B & $1): 0 #Only Read, Write Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - '(mnemonic == "lw" or mnemonic == "sw") and (((pmpcfg0 >> 16) & 0x9F == 0x8B) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)))': 0 - -PMP_TOR_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 16) & {0x8C, 0x8A, 0x89}) == (0x8D & $1): 0 #Only Read, Execute Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No read, execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - #check for the read, write access - '(mnemonic == "lw" or mnemonic == "sw") and (((pmpcfg0 >> 16) & 0x9F == 0x8D) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)))': 0 - -PMP_TOR_rwx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 16) & {0x9C, 0x9A, 0x99}) == (0x8F & $1): 0 #Only Read, Write Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write, execute fault - '(mnemonic == "lw" or mnemonic == "sw") and (((pmpcfg0 >> 16) & 0x9F == 0x8F) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)))': 0 - -PMP_NA4_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x91 & $1): 0 #Only Read Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the read, write access - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 - -PMP_NA4_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x94 & $1): 0 #Only Execute Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #read, write fault - #check for the read, write access - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 - -PMP_NA4_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x93 & $1): 0 #Only Read, Write Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the read, write access - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 - -PMP_NA4_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x95 & $1): 0 #Only Read, Execute Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No read, execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #write fault - #check for the read, write access - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 - -PMP_NA4_rwx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x97 & $1): 0 #Only Read, Write, Execute Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, execute fault - #check for the read, write access - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x97) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 - -PMP_TOR_priority_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x89 & $1): 0 #Read Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.P0) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x89) and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 << 2))': 0 - -PMP_TOR_priority_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8C & $1): 0 #Read Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.P0) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #read, write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x8C) and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 << 2))': 0 - -PMP_TOR_priority_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8B & $1): 0 #Read, Write Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.P0) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x8B) and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 << 2))': 0 - -PMP_TOR_priority_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8D & $1): 0 #Read, Execute Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.P0) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No read, execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x8D) and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 << 2))': 0 - -PMP_TOR_priority_r_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x8C, 0x8A, 0x89}) == (0x89 & $1): 0 #Read Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 0, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x89) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 - -PMP_TOR_priority_rw_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x8C, 0x8A, 0x89}) == (0x8B & $1): 0 #Read, Write Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 0, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8B) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 - -PMP_TOR_priority_x_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x8C, 0x8A, 0x89}) == (0x8C & $1): 0 #Execute Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 0, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #read, write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8C) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 - -PMP_TOR_priority_rx_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x8C, 0x8A, 0x89}) == (0x8D & $1): 0 #Read, Execute Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 0, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_FETCH_ACCESS}}): 0 #No read, execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8D) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 - -PMP_TOR_priority_rwx_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Execute Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 0, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_FETCH_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8F) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 - -PMP_NAPOT_priority_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x9C, 0x9A, 0x99}) == (0x99 & $1): 0 #Read Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x99) and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_priority_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x9C, 0x9A, 0x99}) == (0x9B & $1): 0 #Read, Write Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x9B) and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_priority_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x9C, 0x9A, 0x99}) == (0x9C & $1): 0 #Execute Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No Execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #read, write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x9C) and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_priority_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x9C, 0x9A, 0x99}) == (0x9D & $1): 0 #Read, Execute Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No Read, Execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x9D) and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_priority_r_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x9C, 0x9A, 0x99}) == (0x99 & $1): 0 #Read Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x99) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_priority_rw_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x9C, 0x9A, 0x99}) == (0x9B & $1): 0 #Read, Write Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_priority_x_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x9C, 0x9A, 0x99}) == (0x9C & $1): 0 #Execute Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #Read, write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_priority_rx_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x9C, 0x9A, 0x99}) == (0x9D & $1): 0 #Read, Execute Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No read, execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Read, write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NA4_priority_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x94, 0x92, 0x91}) == (0x91 & $1): 0 #Read Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No Read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr3 << 2))' : 0 - -PMP_NA4_priority_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x94, 0x92, 0x91}) == (0x93 & $1): 0 #Read, Write Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No Read, Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr3 << 2))' : 0 - -PMP_NA4_priority_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x94, 0x92, 0x91}) == (0x94 & $1): 0 #Execute Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No Execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #Read, Write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr3 << 2))' : 0 - -PMP_NA4_priority_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x94, 0x92, 0x91}) == (0x95 & $1): 0 #Read, Execute Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No Read, Execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr3 << 2))' : 0 - -PMP_NA4_priority_r_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x91 & $1): 0 #Read Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No Read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr1 << 2))' : 0 - -PMP_NA4_priority_rw_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x93 & $1): 0 #Read, Write Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No Read, Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr1 << 2))' : 0 - -PMP_NA4_priority_x_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x94 & $1): 0 #Execute Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No Execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #Read, Write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr1 << 2))' : 0 - -PMP_NA4_priority_rx_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x95 & $1): 0 #Read, Execute Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS},${CAUSE_FETCH_ACCESS}}): 0 #No Read, Execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr1 << 2))' : 0 - -pmp_cfg_locked_write_unrelated: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - (pmpcfg{0 ... 3} >> {0, 8, 16, 24} & 0x80 == 0x80) and ((old("pmpcfg$1") & (0xFF << $2)) ^ (pmpcfg$1 & (0xFF << $2)) == 0x00) and old("pmpcfg$1") != 0: 0 - ((old("pmpaddr{0 ... 15}")) ^ (pmpaddr$1) == 0x00) and (pmpcfg{0,1,2,3}{[$1/4]} >> {0, 8, 16, 24}{[$1/4]} & 0x80 == 0x80): 0 - -PMP_access_permission: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - mode == 'M' and (((old("pmpcfg{0 ... 3}") ^ (pmpcfg$1)) != 0x00) and pmpcfg$1 != 0x0): 0 #pmpcfg successfully updated in M mode - mode == 'M' and (((old("pmpaddr{0 ... 15}") ^ (pmpaddr$1)) != 0x00) and pmpaddr$1 != 0x0): 0 #pmpaddr successfully updated in M mode - val_comb: - mnemonic == {"csrrs", "csrrw"} and mode == {'S', 'U'} and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}: 0 #check for illegal instruction fault \ No newline at end of file diff --git a/coverage/pmp32_translated_coverpoints.cgf b/coverage/pmp32_translated_coverpoints.cgf deleted file mode 100644 index 06896515c..000000000 --- a/coverage/pmp32_translated_coverpoints.cgf +++ /dev/null @@ -1,1423 +0,0 @@ -PMP_NA4_priority_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x91) == (0x91 & 0x91): 0 - ((pmpcfg0 >> 24) & 0x92) == (0x91 & 0x92): 0 - ((pmpcfg0 >> 24) & 0x94) == (0x91 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr3 << 2)): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_priority_r_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x91) == (0x91 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x91 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x91 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_priority_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x91) == (0x93 & 0x91): 0 - ((pmpcfg0 >> 24) & 0x92) == (0x93 & 0x92): 0 - ((pmpcfg0 >> 24) & 0x94) == (0x93 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr3 << 2)): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NA4_priority_rw_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x91) == (0x93 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x93 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x93 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NA4_priority_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x91) == (0x95 & 0x91): 0 - ((pmpcfg0 >> 24) & 0x92) == (0x95 & 0x92): 0 - ((pmpcfg0 >> 24) & 0x94) == (0x95 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr3 << 2)): 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_priority_rx_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x91) == (0x95 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x95 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x95 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_priority_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x91) == (0x94 & 0x91): 0 - ((pmpcfg0 >> 24) & 0x92) == (0x94 & 0x92): 0 - ((pmpcfg0 >> 24) & 0x94) == (0x94 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr3 << 2)): 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_priority_x_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x91) == (0x94 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x94 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x94 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x91) == (0x91 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x91 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x91 & 0x94): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x91) == (0x93 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x93 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x93 & 0x94): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NA4_rwx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x91) == (0x97 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x97 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x97 & 0x94): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x97) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NA4_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x91) == (0x95 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x95 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x95 & 0x94): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x91) == (0x94 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x94 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x94 & 0x94): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NAPOT_priority_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x99) == (0x99 & 0x99): 0 - ((pmpcfg0 >> 24) & 0x9A) == (0x99 & 0x9A): 0 - ((pmpcfg0 >> 24) & 0x9C) == (0x99 & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x99) - and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 - << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NAPOT_priority_r_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x99) == (0x99 & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0x99 & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0x99 & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x99) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NAPOT_priority_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x99) == (0x9B & 0x99): 0 - ((pmpcfg0 >> 24) & 0x9A) == (0x9B & 0x9A): 0 - ((pmpcfg0 >> 24) & 0x9C) == (0x9B & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x9B) - and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 - << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NAPOT_priority_rw_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x99) == (0x9B & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0x9B & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0x9B & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NAPOT_priority_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x99) == (0x9D & 0x99): 0 - ((pmpcfg0 >> 24) & 0x9A) == (0x9D & 0x9A): 0 - ((pmpcfg0 >> 24) & 0x9C) == (0x9D & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x9D) - and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 - << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NAPOT_priority_rx_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x99) == (0x9D & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0x9D & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0x9D & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NAPOT_priority_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x99) == (0x9C & 0x99): 0 - ((pmpcfg0 >> 24) & 0x9A) == (0x9C & 0x9A): 0 - ((pmpcfg0 >> 24) & 0x9C) == (0x9C & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x9C) - and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 - << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NAPOT_priority_x_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x99) == (0x9C & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0x9C & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0x9C & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NAPOT_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x99) == (0xF9 & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0xF9 & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0xF9 & 0x9C): 0 - pmpaddr0 != 0 and ((old("pmpaddr0")) ^ (pmpaddr0) != 0x00): 0 - pmpaddr1 != 0 and ((old("pmpaddr1")) ^ (pmpaddr1) != 0x00): 0 - pmpaddr2 != 0 and ((old("pmpaddr2")) ^ (pmpaddr2) != 0x00): 0 - pmpaddr3 != 0 and ((old("pmpaddr3")) ^ (pmpaddr3) != 0x00): 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x99) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x01): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x05): 0 -PMP_NAPOT_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x99) == (0xFB & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0xFB & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0xFB & 0x9C): 0 - pmpaddr0 != 0 and ((old("pmpaddr0")) ^ (pmpaddr0) != 0x00): 0 - pmpaddr1 != 0 and ((old("pmpaddr1")) ^ (pmpaddr1) != 0x00): 0 - pmpaddr2 != 0 and ((old("pmpaddr2")) ^ (pmpaddr2) != 0x00): 0 - pmpaddr3 != 0 and ((old("pmpaddr3")) ^ (pmpaddr3) != 0x00): 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NAPOT_rwx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x99) == (0xFF & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0xFF & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0xFF & 0x9C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9F) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NAPOT_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x99) == (0xFD & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0xFD & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0xFD & 0x9C): 0 - pmpaddr0 != 0 and ((old("pmpaddr0")) ^ (pmpaddr0) != 0x00): 0 - pmpaddr1 != 0 and ((old("pmpaddr1")) ^ (pmpaddr1) != 0x00): 0 - pmpaddr2 != 0 and ((old("pmpaddr2")) ^ (pmpaddr2) != 0x00): 0 - pmpaddr3 != 0 and ((old("pmpaddr3")) ^ (pmpaddr3) != 0x00): 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 -PMP_NAPOT_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x99) == (0xFC & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0xFC & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0xFC & 0x9C): 0 - pmpaddr0 != 0 and ((old("pmpaddr0")) ^ (pmpaddr0) != 0x00): 0 - pmpaddr1 != 0 and ((old("pmpaddr1")) ^ (pmpaddr1) != 0x00): 0 - pmpaddr2 != 0 and ((old("pmpaddr2")) ^ (pmpaddr2) != 0x00): 0 - pmpaddr3 != 0 and ((old("pmpaddr3")) ^ (pmpaddr3) != 0x00): 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x01): 0 -PMP_TOR_priority_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x89 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x89 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x89 & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x89) - and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 - << 2)) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_TOR_priority_r_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x89) == (0x89 & 0x89): 0 - ((pmpcfg0 >> 8) & 0x8A) == (0x89 & 0x8A): 0 - ((pmpcfg0 >> 8) & 0x8C) == (0x89 & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x89) and - (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << - 2)) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_TOR_priority_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x8B & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x8B & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x8B & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x8B) - and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 - << 2)) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_TOR_priority_rw_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x89) == (0x8B & 0x89): 0 - ((pmpcfg0 >> 8) & 0x8A) == (0x8B & 0x8A): 0 - ((pmpcfg0 >> 8) & 0x8C) == (0x8B & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8B) and - (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << - 2)) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_TOR_priority_rwx_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg0 >> 8) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg0 >> 8) & 0x8C) == (0x8F & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8F) and - (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << - 2)) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_TOR_priority_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x8D & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x8D & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x8D & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x8D) - and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 - << 2)) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_TOR_priority_rx_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x89) == (0x8D & 0x89): 0 - ((pmpcfg0 >> 8) & 0x8A) == (0x8D & 0x8A): 0 - ((pmpcfg0 >> 8) & 0x8C) == (0x8D & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8D) and - (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << - 2)) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_TOR_priority_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x8C & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x8C & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x8C & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x8C) - and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 - << 2)) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_TOR_priority_x_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x89) == (0x8C & 0x89): 0 - ((pmpcfg0 >> 8) & 0x8A) == (0x8C & 0x8A): 0 - ((pmpcfg0 >> 8) & 0x8C) == (0x8C & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8C) and - (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << - 2)) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_TOR_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 16) & 0x99) == (0x89 & 0x99): 0 - ((pmpcfg0 >> 16) & 0x9A) == (0x89 & 0x9A): 0 - ((pmpcfg0 >> 16) & 0x9C) == (0x89 & 0x9C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ('((pmpcfg0 >> 16) & 0x9F == 0x89) - and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 - << 2))') - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x01): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x05): 0 -PMP_TOR_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 16) & 0x99) == (0x8B & 0x99): 0 - ((pmpcfg0 >> 16) & 0x9A) == (0x8B & 0x9A): 0 - ((pmpcfg0 >> 16) & 0x9C) == (0x8B & 0x9C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ('((pmpcfg0 >> 16) & 0x9F == 0x89) - and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 - << 2))') - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_TOR_rwx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 16) & 0x99) == (0x8F & 0x99): 0 - ((pmpcfg0 >> 16) & 0x9A) == (0x8F & 0x9A): 0 - ((pmpcfg0 >> 16) & 0x9C) == (0x8F & 0x9C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ('((pmpcfg0 >> 16) & 0x9F == 0x8F) - and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 - << 2))') - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_TOR_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 16) & 0x89) == (0x8D & 0x89): 0 - ((pmpcfg0 >> 16) & 0x8A) == (0x8D & 0x8A): 0 - ((pmpcfg0 >> 16) & 0x8C) == (0x8D & 0x8C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ('((pmpcfg0 >> 16) & 0x9F == 0x8D) - and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 - << 2))') - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_TOR_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 16) & 0x89) == (0x8C & 0x89): 0 - ((pmpcfg0 >> 16) & 0x8A) == (0x8C & 0x8A): 0 - ((pmpcfg0 >> 16) & 0x8C) == (0x8C & 0x8C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ('((pmpcfg0 >> 16) & 0x9F == 0x8C) - and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 - << 2))') - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_access_permission: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - mode == 'M' and (((old("pmpaddr0") ^ (pmpaddr0)) != 0x00) and pmpaddr0 != 0x0): 0 - mode == 'M' and (((old("pmpaddr1") ^ (pmpaddr1)) != 0x00) and pmpaddr1 != 0x0): 0 - mode == 'M' and (((old("pmpaddr10") ^ (pmpaddr10)) != 0x00) and pmpaddr10 != 0x0): 0 - mode == 'M' and (((old("pmpaddr11") ^ (pmpaddr11)) != 0x00) and pmpaddr11 != 0x0): 0 - mode == 'M' and (((old("pmpaddr12") ^ (pmpaddr12)) != 0x00) and pmpaddr12 != 0x0): 0 - mode == 'M' and (((old("pmpaddr13") ^ (pmpaddr13)) != 0x00) and pmpaddr13 != 0x0): 0 - mode == 'M' and (((old("pmpaddr14") ^ (pmpaddr14)) != 0x00) and pmpaddr14 != 0x0): 0 - mode == 'M' and (((old("pmpaddr15") ^ (pmpaddr15)) != 0x00) and pmpaddr15 != 0x0): 0 - mode == 'M' and (((old("pmpaddr2") ^ (pmpaddr2)) != 0x00) and pmpaddr2 != 0x0): 0 - mode == 'M' and (((old("pmpaddr3") ^ (pmpaddr3)) != 0x00) and pmpaddr3 != 0x0): 0 - mode == 'M' and (((old("pmpaddr4") ^ (pmpaddr4)) != 0x00) and pmpaddr4 != 0x0): 0 - mode == 'M' and (((old("pmpaddr5") ^ (pmpaddr5)) != 0x00) and pmpaddr5 != 0x0): 0 - mode == 'M' and (((old("pmpaddr6") ^ (pmpaddr6)) != 0x00) and pmpaddr6 != 0x0): 0 - mode == 'M' and (((old("pmpaddr7") ^ (pmpaddr7)) != 0x00) and pmpaddr7 != 0x0): 0 - mode == 'M' and (((old("pmpaddr8") ^ (pmpaddr8)) != 0x00) and pmpaddr8 != 0x0): 0 - mode == 'M' and (((old("pmpaddr9") ^ (pmpaddr9)) != 0x00) and pmpaddr9 != 0x0): 0 - mode == 'M' and (((old("pmpcfg0") ^ (pmpcfg0)) != 0x00) and pmpcfg0 != 0x0): 0 - mode == 'M' and (((old("pmpcfg1") ^ (pmpcfg1)) != 0x00) and pmpcfg1 != 0x0): 0 - mode == 'M' and (((old("pmpcfg2") ^ (pmpcfg2)) != 0x00) and pmpcfg2 != 0x0): 0 - mode == 'M' and (((old("pmpcfg3") ^ (pmpcfg3)) != 0x00) and pmpcfg3 != 0x0): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - mnemonic == "csrrs" and mode == 'S' and mcause == 0x02: 0 - mnemonic == "csrrs" and mode == 'U' and mcause == 0x02: 0 - mnemonic == "csrrw" and mode == 'S' and mcause == 0x02: 0 - mnemonic == "csrrw" and mode == 'U' and mcause == 0x02: 0 -pmp_cfg_locked_write_unrelated: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((old("pmpaddr0")) ^ (pmpaddr0) == 0x00) and (pmpcfg0 >> 0 & 0x80 == 0x80): 0 - ((old("pmpaddr1")) ^ (pmpaddr1) == 0x00) and (pmpcfg0 >> 0 & 0x80 == 0x80): 0 - ((old("pmpaddr10")) ^ (pmpaddr10) == 0x00) and (pmpcfg2 >> 16 & 0x80 == 0x80): 0 - ((old("pmpaddr11")) ^ (pmpaddr11) == 0x00) and (pmpcfg2 >> 16 & 0x80 == 0x80): 0 - ((old("pmpaddr12")) ^ (pmpaddr12) == 0x00) and (pmpcfg3 >> 24 & 0x80 == 0x80): 0 - ((old("pmpaddr13")) ^ (pmpaddr13) == 0x00) and (pmpcfg3 >> 24 & 0x80 == 0x80): 0 - ((old("pmpaddr14")) ^ (pmpaddr14) == 0x00) and (pmpcfg3 >> 24 & 0x80 == 0x80): 0 - ((old("pmpaddr15")) ^ (pmpaddr15) == 0x00) and (pmpcfg3 >> 24 & 0x80 == 0x80): 0 - ((old("pmpaddr2")) ^ (pmpaddr2) == 0x00) and (pmpcfg0 >> 0 & 0x80 == 0x80): 0 - ((old("pmpaddr3")) ^ (pmpaddr3) == 0x00) and (pmpcfg0 >> 0 & 0x80 == 0x80): 0 - ((old("pmpaddr4")) ^ (pmpaddr4) == 0x00) and (pmpcfg1 >> 8 & 0x80 == 0x80): 0 - ((old("pmpaddr5")) ^ (pmpaddr5) == 0x00) and (pmpcfg1 >> 8 & 0x80 == 0x80): 0 - ((old("pmpaddr6")) ^ (pmpaddr6) == 0x00) and (pmpcfg1 >> 8 & 0x80 == 0x80): 0 - ((old("pmpaddr7")) ^ (pmpaddr7) == 0x00) and (pmpcfg1 >> 8 & 0x80 == 0x80): 0 - ((old("pmpaddr8")) ^ (pmpaddr8) == 0x00) and (pmpcfg2 >> 16 & 0x80 == 0x80): 0 - ((old("pmpaddr9")) ^ (pmpaddr9) == 0x00) and (pmpcfg2 >> 16 & 0x80 == 0x80): 0 - (pmpcfg0 >> 0 & 0x80 == 0x80) and ((old("pmpcfg0") & (0xFF << 0)) ^ (pmpcfg0 & (0xFF << 0)) == 0x00): 0 - (pmpcfg0 >> 16 & 0x80 == 0x80) and ((old("pmpcfg0") & (0xFF << 16)) ^ (pmpcfg0 & (0xFF << 16)) == 0x00): 0 - (pmpcfg0 >> 24 & 0x80 == 0x80) and ((old("pmpcfg0") & (0xFF << 24)) ^ (pmpcfg0 & (0xFF << 24)) == 0x00): 0 - (pmpcfg0 >> 8 & 0x80 == 0x80) and ((old("pmpcfg0") & (0xFF << 8)) ^ (pmpcfg0 & (0xFF << 8)) == 0x00): 0 - (pmpcfg1 >> 0 & 0x80 == 0x80) and ((old("pmpcfg1") & (0xFF << 0)) ^ (pmpcfg1 & (0xFF << 0)) == 0x00): 0 - (pmpcfg1 >> 16 & 0x80 == 0x80) and ((old("pmpcfg1") & (0xFF << 16)) ^ (pmpcfg1 & (0xFF << 16)) == 0x00): 0 - (pmpcfg1 >> 24 & 0x80 == 0x80) and ((old("pmpcfg1") & (0xFF << 24)) ^ (pmpcfg1 & (0xFF << 24)) == 0x00): 0 - (pmpcfg1 >> 8 & 0x80 == 0x80) and ((old("pmpcfg1") & (0xFF << 8)) ^ (pmpcfg1 & (0xFF << 8)) == 0x00): 0 - (pmpcfg2 >> 0 & 0x80 == 0x80) and ((old("pmpcfg2") & (0xFF << 0)) ^ (pmpcfg2 & (0xFF << 0)) == 0x00): 0 - (pmpcfg2 >> 16 & 0x80 == 0x80) and ((old("pmpcfg2") & (0xFF << 16)) ^ (pmpcfg2 & (0xFF << 16)) == 0x00): 0 - (pmpcfg2 >> 24 & 0x80 == 0x80) and ((old("pmpcfg2") & (0xFF << 24)) ^ (pmpcfg2 & (0xFF << 24)) == 0x00): 0 - (pmpcfg2 >> 8 & 0x80 == 0x80) and ((old("pmpcfg2") & (0xFF << 8)) ^ (pmpcfg2 & (0xFF << 8)) == 0x00): 0 - (pmpcfg3 >> 0 & 0x80 == 0x80) and ((old("pmpcfg3") & (0xFF << 0)) ^ (pmpcfg3 & (0xFF << 0)) == 0x00): 0 - (pmpcfg3 >> 16 & 0x80 == 0x80) and ((old("pmpcfg3") & (0xFF << 16)) ^ (pmpcfg3 & (0xFF << 16)) == 0x00): 0 - (pmpcfg3 >> 24 & 0x80 == 0x80) and ((old("pmpcfg3") & (0xFF << 24)) ^ (pmpcfg3 & (0xFF << 24)) == 0x00): 0 - (pmpcfg3 >> 8 & 0x80 == 0x80) and ((old("pmpcfg3") & (0xFF << 8)) ^ (pmpcfg3 & (0xFF << 8)) == 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - diff --git a/coverage/pmp64_coverpoint_def_format.cgf b/coverage/pmp64_coverpoint_def_format.cgf deleted file mode 100644 index 3a59e34b0..000000000 --- a/coverage/pmp64_coverpoint_def_format.cgf +++ /dev/null @@ -1,702 +0,0 @@ -#Load access fault --> ${CAUSE_LOAD_ACCESS} -#Store access fault --> ${CAUSE_STORE_ACCESS} -#Fetch access fault --> ${CAUSE_FETCH_ACCESS} -PMP_NAPOT_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - #0x99 & 0xF9 = 0x99 | 0x9A & 0xF9 = 0x98 | 0x9C & 0xF9 = 0x98 - ((pmpcfg0 >> 8) & {0x99, 0x9A, 0x9C}) == (0xF9 & $1): 0 #No write, Execute permission - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - pmpaddr{0 ... 3} != 0 and ((old("pmpaddr$1")) ^ (pmpaddr$1) != 0x00): 0 #pmpaddr have been updated - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #Check the napot region is accessed at least once - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x99) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x99, 0x9A, 0x9C}) == (0xFC & $1): 0 #No Read, Write permission - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - pmpaddr{0 ... 3} != 0 and ((old("pmpaddr$1")) ^ (pmpaddr$1) != 0x00): 0 #pmpaddr have been updated - val_comb: - # Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #read, write fault - #Check the napot region is accessed at least once - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x99, 0x9A, 0x9C}) == (0xFB & $1): 0 #No Execute permission - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - pmpaddr{0 ... 3} != 0 and ((old("pmpaddr$1")) ^ (pmpaddr$1) != 0x00): 0 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #Check the napot region is accessed at least once - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x99, 0x9A, 0x9C}) == (0xFD & $1): 0 #No Write permission - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - pmpaddr{0 ... 3} != 0 and ((old("pmpaddr$1")) ^ (pmpaddr$1) != 0x00): 0 #pmpaddr have been updated - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No read, Execute fault - mode == 'M' and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - #Check the napot region is accessed at least once - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_rwx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x9C, 0x9A, 0x99}) == (0xFF & $1): 0 #All permissions given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write or execute fault - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9F) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_TOR_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 16) & {0x8C, 0x8A, 0x89}) == (0x89 & $1): 0 #Only Read Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - '(mnemonic == "lw" or mnemonic == "sw") and (((pmpcfg0 >> 16) & 0x9F == 0x89) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)))': 0 - -PMP_TOR_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 16) & {0x8C, 0x8A, 0x89}) == (0x8C & $1): 0 #Only Execute Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #Read, Write fault - #check for the read, write access - '(mnemonic == "lw" or mnemonic == "sw") and (((pmpcfg0 >> 16) & 0x9F == 0x8C) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)))': 0 - -PMP_TOR_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 16) & {0x9C, 0x9A, 0x99}) == (0x8B & $1): 0 #Only Read, Write Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - '(mnemonic == "lw" or mnemonic == "sw") and (((pmpcfg0 >> 16) & 0x9F == 0x8B) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)))': 0 - -PMP_TOR_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 16) & {0x8C, 0x8A, 0x89}) == (0x8D & $1): 0 #Only Read, Execute Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No read, execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - #check for the read, write access - '(mnemonic == "lw" or mnemonic == "sw") and (((pmpcfg0 >> 16) & 0x9F == 0x8D) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)))': 0 - -PMP_TOR_rwx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 16) & {0x9C, 0x9A, 0x99}) == (0x8F & $1): 0 #Only Read, Write Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write, execute fault - '(mnemonic == "lw" or mnemonic == "sw") and (((pmpcfg0 >> 16) & 0x9F == 0x8F) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)))': 0 - -PMP_NA4_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x91 & $1): 0 #Only Read Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the read, write access - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 - -PMP_NA4_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x94 & $1): 0 #Only Execute Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #read, write fault - #check for the read, write access - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 - -PMP_NA4_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x93 & $1): 0 #Only Read, Write Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the read, write access - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 - -PMP_NA4_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x95 & $1): 0 #Only Read, Execute Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No read, execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #write fault - #check for the read, write access - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 - -PMP_NA4_rwx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x97 & $1): 0 #Only Read, Write, Execute Permission given - pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated - (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, execute fault - #check for the read, write access - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x97) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 - -PMP_TOR_priority_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x89 & $1): 0 #Read Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.P0) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x89) and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 << 2))': 0 - -PMP_TOR_priority_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8C & $1): 0 #Read Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.P0) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #read, write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x8C) and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 << 2))': 0 - -PMP_TOR_priority_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8B & $1): 0 #Read, Write Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.P0) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x8B) and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 << 2))': 0 - -PMP_TOR_priority_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8D & $1): 0 #Read, Execute Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.P0) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No read, execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x8D) and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 << 2))': 0 - -PMP_TOR_priority_r_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x8C, 0x8A, 0x89}) == (0x89 & $1): 0 #Read Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 0, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x89) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 - -PMP_TOR_priority_rw_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x8C, 0x8A, 0x89}) == (0x8B & $1): 0 #Read, Write Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 0, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8B) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 - -PMP_TOR_priority_x_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x8C, 0x8A, 0x89}) == (0x8C & $1): 0 #Execute Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 0, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #read, write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8C) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 - -PMP_TOR_priority_rx_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x8C, 0x8A, 0x89}) == (0x8D & $1): 0 #Read, Execute Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 0, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_FETCH_ACCESS}}): 0 #No read, execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8D) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 - -PMP_TOR_priority_rwx_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Execute Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 0, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_FETCH_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8F) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 - -PMP_NAPOT_priority_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x9C, 0x9A, 0x99}) == (0x99 & $1): 0 #Read Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x99) and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_priority_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x9C, 0x9A, 0x99}) == (0x9B & $1): 0 #Read, Write Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x9B) and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_priority_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x9C, 0x9A, 0x99}) == (0x9C & $1): 0 #Execute Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No Execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #read, write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x9C) and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_priority_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x9C, 0x9A, 0x99}) == (0x9D & $1): 0 #Read, Execute Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No Read, Execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x9D) and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_priority_r_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x9C, 0x9A, 0x99}) == (0x99 & $1): 0 #Read Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x99) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_priority_rw_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x9C, 0x9A, 0x99}) == (0x9B & $1): 0 #Read, Write Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_priority_x_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x9C, 0x9A, 0x99}) == (0x9C & $1): 0 #Execute Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #Read, write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NAPOT_priority_rx_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x9C, 0x9A, 0x99}) == (0x9D & $1): 0 #Read, Execute Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No read, execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Read, write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -PMP_NA4_priority_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x94, 0x92, 0x91}) == (0x91 & $1): 0 #Read Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No Read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr3 << 2))' : 0 - -PMP_NA4_priority_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x94, 0x92, 0x91}) == (0x93 & $1): 0 #Read, Write Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No Read, Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr3 << 2))' : 0 - -PMP_NA4_priority_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x94, 0x92, 0x91}) == (0x94 & $1): 0 #Execute Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No Execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #Read, Write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr3 << 2))' : 0 - -PMP_NA4_priority_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x94, 0x92, 0x91}) == (0x95 & $1): 0 #Read, Execute Permission given to high priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No Read, Execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr3 << 2))' : 0 - -PMP_NA4_priority_r_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x91 & $1): 0 #Read Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No Read fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr1 << 2))' : 0 - -PMP_NA4_priority_rw_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x93 & $1): 0 #Read, Write Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No Read, Write fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr1 << 2))' : 0 - -PMP_NA4_priority_x_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x94 & $1): 0 #Execute Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No Execute fault - mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #Read, Write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr1 << 2))' : 0 - -PMP_NA4_priority_rx_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region - ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region - ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x95 & $1): 0 #Read, Execute Permission given to highest priority region - pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated - (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 - val_comb: - #Test for exceptions - mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS},${CAUSE_FETCH_ACCESS}}): 0 #No Read, Execute fault - mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault - #check for the accesses - '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr1 << 2))' : 0 - -pmp_cfg_locked_write_unrelated: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - (pmpcfg{0 ... 3} >> {0, 8, 16, 24} & 0x80 == 0x80) and ((old("pmpcfg$1") & (0xFF << $2)) ^ (pmpcfg$1 & (0xFF << $2)) == 0x00) and old("pmpcfg$1") != 0: 0 - ((old("pmpaddr{0 ... 15}")) ^ (pmpaddr$1) == 0x00) and (pmpcfg{0,1,2,3}{[$1/4]} >> {0, 8, 16, 24}{[$1/4]} & 0x80 == 0x80): 0 - -PMP_access_permission: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw}" : 0 - csr_comb: - mode == 'M' and (((old("pmpcfg{0 ... 3}") ^ (pmpcfg$1)) != 0x00) and pmpcfg$1 != 0x0): 0 #pmpcfg successfully updated in M mode - mode == 'M' and (((old("pmpaddr{0 ... 15}") ^ (pmpaddr$1)) != 0x00) and pmpaddr$1 != 0x0): 0 #pmpaddr successfully updated in M mode - val_comb: - mnemonic == {"csrrs", "csrrw"} and mode == {'S', 'U'} and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}: 0 #check for illegal instruction fault diff --git a/coverage/pmp64_translated_coverpoints.cgf b/coverage/pmp64_translated_coverpoints.cgf deleted file mode 100644 index 93b04612f..000000000 --- a/coverage/pmp64_translated_coverpoints.cgf +++ /dev/null @@ -1,1423 +0,0 @@ -PMP_NA4_priority_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x91) == (0x91 & 0x91): 0 - ((pmpcfg0 >> 24) & 0x92) == (0x91 & 0x92): 0 - ((pmpcfg0 >> 24) & 0x94) == (0x91 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr3 << 2)): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_priority_r_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x91) == (0x91 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x91 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x91 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_priority_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x91) == (0x93 & 0x91): 0 - ((pmpcfg0 >> 24) & 0x92) == (0x93 & 0x92): 0 - ((pmpcfg0 >> 24) & 0x94) == (0x93 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr3 << 2)): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NA4_priority_rw_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x91) == (0x93 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x93 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x93 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NA4_priority_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x91) == (0x95 & 0x91): 0 - ((pmpcfg0 >> 24) & 0x92) == (0x95 & 0x92): 0 - ((pmpcfg0 >> 24) & 0x94) == (0x95 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr3 << 2)): 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_priority_rx_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x91) == (0x95 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x95 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x95 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_priority_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x91) == (0x94 & 0x91): 0 - ((pmpcfg0 >> 24) & 0x92) == (0x94 & 0x92): 0 - ((pmpcfg0 >> 24) & 0x94) == (0x94 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr3 << 2)): 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_priority_x_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x91) == (0x94 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x94 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x94 & 0x94): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x91) == (0x91 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x91 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x91 & 0x94): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x91) == (0x93 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x93 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x93 & 0x94): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NA4_rwx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x91) == (0x97 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x97 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x97 & 0x94): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x97) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NA4_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x91) == (0x95 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x95 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x95 & 0x94): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NA4_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x91) == (0x94 & 0x91): 0 - ((pmpcfg0 >> 8) & 0x92) == (0x94 & 0x92): 0 - ((pmpcfg0 >> 8) & 0x94) == (0x94 & 0x94): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr1 << 2)): 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NAPOT_priority_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x99) == (0x99 & 0x99): 0 - ((pmpcfg0 >> 24) & 0x9A) == (0x99 & 0x9A): 0 - ((pmpcfg0 >> 24) & 0x9C) == (0x99 & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x99) - and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 - << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NAPOT_priority_r_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x99) == (0x99 & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0x99 & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0x99 & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x99) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NAPOT_priority_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x99) == (0x9B & 0x99): 0 - ((pmpcfg0 >> 24) & 0x9A) == (0x9B & 0x9A): 0 - ((pmpcfg0 >> 24) & 0x9C) == (0x9B & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x9B) - and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 - << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NAPOT_priority_rw_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x99) == (0x9B & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0x9B & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0x9B & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NAPOT_priority_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x99) == (0x9D & 0x99): 0 - ((pmpcfg0 >> 24) & 0x9A) == (0x9D & 0x9A): 0 - ((pmpcfg0 >> 24) & 0x9C) == (0x9D & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x9D) - and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 - << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NAPOT_priority_rx_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x99) == (0x9D & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0x9D & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0x9D & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NAPOT_priority_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x99) == (0x9C & 0x99): 0 - ((pmpcfg0 >> 24) & 0x9A) == (0x9C & 0x9A): 0 - ((pmpcfg0 >> 24) & 0x9C) == (0x9C & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x9C) - and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 - << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NAPOT_priority_x_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x99) == (0x9C & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0x9C & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0x9C & 0x9C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_NAPOT_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x99) == (0xF9 & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0xF9 & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0xF9 & 0x9C): 0 - pmpaddr0 != 0 and ((old("pmpaddr0")) ^ (pmpaddr0) != 0x00): 0 - pmpaddr1 != 0 and ((old("pmpaddr1")) ^ (pmpaddr1) != 0x00): 0 - pmpaddr2 != 0 and ((old("pmpaddr2")) ^ (pmpaddr2) != 0x00): 0 - pmpaddr3 != 0 and ((old("pmpaddr3")) ^ (pmpaddr3) != 0x00): 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x99) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x01): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x05): 0 -PMP_NAPOT_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x99) == (0xFB & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0xFB & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0xFB & 0x9C): 0 - pmpaddr0 != 0 and ((old("pmpaddr0")) ^ (pmpaddr0) != 0x00): 0 - pmpaddr1 != 0 and ((old("pmpaddr1")) ^ (pmpaddr1) != 0x00): 0 - pmpaddr2 != 0 and ((old("pmpaddr2")) ^ (pmpaddr2) != 0x00): 0 - pmpaddr3 != 0 and ((old("pmpaddr3")) ^ (pmpaddr3) != 0x00): 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NAPOT_rwx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x99) == (0xFF & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0xFF & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0xFF & 0x9C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9F) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_NAPOT_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x99) == (0xFD & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0xFD & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0xFD & 0x9C): 0 - pmpaddr0 != 0 and ((old("pmpaddr0")) ^ (pmpaddr0) != 0x00): 0 - pmpaddr1 != 0 and ((old("pmpaddr1")) ^ (pmpaddr1) != 0x00): 0 - pmpaddr2 != 0 and ((old("pmpaddr2")) ^ (pmpaddr2) != 0x00): 0 - pmpaddr3 != 0 and ((old("pmpaddr3")) ^ (pmpaddr3) != 0x00): 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 -PMP_NAPOT_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 8) & 0x99) == (0xFC & 0x99): 0 - ((pmpcfg0 >> 8) & 0x9A) == (0xFC & 0x9A): 0 - ((pmpcfg0 >> 8) & 0x9C) == (0xFC & 0x9C): 0 - pmpaddr0 != 0 and ((old("pmpaddr0")) ^ (pmpaddr0) != 0x00): 0 - pmpaddr1 != 0 and ((old("pmpaddr1")) ^ (pmpaddr1) != 0x00): 0 - pmpaddr2 != 0 and ((old("pmpaddr2")) ^ (pmpaddr2) != 0x00): 0 - pmpaddr3 != 0 and ((old("pmpaddr3")) ^ (pmpaddr3) != 0x00): 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and - (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 - << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1))) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x01): 0 -PMP_TOR_priority_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x89 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x89 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x89 & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x89) - and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 - << 2)) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_TOR_priority_r_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x89) == (0x89 & 0x89): 0 - ((pmpcfg0 >> 8) & 0x8A) == (0x89 & 0x8A): 0 - ((pmpcfg0 >> 8) & 0x8C) == (0x89 & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x89) and - (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << - 2)) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_TOR_priority_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x8B & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x8B & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x8B & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x8B) - and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 - << 2)) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_TOR_priority_rw_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x89) == (0x8B & 0x89): 0 - ((pmpcfg0 >> 8) & 0x8A) == (0x8B & 0x8A): 0 - ((pmpcfg0 >> 8) & 0x8C) == (0x8B & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8B) and - (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << - 2)) - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and mode_change == 'M to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'S to M' and (mcause == 0x01): 0 - mode == 'M' and mode_change == 'U to M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_TOR_priority_rwx_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg0 >> 8) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg0 >> 8) & 0x8C) == (0x8F & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8F) and - (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << - 2)) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_TOR_priority_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x8D & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x8D & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x8D & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x8D) - and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 - << 2)) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_TOR_priority_rx_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x89) == (0x8D & 0x89): 0 - ((pmpcfg0 >> 8) & 0x8A) == (0x8D & 0x8A): 0 - ((pmpcfg0 >> 8) & 0x8C) == (0x8D & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8D) and - (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << - 2)) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_TOR_priority_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x8C & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x8C & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x8C & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x8C) - and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 - << 2)) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_TOR_priority_x_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 24) & 0x89) == (0x88 & 0x89): 0 - ((pmpcfg0 >> 24) & 0x8A) == (0x88 & 0x8A): 0 - ((pmpcfg0 >> 24) & 0x8C) == (0x88 & 0x8C): 0 - ((pmpcfg0 >> 8) & 0x89) == (0x8C & 0x89): 0 - ((pmpcfg0 >> 8) & 0x8A) == (0x8C & 0x8A): 0 - ((pmpcfg0 >> 8) & 0x8C) == (0x8C & 0x8C): 0 - ((pmpcfg3 >> 24) & 0x89) == (0x8F & 0x89): 0 - ((pmpcfg3 >> 24) & 0x8A) == (0x8F & 0x8A): 0 - ((pmpcfg3 >> 24) & 0x8C) == (0x8F & 0x8C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr14")) ^ (pmpaddr14) != 0x00: 0 - (old("pmpaddr15")) ^ (pmpaddr15) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg3 != 0 and ((old("pmpcfg3")) ^ (pmpcfg3) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8C) and - (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << - 2)) - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_TOR_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 16) & 0x99) == (0x89 & 0x99): 0 - ((pmpcfg0 >> 16) & 0x9A) == (0x89 & 0x9A): 0 - ((pmpcfg0 >> 16) & 0x9C) == (0x89 & 0x9C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ('((pmpcfg0 >> 16) & 0x9F == 0x89) - and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 - << 2))') - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x01): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x05): 0 -PMP_TOR_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 16) & 0x99) == (0x8B & 0x99): 0 - ((pmpcfg0 >> 16) & 0x9A) == (0x8B & 0x9A): 0 - ((pmpcfg0 >> 16) & 0x9C) == (0x8B & 0x9C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ('((pmpcfg0 >> 16) & 0x9F == 0x89) - and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 - << 2))') - : 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'M' and (mcause == 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_TOR_rwx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 16) & 0x99) == (0x8F & 0x99): 0 - ((pmpcfg0 >> 16) & 0x9A) == (0x8F & 0x9A): 0 - ((pmpcfg0 >> 16) & 0x9C) == (0x8F & 0x9C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ('((pmpcfg0 >> 16) & 0x9F == 0x8F) - and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 - << 2))') - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause != 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause != 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause != 0x07): 0 -PMP_TOR_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 16) & 0x89) == (0x8D & 0x89): 0 - ((pmpcfg0 >> 16) & 0x8A) == (0x8D & 0x8A): 0 - ((pmpcfg0 >> 16) & 0x8C) == (0x8D & 0x8C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ('((pmpcfg0 >> 16) & 0x9F == 0x8D) - and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 - << 2))') - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause != 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause != 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause != 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_TOR_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((pmpcfg0 >> 16) & 0x89) == (0x8C & 0x89): 0 - ((pmpcfg0 >> 16) & 0x8A) == (0x8C & 0x8A): 0 - ((pmpcfg0 >> 16) & 0x8C) == (0x8C & 0x8C): 0 - (old("pmpaddr0")) ^ (pmpaddr0) != 0x00: 0 - (old("pmpaddr1")) ^ (pmpaddr1) != 0x00: 0 - (old("pmpaddr2")) ^ (pmpaddr2) != 0x00: 0 - (old("pmpaddr3")) ^ (pmpaddr3) != 0x00: 0 - pmpcfg0 != 0 and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 - pmpcfg1 != 0 and ((old("pmpcfg1")) ^ (pmpcfg1) != 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - ? (mnemonic == "lw" or mnemonic == "sw") and ('((pmpcfg0 >> 16) & 0x9F == 0x8C) - and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 - << 2))') - : 0 - mode == 'M' and (mcause != 0x01): 0 - mode == 'M' and (mcause == 0x05): 0 - mode == 'M' and (mcause == 0x07): 0 - mode == 'S' and (mcause != 0x01): 0 - mode == 'S' and (mcause == 0x05): 0 - mode == 'S' and (mcause == 0x07): 0 - mode == 'U' and (mcause != 0x01): 0 - mode == 'U' and (mcause == 0x05): 0 - mode == 'U' and (mcause == 0x07): 0 -PMP_access_permission: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - mode == 'M' and (((old("pmpaddr0") ^ (pmpaddr0)) != 0x00) and pmpaddr0 != 0x0): 0 - mode == 'M' and (((old("pmpaddr1") ^ (pmpaddr1)) != 0x00) and pmpaddr1 != 0x0): 0 - mode == 'M' and (((old("pmpaddr10") ^ (pmpaddr10)) != 0x00) and pmpaddr10 != 0x0): 0 - mode == 'M' and (((old("pmpaddr11") ^ (pmpaddr11)) != 0x00) and pmpaddr11 != 0x0): 0 - mode == 'M' and (((old("pmpaddr12") ^ (pmpaddr12)) != 0x00) and pmpaddr12 != 0x0): 0 - mode == 'M' and (((old("pmpaddr13") ^ (pmpaddr13)) != 0x00) and pmpaddr13 != 0x0): 0 - mode == 'M' and (((old("pmpaddr14") ^ (pmpaddr14)) != 0x00) and pmpaddr14 != 0x0): 0 - mode == 'M' and (((old("pmpaddr15") ^ (pmpaddr15)) != 0x00) and pmpaddr15 != 0x0): 0 - mode == 'M' and (((old("pmpaddr2") ^ (pmpaddr2)) != 0x00) and pmpaddr2 != 0x0): 0 - mode == 'M' and (((old("pmpaddr3") ^ (pmpaddr3)) != 0x00) and pmpaddr3 != 0x0): 0 - mode == 'M' and (((old("pmpaddr4") ^ (pmpaddr4)) != 0x00) and pmpaddr4 != 0x0): 0 - mode == 'M' and (((old("pmpaddr5") ^ (pmpaddr5)) != 0x00) and pmpaddr5 != 0x0): 0 - mode == 'M' and (((old("pmpaddr6") ^ (pmpaddr6)) != 0x00) and pmpaddr6 != 0x0): 0 - mode == 'M' and (((old("pmpaddr7") ^ (pmpaddr7)) != 0x00) and pmpaddr7 != 0x0): 0 - mode == 'M' and (((old("pmpaddr8") ^ (pmpaddr8)) != 0x00) and pmpaddr8 != 0x0): 0 - mode == 'M' and (((old("pmpaddr9") ^ (pmpaddr9)) != 0x00) and pmpaddr9 != 0x0): 0 - mode == 'M' and (((old("pmpcfg0") ^ (pmpcfg0)) != 0x00) and pmpcfg0 != 0x0): 0 - mode == 'M' and (((old("pmpcfg1") ^ (pmpcfg1)) != 0x00) and pmpcfg1 != 0x0): 0 - mode == 'M' and (((old("pmpcfg2") ^ (pmpcfg2)) != 0x00) and pmpcfg2 != 0x0): 0 - mode == 'M' and (((old("pmpcfg3") ^ (pmpcfg3)) != 0x00) and pmpcfg3 != 0x0): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - lw: 0 - sw: 0 - val_comb: - mnemonic == "csrrs" and mode == 'S' and mcause == 0x02: 0 - mnemonic == "csrrs" and mode == 'U' and mcause == 0x02: 0 - mnemonic == "csrrw" and mode == 'S' and mcause == 0x02: 0 - mnemonic == "csrrw" and mode == 'U' and mcause == 0x02: 0 -pmp_cfg_locked_write_unrelated: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - csr_comb: - ((old("pmpaddr0")) ^ (pmpaddr0) == 0x00) and (pmpcfg0 >> 0 & 0x80 == 0x80): 0 - ((old("pmpaddr1")) ^ (pmpaddr1) == 0x00) and (pmpcfg0 >> 8 & 0x80 == 0x80): 0 - ((old("pmpaddr2")) ^ (pmpaddr2) == 0x00) and (pmpcfg0 >> 16 & 0x80 == 0x80): 0 - ((old("pmpaddr3")) ^ (pmpaddr3) == 0x00) and (pmpcfg0 >> 24 & 0x80 == 0x80): 0 - ((old("pmpaddr4")) ^ (pmpaddr4) == 0x00) and (pmpcfg0 >> 32 & 0x80 == 0x80): 0 - ((old("pmpaddr5")) ^ (pmpaddr5) == 0x00) and (pmpcfg0 >> 40 & 0x80 == 0x80): 0 - ((old("pmpaddr6")) ^ (pmpaddr6) == 0x00) and (pmpcfg0 >> 48 & 0x80 == 0x80): 0 - ((old("pmpaddr7")) ^ (pmpaddr7) == 0x00) and (pmpcfg0 >> 56 & 0x80 == 0x80): 0 - ((old("pmpaddr8")) ^ (pmpaddr8) == 0x00) and (pmpcfg2 >> 0 & 0x80 == 0x80): 0 - ((old("pmpaddr9")) ^ (pmpaddr9) == 0x00) and (pmpcfg2 >> 8 & 0x80 == 0x80): 0 - ((old("pmpaddr10")) ^ (pmpaddr10) == 0x00) and (pmpcfg2 >> 16 & 0x80 == 0x80): 0 - ((old("pmpaddr11")) ^ (pmpaddr11) == 0x00) and (pmpcfg2 >> 24 & 0x80 == 0x80): 0 - ((old("pmpaddr12")) ^ (pmpaddr12) == 0x00) and (pmpcfg2 >> 32 & 0x80 == 0x80): 0 - ((old("pmpadd13")) ^ (pmpaddr13) == 0x00) and (pmpcfg2 >> 40 & 0x80 == 0x80): 0 - ((old("pmpaddr14")) ^ (pmpaddr14) == 0x00) and (pmpcfg2 >> 48 & 0x80 == 0x80): 0 - ((old("pmpaddr15")) ^ (pmpaddr15) == 0x00) and (pmpcfg2 >> 56 & 0x80 == 0x80): 0 - (pmpcfg0 >> 0 & 0x80 == 0x80) and ((old("pmpcfg0") & (0xFF << 0)) ^ (pmpcfg0 & (0xFF << 0)) == 0x00): 0 - (pmpcfg0 >> 16 & 0x80 == 0x80) and ((old("pmpcfg0") & (0xFF << 16)) ^ (pmpcfg0 & (0xFF << 16)) == 0x00): 0 - (pmpcfg0 >> 24 & 0x80 == 0x80) and ((old("pmpcfg0") & (0xFF << 24)) ^ (pmpcfg0 & (0xFF << 24)) == 0x00): 0 - (pmpcfg0 >> 8 & 0x80 == 0x80) and ((old("pmpcfg0") & (0xFF << 8)) ^ (pmpcfg0 & (0xFF << 8)) == 0x00): 0 - (pmpcfg0 >> 32 & 0x80 == 0x80) and ((old("pmpcfg0") & (0xFF << 32)) ^ (pmpcfg0 & (0xFF << 32)) == 0x00): 0 - (pmpcfg0 >> 40 & 0x80 == 0x80) and ((old("pmpcfg0") & (0xFF << 40)) ^ (pmpcfg0 & (0xFF << 40)) == 0x00): 0 - (pmpcfg0 >> 48 & 0x80 == 0x80) and ((old("pmpcfg0") & (0xFF << 48)) ^ (pmpcfg0 & (0xFF << 48)) == 0x00): 0 - (pmpcfg0 >> 56 & 0x80 == 0x80) and ((old("pmpcfg0") & (0xFF << 56)) ^ (pmpcfg0 & (0xFF << 56)) == 0x00): 0 - (pmpcfg2 >> 0 & 0x80 == 0x80) and ((old("pmpcfg2") & (0xFF << 0)) ^ (pmpcfg2 & (0xFF << 0)) == 0x00): 0 - (pmpcfg2 >> 16 & 0x80 == 0x80) and ((old("pmpcfg2") & (0xFF << 16)) ^ (pmpcfg2 & (0xFF << 16)) == 0x00): 0 - (pmpcfg2 >> 24 & 0x80 == 0x80) and ((old("pmpcfg2") & (0xFF << 24)) ^ (pmpcfg2 & (0xFF << 24)) == 0x00): 0 - (pmpcfg2 >> 8 & 0x80 == 0x80) and ((old("pmpcfg2") & (0xFF << 8)) ^ (pmpcfg2 & (0xFF << 8)) == 0x00): 0 - (pmpcfg2 >> 32 & 0x80 == 0x80) and ((old("pmpcfg2") & (0xFF << 32)) ^ (pmpcfg2 & (0xFF << 32)) == 0x00): 0 - (pmpcfg2 >> 40 & 0x80 == 0x80) and ((old("pmpcfg2") & (0xFF << 40)) ^ (pmpcfg2 & (0xFF << 40)) == 0x00): 0 - (pmpcfg2 >> 48 & 0x80 == 0x80) and ((old("pmpcfg2") & (0xFF << 48)) ^ (pmpcfg2 & (0xFF << 48)) == 0x00): 0 - (pmpcfg2 >> 56 & 0x80 == 0x80) and ((old("pmpcfg2") & (0xFF << 56)) ^ (pmpcfg2 & (0xFF << 56)) == 0x00): 0 - mnemonics: - csrrs: 0 - csrrw: 0 - ld: 0 - sd: 0 - diff --git a/riscv-test-suite/rv32i_m/pmp32/PMP-CFG-reg.S b/riscv-test-suite/rv32i_m/pmp32/PMP-CFG-reg.S deleted file mode 100644 index 7473a030f..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/PMP-CFG-reg.S +++ /dev/null @@ -1,146 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -// -// This assembly file tests access of pmp registers in M, S, and U mode. -// pmp csrs are accessable only in M-mode so it should trap in S, and U mode. -// -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - pmpcfg0 & 0x20 == 0 : 0 // CHECK IF pmpcfg0[5]==0 (Hard wired zero bit) - pmpcfg0 & 0x40 == 0 : 0 // CHECK IF pmpcfg0[6]==0 (Hard wired zero bit) - pmpcfg0 & 0x80 == 0x80 : 0 // CHECK IF pmpcfg0[7]==1 (Lock bit) - (pmpcfg0 >> 8) & 0x20 == 0 : 0 // CHECK IF pmpcfg0[13]==0 (Hard wired zero bit) - (pmpcfg0 >> 8) & 0x40 == 0 : 0 // CHECK IF pmpcfg0[14]==0 (Hard wired zero bit) - (pmpcfg0 >> 8) & 0x80 == 0x80 : 0 // CHECK IF pmpcfg0[15]==1 (Lock bit) - (pmpcfg0 >> 16) & 0x20 == 0 : 0 // CHECK IF pmpcfg0[21]==0 (Hard wired zero bit) - (pmpcfg0 >> 16) & 0x40 == 0 : 0 // CHECK IF pmpcfg0[22]==0 (Hard wired zero bit) - (pmpcfg0 >> 16) & 0x80 == 0x80 : 0 // CHECK IF pmpcfg0[23]==1 (Lock bit) - (pmpcfg0 >> 24) & 0x20 == 0 : 0 // CHECK IF pmpcfg0[29]==0 (Hard wired zero bit) - (pmpcfg0 >> 24) & 0x40 == 0 : 0 // CHECK IF pmpcfg0[30]==0 (Hard wired zero bit) - (pmpcfg0 >> 24) & 0x80 == 0x80 : 0 // CHECK IF pmpcfg0[31]==1 (Lock bit) -// Same coverpoints are defined for pmpcfg1, pmpcfg2, and pmpcfg3 -// Details are given in /coverage/rv32i_priv.cgf -*/ -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",pmp_cfg_locked_write_unrelated) -RVTEST_SIGBASE( x3,signature_x3_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x9,0) // The register to carry offset value - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrc pmpcfgi , a5 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrc pmpaddri, a5 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -//////////////////// Locked bit TEST 1 ///////////////////////////////////////////// - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi, a5 // WRITE pmpcfgi with ALL 1s, Locked the lock-bit [7,15,23,31] - nop // Added nop in case of trap - csrr a4, pmpcfgi // READ pmpcfgi - // THIS READ WILL ALSO CONFIRM THE ZERO BITs OF PMPCFGi REG. - // BIT 5-6, BIT 13-14, BIT 21-22, BIT 29-30 must be hardwired to zero - // Verify that LOCKED bits are HIGH, and ZERO bits are zero - RVTEST_SIGUPD(x3,a4) - // TRY TO WRITE CFG REGISTER AGAIN (TRAP in case of LOCKED bit is HIGH) - csrw pmpcfgi, x5 // WRITE pmpcfgi with some other values - nop // Added nop in case of trap - csrr a4, pmpcfgi // READ pmpcfgi - // Since Locked bit is high, so this should return the old value!!! - RVTEST_SIGUPD(x3,a4) - - .set pmpaddri, PMPADDR0+4*(pmpcfgi-PMPCFG0) -// Initialize an iterating variable with the address of pmpaddr0 in 1st iteration (when pmpcfgi=pmpcfg0) -// Initialize an iterating variable with the address of pmpaddr4 in 2nd iteration (when pmpcfgi=pmpcfg1) -// Initialize an iterating variable with the address of pmpaddr8 in 3rd iteration (when pmpcfgi=pmpcfg2) -// Initialize an iterating variable with the address of pmpaddr12 in 4th iteration (when pmpcfgi=pmpcfg3) - .rept 4 // START OF LOOP - // TRY TO WRITE ADDRESS REGISTER. - csrw pmpaddri, a5 // WRITE pmpaddri with some other values - // The updated write will give a trap!!! - nop // Added nop in case of trap - csrr a4, pmpaddri // READ pmpaddr0, value should not have been changed - nop // Added nop in case of trap - RVTEST_SIGUPD(x3,a4) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF INNER LOOP BODY - - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF OUTER LOOP BODY -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x3_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/PMP-CSR-access.S b/riscv-test-suite/rv32i_m/pmp32/PMP-CSR-access.S deleted file mode 100644 index c36838928..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/PMP-CSR-access.S +++ /dev/null @@ -1,188 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -// -// This assembly file tests access of pmp registers in M, S, and U mode. -// pmp csrs are accessable only in M-mode so it should trap in S, and U mode. -// -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - -// Details are given in /coverage/rv32i_priv.cgf -*/ -// -#define rvtest_strap_routine -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",PMP_access_permission) -RVTEST_SIGBASE( x13,signature_x13_1) - .option nopic - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 -main: -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrc pmpcfgi , a5 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrc pmpaddri, a5 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrs pmpaddri, a5 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY -//////////////// VERIFICATION ///////////////////////////////////////// -// READING pmpaddr in M-mode ///////////////////////////////////////// - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrr a4, pmpaddri // READING pmpaddri (i is from 0-15) - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,a4) // Storing into signature file - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY -// WRITING pmpcfg registers ////////////////////////////////////////// -// Write in M-mode will be valid, Write in other modes will cause trap - LI(a5, PMP_R| PMP_W | PMP_X | PMP_TOR) // LOCKED BIT IS NOT SET - // Loop to Write ALL pmpcfg regs - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi, a5 // Write pmpcfgi - nop // Added nop in case of trap - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY -//////////////// VERIFICATION ///////////////////////////////////////// -// READING pmpcfg in M-mode ///////////////////////////////////////// - // Loop to verify the contents of pmpcfg regs - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrr a4, pmpcfg0 // Read pmpcfg0 - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,a4) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY -/////////////////// Switch to S-mode //////////////////////////////////////////// - csrw satp, zero // Disable address translation. - LI(t2, -1) - csrw pmpaddr0, t2 // Updated pmpaddr0 to define PMP region consisting - // of whole physical memory - csrr t0, pmpaddr0 // Verify its value by reading back - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,t0) - nop // Added nop in case of trap - LI(a5, PMP_L| PMP_R| PMP_W | PMP_X | PMP_TOR) // LOCKED BIT IS SET - csrw pmpcfg0, a5 - - RVTEST_GOTO_LOWER_MODE Smode // GO into S mode -// REPEATING THE SAME TEST ////////////////////////////////////////// -// IN Smode now -/////////////////// TEST 01 //////////////////////////////////////////// -// WRITING pmpaddr registers ////////////////////////////////////////// -// Write in M-mode will be valid, Write in other modes will cause trap - csrw pmpaddr0, x2 // Write pmpaddr0 in S mode (TRAP) - nop // Added nop in case of trap -// READING pmpaddr in S-mode ///////////////////////////////////////// - csrr a4, pmpaddr0 // Reading pmpaddr0 in S mode (TRAP) - nop // Added nop in case of trap -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,a4) -/////////////////// Switch to U-mode //////////////////////////////////////////// - csrw satp, zero // Disable address translation. - LI(t2, -1) - csrw pmpaddr0, t2 // Updated pmpaddr0 to define PMP region consisting - // of whole physical memory - csrr t0, pmpaddr0 // Verify its value by reading back - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,t0) - nop // Added nop in case of trap - LI(a5, PMP_L| PMP_R| PMP_W | PMP_X | PMP_TOR) // LOCKED BIT IS SET - csrw pmpcfg0, a5 -// These steps are repeated and can be removed but it will make sure that you will switch mode -// with full access on physical memory - RVTEST_GOTO_LOWER_MODE Umode -// REPEATING THE SAME TEST ////////////////////////////////////////// -// IN U-mode now -/////////////////// TEST 01 //////////////////////////////////////////// -// WRITING pmpaddr registers ////////////////////////////////////////// -// Write in M-mode will be valid, Write in other modes will cause trap - csrw pmpaddr0, x2 // Write pmpaddr0 in u mode (TRAP) - nop // Added nop in case of trap -//////////////// VERIFICATION ///////////////////////////////////////// -// READING pmpaddr in S-mode ///////////////////////////////////////// - csrr a4, pmpaddr0 // Reading pmpaddr0 in U mode (TRAP) - nop // Added nop in case of trap - -#endif - - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-R-priority-level-2.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-R-priority-level-2.S deleted file mode 100644 index bec6df103..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-R-priority-level-2.S +++ /dev/null @@ -1,210 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-priority-r-level-2.S -// Tests the priority by assigning only R permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", PMP_NA4_priority_r_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x8000 0000 to Address RVMODEL_DATA_END => PMP TOR (Low Priority) Region with RWX enabled. For this purpose, pmpaddr14 has been given the value of 0 and pmpaddr15 is given address to RVMODEL_DATA_END to declare the region from 0->RVMODEL_DATA_END into a single PMP region. - -2. Address RAM_LOCATION_FOR_TEST to Address RETURN_INSTRUCTION => PMP region under test. This region has been declared by entering RAM_LOCATION_FOR_TEST into pmpaddr2 and address to RETURN_INSTRUCTION label into pmpaddr3. Then a PMP region is configure from pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(RETURN_INSTRUCTION) into TOR mode by setting pmpcfg0[31:24]=PMPREGION2 - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-R-priority.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-R-priority.S deleted file mode 100644 index a5ce0f8d5..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-R-priority.S +++ /dev/null @@ -1,188 +0,0 @@ - -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-priority-r.S -// PMP Test in NA4 address matching mode -// Description: -// Tests the priority by assigning only R permissions to the high priority while R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_r) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3[31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_R|PMP_NA4)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-R.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-R.S deleted file mode 100644 index 3581cbe8a..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-R.S +++ /dev/null @@ -1,225 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-R.S -// PMP Test in NA4 address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=0 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -*/ -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - (pmpcfg0 >> 8) & 0x18 == 0x10 : 0 // CHECK pmp2cfg in NA4 mode? - (pmpcfg0 >> 8) & 0x01 == 0x01 : 0 // CHECK R-bit in pmp2cfg was HIGH - (pmpcfg0 >> 8) & 0x02 == 0x02 : 0 // CHECK W-bit in pmp2cfg was HIGH - (pmpcfg0 >> 8) & 0x04 == 0x04 : 0 // CHECK X-bit in pmp2cfg was HIGH -// Details are given in /coverage/rv32i_priv.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_r) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NA4 Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[7:0] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=((PMP_R|PMP_L|PMP_NA4)&0xFF) - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION4) - // Value to be stored in pmpcfg1 register ; Setting up PMP Region-4 - csrs pmpcfg1, x4 // Updated pmpcfg1 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RW-priority-level-2.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RW-priority-level-2.S deleted file mode 100644 index dbc019816..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RW-priority-level-2.S +++ /dev/null @@ -1,206 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-rw-level-2.S -// Tests the priority by assigning only R,W permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_rw_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RW-priority.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RW-priority.S deleted file mode 100644 index 6f9769132..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RW-priority.S +++ /dev/null @@ -1,187 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-priority-rw.S -// PMP Test in NA4 address matching mode -// Description: -// Tests the priority by assigning only R,W permissions to the high priority while R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_rw) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3[31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_R|PMP_W|PMP_NA4)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RW.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RW.S deleted file mode 100644 index e8f4d05a1..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RW.S +++ /dev/null @@ -1,226 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-RW.S -// PMP Test in NA4 address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=0 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - (pmpcfg0 >> 8) & 0x18 == 0x10 : 0 // CHECK pmp2cfg in NA4 mode? - (pmpcfg0 >> 8) & 0x01 == 0x01 : 0 // CHECK R-bit in pmp2cfg was HIGH - (pmpcfg0 >> 8) & 0x02 == 0x02 : 0 // CHECK W-bit in pmp2cfg was HIGH - (pmpcfg0 >> 8) & 0x04 == 0x04 : 0 // CHECK X-bit in pmp2cfg was HIGH -// Details are given in /coverage/rv32i_priv.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_rw) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NA4 Mode with RW enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_W|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[7:0] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=((PMP_R|PMP_W|PMP_L|PMP_NA4)&0xFF) - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION4) - // Value to be stored in pmpcfg1 register ; Setting up PMP Region-4 - csrs pmpcfg1, x4 // Updated pmpcfg1 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RWX.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RWX.S deleted file mode 100644 index 48383f087..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RWX.S +++ /dev/null @@ -1,240 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-RWX.S -// PMP Test in NA4 address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - (pmpcfg0 >> 8) & 0x18 == 0x10 : 0 // CHECK pmp2cfg in NA4 mode? - (pmpcfg0 >> 8) & 0x01 == 0x01 : 0 // CHECK R-bit in pmp2cfg was HIGH - (pmpcfg0 >> 8) & 0x02 == 0x02 : 0 // CHECK W-bit in pmp2cfg was HIGH - (pmpcfg0 >> 8) & 0x04 == 0x04 : 0 // CHECK X-bit in pmp2cfg was HIGH -// Details are given in /coverage/rv32i_priv.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_rwx) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrc pmpcfgi , a5 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrc pmpaddri, a5 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NA4 Mode with RW enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[7:0] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. -This region is the part of the code memory containing our code and the region between code_end to data_begin. -For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to -declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail.) -This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. -Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. -This region has been declared by entering rvtest_code_end into pmpaddr3 and -RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) -to pmpaddr3(rvtest_code_end) into TOR mode -by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. -This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. -For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) -into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). -This PMP Region is mandatory to access signature area in S,U mode */ - - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION4) - // Value to be stored in pmpcfg1 register ; Setting up PMP Region-4 - csrs pmpcfg1, x4 // Updated pmpcfg1 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - nop - j exit -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - - - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RX-priority-level-2.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RX-priority-level-2.S deleted file mode 100644 index 525e37163..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RX-priority-level-2.S +++ /dev/null @@ -1,206 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-rx-level-2.S -// Tests the priority by assigning only R,X permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_rx_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_X|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RX-priority.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RX-priority.S deleted file mode 100644 index 5fbeff6fc..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RX-priority.S +++ /dev/null @@ -1,187 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-priority-rx.S -// PMP Test in NA4 address matching mode -// Description: -// Tests the priority by assigning only R,X permissions to the high priority while R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_rx) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3[31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_R|PMP_X|PMP_NA4)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RX.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RX.S deleted file mode 100644 index fb7851d40..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-RX.S +++ /dev/null @@ -1,224 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-RX.S -// PMP Test in NA4 address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - (pmpcfg0 >> 8) & 0x18 == 0x10 : 0 // CHECK pmp2cfg in NA4 mode? - (pmpcfg0 >> 8) & 0x01 == 0x01 : 0 // CHECK R-bit in pmp2cfg was HIGH - (pmpcfg0 >> 8) & 0x02 == 0x02 : 0 // CHECK W-bit in pmp2cfg was HIGH - (pmpcfg0 >> 8) & 0x04 == 0x04 : 0 // CHECK X-bit in pmp2cfg was HIGH -// Details are given in /coverage/rv32i_priv.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_rx) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NA4 Mode with RX enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_X|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[7:0] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION4) - // Value to be stored in pmpcfg1 register ; Setting up PMP Region-4 - csrs pmpcfg1, x4 // Updated pmpcfg1 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-X-priority-level-2.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-X-priority-level-2.S deleted file mode 100644 index 60bf86bbf..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-X-priority-level-2.S +++ /dev/null @@ -1,207 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-x-level-2.S -// Tests the priority by assigning only X permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_x_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_X|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-X-priority.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-X-priority.S deleted file mode 100644 index 582181d43..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-X-priority.S +++ /dev/null @@ -1,187 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-priority-x.S -// PMP Test in NA4 address matching mode -// Description: -// Tests the priority by assigning only X permissions to the high priority while R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_x) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3[31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_X|PMP_NA4)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-X.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-X.S deleted file mode 100644 index 4bad5e616..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NA4-X.S +++ /dev/null @@ -1,224 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-X.S -// PMP Test in NA4 address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - (pmpcfg0 >> 8) & 0x18 == 0x10 : 0 // CHECK pmp2cfg in NA4 mode? - (pmpcfg0 >> 8) & 0x01 == 0x01 : 0 // CHECK R-bit in pmp2cfg was HIGH - (pmpcfg0 >> 8) & 0x02 == 0x02 : 0 // CHECK W-bit in pmp2cfg was HIGH - (pmpcfg0 >> 8) & 0x04 == 0x04 : 0 // CHECK X-bit in pmp2cfg was HIGH -// Details are given in /coverage/rv32i_priv.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_x) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NA4 Mode with X enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_X|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[7:0] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION4) - // Value to be stored in pmpcfg1 register ; Setting up PMP Region-4 - csrs pmpcfg1, x4 // Updated pmpcfg1 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-R-priority-level-2.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-R-priority-level-2.S deleted file mode 100644 index 4a7158277..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-R-priority-level-2.S +++ /dev/null @@ -1,207 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-r-level-2.S -// Tests the priority by assigning only R permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_r_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-R-priority.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-R-priority.S deleted file mode 100644 index 3b92b0593..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-R-priority.S +++ /dev/null @@ -1,187 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-r.S -// PMP Test in NAPOT address matching mode -// Description: -// Tests the priority by assigning only R permissions to the high priority while R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_r) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3[31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_R|PMP_NAPOT)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-R.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-R.S deleted file mode 100644 index 038324dd9..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-R.S +++ /dev/null @@ -1,225 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-R.S -// PMP Test in NAPOT address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=0 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - (pmpcfg0 >> 16) & 0x18 == 0x18 : 0 // CHECK pmp2cfg in NAPOT mode? - (pmpcfg0 >> 16) & 0x01 == 0x01 : 0 // CHECK R-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x02 == 0x02 : 0 // CHECK W-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x04 == 0x04 : 0 // CHECK X-bit in pmp2cfg was HIGH -// Details are given in /coverage/rv32i_priv.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_r) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[7:0] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1. Then a PMP region is configure into NAPOT mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION4) - // Value to be stored in pmpcfg1 register ; Setting up PMP Region-4 - csrs pmpcfg1, x4 // Updated pmpcfg1 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RW-priority-level-2.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RW-priority-level-2.S deleted file mode 100644 index e706e31fa..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RW-priority-level-2.S +++ /dev/null @@ -1,207 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-rw-level-2.S -// Tests the priority by assigning only R, w permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_rw_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RW-priority.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RW-priority.S deleted file mode 100644 index b5c3acb9d..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RW-priority.S +++ /dev/null @@ -1,187 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-rw.S -// PMP Test in NAPOT address matching mode -// Description: -// Tests the priority by assigning only R,W permissions to the high priority while R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_rw) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3[31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_R|PMP_W|PMP_NAPOT)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RW.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RW.S deleted file mode 100644 index a5d735e4c..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RW.S +++ /dev/null @@ -1,225 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-RW.S -// PMP Test in NAPOT address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=0 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - (pmpcfg0 >> 16) & 0x18 == 0x18 : 0 // CHECK pmp2cfg in NAPOT mode? - (pmpcfg0 >> 16) & 0x01 == 0x01 : 0 // CHECK R-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x02 == 0x02 : 0 // CHECK W-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x04 == 0x04 : 0 // CHECK X-bit in pmp2cfg was HIGH -// Details are given in /coverage/rv32i_priv.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_rw) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with RW enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_W|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[7:0] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION4) - // Value to be stored in pmpcfg1 register ; Setting up PMP Region-4 - csrs pmpcfg1, x4 // Updated pmpcfg1 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RWX.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RWX.S deleted file mode 100644 index e64808957..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RWX.S +++ /dev/null @@ -1,226 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-RWX.S -// PMP Test in NAPOT address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=0 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - (pmpcfg0 >> 16) & 0x18 == 0x18 : 0 // CHECK pmp2cfg in NAPOT mode? - (pmpcfg0 >> 16) & 0x01 == 0x01 : 0 // CHECK R-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x02 == 0x02 : 0 // CHECK W-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x04 == 0x04 : 0 // CHECK X-bit in pmp2cfg was HIGH -// Details are given in /coverage/rv32i_priv.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_rwx) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with RWX enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[7:0] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION4) - // Value to be stored in pmpcfg1 register ; Setting up PMP Region-4 - csrs pmpcfg1, x4 // Updated pmpcfg1 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x0, x0, 0 - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RX-priority-level-2.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RX-priority-level-2.S deleted file mode 100644 index f339ac3ad..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RX-priority-level-2.S +++ /dev/null @@ -1,207 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-rx-level-2.S -// Tests the priority by assigning only R,X permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_rx_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_X|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RX-priority.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RX-priority.S deleted file mode 100644 index b110d10c3..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RX-priority.S +++ /dev/null @@ -1,187 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-rx.S -// PMP Test in NAPOT address matching mode -// Description: -// Tests the priority by assigning only R,X permissions to the high priority while R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_rx) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3[31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_R|PMP_X|PMP_NAPOT)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RX.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RX.S deleted file mode 100644 index 5def8e539..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-RX.S +++ /dev/null @@ -1,225 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-RX.S -// PMP Test in NAPOT address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=0 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - (pmpcfg0 >> 16) & 0x18 == 0x18 : 0 // CHECK pmp2cfg in NAPOT mode? - (pmpcfg0 >> 16) & 0x01 == 0x01 : 0 // CHECK R-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x02 == 0x02 : 0 // CHECK W-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x04 == 0x04 : 0 // CHECK X-bit in pmp2cfg was HIGH -// Details are given in /coverage/rv32i_priv.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_rx) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with RX enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_X|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[7:0] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION4) - // Value to be stored in pmpcfg1 register ; Setting up PMP Region-4 - csrs pmpcfg1, x4 // Updated pmpcfg1 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-X-priority-level-2.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-X-priority-level-2.S deleted file mode 100644 index b9cc6f1e5..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-X-priority-level-2.S +++ /dev/null @@ -1,207 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-x-level-2.S -// Tests the priority by assigning only X permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_x_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_X|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-X-priority.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-X-priority.S deleted file mode 100644 index 7eaafa2f5..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-X-priority.S +++ /dev/null @@ -1,187 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-x.S -// PMP Test in NAPOT address matching mode -// Description: -// Tests the priority by assigning only X permissions to the high priority while R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_x) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3[31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_X|PMP_NAPOT)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-X.S b/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-X.S deleted file mode 100644 index 113afd1cd..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-NAPOT-X.S +++ /dev/null @@ -1,225 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-X.S -// PMP Test in NAPOT address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=0 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - (pmpcfg0 >> 16) & 0x18 == 0x18 : 0 // CHECK pmp2cfg in NAPOT mode? - (pmpcfg0 >> 16) & 0x01 == 0x01 : 0 // CHECK R-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x02 == 0x02 : 0 // CHECK W-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x04 == 0x04 : 0 // CHECK X-bit in pmp2cfg was HIGH -// Details are given in /coverage/rv32i_priv.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_x) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with X enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_X|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[7:0] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION4) - // Value to be stored in pmpcfg1 register ; Setting up PMP Region-4 - csrs pmpcfg1, x4 // Updated pmpcfg1 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-R-priority-level-2.S b/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-R-priority-level-2.S deleted file mode 100644 index 16ec49070..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-R-priority-level-2.S +++ /dev/null @@ -1,213 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-r-level-2.S -// Tests the priority by assigning only R permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_r_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_L|PMP_TOR)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS2 = value to be loaded pmpaddr0 to declare lower address of Region-3 -#define PMPADDRESS0 TEST_FOR_EXECUTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-R-priority.S b/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-R-priority.S deleted file mode 100644 index 7bd2b6724..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-R-priority.S +++ /dev/null @@ -1,192 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-r.S -// Tests the priority by assigning only R permissions to the high priority while R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_r) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr3 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-R.S b/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-R.S deleted file mode 100644 index dc5bc50d8..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-R.S +++ /dev/null @@ -1,231 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-tor-R.S -// PMP Test in TOR address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -*/ -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - (pmpcfg0 >> 16) & 0x18 == 0x08 : 0 // CHECK pmp2cfg in TOR mode? - (pmpcfg0 >> 16) & 0x01 == 0x01 : 0 // CHECK R-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x02 == 0x02 : 0 // CHECK W-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x04 == 0x04 : 0 // CHECK X-bit in pmp2cfg was HIGH -// Details are given in /coverage/rv32i_priv.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_r) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[23:16] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in TOR Mode with X enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_L|PMP_TOR)&0xFF) << PMP2_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[7:0] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RW enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[15:8] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare upper address of region2 -#define PMPADDRESS2 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare lower address of region3 -#define PMPADDRESS3 RAM_LOCATION_FOR_TEST -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region3 -#define PMPADDRESS4 rvtest_code_end -// PMPADDRESS5 = value to be loaded pmpaddr5 to declare upper address of region4 -#define PMPADDRESS5 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x8000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION => PMP region under test. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and rvtest_code_end into pmpaddr2. Then a PMP region is configure from pmpaddr2(RETURN_INSTRUCTION) to pmpaddr1(TEST_FOR_EXECUTION) into TOR mode by setting pmpcfg0[23:16]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr4 and RAM_LOCATION_FOR_TEST into pmpaddr3. configure pmpaddr4(RAM_LOCATION_FOR_TEST) to pmpaddr5(rvtest_code_end) into TOR mode by setting pmpcfg1[15:8]=PMPREGION3 - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr4(rvtest_code_end) to pmpaddr5(PMP_region_High) into TOR mode by setting pmpcfg1[15:8]=PMPREGION4. This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - LA(x4, PMPADDRESS5) // Value to be stored in pmpaddr5 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr5, x4 // Updated pmpaddr5 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg1 register - csrs pmpcfg1, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RW-priority-level-2..S b/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RW-priority-level-2..S deleted file mode 100644 index a378fd361..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RW-priority-level-2..S +++ /dev/null @@ -1,215 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-rw-level-2.S -// Tests the priority by assigning only R,W permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_rw_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R,W enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_L|PMP_TOR)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS2 = value to be loaded pmpaddr0 to declare lower address of Region-3 -#define PMPADDRESS0 TEST_FOR_EXECUTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 1*(XLEN/32),4,NOP //Single - -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION - -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RW-priority.S b/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RW-priority.S deleted file mode 100644 index ec9d143c2..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RW-priority.S +++ /dev/null @@ -1,192 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-rw.S -// Tests the priority by assigning only rw permissions to the high priority while R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_rw) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_W|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr3 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RW.S b/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RW.S deleted file mode 100644 index 093d16e62..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RW.S +++ /dev/null @@ -1,231 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-tor-RW.S -// PMP Test in TOR address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -*/ -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - (pmpcfg0 >> 16) & 0x18 == 0x08 : 0 // CHECK pmp2cfg in TOR mode? - (pmpcfg0 >> 16) & 0x01 == 0x01 : 0 // CHECK R-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x02 == 0x02 : 0 // CHECK W-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x04 == 0x04 : 0 // CHECK X-bit in pmp2cfg was HIGH -// Details are given in /coverage/rv32i_priv.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_rw) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[23:16] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in TOR Mode with X enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_W|PMP_L|PMP_TOR)&0xFF) << PMP2_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[7:0] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RW enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[15:8] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare upper address of region2 -#define PMPADDRESS2 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare lower address of region3 -#define PMPADDRESS3 RAM_LOCATION_FOR_TEST -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region3 -#define PMPADDRESS4 rvtest_code_end -// PMPADDRESS5 = value to be loaded pmpaddr5 to declare upper address of region4 -#define PMPADDRESS5 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x8000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION => PMP region under test. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and rvtest_code_end into pmpaddr2. Then a PMP region is configure from pmpaddr2(RETURN_INSTRUCTION) to pmpaddr1(TEST_FOR_EXECUTION) into TOR mode by setting pmpcfg0[23:16]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr4 and RAM_LOCATION_FOR_TEST into pmpaddr3. configure pmpaddr4(RAM_LOCATION_FOR_TEST) to pmpaddr5(rvtest_code_end) into TOR mode by setting pmpcfg1[15:8]=PMPREGION3 - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr4(rvtest_code_end) to pmpaddr5(PMP_region_High) into TOR mode by setting pmpcfg1[15:8]=PMPREGION4. This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - LA(x4, PMPADDRESS5) // Value to be stored in pmpaddr5 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr5, x4 // Updated pmpaddr5 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg1 register - csrs pmpcfg1, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RWX-priority-level-2.S b/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RWX-priority-level-2.S deleted file mode 100644 index 4fb2b8380..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RWX-priority-level-2.S +++ /dev/null @@ -1,215 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-rwx-level-2.S -// Tests the priority by assigning only R,W,X permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_rwx_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R,W enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS2 = value to be loaded pmpaddr0 to declare lower address of Region-3 -#define PMPADDRESS0 TEST_FOR_EXECUTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 1*(XLEN/32),4,NOP //Single - -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION - -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RWX.S b/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RWX.S deleted file mode 100644 index 694ad37ec..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RWX.S +++ /dev/null @@ -1,231 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-tor-RWX.S -// PMP Test in TOR address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -*/ -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - (pmpcfg0 >> 16) & 0x18 == 0x08 : 0 // CHECK pmp2cfg in TOR mode? - (pmpcfg0 >> 16) & 0x01 == 0x01 : 0 // CHECK R-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x02 == 0x02 : 0 // CHECK W-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x04 == 0x04 : 0 // CHECK X-bit in pmp2cfg was HIGH -// Details are given in /coverage/rv32i_priv.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_rwx) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[23:16] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in TOR Mode with RWX enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP2_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[7:0] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RW enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[15:8] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare upper address of region2 -#define PMPADDRESS2 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare lower address of region3 -#define PMPADDRESS3 RAM_LOCATION_FOR_TEST -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region3 -#define PMPADDRESS4 rvtest_code_end -// PMPADDRESS5 = value to be loaded pmpaddr5 to declare upper address of region4 -#define PMPADDRESS5 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x8000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION => PMP region under test. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and rvtest_code_end into pmpaddr2. Then a PMP region is configure from pmpaddr2(RETURN_INSTRUCTION) to pmpaddr1(TEST_FOR_EXECUTION) into TOR mode by setting pmpcfg0[23:16]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr4 and RAM_LOCATION_FOR_TEST into pmpaddr3. configure pmpaddr4(RAM_LOCATION_FOR_TEST) to pmpaddr5(rvtest_code_end) into TOR mode by setting pmpcfg1[15:8]=PMPREGION3 - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr4(rvtest_code_end) to pmpaddr5(PMP_region_High) into TOR mode by setting pmpcfg1[15:8]=PMPREGION4. This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - LA(x4, PMPADDRESS5) // Value to be stored in pmpaddr5 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr5, x4 // Updated pmpaddr5 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg1 register - csrs pmpcfg1, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RX-priority-level-2.S b/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RX-priority-level-2.S deleted file mode 100644 index c949122fb..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RX-priority-level-2.S +++ /dev/null @@ -1,215 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-rx-level-2.S -// Tests the priority by assigning only R, X permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_rx_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R,W enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS2 = value to be loaded pmpaddr0 to declare lower address of Region-3 -#define PMPADDRESS0 TEST_FOR_EXECUTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 1*(XLEN/32),4,NOP //Single - -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION - -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RX-priority.S b/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RX-priority.S deleted file mode 100644 index efb04a8e1..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RX-priority.S +++ /dev/null @@ -1,192 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-rx.S -// Tests the priority by assigning only rx permissions to the high priority while R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_rx) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr3 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RX.S b/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RX.S deleted file mode 100644 index 4ee57fc98..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-RX.S +++ /dev/null @@ -1,231 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-tor-RX.S -// PMP Test in TOR address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -*/ -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - (pmpcfg0 >> 16) & 0x18 == 0x08 : 0 // CHECK pmp2cfg in TOR mode? - (pmpcfg0 >> 16) & 0x01 == 0x01 : 0 // CHECK R-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x02 == 0x02 : 0 // CHECK W-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x04 == 0x04 : 0 // CHECK X-bit in pmp2cfg was HIGH -// Details are given in /coverage/rv32i_priv.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_rx) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[23:16] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in TOR Mode with RX enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP2_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[7:0] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RW enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[15:8] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare upper address of region2 -#define PMPADDRESS2 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare lower address of region3 -#define PMPADDRESS3 RAM_LOCATION_FOR_TEST -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region3 -#define PMPADDRESS4 rvtest_code_end -// PMPADDRESS5 = value to be loaded pmpaddr5 to declare upper address of region4 -#define PMPADDRESS5 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x8000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION => PMP region under test. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and rvtest_code_end into pmpaddr2. Then a PMP region is configure from pmpaddr2(RETURN_INSTRUCTION) to pmpaddr1(TEST_FOR_EXECUTION) into TOR mode by setting pmpcfg0[23:16]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr4 and RAM_LOCATION_FOR_TEST into pmpaddr3. configure pmpaddr4(RAM_LOCATION_FOR_TEST) to pmpaddr5(rvtest_code_end) into TOR mode by setting pmpcfg1[15:8]=PMPREGION3 - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr4(rvtest_code_end) to pmpaddr5(PMP_region_High) into TOR mode by setting pmpcfg1[15:8]=PMPREGION4. This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - LA(x4, PMPADDRESS5) // Value to be stored in pmpaddr5 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr5, x4 // Updated pmpaddr5 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg1 register - csrs pmpcfg1, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-X-priority-level-2.S b/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-X-priority-level-2.S deleted file mode 100644 index 1730bc32d..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-X-priority-level-2.S +++ /dev/null @@ -1,215 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-x-level-2.S -// Tests the priority by assigning only X permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_x_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R,W enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS2 = value to be loaded pmpaddr0 to declare lower address of Region-3 -#define PMPADDRESS0 TEST_FOR_EXECUTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 1*(XLEN/32),4,NOP //Single - -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION - -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-X-priority.S b/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-X-priority.S deleted file mode 100644 index 4c4a22a98..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-X-priority.S +++ /dev/null @@ -1,192 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-x.S -// Tests the priority by assigning only X permissions to the high priority while R-W-X to low priority region -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_x) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg3 [31:24] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr3 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg3, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-X.S b/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-X.S deleted file mode 100644 index d668a81cf..000000000 --- a/riscv-test-suite/rv32i_m/pmp32/pmp-TOR-X.S +++ /dev/null @@ -1,231 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-tor-X.S -// PMP Test in TOR address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -*/ -/* COVERPOINTS: (Explanation of updates in /coverage/rv32i_priv.cgf) - (pmpcfg0 >> 16) & 0x18 == 0x08 : 0 // CHECK pmp2cfg in TOR mode? - (pmpcfg0 >> 16) & 0x01 == 0x01 : 0 // CHECK R-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x02 == 0x02 : 0 // CHECK W-bit in pmp2cfg was HIGH - (pmpcfg0 >> 16) & 0x04 == 0x04 : 0 // CHECK X-bit in pmp2cfg was HIGH -// Details are given in /coverage/rv32i_priv.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_x) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 4 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[23:16] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in TOR Mode with RX enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP2_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[7:0] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RW enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[15:8] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare upper address of region2 -#define PMPADDRESS2 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare lower address of region3 -#define PMPADDRESS3 RAM_LOCATION_FOR_TEST -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region3 -#define PMPADDRESS4 rvtest_code_end -// PMPADDRESS5 = value to be loaded pmpaddr5 to declare upper address of region4 -#define PMPADDRESS5 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x8000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION => PMP region under test. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and rvtest_code_end into pmpaddr2. Then a PMP region is configure from pmpaddr2(RETURN_INSTRUCTION) to pmpaddr1(TEST_FOR_EXECUTION) into TOR mode by setting pmpcfg0[23:16]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr4 and RAM_LOCATION_FOR_TEST into pmpaddr3. configure pmpaddr4(RAM_LOCATION_FOR_TEST) to pmpaddr5(rvtest_code_end) into TOR mode by setting pmpcfg1[15:8]=PMPREGION3 - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr4(rvtest_code_end) to pmpaddr5(PMP_region_High) into TOR mode by setting pmpcfg1[15:8]=PMPREGION4. This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - LA(x4, PMPADDRESS5) // Value to be stored in pmpaddr5 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr5, x4 // Updated pmpaddr5 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg1 register - csrs pmpcfg1, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-CFG-reg.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-CFG-reg.S deleted file mode 100644 index c913f06aa..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-CFG-reg.S +++ /dev/null @@ -1,132 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -// -// This assembly file tests access of pmp registers in M, S, and U mode. -// pmp csrs are accessable only in M-mode so it should trap in S, and U mode. -// -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",pmp_cfg_locked_write_unrelated) -RVTEST_SIGBASE( x3,signature_x3_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x9,0) // The register to carry offset value - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - csrc pmpcfgi , a5 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrc pmpaddri, a5 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -//////////////////// Locked bit TEST 1 ///////////////////////////////////////////// - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi, a5 // WRITE pmpcfgi with ALL 1s, Locked the lock-bit [7,15,23,31] - nop // Added nop in case of trap - csrr a4, pmpcfgi // READ pmpcfgi - // THIS READ WILL ALSO CONFIRM THE ZERO BITs OF PMPCFGi REG. - // BIT 5-6, BIT 13-14, BIT 21-22, BIT 29-30 must be hardwired to zero - // Verify that LOCKED bits are HIGH, and ZERO bits are zero - RVTEST_SIGUPD(x3,a4) - // TRY TO WRITE CFG REGISTER AGAIN (TRAP in case of LOCKED bit is HIGH) - csrw pmpcfgi, x5 // WRITE pmpcfgi with some other values - nop // Added nop in case of trap - csrr a4, pmpcfgi // READ pmpcfgi - // Since Locked bit is high, so this should return the old value!!! - RVTEST_SIGUPD(x3,a4) - - .set pmpaddri, PMPADDR0+4*(pmpcfgi-PMPCFG0) -// Initialize an iterating variable with the address of pmpaddr0 in 1st iteration (when pmpcfgi=pmpcfg0) -// Initialize an iterating variable with the address of pmpaddr4 in 2nd iteration (when pmpcfgi=pmpcfg1) -// Initialize an iterating variable with the address of pmpaddr8 in 3rd iteration (when pmpcfgi=pmpcfg2) -// Initialize an iterating variable with the address of pmpaddr12 in 4th iteration (when pmpcfgi=pmpcfg3) - .rept 8 // START OF LOOP - // TRY TO WRITE ADDRESS REGISTER. - csrw pmpaddri, a5 // WRITE pmpaddri with some other values - // The updated write will give a trap!!! - nop // Added nop in case of trap - csrr a4, pmpaddri // READ pmpaddr0, value should not have been changed - nop // Added nop in case of trap - RVTEST_SIGUPD(x3,a4) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF INNER LOOP BODY - - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg .endr // END OF OUTER LOOP BODY - .endr -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x3_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-CSR-access.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-CSR-access.S deleted file mode 100644 index 03a1af71f..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-CSR-access.S +++ /dev/null @@ -1,247 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -// -// This assembly file tests access of pmp registers in M, S, and U mode. -// pmp csrs are accessable only in M-mode so it should trap in S, and U mode. -// -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -// -#define rvtest_strap_routine -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",PMP_access_permission) -RVTEST_SIGBASE( x13,signature_x13_1) - .option nopic - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 -main: -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - csrc pmpcfgi , a5 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrc pmpaddri, a5 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY -//////////////// VERIFICATION ///////////////////////////////////////// -// READING pmpaddr in M-mode ///////////////////////////////////////// - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrr a4, pmpaddri // READING pmpaddri (i is from 0-15) - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,a4) // Storing into signature file - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY -// WRITING pmpaddr in M-mode ///////////////////////////////////////// - LI(a4,0x01) // RANDOM VALUE - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, a4 // WRITING pmpaddri (i is from 0-15) - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,a4) // Storing into signature file - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY -// WRITING pmpcfg registers ////////////////////////////////////////// -// Write in M-mode will be valid, Write in other modes will cause trap - LI(a5, PMP_R| PMP_W | PMP_X | PMP_TOR) // LOCKED BIT IS NOT SET - // Loop to Write ALL pmpcfg regs - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - csrw pmpcfgi, a5 // Write pmpcfgi - nop // Added nop in case of trap - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY -//////////////// VERIFICATION ///////////////////////////////////////// -// READING pmpcfg in M-mode ///////////////////////////////////////// - // Loop to verify the contents of pmpcfg regs - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - csrr a4, pmpcfg0 // Read pmpcfg0 - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,a4) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY -/////////////////// Switch to S-mode //////////////////////////////////////////// - csrw satp, zero // Disable address translation. - LI(t2, -1) - csrw pmpaddr0, t2 // Updated pmpaddr0 to define PMP region consisting - // of whole physical memory - csrr t0, pmpaddr0 // Verify its value by reading back - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,t0) - nop // Added nop in case of trap - LI(a5, PMP_L| PMP_R| PMP_W | PMP_X | PMP_TOR) // LOCKED BIT IS SET - csrw pmpcfg0, a5 - - RVTEST_GOTO_LOWER_MODE Smode // GO into S mode -// REPEATING THE SAME TEST ////////////////////////////////////////// -// IN Smode now -/////////////////// TEST 01 //////////////////////////////////////////// -// READING pmpaddr in S-mode ///////////////////////////////////////// - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 4 // START OF LOOP - csrr a4, pmpaddri // READING pmpaddri (i is from 0-15) - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,a4) // Storing into signature file - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY -// WRITING pmpaddr in S-mode ///////////////////////////////////////// - LI(a4,0x01) // RANDOM VALUE - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 4 // START OF LOOP - csrw pmpaddri, a4 // WRITING pmpaddri (i is from 0-15) - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,a4) // Storing into signature file - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY -// WRITING pmpcfg registers ////////////////////////////////////////// -// Write in M-mode will be valid, Write in other modes will cause trap - LI(a5, PMP_R| PMP_W | PMP_X | PMP_TOR) // LOCKED BIT IS NOT SET - // Loop to Write ALL pmpcfg regs - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - csrw pmpcfgi, a5 // Write pmpcfgi - nop // Added nop in case of trap - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY -//////////////// VERIFICATION ///////////////////////////////////////// -// READING pmpcfg in S-mode ///////////////////////////////////////// - // Loop to verify the contents of pmpcfg regs - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - csrr a4, pmpcfg0 // Read pmpcfg0 - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,a4) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,a4) -/////////////////// Switch to U-mode //////////////////////////////////////////// - csrw satp, zero // Disable address translation. - LI(t2, -1) - csrw pmpaddr0, t2 // Updated pmpaddr0 to define PMP region consisting - // of whole physical memory - csrr t0, pmpaddr0 // Verify its value by reading back - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,t0) - nop // Added nop in case of trap - LI(a5, PMP_L| PMP_R| PMP_W | PMP_X | PMP_TOR) // LOCKED BIT IS SET - csrw pmpcfg0, a5 -// These steps are repeated and can be removed but it will make sure that you will switch mode -// with full access on physical memory - RVTEST_GOTO_LOWER_MODE Umode -// REPEATING THE SAME TEST ////////////////////////////////////////// -// IN U-mode now -// READING pmpaddr in U-mode ///////////////////////////////////////// - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 4 // START OF LOOP - csrr a4, pmpaddri // READING pmpaddri (i is from 0-15) - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,a4) // Storing into signature file - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY -// WRITING pmpaddr in U-mode ///////////////////////////////////////// - LI(a4,0x01) // RANDOM VALUE - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 4 // START OF LOOP - csrw pmpaddri, a4 // WRITING pmpaddri (i is from 0-15) - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,a4) // Storing into signature file - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY -// WRITING pmpcfg registers ////////////////////////////////////////// -// Write in M-mode will be valid, Write in other modes will cause trap - LI(a5, PMP_R| PMP_W | PMP_X | PMP_TOR) // LOCKED BIT IS NOT SET - // Loop to Write ALL pmpcfg regs - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - csrw pmpcfgi, a5 // Write pmpcfgi - nop // Added nop in case of trap - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY -//////////////// VERIFICATION ///////////////////////////////////////// -// READING pmpcfg in U-mode ///////////////////////////////////////// - // Loop to verify the contents of pmpcfg regs - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - csrr a4, pmpcfg0 // Read pmpcfg0 - nop // Added nop in case of trap - RVTEST_SIGUPD(x13,a4) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - -#endif - - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 256*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S deleted file mode 100644 index 95d705567..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S +++ /dev/null @@ -1,213 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-priority-r-level-2.S -// Tests the priority by assigning only R permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True", PMP_NA4_priority_r_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x8000 0000 to Address RVMODEL_DATA_END => PMP TOR (Low Priority) Region with RWX enabled. For this purpose, pmpaddr14 has been given the value of 0 and pmpaddr15 is given address to RVMODEL_DATA_END to declare the region from 0->RVMODEL_DATA_END into a single PMP region. - -2. Address RAM_LOCATION_FOR_TEST to Address RETURN_INSTRUCTION => PMP region under test. This region has been declared by entering RAM_LOCATION_FOR_TEST into pmpaddr2 and address to RETURN_INSTRUCTION label into pmpaddr3. Then a PMP region is configure from pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(RETURN_INSTRUCTION) into TOR mode by setting pmpcfg0[31:24]=PMPREGION2 - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-R-priority.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-R-priority.S deleted file mode 100644 index c057e39ef..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-R-priority.S +++ /dev/null @@ -1,191 +0,0 @@ - -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-priority-r.S -// PMP Test in NA4 address matching mode -// Description: -// Tests the priority by assigning only R permissions to the high priority while R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_r) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2[63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_R|PMP_NA4)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg3 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-R.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-R.S deleted file mode 100644 index 661b62312..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-R.S +++ /dev/null @@ -1,216 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-R.S -// PMP Test in NA4 address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=0 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_r) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP4_CFG_SHIFT 32 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NA4 Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[39:32] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP4_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=((PMP_R|PMP_L|PMP_NA4)&0xFF) - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3,4 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S deleted file mode 100644 index 54abfc286..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S +++ /dev/null @@ -1,209 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-rw-level-2.S -// Tests the priority by assigning only R,W permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_rw_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RW-priority.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RW-priority.S deleted file mode 100644 index d46633a58..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RW-priority.S +++ /dev/null @@ -1,190 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-priority-rw.S -// PMP Test in NA4 address matching mode -// Description: -// Tests the priority by assigning only R,W permissions to the high priority while R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_rw) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2[63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_R|PMP_W|PMP_NA4)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RW.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RW.S deleted file mode 100644 index eb527aaf9..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RW.S +++ /dev/null @@ -1,218 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-RW.S -// PMP Test in NA4 address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=0 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_rw) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP4_CFG_SHIFT 32 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NA4 Mode with RW enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_W|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[39:32] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP4_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=((PMP_R|PMP_W|PMP_L|PMP_NA4)&0xFF) - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RWX.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RWX.S deleted file mode 100644 index 284d4f85e..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RWX.S +++ /dev/null @@ -1,231 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-RWX.S -// PMP Test in NA4 address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_rwx) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP4_CFG_SHIFT 32 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - csrc pmpcfgi , a5 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrc pmpaddri, a5 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NA4 Mode with RW enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[39:32] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP4_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. -This region is the part of the code memory containing our code and the region between code_end to data_begin. -For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to -declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail.) -This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. -Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. -This region has been declared by entering rvtest_code_end into pmpaddr3 and -RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) -to pmpaddr3(rvtest_code_end) into TOR mode -by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. -This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. -For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) -into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). -This PMP Region is mandatory to access signature area in S,U mode */ - - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - nop - j exit -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - - - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RX-priority-level-2.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RX-priority-level-2.S deleted file mode 100644 index 86e9d8714..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RX-priority-level-2.S +++ /dev/null @@ -1,209 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-rx-level-2.S -// Tests the priority by assigning only R,X permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_rx_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_X|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RX-priority.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RX-priority.S deleted file mode 100644 index 89c837047..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RX-priority.S +++ /dev/null @@ -1,190 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-priority-rx.S -// PMP Test in NA4 address matching mode -// Description: -// Tests the priority by assigning only R,X permissions to the high priority while R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_rx) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2[63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_R|PMP_X|PMP_NA4)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RX.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RX.S deleted file mode 100644 index f51135d6e..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RX.S +++ /dev/null @@ -1,216 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-RX.S -// PMP Test in NA4 address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_rx) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP4_CFG_SHIFT 32 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NA4 Mode with RX enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_X|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[39:32] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP4_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-X-priority-level-2.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-X-priority-level-2.S deleted file mode 100644 index 2b1c9f213..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-X-priority-level-2.S +++ /dev/null @@ -1,210 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-x-level-2.S -// Tests the priority by assigning only X permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_x_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_X|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-X-priority.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-X-priority.S deleted file mode 100644 index cea1a448c..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-X-priority.S +++ /dev/null @@ -1,190 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-priority-x.S -// PMP Test in NA4 address matching mode -// Description: -// Tests the priority by assigning only X permissions to the high priority while R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_priority_x) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2[63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_X|PMP_NA4)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-X.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-X.S deleted file mode 100644 index 28725ca9f..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-X.S +++ /dev/null @@ -1,216 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NA4-X.S -// PMP Test in NA4 address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NA4_x) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP4_CFG_SHIFT 32 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NA4 Mode with X enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_X|PMP_L|PMP_NA4)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[39:32] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP4_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-R-priority-level-2.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-R-priority-level-2.S deleted file mode 100644 index 96d47e938..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-R-priority-level-2.S +++ /dev/null @@ -1,210 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-r-level-2.S -// Tests the priority by assigning only R permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_r_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-R-priority.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-R-priority.S deleted file mode 100644 index de1d99339..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-R-priority.S +++ /dev/null @@ -1,190 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-r.S -// PMP Test in NAPOT address matching mode -// Description: -// Tests the priority by assigning only R permissions to the high priority while R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_r) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2[63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_R|PMP_NAPOT)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-R.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-R.S deleted file mode 100644 index 1570f25f7..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-R.S +++ /dev/null @@ -1,217 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-R.S -// PMP Test in NAPOT address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=0 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_r) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP4_CFG_SHIFT 32 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop - jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[39:32] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP4_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1. Then a PMP region is configure into NAPOT mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RW-priority-level-2.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RW-priority-level-2.S deleted file mode 100644 index 6fae368c5..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RW-priority-level-2.S +++ /dev/null @@ -1,210 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-rw-level-2.S -// Tests the priority by assigning only R, w permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_rw_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RW-priority.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RW-priority.S deleted file mode 100644 index a15669b37..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RW-priority.S +++ /dev/null @@ -1,190 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-rw.S -// PMP Test in NAPOT address matching mode -// Description: -// Tests the priority by assigning only R,W permissions to the high priority while R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_rw) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2[63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_R|PMP_W|PMP_NAPOT)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RW.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RW.S deleted file mode 100644 index 4deedb4c4..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RW.S +++ /dev/null @@ -1,217 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-RW.S -// PMP Test in NAPOT address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=0 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_rw) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP4_CFG_SHIFT 32 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with RW enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_W|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[39:32] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP4_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RWX.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RWX.S deleted file mode 100644 index c32d06e9a..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RWX.S +++ /dev/null @@ -1,218 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-RWX.S -// PMP Test in NAPOT address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=0 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_rwx) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP4_CFG_SHIFT 32 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with RWX enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[39:32] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP4_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x0, x0, 0 - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RX-priority-level-2.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RX-priority-level-2.S deleted file mode 100644 index 6cd4173e7..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RX-priority-level-2.S +++ /dev/null @@ -1,210 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-rx-level-2.S -// Tests the priority by assigning only R,X permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_rx_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_X|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RX-priority.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RX-priority.S deleted file mode 100644 index 934bdadfa..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RX-priority.S +++ /dev/null @@ -1,190 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-rx.S -// PMP Test in NAPOT address matching mode -// Description: -// Tests the priority by assigning only R,X permissions to the high priority while R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_rx) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2[63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_R|PMP_X|PMP_NAPOT)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RX.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RX.S deleted file mode 100644 index 0efa98663..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RX.S +++ /dev/null @@ -1,217 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-RX.S -// PMP Test in NAPOT address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=0 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_rx) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP4_CFG_SHIFT 32 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with RX enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_X|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[39:32] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP4_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-X-priority-level-2.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-X-priority-level-2.S deleted file mode 100644 index 1c509f6d1..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-X-priority-level-2.S +++ /dev/null @@ -1,210 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-x-level-2.S -// Tests the priority by assigning only X permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_x_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_X|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-X-priority.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-X-priority.S deleted file mode 100644 index e662a6be3..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-X-priority.S +++ /dev/null @@ -1,190 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-priority-x.S -// PMP Test in NAPOT address matching mode -// Description: -// Tests the priority by assigning only X permissions to the high priority while R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_priority_x) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2[63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_X|PMP_NAPOT)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 TEST_FOR_EXECUTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-X.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-X.S deleted file mode 100644 index 64324734b..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-X.S +++ /dev/null @@ -1,217 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-NAPOT-X.S -// PMP Test in NAPOT address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=0 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -*/ -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_NAPOT_x) -RVTEST_SIGBASE( x13,signature_x13_1) - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP4_CFG_SHIFT 32 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in NAPOT Mode with X enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_X|PMP_L|PMP_NAPOT)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RWX enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[39:32] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP4_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of region3 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of region3 -#define PMPADDRESS3 rvtest_code_end -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region4 -#define PMPADDRESS4 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x0000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION =====> This is the PMP region under test (A 4byte region == Granularity of Sail. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and RETURN_INSTRUCTION into pmpaddr2. Then a PMP region is configure into NA4 mode by setting pmpcfg0[15:8]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => Another PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr3 and RAM_LOCATION_FOR_TEST into pmpaddr2. configure pmpaddr2(RAM_LOCATION_FOR_TEST) to pmpaddr3(rvtest_code_end) into TOR mode by setting pmpcfg0[31:24]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr3(rvtest_code_end) to pmpaddr4(PMP_region_High) into TOR mode by setting pmpcfg1[7:0]=((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)). This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg register ; Setting Up PMP Region-1,2,3 - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-R-priority-level-2.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-R-priority-level-2.S deleted file mode 100644 index db2141b8f..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-R-priority-level-2.S +++ /dev/null @@ -1,216 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-r-level-2.S -// Tests the priority by assigning only R permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_r_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_L|PMP_TOR)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS2 = value to be loaded pmpaddr0 to declare lower address of Region-3 -#define PMPADDRESS0 TEST_FOR_EXECUTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-R-priority.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-R-priority.S deleted file mode 100644 index d66aa19cf..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-R-priority.S +++ /dev/null @@ -1,195 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-r.S -// Tests the priority by assigning only R permissions to the high priority while R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_r) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr3 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-R.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-R.S deleted file mode 100644 index 6865aff6a..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-R.S +++ /dev/null @@ -1,224 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-tor-R.S -// PMP Test in TOR address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -*/ -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_r) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP4_CFG_SHIFT 32 -#define PMP5_CFG_SHIFT 40 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[23:16] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in TOR Mode with X enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_L|PMP_TOR)&0xFF) << PMP2_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[39:32] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RW enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP4_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[47:40] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP5_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare upper address of region2 -#define PMPADDRESS2 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare lower address of region3 -#define PMPADDRESS3 RAM_LOCATION_FOR_TEST -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region3 -#define PMPADDRESS4 rvtest_code_end -// PMPADDRESS5 = value to be loaded pmpaddr5 to declare upper address of region4 -#define PMPADDRESS5 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x8000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION => PMP region under test. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and rvtest_code_end into pmpaddr2. Then a PMP region is configure from pmpaddr2(RETURN_INSTRUCTION) to pmpaddr1(TEST_FOR_EXECUTION) into TOR mode by setting pmpcfg0[23:16]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr4 and RAM_LOCATION_FOR_TEST into pmpaddr3. configure pmpaddr4(RAM_LOCATION_FOR_TEST) to pmpaddr5(rvtest_code_end) into TOR mode by setting pmpcfg1[15:8]=PMPREGION3 - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr4(rvtest_code_end) to pmpaddr5(PMP_region_High) into TOR mode by setting pmpcfg1[15:8]=PMPREGION4. This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - LA(x4, PMPADDRESS5) // Value to be stored in pmpaddr5 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr5, x4 // Updated pmpaddr5 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RW-priority-level-2..S b/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RW-priority-level-2..S deleted file mode 100644 index 6b200139c..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RW-priority-level-2..S +++ /dev/null @@ -1,218 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-rw-level-2.S -// Tests the priority by assigning only R,W permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_rw_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R,W enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_L|PMP_TOR)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS2 = value to be loaded pmpaddr0 to declare lower address of Region-3 -#define PMPADDRESS0 TEST_FOR_EXECUTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 1*(XLEN/32),4,NOP //Single - -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION - -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RW-priority.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RW-priority.S deleted file mode 100644 index 25d443d88..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RW-priority.S +++ /dev/null @@ -1,195 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-rw.S -// Tests the priority by assigning only rw permissions to the high priority while R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_rw) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_W|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr3 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RW.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RW.S deleted file mode 100644 index f0ac5ea43..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RW.S +++ /dev/null @@ -1,224 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-tor-RW.S -// PMP Test in TOR address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -*/ -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_rw) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP4_CFG_SHIFT 32 -#define PMP5_CFG_SHIFT 40 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[23:16] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in TOR Mode with X enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_W|PMP_L|PMP_TOR)&0xFF) << PMP2_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[39:32] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RW enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP4_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[47:40] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP5_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare upper address of region2 -#define PMPADDRESS2 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare lower address of region3 -#define PMPADDRESS3 RAM_LOCATION_FOR_TEST -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region3 -#define PMPADDRESS4 rvtest_code_end -// PMPADDRESS5 = value to be loaded pmpaddr5 to declare upper address of region4 -#define PMPADDRESS5 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x8000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION => PMP region under test. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and rvtest_code_end into pmpaddr2. Then a PMP region is configure from pmpaddr2(RETURN_INSTRUCTION) to pmpaddr1(TEST_FOR_EXECUTION) into TOR mode by setting pmpcfg0[23:16]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr4 and RAM_LOCATION_FOR_TEST into pmpaddr3. configure pmpaddr4(RAM_LOCATION_FOR_TEST) to pmpaddr5(rvtest_code_end) into TOR mode by setting pmpcfg1[15:8]=PMPREGION3 - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr4(rvtest_code_end) to pmpaddr5(PMP_region_High) into TOR mode by setting pmpcfg1[15:8]=PMPREGION4. This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - LA(x4, PMPADDRESS5) // Value to be stored in pmpaddr5 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr5, x4 // Updated pmpaddr5 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RWX-priority-level-2.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RWX-priority-level-2.S deleted file mode 100644 index c02caf8dc..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RWX-priority-level-2.S +++ /dev/null @@ -1,217 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-rwx-level-2.S -// Tests the priority by assigning only R,W,X permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_rwx_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R,W enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS2 = value to be loaded pmpaddr0 to declare lower address of Region-3 -#define PMPADDRESS0 TEST_FOR_EXECUTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 1*(XLEN/32),4,NOP //Single - -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION - -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RWX.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RWX.S deleted file mode 100644 index a105928f7..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RWX.S +++ /dev/null @@ -1,224 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-tor-RWX.S -// PMP Test in TOR address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -*/ -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_rwx) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP4_CFG_SHIFT 32 -#define PMP5_CFG_SHIFT 40 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[23:16] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in TOR Mode with RWX enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP2_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[39:32] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RW enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP4_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg1[47:40] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP5_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare upper address of region2 -#define PMPADDRESS2 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare lower address of region3 -#define PMPADDRESS3 RAM_LOCATION_FOR_TEST -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region3 -#define PMPADDRESS4 rvtest_code_end -// PMPADDRESS5 = value to be loaded pmpaddr5 to declare upper address of region4 -#define PMPADDRESS5 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x8000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION => PMP region under test. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and rvtest_code_end into pmpaddr2. Then a PMP region is configure from pmpaddr2(RETURN_INSTRUCTION) to pmpaddr1(TEST_FOR_EXECUTION) into TOR mode by setting pmpcfg0[23:16]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr4 and RAM_LOCATION_FOR_TEST into pmpaddr3. configure pmpaddr4(RAM_LOCATION_FOR_TEST) to pmpaddr5(rvtest_code_end) into TOR mode by setting pmpcfg1[15:8]=PMPREGION3 - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr4(rvtest_code_end) to pmpaddr5(PMP_region_High) into TOR mode by setting pmpcfg1[15:8]=PMPREGION4. This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - LA(x4, PMPADDRESS5) // Value to be stored in pmpaddr5 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr5, x4 // Updated pmpaddr5 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RX-priority-level-2.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RX-priority-level-2.S deleted file mode 100644 index e664cd296..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RX-priority-level-2.S +++ /dev/null @@ -1,218 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-rx-level-2.S -// Tests the priority by assigning only R, X permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_rx_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R,W enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_R|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS2 = value to be loaded pmpaddr0 to declare lower address of Region-3 -#define PMPADDRESS0 TEST_FOR_EXECUTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 1*(XLEN/32),4,NOP //Single - -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION - -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RX-priority.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RX-priority.S deleted file mode 100644 index fa13e8f34..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RX-priority.S +++ /dev/null @@ -1,195 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-rx.S -// Tests the priority by assigning only rx permissions to the high priority while R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_rx) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr3 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RX.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RX.S deleted file mode 100644 index 59c30a5d5..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-RX.S +++ /dev/null @@ -1,224 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-tor-RX.S -// PMP Test in TOR address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -*/ -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_rx) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP4_CFG_SHIFT 32 -#define PMP5_CFG_SHIFT 40 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[23:16] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in TOR Mode with RX enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_R|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP2_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[39:32] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RW enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP4_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[47:40] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP5_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare upper address of region2 -#define PMPADDRESS2 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare lower address of region3 -#define PMPADDRESS3 RAM_LOCATION_FOR_TEST -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region3 -#define PMPADDRESS4 rvtest_code_end -// PMPADDRESS5 = value to be loaded pmpaddr5 to declare upper address of region4 -#define PMPADDRESS5 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x8000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION => PMP region under test. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and rvtest_code_end into pmpaddr2. Then a PMP region is configure from pmpaddr2(RETURN_INSTRUCTION) to pmpaddr1(TEST_FOR_EXECUTION) into TOR mode by setting pmpcfg0[23:16]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr4 and RAM_LOCATION_FOR_TEST into pmpaddr3. configure pmpaddr4(RAM_LOCATION_FOR_TEST) to pmpaddr5(rvtest_code_end) into TOR mode by setting pmpcfg1[15:8]=PMPREGION3 - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr4(rvtest_code_end) to pmpaddr5(PMP_region_High) into TOR mode by setting pmpcfg1[15:8]=PMPREGION4. This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - LA(x4, PMPADDRESS5) // Value to be stored in pmpaddr5 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr5, x4 // Updated pmpaddr5 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-X-priority-level-2.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-X-priority-level-2.S deleted file mode 100644 index 01e1f9a73..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-X-priority-level-2.S +++ /dev/null @@ -1,218 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-x-level-2.S -// Tests the priority by assigning only X permissions to the highest priority while no permissions to high priority region and R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_x_level_2) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with nothing enabled -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[15:8] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R,W enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION3 ((((PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP1_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION -// PMPADDRESS2 = value to be loaded pmpaddr0 to declare lower address of Region-3 -#define PMPADDRESS0 TEST_FOR_EXECUTION -// PMPADDRESS3 = value to be loaded pmpaddr1 to declare upper address of Region-3 -#define PMPADDRESS1 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap - LI(x4, PMPREGION3) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 1*(XLEN/32),4,NOP //Single - -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION - -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-X-priority.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-X-priority.S deleted file mode 100644 index 1ebf503bb..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-X-priority.S +++ /dev/null @@ -1,195 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-TOR-priority-x.S -// Tests the priority by assigning only X permissions to the high priority while R-W-X to low priority region -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf -*/ - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_priority_x) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP7_CFG_SHIFT 56 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg2 [63:56] value to configure address 0->PMP_region_High in TOR Mode with RWX enabled. This is the low priority region -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP7_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[31:24] value to configure address (RAM_LOCATION_FOR_TEST)->(RETURN_INSTRUCTION). This is the high priority region -// in TOR Mode with R enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP3_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -// PMPADDRESS14 = value to be loaded pmpaddr14 to declare lower address of Region-1 -#define PMPADDRESS14 0x80000000 // value to be loaded pmpaddr14 to declare region1 -// PMPADDRESS15 = value to be loaded pmpaddr15 to declare upper address of Region-1 -#define PMPADDRESS15 PMP_region_High -// PMPADDRESS2 = value to be loaded pmpaddr3 to declare lower address of Region-2 -#define PMPADDRESS2 RAM_LOCATION_FOR_TEST -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare upper address of Region-2 -#define PMPADDRESS3 RETURN_INSTRUCTION - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration - - /* Assigning addresses to PMP address registers */ - LI(x4, PMPADDRESS14) // Value to be stored in pmpaddr14 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr14, x4 // Updated pmpaddr14 - nop // Added nop in case of trap - LA(x4, PMPADDRESS15) // Value to be stored in pmpaddr15 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr15, x4 // Updated pmpaddr15 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1) - // Value to be stored in pmpcfg register - csrs pmpcfg2, x4 // Updated pmpcfg2 - nop // Added nop in case of trap - LI(x4, PMPREGION2) - // Value to be stored in pmpcfg1 register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 0*(XLEN/32),4,NOP -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-X.S b/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-X.S deleted file mode 100644 index 2cf079988..000000000 --- a/riscv-test-suite/rv64i_m/pmp64/pmp64-TOR-X.S +++ /dev/null @@ -1,224 +0,0 @@ -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This test belongs to the test plan for RISC-V Privilege Arch Compliance developed by 10xEngineers -// which can be found here: https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit?usp=sharing -/* Test Name: pmp-tor-X.S -// PMP Test in TOR address matching mode -// Description: -=> Foreach mode in MPP (including M), for Load/store instruction, perform the instruction referencing an address where the associated pmpcfg.W=1 and observe an access fault or not. -=> Foreach mode, perform instruction fetches to an address where the associated pmpcfg.X=0 and observe an access fault or not. -=> Foreach mode in MPP (including M), Perform the instruction referencing an address where the associated pmpcfg.R=1 and observe an access fault or not. Do the same for stores where pmpcfg.R=1 and pmpcfg.W=1 to make sure that the R bit only affects loads while W bit only affect store. -=> Do the same for loads where pmpcfg.R=1 and pmpcfg.W=0 to make sure that the W bit only affects stores and AMOs. -*/ -// coverpoint definitions are given in coverage/pmp32_translated_coverpoints.cgf or coverage/pmp32_coverpoint_def_format.cgf - -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64I_Zicsr") -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True",PMP_TOR_x) -RVTEST_SIGBASE( x13,signature_x13_1) - - .attribute unaligned_access, 0 - .attribute stack_align, 16 - .align 2 - .option norvc -#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) -#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) -/* Define PMP Configuration Fields */ -#define PMP0_CFG_SHIFT 0 -#define PMP1_CFG_SHIFT 8 -#define PMP2_CFG_SHIFT 16 -#define PMP3_CFG_SHIFT 24 -#define PMP4_CFG_SHIFT 32 -#define PMP5_CFG_SHIFT 40 -#define NOP 0x13 -.macro VERIFICATION_RWX ADDRESS - LA(a5, \ADDRESS) // Fetch the address to be checked - ld a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled) - nop - nop - /* WRITING new value to memory region - TRAP if the WRITability is blocked */ - LI(a4, NOP) // Load the new value (NOP Instruction ID) - sd a4,0(a5) // Store the new value (NOT TRAP => W enabled) - nop - nop - ld a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - nop -jal \ADDRESS // Test for execution, an instruction is placed at this address -.endm - -main: -//////////////////////// INITIAL VALUES //////////////////////////////// - LI(a5, -1) // SEtting up All locked bits (including everyother non-zero bit, which is redundent for this test) - LI(x5, 100) // A rondom number, to check if pmp regs get update after lock bit enable - // Loop to SET ALL pmpcfg REGs to zero - .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 - .rept 2 // START OF LOOP - - csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) - .set pmpcfgi, pmpcfgi+2 // increment variable to next pmpcfg reg - .endr // END OF LOOP BODY - // Loop to SET ALL pmpaddr REGs to zero - .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 - .rept 16 // START OF LOOP - csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) - .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg - .endr // END OF LOOP BODY - -// pmpcfg0 [7:0] value to configure address 0->RAM_LOCATION_FOR_TEST in TOR Mode with RWX enabled -#define PMPREGION1 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP0_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[23:16] value to configure address (TEST_FOR_EXECUTION)->(RETURN_INSTRUCTION) -// in TOR Mode with RX enabled =========> THIS IS OUR REGION UNDER OBSERVATION. -// THIS REGION CONSISTS OF ONLY ONE INSTRUCTION -#define PMPREGION2 ((((PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP2_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[39:32] value to configure address (RAM_LOCATION_FOR_TEST)->(rvtest_code_end) -// in TOR Mode with RW enabled -// ALSO NOTE THAT PMPREGION2 IS INSIDE THIS REGION, so this test will also check the priority order of PMP regions -#define PMPREGION3 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP4_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// pmpcfg0[47:40] value to configure address (rvtest_code_end)->(PMP_region_High) -// in TOR Mode with RWX enabled -#define PMPREGION4 ((((PMP_R|PMP_W|PMP_X|PMP_L|PMP_TOR)&0xFF) << PMP5_CFG_SHIFT)) -// ------------------------------------------------------------------------------------------------ -// MACROS TO DECLARE THE VALUES TO BE STORED IN PMPADDR registers -#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region1 -// PMPADDRESS1 = value to be loaded pmpaddr1 to declare lower address of region2 -#define PMPADDRESS1 TEST_FOR_EXECUTION -// PMPADDRESS2 = value to be loaded pmpaddr2 to declare upper address of region2 -#define PMPADDRESS2 RETURN_INSTRUCTION -// PMPADDRESS3 = value to be loaded pmpaddr3 to declare lower address of region3 -#define PMPADDRESS3 RAM_LOCATION_FOR_TEST -// PMPADDRESS4 = value to be loaded pmpaddr4 to declare upper address of region3 -#define PMPADDRESS4 rvtest_code_end -// PMPADDRESS5 = value to be loaded pmpaddr5 to declare upper address of region4 -#define PMPADDRESS5 PMP_region_High - - /* SET UP DATA IN THE MEMORY */ - csrw satp, x0 // Disable Address Translation -// PMP Configuration -/* PMP is configure in the following order: -1. Address 0x8000 0000 to Address RAM_LOCATION_FOR_TEST => PMP TOR Region with RWX enabled. This region is the part of the code memory containing our code. For this purpose, pmpaddr0 has been given the value of RAM_LOCATION_FOR_TEST to declare the region from 0->RAM_LOCATION_FOR_TEST into a single PMP region. - -2. Address TEST_FOR_EXECUTION to Address RETURN_INSTRUCTION => PMP region under test. This region has been declared by entering TEST_FOR_EXECUTION into pmpaddr1 and rvtest_code_end into pmpaddr2. Then a PMP region is configure from pmpaddr2(RETURN_INSTRUCTION) to pmpaddr1(TEST_FOR_EXECUTION) into TOR mode by setting pmpcfg0[23:16]=PMPREGION2 - -3. Address RAM_LOCATION_FOR_TEST to Address rvtest_code_end => PMP region under test. This region has been declared by entering rvtest_code_end into pmpaddr4 and RAM_LOCATION_FOR_TEST into pmpaddr3. configure pmpaddr4(RAM_LOCATION_FOR_TEST) to pmpaddr5(rvtest_code_end) into TOR mode by setting pmpcfg1[15:8]=PMPREGION3 - -4. Address rvtest_code_end to address PMP_region_High => PMP TOR Region with RWX enabled. This region is the part of the code memory containing trap handler, epilogs, and other important macro definitions. For this purpose, configure pmpaddr4(rvtest_code_end) to pmpaddr5(PMP_region_High) into TOR mode by setting pmpcfg1[15:8]=PMPREGION4. This PMP Region is mandatory to access signature area in S,U mode */ - /* Assigning addresses to PMP address registers */ - LA(x4, PMPADDRESS0) // Value to be stored in pmpaddr0 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr0, x4 // Updated pmpaddr0 - nop // Added nop in case of trap - LA(x4, PMPADDRESS1) // Value to be stored in pmpaddr1 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr1, x4 // Updated pmpaddr1 - nop // Added nop in case of trap - LA(x4, PMPADDRESS2) // Value to be stored in pmpaddr2 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr2, x4 // Updated pmpaddr2 - nop // Added nop in case of trap - LA(x4, PMPADDRESS3) // Value to be stored in pmpaddr3 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr3, x4 // Updated pmpaddr3 - nop // Added nop in case of trap - LA(x4, PMPADDRESS4) // Value to be stored in pmpaddr4 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr4, x4 // Updated pmpaddr4 - nop // Added nop in case of trap - LA(x4, PMPADDRESS5) // Value to be stored in pmpaddr5 - srl x4, x4, PMP_SHIFT // Shift right by 2 times - csrw pmpaddr5, x4 // Updated pmpaddr5 - nop // Added nop in case of trap - /* Decalring pmp configuration register */ - LI(x4, PMPREGION1 | PMPREGION2 | PMPREGION3 | PMPREGION4) - // Value to be stored in pmpcfg register - csrs pmpcfg0, x4 // Updated pmpcfg0 - nop // Added nop in case of trap -//////////// ALL PMP REGIONS DECLARED ////////////////////////////////////////////// - /* VERIFICATION in M-mode */ - VERIFICATION_RWX TEST_FOR_EXECUTION -// VERIFICATION IN S-Mode - RVTEST_GOTO_LOWER_MODE Smode // SWITCH TO S-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - -/////////////////// Switch back to M-mode //////////////////////////////////////////// - RVTEST_GOTO_MMODE - csrr a4, mstatus // VERIFICATION of M-mode - nop // Added nop in case of trap -// VERIFICATION IN U-Mode - RVTEST_GOTO_LOWER_MODE Umode // SWITCH TO U-mode - VERIFICATION_RWX TEST_FOR_EXECUTION - j exit - -RAM_LOCATION_FOR_TEST: - .fill 3*(XLEN/32),4,0x12345678 -TEST_FOR_EXECUTION: - addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION -RETURN_INSTRUCTION: - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - nop // Added nop in case of trap - jr ra -// AN instruction to bring back PC to the address where TEST_FOR_EXECUTION was called to check for execution. -exit: -#endif - # --------------------------------------------------------------------------------------------- - # HALT -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 4 - -rvtest_data: -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -.word 0xbabecafe -RVTEST_DATA_END - - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; -signature_x13_1: - .fill 32*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -tsig_begin_canary: -CANARY; -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -tsig_end_canary: -CANARY; - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -PMP_region_High: -RVMODEL_DATA_END \ No newline at end of file