diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5bc115f8d..a5bd6dbfa 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,8 +1,14 @@
 # CHANGELOG
 
-## [3.8.7] -- 2024-01-12
+## [3.8.9] -- 2024-01-12
 - Fixed Check ISA fields to include 32/64 in Zicond tests.  Note that the riscv-ctg CGFs have not been updated.
 
+## [3.8.8] -- 2024-01-04
+- Fixed macros to allow assembling tests with LLVM.
+
+## [3.8.7] -- 2024-01-02
+- Update satp initialization macro
+
 ## [3.8.6] -- 2023-12-24
 - Fixed check ISA fields to include 32/64 in Zca and CMO tests.  Note that the riscv-ctg CGFs have not been updated.
 - Fixed check ISA fields in rv32e_m/B/src/ror-01 and rori-01 that listed I instead of E. Again, CGF has not been updated.
diff --git a/riscv-test-suite/env/arch_test.h b/riscv-test-suite/env/arch_test.h
index 2eb0ab436..fee1e748b 100644
--- a/riscv-test-suite/env/arch_test.h
+++ b/riscv-test-suite/env/arch_test.h
@@ -574,13 +574,13 @@
 /******************************************************************************/
 
  .macro XCSR_RENAME __MODE__    // enable CSR names to be parameterized, V,S merged
-  .ifc   \__MODE__, M
+  .ifc   \__MODE__ , M
        _XCSR_RENAME_M
   .endif
-  .ifc   \__MODE__, S
+  .ifc   \__MODE__ , S
        _XCSR_RENAME_S
   .endif
-  .ifc  \__MODE__,  V
+  .ifc  \__MODE__ ,  V
        _XCSR_RENAME_S
   .endif
 .endm
@@ -593,13 +593,13 @@
 /******************************************************************************/
 
  .macro XCSR_VRENAME __MODE__   // enable CSR names to be parameterized, V,S separate 
-  .ifc   \__MODE__, M
+  .ifc   \__MODE__ , M
        _XCSR_RENAME_M
   .endif
-  .ifc   \__MODE__, S
+  .ifc   \__MODE__ , S
        _XCSR_RENAME_S
   .endif
-  .ifc  \__MODE__,  V
+  .ifc  \__MODE__ ,  V
        _XCSR_RENAME_V
   .endif
  .endm
@@ -979,10 +979,10 @@ init_\__MODE__\()scratch:
 //----------------------------------------------------------------------
 init_\__MODE__\()edeleg:
         li      T2, 0                   // save and clear edeleg so we can exit to Mmode
-.if (\__MODE__\() == V)
+.ifc \__MODE__ , V
         csrrw   T2, CSR_VEDELEG, T2     // special case: VS EDELEG available from Vmode
 .else
-  .if (\__MODE__\() == M)
+  .ifc \__MODE__ , M
     #ifdef rvtest_strap_routine
         csrrw   T2, CSR_XEDELEG, T2     // this handles M  mode save, but only if Smode exists
     #endif
@@ -996,6 +996,13 @@ init_\__MODE__\()edeleg:
 init_\__MODE__\()satp:
 .ifnc \__MODE__ , M                      // if S or VS mode **FIXME: fixed offset frm trapreg_sv?
         LA(     T4, rvtest_\__MODE__\()root_pg_tbl)     // rplc xsatp w/ identity-mapped pg table 
+        srli T4, T4, 12
+      #if (XLEN==32)
+        LI(T3, SATP32_MODE)
+      #else
+        LI(T3, (SATP64_MODE) & (SATP_MODE_SV39 << 60))
+      #endif
+        or      T4, T4, T3
         csrrw   T4, CSR_XSATP, T4
         SREG    T4, xsatp_sv_off(T1)
 .endif