diff --git a/riscv-test-suite/env/encoding.h b/riscv-test-suite/env/encoding.h index 1dbe6853a..1e50c6de8 100755 --- a/riscv-test-suite/env/encoding.h +++ b/riscv-test-suite/env/encoding.h @@ -865,6 +865,7 @@ #define CSR_PMPADDR13 0x3bd #define CSR_PMPADDR14 0x3be #define CSR_PMPADDR15 0x3bf +#define CSR_MSECCFG 0x747 #define CSR_TSELECT 0x7a0 #define CSR_TDATA1 0x7a1 #define CSR_TDATA2 0x7a2 @@ -1361,6 +1362,7 @@ DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(mseccfg, CSR_MSECCFG) DECLARE_CSR(tselect, CSR_TSELECT) DECLARE_CSR(tdata1, CSR_TDATA1) DECLARE_CSR(tdata2, CSR_TDATA2) diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_01.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_01.S new file mode 100644 index 000000000..40fa21307 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_01.S @@ -0,0 +1,63 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// This assembly file tests the reset value of mseccfg csr +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_01) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + + csrr x2,mseccfg //Read the value of mseccfg + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_02.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_02.S new file mode 100644 index 000000000..4616625cb --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_02.S @@ -0,0 +1,72 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// This assembly file tests the permissions of csrw, csrr, csrs and csrc in M mode +// It should allow all above instruction to execute because mseccfg is a machine mode csr and we are accessing it in M mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_02) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + + csrw mseccfg,zero //write mseccfg to know whether csrw is permitted + csrr x2,mseccfg //Read the value of mseccfg + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + + csrs mseccfg,zero //set mseccfg to know whether csrs is permitted + csrr x2,mseccfg //Read the value of mseccfg + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + + csrc mseccfg,zero //clear mseccfg to know whether csrc is permitted + csrr x2,mseccfg //Read the value of mseccfg + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_03.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_03.S new file mode 100644 index 000000000..b1127cf57 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_03.S @@ -0,0 +1,139 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// This assembly file tests the permissions of csrw, csrr, csrs and csrc in S mode +// It should generate trap_illegal_instruction because mseccfg is a machine mode csr +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_03) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define EntireMemorySpace 0xFFFFFFFF + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------------ + +{Region 0}-------->[Entire memory sapce] + [With Read,Write and execute permissions enable for that region and Lock is clear] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 EntireMemorySpace // value to be loaded in pmpaddr0 to declare region0 +#define PMPREGION0 (((PMP_R | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 0 + +//------------------ Configuring 1 region as mentioned above-------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x2, PMPADDRESS0) // Starting address 0 upto whole memory is configured + srl x2, x2, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x2 // Updated pmpaddr0 to define PMP region consisting + csrr x3, pmpaddr0 // Verify its value by reading back + RVTEST_SIGUPD(x13,x3) // Update the signature + + LI(x4, PMPREGION0 ) //Permission for Region 0 is loaded + csrw pmpcfg0, x4 + csrr x5,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x5) //Update the signature + + //---------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + + //-------------------------In S mode now--------------------------------------------- + + nop + csrw mseccfg,zero //write mseccfg to know whether csrw is permitted(should trap bcz it is M mode csr) + csrr x3,mseccfg //Read the value of mseccfg(should trap bcz it is M mode csr) + RVTEST_SIGUPD(x13,x3) //Update the signature + + csrs mseccfg,zero //set mseccfg to know whether csrs is permitted(should trap bcz it is M mode csr) + csrr x3,mseccfg //Read the value of mseccfg(should trap bcz it is M mode csr) + RVTEST_SIGUPD(x13,x3) //Update the signature + + csrc mseccfg,zero //clear mseccfg to know whether csrc is permitted(should trap bcz it is M mode csr) + csrr x3,mseccfg //Read the value of mseccfg(should trap bcz it is M mode csr) + RVTEST_SIGUPD(x13,x3) //Update the signature + + nop + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions (IN later files) + .fill 3*(XLEN/32),4,0x12345678 + + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_04.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_04.S new file mode 100644 index 000000000..3be0cf981 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_04.S @@ -0,0 +1,139 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// This assembly file tests the permissions of csrw, csrr, csrs and csrc in U mode +// It should generate trap_illegal_instruction because mseccfg is a machine mode csr +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_04) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define EntireMemorySpace 0xFFFFFFFF + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- `````````````````````````````````````````````````````````````` ``````````````````````````````````````````````````````````````````````````````` + +{Region 0}-------->[Entire memory sapce] + [With Read,Write and execute permissions enable for that region and Lock is clear] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 EntireMemorySpace // value to be loaded in pmpaddr0 to declare region0 +#define PMPREGION0 (((PMP_R | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 0 + +//------------------ Configuring 1 region as mentioned above-------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x2, PMPADDRESS0) // Starting address 0 upto whole memory is configured + srl x2, x2, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x2 // Updated pmpaddr0 to define PMP region consisting + csrr x3, pmpaddr0 // Verify its value by reading back + RVTEST_SIGUPD(x13,x3) // Update the signature + + LI(x4, PMPREGION0 ) //Permission for Region 0 is loaded + csrw pmpcfg0, x4 + csrr x5,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x5) //Update the signature + + //---------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + + //-------------------------In U mode now--------------------------------------------- + + nop + csrw mseccfg,zero //write mseccfg to know whether csrw is permitted(should trap bcz it is M mode csr) + csrr x3,mseccfg //Read the value of mseccfg(should trap bcz it is M mode csr) + RVTEST_SIGUPD(x13,x3) //Update the signature + + csrs mseccfg,zero //set mseccfg to know whether csrs is permitted(should trap bcz it is M mode csr) + csrr x3,mseccfg //Read the value of mseccfg(should trap bcz it is M mode csr) + RVTEST_SIGUPD(x13,x3) //Update the signature + + csrc mseccfg,zero //clear mseccfg to know whether csrc is permitted(should trap bcz it is M mode csr) + csrr x3,mseccfg //Read the value of mseccfg(should trap bcz it is M mode csr) + RVTEST_SIGUPD(x13,x3) //Update the signature + + nop + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions (IN later files) + .fill 3*(XLEN/32),4,0x12345678 + + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_05.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_05.S new file mode 100644 index 000000000..884089190 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_05.S @@ -0,0 +1,71 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// This assembly file tests when we write to the reserved fields of mseccfg it should not write there +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_05) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + + LI(x2,setRLB | setMMWP | setMML) //Set immidiate as all legal values of mseccfg + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + not x2,x2 //set 1's to all other fields except first 3 valid fields of mseccfg + csrw mseccfg,x2 //write mseccfg to know whether fields are written + csrr x3,mseccfg //Read the value of mseccfg to verify whether fields are written(It should remain zero bcz we have written to reserve fields) + RVTEST_SIGUPD(x13,x3) //Update the signature with the csr value + + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_06.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_06.S new file mode 100644 index 000000000..38309d151 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_06.S @@ -0,0 +1,136 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// This assembly file tests if we set (mseccfg.RLB=0 and at least one pmpcfg.L=1) then mseccfg.RLB canot be written\modified +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_06) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define EntireMemorySpace 0xFFFFFFFF + + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + csrw mseccfg, zero //Writing 0 to mseccfg and in specific mseccfg.RLB is cleared + csrr x2,mseccfg //Verify its value by reading back + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + +/*-------------------------------Descritption of all regions used------------------------------------------------- ```` + +{Region 0}-------->[Entire memory sapce] + [With Read,Write and execute permissions enable for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 EntireMemorySpace // value to be loaded in pmpaddr0 to declare region0 +#define PMPREGION0 (((PMP_L | PMP_R | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 0 + +//------------------ Configuring 1 region as mentioned above-------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x2, PMPADDRESS0) // Starting address 0 upto whole memory is configured + srl x2, x2, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x2 // Updated pmpaddr0 to define PMP region consisting + csrr x3, pmpaddr0 // Verify its value by reading back + RVTEST_SIGUPD(x13,x3) // Update the signature + + LI(x4, PMPREGION0 ) //Permission for Region 0 is loaded + csrw pmpcfg0, x4 + csrr x5,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x5) //Update the signature + + //---------------------------------------------------------------------------------- + + csrr x6, mseccfg //Verify the value to double check mseccfg is zero + RVTEST_SIGUPD(x13,x6) //Update the signature + LI(x7,setRLB) //load x7 with value to set mseccfg.RLB which is at bit 3 in mseccfg + csrw mseccfg, x7 //Setting mseccfg.RLB + csrr x8, mseccfg //Read back the value of mseccfg to verify RLB is still unset(If it is, then test is passed) + RVTEST_SIGUPD(x13,x8) //Update the signature + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions (IN later files) + .fill 3*(XLEN/32),4,0x12345678 + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_07.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_07.S new file mode 100644 index 000000000..6ef8312d1 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_07.S @@ -0,0 +1,136 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// This assembly file tests if we set (mseccfg.RLB=0 and pmpcfg.L=0) then mseccfg.RLB can be written\modified +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_07) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define EntireMemorySpace 0xFFFFFFFF + + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + csrw mseccfg, zero //Writing 0 to mseccfg and in specific mseccfg.RLB is cleared + csrr x2,mseccfg //Verify its value by reading back + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[Entire memory sapce] + [With Read,Write and execute permissions enable for that region and Lock is clear] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 EntireMemorySpace // value to be loaded in pmpaddr0 to declare region0 +#define PMPREGION0 ((( PMP_R | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 0 + +//------------------ Configuring 1 region as mentioned above-------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x2, PMPADDRESS0) // Starting address 0 upto whole memory is configured + srl x2, x2, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x2 // Updated pmpaddr0 to define PMP region consisting + csrr x3, pmpaddr0 // Verify its value by reading back + RVTEST_SIGUPD(x13,x3) // Update the signature + + LI(x4, PMPREGION0 ) //Permission for Region 0 is loaded + csrw pmpcfg0, x4 + csrr x5,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x5) //Update the signature + + //---------------------------------------------------------------------------------- + + csrr x6, mseccfg //Verify the value to double check mseccfg is zero + RVTEST_SIGUPD(x13,x6) //Update the signature + LI(x7,setRLB) //load x7 with value to set mseccfg.RLB which is at bit 3 in mseccfg + csrw mseccfg, x7 //Setting mseccfg.RLB + csrr x8, mseccfg //Read back the value of mseccfg to verify RLB is set now(If it is, then test is passed) + RVTEST_SIGUPD(x13,x8) //Update the signature + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions (IN later files) + .fill 3*(XLEN/32),4,0x12345678 + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_08.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_08.S new file mode 100644 index 000000000..b334f0c06 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_08.S @@ -0,0 +1,201 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if we set (mseccfg.RLB=1 and pmpcfg.L=1) then pmp rules may be removed/modified and +//pmp entries may be edited + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_08) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +#define clear_cf_of_Region0 0x00FFFFFF + +//------------------------------This macro is used for testing the RWX for region 3(region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) + csrw mseccfg, x2 //Setting mseccfg.RLB + csrr x2,mseccfg //Verify its value by reading back + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read,Write and execute permissions not enabled for that region and Lock is set] [Old configuration] + [With Read,Write and execute permissions enabled for that region and Lock is set] [New configuration] + +{Region 1}-------->[Entire memory sapce] + [With Read,Write and execute permissions enable for that region and Lock is clear] + +------------------------------------------------------------------------------------------------------------------*/ +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare start of region0 +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded in pmpaddr1 to declare end of region0 +#define PMPREGION0 (((PMP_L |PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 +#define NEW_PMPREGION0 (((PMP_L | PMP_R | PMP_W |PMP_X |PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) //New Configuration for region 0 which will be used later to check our test + + +#define PMPADDRESS2 Start // Value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 EntireMemorySpace // Value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_R | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + + +//------------------ Configuring 2 regions as mentioned above-------------------------------------------------- + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for region 0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion 0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address Start is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address EntireMemorySpace is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region0 and Region 1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + LI(x2,test_value) + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(CALLING from here will give RWX trap bcz permission is not to do RWX) + + LI(x8,clear_cf_of_Region0) + RVTEST_SIGUPD(x13,x8) //Update the signature + csrc pmpcfg0, x8 //Clear the configuration of region0 + csrr x9,pmpcfg0 //Read to confirm configuration is cleared properly + RVTEST_SIGUPD(x13,x9) //Update the signature + + LI(x9,NEW_PMPREGION0) + csrs pmpcfg0, x9 //Update the configuration to give RWX permission (If it is done then our test is passing as we are able to change the configuration of region3 despite being locked using RLB set) + csrr x9,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x9) //Update the signature + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Now no RWX trap) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_09.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_09.S new file mode 100644 index 000000000..1a6e7f36e --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_09.S @@ -0,0 +1,134 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +//This assembly file tests if we set mseccfg.MMWP=1 once, then mseccfg.MMWP cannot be written\modified +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_09) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define clear_mseccfg 0xFFFFFFFF +#define EntireMemorySpace 0xFFFFFFFF + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------------ + +{Region 0}-------->[Entire memory sapce] + [With Read,Write and execute permissions enable for that region and Lock is clear] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 EntireMemorySpace // value to be loaded pmpaddr0 to declare region0 +#define PMPREGION0 (((PMP_R | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 0 + +//------------------ Configuring 1 region as mentioned above-------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) // Starting address 0 upto whole memory is configured + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 // Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 // Verify its value by reading back + RVTEST_SIGUPD(x13,x5) // Update the signature + + LI(x6, PMPREGION0 ) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + +//---------------------------------------------------------------------------------------------- + + LI(x2,setMMWP) //Load a value to set MMWP bit in mseccfg + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + + csrw mseccfg,x2 //Write mseccfg with MMWP bit set + csrr x3,mseccfg //Read back to confirm its value + RVTEST_SIGUPD(x13,x3) //Update the signature with the csr value + + csrw mseccfg,zero //write zero to mseccfg csr + csrr x3,mseccfg //Read back to confirm its value(If it remains same, it signifies test is passing else if it is changed or modified then test is failing) + RVTEST_SIGUPD(x13,x3) //Update the signature with the csr value + + LI(x2,clear_mseccfg) + RVTEST_SIGUPD(x13,x2) //Update the signature + csrc mseccfg,x2 //Try to clear mseccfg + csrr x3,mseccfg //Read back to confirm its value(If it remains same, it signifies test is passing else if it is changed or modified then test is failing) + RVTEST_SIGUPD(x13,x3) //Update the signature with the csr value + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_10.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_10.S new file mode 100644 index 000000000..b0144c640 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_10.S @@ -0,0 +1,178 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests "If mseccfg.MMWP=1 then default PMP policy for M-mode when accessing memory regions that don’t +//have a matching PMP rule, to denied instead of ignored." + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_10) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region 3(region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[0 till RAM_LOCATION_FOR_TEST] + [With Read,Write and execute permissions enabled for that region and Lock is clear] + +{Region 1}-------->[RETURN_INSTRUCTION till PMP_region_High] + [With Read,Write and execute permissions enable for that region and Lock is clear] + +------------------------------------------------------------------------------------------------------------------*/ +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region0 +#define PMPREGION0 (((PMP_R | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region1 start +#define PMPADDRESS2 PMP_region_High // value to be loaded pmpaddr2 to declare region1 end +#define PMPREGION1 (((PMP_R | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP2_CFG_SHIFT) // Configuration for region 1 + +//------------------ Configuring 2 regions as mentioned above and setting MMWP-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address 0 upto RAM_LOCATION_FOR_TEST is configured + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Starting address RETURN_INSTRUCTION is loaded for reigion 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + nop //Added nop in case of trap + RVTEST_SIGUPD(x13,x5) //Update the signature + nop //Added nop in case of trap + + LA(x4, PMPADDRESS2) //Ending address PMP_region_High is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + nop //Added nop in case of trap + RVTEST_SIGUPD(x13,x5) //Update the signature + nop //Added nop in case of trap + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region0 and and Region1 is loaded + csrw pmpcfg0, x6 //Write the configuration in correspondind CSR + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMMWP) + csrw mseccfg, x2 //Setting mseccfg.MMWP + csrr x2,mseccfg //Verify its value by reading back + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + //--------------------------------------------------------------------------------------------------------- + + + LI(x2,test_value) + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(CALLING from here will give RWX trap bcz region is not configured with mseccfg.MMWP set) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_11_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_11_SMode.S new file mode 100644 index 000000000..688d6201b --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_11_SMode.S @@ -0,0 +1,228 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests If (mseccfg.MMWP=0 and mseccfg.MML=1) then PMP policy for S/U-mode when accessing +//memory regions that don’t have a matching PMP rule, to denied. + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_11_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[0 till RAM_LOCATION_FOR_TEST] + [With Write and execute permissions enabled for that region and Lock is set] [Before MML set] + [With Execute permissions enabled for S/U mode for that region and Lock is set] [After MML set] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode and Execute for S/U for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for S/U mode for that region and Lock is clear] + +{Region 3}-------->[RETURN_INSTRUCTION till PMP_region_High] + [With Read and Execute permissions enabled for M mode and Execute for S/U for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region0 +#define PMPREGION0 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 0 +#define NEW_PMPREGION0 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 0 + + +#define PMPADDRESS1 exit_cleanup // value to be loaded pmpaddr1 to declare region1 start +#define PMPADDRESS2 tohost // value to be loaded pmpaddr2 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP2_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS3 Mclr_Msw_int // value to be loaded pmpaddr3 to declare region2 start +#define PMPADDRESS4 PMP_region_High // value to be loaded pmpaddr4 to declare region2 end +#define PMPREGION2 (((PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS5 RETURN_INSTRUCTION // value to be loaded pmpaddr5 to declare region3 start +# define PMPADDRESS6 PMP_region_High // value to be loaded pmpaddr6 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP2_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions as mentioned above-------------------------------------------------- + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address 0 upto RAM_LOCATION_FOR_TEST is configured + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Starting address exit_cleanup is loaded for reigion 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Starting address RETURN_INSTRUCTION is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Ending address PMP_region_High is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrs mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + + LI(x9,NEW_PMPREGION0| PMPREGION1) + csrw pmpcfg0, x9 //Permission for Region0 and Region1 is loaded + csrr x2,pmpcfg0 + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + + LI(x9,PMPREGION3|PMPREGION2) //Permission for Region0 and Region1 is loaded + csrw pmpcfg1, x9 + csrr x2,pmpcfg1 + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + +//----------------------------------------------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + + LI(x2,test_value) + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST (will get RWX trap for S/U mode if region is not configured with MML set) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_11_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_11_UMode.S new file mode 100644 index 000000000..c8336ae21 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_11_UMode.S @@ -0,0 +1,228 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests If (mseccfg.MMWP=0 and mseccfg.MML=1) then PMP policy for S/U-mode when accessing +//memory regions that don’t have a matching PMP rule, to denied. + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_11_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[0 till RAM_LOCATION_FOR_TEST] + [With Write and execute permissions enabled for that region and Lock is set] [Before MML set] + [With Execute permissions enabled for S/U mode for that region and Lock is set] [After MML set] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode and Execute for S/U for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for S/U mode for that region and Lock is clear] + +{Region 3}-------->[RETURN_INSTRUCTION till PMP_region_High] + [With Read and Execute permissions enabled for M mode and Execute for S/U for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region0 +#define PMPREGION0 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 0 +#define NEW_PMPREGION0 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 0 + + +#define PMPADDRESS1 exit_cleanup // value to be loaded pmpaddr1 to declare region1 start +#define PMPADDRESS2 tohost // value to be loaded pmpaddr2 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP2_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS3 Mclr_Msw_int // value to be loaded pmpaddr3 to declare region2 start +#define PMPADDRESS4 PMP_region_High // value to be loaded pmpaddr4 to declare region2 end +#define PMPREGION2 (((PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS5 RETURN_INSTRUCTION // value to be loaded pmpaddr5 to declare region3 start +# define PMPADDRESS6 PMP_region_High // value to be loaded pmpaddr6 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP2_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions as mentioned above-------------------------------------------------- + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address 0 upto RAM_LOCATION_FOR_TEST is configured + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Starting address exit_cleanup is loaded for reigion 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Starting address RETURN_INSTRUCTION is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Ending address PMP_region_High is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrs mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + + LI(x9,NEW_PMPREGION0| PMPREGION1) + csrw pmpcfg0, x9 //Permission for Region0 and Region1 is loaded + csrr x2,pmpcfg0 + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + + LI(x9,PMPREGION3|PMPREGION2) //Permission for Region0 and Region1 is loaded + csrw pmpcfg1, x9 + csrr x2,pmpcfg1 + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + +//----------------------------------------------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + + LI(x2,test_value) + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST (will get RWX trap for S/U mode if region is not configured with MML set) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_12.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_12.S new file mode 100644 index 000000000..7c45c888a --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_12.S @@ -0,0 +1,231 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests If (mseccfg.MMWP=0 and mseccfg.MML=1) then PMP policy for M-mode when accessing +//memory regions that don’t have a matching PMP rule, for R/W, to ignore. + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_12) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS exitLabel + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \exitLabel // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[0 till RAM_LOCATION_FOR_TEST] + [With Write and execute permissions enabled for that region and Lock is set] [Before MML set] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] [After MML set] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[RETURN_INSTRUCTION till PMP_region_High] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region0 +#define PMPREGION0 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 0 + + +#define PMPADDRESS1 exit_cleanup // value to be loaded pmpaddr1 to declare region1 start +#define PMPADDRESS2 tohost // value to be loaded pmpaddr2 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP2_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS3 Mclr_Msw_int // value to be loaded pmpaddr3 to declare region1 start +#define PMPADDRESS4 PMP_region_High // value to be loaded pmpaddr4 to declare region1 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS5 RETURN_INSTRUCTION // value to be loaded pmpaddr5 to declare region2 start +# define PMPADDRESS6 PMP_region_High // value to be loaded pmpaddr6 to declare region2 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP2_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address 0 upto RAM_LOCATION_FOR_TEST is configured + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + nop //Added nop in case of trap + RVTEST_SIGUPD(x13,x5) //Update the signature + nop //Added nop in case of trap + + LA(x4, PMPADDRESS1) //Starting address exit_cleanup is loaded for reigion 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + nop //Added nop in case of trap + RVTEST_SIGUPD(x13,x5) //Update the signature + nop //Added nop in case of trap + + LA(x4, PMPADDRESS2) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + nop //Added nop in case of trap + RVTEST_SIGUPD(x13,x5) //Update the signature + nop //Added nop in case of trap + + LA(x4, PMPADDRESS3) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + nop //Added nop in case of trap + RVTEST_SIGUPD(x13,x5) //Update the signature + nop //Added nop in case of trap + + LA(x4, PMPADDRESS4) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + nop //Added nop in case of trap + RVTEST_SIGUPD(x13,x5) //Update the signature + nop //Added nop in case of trap + + LA(x4, PMPADDRESS5) //Starting address RETURN_INSTRUCTION is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + nop //Added nop in case of trap + RVTEST_SIGUPD(x13,x5) //Update the signature + nop + + LA(x4, PMPADDRESS6) //Ending address PMP_region_High is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + nop //Added nop in case of trap + RVTEST_SIGUPD(x13,x5) //Update the signature + nop + + + LA(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 and Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LA(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region2 and Region2 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + RVTEST_SIGUPD(x13,x2) //Update the signature + + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST exit //macro is called with address as RAM_LOCATION_FOR_TEST and exittlabel as exit (Read and write is permitted in M mode if region is not configured with MML set) + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_13.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_13.S new file mode 100644 index 000000000..6c8f15e77 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_13.S @@ -0,0 +1,220 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests If (mseccfg.MMWP=0 and mseccfg.MML=1) then PMP policy for M-mode when accessing +//memory regions that don’t have a matching PMP rule, for X, to denied. + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_13) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS exitLabel + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \exitLabel // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[0 till RAM_LOCATION_FOR_TEST] + [With Write and execute permissions enabled for that region and Lock is set] [Before MML set] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] [After MML set] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[RETURN_INSTRUCTION till PMP_region_High] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region0 +#define PMPREGION0 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 0 + + +#define PMPADDRESS1 exit_cleanup // value to be loaded pmpaddr1 to declare region1 start +#define PMPADDRESS2 tohost // value to be loaded pmpaddr2 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP2_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS3 Mclr_Msw_int // value to be loaded pmpaddr3 to declare region1 start +#define PMPADDRESS4 PMP_region_High // value to be loaded pmpaddr4 to declare region1 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS5 RETURN_INSTRUCTION // value to be loaded pmpaddr5 to declare region2 start +# define PMPADDRESS6 PMP_region_High // value to be loaded pmpaddr6 to declare region2 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP2_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address 0 upto RAM_LOCATION_FOR_TEST is configured + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Starting address exit_cleanup is loaded for reigion 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + nop //Added nop in case of trap + RVTEST_SIGUPD(x13,x5) //Update the signature + nop //Added nop in case of trap + + LA(x4, PMPADDRESS3) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Starting address RETURN_INSTRUCTION is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Ending address PMP_region_High is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 and Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LA(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region2 and Region2 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + RVTEST_SIGUPD(x13,x2) //Update the signature + + nop + jal RAM_LOCATION_FOR_TEST //jump to RAM_LOCATION_FOR_TEST to check execute permissions for region that is not configured for m mode + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_14.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_14.S new file mode 100644 index 000000000..e0beaeede --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_14.S @@ -0,0 +1,226 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +//This assembly file tests if we set mseccfg.MML=1 once, then mseccfg.MML cannot be written\modified +// + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_14) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define clear_mseccfg 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS exitLabel + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \exitLabel // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[0 till RAM_LOCATION_FOR_TEST] + [With Write and execute permissions enabled for that region and Lock is set] [Before MML set] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] [After MML set] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[RETURN_INSTRUCTION till PMP_region_High] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded pmpaddr0 to declare region0 +#define PMPREGION0 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 0 + + +#define PMPADDRESS1 exit_cleanup // value to be loaded pmpaddr1 to declare region1 start +#define PMPADDRESS2 tohost // value to be loaded pmpaddr2 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP2_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS3 Mclr_Msw_int // value to be loaded pmpaddr3 to declare region1 start +#define PMPADDRESS4 PMP_region_High // value to be loaded pmpaddr4 to declare region1 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP0_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS5 RETURN_INSTRUCTION // value to be loaded pmpaddr5 to declare region2 start +# define PMPADDRESS6 PMP_region_High // value to be loaded pmpaddr6 to declare region2 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP2_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address 0 upto RAM_LOCATION_FOR_TEST is configured + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Starting address exit_cleanup is loaded for reigion 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Starting address RETURN_INSTRUCTION is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Ending address PMP_region_High is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + + LA(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 and Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LA(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region2 and Region2 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + RVTEST_SIGUPD(x13,x2) //Update the signature with the csr value + + csrw mseccfg,zero + csrr x3,mseccfg + RVTEST_SIGUPD(x13,x3) //Update the signature with the csr value + + LI(x2,clear_mseccfg) + RVTEST_SIGUPD(x13,x2) //Update the signature with + csrc mseccfg,x2 + csrr x3,mseccfg + RVTEST_SIGUPD(x13,x3) //Update the signature with the csr value + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_15.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_15.S new file mode 100644 index 000000000..d0d788188 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_15.S @@ -0,0 +1,230 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests, if(mseccfg.MML=1 and pmpcfg.L=0) and (R=0,W=0,X=0) then it is an Inaccessible region + //and access Exception should be thrown for M mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_15) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is set] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for m mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_16_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_16_SMode.S new file mode 100644 index 000000000..dde9e09d3 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_16_SMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=0,W=0,X=0) then it is an Inaccessible region +//and access Exception should be thrown for S/U mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_16_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for S/U mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_16_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_16_UMode.S new file mode 100644 index 000000000..0e1f72369 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_16_UMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=0,W=0,X=0) then it is an Inaccessible region +//and access Exception should be thrown for S/U mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_16_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for S/U mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_17.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_17.S new file mode 100644 index 000000000..c85219cd8 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_17.S @@ -0,0 +1,230 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests, if(mseccfg.MML=1 and pmpcfg.L=0) and (R=0,W=0,X=1) then it is an Inaccessible region + //and access Exception should be thrown for M mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_17) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for m mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_18_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_18_SMode.S new file mode 100644 index 000000000..1ef48280f --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_18_SMode.S @@ -0,0 +1,237 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=0,W=0,X=1) then it is an execute only region for S/U mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_18_Smode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Execute permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Read, write is not permitted for S/U mode and execute is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_18_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_18_UMode.S new file mode 100644 index 000000000..430bbc49c --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_18_UMode.S @@ -0,0 +1,237 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=0,W=0,X=1) then it is an execute only region for S/U mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_18_Umode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Execute permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Read, write is not permitted for S/U mode and execute is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_19.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_19.S new file mode 100644 index 000000000..029485171 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_19.S @@ -0,0 +1,230 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,if(mseccfg.MML=1 and pmpcfg.L=0) and (R=0,W=1,X=0) then it is a shared data region, +//and read and write for M mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_19) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Reand and Write permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Read and write is permitted for m mode But execute is not so will cause trap on exection) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_20_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_20_SMode.S new file mode 100644 index 000000000..acf612484 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_20_SMode.S @@ -0,0 +1,237 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=0,W=1,X=0) then it is a shared data region, +//and read only region for S/U mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_20_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Write and execute is not permitted for S/U mode and Read is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_20_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_20_UMode.S new file mode 100644 index 000000000..0e4da0e4c --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_20_UMode.S @@ -0,0 +1,237 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=0,W=1,X=0) then it is a shared data region, +//and read only region for S/U mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_20_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Write and execute is not permitted for S/U mode and Read is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_21.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_21.S new file mode 100644 index 000000000..1c14009f8 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_21.S @@ -0,0 +1,231 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,if(mseccfg.MML=1 and pmpcfg.L=0) and (R=0,W=1,X=1) then it is a shared data region, + //read and write for M mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_21) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read and Write permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Read and is permitted for m mode and execute is not so will cause trap on execution) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_22_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_22_SMode.S new file mode 100644 index 000000000..02eabb416 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_22_SMode.S @@ -0,0 +1,237 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=0,W=1,X=1) then it is a shared data region, +// read and write for S/U mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_22_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read and write permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Execute is not permitted for S/U mode and Read and write is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_22_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_22_UMode.S new file mode 100644 index 000000000..c584ad26a --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_22_UMode.S @@ -0,0 +1,237 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=0,W=1,X=1) then it is a shared data region, +// read and write for S/U mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_22_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read and write permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Execute is not permitted for S/U mode and Read and write is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_23.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_23.S new file mode 100644 index 000000000..6d2f817c9 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_23.S @@ -0,0 +1,230 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,if(mseccfg.MML=1 and pmpcfg.L=0) and (R=1,W=0,X=0) then it is an Inaccessible region +// and access Exception should be thrown for M mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_23) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_R | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for m mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_24_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_24_SMode.S new file mode 100644 index 000000000..4108d0bf7 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_24_SMode.S @@ -0,0 +1,236 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=1,W=0,X=0) then it is a read only region for S/U mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_24_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_R | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Write and execute is not permitted for S/U mode and Read is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_24_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_24_UMode.S new file mode 100644 index 000000000..8a9f51b0d --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_24_UMode.S @@ -0,0 +1,236 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=1,W=0,X=0) then it is a read only region for S/U mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_24_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_R | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Write and execute is not permitted for S/U mode and Read is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_25.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_25.S new file mode 100644 index 000000000..68698fd5a --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_25.S @@ -0,0 +1,234 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,if(mseccfg.MML=1 and pmpcfg.L=0) and (R=1,W=0,X=1) then it is an Inaccessible region +// and access Exception should be thrown for M mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_25) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for m mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_26_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_26_SMode.S new file mode 100644 index 000000000..acff41bed --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_26_SMode.S @@ -0,0 +1,236 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=1,W=0,X=1) then it is a read and execute region for S/U mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_26_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read and execute permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Write is not permitted for S/U mode and Read and execute is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_26_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_26_UMode.S new file mode 100644 index 000000000..0a28bdeac --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_26_UMode.S @@ -0,0 +1,236 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=1,W=0,X=1) then it is a read and execute region for S/U mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_26_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read and execute permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Write is not permitted for S/U mode and Read and execute is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_27.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_27.S new file mode 100644 index 000000000..f6e82e10b --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_27.S @@ -0,0 +1,230 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,if(mseccfg.MML=1 and pmpcfg.L=0) and (R=1,W=1,X=0) then it is an Inaccessible region +// and access Exception should be thrown for M mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_27) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_R | PMP_W |PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for m mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_28_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_28_SMode.S new file mode 100644 index 000000000..4541ea3a7 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_28_SMode.S @@ -0,0 +1,236 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=1,W=1,X=0) then it is a read and write region for S/U mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_28_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read and write permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Execute is not permitted for S/U mode and Read and write is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_28_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_28_UMode.S new file mode 100644 index 000000000..0357af6e4 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_28_UMode.S @@ -0,0 +1,236 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=1,W=1,X=0) then it is a read and write region for S/U mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_28_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read and write permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Execute is not permitted for S/U mode and Read and write is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_29.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_29.S new file mode 100644 index 000000000..a076439f4 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_29.S @@ -0,0 +1,230 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,if(mseccfg.MML=1 and pmpcfg.L=0) and (R=1,W=1,X=1) then it is an Inaccessible region +// and access Exception should be thrown for M mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_29) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_R | PMP_W | PMP_X |PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for m mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_30_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_30_SMode.S new file mode 100644 index 000000000..207daa4fd --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_30_SMode.S @@ -0,0 +1,237 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=1,W=1,X=1) then it is a read,write and execute region +//for S/U mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_30_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read, write and execution permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_R | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Read, write and execute is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_30_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_30_UMode.S new file mode 100644 index 000000000..3acdad150 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_30_UMode.S @@ -0,0 +1,237 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=0) and (R=1,W=1,X=1) then it is a read,write and execute region +//for S/U mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_30_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read, write and execution permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_R | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Read, write and execute is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_31.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_31.S new file mode 100644 index 000000000..0d15b327b --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_31.S @@ -0,0 +1,230 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,if(mseccfg.MML=1 and pmpcfg.L=1) and (R=0,W=0,X=0) then it is an Inaccessible region +// and access Exception should be thrown for M mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_31) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for m mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_32_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_32_SMode.S new file mode 100644 index 000000000..a0aed7716 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_32_SMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=0,W=0,X=0) then it is an Inaccessible region +//and access Exception should be thrown for S/U mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_32_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for S/U mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_32_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_32_UMode.S new file mode 100644 index 000000000..7c695b059 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_32_UMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=0,W=0,X=0) then it is an Inaccessible region +//and access Exception should be thrown for S/U mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_32_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for S/U mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_33.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_33.S new file mode 100644 index 000000000..031bf7697 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_33.S @@ -0,0 +1,234 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,if(mseccfg.MML=1 and pmpcfg.L=1) and (R=0,W=0,X=1) then it is a locked execute only region +// for M mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_33) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Execute permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_X |PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrs mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST( Read, write is not permitted for m mode and execute is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_34_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_34_SMode.S new file mode 100644 index 000000000..d4f11f1fd --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_34_SMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +// This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=0,W=0,X=1) then it is an Inaccessible region +// and access Exception should be thrown for for S/U mode +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_34_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for S/U mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_34_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_34_UMode.S new file mode 100644 index 000000000..c5025c14a --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_34_UMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +// This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=0,W=0,X=1) then it is an Inaccessible region +// and access Exception should be thrown for for S/U mode +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_34_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for S/U mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_35.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_35.S new file mode 100644 index 000000000..79a8d4924 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_35.S @@ -0,0 +1,234 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,if(mseccfg.MML=1 and pmpcfg.L=1) and (R=0,W=1,X=0) then it is a locked shared code region, + //execute only for M mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_35) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Execute permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_W |PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrs mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST( Read, write is not permitted for m mode and execute is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_36_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_36_SMode.S new file mode 100644 index 000000000..0d4b43ee6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_36_SMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +// This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=0,W=1,X=0) then it is a locked shared code region, +//execute only for S/U mode +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_36_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With execute permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Read and write is not permitted for S/U mode and execute is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_36_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_36_UMode.S new file mode 100644 index 000000000..85b81929d --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_36_UMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +// This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=0,W=1,X=0) then it is a locked shared code region, +//execute only for S/U mode +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_36_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With execute permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Read and write is not permitted for S/U mode and execute is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_37.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_37.S new file mode 100644 index 000000000..5e3d58e2a --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_37.S @@ -0,0 +1,234 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,if(mseccfg.MML=1 and pmpcfg.L=1) and (R=0,W=1,X=1) then it is a locked shared code region, +// read and execute for M mode + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_37) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read and Execute permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_W | PMP_X |PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrs mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST( Write is not permitted for m mode and Read, execute is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_38_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_38_SMode.S new file mode 100644 index 000000000..da17d5f1e --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_38_SMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +// This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=0,W=1,X=1) then it is a locked shared code region, +// execute only for S/U mode +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_38_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With execute permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Read and write is not permitted for S/U mode and execute is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_38_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_38_UMode.S new file mode 100644 index 000000000..663eb7199 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_38_UMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +// This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=0,W=1,X=1) then it is a locked shared code region, +// execute only for S/U mode +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_38_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With execute permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Read and write is not permitted for S/U mode and execute is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_39.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_39.S new file mode 100644 index 000000000..7e387be31 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_39.S @@ -0,0 +1,233 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,if(mseccfg.MML=1 and pmpcfg.L=1) and (R=1,W=0,X=0) then it is a locked read only region +// for M mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_39) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_R |PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrs mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST( Write and execute is not permitted for m mode and Read is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_40_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_40_SMode.S new file mode 100644 index 000000000..4d179892f --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_40_SMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +// This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=1,W=0,X=0) then it is an Inaccessible region +//and access Exception should be thrown for for S/U mode +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_40_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_R | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for S/U mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_40_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_40_UMode.S new file mode 100644 index 000000000..9ace6108b --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_40_UMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +// This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=1,W=0,X=0) then it is an Inaccessible region +//and access Exception should be thrown for for S/U mode +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_40_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_R | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for S/U mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_41_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_41_SMode.S new file mode 100644 index 000000000..9fe44c277 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_41_SMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +// This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=1,W=0,X=1) then it is an +// Inaccessible region and access Exception should be thrown for for S/U mode +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_41_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for S/U mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_41_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_41_UMode.S new file mode 100644 index 000000000..d569903b9 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_41_UMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +// This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=1,W=0,X=1) then it is an +// Inaccessible region and access Exception should be thrown for for S/U mode +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_41_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for S/U mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_42.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_42.S new file mode 100644 index 000000000..6a121c141 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_42.S @@ -0,0 +1,233 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,if(mseccfg.MML=1 and pmpcfg.L=1) and (R=1,W=0,X=1) then it is a locked read and execute region +// for M mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_42) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read and execute permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_R | PMP_X |PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrs mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST( Write is not permitted for m mode and Read, execute is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_43.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_43.S new file mode 100644 index 000000000..8b65ca33b --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_43.S @@ -0,0 +1,233 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,if(mseccfg.MML=1 and pmpcfg.L=1) and (R=1,W=1,X=0) then it is a locked read and write region +// for M mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_43) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read and write permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_R | PMP_W |PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrs mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST( Execute is not permitted for m mode and Read, write is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_44_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_44_SMode.S new file mode 100644 index 000000000..e23fc40cc --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_44_SMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +// This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=1,W=1,X=0) then it is an Inaccessible region +// and access Exception should be thrown for for S/U mode +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_44_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for S/U mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_44_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_44_UMode.S new file mode 100644 index 000000000..af6e050cf --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_44_UMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +// This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=1,W=1,X=0) then it is an Inaccessible region +// and access Exception should be thrown for for S/U mode +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_44_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With no permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Neither Read, write nor execute is permitted for S/U mode) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_45.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_45.S new file mode 100644 index 000000000..74ca48bb0 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_45.S @@ -0,0 +1,233 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,if(mseccfg.MML=1 and pmpcfg.L=1) and (R=1,W=1,X=1) then it is a locked share data region + //and read only region for M mode +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_45) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read permission is enabled for M mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_R | PMP_W | PMP_X |PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x2,setMML) + csrs mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + //--------------------------------------------------------------------------------------------------------- + + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Write and Execute is not permitted for m mode and Read is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_46_SMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_46_SMode.S new file mode 100644 index 000000000..a90c147a9 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_46_SMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +// This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=1,W=1,X=1) then it is a locked share data region +// and read only region for S/U mode +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_46_SMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_R | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Smode // GO into S mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Write and execute is not permitted for S/U mode and Read is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_46_UMode.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_46_UMode.S new file mode 100644 index 000000000..9858dcd2b --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_46_UMode.S @@ -0,0 +1,238 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +// This assembly file tests if(mseccfg.MML=1 and pmpcfg.L=1) and (R=1,W=1,X=1) then it is a locked share data region +// and read only region for S/U mode +// +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_46_UMode) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) //To add an executable region after MML set we need RLB set that is why set here + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [With Read permission is enabled for S/U mode for that region] [Testing region for RWX permissions] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M and S/U mode for that region and Lock is clear] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set][Old configuration] + [With Read, Execute permissions enabled for M mode and Execute only for S/U mode for that region and Lock is set][New configuration] +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_R | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_X | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 +# define NEW_PMPREGION3 ((( PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION3) //Permission for Region3 is loaded + csrw pmpcfg1, x6 + csrr x9,pmpcfg1 //Read to confirm configuration is set properly + + LI(x10,setMML) + csrs mseccfg, x10 //Setting mseccfg.MML + csrr x10,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0 | PMPREGION1) //Permission for Region 0 is loaded + csrw pmpcfg0, x6 + csrr x11,pmpcfg0 //Read to confirm configuration is set properly + + LI(x6, PMPREGION2 | NEW_PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x12,pmpcfg1 //Read to confirm configuration is set properly + + RVTEST_SIGUPD(x13,x9) //Update the signature + RVTEST_SIGUPD(x13,x10) //Update the signature with mseccfg value + RVTEST_SIGUPD(x13,x11) //Update the signature with configuration of region 0 and 1 + RVTEST_SIGUPD(x13,x12) //Update the signature with configuration of region 2 and 3 + + //--------------------------------------------------------------------------------------------------------- + + RVTEST_GOTO_LOWER_MODE Umode // GO into U mode + nop + VERIFICATION_RWX RAM_LOCATION_FOR_TEST //macro is called with address as RAM_LOCATION_FOR_TEST(Write and execute is not permitted for S/U mode and Read is permitted) + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_47.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_47.S new file mode 100644 index 000000000..de4069de6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_47.S @@ -0,0 +1,230 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,Set (mseccfg.MML=1, mseccfg.RLB=0 and pmpcfg.L=1) (R=0,W=0,X=1)and +// now perform pmpcfg writes such pmpcfg writes are ignored, leaving pmpcfg +// unchanged for M-mode-only or a locked Shared-Region rule with executable privileges + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_47) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [Adding an executable region (mseccfg.MML=1, mseccfg.RLB=0 and pmpcfg.L=1) (R=0,W=0,X=1)] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is set] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + +//--------------------------------------------------------------------------------------------------------- + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration should not be written which is what spec says when MML is set we cannot add an executable region + RVTEST_SIGUPD(x13,x7) //Update the signature + + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_48.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_48.S new file mode 100644 index 000000000..7884ca019 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_48.S @@ -0,0 +1,230 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,Set (mseccfg.MML=1, mseccfg.RLB=0 and pmpcfg.L=1) (R=0,W=1,X=0)and +// now perform pmpcfg writes such pmpcfg writes are ignored, leaving pmpcfg +// unchanged for M-mode-only or a locked Shared-Region rule with executable privileges + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_48) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [Adding an executable region (mseccfg.MML=1, mseccfg.RLB=0 and pmpcfg.L=1) (R=0,W=1,X=0)] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is set] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + +//--------------------------------------------------------------------------------------------------------- + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration should not be written which is what spec says when MML is set we cannot add an executable region + RVTEST_SIGUPD(x13,x7) //Update the signature + + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_49.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_49.S new file mode 100644 index 000000000..4fbb980b0 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_49.S @@ -0,0 +1,230 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,Set (mseccfg.MML=1, mseccfg.RLB=0 and pmpcfg.L=1) (R=0,W=1,X=1)and +// now perform pmpcfg writes such pmpcfg writes are ignored, leaving pmpcfg +// unchanged for M-mode-only or a locked Shared-Region rule with executable privileges + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_49) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [Adding an executable region (mseccfg.MML=1, mseccfg.RLB=0 and pmpcfg.L=1) (R=0,W=1,X=1)] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is set] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + +//--------------------------------------------------------------------------------------------------------- + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration should not be written which is what spec says when MML is set we cannot add an executable region + RVTEST_SIGUPD(x13,x7) //Update the signature + + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_50.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_50.S new file mode 100644 index 000000000..09201f108 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_50.S @@ -0,0 +1,230 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,Set (mseccfg.MML=1, mseccfg.RLB=0 and pmpcfg.L=1) (R=1,W=0,X=1)and +// now perform pmpcfg writes such pmpcfg writes are ignored, leaving pmpcfg +// unchanged for M-mode-only or a locked Shared-Region rule with executable privileges + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_50) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [Adding an executable region (mseccfg.MML=1, mseccfg.RLB=0 and pmpcfg.L=1) (R=1,W=0,X=1)] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is set] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + +//--------------------------------------------------------------------------------------------------------- + + LI(x2,setMML) + csrw mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration should not be written which is what spec says when MML is set we cannot add an executable region + RVTEST_SIGUPD(x13,x7) //Update the signature + + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_51.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_51.S new file mode 100644 index 000000000..94b7ff4d7 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_51.S @@ -0,0 +1,234 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,Set (mseccfg.MML=1, mseccfg.RLB=1 and pmpcfg.L=1) (R=0,W=0,X=1)and +// now perform pmpcfg writes such pmpcfg writes are not ignored now, leaving pmpcfg +// changed for M-mode-only or a locked Shared-Region rule with executable privileges + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_51) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) + csrw mseccfg, x2 //Setting mseccfg.RLB + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [Adding an executable region (mseccfg.MML=1, mseccfg.RLB=1 and pmpcfg.L=1) (R=0,W=0,X=1)] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is set] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + +//--------------------------------------------------------------------------------------------------------- + + LI(x2,setMML) + csrs mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration should be written which is what spec says when MML is set with RLB set we can add an executable region + RVTEST_SIGUPD(x13,x7) //Update the signature + + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_52.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_52.S new file mode 100644 index 000000000..94c4d3ab5 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_52.S @@ -0,0 +1,234 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,Set (mseccfg.MML=1, mseccfg.RLB=1 and pmpcfg.L=1) (R=0,W=1,X=0)and +// now perform pmpcfg writes such pmpcfg writes are not ignored now, leaving pmpcfg +// changed for M-mode-only or a locked Shared-Region rule with executable privileges + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_52) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) + csrw mseccfg, x2 //Setting mseccfg.RLB + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [Adding an executable region (mseccfg.MML=1, mseccfg.RLB=1 and pmpcfg.L=1) (R=0,W=1,X=0)] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is set] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + +//--------------------------------------------------------------------------------------------------------- + + LI(x2,setMML) + csrs mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration should be written which is what spec says when MML is set with RLB set we can add an executable region + RVTEST_SIGUPD(x13,x7) //Update the signature + + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_53.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_53.S new file mode 100644 index 000000000..1c15984c4 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_53.S @@ -0,0 +1,234 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,Set (mseccfg.MML=1, mseccfg.RLB=1 and pmpcfg.L=1) (R=0,W=1,X=1)and +// now perform pmpcfg writes such pmpcfg writes are not ignored now, leaving pmpcfg +// changed for M-mode-only or a locked Shared-Region rule with executable privileges + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_53) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) + csrw mseccfg, x2 //Setting mseccfg.RLB + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [Adding an executable region (mseccfg.MML=1, mseccfg.RLB=1 and pmpcfg.L=1) (R=0,W=1,X=1)] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is set] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_W | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + +//--------------------------------------------------------------------------------------------------------- + + LI(x2,setMML) + csrs mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration should be written which is what spec says when MML is set with RLB set we can add an executable region + RVTEST_SIGUPD(x13,x7) //Update the signature + + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_54.S b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_54.S new file mode 100644 index 000000000..dd6c8a8ad --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/ePMP32/ePMP_54.S @@ -0,0 +1,234 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This test belongs to ePMP Test plan developed by 10xEngineers +// which can be found here: https://docs.google.com/spreadsheets/d/1dDeSlpOrtMDFhkv7ysAbCgCjOKVzhhvxCY83DirL92w/edit?usp=sharing +// +// +//This assembly file tests,Set (mseccfg.MML=1, mseccfg.RLB=1 and pmpcfg.L=1) (R=1,W=0,X=1)and +// now perform pmpcfg writes such pmpcfg writes are not ignored now, leaving pmpcfg +// changed for M-mode-only or a locked Shared-Region rule with executable privileges + +#define rvtest_strap_routine +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",ePMP_test_54) +RVTEST_SIGBASE( x13,signature_x13_1) + .option nopic + .attribute unaligned_access, 0 + .attribute stack_align, 16 + .align 2 + +#define test_value 0x44444444 +#define Start 0x00000000 +#define EntireMemorySpace 0xFFFFFFFF + +#define setRLB 4 +#define setMMWP 2 +#define setMML 1 + +#define PMPCFG0 0x3A0 // Address of pmpcfg0 (HAS BEEN USED WHILE ITERATING THE LOOP) +#define PMPADDR0 0x3B0 // Address of pmpaddr0 (HAS BEEN USED WHILE ITERATING THE LOOP) + +#define PMP0_CFG_SHIFT 0 +#define PMP1_CFG_SHIFT 8 +#define PMP2_CFG_SHIFT 16 +#define PMP3_CFG_SHIFT 24 + +//------------------------------This macro is used for testing the RWX for region5 (region under test)------------------ + +#define NOP 0x13 +.macro VERIFICATION_RWX ADDRESS + LA(a5, \ADDRESS) //Fetch the address to be checked + lw a4,0(a5) // Load data from it (CHECK FOR READ) ; (NOT TRAP => R enabled) + nop // Added nop in case of trap + // WRITING new value to memory region TRAP if the WRITability is blocked + LI(a4, NOP) // Load the new value (NOP Instruction ID) + sw a4,0(a5) // Store the new value (NOT TRAP => W enabled) + nop // Added nop in case of trap + lw a4,0(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + nop // Added nop in case of trap + jal \ADDRESS // Test for execution, an instruction is placed at this address +.endm +//----------------------------------------------------------------------------------------------------------------------- + + +main: + + LI(x1,test_value) //Load a value in a register which signifies we are in main + RVTEST_SIGUPD(x13,x1) //Update the signature + +//------------------------------Loop to initialize all pmpaddr and pmpcfg CSR(s) to zero-------------------------------- + + .set pmpcfgi, PMPCFG0 // Initialize an iterating variable with the address of pmpcfg0 + .rept 4 // START OF LOOP(Repeat 4 times) + csrw pmpcfgi , x0 // Set all pmpcfg regs to zero (initial value) + .set pmpcfgi, pmpcfgi+1 // increment variable to next pmpcfg reg + .endr // END OF LOOP BODY + // Loop to SET ALL pmpaddr REGs to zero + .set pmpaddri, PMPADDR0 // Initialize an iterating variable with the address of pmpaddr0 + .rept 16 // START OF LOOP(Repeat 16 times) + csrw pmpaddri, x0 // Set all pmpaddr regs to zero (initial value) + .set pmpaddri, pmpaddri+1 // increment variable pmpaddri to the next pmpaddr reg + .endr // END OF LOOP BODY + +//----------------------------------------------------------------------------------------------------------------------- + + LI(x2,setRLB) + csrw mseccfg, x2 //Setting mseccfg.RLB + csrr x2,mseccfg //Verify its value by reading back + +/*-------------------------------Descritption of all regions used------------------------------------------------- + +{Region 0}-------->[RAM_LOCATION_FOR_TEST till RETURN_INSTRUCTION] + [Adding an executable region (mseccfg.MML=1, mseccfg.RLB=1 and pmpcfg.L=1) (R=1,W=0,X=1)] + +{Region 1}-------->[exit_cleanup till tohost] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +{Region 2}-------->[Mclr_Msw_int till PMP_region_High] + [With Read and Write permissions enabled for M mode for that region and Lock is set] + +{Region 3}-------->[Start till EntireMemorySpace] + [With Read and Execute permissions enabled for M mode for that region and Lock is set] + +------------------------------------------------------------------------------------------------------------------*/ + +#define PMPADDRESS0 RAM_LOCATION_FOR_TEST // value to be loaded in pmpaddr0 to declare region0 start +#define PMPADDRESS1 RETURN_INSTRUCTION // value to be loaded pmpaddr1 to declare region0 end +#define PMPREGION0 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 0 + +#define PMPADDRESS2 exit_cleanup // value to be loaded in pmpaddr2 to declare region1 start +#define PMPADDRESS3 tohost // value to be loaded in pmpaddr3 to declare region1 end +#define PMPREGION1 (((PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 1 + +#define PMPADDRESS4 Mclr_Msw_int // value to be loaded in pmpaddr4 to declare region2 start +#define PMPADDRESS5 PMP_region_High // value to be loaded in pmpaddr5 to declare region2 end +#define PMPREGION2 (((PMP_L | PMP_R | PMP_W | PMP_TOR)&0xFF)<< PMP1_CFG_SHIFT) // Configuration for region 2 + +# define PMPADDRESS6 Start // value to be loaded in pmpaddr6 to declare region3 start +# define PMPADDRESS7 EntireMemorySpace // value to be loaded in pmpaddr7 to declare region3 end +# define PMPREGION3 ((( PMP_L | PMP_R | PMP_X | PMP_TOR)&0xFF)<< PMP3_CFG_SHIFT) // Configuration for region 3 + + +//------------------ Configuring 4 regions and setting mseccfg.MML as mentioned above-------------------------------------------------- + + csrw satp, zero //Disable address translation. + + LA(x4, PMPADDRESS0) //Starting address RAM_LOCATION_FOR_TEST is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr0, x4 //Updated pmpaddr0 to define PMP region consisting + csrr x5, pmpaddr0 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS1) //Ending address RETURN_INSTRUCTION is loaded for reigion0 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr1, x4 //Updated pmpaddr1 to define PMP region consisting + csrr x5, pmpaddr1 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS2) //Starting address exit_cleanup is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr2, x4 //Updated pmpaddr2 to define PMP region consisting + csrr x5, pmpaddr2 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS3) //Ending address tohost is loaded for region 1 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr3, x4 //Updated pmpaddr3 to define PMP region consisting + csrr x5, pmpaddr3 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS4) //Starting address Mclr_Msw_int is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr4, x4 //Updated pmpaddr4 to define PMP region consisting + csrr x5, pmpaddr4 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS5) //Ending address PMP_region_High is loaded for region 2 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr5, x4 //Updated pmpaddr5 to define PMP region consisting + csrr x5, pmpaddr5 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS6) //Starting address Start is loaded for region 3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr6, x4 //Updated pmpaddr6 to define PMP region consisting + csrr x5, pmpaddr6 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LA(x4, PMPADDRESS7) //Ending address EntireMemorySpace is loaded for region3 + srl x4, x4, PMP_SHIFT // Shift right by 2 times + csrw pmpaddr7, x4 //Updated pmpaddr7 to define PMP region consisting + csrr x5, pmpaddr7 //Verify its value by reading back + RVTEST_SIGUPD(x13,x5) //Update the signature + + LI(x6, PMPREGION1) //Permission for Region1 is loaded + csrw pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + + LI(x6, PMPREGION2 | PMPREGION3 ) //Permission for Region 2 and region 3 is loaded + csrw pmpcfg1, x6 + csrr x7,pmpcfg1 //Read to confirm configuration is set properly + RVTEST_SIGUPD(x13,x7) //Update the signature + +//--------------------------------------------------------------------------------------------------------- + + LI(x2,setMML) + csrs mseccfg, x2 //Setting mseccfg.MML + csrr x2,mseccfg //Verify its value by reading back + nop + + LI(x6, PMPREGION0) //Permission for Region 0 is loaded + csrs pmpcfg0, x6 + csrr x7,pmpcfg0 //Read to confirm configuration should not be written which is what spec says when MML is set we cannot add an executable region + RVTEST_SIGUPD(x13,x7) //Update the signature + + + j exit + +RAM_LOCATION_FOR_TEST: //This is the region which will be used to test RWX permissions + .fill 1*(XLEN/32),4,0x13 + addi x9,x9,0x01 // A TEST INSTRUCTION TO TEST THE EXECUTION CHECK ON PMP REGION + +RETURN_INSTRUCTION: + ret + +exit: + +#endif + # --------------------------------------------------------------------------------------------- + # HALT +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xdeadcafe +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +signature_x13_0: + .fill 0*(XLEN/32),4,0x12345678 +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 256*(XLEN/32),4,0xdeadbeef +#endif +#ifdef rvtest_gpr_save +gpr_save: + .fill 24*(XLEN/32),4,0xc9a8b7f1 +#endif +PMP_region_High: +RVMODEL_DATA_END \ No newline at end of file