diff --git a/riscv-test-suite/env/test_macros.h b/riscv-test-suite/env/test_macros.h index 972be7706..5f76261df 100644 --- a/riscv-test-suite/env/test_macros.h +++ b/riscv-test-suite/env/test_macros.h @@ -453,16 +453,69 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg) csrr flagreg, fcsr ;\ ) +#define TEST_FPSR_OP_VFWMACCBF16_VV( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \ + LI(testreg, fcsr_val) ; \ + csrw fcsr, testreg ; \ + vmv.s.x v1, x0 ; \ + vfmv.s.f v2, freg ; \ + vfmv.s.f v3, freg ; \ + inst v1, v2, v3 ; \ + vfmv.f.s destreg, v1 ; \ + csrr flagreg, fcsr ; \ + ) + +#define TEST_FPSR_OP_VFWMACCBF16_VF( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \ + LI(testreg, fcsr_val) ; \ + csrw fcsr, testreg ; \ + vmv.s.x v1, x0 ; \ + vfmv.s.f v3, freg ; \ + inst v1, freg, v3 ; \ + vfmv.f.s destreg, v1 ; \ + csrr flagreg, fcsr ; \ + ) + +//Tests for floating-point instructions with a single register operand +#define TEST_FPSR_OP_V16_32( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \ + LI(testreg, fcsr_val) ; \ + csrw fcsr, testreg ; \ + vsetivli x0, 1, e16, m1, ta, ma ; \ + vfmv.s.f v1, freg ; \ + inst v2, v1 ; \ + vsetivli x0, 1, e32, m1, ta, ma ; \ + vfmv.f.s destreg, v2 ; \ + csrr flagreg, fcsr ; \ + ) + //Tests for floating-point instructions with a single register operand //This variant does not take the rm field and set it while writing the instruction -#define TEST_FPSR_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ +#define TEST_FPSR_OP_NRM_V32_16( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg) ;\ li testreg, fcsr_val; csrw fcsr, testreg ;\ - inst destreg, freg ;\ + vsetivli x0, 1, e32, m1, ta, ma ; \ + vfmv.s.f v1, freg ; \ + vsetivli x0, 1, e16, m1, ta, ma ; \ + inst v2, v1 ; \ + vfmv.f.s destreg, v2 ; \ csrr flagreg, fcsr ;\ ) +//Tests for floating-point instructions with a single register operand +//This variant does not take the rm field and set it while writing the instruction +#define TEST_FPSR_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg) ; \ + li testreg, fcsr_val; csrw fcsr, testreg ; \ + inst destreg, freg ; \ + csrr flagreg, fcsr ; \ + ) + //Tests for floating-point instructions with a single register operand and integer destination register #define TEST_FPID_OP( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg,load_instr) \ TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, \ diff --git a/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b1-01.S b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b1-01.S new file mode 100644 index 000000000..3ba42b5d5 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b1-01.S @@ -0,0 +1,1254 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:32 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.bf16.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.bf16.s instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.bf16.s_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfbfmin,RV64IF_Zicsr_Zfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfbfmin.*);def TEST_CASE_1=True;",fcvt.bf16.s_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f29; dest:f29; op1val:0x0; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f30; op1val:0x0; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f27; dest:f28; op1val:0x0; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f28; dest:f27; op1val:0x0; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f25; dest:f26; op1val:0x80000000; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f26; dest:f25; op1val:0x80000000; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f23; dest:f24; op1val:0x80000000; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f24; dest:f23; op1val:0x80000000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f21; dest:f22; op1val:0x80000000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f22; dest:f21; op1val:0x1; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f19; dest:f20; op1val:0x1; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f20; dest:f19; op1val:0x1; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f17; dest:f18; op1val:0x1; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f18; dest:f17; op1val:0x1; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f15; dest:f16; op1val:0x80000001; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f16; dest:f15; op1val:0x80000001; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f13; dest:f14; op1val:0x80000001; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f14; dest:f13; op1val:0x80000001; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f11; dest:f12; op1val:0x80000001; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f12; dest:f11; op1val:0x2; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f9; dest:f10; op1val:0x2; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f10; dest:f9; op1val:0x2; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f7; dest:f8; op1val:0x2; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f8; dest:f7; op1val:0x2; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f5; dest:f6; op1val:0x807ffffe; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f6; dest:f5; op1val:0x807ffffe; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f3; dest:f4; op1val:0x807ffffe; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f4; dest:f3; op1val:0x807ffffe; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f1; dest:f2; op1val:0x807ffffe; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f2; dest:f1; op1val:0x7fffff; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f0; dest:f31; op1val:0x7fffff; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f0; op1val:0x7fffff; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fffff; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fffff; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x807fffff; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x807fffff; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x807fffff; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x807fffff; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x807fffff; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800000; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800000; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800000; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800000; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800000; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80800000; valaddr_reg:x3; +val_offset:45*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80800000; valaddr_reg:x3; +val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80800000; valaddr_reg:x3; +val_offset:47*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 47*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80800000; valaddr_reg:x3; +val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80800000; valaddr_reg:x3; +val_offset:49*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 49*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800001; valaddr_reg:x3; +val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800001; valaddr_reg:x3; +val_offset:51*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800001; valaddr_reg:x3; +val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800001; valaddr_reg:x3; +val_offset:53*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 53*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800001; valaddr_reg:x3; +val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80855555; valaddr_reg:x3; +val_offset:55*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 55*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80855555; valaddr_reg:x3; +val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80855555; valaddr_reg:x3; +val_offset:57*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80855555; valaddr_reg:x3; +val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80855555; valaddr_reg:x3; +val_offset:59*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 59*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f8001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f8001; valaddr_reg:x3; +val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f8001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f8001; valaddr_reg:x3; +val_offset:61*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 61*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f8001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f8001; valaddr_reg:x3; +val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f8001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f8001; valaddr_reg:x3; +val_offset:63*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f8001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f8001; valaddr_reg:x3; +val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f0001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f0001; valaddr_reg:x3; +val_offset:65*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 65*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f0001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f0001; valaddr_reg:x3; +val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f0001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f0001; valaddr_reg:x3; +val_offset:67*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 67*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f0001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f0001; valaddr_reg:x3; +val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f0001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f0001; valaddr_reg:x3; +val_offset:69*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550000; valaddr_reg:x3; +val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550000; valaddr_reg:x3; +val_offset:71*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 71*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550000; valaddr_reg:x3; +val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550000; valaddr_reg:x3; +val_offset:73*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 73*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550000; valaddr_reg:x3; +val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550001; valaddr_reg:x3; +val_offset:75*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550001; valaddr_reg:x3; +val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550001; valaddr_reg:x3; +val_offset:77*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 77*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550001; valaddr_reg:x3; +val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550001; valaddr_reg:x3; +val_offset:79*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 79*FLEN/8, x4, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f8000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f8000; valaddr_reg:x3; +val_offset:80*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 80*FLEN/8, x4, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f8000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f8000; valaddr_reg:x3; +val_offset:81*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 81*FLEN/8, x4, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f8000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f8000; valaddr_reg:x3; +val_offset:82*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 82*FLEN/8, x4, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f8000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f8000; valaddr_reg:x3; +val_offset:83*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 83*FLEN/8, x4, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f8000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f8000; valaddr_reg:x3; +val_offset:84*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 84*FLEN/8, x4, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7fffff; valaddr_reg:x3; +val_offset:85*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 85*FLEN/8, x4, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7fffff; valaddr_reg:x3; +val_offset:86*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 86*FLEN/8, x4, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7fffff; valaddr_reg:x3; +val_offset:87*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 87*FLEN/8, x4, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7fffff; valaddr_reg:x3; +val_offset:88*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 88*FLEN/8, x4, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7fffff; valaddr_reg:x3; +val_offset:89*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 89*FLEN/8, x4, x1, x2) + +inst_90: +// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff7fffff; valaddr_reg:x3; +val_offset:90*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 90*FLEN/8, x4, x1, x2) + +inst_91: +// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff7fffff; valaddr_reg:x3; +val_offset:91*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 91*FLEN/8, x4, x1, x2) + +inst_92: +// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff7fffff; valaddr_reg:x3; +val_offset:92*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 92*FLEN/8, x4, x1, x2) + +inst_93: +// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff7fffff; valaddr_reg:x3; +val_offset:93*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 93*FLEN/8, x4, x1, x2) + +inst_94: +// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff7fffff; valaddr_reg:x3; +val_offset:94*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 94*FLEN/8, x4, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800000; valaddr_reg:x3; +val_offset:95*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 95*FLEN/8, x4, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800000; valaddr_reg:x3; +val_offset:96*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 96*FLEN/8, x4, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800000; valaddr_reg:x3; +val_offset:97*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 97*FLEN/8, x4, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800000; valaddr_reg:x3; +val_offset:98*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 98*FLEN/8, x4, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800000; valaddr_reg:x3; +val_offset:99*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 99*FLEN/8, x4, x1, x2) + +inst_100: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff800000; valaddr_reg:x3; +val_offset:100*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 100*FLEN/8, x4, x1, x2) + +inst_101: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff800000; valaddr_reg:x3; +val_offset:101*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 101*FLEN/8, x4, x1, x2) + +inst_102: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff800000; valaddr_reg:x3; +val_offset:102*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 102*FLEN/8, x4, x1, x2) + +inst_103: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff800000; valaddr_reg:x3; +val_offset:103*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 103*FLEN/8, x4, x1, x2) + +inst_104: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff800000; valaddr_reg:x3; +val_offset:104*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 104*FLEN/8, x4, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00000; valaddr_reg:x3; +val_offset:105*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 105*FLEN/8, x4, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00000; valaddr_reg:x3; +val_offset:106*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 106*FLEN/8, x4, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00000; valaddr_reg:x3; +val_offset:107*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 107*FLEN/8, x4, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00000; valaddr_reg:x3; +val_offset:108*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 108*FLEN/8, x4, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00000; valaddr_reg:x3; +val_offset:109*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 109*FLEN/8, x4, x1, x2) + +inst_110: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc00000; valaddr_reg:x3; +val_offset:110*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 110*FLEN/8, x4, x1, x2) + +inst_111: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc00000; valaddr_reg:x3; +val_offset:111*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 111*FLEN/8, x4, x1, x2) + +inst_112: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc00000; valaddr_reg:x3; +val_offset:112*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 112*FLEN/8, x4, x1, x2) + +inst_113: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc00000; valaddr_reg:x3; +val_offset:113*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 113*FLEN/8, x4, x1, x2) + +inst_114: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc00000; valaddr_reg:x3; +val_offset:114*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 114*FLEN/8, x4, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:115*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 115*FLEN/8, x4, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:116*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 116*FLEN/8, x4, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:117*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 117*FLEN/8, x4, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:118*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 118*FLEN/8, x4, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:119*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 119*FLEN/8, x4, x1, x2) + +inst_120: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc55555; valaddr_reg:x3; +val_offset:120*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 120*FLEN/8, x4, x1, x2) + +inst_121: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc55555; valaddr_reg:x3; +val_offset:121*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 121*FLEN/8, x4, x1, x2) + +inst_122: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc55555; valaddr_reg:x3; +val_offset:122*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 122*FLEN/8, x4, x1, x2) + +inst_123: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc55555; valaddr_reg:x3; +val_offset:123*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 123*FLEN/8, x4, x1, x2) + +inst_124: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc55555; valaddr_reg:x3; +val_offset:124*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 124*FLEN/8, x4, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800001; valaddr_reg:x3; +val_offset:125*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 125*FLEN/8, x4, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800001; valaddr_reg:x3; +val_offset:126*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 126*FLEN/8, x4, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800001; valaddr_reg:x3; +val_offset:127*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 127*FLEN/8, x4, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_128: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800001; valaddr_reg:x3; +val_offset:128*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 128*FLEN/8, x4, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800001; valaddr_reg:x3; +val_offset:129*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 129*FLEN/8, x4, x1, x2) + +inst_130: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:130*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 130*FLEN/8, x4, x1, x2) + +inst_131: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:131*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 131*FLEN/8, x4, x1, x2) + +inst_132: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:132*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 132*FLEN/8, x4, x1, x2) + +inst_133: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:133*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 133*FLEN/8, x4, x1, x2) + +inst_134: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:134*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 134*FLEN/8, x4, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:135*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 135*FLEN/8, x4, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:136*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 136*FLEN/8, x4, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:137*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 137*FLEN/8, x4, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:138*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 138*FLEN/8, x4, x1, x2) + +inst_139: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:139*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 139*FLEN/8, x4, x1, x2) + +inst_140: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:140*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 140*FLEN/8, x4, x1, x2) + +inst_141: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:141*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 141*FLEN/8, x4, x1, x2) + +inst_142: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:142*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 142*FLEN/8, x4, x1, x2) + +inst_143: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:143*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 143*FLEN/8, x4, x1, x2) + +inst_144: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:144*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 144*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(2147483649,32,FLEN) +NAN_BOXED(2147483649,32,FLEN) +NAN_BOXED(2147483649,32,FLEN) +NAN_BOXED(2147483649,32,FLEN) +NAN_BOXED(2147483649,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(2155872254,32,FLEN) +NAN_BOXED(2155872254,32,FLEN) +NAN_BOXED(2155872254,32,FLEN) +NAN_BOXED(2155872254,32,FLEN) +NAN_BOXED(2155872254,32,FLEN) +NAN_BOXED(8388607,32,FLEN) +NAN_BOXED(8388607,32,FLEN) +NAN_BOXED(8388607,32,FLEN) +NAN_BOXED(8388607,32,FLEN) +NAN_BOXED(8388607,32,FLEN) +NAN_BOXED(2155872255,32,FLEN) +NAN_BOXED(2155872255,32,FLEN) +NAN_BOXED(2155872255,32,FLEN) +NAN_BOXED(2155872255,32,FLEN) +NAN_BOXED(2155872255,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(2155872256,32,FLEN) +NAN_BOXED(2155872256,32,FLEN) +NAN_BOXED(2155872256,32,FLEN) +NAN_BOXED(2155872256,32,FLEN) +NAN_BOXED(2155872256,32,FLEN) +NAN_BOXED(8388609,32,FLEN) +NAN_BOXED(8388609,32,FLEN) +NAN_BOXED(8388609,32,FLEN) +NAN_BOXED(8388609,32,FLEN) +NAN_BOXED(8388609,32,FLEN) +NAN_BOXED(2156221781,32,FLEN) +NAN_BOXED(2156221781,32,FLEN) +NAN_BOXED(2156221781,32,FLEN) +NAN_BOXED(2156221781,32,FLEN) +NAN_BOXED(2156221781,32,FLEN) +NAN_BOXED(2139062273,32,FLEN) +NAN_BOXED(2139062273,32,FLEN) +NAN_BOXED(2139062273,32,FLEN) +NAN_BOXED(2139062273,32,FLEN) +NAN_BOXED(2139062273,32,FLEN) +NAN_BOXED(2139029505,32,FLEN) +NAN_BOXED(2139029505,32,FLEN) +NAN_BOXED(2139029505,32,FLEN) +NAN_BOXED(2139029505,32,FLEN) +NAN_BOXED(2139029505,32,FLEN) +NAN_BOXED(5570560,32,FLEN) +NAN_BOXED(5570560,32,FLEN) +NAN_BOXED(5570560,32,FLEN) +NAN_BOXED(5570560,32,FLEN) +NAN_BOXED(5570560,32,FLEN) +NAN_BOXED(5570561,32,FLEN) +NAN_BOXED(5570561,32,FLEN) +NAN_BOXED(5570561,32,FLEN) +NAN_BOXED(5570561,32,FLEN) +NAN_BOXED(5570561,32,FLEN) +NAN_BOXED(8355840,32,FLEN) +NAN_BOXED(8355840,32,FLEN) +NAN_BOXED(8355840,32,FLEN) +NAN_BOXED(8355840,32,FLEN) +NAN_BOXED(8355840,32,FLEN) +NAN_BOXED(2139095039,32,FLEN) +NAN_BOXED(2139095039,32,FLEN) +NAN_BOXED(2139095039,32,FLEN) +NAN_BOXED(2139095039,32,FLEN) +NAN_BOXED(2139095039,32,FLEN) +NAN_BOXED(4286578687,32,FLEN) +NAN_BOXED(4286578687,32,FLEN) +NAN_BOXED(4286578687,32,FLEN) +NAN_BOXED(4286578687,32,FLEN) +NAN_BOXED(4286578687,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(2143289344,32,FLEN) +NAN_BOXED(2143289344,32,FLEN) +NAN_BOXED(2143289344,32,FLEN) +NAN_BOXED(2143289344,32,FLEN) +NAN_BOXED(2143289344,32,FLEN) +NAN_BOXED(4290772992,32,FLEN) +NAN_BOXED(4290772992,32,FLEN) +NAN_BOXED(4290772992,32,FLEN) +NAN_BOXED(4290772992,32,FLEN) +NAN_BOXED(4290772992,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b22-01.S b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b22-01.S new file mode 100644 index 000000000..cdab11f69 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b22-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:32 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.bf16.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.bf16.s instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.bf16.s_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfbfmin,RV64IF_Zicsr_Zfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfbfmin.*);def TEST_CASE_1=True;",fcvt.bf16.s_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x7d and fm1 == 0x36e5d6 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f29; dest:f29; op1val:0x3eb6e5d6; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x7e and fm1 == 0x49fee5 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f30; op1val:0x3f49fee5; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x7f and fm1 == 0x1a616d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f27; dest:f28; op1val:0x3f9a616d; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x80 and fm1 == 0x681ae9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f28; dest:f27; op1val:0x40681ae9; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x81 and fm1 == 0x696b5c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f25; dest:f26; op1val:0x40e96b5c; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x67 and fm1 == 0x53a4fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f26; dest:f25; op1val:0x33d3a4fc; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0xc4 and fm1 == 0x046756 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f23; dest:f24; op1val:0x62046756; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.bf16.s ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.bf16.s ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.bf16.s ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.bf16.s ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.bf16.s ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.bf16.s ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.bf16.s ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.bf16.s ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.bf16.s ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.bf16.s ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.bf16.s ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.bf16.s ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.bf16.s ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.bf16.s ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.bf16.s ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.bf16.s ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.bf16.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.bf16.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.bf16.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.bf16.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.bf16.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.bf16.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.bf16.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.bf16.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.bf16.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1052173782,32,FLEN) +NAN_BOXED(1061813989,32,FLEN) +NAN_BOXED(1067082093,32,FLEN) +NAN_BOXED(1080564457,32,FLEN) +NAN_BOXED(1089039196,32,FLEN) +NAN_BOXED(869508348,32,FLEN) +NAN_BOXED(1644455766,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b23-01.S b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b23-01.S new file mode 100644 index 000000000..f92d54314 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b23-01.S @@ -0,0 +1,449 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:32 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.bf16.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.bf16.s instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.bf16.s_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfbfmin,RV64IF_Zicsr_Zfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfbfmin.*);def TEST_CASE_1=True;",fcvt.bf16.s_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f29; dest:f29; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f30; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f27; dest:f28; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f28; dest:f27; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f25; dest:f26; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f26; dest:f25; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f23; dest:f24; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f24; dest:f23; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f21; dest:f22; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f22; dest:f21; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f19; dest:f20; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f20; dest:f19; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f17; dest:f18; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f18; dest:f17; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f15; dest:f16; op1val:0x4effffff; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f16; dest:f15; op1val:0x4effffff; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f13; dest:f14; op1val:0x4effffff; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f14; dest:f13; op1val:0x4effffff; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f11; dest:f12; op1val:0x4effffff; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f12; dest:f11; op1val:0x4f000000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f9; dest:f10; op1val:0x4f000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f10; dest:f9; op1val:0x4f000000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f7; dest:f8; op1val:0x4f000000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f8; dest:f7; op1val:0x4f000000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f5; dest:f6; op1val:0x4f000001; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f6; dest:f5; op1val:0x4f000001; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f3; dest:f4; op1val:0x4f000001; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f4; dest:f3; op1val:0x4f000001; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f1; dest:f2; op1val:0x4f000001; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f2; dest:f1; op1val:0x4f000002; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f0; dest:f31; op1val:0x4f000002; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f0; op1val:0x4f000002; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000002; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000002; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 90*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b24-01.S b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b24-01.S new file mode 100644 index 000000000..5b3acb3ec --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b24-01.S @@ -0,0 +1,929 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:32 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.bf16.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.bf16.s instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.bf16.s_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfbfmin,RV64IF_Zicsr_Zfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfbfmin.*);def TEST_CASE_1=True;",fcvt.bf16.s_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f29; dest:f29; op1val:0xbf666666; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f30; op1val:0xbf666666; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f27; dest:f28; op1val:0xbf666666; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f28; dest:f27; op1val:0xbf666666; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f25; dest:f26; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f26; dest:f25; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f23; dest:f24; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f24; dest:f23; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f21; dest:f22; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f22; dest:f21; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f19; dest:f20; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f20; dest:f19; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f17; dest:f18; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f18; dest:f17; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f15; dest:f16; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f16; dest:f15; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f13; dest:f14; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f14; dest:f13; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f11; dest:f12; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f12; dest:f11; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f9; dest:f10; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f10; dest:f9; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f7; dest:f8; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f8; dest:f7; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f5; dest:f6; op1val:0x3f666666; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f6; dest:f5; op1val:0x3f666666; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f3; dest:f4; op1val:0x3f666666; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f4; dest:f3; op1val:0x3f666666; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f1; dest:f2; op1val:0x3f666666; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f2; dest:f1; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f0; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f0; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f0; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f0; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f0; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f0; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f0; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:45*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:47*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 47*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:49*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 49*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:51*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:53*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 53*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:55*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 55*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:57*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:59*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 59*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:61*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 61*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:63*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:65*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 65*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:67*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 67*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:69*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:71*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 71*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:73*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 73*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:75*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:77*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 77*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:79*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 79*FLEN/8, x4, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:80*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 80*FLEN/8, x4, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:81*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 81*FLEN/8, x4, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:82*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 82*FLEN/8, x4, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:83*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 83*FLEN/8, x4, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:84*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 84*FLEN/8, x4, x1, x2) + +inst_85: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:85*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 85*FLEN/8, x4, x1, x2) + +inst_86: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:86*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 86*FLEN/8, x4, x1, x2) + +inst_87: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:87*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 87*FLEN/8, x4, x1, x2) + +inst_88: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:88*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 88*FLEN/8, x4, x1, x2) + +inst_89: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:89*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 89*FLEN/8, x4, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:90*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 90*FLEN/8, x4, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:91*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 91*FLEN/8, x4, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:92*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 92*FLEN/8, x4, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:93*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 93*FLEN/8, x4, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:94*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 94*FLEN/8, x4, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:95*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 95*FLEN/8, x4, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:96*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 96*FLEN/8, x4, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:97*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 97*FLEN/8, x4, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:98*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 98*FLEN/8, x4, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:99*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 99*FLEN/8, x4, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:100*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 100*FLEN/8, x4, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:101*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 101*FLEN/8, x4, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:102*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 102*FLEN/8, x4, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:103*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 103*FLEN/8, x4, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:104*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 104*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 210*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b27-01.S b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b27-01.S new file mode 100644 index 000000000..519101ff5 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b27-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:32 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.bf16.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.bf16.s instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.bf16.s_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfbfmin,RV64IF_Zicsr_Zfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfbfmin.*);def TEST_CASE_1=True;",fcvt.bf16.s_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800001; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f29; dest:f29; op1val:0xff800001; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f30; op1val:0x7faaaaaa; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f27; dest:f28; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f28; dest:f27; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f25; dest:f26; op1val:0xffc00001; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f26; dest:f25; op1val:0x7fc55555; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f23; dest:f24; op1val:0xffc55555; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.bf16.s ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.bf16.s ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.bf16.s ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.bf16.s ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.bf16.s ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.bf16.s ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.bf16.s ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.bf16.s ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.bf16.s ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.bf16.s ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.bf16.s ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.bf16.s ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.bf16.s ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.bf16.s ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.bf16.s ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.bf16.s ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.bf16.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.bf16.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.bf16.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.bf16.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.bf16.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.bf16.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.bf16.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.bf16.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.bf16.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(4286578689,32,FLEN) +NAN_BOXED(2141891242,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(4290772993,32,FLEN) +NAN_BOXED(2143638869,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b28-01.S b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b28-01.S new file mode 100644 index 000000000..8ad5f99ba --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b28-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:32 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.bf16.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.bf16.s instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.bf16.s_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfbfmin,RV64IF_Zicsr_Zfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfbfmin.*);def TEST_CASE_1=True;",fcvt.bf16.s_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x7e and fm1 == 0x124770 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f29; dest:f29; op1val:0x3f124770; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f30; op1val:0x3f800000; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x7f and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f27; dest:f28; op1val:0x3fa00000; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x7f and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f28; dest:f27; op1val:0x3fc00000; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x7f and fm1 == 0x600000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f25; dest:f26; op1val:0x3fe00000; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x80 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f26; dest:f25; op1val:0x40000000; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x80 and fm1 == 0x100000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f23; dest:f24; op1val:0x40100000; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x80 and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f24; dest:f23; op1val:0x40200000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x80 and fm1 == 0x300000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f21; dest:f22; op1val:0x40300000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x9c and fm1 == 0x5b9758 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f22; dest:f21; op1val:0x4e5b9758; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f19; dest:f20; op1val:0x4effffff; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f20; dest:f19; op1val:0x7f800000; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f17; dest:f18; op1val:0x7f800001; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f18; dest:f17; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f15; dest:f16; op1val:0x80000000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x7d and fm1 == 0x58046a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f16; dest:f15; op1val:0xbed8046a; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f13; dest:f14; op1val:0xbf800000; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x80 and fm1 == 0x300000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f14; dest:f13; op1val:0xc0300000; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x80 and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f11; dest:f12; op1val:0xc0200000; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x80 and fm1 == 0x100000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f12; dest:f11; op1val:0xc0100000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x80 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f9; dest:f10; op1val:0xc0000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x7f and fm1 == 0x600000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f10; dest:f9; op1val:0xbfe00000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f7; dest:f8; op1val:0xbfc00000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x7f and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f8; dest:f7; op1val:0xbfa00000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x9d and fm1 == 0x4b3d25 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f5; dest:f6; op1val:0xcecb3d25; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f6; dest:f5; op1val:0xcf000000; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f3; dest:f4; op1val:0xff800000; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.bf16.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.bf16.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.bf16.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.bf16.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.bf16.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1058162544,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1067450368,32,FLEN) +NAN_BOXED(1069547520,32,FLEN) +NAN_BOXED(1071644672,32,FLEN) +NAN_BOXED(1073741824,32,FLEN) +NAN_BOXED(1074790400,32,FLEN) +NAN_BOXED(1075838976,32,FLEN) +NAN_BOXED(1076887552,32,FLEN) +NAN_BOXED(1314625368,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(3201827946,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3224371200,32,FLEN) +NAN_BOXED(3223322624,32,FLEN) +NAN_BOXED(3222274048,32,FLEN) +NAN_BOXED(3221225472,32,FLEN) +NAN_BOXED(3219128320,32,FLEN) +NAN_BOXED(3217031168,32,FLEN) +NAN_BOXED(3214934016,32,FLEN) +NAN_BOXED(3469425957,32,FLEN) +NAN_BOXED(3472883712,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b29-01.S b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b29-01.S new file mode 100644 index 000000000..4b09ef384 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.bf16.s_b29-01.S @@ -0,0 +1,729 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:32 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.bf16.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.bf16.s instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.bf16.s_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfbfmin,RV64IF_Zicsr_Zfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfbfmin.*);def TEST_CASE_1=True;",fcvt.bf16.s_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f29; dest:f29; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f30; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f27; dest:f28; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f28; dest:f27; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f25; dest:f26; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f26; dest:f25; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f23; dest:f24; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f24; dest:f23; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f21; dest:f22; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f22; dest:f21; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f19; dest:f20; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f20; dest:f19; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f17; dest:f18; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f18; dest:f17; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f15; dest:f16; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f16; dest:f15; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f13; dest:f14; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f14; dest:f13; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f11; dest:f12; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f12; dest:f11; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f9; dest:f10; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f10; dest:f9; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f7; dest:f8; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f8; dest:f7; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f5; dest:f6; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f6; dest:f5; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f3; dest:f4; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f4; dest:f3; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f1; dest:f2; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f2; dest:f1; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f0; dest:f31; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f0; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:45*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:47*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 47*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:49*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 49*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:51*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:53*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 53*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:55*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 55*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:57*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:59*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 59*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:61*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 61*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:63*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:65*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 65*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:67*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 67*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:69*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:71*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 71*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:73*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 73*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:75*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 32, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:77*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 64, 0, x3, 77*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 96, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:79*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.bf16.s, f31, f30, 128, 0, x3, 79*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 160*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.s.bf16_b1-01.S b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.s.bf16_b1-01.S new file mode 100644 index 000000000..bdf7a0999 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfbfmin/src/fcvt.s.bf16_b1-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:22 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.s.bf16.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.bf16 instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.s.bf16_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfbfmin,RV64IF_Zicsr_Zfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfbfmin.*);def TEST_CASE_1=True;",fcvt.s.bf16_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fcvt.s.bf16, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f29; dest:f30; op1val:0x0; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP(fcvt.s.bf16, f30, f29, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f30; dest:f29; op1val:0x0; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP(fcvt.s.bf16, f29, f30, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f27; dest:f28; op1val:0x0; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP(fcvt.s.bf16, f28, f27, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f28; dest:f27; op1val:0x0; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP(fcvt.s.bf16, f27, f28, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f25; dest:f26; op1val:0x8000; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fcvt.s.bf16, f26, f25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f26; dest:f25; op1val:0x8000; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP(fcvt.s.bf16, f25, f26, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f23; dest:f24; op1val:0x8000; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP(fcvt.s.bf16, f24, f23, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f24; dest:f23; op1val:0x8000; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP(fcvt.s.bf16, f23, f24, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f21; dest:f22; op1val:0x8000; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP(fcvt.s.bf16, f22, f21, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f22; dest:f21; op1val:0x1; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fcvt.s.bf16, f21, f22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f19; dest:f20; op1val:0x1; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP(fcvt.s.bf16, f20, f19, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f20; dest:f19; op1val:0x1; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP(fcvt.s.bf16, f19, f20, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f17; dest:f18; op1val:0x1; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP(fcvt.s.bf16, f18, f17, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f18; dest:f17; op1val:0x1; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP(fcvt.s.bf16, f17, f18, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f15; dest:f16; op1val:0x8001; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fcvt.s.bf16, f16, f15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f16; dest:f15; op1val:0x8001; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP(fcvt.s.bf16, f15, f16, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f13; dest:f14; op1val:0x8001; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP(fcvt.s.bf16, f14, f13, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f14; dest:f13; op1val:0x8001; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP(fcvt.s.bf16, f13, f14, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f11; dest:f12; op1val:0x8001; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP(fcvt.s.bf16, f12, f11, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f12; dest:f11; op1val:0x2; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fcvt.s.bf16, f11, f12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f9; dest:f10; op1val:0x2; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP(fcvt.s.bf16, f10, f9, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f10; dest:f9; op1val:0x2; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP(fcvt.s.bf16, f9, f10, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f7; dest:f8; op1val:0x2; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP(fcvt.s.bf16, f8, f7, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f8; dest:f7; op1val:0x2; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP(fcvt.s.bf16, f7, f8, dyn, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f5; dest:f6; op1val:0x807e; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fcvt.s.bf16, f6, f5, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f6; dest:f5; op1val:0x807e; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP(fcvt.s.bf16, f5, f6, dyn, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f3; dest:f4; op1val:0x807e; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP(fcvt.s.bf16, f4, f3, dyn, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f4; dest:f3; op1val:0x807e; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP(fcvt.s.bf16, f3, f4, dyn, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f1; dest:f2; op1val:0x807e; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP(fcvt.s.bf16, f2, f1, dyn, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f2; dest:f1; op1val:0x7f; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP(fcvt.s.bf16, f1, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f0; dest:f31; op1val:0x7f; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP(fcvt.s.bf16, f31, f0, dyn, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f31; dest:f0; op1val:0x7f; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP(fcvt.s.bf16, f0, f31, dyn, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(127,16,FLEN) +NAN_BOXED(127,16,FLEN) +NAN_BOXED(127,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b1-01.S b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b1-01.S new file mode 100644 index 000000000..4bda61061 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b1-01.S @@ -0,0 +1,1254 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:32 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.bf16.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.bf16.s instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.bf16.s_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zvfbfmin,RV64IF_Zicsr_Zvfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zvfbfmin.*);def TEST_CASE_1=True;",vfncvtbf16.f.f.w_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f29; dest:f29; op1val:0x0; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f30; op1val:0x0; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f27; dest:f28; op1val:0x0; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f28; dest:f27; op1val:0x0; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f25; dest:f26; op1val:0x80000000; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f26; dest:f25; op1val:0x80000000; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f23; dest:f24; op1val:0x80000000; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f24; dest:f23; op1val:0x80000000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f21; dest:f22; op1val:0x80000000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f22; dest:f21; op1val:0x1; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f19; dest:f20; op1val:0x1; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f20; dest:f19; op1val:0x1; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f17; dest:f18; op1val:0x1; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f18; dest:f17; op1val:0x1; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f15; dest:f16; op1val:0x80000001; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f16; dest:f15; op1val:0x80000001; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f13; dest:f14; op1val:0x80000001; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f14; dest:f13; op1val:0x80000001; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f11; dest:f12; op1val:0x80000001; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f12; dest:f11; op1val:0x2; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f9; dest:f10; op1val:0x2; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f10; dest:f9; op1val:0x2; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f7; dest:f8; op1val:0x2; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f8; dest:f7; op1val:0x2; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f5; dest:f6; op1val:0x807ffffe; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f6; dest:f5; op1val:0x807ffffe; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f3; dest:f4; op1val:0x807ffffe; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f4; dest:f3; op1val:0x807ffffe; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f1; dest:f2; op1val:0x807ffffe; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f2; dest:f1; op1val:0x7fffff; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f0; dest:f31; op1val:0x7fffff; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f0; op1val:0x7fffff; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fffff; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fffff; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x807fffff; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x807fffff; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x807fffff; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x807fffff; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x807fffff; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800000; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800000; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800000; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800000; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800000; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80800000; valaddr_reg:x3; +val_offset:45*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80800000; valaddr_reg:x3; +val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80800000; valaddr_reg:x3; +val_offset:47*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 47*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80800000; valaddr_reg:x3; +val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80800000; valaddr_reg:x3; +val_offset:49*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 49*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800001; valaddr_reg:x3; +val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800001; valaddr_reg:x3; +val_offset:51*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800001; valaddr_reg:x3; +val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800001; valaddr_reg:x3; +val_offset:53*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 53*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x800001; valaddr_reg:x3; +val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80855555; valaddr_reg:x3; +val_offset:55*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 55*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80855555; valaddr_reg:x3; +val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80855555; valaddr_reg:x3; +val_offset:57*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80855555; valaddr_reg:x3; +val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x80855555; valaddr_reg:x3; +val_offset:59*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 59*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f8001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f8001; valaddr_reg:x3; +val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f8001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f8001; valaddr_reg:x3; +val_offset:61*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 61*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f8001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f8001; valaddr_reg:x3; +val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f8001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f8001; valaddr_reg:x3; +val_offset:63*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f8001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f8001; valaddr_reg:x3; +val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f0001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f0001; valaddr_reg:x3; +val_offset:65*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 65*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f0001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f0001; valaddr_reg:x3; +val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f0001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f0001; valaddr_reg:x3; +val_offset:67*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 67*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f0001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f0001; valaddr_reg:x3; +val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7f0001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7f0001; valaddr_reg:x3; +val_offset:69*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550000; valaddr_reg:x3; +val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550000; valaddr_reg:x3; +val_offset:71*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 71*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550000; valaddr_reg:x3; +val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550000; valaddr_reg:x3; +val_offset:73*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 73*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550000; valaddr_reg:x3; +val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550001; valaddr_reg:x3; +val_offset:75*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550001; valaddr_reg:x3; +val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550001; valaddr_reg:x3; +val_offset:77*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 77*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550001; valaddr_reg:x3; +val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x550001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x550001; valaddr_reg:x3; +val_offset:79*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 79*FLEN/8, x4, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f8000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f8000; valaddr_reg:x3; +val_offset:80*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 80*FLEN/8, x4, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f8000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f8000; valaddr_reg:x3; +val_offset:81*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 81*FLEN/8, x4, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f8000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f8000; valaddr_reg:x3; +val_offset:82*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 82*FLEN/8, x4, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f8000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f8000; valaddr_reg:x3; +val_offset:83*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 83*FLEN/8, x4, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f8000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f8000; valaddr_reg:x3; +val_offset:84*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 84*FLEN/8, x4, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7fffff; valaddr_reg:x3; +val_offset:85*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 85*FLEN/8, x4, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7fffff; valaddr_reg:x3; +val_offset:86*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 86*FLEN/8, x4, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7fffff; valaddr_reg:x3; +val_offset:87*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 87*FLEN/8, x4, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7fffff; valaddr_reg:x3; +val_offset:88*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 88*FLEN/8, x4, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f7fffff; valaddr_reg:x3; +val_offset:89*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 89*FLEN/8, x4, x1, x2) + +inst_90: +// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff7fffff; valaddr_reg:x3; +val_offset:90*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 90*FLEN/8, x4, x1, x2) + +inst_91: +// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff7fffff; valaddr_reg:x3; +val_offset:91*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 91*FLEN/8, x4, x1, x2) + +inst_92: +// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff7fffff; valaddr_reg:x3; +val_offset:92*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 92*FLEN/8, x4, x1, x2) + +inst_93: +// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff7fffff; valaddr_reg:x3; +val_offset:93*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 93*FLEN/8, x4, x1, x2) + +inst_94: +// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff7fffff; valaddr_reg:x3; +val_offset:94*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 94*FLEN/8, x4, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800000; valaddr_reg:x3; +val_offset:95*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 95*FLEN/8, x4, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800000; valaddr_reg:x3; +val_offset:96*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 96*FLEN/8, x4, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800000; valaddr_reg:x3; +val_offset:97*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 97*FLEN/8, x4, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800000; valaddr_reg:x3; +val_offset:98*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 98*FLEN/8, x4, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800000; valaddr_reg:x3; +val_offset:99*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 99*FLEN/8, x4, x1, x2) + +inst_100: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff800000; valaddr_reg:x3; +val_offset:100*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 100*FLEN/8, x4, x1, x2) + +inst_101: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff800000; valaddr_reg:x3; +val_offset:101*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 101*FLEN/8, x4, x1, x2) + +inst_102: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff800000; valaddr_reg:x3; +val_offset:102*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 102*FLEN/8, x4, x1, x2) + +inst_103: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff800000; valaddr_reg:x3; +val_offset:103*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 103*FLEN/8, x4, x1, x2) + +inst_104: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xff800000; valaddr_reg:x3; +val_offset:104*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 104*FLEN/8, x4, x1, x2) + +inst_105: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00000; valaddr_reg:x3; +val_offset:105*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 105*FLEN/8, x4, x1, x2) + +inst_106: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00000; valaddr_reg:x3; +val_offset:106*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 106*FLEN/8, x4, x1, x2) + +inst_107: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00000; valaddr_reg:x3; +val_offset:107*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 107*FLEN/8, x4, x1, x2) + +inst_108: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00000; valaddr_reg:x3; +val_offset:108*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 108*FLEN/8, x4, x1, x2) + +inst_109: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00000; valaddr_reg:x3; +val_offset:109*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 109*FLEN/8, x4, x1, x2) + +inst_110: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc00000; valaddr_reg:x3; +val_offset:110*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 110*FLEN/8, x4, x1, x2) + +inst_111: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc00000; valaddr_reg:x3; +val_offset:111*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 111*FLEN/8, x4, x1, x2) + +inst_112: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc00000; valaddr_reg:x3; +val_offset:112*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 112*FLEN/8, x4, x1, x2) + +inst_113: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc00000; valaddr_reg:x3; +val_offset:113*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 113*FLEN/8, x4, x1, x2) + +inst_114: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc00000; valaddr_reg:x3; +val_offset:114*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 114*FLEN/8, x4, x1, x2) + +inst_115: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:115*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 115*FLEN/8, x4, x1, x2) + +inst_116: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:116*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 116*FLEN/8, x4, x1, x2) + +inst_117: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:117*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 117*FLEN/8, x4, x1, x2) + +inst_118: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:118*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 118*FLEN/8, x4, x1, x2) + +inst_119: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:119*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 119*FLEN/8, x4, x1, x2) + +inst_120: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc55555; valaddr_reg:x3; +val_offset:120*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 120*FLEN/8, x4, x1, x2) + +inst_121: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc55555; valaddr_reg:x3; +val_offset:121*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 121*FLEN/8, x4, x1, x2) + +inst_122: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc55555; valaddr_reg:x3; +val_offset:122*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 122*FLEN/8, x4, x1, x2) + +inst_123: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc55555; valaddr_reg:x3; +val_offset:123*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 123*FLEN/8, x4, x1, x2) + +inst_124: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffc55555; valaddr_reg:x3; +val_offset:124*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 124*FLEN/8, x4, x1, x2) + +inst_125: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800001; valaddr_reg:x3; +val_offset:125*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 125*FLEN/8, x4, x1, x2) + +inst_126: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800001; valaddr_reg:x3; +val_offset:126*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 126*FLEN/8, x4, x1, x2) + +inst_127: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800001; valaddr_reg:x3; +val_offset:127*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 127*FLEN/8, x4, x1, x2) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_128: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800001; valaddr_reg:x3; +val_offset:128*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 128*FLEN/8, x4, x1, x2) + +inst_129: +// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800001; valaddr_reg:x3; +val_offset:129*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 129*FLEN/8, x4, x1, x2) + +inst_130: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:130*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 130*FLEN/8, x4, x1, x2) + +inst_131: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:131*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 131*FLEN/8, x4, x1, x2) + +inst_132: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:132*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 132*FLEN/8, x4, x1, x2) + +inst_133: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:133*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 133*FLEN/8, x4, x1, x2) + +inst_134: +// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:134*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 134*FLEN/8, x4, x1, x2) + +inst_135: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:135*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 135*FLEN/8, x4, x1, x2) + +inst_136: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:136*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 136*FLEN/8, x4, x1, x2) + +inst_137: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:137*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 137*FLEN/8, x4, x1, x2) + +inst_138: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:138*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 138*FLEN/8, x4, x1, x2) + +inst_139: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:139*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 139*FLEN/8, x4, x1, x2) + +inst_140: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:140*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 140*FLEN/8, x4, x1, x2) + +inst_141: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:141*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 141*FLEN/8, x4, x1, x2) + +inst_142: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:142*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 142*FLEN/8, x4, x1, x2) + +inst_143: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:143*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 143*FLEN/8, x4, x1, x2) + +inst_144: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:144*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 144*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(2147483649,32,FLEN) +NAN_BOXED(2147483649,32,FLEN) +NAN_BOXED(2147483649,32,FLEN) +NAN_BOXED(2147483649,32,FLEN) +NAN_BOXED(2147483649,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(2155872254,32,FLEN) +NAN_BOXED(2155872254,32,FLEN) +NAN_BOXED(2155872254,32,FLEN) +NAN_BOXED(2155872254,32,FLEN) +NAN_BOXED(2155872254,32,FLEN) +NAN_BOXED(8388607,32,FLEN) +NAN_BOXED(8388607,32,FLEN) +NAN_BOXED(8388607,32,FLEN) +NAN_BOXED(8388607,32,FLEN) +NAN_BOXED(8388607,32,FLEN) +NAN_BOXED(2155872255,32,FLEN) +NAN_BOXED(2155872255,32,FLEN) +NAN_BOXED(2155872255,32,FLEN) +NAN_BOXED(2155872255,32,FLEN) +NAN_BOXED(2155872255,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(2155872256,32,FLEN) +NAN_BOXED(2155872256,32,FLEN) +NAN_BOXED(2155872256,32,FLEN) +NAN_BOXED(2155872256,32,FLEN) +NAN_BOXED(2155872256,32,FLEN) +NAN_BOXED(8388609,32,FLEN) +NAN_BOXED(8388609,32,FLEN) +NAN_BOXED(8388609,32,FLEN) +NAN_BOXED(8388609,32,FLEN) +NAN_BOXED(8388609,32,FLEN) +NAN_BOXED(2156221781,32,FLEN) +NAN_BOXED(2156221781,32,FLEN) +NAN_BOXED(2156221781,32,FLEN) +NAN_BOXED(2156221781,32,FLEN) +NAN_BOXED(2156221781,32,FLEN) +NAN_BOXED(2139062273,32,FLEN) +NAN_BOXED(2139062273,32,FLEN) +NAN_BOXED(2139062273,32,FLEN) +NAN_BOXED(2139062273,32,FLEN) +NAN_BOXED(2139062273,32,FLEN) +NAN_BOXED(2139029505,32,FLEN) +NAN_BOXED(2139029505,32,FLEN) +NAN_BOXED(2139029505,32,FLEN) +NAN_BOXED(2139029505,32,FLEN) +NAN_BOXED(2139029505,32,FLEN) +NAN_BOXED(5570560,32,FLEN) +NAN_BOXED(5570560,32,FLEN) +NAN_BOXED(5570560,32,FLEN) +NAN_BOXED(5570560,32,FLEN) +NAN_BOXED(5570560,32,FLEN) +NAN_BOXED(5570561,32,FLEN) +NAN_BOXED(5570561,32,FLEN) +NAN_BOXED(5570561,32,FLEN) +NAN_BOXED(5570561,32,FLEN) +NAN_BOXED(5570561,32,FLEN) +NAN_BOXED(8355840,32,FLEN) +NAN_BOXED(8355840,32,FLEN) +NAN_BOXED(8355840,32,FLEN) +NAN_BOXED(8355840,32,FLEN) +NAN_BOXED(8355840,32,FLEN) +NAN_BOXED(2139095039,32,FLEN) +NAN_BOXED(2139095039,32,FLEN) +NAN_BOXED(2139095039,32,FLEN) +NAN_BOXED(2139095039,32,FLEN) +NAN_BOXED(2139095039,32,FLEN) +NAN_BOXED(4286578687,32,FLEN) +NAN_BOXED(4286578687,32,FLEN) +NAN_BOXED(4286578687,32,FLEN) +NAN_BOXED(4286578687,32,FLEN) +NAN_BOXED(4286578687,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(2143289344,32,FLEN) +NAN_BOXED(2143289344,32,FLEN) +NAN_BOXED(2143289344,32,FLEN) +NAN_BOXED(2143289344,32,FLEN) +NAN_BOXED(2143289344,32,FLEN) +NAN_BOXED(4290772992,32,FLEN) +NAN_BOXED(4290772992,32,FLEN) +NAN_BOXED(4290772992,32,FLEN) +NAN_BOXED(4290772992,32,FLEN) +NAN_BOXED(4290772992,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 256*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 34*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b22-01.S b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b22-01.S new file mode 100644 index 000000000..ddca94266 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b22-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:32 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.bf16.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.bf16.s instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.bf16.s_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zvfbfmin,RV64IF_Zicsr_Zvfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zvfbfmin.*);def TEST_CASE_1=True;",vfncvtbf16.f.f.w_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x7d and fm1 == 0x36e5d6 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f29; dest:f29; op1val:0x3eb6e5d6; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x7e and fm1 == 0x49fee5 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f30; op1val:0x3f49fee5; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x7f and fm1 == 0x1a616d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f27; dest:f28; op1val:0x3f9a616d; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x80 and fm1 == 0x681ae9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f28; dest:f27; op1val:0x40681ae9; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x81 and fm1 == 0x696b5c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f25; dest:f26; op1val:0x40e96b5c; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x67 and fm1 == 0x53a4fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f26; dest:f25; op1val:0x33d3a4fc; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0xc4 and fm1 == 0x046756 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f23; dest:f24; op1val:0x62046756; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.bf16.s ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.bf16.s ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.bf16.s ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.bf16.s ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.bf16.s ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.bf16.s ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.bf16.s ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.bf16.s ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.bf16.s ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.bf16.s ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.bf16.s ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.bf16.s ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.bf16.s ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.bf16.s ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.bf16.s ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.bf16.s ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.bf16.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.bf16.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.bf16.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.bf16.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.bf16.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.bf16.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.bf16.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.bf16.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.bf16.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1052173782,32,FLEN) +NAN_BOXED(1061813989,32,FLEN) +NAN_BOXED(1067082093,32,FLEN) +NAN_BOXED(1080564457,32,FLEN) +NAN_BOXED(1089039196,32,FLEN) +NAN_BOXED(869508348,32,FLEN) +NAN_BOXED(1644455766,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b23-01.S b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b23-01.S new file mode 100644 index 000000000..f89c64d2e --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b23-01.S @@ -0,0 +1,449 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:32 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.bf16.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.bf16.s instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.bf16.s_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zvfbfmin,RV64IF_Zicsr_Zvfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zvfbfmin.*);def TEST_CASE_1=True;",vfncvtbf16.f.f.w_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f29; dest:f29; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f30; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f27; dest:f28; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f28; dest:f27; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f25; dest:f26; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f26; dest:f25; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f23; dest:f24; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f24; dest:f23; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f21; dest:f22; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f22; dest:f21; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f19; dest:f20; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f20; dest:f19; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f17; dest:f18; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f18; dest:f17; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f15; dest:f16; op1val:0x4effffff; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f16; dest:f15; op1val:0x4effffff; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f13; dest:f14; op1val:0x4effffff; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f14; dest:f13; op1val:0x4effffff; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f11; dest:f12; op1val:0x4effffff; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f12; dest:f11; op1val:0x4f000000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f9; dest:f10; op1val:0x4f000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f10; dest:f9; op1val:0x4f000000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f7; dest:f8; op1val:0x4f000000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f8; dest:f7; op1val:0x4f000000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f5; dest:f6; op1val:0x4f000001; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f6; dest:f5; op1val:0x4f000001; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f3; dest:f4; op1val:0x4f000001; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f4; dest:f3; op1val:0x4f000001; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f1; dest:f2; op1val:0x4f000001; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f2; dest:f1; op1val:0x4f000002; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f0; dest:f31; op1val:0x4f000002; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f0; op1val:0x4f000002; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000002; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000002; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 90*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b24-01.S b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b24-01.S new file mode 100644 index 000000000..19bb1df3e --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b24-01.S @@ -0,0 +1,929 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:32 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.bf16.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.bf16.s instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.bf16.s_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zvfbfmin,RV64IF_Zicsr_Zvfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zvfbfmin.*);def TEST_CASE_1=True;",vfncvtbf16.f.f.w_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f29; dest:f29; op1val:0xbf666666; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f30; op1val:0xbf666666; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f27; dest:f28; op1val:0xbf666666; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f28; dest:f27; op1val:0xbf666666; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f25; dest:f26; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f26; dest:f25; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f23; dest:f24; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f24; dest:f23; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f21; dest:f22; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f22; dest:f21; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f19; dest:f20; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f20; dest:f19; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f17; dest:f18; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f18; dest:f17; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f15; dest:f16; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f16; dest:f15; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f13; dest:f14; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f14; dest:f13; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f11; dest:f12; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f12; dest:f11; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f9; dest:f10; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f10; dest:f9; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f7; dest:f8; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f8; dest:f7; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f5; dest:f6; op1val:0x3f666666; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f6; dest:f5; op1val:0x3f666666; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f3; dest:f4; op1val:0x3f666666; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f4; dest:f3; op1val:0x3f666666; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f1; dest:f2; op1val:0x3f666666; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f2; dest:f1; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f0; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f0; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f0; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f0; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f0; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f0; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f0; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:45*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:47*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 47*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:49*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 49*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:51*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:53*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 53*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:55*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 55*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:57*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:59*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 59*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:61*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 61*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:63*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:65*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 65*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:67*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 67*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:69*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:71*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 71*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:73*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 73*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:75*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:77*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 77*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:79*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 79*FLEN/8, x4, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:80*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 80*FLEN/8, x4, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:81*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 81*FLEN/8, x4, x1, x2) + +inst_82: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:82*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 82*FLEN/8, x4, x1, x2) + +inst_83: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:83*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 83*FLEN/8, x4, x1, x2) + +inst_84: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:84*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 84*FLEN/8, x4, x1, x2) + +inst_85: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:85*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 85*FLEN/8, x4, x1, x2) + +inst_86: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:86*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 86*FLEN/8, x4, x1, x2) + +inst_87: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:87*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 87*FLEN/8, x4, x1, x2) + +inst_88: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:88*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 88*FLEN/8, x4, x1, x2) + +inst_89: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:89*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 89*FLEN/8, x4, x1, x2) + +inst_90: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:90*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 90*FLEN/8, x4, x1, x2) + +inst_91: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:91*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 91*FLEN/8, x4, x1, x2) + +inst_92: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:92*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 92*FLEN/8, x4, x1, x2) + +inst_93: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:93*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 93*FLEN/8, x4, x1, x2) + +inst_94: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:94*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 94*FLEN/8, x4, x1, x2) + +inst_95: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:95*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 95*FLEN/8, x4, x1, x2) + +inst_96: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:96*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 96*FLEN/8, x4, x1, x2) + +inst_97: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:97*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 97*FLEN/8, x4, x1, x2) + +inst_98: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:98*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 98*FLEN/8, x4, x1, x2) + +inst_99: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:99*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 99*FLEN/8, x4, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:100*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 100*FLEN/8, x4, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:101*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 101*FLEN/8, x4, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:102*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 102*FLEN/8, x4, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:103*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 103*FLEN/8, x4, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:104*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 104*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 210*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b27-01.S b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b27-01.S new file mode 100644 index 000000000..a70021e72 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b27-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:32 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.bf16.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.bf16.s instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.bf16.s_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zvfbfmin,RV64IF_Zicsr_Zvfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zvfbfmin.*);def TEST_CASE_1=True;",vfncvtbf16.f.f.w_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x7f800001; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f29; dest:f29; op1val:0xff800001; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f30; op1val:0x7faaaaaa; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f27; dest:f28; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f28; dest:f27; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f25; dest:f26; op1val:0xffc00001; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f26; dest:f25; op1val:0x7fc55555; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f23; dest:f24; op1val:0xffc55555; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.bf16.s ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.bf16.s ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.bf16.s ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.bf16.s ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.bf16.s ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.bf16.s ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.bf16.s ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.bf16.s ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.bf16.s ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.bf16.s ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.bf16.s ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.bf16.s ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.bf16.s ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.bf16.s ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.bf16.s ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.bf16.s ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.bf16.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.bf16.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.bf16.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.bf16.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.bf16.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.bf16.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.bf16.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.bf16.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.bf16.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(4286578689,32,FLEN) +NAN_BOXED(2141891242,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(4290772993,32,FLEN) +NAN_BOXED(2143638869,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b28-01.S b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b28-01.S new file mode 100644 index 000000000..8a260a596 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b28-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:32 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.bf16.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.bf16.s instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.bf16.s_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zvfbfmin,RV64IF_Zicsr_Zvfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zvfbfmin.*);def TEST_CASE_1=True;",vfncvtbf16.f.f.w_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x7e and fm1 == 0x124770 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f29; dest:f29; op1val:0x3f124770; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f30; op1val:0x3f800000; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x7f and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f27; dest:f28; op1val:0x3fa00000; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x7f and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f28; dest:f27; op1val:0x3fc00000; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x7f and fm1 == 0x600000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f25; dest:f26; op1val:0x3fe00000; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x80 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f26; dest:f25; op1val:0x40000000; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x80 and fm1 == 0x100000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f23; dest:f24; op1val:0x40100000; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x80 and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f24; dest:f23; op1val:0x40200000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x80 and fm1 == 0x300000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f21; dest:f22; op1val:0x40300000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x9c and fm1 == 0x5b9758 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f22; dest:f21; op1val:0x4e5b9758; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f19; dest:f20; op1val:0x4effffff; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f20; dest:f19; op1val:0x7f800000; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f17; dest:f18; op1val:0x7f800001; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f18; dest:f17; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f15; dest:f16; op1val:0x80000000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x7d and fm1 == 0x58046a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f16; dest:f15; op1val:0xbed8046a; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f13; dest:f14; op1val:0xbf800000; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x80 and fm1 == 0x300000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f14; dest:f13; op1val:0xc0300000; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x80 and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f11; dest:f12; op1val:0xc0200000; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x80 and fm1 == 0x100000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f12; dest:f11; op1val:0xc0100000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x80 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f9; dest:f10; op1val:0xc0000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x7f and fm1 == 0x600000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f10; dest:f9; op1val:0xbfe00000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f7; dest:f8; op1val:0xbfc00000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x7f and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f8; dest:f7; op1val:0xbfa00000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x9d and fm1 == 0x4b3d25 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f5; dest:f6; op1val:0xcecb3d25; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f6; dest:f5; op1val:0xcf000000; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f3; dest:f4; op1val:0xff800000; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.bf16.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.bf16.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.bf16.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.bf16.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.bf16.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1058162544,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1067450368,32,FLEN) +NAN_BOXED(1069547520,32,FLEN) +NAN_BOXED(1071644672,32,FLEN) +NAN_BOXED(1073741824,32,FLEN) +NAN_BOXED(1074790400,32,FLEN) +NAN_BOXED(1075838976,32,FLEN) +NAN_BOXED(1076887552,32,FLEN) +NAN_BOXED(1314625368,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(3201827946,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3224371200,32,FLEN) +NAN_BOXED(3223322624,32,FLEN) +NAN_BOXED(3222274048,32,FLEN) +NAN_BOXED(3221225472,32,FLEN) +NAN_BOXED(3219128320,32,FLEN) +NAN_BOXED(3217031168,32,FLEN) +NAN_BOXED(3214934016,32,FLEN) +NAN_BOXED(3469425957,32,FLEN) +NAN_BOXED(3472883712,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b29-01.S b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b29-01.S new file mode 100644 index 000000000..d22e59f7b --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfncvtbf16.f.f.w_b29-01.S @@ -0,0 +1,729 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:32 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.bf16.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.bf16.s instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.bf16.s_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zvfbfmin,RV64IF_Zicsr_Zvfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zvfbfmin.*);def TEST_CASE_1=True;",vfncvtbf16.f.f.w_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f29; dest:f29; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f30; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f27; dest:f28; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f28; dest:f27; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f25; dest:f26; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f26; dest:f25; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f23; dest:f24; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f24; dest:f23; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f21; dest:f22; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f22; dest:f21; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f19; dest:f20; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f20; dest:f19; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f17; dest:f18; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f18; dest:f17; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f15; dest:f16; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f16; dest:f15; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f13; dest:f14; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f14; dest:f13; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f11; dest:f12; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f12; dest:f11; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f9; dest:f10; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f10; dest:f9; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f7; dest:f8; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f8; dest:f7; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f5; dest:f6; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f6; dest:f5; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f3; dest:f4; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f4; dest:f3; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f1; dest:f2; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f2; dest:f1; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f0; dest:f31; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f31; dest:f0; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:45*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:47*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 47*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:49*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 49*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:51*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:53*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 53*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:55*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 55*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:57*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:59*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 59*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:61*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 61*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:63*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:65*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 65*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:67*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 67*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:69*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:71*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 71*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:73*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 73*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:75*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 32, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:77*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 64, 0, x3, 77*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 96, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffff +/* opcode: fcvt.bf16.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:79*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM_V32_16(vfncvtbf16.f.f.w, f31, f30, 128, 0, x3, 79*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 160*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfwcvtbf16.f.f.v_b1-01.S b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfwcvtbf16.f.f.v_b1-01.S new file mode 100644 index 000000000..136833373 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvfbfmin/src/vfwcvtbf16.f.f.v_b1-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:22 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.s.bf16.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.bf16 instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.s.bf16_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zvfbfmin,RV64IF_Zicsr_Zvfbfmin") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zvfbfmin.*);def TEST_CASE_1=True;",vfwcvtbf16.f.f.v_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f29; dest:f30; op1val:0x0; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f30, f29, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f30; dest:f29; op1val:0x0; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f29, f30, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f27; dest:f28; op1val:0x0; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f28, f27, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f28; dest:f27; op1val:0x0; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f27, f28, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f25; dest:f26; op1val:0x8000; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f26, f25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f26; dest:f25; op1val:0x8000; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f25, f26, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f23; dest:f24; op1val:0x8000; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f24, f23, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f24; dest:f23; op1val:0x8000; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f23, f24, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f21; dest:f22; op1val:0x8000; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f22, f21, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f22; dest:f21; op1val:0x1; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f21, f22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f19; dest:f20; op1val:0x1; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f20, f19, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f20; dest:f19; op1val:0x1; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f19, f20, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f17; dest:f18; op1val:0x1; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f18, f17, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f18; dest:f17; op1val:0x1; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f17, f18, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f15; dest:f16; op1val:0x8001; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f16, f15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f16; dest:f15; op1val:0x8001; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f15, f16, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f13; dest:f14; op1val:0x8001; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f14, f13, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f14; dest:f13; op1val:0x8001; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f13, f14, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f11; dest:f12; op1val:0x8001; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f12, f11, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f12; dest:f11; op1val:0x2; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f11, f12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f9; dest:f10; op1val:0x2; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f10, f9, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f10; dest:f9; op1val:0x2; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f9, f10, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f7; dest:f8; op1val:0x2; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f8, f7, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f8; dest:f7; op1val:0x2; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f7, f8, dyn, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f5; dest:f6; op1val:0x807e; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f6, f5, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f6; dest:f5; op1val:0x807e; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f5, f6, dyn, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f3; dest:f4; op1val:0x807e; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f4, f3, dyn, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f4; dest:f3; op1val:0x807e; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f3, f4, dyn, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f1; dest:f2; op1val:0x807e; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f2, f1, dyn, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f2; dest:f1; op1val:0x7f; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f1, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f0; dest:f31; op1val:0x7f; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f31, f0, dyn, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f31; dest:f0; op1val:0x7f; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_V16_32(vfwcvtbf16.f.f.v, f0, f31, dyn, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(127,16,FLEN) +NAN_BOXED(127,16,FLEN) +NAN_BOXED(127,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvfbfwma/src/vfwmaaccbf16.vf_b1-01.S b/riscv-test-suite/rv32i_m/Zvfbfwma/src/vfwmaaccbf16.vf_b1-01.S new file mode 100644 index 000000000..2555f4808 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvfbfwma/src/vfwmaaccbf16.vf_b1-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:22 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.s.bf16.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.bf16 instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.s.bf16_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zvfbfwma,RV64IF_Zicsr_Zvfbfwma") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zvfbfwma.*);def TEST_CASE_1=True;",vfwmaaccbf16.vf_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f29; dest:f30; op1val:0x0; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f30, f29, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f30; dest:f29; op1val:0x0; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f29, f30, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f27; dest:f28; op1val:0x0; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f28, f27, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f28; dest:f27; op1val:0x0; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f27, f28, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f25; dest:f26; op1val:0x8000; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f26, f25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f26; dest:f25; op1val:0x8000; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f25, f26, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f23; dest:f24; op1val:0x8000; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f24, f23, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f24; dest:f23; op1val:0x8000; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f23, f24, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f21; dest:f22; op1val:0x8000; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f22, f21, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f22; dest:f21; op1val:0x1; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f21, f22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f19; dest:f20; op1val:0x1; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f20, f19, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f20; dest:f19; op1val:0x1; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f19, f20, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f17; dest:f18; op1val:0x1; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f18, f17, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f18; dest:f17; op1val:0x1; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f17, f18, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f15; dest:f16; op1val:0x8001; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f16, f15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f16; dest:f15; op1val:0x8001; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f15, f16, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f13; dest:f14; op1val:0x8001; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f14, f13, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f14; dest:f13; op1val:0x8001; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f13, f14, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f11; dest:f12; op1val:0x8001; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f12, f11, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f12; dest:f11; op1val:0x2; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f11, f12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f9; dest:f10; op1val:0x2; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f10, f9, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f10; dest:f9; op1val:0x2; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f9, f10, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f7; dest:f8; op1val:0x2; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f8, f7, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f8; dest:f7; op1val:0x2; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f7, f8, dyn, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f5; dest:f6; op1val:0x807e; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f6, f5, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f6; dest:f5; op1val:0x807e; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f5, f6, dyn, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f3; dest:f4; op1val:0x807e; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f4, f3, dyn, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f4; dest:f3; op1val:0x807e; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f3, f4, dyn, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f1; dest:f2; op1val:0x807e; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f2, f1, dyn, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f2; dest:f1; op1val:0x7f; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f1, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f0; dest:f31; op1val:0x7f; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f31, f0, dyn, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f31; dest:f0; op1val:0x7f; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_VFWMACCBF16_VF(vfwmaaccbf16.vf, f0, f31, dyn, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(127,16,FLEN) +NAN_BOXED(127,16,FLEN) +NAN_BOXED(127,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvfbfwma/src/vfwmaaccbf16.vv_b1-01.S b/riscv-test-suite/rv32i_m/Zvfbfwma/src/vfwmaaccbf16.vv_b1-01.S new file mode 100644 index 000000000..07872f08a --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvfbfwma/src/vfwmaaccbf16.vv_b1-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.0 +// timestamp : Wed Sep 13 20:38:22 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /scratch/riscof-docker2/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32Zfbfmin/rv32h_fcvt.s.bf16.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.bf16 instruction of the RISC-V RV32F_Zicsr_Zfbfmin,RV64F_Zicsr_Zfbfmin extension for the fcvt.s.bf16_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zvfbfwma,RV64IF_Zicsr_Zvfbfwma") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zvfbfwma.*);def TEST_CASE_1=True;",vfwmaaccbf16.vv_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f29; dest:f30; op1val:0x0; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f30, f29, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f30; dest:f29; op1val:0x0; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f29, f30, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f27; dest:f28; op1val:0x0; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f28, f27, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f28; dest:f27; op1val:0x0; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f27, f28, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f25; dest:f26; op1val:0x8000; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f26, f25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f26; dest:f25; op1val:0x8000; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f25, f26, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f23; dest:f24; op1val:0x8000; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f24, f23, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f24; dest:f23; op1val:0x8000; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f23, f24, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x00 and fm1 == 0x00 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f21; dest:f22; op1val:0x8000; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f22, f21, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f22; dest:f21; op1val:0x1; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f21, f22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f19; dest:f20; op1val:0x1; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f20, f19, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f20; dest:f19; op1val:0x1; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f19, f20, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f17; dest:f18; op1val:0x1; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f18, f17, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f18; dest:f17; op1val:0x1; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f17, f18, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f15; dest:f16; op1val:0x8001; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f16, f15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f16; dest:f15; op1val:0x8001; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f15, f16, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f13; dest:f14; op1val:0x8001; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f14, f13, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f14; dest:f13; op1val:0x8001; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f13, f14, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x00 and fm1 == 0x01 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f11; dest:f12; op1val:0x8001; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f12, f11, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f12; dest:f11; op1val:0x2; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f11, f12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f9; dest:f10; op1val:0x2; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f10, f9, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f10; dest:f9; op1val:0x2; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f9, f10, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f7; dest:f8; op1val:0x2; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f8, f7, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f8; dest:f7; op1val:0x2; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f7, f8, dyn, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f5; dest:f6; op1val:0x807e; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f6, f5, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f6; dest:f5; op1val:0x807e; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f5, f6, dyn, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f3; dest:f4; op1val:0x807e; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f4, f3, dyn, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f4; dest:f3; op1val:0x807e; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f3, f4, dyn, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f1; dest:f2; op1val:0x807e; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f2, f1, dyn, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f2; dest:f1; op1val:0x7f; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f1, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f0; dest:f31; op1val:0x7f; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f31, f0, dyn, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffffffffffff +/* opcode: fcvt.s.bf16 ; op1:f31; dest:f0; op1val:0x7f; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_VFWMACCBF16_VV(vfwmaaccbf16.vv, f0, f31, dyn, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(32894,16,FLEN) +NAN_BOXED(127,16,FLEN) +NAN_BOXED(127,16,FLEN) +NAN_BOXED(127,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END