diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5cfe4c8ae..00a84652b 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,4 +1,8 @@
 # CHANGELOG
+
+## [3.9.2] - 2024-06-11
+- Fixed reversed order of zicboz and Zicsr in cbo.zero RVTEST_ISA/RVTET_CASE strings.  Note that Sail does not yet handle cbo.zero
+	
 ## [3.9.1] - 2024-05-24
 - Split rv32i_m/F/fnmadd_b15.S, fnmsub_b15.S, fmadd_b15.S, fmsub_b15.S into multiple smaller tests
 - Split each _b15 file into 50 files consists of 768 (128*6) tests
diff --git a/riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S b/riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S
index 4fbfdf2e7..972275e4b 100644
--- a/riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S
+++ b/riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S
@@ -20,7 +20,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IZicsr_Zicboz")
+RVTEST_ISA("RV32IZicboz_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zicsr.*Zicboz.*);def TEST_CASE_1=True;",cbozero)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zicboz.*Zicsr.*);def TEST_CASE_1=True;",cbozero)
 
 RVTEST_SIGBASE(x2,signature_x2_1)
 
diff --git a/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S b/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S
index cc66623c1..093ec88e1 100644
--- a/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S
+++ b/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S
@@ -20,7 +20,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV64IZicboz")
+RVTEST_ISA("RV64IZicboz_Zicsr")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zicsr.*Zicboz.*);def TEST_CASE_1=True;",cbozero)
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zicboz.*Zicsr.*);def TEST_CASE_1=True;",cbozero)
 
 RVTEST_SIGBASE(x3,signature_x3_1)