From 4bc28e5865883b6135c5dfbc2fea65f7f7e5bf63 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 11 Jun 2024 12:49:49 -0700 Subject: [PATCH 1/3] Fixed reversed order of Zicboz and Zicsr in macros for cbo.zero --- CHANGELOG.md | 4 ++++ riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S | 4 ++-- riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S | 2 +- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 5cfe4c8ae..00a84652b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,4 +1,8 @@ # CHANGELOG + +## [3.9.2] - 2024-06-11 +- Fixed reversed order of zicboz and Zicsr in cbo.zero RVTEST_ISA/RVTET_CASE strings. Note that Sail does not yet handle cbo.zero + ## [3.9.1] - 2024-05-24 - Split rv32i_m/F/fnmadd_b15.S, fnmsub_b15.S, fmadd_b15.S, fmsub_b15.S into multiple smaller tests - Split each _b15 file into 50 files consists of 768 (128*6) tests diff --git a/riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S b/riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S index 4fbfdf2e7..972275e4b 100644 --- a/riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S +++ b/riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S @@ -20,7 +20,7 @@ // #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32IZicsr_Zicboz") +RVTEST_ISA("RV32IZicboz_Zicsr") .section .text.init .globl rvtest_entry_point @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zicsr.*Zicboz.*);def TEST_CASE_1=True;",cbozero) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zicboz.*Zicsr.*);def TEST_CASE_1=True;",cbozero) RVTEST_SIGBASE(x2,signature_x2_1) diff --git a/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S b/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S index cc66623c1..94958c9da 100644 --- a/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S +++ b/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S @@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zicsr.*Zicboz.*);def TEST_CASE_1=True;",cbozero) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*Zicboz.*Zicsr.*);def TEST_CASE_1=True;",cbozero) RVTEST_SIGBASE(x3,signature_x3_1) From 9dc21c7ea7d4f8095a3f12954a78e625454a8ff7 Mon Sep 17 00:00:00 2001 From: Umer Shahid Date: Wed, 12 Jun 2024 14:20:34 +0500 Subject: [PATCH 2/3] Update cbo.zero-01.S Updated RVTEST_ISA string for RV64-cbo.zero test --- riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S b/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S index 94958c9da..093ec88e1 100644 --- a/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S +++ b/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S @@ -20,7 +20,7 @@ // #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64IZicboz") +RVTEST_ISA("RV64IZicboz_Zicsr") .section .text.init .globl rvtest_entry_point From 26507ab504ada5ac851e49b78bd693fa1f1f118c Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 12 Jun 2024 03:25:48 -0700 Subject: [PATCH 3/3] Made RVTEST_ISA consistent between RV64 and RV32 --- riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S b/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S index 94958c9da..093ec88e1 100644 --- a/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S +++ b/riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S @@ -20,7 +20,7 @@ // #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64IZicboz") +RVTEST_ISA("RV64IZicboz_Zicsr") .section .text.init .globl rvtest_entry_point