The Advanced Configuration and Power Interface Specification provides the OS-centric view of system configuration, various hardware resources, events and power management.
This section defines the BRS-I mandatory and optional ACPI requirements on top of existing cite:[ACPI] and cite:[UEFI] specification requirements. Additional non-normative guidance may be found in the firmware implementation guidance section.
Important
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All content in this section is optional and recommended for BRS-B. |
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Be 64-bits clean.
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Implement the hardware-reduced ACPI mode (no FACS table). |
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The Processor Properties Table (PPTT) MUST be implemented, even on systems with a simple hart topology. |
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The PCI Memory-mapped Configuration Space (MCFG) table MUST NOT be present if it violates cite:[PCIFW]. |
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Only compatible PCIe segments, exposed via ECAM (Enhanced Configuration Access Mechanism), may be described in the MCFG. The MCFG MUST NOT require vendor-specific OS support. See PCI Services (cite:[ACPI], Section 4) for more ACPI requirements relating to PCIe support. See additional guidance. |
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A Serial Port Console Redirection Table cite:[SPCR] MUST be present on systems, where the graphics hardware is not present or not made
available to an OS loader via the standard |
In these cases, the table provides essential configuration for an early OS boot console. |
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An SPCR table, if present, MUST meet the following requirements:
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See additional guidance. |
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PLIC/APLIC namespace devices MUST be present in the ACPI namespace whenever corresponding MADT entries are present. See RVI ACPI IDs. |
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Also see AML_090 and additional guidance. |
This section lists additional requirements for ACPI methods and objects.
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The Cache Coherency Attribute ( |
This object provides information about whether a device has to manage cache coherency and about hardware support. This object is mandatory for all devices that can access CPU-visible memory. (cite:[ACPI] Section 6.2.17). |
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The Current Resource Setting (_CRS) device method for a PCIe Root Complex SHOULD NOT return any descriptors for I/O ranges (such as created by ASL macros WordIO, DWordIO, QWordIO, IO, FixedIO, or ExtendedIO). |
Legacy PCI I/O BARs are uncommon in modern PCIe devices and support for PCI I/O space may complicate configuration of PCIe Root Complex hardware in a compliant manner. |
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The Possible Resource Settings ( |
ACPI resource descriptors are typically used to describe devices with fixed I/O regions that do not change. Flexible resource assignment is not supported by most modern ACPI OSes. |
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Per-hart device objects MUST be defined under |
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Systems supporting OS-directed hart performance control and power management MUST expose these via Collaborative Processor Performance Control (CPPC, cite:[ACPI] Section 8.4.6). |
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Processor idle states MUST be described using Low Power Idle ( |
Systems with a Real-Time Clock on an OS-managed bus (e.g. I2C, subject to arbitration issues due to access to the bus by the OS) MUST implement the Time and Alarm Device (TAD) with functioning |
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Also see |
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Systems implementing a TAD MUST be functional without additional system-specific OS drivers. |
In situations where the Time and Alarm Device (TAD) depends on a
vendor-specific OS driver for correct function (SPI, I2C, etc), the TAD MUST
be functional if the OS driver is not loaded. That is, when a dependent
driver is loaded, an AML method switches further accesses to go
through the driver-backed |
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PLIC and APLIC device objects MUST support
the Global System Interrupt Base ( |
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UART device objects with ID |