The RISC-V Supervisor Binary Interface Specification (SBI) cite: [SBI] defines an interface between the supervisor mode and the next higher privilege mode. This section defines the mandatory SBI version and extensions implemented by the higher privilege mode in order to be compatible with this specification.
| ID# | Rule |
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The SBI implementation MUST conform to SBI v2.0 or later. |
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The SBI implementation MUST implement the Hart State Management (HSM) extension. |
HSM is used by an OS for starting up, stopping, suspending and querying the status of secondary harts. |
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Certain requirements are conditional on the presence of RISC-V ISA extensions or system features.
| ID# | Rule |
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The Timer Extension (TIME) MUST be implemented, if the RISC-V "stimecmp / vstimecmp" Extension (Sstc, cite: [Sstc]) is not available. |
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The S-Mode IPI Extension (sPI) MUST be implemented, if the Incoming MSI Controller (IMSIC, cite: [Aia]) is not available. |
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The RFENCE Extension (RFNC) extension MUST be implemented, if the Incoming MSI Controller (IMSIC, cite: [Aia]) is not available. |
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The Performance Monitoring Extension (PMU) MUST be implemented, if the counter delegation-related S-Mode ISA extensions (Sscsrind cite: [Sscsrind], Ssccfg cite: [Smcdeleg]) are not present. |
NOTE: The PMU extension is currently being developed by the performance analysis TG cite: [PerfAnalysis]. |
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