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Asm constraint to require an even register #37

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asb opened this issue Apr 26, 2023 · 2 comments
Open

Asm constraint to require an even register #37

asb opened this issue Apr 26, 2023 · 2 comments

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@asb
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asb commented Apr 26, 2023 •
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We don't currently have an asm constraint to require an even register (for an input or output in a register pair) and I don't believe there's a cross-target constraint already defined. We should likely decide on one. This could be used with the proposed zacas extension (amocas.d on rv32 or amocas.q on rv64), for zdinx, and IIRC the P extension.
@kito-cheng
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Good catch, Zdinx still using f in GCC internally, but I think we should have one for P and Zacas

@kito-cheng kito-cheng mentioned this issue Apr 27, 2023
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@kito-cheng
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#39

asb added a commit to llvm/llvm-project that referenced this issue Jul 10, 2023
@asb
[RISCV][MC] MC layer support for the experimental zacas extension
29f630a 
This implements the v1.0-rc1 draft extension.

amocas.d on RV32 and amocas.q have the restriction that rd and rs2 must
be even registers. I've opted to implement this restriction in
RISCVAsmParser::validateInstruction even though for codegen we'll need a
new register class and can then remove this validation. This also
sidesteps, for now, the issue of amocas.d being different on rv32 vs
rv64.

See <riscv-non-isa/riscv-c-api-doc#37> for the
issue of needing an agreed asm register constraint for register pairs.

Differential Revision: https://reviews.llvm.org/D149248
veselypeta pushed a commit to veselypeta/cherillvm that referenced this issue Sep 4, 2024
@asb @veselypeta
[RISCV][MC] MC layer support for the experimental zacas extension
f953e4f 
This implements the v1.0-rc1 draft extension.

amocas.d on RV32 and amocas.q have the restriction that rd and rs2 must
be even registers. I've opted to implement this restriction in
RISCVAsmParser::validateInstruction even though for codegen we'll need a
new register class and can then remove this validation. This also
sidesteps, for now, the issue of amocas.d being different on rv32 vs
rv64.

See <riscv-non-isa/riscv-c-api-doc#37> for the
issue of needing an agreed asm register constraint for register pairs.

Differential Revision: https://reviews.llvm.org/D149248
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Introduce new constraint for register pair riscv-non-isa/riscv-c-api-doc
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@asb @kito-cheng