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Update qos_intro.adoc
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Signed-off-by: Kersten Richter <[email protected]>
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kersten1 authored May 14, 2024
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Expand Up @@ -96,11 +96,7 @@ accesses are performed.

[NOTE]
====
The CBQRI registers are defined so that the software can perform two
individual 4 byte accesses or the hardware can perform two independent 4-byte
transactions to the high and low halves of the register, as long as the register
semantics are respected between the two software accesses or two hardware transactions,
respectively.
The CBQRI registers are defined so that software can perform two individual 4 byte accesses, or hardware can perform two independent 4 byte transactions resulting from an 8 byte access, to the high and low halves of the register as long as the register semantics, with regards to side-effects, are respected between the two software accesses, or two hardware transactions, respectively.
====

The controller registers use little-endian byte order (even if all harts are
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