From 6705ecba6ef67cf6a6d8d5751d7cb0c11223b5ca Mon Sep 17 00:00:00 2001 From: Dan Smathers Date: Mon, 5 Feb 2024 18:56:00 -0700 Subject: [PATCH 1/2] Update RVMODEL MSW and MTIMER macros currently MSW and MTIMER macros aren't functional. Updating to match https://github.com/riscv-software-src/riscv-isa-sim/blob/master/arch_test_target/spike/model_test.h Signed-off-by: Dan Smathers --- riscof/Templates/setup/model/env/model_test.h | 50 ++++++++++++++++--- 1 file changed, 42 insertions(+), 8 deletions(-) diff --git a/riscof/Templates/setup/model/env/model_test.h b/riscof/Templates/setup/model/env/model_test.h index 80101da..da1f09e 100644 --- a/riscof/Templates/setup/model/env/model_test.h +++ b/riscof/Templates/setup/model/env/model_test.h @@ -43,16 +43,50 @@ //RVTEST_IO_ASSERT_DFPR_EQ #define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) -#define RVMODEL_SET_MSW_INT \ - li t1, 1; \ - li t2, 0x2000000; \ - sw t1, 0(t2); +#ifndef RVMODEL_MCLINTBASE + #define RVMODEL_MCLINTBASE 0x02000000 +#endif -#define RVMODEL_CLEAR_MSW_INT \ - li t2, 0x2000000; \ - sw x0, 0(t2); +#ifndef RVMODEL_MSIP_OFFSET + #define RVMODEL_MSIP_OFFSET 0x0 +#endif -#define RVMODEL_CLEAR_MTIMER_INT +#ifndef RVMODEL_MTIMECMP_OFFSET + #define RVMODEL_MTIMECMP_OFFSET 0x4000 +#endif + +#ifndef RVMODEL_MTIMECMPH_OFFSET + #define RVMODEL_MTIMECMPH_OFFSET 0x4004 +#endif + +#define RVMODEL_SET_MSW_INT \ + lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET)>> 12); \ + addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET) & 0xFFF); \ + li t1, 1; \ + sw t1, (t0); \ + +#define RVMODEL_CLEAR_MSW_INT \ + lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET)>> 12); \ + addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET) & 0xFFF); \ + sw x0, (t0); \ + +#define RVMODEL_SET_MTIMER_INT \ + lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET)>> 12); \ + addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET) & 0xFFF); \ + sw x0, (t0); \ + lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET)>> 12); \ + addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET) & 0xFFF); \ + sw x0, (t0); \ + +#define RVMODEL_CLEAR_MTIMER_INT \ + addi t1,x0,1; \ + neg t1,t1; \ + lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET)>> 12); \ + addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET) & 0xFFF); \ + sw t1, (t0); \ + lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET)>> 12); \ + addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET) & 0xFFF); \ + sw t1, (t0); \ #define RVMODEL_CLEAR_MEXT_INT From 207698649563d2920252d577e0e866d7f90baa59 Mon Sep 17 00:00:00 2001 From: Dan Smathers Date: Mon, 5 Feb 2024 19:03:18 -0700 Subject: [PATCH 2/2] Update sail_cSim model_test.h updating sail_cSim template to match https://github.com/riscv-software-src/riscv-isa-sim/blob/master/arch_test_target/spike/model_test.h Signed-off-by: Dan Smathers --- .../setup/sail_cSim/env/model_test.h | 45 +++++++++++++++++-- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/riscof/Templates/setup/sail_cSim/env/model_test.h b/riscof/Templates/setup/sail_cSim/env/model_test.h index 386ffdf..0a0e3c2 100644 --- a/riscof/Templates/setup/sail_cSim/env/model_test.h +++ b/riscof/Templates/setup/sail_cSim/env/model_test.h @@ -43,11 +43,50 @@ //RVTEST_IO_ASSERT_DFPR_EQ #define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) -#define RVMODEL_SET_MSW_INT +#ifndef RVMODEL_MCLINTBASE + #define RVMODEL_MCLINTBASE 0x02000000 +#endif -#define RVMODEL_CLEAR_MSW_INT +#ifndef RVMODEL_MSIP_OFFSET + #define RVMODEL_MSIP_OFFSET 0x0 +#endif -#define RVMODEL_CLEAR_MTIMER_INT +#ifndef RVMODEL_MTIMECMP_OFFSET + #define RVMODEL_MTIMECMP_OFFSET 0x4000 +#endif + +#ifndef RVMODEL_MTIMECMPH_OFFSET + #define RVMODEL_MTIMECMPH_OFFSET 0x4004 +#endif + +#define RVMODEL_SET_MSW_INT \ + lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET)>> 12); \ + addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET) & 0xFFF); \ + li t1, 1; \ + sw t1, (t0); \ + +#define RVMODEL_CLEAR_MSW_INT \ + lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET)>> 12); \ + addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MSIP_OFFSET) & 0xFFF); \ + sw x0, (t0); \ + +#define RVMODEL_SET_MTIMER_INT \ + lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET)>> 12); \ + addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET) & 0xFFF); \ + sw x0, (t0); \ + lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET)>> 12); \ + addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET) & 0xFFF); \ + sw x0, (t0); \ + +#define RVMODEL_CLEAR_MTIMER_INT \ + addi t1,x0,1; \ + neg t1,t1; \ + lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET)>> 12); \ + addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMPH_OFFSET) & 0xFFF); \ + sw t1, (t0); \ + lui t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET)>> 12); \ + addi t0, t0, ((RVMODEL_MCLINTBASE + RVMODEL_MTIMECMP_OFFSET) & 0xFFF); \ + sw t1, (t0); \ #define RVMODEL_CLEAR_MEXT_INT