diff --git a/CHANGELOG.md b/CHANGELOG.md index a208451c..0371043a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,10 +2,15 @@ This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). + Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch. Only when a release to the main branch is done, the contents of the WIP-DEV are put under a versioned header while the `WIP-DEV` is left empty +## [0.12.2] - 2024-03-06 +- Add Zfa support. (PR#60) +- Initial covergroups for Zvk* instructions (PR#61) + ## [0.12.1] - 2024-02-27 - Fix test.yml diff --git a/riscv_ctg/__init__.py b/riscv_ctg/__init__.py index 2862388f..29adebcf 100644 --- a/riscv_ctg/__init__.py +++ b/riscv_ctg/__init__.py @@ -4,4 +4,4 @@ __author__ = """InCore Semiconductors Pvt Ltd""" __email__ = 'incorebot@gmail.com' -__version__ = '0.12.1' +__version__ = '0.12.2' diff --git a/riscv_ctg/data/fd.yaml b/riscv_ctg/data/fd.yaml index 46c86cda..ca33a625 100644 --- a/riscv_ctg/data/fd.yaml +++ b/riscv_ctg/data/fd.yaml @@ -1709,6 +1709,7 @@ fcvt.s.lu: fcsr_val: $fcsr*/ TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + flh: sig: stride: 2 @@ -1735,7 +1736,7 @@ flh: TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) fsgnj.h: - sig: + sig: stride: 2 sz: 'SIGALIGN' val: @@ -1761,6 +1762,7 @@ fsgnj.h: correctval:??; testreg:$testreg */ TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + fsgnjn.h: sig: @@ -2028,11 +2030,11 @@ fcvt.h.d: val: stride: 1 sz: 'FLEN/8' - val_template: "'NAN_BOXED($val,$width,FLEN)'" - load_instr: "FLREG" + val_template: "'.dword $val;'" + load_instr: "ld" xlen: [32,64] isa: - - IF_Zicsr_Zfh + - IFD_Zicsr_Zfh flen: [32,64] rm_val_data: '[7,0,1,2,3,4]' fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' @@ -2044,9 +2046,9 @@ fcvt.h.d: // $comment /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; - val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + val_offset:$val_offset; correctval:??; testreg:$testreg; fcsr_val: $fcsr */ - TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + TEST_FPSR_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) fcvt.h.s: sig: @@ -2073,7 +2075,7 @@ fcvt.h.s: /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; fcsr_val: $fcsr */ - TEST_FPSR_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + TEST_FPSR_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) feq.h: sig: @@ -2248,7 +2250,7 @@ fcvt.s.h: xlen: [32,64] isa: - IF_Zicsr_Zfh - flen: [16,32,64] + flen: [16,32] rm_val_data: '[7,0,1,2,3,4]' fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' std_op: @@ -2374,8 +2376,8 @@ fcvt.d.h: val: stride: 1 sz: 'FLEN/8' - val_template: "'NAN_BOXED($val,$width,FLEN)'" - load_instr: "FLREG" + val_template: "'.word $val;'" + load_instr: "lw" xlen: [32,64] isa: - IFD_Zicsr_Zfh @@ -2392,7 +2394,7 @@ fcvt.d.h: /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; fcsr_val: $fcsr */ - TEST_FPSR_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + TEST_FPSR_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) fmv.h.x: sig: @@ -2526,9 +2528,6 @@ fclass.h: fcsr_val:$fcsr*/ TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) - - - fcvt.h.w: sig: stride: 2 @@ -2632,3 +2631,392 @@ fcvt.lu.h: val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; fcsr_val:$fcsr*/ TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +# +# Zfa extension +# + +fminm.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) +fminm.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) +fmaxm.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) +fmaxm.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) +fround.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + std_op: + formattype: 'fsrformat' + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) +fround.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) +froundnx.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + std_op: + formattype: 'fsrformat' + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) +froundnx.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) +fmvh.x.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) +fmvp.d.x: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: '4' + val_template: "'.word $val;'" + load_instr: "lw" + xlen: [32] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIOIO_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) +fcvtmod.w.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + rm_val_data: '[1]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:rtz; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, rtz, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) +fltq.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) +fltq.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) +fleq.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) +fleq.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml index be5b1995..d77570ef 100644 --- a/riscv_ctg/data/imc.yaml +++ b/riscv_ctg/data/imc.yaml @@ -1862,6 +1862,7 @@ c.jr: isa: - IC formattype: 'crformat' + ea_align_data: '[0,1]' rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' template: |- @@ -1880,6 +1881,7 @@ c.jalr: isa: - IC formattype: 'crformat' + ea_align_data: '[0,1]' rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' template: |- diff --git a/riscv_ctg/env/arch_test.h b/riscv_ctg/env/arch_test.h index 2cff7041..e93a7d54 100644 --- a/riscv_ctg/env/arch_test.h +++ b/riscv_ctg/env/arch_test.h @@ -1066,7 +1066,7 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg) csrr flagreg, fcsr ; \ ) -//Tests for floating-point instructions with a single register operand and integer operand register +//Tests for floating-point instructions with one GPR operand and a single FPR result //This variant does not take the rm field and set it while writing the instruction #define TEST_FPIO_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg, load_instr) \ TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ @@ -1076,6 +1076,17 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg) csrr flagreg, fcsr; \ ) +//Tests for floating-point instructions with two GPR operands and a single FPR result +//This variant does not take the rm field and set it while writing the instruction +#define TEST_FPIOIO_OP_NRM(inst, destreg, freg1, freg2, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg, load_instr) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(load_instr, valaddr_reg, freg1, val_offset, testreg); \ + LOAD_MEM_VAL(load_instr, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg; \ + csrr flagreg, fcsr; \ + ) + //Tests for instructions with register-register-immediate operands #define TEST_RRI_OP(inst, destreg, reg1, reg2, imm, correctval, val1, val2, swreg, offset, testreg) \ TEST_CASE(testreg, destreg, correctval, swreg, offset, \ diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index 7cde0487..9f3fc8d0 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -14,17 +14,39 @@ import itertools import re +# F one_operand_finstructions = ["fsqrt.s","fmv.x.w","fcvt.wu.s","fcvt.w.s","fclass.s","fcvt.l.s","fcvt.lu.s","fcvt.s.l","fcvt.s.lu"] two_operand_finstructions = ["fadd.s","fsub.s","fmul.s","fdiv.s","fmax.s","fmin.s","feq.s","flt.s","fle.s","fsgnj.s","fsgnjn.s","fsgnjx.s"] three_operand_finstructions = ["fmadd.s","fmsub.s","fnmadd.s","fnmsub.s"] +# Zfa/F: +one_operand_finstructions += ["fround.s", "froundnx.s", "fcvtmod.w.d","fmvh.x.d"] +two_operand_finstructions += ["fmaxm.s", "fminm.s", "fmvp.d.x", "fleq.s", "fltq.s"] +# D one_operand_dinstructions = ["fsqrt.d","fclass.d","fcvt.w.d","fcvt.wu.d","fcvt.d.w","fcvt.d.wu","fcvt.d.s","fcvt.s.d"] two_operand_dinstructions = ["fadd.d","fsub.d","fmul.d","fdiv.d","fmax.d","fmin.d","feq.d","flt.d","fle.d","fsgnj.d","fsgnjn.d","fsgnjx.d"] three_operand_dinstructions = ["fmadd.d","fmsub.d","fnmadd.d","fnmsub.d"] +# H one_operand_hinstructions = ["fsqrt.h","fclass.h","fcvt.w.h","fcvt.wu.h","fcvt.h.w","fcvt.h.wu","fcvt.h.l","fcvt.h.lu","fcvt.l.h","fcvt.d.h","fcvt.h.d","fcvt.s.h","fcvt.s.h"] two_operand_hinstructions = ["fadd.h","fsub.h","fmul.h","fdiv.h","fmax.h","fmin.h","feq.h","flt.h","fle.h","fsgnj.h","fsgnjn.h","fsgnjx.h"] three_operand_hinstructions = ["fmadd.h","fmsub.h","fnmadd.h","fnmsub.h"] + +# Zfa/D: +one_operand_dinstructions += ["fround.d", "froundnx.d"] +two_operand_dinstructions += ["fmaxm.d", "fminm.d", "fleq.d", "fltq.d"] + + +def is_fp_instruction(insn): + ''' + Takes an instruction string (e.g. 'fadd.s') and returns True if it is a FP instruction. + The function is compatible with all existing and future RISC-V ISA extensions. + + :param insn: String representing an instruction (e.g. 'fadd.s', 'lw') + ''' + return type(insn) == str and insn.lower()[0] == 'f' + + from riscv_ctg.dsp_function import * twos_xlen = lambda x: twos(x,xlen) @@ -36,9 +58,10 @@ def toint(x: str): return int(x) def get_rm(opcode): - if any([x in opcode for x in - ['fsgnj','fle','flt','feq','fclass','fmv','flw','fsw','fld','fsd','fmin','fmax', - 'fcvt.d.s', 'fcvt.d.w','fcvt.d.wu']]): + insns = ['fsgnj','fle','flt','feq','fclass','fmv','flw','fsw','fld','fsd','fmin','fmax', + 'fcvt.d.s', 'fcvt.d.w','fcvt.d.wu'] + insns += ['fminm', 'fmaxm'] + if any([x in opcode for x in insns]): return [] else: return ['rm_val'] @@ -258,7 +281,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str,inx self.inxFlag = inxFlag self.is_sgn_extd = is_sgn_extd - if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","flw","fsw","fld","fsd","flh","fsh","c.lbu","c.lhu","c.lh","c.sb","c.sh","c.flw"]: + if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd","flh","fsh","c.lbu","c.lhu","c.lh","c.sb","c.sh","c.flw"]: self.val_vars = self.val_vars + ['ea_align'] self.template = opnode['template'] self.opnode = opnode @@ -849,14 +872,24 @@ def eval_inst_coverage(coverpoints,instr): else: var_dict['imm_val'] = toint(instr['imm_val']) elif key == 'rm_val': - var_dict['rm_val'] = toint(rm_dict[instr['rm_val']]) + var_dict['rm_val'] = rm_dict[instr['rm_val']] else: var_dict[key] = toint(instr[key]) for key in self.op_vars: var_dict[key] = instr[key] + instr_obj = instructionObject(None, instr['inst'], None) ext_specific_vars = instr_obj.evaluate_instr_var("ext_specific_vars", {**var_dict, 'flen': self.flen, 'iflen': self.iflen, 'inxFlag': self.inxFlag, 'xlen': self.xlen}, None, {'fcsr': hex(var_dict.get('fcsr', 0))}) + insn = instr['inst'] + # instructionObject() has an outdated list of instructions. + # Let's make it support all FP instructions until this is fixed. + # See https://github.com/riscv-software-src/riscv-isac/issues/69 + if (is_fp_instruction(insn)): + insn = "fadd.s" + instr_obj = instructionObject(None, insn, None) + ext_specific_vars = instr_obj.evaluate_instr_var("ext_specific_vars", {**var_dict, 'flen': self.flen, 'iflen': self.iflen}, None, {'fcsr': hex(var_dict.get('fcsr', 0))}) + if ext_specific_vars is not None: var_dict.update(ext_specific_vars) @@ -1416,4 +1449,4 @@ def __write_test__(self, file_name,node,label,instr_dict, op_node, usage_str): sign.append("#ifdef rvtest_gpr_save\n"+signode_template.substitute( {'n':32,'label':"gpr_save",'sz':'XLEN/32'})+"\n#endif\n") with open(file_name,"w") as fd: - fd.write(usage_str + test_template.safe_substitute(data='\n'.join(data),test=test,sig='\n'.join(sign),isa=op_node_isa,opcode=opcode,extension=extension,label=label)) \ No newline at end of file + fd.write(usage_str + test_template.safe_substitute(data='\n'.join(data),test=test,sig='\n'.join(sign),isa=op_node_isa,opcode=opcode,extension=extension,label=label)) diff --git a/sample_cgfs/dataset.cgf b/sample_cgfs/dataset.cgf index 2d3565ea..a1a1a01f 100644 --- a/sample_cgfs/dataset.cgf +++ b/sample_cgfs/dataset.cgf @@ -120,6 +120,40 @@ datasets: f30: 0 f31: 0 + all_vregs: &all_vregs + v0: 0 + v1: 0 + v2: 0 + v3: 0 + v4: 0 + v5: 0 + v6: 0 + v7: 0 + v8: 0 + v9: 0 + v10: 0 + v11: 0 + v12: 0 + v13: 0 + v14: 0 + v15: 0 + v16: 0 + v17: 0 + v18: 0 + v19: 0 + v20: 0 + v21: 0 + v22: 0 + v23: 0 + v24: 0 + v25: 0 + v26: 0 + v27: 0 + v28: 0 + v29: 0 + v30: 0 + v31: 0 + pair_regs: &pair_regs x2: 0 x4: 0 diff --git a/sample_cgfs/rv32i_priv.cgf b/sample_cgfs/rv32i_priv.cgf index 94131f0a..2575375e 100644 --- a/sample_cgfs/rv32i_priv.cgf +++ b/sample_cgfs/rv32i_priv.cgf @@ -85,6 +85,22 @@ misalign1-jalr: 'imm_val%2 == 1 and ea_align == 1': 0 'imm_val%2 == 0 and ea_align == 1': 0 +misalign1-cjalr: + config: + - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True + mnemonics: + c.jalr: 0 + val_comb: + 'ea_align == 1': 0 + +misalign1-cjr: + config: + - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True + mnemonics: + c.jr: 0 + val_comb: + 'ea_align == 1': 0 + misalign-jal: config: - check ISA:=regex(.*I.*C.*) diff --git a/sample_cgfs/rv64i_priv.cgf b/sample_cgfs/rv64i_priv.cgf index 8babd644..ba51952b 100644 --- a/sample_cgfs/rv64i_priv.cgf +++ b/sample_cgfs/rv64i_priv.cgf @@ -126,6 +126,22 @@ misalign1-jalr: val_comb: 'ea_align == 1': 0 +misalign1-cjalr: + config: + - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True + mnemonics: + c.jalr: 0 + val_comb: + 'ea_align == 1': 0 + +misalign1-cjr: + config: + - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True + mnemonics: + c.jr: 0 + val_comb: + 'ea_align == 1': 0 + misalign-jal: config: - check ISA:=regex(.*I.*C.*) diff --git a/sample_cgfs/zfa/fcvtmod.w.d.cgf b/sample_cgfs/zfa/fcvtmod.w.d.cgf new file mode 100644 index 00000000..6d83fdca --- /dev/null +++ b/sample_cgfs/zfa/fcvtmod.w.d.cgf @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fcvtmod.w.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b22: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b23: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b24: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b27: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b28: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b29: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen, 64, "fcvt.w.d", 1)': 0 diff --git a/sample_cgfs/zfa/fleq.d.cgf b/sample_cgfs/zfa/fleq.d.cgf new file mode 100644 index 00000000..392b7e31 --- /dev/null +++ b/sample_cgfs/zfa/fleq.d.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fleq.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fleq.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fle.d", 2)': 0 + +fleq.d_b19: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fleq.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 64, "fle.d", 2)': 0 diff --git a/sample_cgfs/zfa/fleq.s.cgf b/sample_cgfs/zfa/fleq.s.cgf new file mode 100644 index 00000000..518ff63d --- /dev/null +++ b/sample_cgfs/zfa/fleq.s.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fleq_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fleq.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "fle.s", 2)': 0 + +fleq_b19: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fleq.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 32, "fle.s", 2)': 0 diff --git a/sample_cgfs/zfa/fli.d.cgf b/sample_cgfs/zfa/fli.d.cgf new file mode 100644 index 00000000..dea19ac2 --- /dev/null +++ b/sample_cgfs/zfa/fli.d.cgf @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fli.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fli.d: 0 + rd: + <<: *all_fregs diff --git a/sample_cgfs/zfa/fli.s.cgf b/sample_cgfs/zfa/fli.s.cgf new file mode 100644 index 00000000..d16cc2c2 --- /dev/null +++ b/sample_cgfs/zfa/fli.s.cgf @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fli_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fli.s: 0 + rd: + <<: *all_fregs diff --git a/sample_cgfs/zfa/fltq.d.cgf b/sample_cgfs/zfa/fltq.d.cgf new file mode 100644 index 00000000..1bc2c082 --- /dev/null +++ b/sample_cgfs/zfa/fltq.d.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fltq.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fltq.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "flt.d", 2)': 0 + +fltq.d_b19: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fltq.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 64, "flt.d", 2)': 0 diff --git a/sample_cgfs/zfa/fltq.s.cgf b/sample_cgfs/zfa/fltq.s.cgf new file mode 100644 index 00000000..8449a73a --- /dev/null +++ b/sample_cgfs/zfa/fltq.s.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fltq_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fltq.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "flt.s", 2)': 0 + +fltq_b19: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fltq.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 32, "flt.s", 2)': 0 diff --git a/sample_cgfs/zfa/fmaxm.d.cgf b/sample_cgfs/zfa/fmaxm.d.cgf new file mode 100644 index 00000000..1538ea4e --- /dev/null +++ b/sample_cgfs/zfa/fmaxm.d.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fmaxm.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fmaxm.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fmax.d", 2)': 0 + +fmaxm.d_b19: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fmaxm.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 64, "fmax.d", 2)': 0 diff --git a/sample_cgfs/zfa/fmaxm.s.cgf b/sample_cgfs/zfa/fmaxm.s.cgf new file mode 100644 index 00000000..08d65acc --- /dev/null +++ b/sample_cgfs/zfa/fmaxm.s.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fmaxm_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fmaxm.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "fmax.s", 2)': 0 + +fmaxm_b19: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fmaxm.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 32, "fmax.s", 2)': 0 diff --git a/sample_cgfs/zfa/fminm.d.cgf b/sample_cgfs/zfa/fminm.d.cgf new file mode 100644 index 00000000..9f559c81 --- /dev/null +++ b/sample_cgfs/zfa/fminm.d.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fminm.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fminm.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fmin.d", 2)': 0 + +fminm.d_b19: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fminm.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 64, "fmin.d", 2)': 0 diff --git a/sample_cgfs/zfa/fminm.s.cgf b/sample_cgfs/zfa/fminm.s.cgf new file mode 100644 index 00000000..0c53416f --- /dev/null +++ b/sample_cgfs/zfa/fminm.s.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fminm_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fminm.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "fmin.s", 2)': 0 + +fminm_b19: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fminm.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 32, "fmin.s", 2)': 0 diff --git a/sample_cgfs/zfa/fmvh.x.d.cgf b/sample_cgfs/zfa/fmvh.x.d.cgf new file mode 100644 index 00000000..f3eb4fdf --- /dev/null +++ b/sample_cgfs/zfa/fmvh.x.d.cgf @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fmvh.x.d_b1: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b22: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b23: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b24: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b27: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b28: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b29: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fmv.x.d", 1)': 0 diff --git a/sample_cgfs/zfa/fmvp.d.x.cgf b/sample_cgfs/zfa/fmvp.d.x.cgf new file mode 100644 index 00000000..85633d60 --- /dev/null +++ b/sample_cgfs/zfa/fmvp.d.x.cgf @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fmvp.d.x_b25: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvp.d.x: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen, 64, "fmv.d.x", 2)': 0 + +fmvp.d.x_b26: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvp.d.x: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(64, "fmv.d.x", 2)': 0 + + diff --git a/sample_cgfs/zfa/fround.d.cgf b/sample_cgfs/zfa/fround.d.cgf new file mode 100644 index 00000000..671392d1 --- /dev/null +++ b/sample_cgfs/zfa/fround.d.cgf @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fround.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fround.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fsqrt.d", 1)': 0 diff --git a/sample_cgfs/zfa/fround.s.cgf b/sample_cgfs/zfa/fround.s.cgf new file mode 100644 index 00000000..629fea2c --- /dev/null +++ b/sample_cgfs/zfa/fround.s.cgf @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fround_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fround.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "fsqrt.s", 1)': 0 diff --git a/sample_cgfs/zfa/froundnx.d.cgf b/sample_cgfs/zfa/froundnx.d.cgf new file mode 100644 index 00000000..6fe670b7 --- /dev/null +++ b/sample_cgfs/zfa/froundnx.d.cgf @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause + +froundnx.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + froundnx.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fsqrt.d", 1)': 0 diff --git a/sample_cgfs/zfa/froundnx.s.cgf b/sample_cgfs/zfa/froundnx.s.cgf new file mode 100644 index 00000000..9bcdef9a --- /dev/null +++ b/sample_cgfs/zfa/froundnx.s.cgf @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause + +froundnx_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + froundnx.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "fsqrt.s", 1)': 0 diff --git a/sample_cgfs/zvk/vaesdf.cgf b/sample_cgfs/zvk/vaesdf.cgf new file mode 100644 index 00000000..be9eccad --- /dev/null +++ b/sample_cgfs/zvk/vaesdf.cgf @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vaesdf.vv: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesdf.vv: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + +vaesdf.vs: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesdf.vs: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vaesdm.cgf b/sample_cgfs/zvk/vaesdm.cgf new file mode 100644 index 00000000..2a8d96a6 --- /dev/null +++ b/sample_cgfs/zvk/vaesdm.cgf @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vaesdm.vv: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesdm.vv: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + +vaesdm.vs: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesdm.vs: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vaesef.cgf b/sample_cgfs/zvk/vaesef.cgf new file mode 100644 index 00000000..3ee274f8 --- /dev/null +++ b/sample_cgfs/zvk/vaesef.cgf @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vaesef.vv: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesef.vv: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + +vaesef.vs: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesef.vs: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vaesem.cgf b/sample_cgfs/zvk/vaesem.cgf new file mode 100644 index 00000000..e080c3c6 --- /dev/null +++ b/sample_cgfs/zvk/vaesem.cgf @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vaesem.vv: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesem.vv: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + +vaesem.vs: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesem.vs: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vaeskf1.cgf b/sample_cgfs/zvk/vaeskf1.cgf new file mode 100644 index 00000000..15ffee26 --- /dev/null +++ b/sample_cgfs/zvk/vaeskf1.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vaeskf1.vi: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaeskf1.vi: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vaeskf2.cgf b/sample_cgfs/zvk/vaeskf2.cgf new file mode 100644 index 00000000..352a0c0c --- /dev/null +++ b/sample_cgfs/zvk/vaeskf2.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vaeskf2.vi: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaeskf2.vi: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vaesz.cgf b/sample_cgfs/zvk/vaesz.cgf new file mode 100644 index 00000000..918194ed --- /dev/null +++ b/sample_cgfs/zvk/vaesz.cgf @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vaesz.vs: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesz.vs: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + + diff --git a/sample_cgfs/zvk/vandn.cgf b/sample_cgfs/zvk/vandn.cgf new file mode 100644 index 00000000..403493ea --- /dev/null +++ b/sample_cgfs/zvk/vandn.cgf @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vandn.vv: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vandn.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vandn.vx: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vandn.vx: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vbrev8.cgf b/sample_cgfs/zvk/vbrev8.cgf new file mode 100644 index 00000000..f4a60ee1 --- /dev/null +++ b/sample_cgfs/zvk/vbrev8.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vbrev8.v: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vbrev8.v: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vclmul.cgf b/sample_cgfs/zvk/vclmul.cgf new file mode 100644 index 00000000..ccd772bd --- /dev/null +++ b/sample_cgfs/zvk/vclmul.cgf @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vclmul.vv: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vclmul.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vclmul.vx: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vclmul.vx: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vclmulh.cgf b/sample_cgfs/zvk/vclmulh.cgf new file mode 100644 index 00000000..b817719e --- /dev/null +++ b/sample_cgfs/zvk/vclmulh.cgf @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vclmulh.vv: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vclmulh.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vclmulh.vx: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vclmulh.vx: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vghsh.cgf b/sample_cgfs/zvk/vghsh.cgf new file mode 100644 index 00000000..43ed9e62 --- /dev/null +++ b/sample_cgfs/zvk/vghsh.cgf @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vghsh.vv: + config: + - check ISA:=(.*I.*V.*Zvkg) + mnemonics: + vghsh.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vgmul.cgf b/sample_cgfs/zvk/vgmul.cgf new file mode 100644 index 00000000..f0e5d7a8 --- /dev/null +++ b/sample_cgfs/zvk/vgmul.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vgmul.vv: + config: + - check ISA:=(.*I.*V.*Zvkg) + mnemonics: + vgmul.vv: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vrev8.cgf b/sample_cgfs/zvk/vrev8.cgf new file mode 100644 index 00000000..6dd373e2 --- /dev/null +++ b/sample_cgfs/zvk/vrev8.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vrev8.v: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vrev8.v: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vrol.cgf b/sample_cgfs/zvk/vrol.cgf new file mode 100644 index 00000000..36ab5818 --- /dev/null +++ b/sample_cgfs/zvk/vrol.cgf @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vrol.vv: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vrol.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vrol.vx: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vrol.vx: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vror.cgf b/sample_cgfs/zvk/vror.cgf new file mode 100644 index 00000000..6d0974e1 --- /dev/null +++ b/sample_cgfs/zvk/vror.cgf @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vror.vv: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vror.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vror.vx: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vror.vx: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vror.vi: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vror.vi: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vsha2ch.cgf b/sample_cgfs/zvk/vsha2ch.cgf new file mode 100644 index 00000000..26778123 --- /dev/null +++ b/sample_cgfs/zvk/vsha2ch.cgf @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vsha2ch.vv: + config: + - check ISA:=(.*I.*V.*Zvknha) + mnemonics: + vsha2ch.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vsha2ch.vv: + config: + - check ISA:=(.*I.*V.*Zvknhb) + mnemonics: + vsha2ch.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vsha2cl.cfg b/sample_cgfs/zvk/vsha2cl.cfg new file mode 100644 index 00000000..3a190c42 --- /dev/null +++ b/sample_cgfs/zvk/vsha2cl.cfg @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vsha2cl.vv: + config: + - check ISA:=(.*I.*V.*Zvknha) + mnemonics: + vsha2cl.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vsha2cl.vv: + config: + - check ISA:=(.*I.*V.*Zvknhb) + mnemonics: + vsha2cl.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vsha2ms.cgf b/sample_cgfs/zvk/vsha2ms.cgf new file mode 100644 index 00000000..e7598d42 --- /dev/null +++ b/sample_cgfs/zvk/vsha2ms.cgf @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vsha2ms.vv: + config: + - check ISA:=(.*I.*V.*Zvknha) + mnemonics: + vsha2ms.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vsha2ms.vv: + config: + - check ISA:=(.*I.*V.*Zvknhb) + mnemonics: + vsha2ms.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vsm3c.cgf b/sample_cgfs/zvk/vsm3c.cgf new file mode 100644 index 00000000..4d2a1694 --- /dev/null +++ b/sample_cgfs/zvk/vsm3c.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vsm3c.vi: + config: + - check ISA:=(.*I.*V.*Zvksh) + mnemonics: + vsm3c.vi: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vsm3me.cgf b/sample_cgfs/zvk/vsm3me.cgf new file mode 100644 index 00000000..8685d373 --- /dev/null +++ b/sample_cgfs/zvk/vsm3me.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vsm3me.vi: + config: + - check ISA:=(.*I.*V.*Zvksh) + mnemonics: + vsm3me.vi: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vsm4k.cgf b/sample_cgfs/zvk/vsm4k.cgf new file mode 100644 index 00000000..c1685e8c --- /dev/null +++ b/sample_cgfs/zvk/vsm4k.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vsm4k.vi: + config: + - check ISA:=(.*I.*V.*Zvksed) + mnemonics: + vsm4k.vi: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vsm4r.cgf b/sample_cgfs/zvk/vsm4r.cgf new file mode 100644 index 00000000..9e20e54c --- /dev/null +++ b/sample_cgfs/zvk/vsm4r.cgf @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vsm4r.vv: + config: + - check ISA:=(.*I.*V.*Zvksed) + mnemonics: + vsm4r.vv: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + +vsm4r.vs: + config: + - check ISA:=(.*I.*V.*Zvksed) + mnemonics: + vsm4r.vs: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0