From 3ed8269b598a7b9a363b86d24034cc854a320775 Mon Sep 17 00:00:00 2001 From: Yu-Cheng Chang Date: Thu, 18 Jul 2024 15:50:33 +0800 Subject: [PATCH] Add coverage for misalign1-cjalr and misalign1-cjr (#116) * Add coverage for misalign1-cjalr and misalign1-cjr Signed-off-by: Roger Chang * Add ea_align_data for c.jalr and c.jr --------- Signed-off-by: Roger Chang --- riscv_ctg/data/imc.yaml | 2 ++ riscv_ctg/generator.py | 4 ++-- sample_cgfs/rv32i_priv.cgf | 16 ++++++++++++++++ sample_cgfs/rv64i_priv.cgf | 16 ++++++++++++++++ 4 files changed, 36 insertions(+), 2 deletions(-) diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml index be5b1995..d77570ef 100644 --- a/riscv_ctg/data/imc.yaml +++ b/riscv_ctg/data/imc.yaml @@ -1862,6 +1862,7 @@ c.jr: isa: - IC formattype: 'crformat' + ea_align_data: '[0,1]' rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' template: |- @@ -1880,6 +1881,7 @@ c.jalr: isa: - IC formattype: 'crformat' + ea_align_data: '[0,1]' rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' template: |- diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index 5bf34f68..6ac8afb3 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -256,7 +256,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str): self.is_fext = is_fext self.is_nan_box = is_nan_box - if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","flw","fsw","fld","fsd"]: + if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd"]: self.val_vars = self.val_vars + ['ea_align'] self.template = opnode['template'] self.opnode = opnode @@ -1417,4 +1417,4 @@ def __write_test__(self, file_name,node,label,instr_dict, op_node, usage_str): sign.append("#ifdef rvtest_gpr_save\n"+signode_template.substitute( {'n':32,'label':"gpr_save",'sz':'XLEN/32'})+"\n#endif\n") with open(file_name,"w") as fd: - fd.write(usage_str + test_template.safe_substitute(data='\n'.join(data),test=test,sig='\n'.join(sign),isa=op_node_isa,opcode=opcode,extension=extension,label=label)) \ No newline at end of file + fd.write(usage_str + test_template.safe_substitute(data='\n'.join(data),test=test,sig='\n'.join(sign),isa=op_node_isa,opcode=opcode,extension=extension,label=label)) diff --git a/sample_cgfs/rv32i_priv.cgf b/sample_cgfs/rv32i_priv.cgf index 94131f0a..2575375e 100644 --- a/sample_cgfs/rv32i_priv.cgf +++ b/sample_cgfs/rv32i_priv.cgf @@ -85,6 +85,22 @@ misalign1-jalr: 'imm_val%2 == 1 and ea_align == 1': 0 'imm_val%2 == 0 and ea_align == 1': 0 +misalign1-cjalr: + config: + - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True + mnemonics: + c.jalr: 0 + val_comb: + 'ea_align == 1': 0 + +misalign1-cjr: + config: + - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True + mnemonics: + c.jr: 0 + val_comb: + 'ea_align == 1': 0 + misalign-jal: config: - check ISA:=regex(.*I.*C.*) diff --git a/sample_cgfs/rv64i_priv.cgf b/sample_cgfs/rv64i_priv.cgf index 8babd644..ba51952b 100644 --- a/sample_cgfs/rv64i_priv.cgf +++ b/sample_cgfs/rv64i_priv.cgf @@ -126,6 +126,22 @@ misalign1-jalr: val_comb: 'ea_align == 1': 0 +misalign1-cjalr: + config: + - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True + mnemonics: + c.jalr: 0 + val_comb: + 'ea_align == 1': 0 + +misalign1-cjr: + config: + - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True + mnemonics: + c.jr: 0 + val_comb: + 'ea_align == 1': 0 + misalign-jal: config: - check ISA:=regex(.*I.*C.*)