From 630ffcd8ad3bdf72bbf97a9b78d184ab6de046fa Mon Sep 17 00:00:00 2001 From: Anusha Date: Mon, 5 Aug 2024 09:46:26 +0530 Subject: [PATCH] Removed unwanted space --- riscv_ctg/data/fd.yaml | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/riscv_ctg/data/fd.yaml b/riscv_ctg/data/fd.yaml index ca33a62..22cb898 100644 --- a/riscv_ctg/data/fd.yaml +++ b/riscv_ctg/data/fd.yaml @@ -1532,7 +1532,7 @@ flw: sz: '4' val_template: "''" load_instr: "flw" - rs1_op_data: *all_regs_mx0 + rs1_op_data: *all_regs_mx0 rd_op_data: *all_fregs xlen: [32,64] std_op: @@ -1709,7 +1709,6 @@ fcvt.s.lu: fcsr_val: $fcsr*/ TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) - flh: sig: stride: 2 @@ -1736,7 +1735,7 @@ flh: TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) fsgnj.h: - sig: + sig: stride: 2 sz: 'SIGALIGN' val: @@ -2657,12 +2656,14 @@ fminm.s: rs2_op_data: *all_fregs rd_op_data: *all_fregs template: |- + // $comment /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; correctval:??; testreg:$testreg */ TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + fminm.d: sig: stride: 2 @@ -2683,12 +2684,14 @@ fminm.d: rs2_op_data: *all_fregs rd_op_data: *all_fregs template: |- + // $comment /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; correctval:??; testreg:$testreg */ TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + fmaxm.s: sig: stride: 2 @@ -2710,12 +2713,14 @@ fmaxm.s: rs2_op_data: *all_fregs rd_op_data: *all_fregs template: |- + // $comment /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; correctval:??; testreg:$testreg */ TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + fmaxm.d: sig: stride: 2 @@ -2736,12 +2741,14 @@ fmaxm.d: rs2_op_data: *all_fregs rd_op_data: *all_fregs template: |- + // $comment /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; correctval:??; testreg:$testreg */ TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + fround.s: sig: stride: 2 @@ -2763,11 +2770,13 @@ fround.s: rs1_op_data: *all_fregs rd_op_data: *all_fregs template: |- + // $comment /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; fcsr_val: $fcsr */ TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + fround.d: sig: stride: 2 @@ -2788,11 +2797,13 @@ fround.d: rs1_op_data: *all_fregs rd_op_data: *all_fregs template: |- + // $comment /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; fcsr_val: $fcsr */ TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + froundnx.s: sig: stride: 2 @@ -2814,11 +2825,13 @@ froundnx.s: rs1_op_data: *all_fregs rd_op_data: *all_fregs template: |- + // $comment /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; fcsr_val: $fcsr */ TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + froundnx.d: sig: stride: 2 @@ -2839,11 +2852,13 @@ froundnx.d: rs1_op_data: *all_fregs rd_op_data: *all_fregs template: |- + // $comment /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; fcsr_val: $fcsr */ TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + fmvh.x.d: sig: stride: 2 @@ -2868,6 +2883,7 @@ fmvh.x.d: val_offset:$val_offset; correctval:??; testreg:$testreg; fcsr_val:$fcsr*/ TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + fmvp.d.x: sig: stride: 2 @@ -2893,6 +2909,7 @@ fmvp.d.x: val_offset:$val_offset; correctval:??; testreg:$testreg; fcsr_val: $fcsr*/ TEST_FPIOIO_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + fcvtmod.w.d: sig: stride: 2 @@ -2918,6 +2935,7 @@ fcvtmod.w.d: val_offset:$val_offset; rmval:rtz; correctval:??; testreg:$testreg; fcsr_val:$fcsr*/ TEST_FPID_OP($inst, $rd, $rs1, rtz, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + fltq.s: sig: stride: 2 @@ -2944,6 +2962,7 @@ fltq.s: valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; fcsr_val: $fcsr*/ TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + fltq.d: sig: stride: 2 @@ -2969,6 +2988,7 @@ fltq.d: valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; fcsr_val: $fcsr*/ TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + fleq.s: sig: stride: 2 @@ -2995,6 +3015,7 @@ fleq.s: valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; fcsr_val: $fcsr*/ TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + fleq.d: sig: stride: 2