From 9d5e1e5f71db7560ae719abce851c39f8aae5d90 Mon Sep 17 00:00:00 2001 From: anuani21 <114156183+anuani21@users.noreply.github.com> Date: Thu, 22 Aug 2024 18:19:33 +0530 Subject: [PATCH] Add support for Zfinx and Zfh extension (#67) * Updated Zfinx sign extension * Updated Zfinx sign extension code * latest Zfh code * Updated latest code * updated Zfinx code * Introduced half width and half word with respect to Zfh * Added RV64Zfh cgf files * Added RV64Zfinx cgf files * Updated the missing ISA regex expression * updated the yaml * Removed unwanted space --------- Signed-off-by: anuani21 <114156183+anuani21@users.noreply.github.com> Signed-off-by: Umer Shahid Co-authored-by: Umer Shahid --- riscv_ctg/constants.py | 2 +- riscv_ctg/ctg.py | 16 +- riscv_ctg/data/fd.yaml | 922 ++++++++++ riscv_ctg/data/inx.yaml | 1530 +++++++++++++++++ riscv_ctg/env/arch_test.h | 56 +- riscv_ctg/generator.py | 66 +- riscv_ctg/helpers.py | 28 +- riscv_ctg/main.py | 7 +- .../sample_cgfs_fext/RV32H/rv32h_fadd.cgf | 188 ++ .../sample_cgfs_fext/RV32H/rv32h_fclass.cgf | 15 + .../sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf | 106 ++ .../sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf | 106 ++ .../sample_cgfs_fext/RV32H/rv32h_fcvt.h.l.cgf | 27 + .../RV32H/rv32h_fcvt.h.lu.cgf | 27 + .../sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf | 106 ++ .../sample_cgfs_fext/RV32H/rv32h_fcvt.h.w.cgf | 27 + .../RV32H/rv32h_fcvt.h.wu.cgf | 27 + .../sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf | 106 ++ .../sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf | 92 + .../RV32H/rv32h_fcvt.wu.h.cgf | 92 + .../sample_cgfs_fext/RV32H/rv32h_fdiv.cgf | 188 ++ .../sample_cgfs_fext/RV32H/rv32h_feq.cgf | 35 + .../sample_cgfs_fext/RV32H/rv32h_fle.cgf | 35 + .../sample_cgfs_fext/RV32H/rv32h_flh.cgf | 19 + .../sample_cgfs_fext/RV32H/rv32h_flt.cgf | 35 + .../sample_cgfs_fext/RV32H/rv32h_fmadd.cgf | 229 +++ .../sample_cgfs_fext/RV32H/rv32h_fmax.cgf | 35 + .../sample_cgfs_fext/RV32H/rv32h_fmin.cgf | 35 + .../sample_cgfs_fext/RV32H/rv32h_fmsub.cgf | 229 +++ .../sample_cgfs_fext/RV32H/rv32h_fmul.cgf | 155 ++ .../sample_cgfs_fext/RV32H/rv32h_fmv.h.x.cgf | 28 + .../sample_cgfs_fext/RV32H/rv32h_fmv.x.h.cgf | 92 + .../sample_cgfs_fext/RV32H/rv32h_fnmadd.cgf | 229 +++ .../sample_cgfs_fext/RV32H/rv32h_fnmsub.cgf | 229 +++ .../sample_cgfs_fext/RV32H/rv32h_fsgnj.cgf | 19 + .../sample_cgfs_fext/RV32H/rv32h_fsgnjn.cgf | 19 + .../sample_cgfs_fext/RV32H/rv32h_fsgnjx.cgf | 19 + .../sample_cgfs_fext/RV32H/rv32h_fsh.cgf | 19 + .../sample_cgfs_fext/RV32H/rv32h_fsqrt.cgf | 136 ++ .../sample_cgfs_fext/RV32H/rv32h_fsub.cgf | 188 ++ .../sample_cgfs_fext/RV64H/rv64h_fcvt.h.l.cgf | 14 + .../RV64H/rv64h_fcvt.h.lu.cgf | 14 + .../sample_cgfs_fext/RV64H/rv64h_fcvt.l.h.cgf | 14 + .../RV64H/rv64h_fcvt.lu.h.cgf | 14 + .../sample_cgfs_fext/RV64Zfinx/fadd.s.cgf | 188 ++ .../sample_cgfs_fext/RV64Zfinx/fclass.s.cgf | 14 + .../sample_cgfs_fext/RV64Zfinx/fcvt.l.s.cgf | 92 + .../sample_cgfs_fext/RV64Zfinx/fcvt.lu.s.cgf | 92 + .../sample_cgfs_fext/RV64Zfinx/fcvt.w.s.cgf | 92 + .../sample_cgfs_fext/RV64Zfinx/fcvt.wu.s.cgf | 92 + .../sample_cgfs_fext/RV64Zfinx/fdiv.s.cgf | 188 ++ .../sample_cgfs_fext/RV64Zfinx/feq.s.cgf | 35 + .../sample_cgfs_fext/RV64Zfinx/fle.s.cgf | 35 + .../sample_cgfs_fext/RV64Zfinx/flt.s.cgf | 35 + .../sample_cgfs_fext/RV64Zfinx/fmadd.s.cgf | 248 +++ .../sample_cgfs_fext/RV64Zfinx/fmax.s.cgf | 35 + .../sample_cgfs_fext/RV64Zfinx/fmin.s.cgf | 35 + .../sample_cgfs_fext/RV64Zfinx/fmsub.s.cgf | 247 +++ .../sample_cgfs_fext/RV64Zfinx/fmul.s.cgf | 155 ++ .../sample_cgfs_fext/RV64Zfinx/fnmadd.s.cgf | 247 +++ .../sample_cgfs_fext/RV64Zfinx/fnmsub.s.cgf | 247 +++ .../sample_cgfs_fext/RV64Zfinx/fsgnj.s.cgf | 19 + .../sample_cgfs_fext/RV64Zfinx/fsgnjn.s.cgf | 17 + .../sample_cgfs_fext/RV64Zfinx/fsgnjx.s.cgf | 19 + .../sample_cgfs_fext/RV64Zfinx/fsqrt.s.cgf | 136 ++ .../sample_cgfs_fext/RV64Zfinx/fsub.s.cgf | 188 ++ 66 files changed, 7993 insertions(+), 38 deletions(-) create mode 100644 riscv_ctg/data/inx.yaml create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fadd.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fclass.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.l.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.lu.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.w.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.wu.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fdiv.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_feq.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fle.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_flh.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_flt.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmadd.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmax.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmin.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmsub.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmul.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmv.h.x.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmv.x.h.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fnmadd.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fnmsub.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsgnj.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsgnjn.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsgnjx.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsh.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsqrt.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsub.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.l.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.lu.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.l.h.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.lu.h.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fadd.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fclass.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.l.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.lu.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.w.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.wu.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fdiv.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/feq.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fle.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/flt.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmadd.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmax.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmin.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmsub.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmul.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fnmadd.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fnmsub.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsgnj.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsgnjn.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsgnjx.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsqrt.s.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsub.s.cgf diff --git a/riscv_ctg/constants.py b/riscv_ctg/constants.py index 3f3f8017..ccf8e471 100644 --- a/riscv_ctg/constants.py +++ b/riscv_ctg/constants.py @@ -191,7 +191,7 @@ def gen_bitmanip_dataset(bit_width,sign=True): # increment each value in dataset, increment each value in dataset, add them to the dataset return dataset + [x - 1 for x in dataset] + [x+1 for x in dataset] + dataset0 -template_fnames = ["template.yaml","imc.yaml","fd.yaml"] +template_fnames = ["template.yaml","imc.yaml","fd.yaml","inx.yaml"] template_files = [os.path.join(root,"data/"+f) for f in template_fnames] diff --git a/riscv_ctg/ctg.py b/riscv_ctg/ctg.py index 9d7c0fa8..1d1dced1 100644 --- a/riscv_ctg/ctg.py +++ b/riscv_ctg/ctg.py @@ -16,7 +16,7 @@ from math import * from riscv_ctg.__init__ import __version__ -def create_test(usage_str, node,label,base_isa,max_inst, op_template, randomize, out_dir, xlen, flen): +def create_test(usage_str, node,label,base_isa,max_inst, op_template, randomize, out_dir, xlen, flen, inxFlag): iflen = 0 if 'mnemonics' not in node and 'csr_comb' not in node: logger.warning("Neither mnemonics nor csr_comb node not found in covergroup: " + str(label)) @@ -42,7 +42,7 @@ def gen_test(op_node, opcode): fprefix = os.path.join(out_dir,str(label)) logger.info('Generating Test for :' + str(label) +"-" + opcode) formattype = op_node['formattype'] - gen = Generator(formattype,op_node,opcode,randomize,xlen,flen,iflen,base_isa) + gen = Generator(formattype,op_node,opcode,randomize,xlen,flen,iflen,base_isa,inxFlag) op_comb = gen.opcomb(node) val_comb = gen.valcomb(node) instr_dict = gen.correct_val( @@ -100,7 +100,7 @@ def gen_test(op_node, opcode): logger.info('Writing tests for csr_comb') csr_comb_gen.write_test(fprefix, node, usage_str, label, csr_comb_instr_dict) -def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, max_inst): +def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, max_inst,inxFlag): logger.level(verbose) logger.info('****** RISC-V Compliance Test Generator {0} *******'.format(__version__ )) logger.info('Copyright (c) 2020, InCore Semiconductors Pvt. Ltd.') @@ -123,9 +123,17 @@ def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, ma usage_str = const.usage.safe_substitute(base_isa=base_isa, \ cgf=cgf_argument, version = __version__, time=mytime, \ randomize=randomize_argument,xlen=str(xlen_arg)) + # --------------------------------- + # IITM Changes + # This is introduced to handle the template conflict over float instructions + # --------------------------------- + if inxFlag: + const.template_files.remove([fd for fd in const.template_files if "fd.yaml" in fd][0]) + else: + const.template_files.remove([fd for fd in const.template_files if "inx.yaml" in fd][0]) op_template = utils.load_yamls(const.template_files) cgf = expand_cgf(cgf_file,xlen,flen) pool = mp.Pool(num_procs) results = pool.starmap(create_test, [(usage_str, node,label,base_isa,max_inst, op_template, - randomize, out_dir, xlen, flen) for label,node in cgf.items()]) + randomize, out_dir, xlen, flen, inxFlag) for label,node in cgf.items()]) pool.close() diff --git a/riscv_ctg/data/fd.yaml b/riscv_ctg/data/fd.yaml index 2235c957..22cb8985 100644 --- a/riscv_ctg/data/fd.yaml +++ b/riscv_ctg/data/fd.yaml @@ -1709,6 +1709,928 @@ fcvt.s.lu: fcsr_val: $fcsr*/ TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) +flh: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "''" + load_instr: "flh" + rs1_op_data: *all_regs_mx0 + rd_op_data: *all_fregs + xlen: [32,64] + std_op: + isa: + - IF_Zicsr_Zfh + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'iformat' + ea_align_data: '[0,1,2,3]' + imm_val_data: 'gen_sign_dataset(12)' + template: |- + // $comment + // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + +fsgnj.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + + +fsgnjn.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnjx.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmadd.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rs3_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmax.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED_Z($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fnmadd.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + - IFD_Zicsr + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rs3_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fnmsub.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + - IFD_Zicsr + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rs3_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsub.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg*/ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmul.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fdiv.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fcvt.h.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfh + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fcvt.h.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +feq.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED_Z($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fle.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED_Z($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +flt.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED_Z($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsqrt.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmsub.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rs3_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsh: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/4' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_fregs + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'sformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: '[0xABCDEF12]' + imm_val_data: 'gen_sign_dataset(12)' + template: |- + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + // valreg: $valaddr_reg; valoffset: $val_offset + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + +fcvt.s.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fcvt.h.l: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + std_op: + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.h.lu: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.w.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED_Z($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.wu.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED_Z($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.d.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'.word $val;'" + load_instr: "lw" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfh + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmv.h.x: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "lw" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fmv.x.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fadd.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32] + std_op: + formattype: 'rformat' + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmin.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED_Z($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fclass.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fcvt.h.w: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "lw" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.h.wu: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "LREGWU" + xlen: [32,64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.l.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [64] + std_op: + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + rm_val_data: '[0,1,2,3,4,7]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.lu.h: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [64] + isa: + - IF_Zicsr_Zfh + flen: [16,32,64] + rm_val_data: '[0,1,2,3,4,7]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + # # Zfa extension # diff --git a/riscv_ctg/data/inx.yaml b/riscv_ctg/data/inx.yaml new file mode 100644 index 00000000..867e6a91 --- /dev/null +++ b/riscv_ctg/data/inx.yaml @@ -0,0 +1,1530 @@ +# See LICENSE.incore for details +# IITM Changes +# This new inx.yaml file handles all of the z*inx extensions +# ======= +fadd.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + std_op: + formattype: 'rformat' + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fadd.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsub.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsub.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmul.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmul.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fdiv.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fdiv.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsqrt.s: + sig: + stride: 1 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsqrt.d: + sig: + stride: 1 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/4' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmadd.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rs3_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmadd.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rs3_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmsub.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rs3_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmsub.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rs3_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fnmadd.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rs3_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fnmadd.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rs3_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fnmsub.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rs3_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fnmsub.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rs3_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnj.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnj.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnjn.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnjn.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnjx.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnjx.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmin.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmin.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmax.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmax.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:$correctval; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +feq.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +feq.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +flt.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +flt.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fle.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fle.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fcvt.w.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.w.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.wu.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.wu.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.l.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.lu.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.s.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fcvt.d.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zdinx + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fcvt.s.w: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "lw" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.s.wu: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "LREGWU" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.d.w: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "lw" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.d.wu: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "LREGWU" + xlen: [32,64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.d.l: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.d.lu: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [64] + isa: + - I_Zdinx + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fmv.d.x: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [64] + isa: + - I_Zdinx + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fclass.s: + sig: + stride: 1 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32,64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:$correctval; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fclass.d: + sig: + stride: 1 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [32, 64] + isa: + - I_Zdinx + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *pair_regs + rd_op_data: *pair_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:$correctval; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +# The val nodes are present in the fmem ops right now as a hack to force allocation of flagreg. Once +# anxilliary registers are moved to their own functions, this can be removed. + +fcvt.l.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/4' + val_template: "'NAN_BOXED($val,64,FLEN)'" + load_instr: "LREG" + xlen: [64] + std_op: + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + rm_val_data: '[0,1,2,3,4,7]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.lu.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "LREG" + xlen: [64] + isa: + - I_Zfinx + - I_Zdinx + flen: [32,64] + rm_val_data: '[0,1,2,3,4,7]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.s.l: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [64] + isa: + - I_Zfinx + - I_Zdinx + std_op: + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.s.lu: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [64] + isa: + - I_Zfinx + - I_Zdinxz + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg; + fcsr_val: $fcsr*/ \ No newline at end of file diff --git a/riscv_ctg/env/arch_test.h b/riscv_ctg/env/arch_test.h index eb4cb3e3..e93a7d54 100644 --- a/riscv_ctg/env/arch_test.h +++ b/riscv_ctg/env/arch_test.h @@ -86,13 +86,31 @@ #define FLREG fld #define FSREG fsd #define FREGWIDTH 8 - #define SIGALIGN 8 -#else - #if FLEN==32 +#elif FLEN==32 #define FLREG flw #define FSREG fsw #define FREGWIDTH 4 + #elif FLEN==16 + #define FLREG flh + #define FSREG fsh + #define FREGWIDTH 2 +#endif + +#if ZFINX==1 + #define FLREG ld + #define FSREG sd + #define FREGWIDTH 8 + #define FLEN 64 + #if XLEN==64 + #define SIGALIGN 8 + #else + #define SIGALIGN 4 #endif +#elif ZDINX==1 + #define FLREG LREG + #define FSREG SREG + #define FREGWIDTH 8 + #define FLEN 64 #endif #if FLEN>XLEN @@ -101,7 +119,6 @@ #define SIGALIGN REGWIDTH #endif - #if SIGALIGN==8 #define CANARY \ .dword 0x6F5CA309E7D4B281 @@ -109,7 +126,6 @@ #define CANARY \ .word 0x6F5CA309 #endif - #define MMODE_SIG 3 #define RLENG (REGWIDTH<<3) @@ -124,21 +140,34 @@ #endif #define NAN_BOXED(__val__,__width__,__max__) \ + .if __width__ == 16 ;\ + .hword __val__ ;\ + .endif ;\ .if __width__ == 32 ;\ .word __val__ ;\ - .else ;\ + .endif ;\ + .if __width__ == 64 ;\ .dword __val__ ;\ .endif ;\ - .if __max__ > __width__ ;\ - .set pref_bytes,(__max__-__width__)/32 ;\ + .if __max__ > __width__ ;\ + .if __width__ == 16 ;\ + .set pref_bytes,(__max__-__width__)/16;\ + .else ;\ + .set pref_bytes,(__max__-__width__)/32;\ + .endif ;\ .else ;\ .set pref_bytes, 0 ;\ .endif ;\ .rept pref_bytes ;\ - .word 0xffffffff ;\ + .if __width__ == 16 ;\ + .hword 0xffff ;\ + .else ;\ + .word 0xffffffff ;\ + .endif ;\ .endr ; + #define ZERO_EXTEND(__val__,__width__,__max__) \ .if __max__ > __width__ ;\ .set pref_bytes,(__max__-__width__)/32 ;\ @@ -1284,10 +1313,17 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg) inst destreg, x2,imm; \ ) +// Tests for instructions with single (rd/rs1) register operand. +#define TEST_CU_OP( inst, destreg, correctval, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(destreg, MASK_XLEN(val2)); \ + inst destreg; \ + ) //Tests for instructions with a single register operand -#define TEST_RD_OP(inst, destreg, reg1, correctval, val1, swreg, offset, testreg) \ +#define TEST_RD_OP(inst, destreg,reg1, correctval, val1, swreg, offset, testreg) \ TEST_CMV_OP(inst, destreg, reg1, correctval, val1, swreg, offset, testreg) + #define TEST_CBRANCH_OP(inst, tempreg, reg2, val2, imm, label, swreg, offset) \ LI(reg2, MASK_XLEN(val2)) ;\ j 2f ;\ diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index 6ac8afb3..9f3fc8d0 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -26,6 +26,12 @@ one_operand_dinstructions = ["fsqrt.d","fclass.d","fcvt.w.d","fcvt.wu.d","fcvt.d.w","fcvt.d.wu","fcvt.d.s","fcvt.s.d"] two_operand_dinstructions = ["fadd.d","fsub.d","fmul.d","fdiv.d","fmax.d","fmin.d","feq.d","flt.d","fle.d","fsgnj.d","fsgnjn.d","fsgnjx.d"] three_operand_dinstructions = ["fmadd.d","fmsub.d","fnmadd.d","fnmsub.d"] + +# H +one_operand_hinstructions = ["fsqrt.h","fclass.h","fcvt.w.h","fcvt.wu.h","fcvt.h.w","fcvt.h.wu","fcvt.h.l","fcvt.h.lu","fcvt.l.h","fcvt.d.h","fcvt.h.d","fcvt.s.h","fcvt.s.h"] +two_operand_hinstructions = ["fadd.h","fsub.h","fmul.h","fdiv.h","fmax.h","fmin.h","feq.h","flt.h","fle.h","fsgnj.h","fsgnjn.h","fsgnjx.h"] +three_operand_hinstructions = ["fmadd.h","fmsub.h","fnmadd.h","fnmsub.h"] + # Zfa/D: one_operand_dinstructions += ["fround.d", "froundnx.d"] two_operand_dinstructions += ["fmaxm.d", "fminm.d", "fleq.d", "fltq.d"] @@ -40,6 +46,7 @@ def is_fp_instruction(insn): ''' return type(insn) == str and insn.lower()[0] == 'f' + from riscv_ctg.dsp_function import * twos_xlen = lambda x: twos(x,xlen) @@ -73,11 +80,17 @@ def get_rm(opcode): 'ciformat': ['rd'], 'cssformat': ['rs2'], 'ciwformat': ['rd'], - 'clformat': ['rd', 'rs1'], + 'clformat': ['rs1', 'rd'], 'csformat': ['rs1', 'rs2'], 'caformat': ['rs1', 'rs2'], + 'cuformat': ['rs1'], 'cbformat': ['rs1'], + 'clbformat': ['rs1','rd'], + 'clhformat': ['rs1','rd'], + 'csbformat': ['rs1','rs2'], + 'cshformat': ['rs1','rs2'], 'cjformat': [], + 'ckformat': ['rs1'], 'kformat': ['rs1','rd'], 'ckformat': ['rs1'], # 'frformat': ['rs1', 'rs2', 'rd'], @@ -106,9 +119,11 @@ def get_rm(opcode): VALS = { 'rformat': "['rs1_val', 'rs2_val'] + ((get_rm(opcode)+['fcsr']) if is_fext else []) + \ - ([] if not is_nan_box else ['rs{0}_nan_prefix'.format(x) for x in range(1,3)])", + ([] if not is_nan_box else ['rs{0}_nan_prefix'.format(x) for x in range(1,3)]) + \ + (['rs{0}_sgn_prefix'.format(x) for x in range(1,3)] if is_sgn_extd else [])", 'r4format': "['rs1_val', 'rs2_val', 'rs3_val'] + (['rm_val','fcsr'] if is_fext else []) + \ - ([] if not is_nan_box else ['rs{0}_nan_prefix'.format(x) for x in range(1,4)])", + ([] if not is_nan_box else ['rs{0}_nan_prefix'.format(x) for x in range(1,4)]) + \ + (['rs{0}_sgn_prefix'.format(x) for x in range(1,4)] if is_sgn_extd else [])", 'iformat': "['rs1_val', 'imm_val'] + ([] if not is_fext else ['fcsr'])", 'sformat': "['rs1_val', 'rs2_val', 'imm_val'] + ([] if not is_fext else ['fcsr'])", 'bsformat': "['rs1_val', 'rs2_val', 'imm_val']", @@ -120,16 +135,23 @@ def get_rm(opcode): 'ciformat': "['rs1_val', 'imm_val']", 'cssformat': "['rs2_val', 'imm_val']", 'ciwformat': "['imm_val']", - 'clformat': "['rs1_val', 'imm_val']", + 'clformat': "['rs1_val', 'imm_val', 'fcsr']", + 'cuformat': "['rs1_val']", + 'clbformat': "['rs1_val','imm_val']", + 'clhformat': "['rs1_val','imm_val']", + 'csbformat': "['rs1_val','rs2_val','imm_val']", + 'cshformat': "['rs1_val','rs2_val','imm_val']", 'csformat': "['rs1_val', 'rs2_val', 'imm_val']", 'caformat': "['rs1_val', 'rs2_val']", 'cbformat': "['rs1_val', 'imm_val']", 'cjformat': "['imm_val']", + 'ckformat': "['rs1_val']", 'kformat': "['rs1_val']", 'ckformat': "['rs1_val']", # 'frformat': "['rs1_val', 'rs2_val', 'rm_val', 'fcsr']", - 'fsrformat': "['rs1_val', 'fcsr'] + get_rm(opcode) + \ - ([] if not is_nan_box else ['rs1_nan_prefix'])", + 'fsrformat': "['rs1_val','fcsr'] + get_rm(opcode) + \ + ([] if not is_nan_box else ['rs1_nan_prefix']) + \ + (['rs1_sgn_prefix'] if is_sgn_extd else [])", # 'fr4format': "['rs1_val', 'rs2_val', 'rs3_val', 'rm_val', 'fcsr']", 'pbrrformat': 'simd_val_vars("rs1", xlen, 8) + simd_val_vars("rs2", xlen, 8)', 'phrrformat': 'simd_val_vars("rs1", xlen, 16) + simd_val_vars("rs2", xlen, 16)', @@ -213,7 +235,7 @@ class Generator(): :type xl: int :type base_isa_str: str ''' - def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str): + def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str,inxFlag): ''' This is a Constructor function which initializes various class variables depending on the arguments. @@ -238,12 +260,13 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str): is_nan_box = False - is_fext = any(['F' in x or 'D' in x for x in opnode['isa']]) + is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x for x in opnode['isa']]) + is_sgn_extd = True if (inxFlag and iflen ifl: is_int_src = any([opcode.endswith(x) for x in ['.x','.w','.l','.wu','.lu']]) - is_nan_box = not is_int_src + is_nan_box = not is_int_src and is_sgn_extd self.xlen = xl self.flen = fl @@ -255,8 +278,10 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str): self.val_vars = eval(VALS[fmt]) self.is_fext = is_fext self.is_nan_box = is_nan_box + self.inxFlag = inxFlag + self.is_sgn_extd = is_sgn_extd - if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd"]: + if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd","flh","fsh","c.lbu","c.lhu","c.lh","c.sb","c.sh","c.flw"]: self.val_vars = self.val_vars + ['ea_align'] self.template = opnode['template'] self.opnode = opnode @@ -441,7 +466,7 @@ def valcomb(self, cgf): if self.is_fext: # fs + fe + fm -> Combiner Script try: - d = merge_fields_f(self.val_vars,req_val_comb,self.flen,self.iflen,merge) + d = merge_fields_f(self.val_vars,req_val_comb,self.flen,self.iflen,merge,self.inxFlag) except ExtractException as e: logger.warning("Valcomb skip: "+str(e)) continue @@ -811,7 +836,7 @@ def gen_inst(self,op_comb, val_comb, cgf): instr_dict.append(self.__fext_instr__(op,val)) elif self.opcode == 'c.lui': instr_dict.append(self.__clui_instr__(op,val)) - elif self.opcode in ['c.beqz', 'c.bnez']: + elif self.opcode in ['c.beqz', 'c.bnez','c.lbu','c.lhu','c.lh','c.sb','c.sh']: instr_dict.append(self.__cb_instr__(op,val)) elif self.opcode in ['c.lwsp', 'c.swsp', 'c.ldsp', 'c.sdsp']: instr_dict.append(self.__cmemsp_instr__(op,val)) @@ -853,6 +878,9 @@ def eval_inst_coverage(coverpoints,instr): for key in self.op_vars: var_dict[key] = instr[key] + + instr_obj = instructionObject(None, instr['inst'], None) + ext_specific_vars = instr_obj.evaluate_instr_var("ext_specific_vars", {**var_dict, 'flen': self.flen, 'iflen': self.iflen, 'inxFlag': self.inxFlag, 'xlen': self.xlen}, None, {'fcsr': hex(var_dict.get('fcsr', 0))}) insn = instr['inst'] # instructionObject() has an outdated list of instructions. # Let's make it support all FP instructions until this is fixed. @@ -861,6 +889,7 @@ def eval_inst_coverage(coverpoints,instr): insn = "fadd.s" instr_obj = instructionObject(None, insn, None) ext_specific_vars = instr_obj.evaluate_instr_var("ext_specific_vars", {**var_dict, 'flen': self.flen, 'iflen': self.iflen}, None, {'fcsr': hex(var_dict.get('fcsr', 0))}) + if ext_specific_vars is not None: var_dict.update(ext_specific_vars) @@ -910,7 +939,7 @@ def eval_inst_coverage(coverpoints,instr): cover_hits = eval_inst_coverage(cgf,instr) for entry in cover_hits: if entry=='val_comb' and skip_val: - continue + continue over = hits[entry] & cover_hits[entry] if over != cover_hits[entry]: unique = unique or True @@ -926,6 +955,7 @@ def eval_inst_coverage(coverpoints,instr): elif 'bit_width' in self.opnode: concat_simd_data(final_instr, self.xlen, self.opnode['bit_width']) + ''' Zacas introduces double xlen cas operations that need paired source and destination registers ''' @@ -933,7 +963,6 @@ def eval_inst_coverage(coverpoints,instr): if 'dcas_profile' in self.opnode: gen_pair_reg_data(final_instr, self.xlen, self.opnode['bit_width'], self.opnode['dcas_profile']) - return final_instr def valreg(self,instr_dict): @@ -984,7 +1013,7 @@ def valreg(self,instr_dict): SIGALIGN = max(XLEN,FLEN)/8 stride_sz = eval(suffix) template = Template(eval(self.opnode['val']['val_template'])) - width = self.iflen if self.is_fext else self.xlen + width = self.iflen if self.is_fext else self.flen for instr in instr_dict: if 'rs1' in instr and instr['rs1'] in available_reg: available_reg.remove(instr['rs1']) @@ -1019,6 +1048,9 @@ def valreg(self,instr_dict): if self.is_nan_box: dval = nan_box(instr_dict[i]['rs{0}_nan_prefix'.format(j)], instr_dict[i]['rs{0}_val'.format(j)],self.flen,self.iflen) + if self.is_sgn_extd: + dval = sgn_extd(instr_dict[i]['rs{0}_sgn_prefix'.format(j)], + instr_dict[i]['rs{0}_val'.format(j)],self.flen,self.iflen) else: dval = (instr_dict[i]['rs{0}_val'.format(j)],width) if self.is_fext: @@ -1301,7 +1333,7 @@ def write_test(self, fprefix, node, label, instr_dict, op_node, usage_str,max_in total = len(instr_dict) end = len(instr_dict) if max_inst: - end = max_inst + end = max_inst else: max_inst = total i = 1 @@ -1355,7 +1387,7 @@ def __write_test__(self, file_name,node,label,instr_dict, op_node, usage_str): dcas_profile = self.opnode['dcas_profile'] n = 0 - is_int_src = any([self.opcode.endswith(x) for x in ['.x','.w','.l','.wu','.lu']]) + is_int_src = any([self.opcode.endswith(x) for x in ['.x','.w','.l','.wu','.lu']]) or self.inxFlag src_len = xlen if self.opcode.endswith('.x') else (32 if 'w' in self.opcode else 64) sz = 'word' if src_len == 32 else 'dword' opcode = instr_dict[0]['inst'] diff --git a/riscv_ctg/helpers.py b/riscv_ctg/helpers.py index fd2f394c..ed8d2ca6 100644 --- a/riscv_ctg/helpers.py +++ b/riscv_ctg/helpers.py @@ -24,8 +24,18 @@ def nan_box(prefix,rs,flen,iflen): else: return (str(to_int(rs)|(to_int(prefix)< iflen: - nan_box = True + if inxFlag: + sgn_extd = True + else: + nan_box = True fdict = {} for var in val_vars: if var in num_dict and merge: @@ -64,6 +78,14 @@ def merge_fields_f(val_vars,cvp,flen,iflen,merge): fdict[nan_var] = eval(match_obj.group(nan_var)) else: fdict[nan_var] = (2**(flen-iflen))-1 + elif sgn_extd: + sgn_var = 'rs{0}_sgn_prefix'.format(num_dict[var]) + regex = val_regex.format(sgn_var.replace("_","\\_"),sgn_var) + match_obj = re.search(regex,cvp) + if match_obj is not None: + fdict[sgn_var] = eval(match_obj.group(sgn_var)) + else: + fdict[sgn_var] = (2**(flen-iflen))-1 else: regex = val_regex.format(var.replace("_","\\_"),var) match_obj = re.search(regex,cvp) diff --git a/riscv_ctg/main.py b/riscv_ctg/main.py index 0e0bc30d..98d172e3 100644 --- a/riscv_ctg/main.py +++ b/riscv_ctg/main.py @@ -17,13 +17,14 @@ @click.option('--procs','-p',type=int,default=1,help='Max number of processes to spawn') @click.option('--base-isa','-bi',type=click.Choice(['rv32e','rv32i','rv64i']),help="Base ISA string for the tests.") @click.option('--flen','-fl',type=click.Choice(['32','64','0']),help="Value of FLEN in\ - hardware.",default='0') + hardware.",default='32') @click.option("--inst",type=int,help="Maximum number of Macro Instances per test.") -def cli(verbose, out_dir, randomize , cgf,procs,base_isa, flen,inst): +@click.option("--z-inx", '-ix', type=bool, default='False', help="If the extension is Z*inx then pass True otherwise defaulted to False") +def cli(verbose, out_dir, randomize , cgf,procs,base_isa, flen,inst,z_inx): if not os.path.exists(out_dir): os.mkdir(out_dir) if '32' in base_isa: xlen = 32 elif '64' in base_isa: xlen = 64 - ctg(verbose, out_dir, randomize ,xlen, int(flen), cgf,procs,base_isa,inst) + ctg(verbose, out_dir, randomize ,xlen, int(flen), cgf,procs,base_isa,inst,z_inx) diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fadd.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fadd.cgf new file mode 100644 index 00000000..cf5c4301 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fadd.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fadd_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fadd.h", 2)': 0 + +fadd_b2: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fadd.h", 2)': 0 + +fadd_b3: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fadd.h", 2)': 0 + +fadd_b4: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fadd.h", 2)': 0 + +fadd_b5: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fadd.h", 2)': 0 + +fadd_b7: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fadd.h", 2)': 0 + +fadd_b8: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fadd.h", 2)': 0 + +fadd_b10: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b10(flen,16, "fadd.h", 2)': 0 + +fadd_b11: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b11(flen,16, "fadd.h", 2)': 0 + +fadd_b12: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b12(flen,16, "fadd.h", 2)': 0 + +fadd_b13: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b13(flen,16, "fadd.h", 2)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fclass.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fclass.cgf new file mode 100644 index 00000000..f83b1a8a --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fclass.cgf @@ -0,0 +1,15 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fclass_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fclass.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fclass.h", 1)': 0 + diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf new file mode 100644 index 00000000..1d47c5cf --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf @@ -0,0 +1,106 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.d.h_b1: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b22: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b23: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b24: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b27: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b28: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.d.h", 1)': 0 + +fcvt.d.h_b29: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.d.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.d.h", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf new file mode 100644 index 00000000..07af2333 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf @@ -0,0 +1,106 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.d_b1: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b22: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b23: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b24: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b27: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b28: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fcvt.h.d", 1)': 0 + +fcvt.h.d_b29: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + mnemonics: + fcvt.h.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fcvt.h.d", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.l.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.l.cgf new file mode 100644 index 00000000..45e9c45f --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.l.cgf @@ -0,0 +1,27 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.l_b25: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + opcode: + fcvt.h.l: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,16, "fcvt.h.l", 1)': 0 + +fcvt.h.l_b26: + config: + - check ISA:=regex(.*I.*F.*D.*Zfh.*) + opcode: + fcvt.h.l: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(16, "fcvt.h.l", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.lu.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.lu.cgf new file mode 100644 index 00000000..886da150 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.lu.cgf @@ -0,0 +1,27 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.lu_b25: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.lu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,16, "fcvt.h.lu", 1)': 0 + +fcvt.h.lu_b26: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.lu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(16, "fcvt.h.lu", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf new file mode 100644 index 00000000..5ddc2fa5 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf @@ -0,0 +1,106 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.s_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b22: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b23: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b24: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b27: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b28: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,32, "fcvt.h.s", 1)': 0 + +fcvt.h.s_b29: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,32, "fcvt.h.s", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.w.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.w.cgf new file mode 100644 index 00000000..cd976f40 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.w.cgf @@ -0,0 +1,27 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.w_b25: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.w: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,32, "fcvt.h.w", 1)': 0 + +fcvt.h.w_b26: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.w: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(32, "fcvt.h.w", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.wu.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.wu.cgf new file mode 100644 index 00000000..ee7cad70 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.wu.cgf @@ -0,0 +1,27 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.wu_b25: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.wu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,32, "fcvt.h.wu", 1)': 0 + +fcvt.h.wu_b26: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.wu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(32, "fcvt.h.wu", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf new file mode 100644 index 00000000..ba74626b --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf @@ -0,0 +1,106 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.s.h_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b22: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b23: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b24: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b27: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b28: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.s.h", 1)': 0 + +fcvt.s.h_b29: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.s.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.s.h", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf new file mode 100644 index 00000000..8ce3cbd0 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.w.h_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.w.h", 1)': 0 + +fcvt.w.h_b22: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.w.h", 1)': 0 + +fcvt.w.h_b23: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.w.h", 1)': 0 + +fcvt.w.h_b24: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.w.h", 1)': 0 + +fcvt.w.h_b27: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.w.h", 1)': 0 + +fcvt.w.h_b28: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.w.h", 1)': 0 + +fcvt.w.h_b29: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.w.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.w.h", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf new file mode 100644 index 00000000..667accdf --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.wu.h_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.wu.h", 1)': 0 + +fcvt.wu.h_b22: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fcvt.wu.h", 1)': 0 + +fcvt.wu.h_b23: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fcvt.wu.h", 1)': 0 + +fcvt.wu.h_b24: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fcvt.wu.h", 1)': 0 + +fcvt.wu.h_b27: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fcvt.wu.h", 1)': 0 + +fcvt.wu.h_b28: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fcvt.wu.h", 1)': 0 + +fcvt.wu.h_b29: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.wu.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,16, "fcvt.wu.h", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fdiv.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fdiv.cgf new file mode 100644 index 00000000..afbfb25c --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fdiv.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fdiv_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fdiv.h", 2)': 0 + +fdiv_b2: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fdiv.h", 2)': 0 + +fdiv_b3: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fdiv.h", 2)': 0 + +fdiv_b4: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fdiv.h", 2)': 0 + +fdiv_b5: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fdiv.h", 2)': 0 + +fdiv_b6: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fdiv.h", 2)': 0 + +fdiv_b7: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fdiv.h", 2)': 0 + +fdiv_b8: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fdiv.h", 2)': 0 + +fdiv_b9: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,16, "fdiv.h", 2)': 0 + +fdiv_b20: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b20(flen,16, "fdiv.h", 2)': 0 + +fdiv_b21: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fdiv.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b21(flen,16, "fdiv.h", 2)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_feq.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_feq.cgf new file mode 100644 index 00000000..65e332ab --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_feq.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +feq_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + feq.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "feq.h", 2)': 0 + +feq_b19: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + feq.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,16, "feq.h", 2)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fle.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fle.cgf new file mode 100644 index 00000000..b3747e79 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fle.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fle_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fle.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fle.h", 2)': 0 + +fle_b19: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fle.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,16, "fle.h", 2)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_flh.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_flh.cgf new file mode 100644 index 00000000..d0c0bc98 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_flh.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +flh-align: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + flh: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_fregs + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_flt.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_flt.cgf new file mode 100644 index 00000000..863f2df3 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_flt.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +flt_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + flt.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 16, "flt.h", 2)': 0 + +flt_b19: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + flt.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,16, "flt.h", 2)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmadd.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmadd.cgf new file mode 100644 index 00000000..4725656f --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmadd.cgf @@ -0,0 +1,229 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmadd_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmadd.h", 3)': 0 + +fmadd_b2: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fmadd.h", 3)': 0 + +fmadd_b3: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fmadd.h", 3)': 0 + +fmadd_b4: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fmadd.h", 3)': 0 + +fmadd_b5: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fmadd.h", 3)': 0 + +fmadd_b6: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fmadd.h", 3)': 0 + +fmadd_b7: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fmadd.h", 3)': 0 + +fmadd_b8: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fmadd.h", 3)': 0 + +fmadd_b14: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,16, "fmadd.h", 3)': 0 + +fmadd_b16: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,16, "fmadd.h", 3)': 0 + +fmadd_b17: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,16, "fmadd.h", 3)': 0 + +fmadd_b18: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,16, "fmadd.h", 3)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmax.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmax.cgf new file mode 100644 index 00000000..f9d08a40 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmax.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmax_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmax.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmax.h", 2)': 0 + +fmax_b19: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmax.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,16, "fmax.h", 2)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmin.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmin.cgf new file mode 100644 index 00000000..91db1bf1 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmin.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmin_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmin.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmin.h", 2)': 0 + +fmin_b19: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmin.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,16, "fmin.h", 2)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmsub.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmsub.cgf new file mode 100644 index 00000000..ea60b6b2 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmsub.cgf @@ -0,0 +1,229 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmsub_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmsub.h", 3)': 0 + +fmsub_b2: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fmsub.h", 3)': 0 + +fmsub_b3: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fmsub.h", 3)': 0 + +fmsub_b4: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fmsub.h", 3)': 0 + +fmsub_b5: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fmsub.h", 3)': 0 + +fmsub_b6: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fmsub.h", 3)': 0 + +fmsub_b7: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fmsub.h", 3)': 0 + +fmsub_b8: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fmsub.h", 3)': 0 + +fmsub_b14: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,16, "fmsub.h", 3)': 0 + +fmsub_b16: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,16, "fmsub.h", 3)': 0 + +fmsub_b17: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,16, "fmsub.h", 3)': 0 + +fmsub_b18: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,16, "fmsub.h", 3)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmul.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmul.cgf new file mode 100644 index 00000000..f53aefee --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmul.cgf @@ -0,0 +1,155 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmul_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmul.h", 2)': 0 + +fmul_b2: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fmul.h", 2)': 0 + +fmul_b3: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fmul.h", 2)': 0 + +fmul_b4: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fmul.h", 2)': 0 + +fmul_b5: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fmul.h", 2)': 0 + +fmul_b6: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fmul.h", 2)': 0 + +fmul_b7: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fmul.h", 2)': 0 + +fmul_b8: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fmul.h", 2)': 0 + +fmul_b9: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmul.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,16, "fmul.h", 2)': 0 + diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmv.h.x.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmv.h.x.cgf new file mode 100644 index 00000000..1a24a485 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmv.h.x.cgf @@ -0,0 +1,28 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmv.h.x_b25: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmv.h.x: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,32, "fmv.h.x", 1)': 0 + +fmv.h.x_b26: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmv.h.x: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(flen,"fmv.h.x", 1)': 0 + diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmv.x.h.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmv.x.h.cgf new file mode 100644 index 00000000..3f6fb185 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmv.x.h.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmv.x.h_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmv.x.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fmv.x.h", 1)': 0 + +fmv.x.h_b22: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmv.x.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,16, "fmv.x.h", 1)': 0 + +fmv.x.h_b23: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmv.x.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,16, "fmv.x.h", 1)': 0 + +fmv.x.h_b24: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmv.x.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,16, "fmv.x.h", 1)': 0 + +fmv.x.h_b27: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmv.x.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,16, "fmv.x.h", 1)': 0 + +fmv.x.h_b28: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmv.x.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,16, "fmv.x.h", 1)': 0 + +fmv.x.h_b29: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fmv.x.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen, 16, "fmv.x.h", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fnmadd.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fnmadd.cgf new file mode 100644 index 00000000..92ebf1ac --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fnmadd.cgf @@ -0,0 +1,229 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fnmadd_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fnmadd.h", 3)': 0 + +fnmadd_b2: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fnmadd.h", 3)': 0 + +fnmadd_b3: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fnmadd.h", 3)': 0 + +fnmadd_b4: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fnmadd.h", 3)': 0 + +fnmadd_b5: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fnmadd.h", 3)': 0 + +fnmadd_b6: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fnmadd.h", 3)': 0 + +fnmadd_b7: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fnmadd.h", 3)': 0 + +fnmadd_b8: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fnmadd.h", 3)': 0 + +fnmadd_b14: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,16, "fnmadd.h", 3)': 0 + +fnmadd_b16: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,16, "fnmadd.h", 3)': 0 + +fnmadd_b17: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,16, "fnmadd.h", 3)': 0 + +fnmadd_b18: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmadd.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,16, "fnmadd.h", 3)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fnmsub.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fnmsub.cgf new file mode 100644 index 00000000..f59970de --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fnmsub.cgf @@ -0,0 +1,229 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fnmsub_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fnmsub.h", 3)': 0 + +fnmsub_b2: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fnmsub.h", 3)': 0 + +fnmsub_b3: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fnmsub.h", 3)': 0 + +fnmsub_b4: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fnmsub.h", 3)': 0 + +fnmsub_b5: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fnmsub.h", 3)': 0 + +fnmsub_b6: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,16, "fnmsub.h", 3)': 0 + +fnmsub_b7: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fnmsub.h", 3)': 0 + +fnmsub_b8: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fnmsub.h", 3)': 0 + +fnmsub_b14: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,16, "fnmsub.h", 3)': 0 + +fnmsub_b16: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,16, "fnmsub.h", 3)': 0 + +fnmsub_b17: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,16, "fnmsub.h", 3)': 0 + +fnmsub_b18: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fnmsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,16, "fnmsub.h", 3)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsgnj.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsgnj.cgf new file mode 100644 index 00000000..f325b0aa --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsgnj.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnj_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsgnj.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fsgnj.h", 2)': 0 + diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsgnjn.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsgnjn.cgf new file mode 100644 index 00000000..d371df88 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsgnjn.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnjn_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsgnjn.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fsgnjn.h", 2)': 0 + diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsgnjx.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsgnjx.cgf new file mode 100644 index 00000000..b0cc19c8 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsgnjx.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnjx_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsgnjx.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fsgnjx.h", 2)': 0 + diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsh.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsh.cgf new file mode 100644 index 00000000..a3bb9b93 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsh.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsh-align: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsh: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_fregs + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsqrt.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsqrt.cgf new file mode 100644 index 00000000..91686f9e --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsqrt.cgf @@ -0,0 +1,136 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsqrt_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fsqrt.h", 1)': 0 + +fsqrt_b2: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fsqrt.h", 1)': 0 + +fsqrt_b3: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fsqrt.h", 1)': 0 + +fsqrt_b4: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fsqrt.h", 1)': 0 + +fsqrt_b5: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fsqrt.h", 1)': 0 + +fsqrt_b7: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fsqrt.h", 1)': 0 + +fsqrt_b8: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fsqrt.h", 1)': 0 + +fsqrt_b9: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,16, "fsqrt.h", 1)': 0 + +fsqrt_b20: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsqrt.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b20(flen,16, "fsqrt.h", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsub.cgf b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsub.cgf new file mode 100644 index 00000000..5fe7229d --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fsub.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsub_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fsub.h", 2)': 0 + +fsub_b2: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,16, "fsub.h", 2)': 0 + +fsub_b3: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,16, "fsub.h", 2)': 0 + +fsub_b4: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,16, "fsub.h", 2)': 0 + +fsub_b5: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,16, "fsub.h", 2)': 0 + +fsub_b7: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,16, "fsub.h", 2)': 0 + +fsub_b8: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,16, "fsub.h", 2)': 0 + +fsub_b10: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b10(flen,16, "fsub.h", 2)': 0 + +fsub_b11: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b11(flen,16, "fsub.h", 2)': 0 + +fsub_b12: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b12(flen,16, "fsub.h", 2)': 0 + +fsub_b13: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fsub.h: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b13(flen,16, "fsub.h", 2)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.l.cgf b/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.l.cgf new file mode 100644 index 00000000..57e8900b --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.l.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.l_b25: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.l: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,64, "fcvt.h.l", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.lu.cgf b/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.lu.cgf new file mode 100644 index 00000000..b079a5da --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.h.lu.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.h.lu_b25: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + opcode: + fcvt.h.lu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,64, "fcvt.h.lu", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.l.h.cgf b/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.l.h.cgf new file mode 100644 index 00000000..7a3290cf --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.l.h.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.l.h_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.l.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.l.h", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.lu.h.cgf b/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.lu.h.cgf new file mode 100644 index 00000000..1077ecdd --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64H/rv64h_fcvt.lu.h.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.lu.h_b1: + config: + - check ISA:=regex(.*I.*F.*Zfh.*) + mnemonics: + fcvt.lu.h: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,16, "fcvt.lu.h", 1)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fadd.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fadd.s.cgf new file mode 100644 index 00000000..a49a5ad0 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fadd.s.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fadd_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fadd.s", 2, True)': 0 + +fadd_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fadd.s", 2, True)': 0 + +fadd_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fadd.s", 2, True)': 0 + +fadd_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fadd.s", 2, True)': 0 + +fadd_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fadd.s", 2, True)': 0 + +fadd_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fadd.s", 2, True)': 0 + +fadd_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fadd.s", 2, True)': 0 + +fadd_b10: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b10(flen,32, "fadd.s", 2, True)': 0 + +fadd_b11: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b11(flen,32, "fadd.s", 2, True)': 0 + +fadd_b12: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b12(flen,32, "fadd.s", 2, True)': 0 + +fadd_b13: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b13(flen,32, "fadd.s", 2, True)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fclass.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fclass.s.cgf new file mode 100644 index 00000000..61b12b71 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fclass.s.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fclass_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fclass.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fclass.s", 1, True)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.l.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.l.s.cgf new file mode 100644 index 00000000..23f0b793 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.l.s.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.l.s_b1: + config: + - check ISA:=regex(.*RV64.*I.*Zfinx.*) + mnemonics: + fcvt.l.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fcvt.l.s", 1, True)': 0 + +fcvt.l.s_b22: + config: + - check ISA:=regex(.*RV64.*I.*Zfinx.*) + mnemonics: + fcvt.l.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,32, "fcvt.l.s", 1, True)': 0 + +fcvt.l.s_b23: + config: + - check ISA:=regex(.*RV64.*I.*Zfinx.*) + mnemonics: + fcvt.l.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,32, "fcvt.l.s", 1, True)': 0 + +fcvt.l.s_b24: + config: + - check ISA:=regex(.*RV64.*I.*Zfinx.*) + mnemonics: + fcvt.l.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,32, "fcvt.l.s", 1, True)': 0 + +fcvt.l.s_b27: + config: + - check ISA:=regex(.*RV64.*I.*Zfinx.*) + mnemonics: + fcvt.l.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,32, "fcvt.l.s", 1, True)': 0 + +fcvt.l.s_b28: + config: + - check ISA:=regex(.*RV64.*I.*Zfinx.*) + mnemonics: + fcvt.l.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,32, "fcvt.l.s", 1, True)': 0 + +fcvt.l.s_b29: + config: + - check ISA:=regex(.*RV64.*I.*Zfinx.*) + mnemonics: + fcvt.l.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,32, "fcvt.l.s", 1, True)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.lu.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.lu.s.cgf new file mode 100644 index 00000000..6453ece2 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.lu.s.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.lu.s_b1: + config: + - check ISA:=regex(.*RV64.*I.*Zfinx.*) + mnemonics: + fcvt.lu.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fcvt.lu.s", 1, True)': 0 + +fcvt.lu.s_b22: + config: + - check ISA:=regex(.*RV64.*I.*Zfinx.*) + mnemonics: + fcvt.lu.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,32, "fcvt.lu.s", 1, True)': 0 + +fcvt.lu.s_b23: + config: + - check ISA:=regex(.*RV64.*I.*Zfinx.*) + mnemonics: + fcvt.lu.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,32, "fcvt.lu.s", 1, True)': 0 + +fcvt.lu.s_b24: + config: + - check ISA:=regex(.*RV64.*I.*Zfinx.*) + mnemonics: + fcvt.lu.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,32, "fcvt.lu.s", 1, True)': 0 + +fcvt.lu.s_b27: + config: + - check ISA:=regex(.*RV64.*I.*Zfinx.*) + mnemonics: + fcvt.lu.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,32, "fcvt.lu.s", 1, True)': 0 + +fcvt.lu.s_b28: + config: + - check ISA:=regex(.*RV64.*I.*Zfinx.*) + mnemonics: + fcvt.lu.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,32, "fcvt.lu.s", 1, True)': 0 + +fcvt.lu.s_b29: + config: + - check ISA:=regex(.*RV64.*I.*Zfinx.*) + mnemonics: + fcvt.lu.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,32, "fcvt.lu.s", 1, True)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.w.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.w.s.cgf new file mode 100644 index 00000000..b00ad8ab --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.w.s.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.w.s_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fcvt.w.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fcvt.w.s", 1, True)': 0 + +fcvt.w.s_b22: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fcvt.w.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,32, "fcvt.w.s", 1, True)': 0 + +fcvt.w.s_b23: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fcvt.w.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,32, "fcvt.w.s", 1, True)': 0 + +fcvt.w.s_b24: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fcvt.w.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,32, "fcvt.w.s", 1, True)': 0 + +fcvt.w.s_b27: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fcvt.w.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,32, "fcvt.w.s", 1, True)': 0 + +fcvt.w.s_b28: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fcvt.w.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,32, "fcvt.w.s", 1, True)': 0 + +fcvt.w.s_b29: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fcvt.w.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,32, "fcvt.w.s", 1, True)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.wu.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.wu.s.cgf new file mode 100644 index 00000000..ad4dec66 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fcvt.wu.s.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.wu.s_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fcvt.wu.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fcvt.wu.s", 1, True)': 0 + +fcvt.wu.s_b22: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fcvt.wu.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,32, "fcvt.wu.s", 1, True)': 0 + +fcvt.wu.s_b23: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fcvt.wu.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,32, "fcvt.wu.s", 1, True)': 0 + +fcvt.wu.s_b24: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fcvt.wu.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,32, "fcvt.wu.s", 1, True)': 0 + +fcvt.wu.s_b27: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fcvt.wu.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,32, "fcvt.wu.s", 1, True)': 0 + +fcvt.wu.s_b28: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fcvt.wu.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,32, "fcvt.wu.s", 1, True)': 0 + +fcvt.wu.s_b29: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fcvt.wu.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,32, "fcvt.wu.s", 1, True)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fdiv.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fdiv.s.cgf new file mode 100644 index 00000000..20191510 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fdiv.s.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fdiv_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fdiv.s", 2, True)': 0 + +fdiv_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fdiv.s", 2, True)': 0 + +fdiv_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fdiv.s", 2, True)': 0 + +fdiv_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fdiv.s", 2, True)': 0 + +fdiv_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fdiv.s", 2, True)': 0 + +fdiv_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,32, "fdiv.s", 2, True)': 0 + +fdiv_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fdiv.s", 2, True)': 0 + +fdiv_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fdiv.s", 2, True)': 0 + +fdiv_b9: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,32, "fdiv.s", 2, True)': 0 + +fdiv_b20: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b20(flen,32, "fdiv.s", 2, True)': 0 + +fdiv_b21: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b21(flen,32, "fdiv.s", 2, True)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/feq.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/feq.s.cgf new file mode 100644 index 00000000..abe30ff1 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/feq.s.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +feq_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + feq.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "feq.s", 2, True)': 0 + +feq_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + feq.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,32, "feq.s", 2, True)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fle.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fle.s.cgf new file mode 100644 index 00000000..8ad88e5e --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fle.s.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fle_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fle.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fle.s", 2, True)': 0 + +fle_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fle.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,32, "fle.s", 2, True)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/flt.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/flt.s.cgf new file mode 100644 index 00000000..e947d2a2 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/flt.s.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +flt_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + flt.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "flt.s", 2, True)': 0 + +flt_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + flt.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 32, "flt.s", 2, True)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmadd.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmadd.s.cgf new file mode 100644 index 00000000..e44f02fd --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmadd.s.cgf @@ -0,0 +1,248 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmadd_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fmadd.s", 3, True)': 0 + +fmadd_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fmadd.s", 3, True)': 0 + +fmadd_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fmadd.s", 3, True)': 0 + +fmadd_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fmadd.s", 3, True)': 0 + +fmadd_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fmadd.s", 3, True)': 0 + +fmadd_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,32, "fmadd.s", 3, True)': 0 + +fmadd_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fmadd.s", 3, True)': 0 + +fmadd_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fmadd.s", 3, True)': 0 + +fmadd_b14: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,32, "fmadd.s", 3, True)': 0 + +fmadd_b15: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b15(flen,32, "fmadd.s", 3, True)': 0 + +fmadd_b16: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,32, "fmadd.s", 3, True)': 0 + +fmadd_b17: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,32, "fmadd.s", 3, True)': 0 + +fmadd_b18: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,32, "fmadd.s", 3, True)': 0 \ No newline at end of file diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmax.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmax.s.cgf new file mode 100644 index 00000000..74693109 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmax.s.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmax_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmax.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fmax.s", 2, True)': 0 + +fmax_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmax.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,32, "fmax.s", 2, True)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmin.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmin.s.cgf new file mode 100644 index 00000000..fdbeeced --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmin.s.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmin_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmin.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fmin.s", 2, True)': 0 + +fmin_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmin.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,32, "fmin.s", 2, True)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmsub.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmsub.s.cgf new file mode 100644 index 00000000..37f87d22 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmsub.s.cgf @@ -0,0 +1,247 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore +fmsub_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fmsub.s", 3, True)': 0 + +fmsub_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fmsub.s", 3, True)': 0 + +fmsub_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fmsub.s", 3, True)': 0 + +fmsub_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fmsub.s", 3, True)': 0 + +fmsub_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fmsub.s", 3, True)': 0 + +fmsub_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,32, "fmsub.s", 3, True)': 0 + +fmsub_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fmsub.s", 3, True)': 0 + +fmsub_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fmsub.s", 3, True)': 0 + +fmsub_b14: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,32, "fmsub.s", 3, True)': 0 + +fmsub_b15: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b15(flen,32, "fmsub.s", 3, True)': 0 + +fmsub_b16: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,32, "fmsub.s", 3, True)': 0 + +fmsub_b17: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,32, "fmsub.s", 3, True)': 0 + +fmsub_b18: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,32, "fmsub.s", 3, True)': 0 \ No newline at end of file diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmul.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmul.s.cgf new file mode 100644 index 00000000..624f49ff --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fmul.s.cgf @@ -0,0 +1,155 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmul_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fmul.s", 2, True)': 0 + +fmul_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fmul.s", 2, True)': 0 + +fmul_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fmul.s", 2, True)': 0 + +fmul_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fmul.s", 2, True)': 0 + +fmul_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fmul.s", 2, True)': 0 + +fmul_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,32, "fmul.s", 2, True)': 0 + +fmul_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fmul.s", 2, True)': 0 + +fmul_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fmul.s", 2, True)': 0 + +fmul_b9: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,32, "fmul.s", 2, True)': 0 + diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fnmadd.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fnmadd.s.cgf new file mode 100644 index 00000000..582b3c40 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fnmadd.s.cgf @@ -0,0 +1,247 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore +fnmadd_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fnmadd.s", 3, True)': 0 + +fnmadd_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fnmadd.s", 3, True)': 0 + +fnmadd_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fnmadd.s", 3, True)': 0 + +fnmadd_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fnmadd.s", 3, True)': 0 + +fnmadd_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fnmadd.s", 3, True)': 0 + +fnmadd_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,32, "fnmadd.s", 3, True)': 0 + +fnmadd_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fnmadd.s", 3, True)': 0 + +fnmadd_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fnmadd.s", 3, True)': 0 + +fnmadd_b14: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,32, "fnmadd.s", 3, True)': 0 + +fnmadd_b15: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b15(flen,32, "fnmadd.s", 3, True)': 0 + +fnmadd_b16: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,32, "fnmadd.s", 3, True)': 0 + +fnmadd_b17: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,32, "fnmadd.s", 3, True)': 0 + +fnmadd_b18: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,32, "fnmadd.s", 3, True)': 0 \ No newline at end of file diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fnmsub.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fnmsub.s.cgf new file mode 100644 index 00000000..73c7e341 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fnmsub.s.cgf @@ -0,0 +1,247 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore +fnmsub_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fnmsub.s", 3, True)': 0 + +fnmsub_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fnmsub.s", 3, True)': 0 + +fnmsub_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fnmsub.s", 3, True)': 0 + +fnmsub_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fnmsub.s", 3, True)': 0 + +fnmsub_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fnmsub.s", 3, True)': 0 + +fnmsub_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,32, "fnmsub.s", 3, True)': 0 + +fnmsub_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fnmsub.s", 3, True)': 0 + +fnmsub_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fnmsub.s", 3, True)': 0 + +fnmsub_b14: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,32, "fnmsub.s", 3, True)': 0 + +fnmsub_b15: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b15(flen,32, "fnmsub.s", 3, True)': 0 + +fnmsub_b16: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,32, "fnmsub.s", 3, True)': 0 + +fnmsub_b17: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,32, "fnmsub.s", 3, True)': 0 + +fnmsub_b18: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rs3: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,32, "fnmsub.s", 3, True)': 0 \ No newline at end of file diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsgnj.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsgnj.s.cgf new file mode 100644 index 00000000..46a03b03 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsgnj.s.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnj_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsgnj.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fsgnj.s", 2, True)': 0 + diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsgnjn.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsgnjn.s.cgf new file mode 100644 index 00000000..81ae1f94 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsgnjn.s.cgf @@ -0,0 +1,17 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore +fsgnjn_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsgnjn.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fsgnjn.s", 2, True)': 0 \ No newline at end of file diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsgnjx.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsgnjx.s.cgf new file mode 100644 index 00000000..bc84394d --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsgnjx.s.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnjx_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsgnjx.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fsgnjx.s", 2, True)': 0 + diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsqrt.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsqrt.s.cgf new file mode 100644 index 00000000..bb3170fa --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsqrt.s.cgf @@ -0,0 +1,136 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsqrt_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fsqrt.s", 1, True)': 0 + +fsqrt_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fsqrt.s", 1, True)': 0 + +fsqrt_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fsqrt.s", 1, True)': 0 + +fsqrt_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fsqrt.s", 1, True)': 0 + +fsqrt_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fsqrt.s", 1, True)': 0 + +fsqrt_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fsqrt.s", 1, True)': 0 + +fsqrt_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fsqrt.s", 1, True)': 0 + +fsqrt_b9: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,32, "fsqrt.s", 1, True)': 0 + +fsqrt_b20: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b20(flen,32, "fsqrt.s", 1, True)': 0 \ No newline at end of file diff --git a/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsub.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsub.s.cgf new file mode 100644 index 00000000..0f5aa2d7 --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/RV64Zfinx/fsub.s.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsub_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fsub.s", 2, True)': 0 + +fsub_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fsub.s", 2, True)': 0 + +fsub_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fsub.s", 2, True)': 0 + +fsub_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fsub.s", 2, True)': 0 + +fsub_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fsub.s", 2, True)': 0 + +fsub_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fsub.s", 2, True)': 0 + +fsub_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fsub.s", 2, True)': 0 + +fsub_b10: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b10(flen,32, "fsub.s", 2, True)': 0 + +fsub_b11: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b11(flen,32, "fsub.s", 2, True)': 0 + +fsub_b12: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b12(flen,32, "fsub.s", 2, True)': 0 + +fsub_b13: + config: + - check ISA:=regex(.*I.*Zfinx.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b13(flen,32, "fsub.s", 2, True)': 0 \ No newline at end of file