From 3ed8269b598a7b9a363b86d24034cc854a320775 Mon Sep 17 00:00:00 2001 From: Yu-Cheng Chang Date: Thu, 18 Jul 2024 15:50:33 +0800 Subject: [PATCH 1/4] Add coverage for misalign1-cjalr and misalign1-cjr (#116) * Add coverage for misalign1-cjalr and misalign1-cjr Signed-off-by: Roger Chang * Add ea_align_data for c.jalr and c.jr --------- Signed-off-by: Roger Chang --- riscv_ctg/data/imc.yaml | 2 ++ riscv_ctg/generator.py | 4 ++-- sample_cgfs/rv32i_priv.cgf | 16 ++++++++++++++++ sample_cgfs/rv64i_priv.cgf | 16 ++++++++++++++++ 4 files changed, 36 insertions(+), 2 deletions(-) diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml index be5b1995..d77570ef 100644 --- a/riscv_ctg/data/imc.yaml +++ b/riscv_ctg/data/imc.yaml @@ -1862,6 +1862,7 @@ c.jr: isa: - IC formattype: 'crformat' + ea_align_data: '[0,1]' rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' template: |- @@ -1880,6 +1881,7 @@ c.jalr: isa: - IC formattype: 'crformat' + ea_align_data: '[0,1]' rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' template: |- diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index 5bf34f68..6ac8afb3 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -256,7 +256,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str): self.is_fext = is_fext self.is_nan_box = is_nan_box - if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","flw","fsw","fld","fsd"]: + if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd"]: self.val_vars = self.val_vars + ['ea_align'] self.template = opnode['template'] self.opnode = opnode @@ -1417,4 +1417,4 @@ def __write_test__(self, file_name,node,label,instr_dict, op_node, usage_str): sign.append("#ifdef rvtest_gpr_save\n"+signode_template.substitute( {'n':32,'label':"gpr_save",'sz':'XLEN/32'})+"\n#endif\n") with open(file_name,"w") as fd: - fd.write(usage_str + test_template.safe_substitute(data='\n'.join(data),test=test,sig='\n'.join(sign),isa=op_node_isa,opcode=opcode,extension=extension,label=label)) \ No newline at end of file + fd.write(usage_str + test_template.safe_substitute(data='\n'.join(data),test=test,sig='\n'.join(sign),isa=op_node_isa,opcode=opcode,extension=extension,label=label)) diff --git a/sample_cgfs/rv32i_priv.cgf b/sample_cgfs/rv32i_priv.cgf index 94131f0a..2575375e 100644 --- a/sample_cgfs/rv32i_priv.cgf +++ b/sample_cgfs/rv32i_priv.cgf @@ -85,6 +85,22 @@ misalign1-jalr: 'imm_val%2 == 1 and ea_align == 1': 0 'imm_val%2 == 0 and ea_align == 1': 0 +misalign1-cjalr: + config: + - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True + mnemonics: + c.jalr: 0 + val_comb: + 'ea_align == 1': 0 + +misalign1-cjr: + config: + - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True + mnemonics: + c.jr: 0 + val_comb: + 'ea_align == 1': 0 + misalign-jal: config: - check ISA:=regex(.*I.*C.*) diff --git a/sample_cgfs/rv64i_priv.cgf b/sample_cgfs/rv64i_priv.cgf index 8babd644..ba51952b 100644 --- a/sample_cgfs/rv64i_priv.cgf +++ b/sample_cgfs/rv64i_priv.cgf @@ -126,6 +126,22 @@ misalign1-jalr: val_comb: 'ea_align == 1': 0 +misalign1-cjalr: + config: + - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True + mnemonics: + c.jalr: 0 + val_comb: + 'ea_align == 1': 0 + +misalign1-cjr: + config: + - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True + mnemonics: + c.jr: 0 + val_comb: + 'ea_align == 1': 0 + misalign-jal: config: - check ISA:=regex(.*I.*C.*) From 15c8ee90a3f7a5676cb4ee8b11945f5b3e3871a4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20M=C3=BCllner?= Date: Fri, 19 Jul 2024 08:07:00 +0200 Subject: [PATCH 2/4] Initial covergroups for Zvk* instructions (#61) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Initial covergroups for Zvk* instructions This patch introduces initial versions of covergroups for the Zvk* instructions. The lack of vector support makes these pretty useless, but once this is available it should not be too hard to adjust these. Support for RV32 and RV64 is added, but both versions are identical. Signed-off-by: Christoph Müllner * Update CHANGELOG.md Updated ChangeLOG file and resolved conflicts Signed-off-by: Umer Shahid * Update CHANGELOG.md Merged version number to resolve the conflict with __init__.py Signed-off-by: Umer Shahid --------- Signed-off-by: Christoph Müllner Signed-off-by: Umer Shahid Co-authored-by: Umer Shahid --- CHANGELOG.md | 4 +++- sample_cgfs/dataset.cgf | 34 ++++++++++++++++++++++++++++++ sample_cgfs/zvk/vaesdf.cgf | 27 ++++++++++++++++++++++++ sample_cgfs/zvk/vaesdm.cgf | 27 ++++++++++++++++++++++++ sample_cgfs/zvk/vaesef.cgf | 27 ++++++++++++++++++++++++ sample_cgfs/zvk/vaesem.cgf | 27 ++++++++++++++++++++++++ sample_cgfs/zvk/vaeskf1.cgf | 14 +++++++++++++ sample_cgfs/zvk/vaeskf2.cgf | 14 +++++++++++++ sample_cgfs/zvk/vaesz.cgf | 16 ++++++++++++++ sample_cgfs/zvk/vandn.cgf | 29 +++++++++++++++++++++++++ sample_cgfs/zvk/vbrev8.cgf | 14 +++++++++++++ sample_cgfs/zvk/vclmul.cgf | 29 +++++++++++++++++++++++++ sample_cgfs/zvk/vclmulh.cgf | 29 +++++++++++++++++++++++++ sample_cgfs/zvk/vghsh.cgf | 15 +++++++++++++ sample_cgfs/zvk/vgmul.cgf | 14 +++++++++++++ sample_cgfs/zvk/vrev8.cgf | 14 +++++++++++++ sample_cgfs/zvk/vrol.cgf | 29 +++++++++++++++++++++++++ sample_cgfs/zvk/vror.cgf | 42 +++++++++++++++++++++++++++++++++++++ sample_cgfs/zvk/vsha2ch.cgf | 29 +++++++++++++++++++++++++ sample_cgfs/zvk/vsha2cl.cfg | 29 +++++++++++++++++++++++++ sample_cgfs/zvk/vsha2ms.cgf | 29 +++++++++++++++++++++++++ sample_cgfs/zvk/vsm3c.cgf | 14 +++++++++++++ sample_cgfs/zvk/vsm3me.cgf | 14 +++++++++++++ sample_cgfs/zvk/vsm4k.cgf | 14 +++++++++++++ sample_cgfs/zvk/vsm4r.cgf | 27 ++++++++++++++++++++++++ 25 files changed, 560 insertions(+), 1 deletion(-) create mode 100644 sample_cgfs/zvk/vaesdf.cgf create mode 100644 sample_cgfs/zvk/vaesdm.cgf create mode 100644 sample_cgfs/zvk/vaesef.cgf create mode 100644 sample_cgfs/zvk/vaesem.cgf create mode 100644 sample_cgfs/zvk/vaeskf1.cgf create mode 100644 sample_cgfs/zvk/vaeskf2.cgf create mode 100644 sample_cgfs/zvk/vaesz.cgf create mode 100644 sample_cgfs/zvk/vandn.cgf create mode 100644 sample_cgfs/zvk/vbrev8.cgf create mode 100644 sample_cgfs/zvk/vclmul.cgf create mode 100644 sample_cgfs/zvk/vclmulh.cgf create mode 100644 sample_cgfs/zvk/vghsh.cgf create mode 100644 sample_cgfs/zvk/vgmul.cgf create mode 100644 sample_cgfs/zvk/vrev8.cgf create mode 100644 sample_cgfs/zvk/vrol.cgf create mode 100644 sample_cgfs/zvk/vror.cgf create mode 100644 sample_cgfs/zvk/vsha2ch.cgf create mode 100644 sample_cgfs/zvk/vsha2cl.cfg create mode 100644 sample_cgfs/zvk/vsha2ms.cgf create mode 100644 sample_cgfs/zvk/vsm3c.cgf create mode 100644 sample_cgfs/zvk/vsm3me.cgf create mode 100644 sample_cgfs/zvk/vsm4k.cgf create mode 100644 sample_cgfs/zvk/vsm4r.cgf diff --git a/CHANGELOG.md b/CHANGELOG.md index 71683e36..0371043a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,12 +2,14 @@ This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). + Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch. Only when a release to the main branch is done, the contents of the WIP-DEV are put under a versioned header while the `WIP-DEV` is left empty ## [0.12.2] - 2024-03-06 -- Add Zfa support. +- Add Zfa support. (PR#60) +- Initial covergroups for Zvk* instructions (PR#61) ## [0.12.1] - 2024-02-27 - Fix test.yml diff --git a/sample_cgfs/dataset.cgf b/sample_cgfs/dataset.cgf index 2d3565ea..a1a1a01f 100644 --- a/sample_cgfs/dataset.cgf +++ b/sample_cgfs/dataset.cgf @@ -120,6 +120,40 @@ datasets: f30: 0 f31: 0 + all_vregs: &all_vregs + v0: 0 + v1: 0 + v2: 0 + v3: 0 + v4: 0 + v5: 0 + v6: 0 + v7: 0 + v8: 0 + v9: 0 + v10: 0 + v11: 0 + v12: 0 + v13: 0 + v14: 0 + v15: 0 + v16: 0 + v17: 0 + v18: 0 + v19: 0 + v20: 0 + v21: 0 + v22: 0 + v23: 0 + v24: 0 + v25: 0 + v26: 0 + v27: 0 + v28: 0 + v29: 0 + v30: 0 + v31: 0 + pair_regs: &pair_regs x2: 0 x4: 0 diff --git a/sample_cgfs/zvk/vaesdf.cgf b/sample_cgfs/zvk/vaesdf.cgf new file mode 100644 index 00000000..be9eccad --- /dev/null +++ b/sample_cgfs/zvk/vaesdf.cgf @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vaesdf.vv: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesdf.vv: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + +vaesdf.vs: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesdf.vs: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vaesdm.cgf b/sample_cgfs/zvk/vaesdm.cgf new file mode 100644 index 00000000..2a8d96a6 --- /dev/null +++ b/sample_cgfs/zvk/vaesdm.cgf @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vaesdm.vv: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesdm.vv: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + +vaesdm.vs: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesdm.vs: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vaesef.cgf b/sample_cgfs/zvk/vaesef.cgf new file mode 100644 index 00000000..3ee274f8 --- /dev/null +++ b/sample_cgfs/zvk/vaesef.cgf @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vaesef.vv: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesef.vv: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + +vaesef.vs: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesef.vs: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vaesem.cgf b/sample_cgfs/zvk/vaesem.cgf new file mode 100644 index 00000000..e080c3c6 --- /dev/null +++ b/sample_cgfs/zvk/vaesem.cgf @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vaesem.vv: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesem.vv: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + +vaesem.vs: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesem.vs: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vaeskf1.cgf b/sample_cgfs/zvk/vaeskf1.cgf new file mode 100644 index 00000000..15ffee26 --- /dev/null +++ b/sample_cgfs/zvk/vaeskf1.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vaeskf1.vi: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaeskf1.vi: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vaeskf2.cgf b/sample_cgfs/zvk/vaeskf2.cgf new file mode 100644 index 00000000..352a0c0c --- /dev/null +++ b/sample_cgfs/zvk/vaeskf2.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vaeskf2.vi: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaeskf2.vi: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vaesz.cgf b/sample_cgfs/zvk/vaesz.cgf new file mode 100644 index 00000000..918194ed --- /dev/null +++ b/sample_cgfs/zvk/vaesz.cgf @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vaesz.vs: + config: + - check ISA:=(.*I.*V.*Zvkned) + mnemonics: + vaesz.vs: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + + diff --git a/sample_cgfs/zvk/vandn.cgf b/sample_cgfs/zvk/vandn.cgf new file mode 100644 index 00000000..403493ea --- /dev/null +++ b/sample_cgfs/zvk/vandn.cgf @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vandn.vv: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vandn.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vandn.vx: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vandn.vx: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vbrev8.cgf b/sample_cgfs/zvk/vbrev8.cgf new file mode 100644 index 00000000..f4a60ee1 --- /dev/null +++ b/sample_cgfs/zvk/vbrev8.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vbrev8.v: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vbrev8.v: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vclmul.cgf b/sample_cgfs/zvk/vclmul.cgf new file mode 100644 index 00000000..ccd772bd --- /dev/null +++ b/sample_cgfs/zvk/vclmul.cgf @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vclmul.vv: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vclmul.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vclmul.vx: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vclmul.vx: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vclmulh.cgf b/sample_cgfs/zvk/vclmulh.cgf new file mode 100644 index 00000000..b817719e --- /dev/null +++ b/sample_cgfs/zvk/vclmulh.cgf @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vclmulh.vv: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vclmulh.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vclmulh.vx: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vclmulh.vx: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vghsh.cgf b/sample_cgfs/zvk/vghsh.cgf new file mode 100644 index 00000000..43ed9e62 --- /dev/null +++ b/sample_cgfs/zvk/vghsh.cgf @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vghsh.vv: + config: + - check ISA:=(.*I.*V.*Zvkg) + mnemonics: + vghsh.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vgmul.cgf b/sample_cgfs/zvk/vgmul.cgf new file mode 100644 index 00000000..f0e5d7a8 --- /dev/null +++ b/sample_cgfs/zvk/vgmul.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vgmul.vv: + config: + - check ISA:=(.*I.*V.*Zvkg) + mnemonics: + vgmul.vv: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vrev8.cgf b/sample_cgfs/zvk/vrev8.cgf new file mode 100644 index 00000000..6dd373e2 --- /dev/null +++ b/sample_cgfs/zvk/vrev8.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vrev8.v: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vrev8.v: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vrol.cgf b/sample_cgfs/zvk/vrol.cgf new file mode 100644 index 00000000..36ab5818 --- /dev/null +++ b/sample_cgfs/zvk/vrol.cgf @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vrol.vv: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vrol.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vrol.vx: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vrol.vx: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vror.cgf b/sample_cgfs/zvk/vror.cgf new file mode 100644 index 00000000..6d0974e1 --- /dev/null +++ b/sample_cgfs/zvk/vror.cgf @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vror.vv: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vror.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vror.vx: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vror.vx: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vror.vi: + config: + - check ISA:=(.*I.*V.*Zvkb) + mnemonics: + vror.vi: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vsha2ch.cgf b/sample_cgfs/zvk/vsha2ch.cgf new file mode 100644 index 00000000..26778123 --- /dev/null +++ b/sample_cgfs/zvk/vsha2ch.cgf @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vsha2ch.vv: + config: + - check ISA:=(.*I.*V.*Zvknha) + mnemonics: + vsha2ch.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vsha2ch.vv: + config: + - check ISA:=(.*I.*V.*Zvknhb) + mnemonics: + vsha2ch.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vsha2cl.cfg b/sample_cgfs/zvk/vsha2cl.cfg new file mode 100644 index 00000000..3a190c42 --- /dev/null +++ b/sample_cgfs/zvk/vsha2cl.cfg @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vsha2cl.vv: + config: + - check ISA:=(.*I.*V.*Zvknha) + mnemonics: + vsha2cl.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vsha2cl.vv: + config: + - check ISA:=(.*I.*V.*Zvknhb) + mnemonics: + vsha2cl.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vsha2ms.cgf b/sample_cgfs/zvk/vsha2ms.cgf new file mode 100644 index 00000000..e7598d42 --- /dev/null +++ b/sample_cgfs/zvk/vsha2ms.cgf @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vsha2ms.vv: + config: + - check ISA:=(.*I.*V.*Zvknha) + mnemonics: + vsha2ms.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb + +vsha2ms.vv: + config: + - check ISA:=(.*I.*V.*Zvknhb) + mnemonics: + vsha2ms.vv: 0 + rs1: + <<: *all_vregs + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + <<: *sfmt_op_comb diff --git a/sample_cgfs/zvk/vsm3c.cgf b/sample_cgfs/zvk/vsm3c.cgf new file mode 100644 index 00000000..4d2a1694 --- /dev/null +++ b/sample_cgfs/zvk/vsm3c.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vsm3c.vi: + config: + - check ISA:=(.*I.*V.*Zvksh) + mnemonics: + vsm3c.vi: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vsm3me.cgf b/sample_cgfs/zvk/vsm3me.cgf new file mode 100644 index 00000000..8685d373 --- /dev/null +++ b/sample_cgfs/zvk/vsm3me.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vsm3me.vi: + config: + - check ISA:=(.*I.*V.*Zvksh) + mnemonics: + vsm3me.vi: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vsm4k.cgf b/sample_cgfs/zvk/vsm4k.cgf new file mode 100644 index 00000000..c1685e8c --- /dev/null +++ b/sample_cgfs/zvk/vsm4k.cgf @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vsm4k.vi: + config: + - check ISA:=(.*I.*V.*Zvksed) + mnemonics: + vsm4k.vi: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 diff --git a/sample_cgfs/zvk/vsm4r.cgf b/sample_cgfs/zvk/vsm4r.cgf new file mode 100644 index 00000000..9e20e54c --- /dev/null +++ b/sample_cgfs/zvk/vsm4r.cgf @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: BSD-3-Clause + +vsm4r.vv: + config: + - check ISA:=(.*I.*V.*Zvksed) + mnemonics: + vsm4r.vv: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + +vsm4r.vs: + config: + - check ISA:=(.*I.*V.*Zvksed) + mnemonics: + vsm4r.vs: 0 + rs2: + <<: *all_vregs + rd: + <<: *all_vregs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 From a0d3852a55afe9f4bb4b507a73cb70c7e258f059 Mon Sep 17 00:00:00 2001 From: kumaransvyoma <140789916+kumaransvyoma@users.noreply.github.com> Date: Mon, 22 Jul 2024 11:46:43 +0530 Subject: [PATCH 3/4] fix:removed conflict --- riscv_ctg/generator.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index b42f2839..f4b68133 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -264,7 +264,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str): self.is_fext = is_fext self.is_nan_box = is_nan_box - if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","flw","fsw","fld","fsd", "ldz","sdz"]: + if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","flw","fsw","fld","fsd"]: self.val_vars = self.val_vars + ['ea_align'] self.template = opnode['template'] self.opnode = opnode From 7a13c48eb06e752654776950e5d751051f258c0a Mon Sep 17 00:00:00 2001 From: kumaransvyoma <140789916+kumaransvyoma@users.noreply.github.com> Date: Mon, 22 Jul 2024 11:48:21 +0530 Subject: [PATCH 4/4] fix:updated opcode --- riscv_ctg/generator.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index 308ea46f..894ee0ae 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -264,7 +264,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str): self.is_fext = is_fext self.is_nan_box = is_nan_box - if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd"]: + if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd","ldz","sdz"]: self.val_vars = self.val_vars + ['ea_align'] self.template = opnode['template'] self.opnode = opnode