From dd17923c1242d38108c7053170d457a1e6319d50 Mon Sep 17 00:00:00 2001 From: Anusha Date: Thu, 26 Sep 2024 14:35:44 +0530 Subject: [PATCH 1/5] updated the code for Zcf and Zcd extensions --- riscv_ctg/data/imc.yaml | 82 ++++++++++++++++++++ riscv_ctg/data/template.yaml | 1 + riscv_ctg/generator.py | 8 +- sample_cgfs/dataset.cgf | 10 +++ sample_cgfs/sample_cgfs_fext/RV32Zcf/flw.cgf | 65 ++++++++++++++++ sample_cgfs/sample_cgfs_fext/Zcd/fld.cgf | 67 ++++++++++++++++ 6 files changed, 229 insertions(+), 4 deletions(-) create mode 100644 sample_cgfs/sample_cgfs_fext/RV32Zcf/flw.cgf create mode 100644 sample_cgfs/sample_cgfs_fext/Zcd/fld.cgf diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml index d77570ef..6993c4c2 100644 --- a/riscv_ctg/data/imc.yaml +++ b/riscv_ctg/data/imc.yaml @@ -1890,3 +1890,85 @@ c.jalr: // opcode: c.jalr; op1:$rs1 TEST_CJALR_OP($testreg, $rs1, $swreg, $offset) +c.flw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + rd_op_data: *all_fregs + xlen: [32] + std_op: + isa: + - IFC + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'clformat' + ea_align_data: '[0,1,2,3]' + rs1_val_data: '[0]' + imm_val_data: '[x*4 for x in gen_usign_dataset(5)]' + template: |- + // $comment + // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + +c.flwsp: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *all_fregs + xlen: [32] + std_op: + isa: + - IFC + formattype: 'ciformat' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + ea_align_data: '[0,1,2,3]' + imm_val_data: '[x*4 for x in gen_usign_dataset(6)]' + template: |- + // $comment + // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + + +c.fsw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_fregs + isa: + - IFC + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'csformat' + ea_align_data: '[0,1,2,3]' + rs1_val_data: '[0]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*4 for x in gen_usign_dataset(5)]' + template: |- + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + // valreg: $valaddr_reg; valoffset: $val_offset + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + + +c.fswsp: + sig: + stride: 1 + sz: 'XLEN/8' + rs2_op_data: *all_fregs + xlen: [32] + std_op: + isa: + - IFC + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'cssformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*4 for x in gen_usign_dataset(6)]' + template: |- + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + // valreg: $valaddr_reg; valoffset: $val_offset + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml index d1f87c8d..40d23c71 100644 --- a/riscv_ctg/data/template.yaml +++ b/riscv_ctg/data/template.yaml @@ -4,6 +4,7 @@ metadata: all_fregs: &all_fregs "['f'+str(x) for x in range(0,32 if 'e' not in base_isa else 16)]" all_regs_mx0: &all_regs_mx0 "['x'+str(x) for x in range(1,32 if 'e' not in base_isa else 16)]" c_regs: &c_regs "['x'+str(x) for x in range(8,16)]" + c_fregs: &c_fregs "['x'+str(x) for x in range(8,16)]" pair_regs: &pair_regs "['x'+str(x) for x in range(2,32 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]" rv32rv64pair_regs: &rv32rv64pair_regs "['x'+str(x) for x in range(2,30 if 'e' not in base_isa else 16, 2)]" diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index 9f3fc8d0..373787c9 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -260,7 +260,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str,inx is_nan_box = False - is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x for x in opnode['isa']]) + is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x or 'Zcf' in x or 'Zcd' in x for x in opnode['isa']]) is_sgn_extd = True if (inxFlag and iflen 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + +c.flwsp: + config: + - check ISA:=regex(.*I.*F.*C.*) + opcode: + c.flwsp: 0 + rd: + <<: *c_fregs + val_comb: + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 + +c.fsw: + config: + - check ISA:=regex(.*I.*F.*C.*) + opcode: + c.fsw: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_fregs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + +c.fswsp: + config: + - check ISA:=regex(.*I.*F.*C.*) + opcode: + c.fswsp: 0 + rs2: + <<: *c_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/Zcd/fld.cgf b/sample_cgfs/sample_cgfs_fext/Zcd/fld.cgf new file mode 100644 index 00000000..4c42779d --- /dev/null +++ b/sample_cgfs/sample_cgfs_fext/Zcd/fld.cgf @@ -0,0 +1,67 @@ +c.fld: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + mnemonics: + c.fld: 0 + rs1: + <<: *c_regs + rd: + <<: *c_fregs + op_comb: + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +c.fsd: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fsd: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_fregs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +c.fldsp: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fldsp: 0 + rd: + <<: *all_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + +c.fsdsp: + config: + - check ISA:=regex(.*I.*F.*D.*C.*) + opcode: + c.fsdsp: 0 + rs2: + <<: *all_fregs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 From 0827734a104cfd927bf577d664b62aee67a11088 Mon Sep 17 00:00:00 2001 From: Anusha Date: Thu, 26 Sep 2024 15:11:51 +0530 Subject: [PATCH 2/5] Updated yaml for Zcd instruction --- riscv_ctg/data/imc.yaml | 94 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml index 6993c4c2..a724f52d 100644 --- a/riscv_ctg/data/imc.yaml +++ b/riscv_ctg/data/imc.yaml @@ -1972,3 +1972,97 @@ c.fswsp: // valreg: $valaddr_reg; valoffset: $val_offset TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) +c.fld: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "''" + load_instr: "fld" + rs1_op_data: *c_regs + rd_op_data: *c_fregs + xlen: [32,64] + std_op: + isa: + - IFDC + formattype: 'clformat' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + ea_align_data: '[0,1,2,3]' + imm_val_data: '[x*8 for x in gen_usign_dataset(5)]' + template: |- + + // $comment + // opcode:$inst; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + +c.fldsp: + sig: + stride: 2 + sz: 'SIGALIGN' + rd_op_data: *all_fregs + xlen: [32,64] + std_op: + isa: + - IFDC + formattype: 'ciformat' + imm_val_data: '[x*8 for x in gen_usign_dataset(6)]' + template: |- + + // $comment + // opcode:$inst; op1:x2; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:x4 + TEST_LOAD_F($swreg,$testreg,$fcsr,x2,$rd,$imm_val,$inst,$ea_align,x4) + +c.fsd: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "''" + load_instr: "FLREG" + rs1_op_data: *c_regs + rs2_op_data: *c_fregs + xlen: [32,64] + isa: + - IFDC + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'csformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*8 for x in gen_usign_dataset(5)]' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + // valreg: $valaddr_reg; valoffset: $val_offset; + TEST_STORE_F($swreg,$testreg,0,$rs1,$rs2,$imm_val,$offset,$inst,0,$flagreg,$valaddr_reg, $val_offset) + +c.fsdsp: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "''" + load_instr: "FLREG" + rs2_op_data: *all_fregs + xlen: [32,64] + std_op: + isa: + - IFDC + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'cssformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*8 for x in gen_usign_dataset(6)]' + template: |- + + // $comment + // opcode: $inst; op1:x2; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + // valreg: $valaddr_reg ; valoffset: $val_offset + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,0,$flagreg,$valaddr_reg,$val_offset) From b28007b5352e18de157d788e411cf4af2d7a8fe0 Mon Sep 17 00:00:00 2001 From: Anusha Date: Mon, 30 Sep 2024 10:40:51 +0530 Subject: [PATCH 3/5] Updated the yaml and cover group files to accomdate the compreseed floating point --- riscv_ctg/data/imc.yaml | 77 +++++++++++--------- riscv_ctg/generator.py | 17 ++++- sample_cgfs/dataset.cgf | 2 +- sample_cgfs/sample_cgfs_fext/RV32Zcf/flw.cgf | 56 +++++++------- sample_cgfs/sample_cgfs_fext/Zcd/fld.cgf | 64 ++++++++-------- 5 files changed, 117 insertions(+), 99 deletions(-) diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml index a724f52d..945deee6 100644 --- a/riscv_ctg/data/imc.yaml +++ b/riscv_ctg/data/imc.yaml @@ -1894,38 +1894,40 @@ c.flw: sig: stride: 1 sz: 'XLEN/8' - rs1_op_data: *all_regs_mx0 - rd_op_data: *all_fregs + rs1_op_data: *c_regs + rd_op_data: *c_fregs xlen: [32] std_op: isa: - - IFC + - IF_Zcf fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' formattype: 'clformat' ea_align_data: '[0,1,2,3]' rs1_val_data: '[0]' imm_val_data: '[x*4 for x in gen_usign_dataset(5)]' template: |- + // $comment - // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg; fcsr: $fcsr TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) c.flwsp: sig: stride: 1 sz: 'XLEN/8' - rd_op_data: *all_fregs + rd_op_data: *c_fregs xlen: [32] std_op: isa: - - IFC + - IF_Zcf formattype: 'ciformat' fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' ea_align_data: '[0,1,2,3]' imm_val_data: '[x*4 for x in gen_usign_dataset(6)]' template: |- + // $comment - // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg + // opcode: $inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg; fcsr: $fcsr TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) @@ -1934,21 +1936,23 @@ c.fsw: stride: 1 sz: 'XLEN/8' xlen: [32] - rs1_op_data: *all_regs_mx0 - rs2_op_data: *all_fregs + rs1_op_data: *c_regs + rs2_op_data: *c_fregs + std_op: isa: - - IFC + - IF_Zcf fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' - std_op: formattype: 'csformat' ea_align_data: '[0,1,2,3]' rs1_val_data: '[0]' rs2_val_data: 'gen_sign_dataset(xlen)' imm_val_data: '[x*4 for x in gen_usign_dataset(5)]' template: |- + // $comment - // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; - // valreg: $valaddr_reg; valoffset: $val_offset + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) @@ -1956,20 +1960,22 @@ c.fswsp: sig: stride: 1 sz: 'XLEN/8' - rs2_op_data: *all_fregs + rs2_op_data: *c_fregs xlen: [32] std_op: isa: - - IFC + - IF_Zcf fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' formattype: 'cssformat' ea_align_data: '[0,1,2,3]' rs2_val_data: 'gen_sign_dataset(xlen)' imm_val_data: '[x*4 for x in gen_usign_dataset(6)]' template: |- + // $comment - // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; - // valreg: $valaddr_reg; valoffset: $val_offset + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) c.fld: @@ -1986,7 +1992,7 @@ c.fld: xlen: [32,64] std_op: isa: - - IFDC + - IFD_Zcd formattype: 'clformat' fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' ea_align_data: '[0,1,2,3]' @@ -1994,24 +2000,24 @@ c.fld: template: |- // $comment - // opcode:$inst; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) c.fldsp: sig: stride: 2 sz: 'SIGALIGN' - rd_op_data: *all_fregs + rd_op_data: *c_fregs xlen: [32,64] std_op: isa: - - IFDC + - IFD_Zcd formattype: 'ciformat' imm_val_data: '[x*8 for x in gen_usign_dataset(6)]' template: |- // $comment - // opcode:$inst; op1:x2; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:x4 + // opcode: $inst; op1:x2; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:x4 TEST_LOAD_F($swreg,$testreg,$fcsr,x2,$rd,$imm_val,$inst,$ea_align,x4) c.fsd: @@ -2026,20 +2032,21 @@ c.fsd: rs1_op_data: *c_regs rs2_op_data: *c_fregs xlen: [32,64] + std_op: isa: - - IFDC + - IFD_Zcd fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' - std_op: formattype: 'csformat' ea_align_data: '[0,1,2,3]' rs2_val_data: 'gen_sign_dataset(xlen)' imm_val_data: '[x*8 for x in gen_usign_dataset(5)]' template: |- - + // $comment - // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; - // valreg: $valaddr_reg; valoffset: $val_offset; - TEST_STORE_F($swreg,$testreg,0,$rs1,$rs2,$imm_val,$offset,$inst,0,$flagreg,$valaddr_reg, $val_offset) + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) c.fsdsp: sig: @@ -2050,19 +2057,21 @@ c.fsdsp: sz: 'FLEN/8' val_template: "''" load_instr: "FLREG" - rs2_op_data: *all_fregs + rs2_op_data: *c_fregs xlen: [32,64] std_op: isa: - - IFDC + - IFD_Zcd fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' formattype: 'cssformat' ea_align_data: '[0,1,2,3]' rs2_val_data: 'gen_sign_dataset(xlen)' imm_val_data: '[x*8 for x in gen_usign_dataset(6)]' template: |- - + // $comment - // opcode: $inst; op1:x2; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; - // valreg: $valaddr_reg ; valoffset: $val_offset - TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,0,$flagreg,$valaddr_reg,$val_offset) + /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + valreg: $valaddr_reg; valoffset: $val_offset + */ + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index 373787c9..01dd0b91 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -132,8 +132,8 @@ def get_rm(opcode): 'jformat': "['imm_val']", 'crformat': "['rs1_val', 'rs2_val']", 'cmvformat': "['rs2_val']", - 'ciformat': "['rs1_val', 'imm_val']", - 'cssformat': "['rs2_val', 'imm_val']", + 'ciformat': "[ 'imm_val','fcsr']", + 'cssformat': "['rs2_val', 'imm_val','fcsr']", 'ciwformat': "['imm_val']", 'clformat': "['rs1_val', 'imm_val', 'fcsr']", 'cuformat': "['rs1_val']", @@ -281,7 +281,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str,inx self.inxFlag = inxFlag self.is_sgn_extd = is_sgn_extd - if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd","flh","fsh","c.lbu","c.lhu","c.lh","c.sb","c.sh","c.flw","c.fld","c.flwsp","c.fswsp","c.fldsp","c.fsdsp"]: + if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd","flh","fsh","c.lbu","c.lhu","c.lh","c.sb","c.sh","c.fld","c.flwsp","c.fswsp","c.fldsp","c.fsdsp"]: self.val_vars = self.val_vars + ['ea_align'] self.template = opnode['template'] self.opnode = opnode @@ -812,7 +812,11 @@ def gen_inst(self,op_comb, val_comb, cgf): for y in op_inds[i:]: if op[y] == op[x]: val[ind_dict[y]] = val[ind_dict[x]] - if self.is_fext: + if self.is_fext and self.opcode in ['c.flwsp','c.fswsp','c.fldsp','c.fsdsp']: + if any([x == 'x2' for x in op]): + cont.append(val) + instr_dict.append(self.__cmemsp_instr__(op,val)) + elif self.is_fext: instr_dict.append(self.__fext_instr__(op,val)) elif self.opcode == 'c.lui': instr_dict.append(self.__clui_instr__(op,val)) @@ -1078,6 +1082,11 @@ def valreg(self,instr_dict): if self.is_nan_box: dval = nan_box(instr_dict[i]['rs{0}_nan_prefix'.format(j)], instr_dict[i]['rs{0}_val'.format(j)],self.flen,self.iflen) + elif self.is_fext and self.opcode in ['c.flwsp', 'c.fldsp']: + dval = (instr_dict[i]['rs{0}_val'.format(j)],width) + # instr_dict[i]['flagreg'] = available_reg[1] + elif self.is_fext and self.opcode in ['c.fswsp', 'c.fsdsp']: + dval = (instr_dict[i]['rs2_val'.format(j)],width) else: dval = (instr_dict[i]['rs{0}_val'.format(j)],width) if self.is_fext: diff --git a/sample_cgfs/dataset.cgf b/sample_cgfs/dataset.cgf index 1f510f00..0fa019b1 100644 --- a/sample_cgfs/dataset.cgf +++ b/sample_cgfs/dataset.cgf @@ -181,7 +181,7 @@ datasets: x14: 0 x15: 0 - c_fregs: &c_fregs + c_fregs: &c_fregs f8: 0 f9: 0 f10: 0 diff --git a/sample_cgfs/sample_cgfs_fext/RV32Zcf/flw.cgf b/sample_cgfs/sample_cgfs_fext/RV32Zcf/flw.cgf index 46284004..3d0c5686 100644 --- a/sample_cgfs/sample_cgfs_fext/RV32Zcf/flw.cgf +++ b/sample_cgfs/sample_cgfs_fext/RV32Zcf/flw.cgf @@ -1,6 +1,6 @@ c.flw: config: - - check ISA:=regex(.*I.*F.*C.*) + - check ISA:=regex(.*I.*F.*Zcf.*) opcode: c.flw: 0 rs1: @@ -8,31 +8,31 @@ c.flw: rd: <<: *c_fregs val_comb: - 'imm_val > 0 and fcsr == 0': 0 - 'imm_val == 0 and fcsr == 0': 0 - abstract_comb: - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 c.flwsp: config: - - check ISA:=regex(.*I.*F.*C.*) + - check ISA:=regex(.*I.*F.*Zcf.*) opcode: c.flwsp: 0 rd: <<: *c_fregs val_comb: - 'imm_val > 0 and fcsr == 0': 0 - 'imm_val == 0 and fcsr == 0': 0 - abstract_comb: - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 c.fsw: config: - - check ISA:=regex(.*I.*F.*C.*) + - check ISA:=regex(.*I.*F.*Zcf.*) opcode: c.fsw: 0 rs1: @@ -42,24 +42,24 @@ c.fsw: op_comb: 'rs1 != rs2': 0 val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 c.fswsp: config: - - check ISA:=regex(.*I.*F.*C.*) + - check ISA:=regex(.*I.*F.*Zcf.*) opcode: c.fswsp: 0 rs2: <<: *c_fregs val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 diff --git a/sample_cgfs/sample_cgfs_fext/Zcd/fld.cgf b/sample_cgfs/sample_cgfs_fext/Zcd/fld.cgf index 4c42779d..b74b0866 100644 --- a/sample_cgfs/sample_cgfs_fext/Zcd/fld.cgf +++ b/sample_cgfs/sample_cgfs_fext/Zcd/fld.cgf @@ -1,6 +1,6 @@ c.fld: config: - - check ISA:=regex(.*I.*F.*D.*C.*) + - check ISA:=regex(.*I.*F.*D.*Zcd.*) mnemonics: c.fld: 0 rs1: @@ -8,18 +8,18 @@ c.fld: rd: <<: *c_fregs op_comb: - 'rs1 != rd': 0 + 'rs1 != rd': 0 val_comb: - 'imm_val > 0 and fcsr == 0': 0 - 'imm_val == 0 and fcsr == 0': 0 - abstract_comb: - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 c.fsd: config: - - check ISA:=regex(.*I.*F.*D.*C.*) + - check ISA:=regex(.*I.*F.*D.*Zcd.*) opcode: c.fsd: 0 rs1: @@ -27,41 +27,41 @@ c.fsd: rs2: <<: *c_fregs op_comb: - 'rs1 != rs2': 0 + 'rs1 != rs2': 0 val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 c.fldsp: config: - - check ISA:=regex(.*I.*F.*D.*C.*) + - check ISA:=regex(.*I.*F.*D.*Zcd.*) opcode: c.fldsp: 0 rd: - <<: *all_fregs + <<: *c_fregs val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 c.fsdsp: config: - - check ISA:=regex(.*I.*F.*D.*C.*) + - check ISA:=regex(.*I.*F.*D.*Zcd.*) opcode: c.fsdsp: 0 rs2: - <<: *all_fregs + <<: *c_fregs val_comb: - 'imm_val > 0': 0 - 'imm_val == 0': 0 - abstract_comb: - 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 - 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 From 64ceaa4ca0c8b7ab4ba1e6c09fcec7ef317b1345 Mon Sep 17 00:00:00 2001 From: Anusha Date: Mon, 30 Sep 2024 11:07:16 +0530 Subject: [PATCH 4/5] updated generator.py --- riscv_ctg/generator.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index 01dd0b91..9a890fed 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -132,10 +132,10 @@ def get_rm(opcode): 'jformat': "['imm_val']", 'crformat': "['rs1_val', 'rs2_val']", 'cmvformat': "['rs2_val']", - 'ciformat': "[ 'imm_val','fcsr']", - 'cssformat': "['rs2_val', 'imm_val','fcsr']", + 'ciformat': "[ 'imm_val']", + 'cssformat': "['rs2_val', 'imm_val']", 'ciwformat': "['imm_val']", - 'clformat': "['rs1_val', 'imm_val', 'fcsr']", + 'clformat': "['rs1_val', 'imm_val']", 'cuformat': "['rs1_val']", 'clbformat': "['rs1_val','imm_val']", 'clhformat': "['rs1_val','imm_val']", From 6fbe3ba704cd023720903f068b307beef54e69eb Mon Sep 17 00:00:00 2001 From: Anusha Date: Mon, 30 Sep 2024 11:48:03 +0530 Subject: [PATCH 5/5] updated generator.py --- riscv_ctg/generator.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index 9a890fed..2f954984 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -1052,7 +1052,7 @@ def valreg(self,instr_dict): if self.is_nan_box: dval = nan_box(instr_dict[i]['rs{0}_nan_prefix'.format(j)], instr_dict[i]['rs{0}_val'.format(j)],self.flen,self.iflen) - if self.is_sgn_extd: + elif self.is_sgn_extd: dval = sgn_extd(instr_dict[i]['rs{0}_sgn_prefix'.format(j)], instr_dict[i]['rs{0}_val'.format(j)],self.flen,self.iflen) else: