From b18372fcc63ac3ae44fbec710e94753347a74c39 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Wed, 8 Nov 2023 08:34:40 +0500 Subject: [PATCH 1/4] Physical Memory Protection coverpoints added --- sample_cgfs/rv32_pmp.cgf | 429 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 429 insertions(+) create mode 100644 sample_cgfs/rv32_pmp.cgf diff --git a/sample_cgfs/rv32_pmp.cgf b/sample_cgfs/rv32_pmp.cgf new file mode 100644 index 00000000..ca0add68 --- /dev/null +++ b/sample_cgfs/rv32_pmp.cgf @@ -0,0 +1,429 @@ +# *- Write to pmpcfg with L=1 and check that: +# *- Writes are ignored +# *- Writes to other, unrelated entries in the same CSR are not ignored" +pmp_cfg_locked_write_unrelated: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + csr_comb: + (pmpcfg0 & 0x80 == 0x80) and (old("pmpcfg0") & 0xFF) ^ (pmpcfg0 & 0xFF) == 0x00: 0 #any other write ignored + (pmpcfg0 & 0x80 == 0x80) and (old("pmpaddr0")) ^ (pmpaddr0) == 0x00: 0 #any other write ignored + (pmpcfg0>>8 & 0x80 == 0x80) and (old("pmpcfg0") & (0xFF<<8)) ^ (pmpcfg0 & (0xFF<<8)) == 0x00: 0 #any other write ignored + (pmpcfg0>>8 & 0x80 == 0x80) and (old("pmpaddr1")) ^ (pmpaddr1) == 0x00: 0 #any other write ignored + (pmpcfg0>>16 & 0x80 == 0x80) and (old("pmpcfg0") & (0xFF<<16)) ^ (pmpcfg0 & (0xFF<<16)) == 0x00: 0 #any other write ignored + (pmpcfg0>>16 & 0x80 == 0x80) and (old("pmpaddr2")) ^ (pmpaddr2) == 0x00: 0 #any other write ignored + (pmpcfg0>>24 & 0x80 == 0x80) and (old("pmpcfg0") & (0xFF<<24)) ^ (pmpcfg0 & (0xFF<<24)) == 0x00: 0 #any other write ignored + (pmpcfg0>>24 & 0x80 == 0x80) and (old("pmpaddr3")) ^ (pmpaddr3) == 0x00: 0 #any other write ignored + (pmpcfg1 & 0x80 == 0x80) and (old("pmpcfg1") & 0xFF) ^ (pmpcfg1 & 0xFF) == 0x00: 0 #any other write ignored + (pmpcfg1 & 0x80 == 0x80) and (old("pmpaddr4")) ^ (pmpaddr4) == 0x00: 0 #any other write ignored + (pmpcfg1>>8 & 0x80 == 0x80) and (old("pmpcfg1") & (0xFF<<8)) ^ (pmpcfg1 & (0xFF<<8)) == 0x00: 0 #any other write ignored + (pmpcfg1>>8 & 0x80 == 0x80) and (old("pmpaddr5")) ^ (pmpaddr5) == 0x00: 0 #any other write ignored + (pmpcfg1>>16 & 0x80 == 0x80) and (old("pmpcfg1") & (0xFF<<16)) ^ (pmpcfg1 & (0xFF<<16)) == 0x00: 0 #any other write ignored + (pmpcfg1>>16 & 0x80 == 0x80) and (old("pmpaddr6")) ^ (pmpaddr6) == 0x00: 0 #any other write ignored + (pmpcfg1>>24 & 0x80 == 0x80) and (old("pmpcfg1") & (0xFF<<24)) ^ (pmpcfg1 & (0xFF<<24)) == 0x00: 0 #any other write ignored + (pmpcfg1>>24 & 0x80 == 0x80) and (old("pmpaddr7")) ^ (pmpaddr7) == 0x00: 0 #any other write ignored + (pmpcfg2 & 0x80 == 0x80) and (old("pmpcfg2") & 0xFF) ^ (pmpcfg2 & 0xFF) == 0x00: 0 #any other write ignored + (pmpcfg2 & 0x80 == 0x80) and (old("pmpaddr8")) ^ (pmpaddr8) == 0x00: 0 #any other write ignored + (pmpcfg2>>8 & 0x80 == 0x80) and (old("pmpcfg2") & (0xFF<<8)) ^ (pmpcfg2 & (0xFF<<8)) == 0x00: 0 #any other write ignored + (pmpcfg2>>8 & 0x80 == 0x80) and (old("pmpaddr9")) ^ (pmpaddr9) == 0x00: 0 #any other write ignored + (pmpcfg2>>16 & 0x80 == 0x80) and (old("pmpcfg2") & (0xFF<<16)) ^ (pmpcfg2 & (0xFF<<16)) == 0x00: 0 #any other write ignored + (pmpcfg2>>16 & 0x80 == 0x80) and (old("pmpaddr10")) ^ (pmpaddr10) == 0x00: 0 #any other write ignored + (pmpcfg2>>24 & 0x80 == 0x80) and (old("pmpcfg2") & (0xFF<<24)) ^ (pmpcfg2 & (0xFF<<24)) == 0x00: 0 #any other write ignored + (pmpcfg2>>24 & 0x80 == 0x80) and (old("pmpaddr11")) ^ (pmpaddr11) == 0x00: 0 #any other write ignored + (pmpcfg3 & 0x80 == 0x80) and (old("pmpcfg3") & 0xFF) ^ (pmpcfg3 & 0xFF) == 0x00: 0 #any other write ignored + (pmpcfg3 & 0x80 == 0x80) and (old("pmpaddr12")) ^ (pmpaddr12) == 0x00: 0 #any other write ignored + (pmpcfg3>>8 & 0x80 == 0x80) and (old("pmpcfg3") & (0xFF<<8)) ^ (pmpcfg3 & (0xFF<<8)) == 0x00: 0 #any other write ignored + (pmpcfg3>>8 & 0x80 == 0x80) and (old("pmpaddr13")) ^ (pmpaddr13) == 0x00: 0 #any other write ignored + (pmpcfg3>>16 & 0x80 == 0x80) and (old("pmpcfg3") & (0xFF<<16)) ^ (pmpcfg3 & (0xFF<<16)) == 0x00: 0 #any other write ignored + (pmpcfg3>>16 & 0x80 == 0x80) and (old("pmpaddr14")) ^ (pmpaddr14) == 0x00: 0 #any other write ignored + (pmpcfg3>>24 & 0x80 == 0x80) and (old("pmpcfg3") & (0xFF<<24)) ^ (pmpcfg3 & (0xFF<<24)) == 0x00: 0 #any other write ignored + (pmpcfg3>>24 & 0x80 == 0x80) and (old("pmpaddr15")) ^ (pmpaddr15) == 0x00: 0 #any other write ignored +# #------------------------------------------------------------------------------ +# #PMP Permission. Check csrrw. csrrs and csrrc in all 3 modes +# # *No exception in Machine mode +# # *Page 57 -- pmp csrs accessible only in M mode. So, exception in Supervisor mode +# # *Page 57 -- pmp csrs accessible only in M mode. So, exception in User mode +pmp_access_permission: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw : 0 + csrrs : 0 + mret : 0 + sw : 0 + csr_comb: + (mstatus & 0x1800 != 0x0800) and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 #any other write ignored + (mstatus & 0x1800 != 0x0800) and ((old("pmpaddr0")) ^ (pmpaddr0) != 0x00): 0 #any other write ignored + val_comb: + 'mstatus & 0x1800 == 0x800 and (rs2_val == 0x00000002) and (rs1_val + imm_val >= 0x80005198) and (rs1_val + imm_val <= 0x80005198 + 0x10)' : 0 #Start of mtrap_sigptr + 'mstatus & 0x1800 == 0x800 and (rs2_val == 0x00000002) and (rs1_val + imm_val >= 0x80005198+0x10) and (rs1_val + imm_val <= 0x80005198 + 0x20)' : 0 #Start of mtrap_sigptr + 'mstatus & 0x1800 == 0x000 and (rs2_val == 0x00000002) and (rs1_val + imm_val >= 0x80005198+0x20) and (rs1_val + imm_val <= 0x80005198 + 0x30)' : 0 #Start of mtrap_sigptr + 'mstatus & 0x1800 == 0x000 and (rs2_val == 0x00000002) and (rs1_val + imm_val >= 0x80005198+0x30) and (rs1_val + imm_val <= 0x80005198 + 0x40)' : 0 #Start of mtrap_sigptr +pmp_NA4_RWX: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + lw: 0 + sw: 0 + csr_comb: + ((pmpcfg0 >> 8) & 0x9C) == 0x94: 0 + ((pmpcfg0 >> 8) & 0x9A) == 0x92: 0 + ((pmpcfg0 >> 8) & 0x99) == 0x91: 0 + ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + val_comb: + #address should be in range of PMP + '((pmpcfg0 >> 8) & 0x9F == 0x97) and (rs1_val + imm_val == (pmpaddr1 << 2)) and (mnemonic == "lw")': 0 + #No exception in M Mode + '(rs2_val != 0x00000007)': 0 + '(rs2_val != 0x00000005)': 0 + '(rs2_val != 0x00000001)': 0 + #No exception in S and U Mode + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 +pmp_NAPOT_RWX: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + lw: 0 + sw: 0 + csr_comb: + ((pmpcfg0 >> 8) & 0x9C) == 0x9C: 0 + ((pmpcfg0 >> 8) & 0x9A) == 0x9A: 0 + ((pmpcfg0 >> 8) & 0x99) == 0x99: 0 + ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + val_comb: + '((pmpcfg0 >> 8) & 0x9F == 0x9F) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + '(rs2_val != 0x00000007)': 0 + '(rs2_val != 0x00000005)': 0 + '(rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 +pmp_TOR_RWX: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + lw: 0 + sw: 0 + csr_comb: + ((pmpcfg0 >> 8) & 0x9C) == 0x94: 0 + ((pmpcfg0 >> 8) & 0x9A) == 0x92: 0 + ((pmpcfg0 >> 8) & 0x99) == 0x91: 0 + ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + val_comb: + '((pmpcfg0 >> 8) & 0x9F == 0x97) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 + '(rs2_val != 0x00000007)': 0 + '(rs2_val != 0x00000005)': 0 + '(rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 + +pmp_NA4_RW: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + lw: 0 + sw: 0 + csr_comb: + ((pmpcfg0 >> 8) & 0x9C) == 0x90: 0 + ((pmpcfg0 >> 8) & 0x9A) == 0x92: 0 + ((pmpcfg0 >> 8) & 0x99) == 0x91: 0 #No execute permissions + ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + val_comb: + '((pmpcfg0 >> 8) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 + '(rs2_val != 0x00000007)': 0 + '(rs2_val != 0x00000005)': 0 + '(rs2_val == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000001)': 0 +pmp_NAPOT_RW: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + lw: 0 + sw: 0 + csr_comb: + ((pmpcfg0 >> 8) & 0x9C) == 0x98: 0 + ((pmpcfg0 >> 8) & 0x9A) == 0x9A: 0 + ((pmpcfg0 >> 8) & 0x99) == 0x99: 0 + ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + val_comb: + '((pmpcfg0 >> 8) & 0x9F == 0x9B) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + '(rs2_val != 0x00000007)': 0 + '(rs2_val != 0x00000005)': 0 + '(rs2_val == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000001)': 0 +pmp_TOR_RW: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + lw: 0 + sw: 0 + csr_comb: + ((pmpcfg0 >> 16) & 0x9C) == 0x88: 0 + ((pmpcfg0 >> 16) & 0x9A) == 0x8A: 0 + ((pmpcfg0 >> 16) & 0x99) == 0x89: 0 + ((pmpaddr2) >= 0x00000000) and ((pmpaddr2) <= 0xFFFFFFFF): 0 + val_comb: + '((pmpcfg0 >> 16) & 0x9F == 0x8B) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2))': 0 + '(rs2_val != 0x00000007)': 0 + '(rs2_val != 0x00000005)': 0 + '(rs2_val == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000001)': 0 + +pmp_NA4_R: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + lw: 0 + sw: 0 + csr_comb: + ((pmpcfg0 >> 8) & 0x9C) == 0x90: 0 + ((pmpcfg0 >> 8) & 0x9A) == 0x90: 0 + ((pmpcfg0 >> 8) & 0x99) == 0x91: 0 #No execute permissions + ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + val_comb: + '((pmpcfg0 >> 8) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 + '(rs2_val == 0x00000007)': 0 + '(rs2_val != 0x00000005)': 0 + '(rs2_val == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000001)': 0 +pmp_NAPOT_R: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + lw: 0 + sw: 0 + csr_comb: + ((pmpcfg0 >> 8) & 0x9C) == 0x98: 0 + ((pmpcfg0 >> 8) & 0x9A) == 0x98: 0 + ((pmpcfg0 >> 8) & 0x99) == 0x99: 0 + ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + val_comb: + '((pmpcfg0 >> 8) & 0x9F == 0x99) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + '(rs2_val == 0x00000007)': 0 + '(rs2_val != 0x00000005)': 0 + '(rs2_val == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000001)': 0 +pmp_TOR_R: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + lw: 0 + sw: 0 + csr_comb: + ((pmpcfg0 >> 16) & 0x9C) == 0x88: 0 + ((pmpcfg0 >> 16) & 0x9A) == 0x88: 0 + ((pmpcfg0 >> 16) & 0x99) == 0x89: 0 + ((pmpaddr2) >= 0x00000000) and ((pmpaddr2) <= 0xFFFFFFFF): 0 + val_comb: + '((pmpcfg0 >> 16) & 0x9F == 0x89) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2))': 0 + '(rs2_val == 0x00000007)': 0 + '(rs2_val != 0x00000005)': 0 + '(rs2_val == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000001)': 0 + +pmp_NA4_X: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + lw: 0 + sw: 0 + csr_comb: + ((pmpcfg0 >> 8) & 0x9C) == 0x94: 0 + ((pmpcfg0 >> 8) & 0x9A) == 0x90: 0 + ((pmpcfg0 >> 8) & 0x99) == 0x90: 0 #No execute permissions + ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + val_comb: + '((pmpcfg0 >> 8) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 + '(rs2_val == 0x00000007)': 0 + '(rs2_val == 0x00000005)': 0 + '(rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000005)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 +pmp_NAPOT_X: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + lw: 0 + sw: 0 + csr_comb: + ((pmpcfg0 >> 8) & 0x9C) == 0x9C: 0 + ((pmpcfg0 >> 8) & 0x9A) == 0x98: 0 + ((pmpcfg0 >> 8) & 0x99) == 0x98: 0 + ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + val_comb: + '((pmpcfg0 >> 8) & 0x9F == 0x9C) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + '(rs2_val == 0x00000007)': 0 + '(rs2_val == 0x00000005)': 0 + '(rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000005)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 +pmp_TOR_X: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + lw: 0 + sw: 0 + csr_comb: + ((pmpcfg0 >> 16) & 0x9C) == 0x8C: 0 + ((pmpcfg0 >> 16) & 0x9A) == 0x88: 0 + ((pmpcfg0 >> 16) & 0x99) == 0x88: 0 + ((pmpaddr2) >= 0x00000000) and ((pmpaddr2) <= 0xFFFFFFFF): 0 + val_comb: + '((pmpcfg0 >> 16) & 0x9F == 0x8C) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2))': 0 + '(rs2_val == 0x00000007)': 0 + '(rs2_val == 0x00000005)': 0 + '(rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000005)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 +pmp_NA4_RX: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + lw: 0 + sw: 0 + csr_comb: + ((pmpcfg0 >> 8) & 0x9C) == 0x94: 0 + ((pmpcfg0 >> 8) & 0x9A) == 0x90: 0 + ((pmpcfg0 >> 8) & 0x99) == 0x91: 0 #No execute permissions + ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + val_comb: + '((pmpcfg0 >> 8) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 + '(rs2_val == 0x00000007)': 0 + '(rs2_val != 0x00000005)': 0 + '(rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 +pmp_NAPOT_RX: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + lw: 0 + sw: 0 + csr_comb: + ((pmpcfg0 >> 8) & 0x9C) == 0x9C: 0 + ((pmpcfg0 >> 8) & 0x9A) == 0x98: 0 + ((pmpcfg0 >> 8) & 0x99) == 0x99: 0 + ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + val_comb: + '((pmpcfg0 >> 8) & 0x9F == 0x9D) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + '(rs2_val == 0x00000007)': 0 + '(rs2_val != 0x00000005)': 0 + '(rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 +pmp_TOR_RX: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + csrrw: 0 + csrrs: 0 + lw: 0 + sw: 0 + csr_comb: + ((pmpcfg0 >> 16) & 0x9C) == 0x8C: 0 + ((pmpcfg0 >> 16) & 0x9A) == 0x88: 0 + ((pmpcfg0 >> 16) & 0x99) == 0x89: 0 + ((pmpaddr2) >= 0x00000000) and ((pmpaddr2) <= 0xFFFFFFFF): 0 + val_comb: + '((pmpcfg0 >> 16) & 0x9F == 0x8D) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2))': 0 + '(rs2_val == 0x00000007)': 0 + '(rs2_val != 0x00000005)': 0 + '(rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 From 486feec755badec7eafa69d45b06b3612644c1cb Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Tue, 14 Nov 2023 21:00:28 +0500 Subject: [PATCH 2/4] Phyical Memory Protection Coverpoints added --- sample_cgfs/{rv32_pmp.cgf => rv32i_pmp.cgf} | 279 ++++++++++---------- 1 file changed, 136 insertions(+), 143 deletions(-) rename sample_cgfs/{rv32_pmp.cgf => rv32i_pmp.cgf} (60%) diff --git a/sample_cgfs/rv32_pmp.cgf b/sample_cgfs/rv32i_pmp.cgf similarity index 60% rename from sample_cgfs/rv32_pmp.cgf rename to sample_cgfs/rv32i_pmp.cgf index ca0add68..21376f91 100644 --- a/sample_cgfs/rv32_pmp.cgf +++ b/sample_cgfs/rv32i_pmp.cgf @@ -57,10 +57,10 @@ pmp_access_permission: (mstatus & 0x1800 != 0x0800) and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 #any other write ignored (mstatus & 0x1800 != 0x0800) and ((old("pmpaddr0")) ^ (pmpaddr0) != 0x00): 0 #any other write ignored val_comb: - 'mstatus & 0x1800 == 0x800 and (rs2_val == 0x00000002) and (rs1_val + imm_val >= 0x80005198) and (rs1_val + imm_val <= 0x80005198 + 0x10)' : 0 #Start of mtrap_sigptr - 'mstatus & 0x1800 == 0x800 and (rs2_val == 0x00000002) and (rs1_val + imm_val >= 0x80005198+0x10) and (rs1_val + imm_val <= 0x80005198 + 0x20)' : 0 #Start of mtrap_sigptr - 'mstatus & 0x1800 == 0x000 and (rs2_val == 0x00000002) and (rs1_val + imm_val >= 0x80005198+0x20) and (rs1_val + imm_val <= 0x80005198 + 0x30)' : 0 #Start of mtrap_sigptr - 'mstatus & 0x1800 == 0x000 and (rs2_val == 0x00000002) and (rs1_val + imm_val >= 0x80005198+0x30) and (rs1_val + imm_val <= 0x80005198 + 0x40)' : 0 #Start of mtrap_sigptr + 'mstatus & 0x1800 == 0x800 and (read_csr("mcause") == 0x00000002) and (rs1_val + imm_val >= 0x80005198) and (rs1_val + imm_val <= 0x80005198 + 0x10)' : 0 #Start of mtrap_sigptr + 'mstatus & 0x1800 == 0x800 and (read_csr("mcause") == 0x00000002) and (rs1_val + imm_val >= 0x80005198+0x10) and (rs1_val + imm_val <= 0x80005198 + 0x20)' : 0 #Start of mtrap_sigptr + 'mstatus & 0x1800 == 0x000 and (read_csr("mcause") == 0x00000002) and (rs1_val + imm_val >= 0x80005198+0x20) and (rs1_val + imm_val <= 0x80005198 + 0x30)' : 0 #Start of mtrap_sigptr + 'mstatus & 0x1800 == 0x000 and (read_csr("mcause") == 0x00000002) and (rs1_val + imm_val >= 0x80005198+0x30) and (rs1_val + imm_val <= 0x80005198 + 0x40)' : 0 #Start of mtrap_sigptr pmp_NA4_RWX: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; @@ -74,20 +74,19 @@ pmp_NA4_RWX: ((pmpcfg0 >> 8) & 0x9A) == 0x92: 0 ((pmpcfg0 >> 8) & 0x99) == 0x91: 0 ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 - val_comb: - #address should be in range of PMP - '((pmpcfg0 >> 8) & 0x9F == 0x97) and (rs1_val + imm_val == (pmpaddr1 << 2)) and (mnemonic == "lw")': 0 #No exception in M Mode - '(rs2_val != 0x00000007)': 0 - '(rs2_val != 0x00000005)': 0 - '(rs2_val != 0x00000001)': 0 + '(read_csr("mcause") != 0x00000007)': 0 + '(read_csr("mcause") != 0x00000005)': 0 + '(read_csr("mcause") != 0x00000001)': 0 #No exception in S and U Mode - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 + val_comb: + #address should be in range of PMP + '((pmpcfg0 >> 8) & 0x9F == 0x97) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 pmp_NAPOT_RWX: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; @@ -101,17 +100,17 @@ pmp_NAPOT_RWX: ((pmpcfg0 >> 8) & 0x9A) == 0x9A: 0 ((pmpcfg0 >> 8) & 0x99) == 0x99: 0 ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + '(read_csr("mcause") != 0x00000007)': 0 + '(read_csr("mcause") != 0x00000005)': 0 + '(read_csr("mcause") != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 val_comb: '((pmpcfg0 >> 8) & 0x9F == 0x9F) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - '(rs2_val != 0x00000007)': 0 - '(rs2_val != 0x00000005)': 0 - '(rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 + pmp_TOR_RWX: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; @@ -125,17 +124,16 @@ pmp_TOR_RWX: ((pmpcfg0 >> 8) & 0x9A) == 0x92: 0 ((pmpcfg0 >> 8) & 0x99) == 0x91: 0 ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + '(read_csr("mcause") != 0x00000007)': 0 + '(read_csr("mcause") != 0x00000005)': 0 + '(read_csr("mcause") != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 val_comb: '((pmpcfg0 >> 8) & 0x9F == 0x97) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 - '(rs2_val != 0x00000007)': 0 - '(rs2_val != 0x00000005)': 0 - '(rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 pmp_NA4_RW: config: @@ -150,17 +148,17 @@ pmp_NA4_RW: ((pmpcfg0 >> 8) & 0x9A) == 0x92: 0 ((pmpcfg0 >> 8) & 0x99) == 0x91: 0 #No execute permissions ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + '(read_csr("mcause") != 0x00000007)': 0 + '(read_csr("mcause") != 0x00000005)': 0 + '(read_csr("mcause") == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000001)': 0 val_comb: '((pmpcfg0 >> 8) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 - '(rs2_val != 0x00000007)': 0 - '(rs2_val != 0x00000005)': 0 - '(rs2_val == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000001)': 0 + pmp_NAPOT_RW: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; @@ -174,17 +172,16 @@ pmp_NAPOT_RW: ((pmpcfg0 >> 8) & 0x9A) == 0x9A: 0 ((pmpcfg0 >> 8) & 0x99) == 0x99: 0 ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + '(read_csr("mcause") != 0x00000007)': 0 + '(read_csr("mcause") != 0x00000005)': 0 + '(read_csr("mcause") == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000001)': 0 val_comb: '((pmpcfg0 >> 8) & 0x9F == 0x9B) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - '(rs2_val != 0x00000007)': 0 - '(rs2_val != 0x00000005)': 0 - '(rs2_val == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000001)': 0 pmp_TOR_RW: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; @@ -198,17 +195,16 @@ pmp_TOR_RW: ((pmpcfg0 >> 16) & 0x9A) == 0x8A: 0 ((pmpcfg0 >> 16) & 0x99) == 0x89: 0 ((pmpaddr2) >= 0x00000000) and ((pmpaddr2) <= 0xFFFFFFFF): 0 + '(read_csr("mcause") != 0x00000007)': 0 + '(read_csr("mcause") != 0x00000005)': 0 + '(read_csr("mcause") == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000001)': 0 val_comb: '((pmpcfg0 >> 16) & 0x9F == 0x8B) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2))': 0 - '(rs2_val != 0x00000007)': 0 - '(rs2_val != 0x00000005)': 0 - '(rs2_val == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000001)': 0 pmp_NA4_R: config: @@ -223,17 +219,16 @@ pmp_NA4_R: ((pmpcfg0 >> 8) & 0x9A) == 0x90: 0 ((pmpcfg0 >> 8) & 0x99) == 0x91: 0 #No execute permissions ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + '(read_csr("mcause") == 0x00000007)': 0 + '(read_csr("mcause") != 0x00000005)': 0 + '(read_csr("mcause") == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000001)': 0 val_comb: '((pmpcfg0 >> 8) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 - '(rs2_val == 0x00000007)': 0 - '(rs2_val != 0x00000005)': 0 - '(rs2_val == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000001)': 0 pmp_NAPOT_R: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; @@ -247,17 +242,17 @@ pmp_NAPOT_R: ((pmpcfg0 >> 8) & 0x9A) == 0x98: 0 ((pmpcfg0 >> 8) & 0x99) == 0x99: 0 ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + '(read_csr("mcause") == 0x00000007)': 0 + '(read_csr("mcause") != 0x00000005)': 0 + '(read_csr("mcause") == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000001)': 0 val_comb: '((pmpcfg0 >> 8) & 0x9F == 0x99) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - '(rs2_val == 0x00000007)': 0 - '(rs2_val != 0x00000005)': 0 - '(rs2_val == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000001)': 0 + pmp_TOR_R: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; @@ -271,17 +266,16 @@ pmp_TOR_R: ((pmpcfg0 >> 16) & 0x9A) == 0x88: 0 ((pmpcfg0 >> 16) & 0x99) == 0x89: 0 ((pmpaddr2) >= 0x00000000) and ((pmpaddr2) <= 0xFFFFFFFF): 0 + '(read_csr("mcause") == 0x00000007)': 0 + '(read_csr("mcause") != 0x00000005)': 0 + '(read_csr("mcause") == 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000001)': 0 val_comb: '((pmpcfg0 >> 16) & 0x9F == 0x89) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2))': 0 - '(rs2_val == 0x00000007)': 0 - '(rs2_val != 0x00000005)': 0 - '(rs2_val == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000001)': 0 pmp_NA4_X: config: @@ -296,17 +290,17 @@ pmp_NA4_X: ((pmpcfg0 >> 8) & 0x9A) == 0x90: 0 ((pmpcfg0 >> 8) & 0x99) == 0x90: 0 #No execute permissions ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + '(read_csr("mcause") == 0x00000007)': 0 + '(read_csr("mcause") == 0x00000005)': 0 + '(read_csr("mcause") != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 val_comb: '((pmpcfg0 >> 8) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 - '(rs2_val == 0x00000007)': 0 - '(rs2_val == 0x00000005)': 0 - '(rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000005)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 + pmp_NAPOT_X: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; @@ -320,17 +314,17 @@ pmp_NAPOT_X: ((pmpcfg0 >> 8) & 0x9A) == 0x98: 0 ((pmpcfg0 >> 8) & 0x99) == 0x98: 0 ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + '(read_csr("mcause") == 0x00000007)': 0 + '(read_csr("mcause") == 0x00000005)': 0 + '(read_csr("mcause") != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 val_comb: '((pmpcfg0 >> 8) & 0x9F == 0x9C) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - '(rs2_val == 0x00000007)': 0 - '(rs2_val == 0x00000005)': 0 - '(rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000005)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 + pmp_TOR_X: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; @@ -344,17 +338,17 @@ pmp_TOR_X: ((pmpcfg0 >> 16) & 0x9A) == 0x88: 0 ((pmpcfg0 >> 16) & 0x99) == 0x88: 0 ((pmpaddr2) >= 0x00000000) and ((pmpaddr2) <= 0xFFFFFFFF): 0 + '(read_csr("mcause") == 0x00000007)': 0 + '(read_csr("mcause") == 0x00000005)': 0 + '(read_csr("mcause") != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 val_comb: '((pmpcfg0 >> 16) & 0x9F == 0x8C) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2))': 0 - '(rs2_val == 0x00000007)': 0 - '(rs2_val == 0x00000005)': 0 - '(rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000005)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 + pmp_NA4_RX: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; @@ -368,17 +362,17 @@ pmp_NA4_RX: ((pmpcfg0 >> 8) & 0x9A) == 0x90: 0 ((pmpcfg0 >> 8) & 0x99) == 0x91: 0 #No execute permissions ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + '(read_csr("mcause") == 0x00000007)': 0 + '(read_csr("mcause") != 0x00000005)': 0 + '(read_csr("mcause") != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 val_comb: '((pmpcfg0 >> 8) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 - '(rs2_val == 0x00000007)': 0 - '(rs2_val != 0x00000005)': 0 - '(rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 + pmp_NAPOT_RX: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; @@ -392,17 +386,17 @@ pmp_NAPOT_RX: ((pmpcfg0 >> 8) & 0x9A) == 0x98: 0 ((pmpcfg0 >> 8) & 0x99) == 0x99: 0 ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + '(read_csr("mcause") == 0x00000007)': 0 + '(read_csr("mcause") != 0x00000005)': 0 + '(read_csr("mcause") != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 val_comb: '((pmpcfg0 >> 8) & 0x9F == 0x9D) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - '(rs2_val == 0x00000007)': 0 - '(rs2_val != 0x00000005)': 0 - '(rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 + pmp_TOR_RX: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; @@ -416,14 +410,13 @@ pmp_TOR_RX: ((pmpcfg0 >> 16) & 0x9A) == 0x88: 0 ((pmpcfg0 >> 16) & 0x99) == 0x89: 0 ((pmpaddr2) >= 0x00000000) and ((pmpaddr2) <= 0xFFFFFFFF): 0 + '(read_csr("mcause") == 0x00000007)': 0 + '(read_csr("mcause") != 0x00000005)': 0 + '(read_csr("mcause") != 0x00000001)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 + '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 val_comb: - '((pmpcfg0 >> 16) & 0x9F == 0x8D) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2))': 0 - '(rs2_val == 0x00000007)': 0 - '(rs2_val != 0x00000005)': 0 - '(rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x800) and rs2_val != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and rs2_val != 0x00000001)': 0 + '((pmpcfg0 >> 16) & 0x9F == 0x8D) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2))': 0 \ No newline at end of file From 0ae3f3ed4e8be1dc5c9b57956698941022affb13 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Tue, 14 Nov 2023 21:45:52 +0500 Subject: [PATCH 3/4] Coverpoints updated --- sample_cgfs/rv32i_pmp.cgf | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/sample_cgfs/rv32i_pmp.cgf b/sample_cgfs/rv32i_pmp.cgf index 21376f91..63e18d09 100644 --- a/sample_cgfs/rv32i_pmp.cgf +++ b/sample_cgfs/rv32i_pmp.cgf @@ -51,16 +51,12 @@ pmp_access_permission: mnemonics: csrrw : 0 csrrs : 0 - mret : 0 sw : 0 csr_comb: (mstatus & 0x1800 != 0x0800) and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 #any other write ignored (mstatus & 0x1800 != 0x0800) and ((old("pmpaddr0")) ^ (pmpaddr0) != 0x00): 0 #any other write ignored - val_comb: - 'mstatus & 0x1800 == 0x800 and (read_csr("mcause") == 0x00000002) and (rs1_val + imm_val >= 0x80005198) and (rs1_val + imm_val <= 0x80005198 + 0x10)' : 0 #Start of mtrap_sigptr - 'mstatus & 0x1800 == 0x800 and (read_csr("mcause") == 0x00000002) and (rs1_val + imm_val >= 0x80005198+0x10) and (rs1_val + imm_val <= 0x80005198 + 0x20)' : 0 #Start of mtrap_sigptr - 'mstatus & 0x1800 == 0x000 and (read_csr("mcause") == 0x00000002) and (rs1_val + imm_val >= 0x80005198+0x20) and (rs1_val + imm_val <= 0x80005198 + 0x30)' : 0 #Start of mtrap_sigptr - 'mstatus & 0x1800 == 0x000 and (read_csr("mcause") == 0x00000002) and (rs1_val + imm_val >= 0x80005198+0x30) and (rs1_val + imm_val <= 0x80005198 + 0x40)' : 0 #Start of mtrap_sigptr + 'mstatus & 0x1800 == 0x800 and (read_csr("mcause") == 0x00000002)' : 0 #Start of mtrap_sigptr + 'mstatus & 0x1800 == 0x000 and (read_csr("mcause") == 0x00000002)' : 0 #Start of mtrap_sigptr pmp_NA4_RWX: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; @@ -120,10 +116,10 @@ pmp_TOR_RWX: lw: 0 sw: 0 csr_comb: - ((pmpcfg0 >> 8) & 0x9C) == 0x94: 0 - ((pmpcfg0 >> 8) & 0x9A) == 0x92: 0 - ((pmpcfg0 >> 8) & 0x99) == 0x91: 0 - ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 + ((pmpcfg0 >> 16) & 0x9C) == 0x8C: 0 + ((pmpcfg0 >> 16) & 0x9A) == 0x8A: 0 + ((pmpcfg0 >> 16) & 0x99) == 0x89: 0 + ((pmpaddr2) >= 0x00000000) and ((pmpaddr2) <= 0xFFFFFFFF): 0 '(read_csr("mcause") != 0x00000007)': 0 '(read_csr("mcause") != 0x00000005)': 0 '(read_csr("mcause") != 0x00000001)': 0 @@ -133,7 +129,7 @@ pmp_TOR_RWX: '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 val_comb: - '((pmpcfg0 >> 8) & 0x9F == 0x97) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 + '((pmpcfg0 >> 16) & 0x9F == 0x8F) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2))': 0 pmp_NA4_RW: config: From e6c6aee73d74fa9a73665dea58414067dcd0a0b3 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Wed, 17 Apr 2024 02:02:15 +0500 Subject: [PATCH 4/4] Coverpoints updated using Translator format and macros added --- sample_cgfs/macro_file.yaml | 903 ++++++++++++++++++++++++++++++ sample_cgfs/rv32i_pmp.cgf | 1030 ++++++++++++++++++++++------------- 2 files changed, 1560 insertions(+), 373 deletions(-) create mode 100644 sample_cgfs/macro_file.yaml diff --git a/sample_cgfs/macro_file.yaml b/sample_cgfs/macro_file.yaml new file mode 100644 index 00000000..943e4081 --- /dev/null +++ b/sample_cgfs/macro_file.yaml @@ -0,0 +1,903 @@ +common: + MSTATUS_UIE: 0x00000001 + MSTATUS_SIE: 0x00000002 + MSTATUS_HIE: 0x00000004 + MSTATUS_MIE: 0x00000008 + MSTATUS_UPIE: 0x00000010 + MSTATUS_SPIE: 0x00000020 + MSTATUS_HPIE: 0x00000040 + MSTATUS_MPIE: 0x00000080 + MSTATUS_SPP: 0x00000100 + MSTATUS_HPP: 0x00000600 + MSTATUS_MPP: 0x00001800 + MSTATUS_FS: 0x00006000 + MSTATUS_VS: 0x00000600 + MSTATUS_XS: 0x00018000 + MSTATUS_MPRV: 0x00020000 + MSTATUS_SUM: 0x00040000 + MSTATUS_MXR: 0x00080000 + MSTATUS_TVM: 0x00100000 + MSTATUS_TW: 0x00200000 + MSTATUS_TSR: 0x00400000 + MSTATUS32_SD: 0x80000000 + MSTATUS_UXL: 0x0000000300000000 + MSTATUS_SXL: 0x0000000C00000000 + MSTATUS64_SD: 0x8000000000000000 + SSTATUS_UIE: 0x00000001 + SSTATUS_SIE: 0x00000002 + SSTATUS_UPIE: 0x00000010 + SSTATUS_SPIE: 0x00000020 + SSTATUS_SPP: 0x00000100 + SSTATUS_FS: 0x00006000 + SSTATUS_XS: 0x00018000 + SSTATUS_SUM: 0x00040000 + SSTATUS_MXR: 0x00080000 + SSTATUS32_SD: 0x80000000 + SSTATUS_UXL: 0x0000000300000000 + SSTATUS64_SD: 0x8000000000000000 + DCSR_CAUSE_NONE: 0 + DCSR_CAUSE_SWBP: 1 + DCSR_CAUSE_HWBP: 2 + DCSR_CAUSE_DEBUGINT: 3 + DCSR_CAUSE_STEP: 4 + DCSR_CAUSE_HALT: 5 + MCONTROL_TYPE_NONE: 0 + MCONTROL_TYPE_MATCH: 2 + MCONTROL_ACTION_DEBUG_EXCEPTION: 0 + MCONTROL_ACTION_DEBUG_MODE: 1 + MCONTROL_ACTION_TRACE_START: 2 + MCONTROL_ACTION_TRACE_STOP: 3 + MCONTROL_ACTION_TRACE_EMIT: 4 + MCONTROL_MATCH_EQUAL: 0 + MCONTROL_MATCH_NAPOT: 1 + MCONTROL_MATCH_GE: 2 + MCONTROL_MATCH_LT: 3 + MCONTROL_MATCH_MASK_LOW: 4 + MCONTROL_MATCH_MASK_HIGH: 5 + SIP_SSIP: MIP_SSIP + SIP_STIP: MIP_STIP + PRV_U: 0 + PRV_S: 1 + PRV_H: 2 + PRV_M: 3 + SATP32_MODE: 0x80000000 + SATP32_ASID: 0x7FC00000 + SATP32_PPN: 0x003FFFFF + SATP64_MODE: 0xF000000000000000 + SATP64_ASID: 0x0FFFF00000000000 + SATP64_PPN: 0x00000FFFFFFFFFFF + SATP_MODE_OFF: 0 + SATP_MODE_SV32: 1 + SATP_MODE_SV39: 8 + SATP_MODE_SV48: 9 + SATP_MODE_SV57: 10 + SATP_MODE_SV64: 11 + PMP_R: 0x01 + PMP_W: 0x02 + PMP_X: 0x04 + PMP_A: 0x18 + PMP_L: 0x80 + PMP_SHIFT: 2 + PMP_TOR: 0x08 + PMP_NA4: 0x10 + PMP_NAPOT: 0x18 + IRQ_S_SOFT: 1 + IRQ_H_SOFT: 2 + IRQ_M_SOFT: 3 + IRQ_S_TIMER: 5 + IRQ_H_TIMER: 6 + IRQ_M_TIMER: 7 + IRQ_S_EXT: 9 + IRQ_H_EXT: 10 + IRQ_M_EXT: 11 + IRQ_COP: 12 + IRQ_HOST: 13 + DEFAULT_RSTVEC: 0x00001000 + CLINT_BASE: 0x02000000 + CLINT_SIZE: 0x000c0000 + EXT_IO_BASE: 0x40000000 + DRAM_BASE: 0x80000000 + PTE_V: 0x001 + PTE_R: 0x002 + PTE_W: 0x004 + PTE_X: 0x008 + PTE_U: 0x010 + PTE_G: 0x020 + PTE_A: 0x040 + PTE_D: 0x080 + PTE_SOFT: 0x300 + PTE_PPN_SHIFT: 10 + RISCV_PGSHIFT: 12 + MATCH_BEQ: 0x63 + MASK_BEQ: 0x707f + MATCH_BNE: 0x1063 + MASK_BNE: 0x707f + MATCH_BLT: 0x4063 + MASK_BLT: 0x707f + MATCH_BGE: 0x5063 + MASK_BGE: 0x707f + MATCH_BLTU: 0x6063 + MASK_BLTU: 0x707f + MATCH_BGEU: 0x7063 + MASK_BGEU: 0x707f + MATCH_JALR: 0x67 + MASK_JALR: 0x707f + MATCH_JAL: 0x6f + MASK_JAL: 0x7f + MATCH_LUI: 0x37 + MASK_LUI: 0x7f + MATCH_AUIPC: 0x17 + MASK_AUIPC: 0x7f + MATCH_ADDI: 0x13 + MASK_ADDI: 0x707f + MATCH_SLLI: 0x1013 + MASK_SLLI: 0xfc00707f + MATCH_SLTI: 0x2013 + MASK_SLTI: 0x707f + MATCH_SLTIU: 0x3013 + MASK_SLTIU: 0x707f + MATCH_XORI: 0x4013 + MASK_XORI: 0x707f + MATCH_SRLI: 0x5013 + MASK_SRLI: 0xfc00707f + MATCH_SRAI: 0x40005013 + MASK_SRAI: 0xfc00707f + MATCH_ORI: 0x6013 + MASK_ORI: 0x707f + MATCH_ANDI: 0x7013 + MASK_ANDI: 0x707f + MATCH_ADD: 0x33 + MASK_ADD: 0xfe00707f + MATCH_SUB: 0x40000033 + MASK_SUB: 0xfe00707f + MATCH_SLL: 0x1033 + MASK_SLL: 0xfe00707f + MATCH_SLT: 0x2033 + MASK_SLT: 0xfe00707f + MATCH_SLTU: 0x3033 + MASK_SLTU: 0xfe00707f + MATCH_XOR: 0x4033 + MASK_XOR: 0xfe00707f + MATCH_SRL: 0x5033 + MASK_SRL: 0xfe00707f + MATCH_SRA: 0x40005033 + MASK_SRA: 0xfe00707f + MATCH_OR: 0x6033 + MASK_OR: 0xfe00707f + MATCH_AND: 0x7033 + MASK_AND: 0xfe00707f + MATCH_ADDIW: 0x1b + MASK_ADDIW: 0x707f + MATCH_SLLIW: 0x101b + MASK_SLLIW: 0xfe00707f + MATCH_SRLIW: 0x501b + MASK_SRLIW: 0xfe00707f + MATCH_SRAIW: 0x4000501b + MASK_SRAIW: 0xfe00707f + MATCH_ADDW: 0x3b + MASK_ADDW: 0xfe00707f + MATCH_SUBW: 0x4000003b + MASK_SUBW: 0xfe00707f + MATCH_SLLW: 0x103b + MASK_SLLW: 0xfe00707f + MATCH_SRLW: 0x503b + MASK_SRLW: 0xfe00707f + MATCH_SRAW: 0x4000503b + MASK_SRAW: 0xfe00707f + MATCH_LB: 0x3 + MASK_LB: 0x707f + MATCH_LH: 0x1003 + MASK_LH: 0x707f + MATCH_LW: 0x2003 + MASK_LW: 0x707f + MATCH_LD: 0x3003 + MASK_LD: 0x707f + MATCH_LBU: 0x4003 + MASK_LBU: 0x707f + MATCH_LHU: 0x5003 + MASK_LHU: 0x707f + MATCH_LWU: 0x6003 + MASK_LWU: 0x707f + MATCH_SB: 0x23 + MASK_SB: 0x707f + MATCH_SH: 0x1023 + MASK_SH: 0x707f + MATCH_SW: 0x2023 + MASK_SW: 0x707f + MATCH_SD: 0x3023 + MASK_SD: 0x707f + MATCH_FENCE: 0xf + MASK_FENCE: 0x707f + MATCH_FENCE_I: 0x100f + MASK_FENCE_I: 0x707f + MATCH_MUL: 0x2000033 + MASK_MUL: 0xfe00707f + MATCH_MULH: 0x2001033 + MASK_MULH: 0xfe00707f + MATCH_MULHSU: 0x2002033 + MASK_MULHSU: 0xfe00707f + MATCH_MULHU: 0x2003033 + MASK_MULHU: 0xfe00707f + MATCH_DIV: 0x2004033 + MASK_DIV: 0xfe00707f + MATCH_DIVU: 0x2005033 + MASK_DIVU: 0xfe00707f + MATCH_REM: 0x2006033 + MASK_REM: 0xfe00707f + MATCH_REMU: 0x2007033 + MASK_REMU: 0xfe00707f + MATCH_MULW: 0x200003b + MASK_MULW: 0xfe00707f + MATCH_DIVW: 0x200403b + MASK_DIVW: 0xfe00707f + MATCH_DIVUW: 0x200503b + MASK_DIVUW: 0xfe00707f + MATCH_REMW: 0x200603b + MASK_REMW: 0xfe00707f + MATCH_REMUW: 0x200703b + MASK_REMUW: 0xfe00707f + MATCH_AMOADD_W: 0x202f + MASK_AMOADD_W: 0xf800707f + MATCH_AMOXOR_W: 0x2000202f + MASK_AMOXOR_W: 0xf800707f + MATCH_AMOOR_W: 0x4000202f + MASK_AMOOR_W: 0xf800707f + MATCH_AMOAND_W: 0x6000202f + MASK_AMOAND_W: 0xf800707f + MATCH_AMOMIN_W: 0x8000202f + MASK_AMOMIN_W: 0xf800707f + MATCH_AMOMAX_W: 0xa000202f + MASK_AMOMAX_W: 0xf800707f + MATCH_AMOMINU_W: 0xc000202f + MASK_AMOMINU_W: 0xf800707f + MATCH_AMOMAXU_W: 0xe000202f + MASK_AMOMAXU_W: 0xf800707f + MATCH_AMOSWAP_W: 0x800202f + MASK_AMOSWAP_W: 0xf800707f + MATCH_LR_W: 0x1000202f + MASK_LR_W: 0xf9f0707f + MATCH_SC_W: 0x1800202f + MASK_SC_W: 0xf800707f + MATCH_AMOADD_D: 0x302f + MASK_AMOADD_D: 0xf800707f + MATCH_AMOXOR_D: 0x2000302f + MASK_AMOXOR_D: 0xf800707f + MATCH_AMOOR_D: 0x4000302f + MASK_AMOOR_D: 0xf800707f + MATCH_AMOAND_D: 0x6000302f + MASK_AMOAND_D: 0xf800707f + MATCH_AMOMIN_D: 0x8000302f + MASK_AMOMIN_D: 0xf800707f + MATCH_AMOMAX_D: 0xa000302f + MASK_AMOMAX_D: 0xf800707f + MATCH_AMOMINU_D: 0xc000302f + MASK_AMOMINU_D: 0xf800707f + MATCH_AMOMAXU_D: 0xe000302f + MASK_AMOMAXU_D: 0xf800707f + MATCH_AMOSWAP_D: 0x800302f + MASK_AMOSWAP_D: 0xf800707f + MATCH_LR_D: 0x1000302f + MASK_LR_D: 0xf9f0707f + MATCH_SC_D: 0x1800302f + MASK_SC_D: 0xf800707f + MATCH_ECALL: 0x73 + MASK_ECALL: 0xffffffff + MATCH_EBREAK: 0x100073 + MASK_EBREAK: 0xffffffff + MATCH_URET: 0x200073 + MASK_URET: 0xffffffff + MATCH_SRET: 0x10200073 + MASK_SRET: 0xffffffff + MATCH_MRET: 0x30200073 + MASK_MRET: 0xffffffff + MATCH_DRET: 0x7b200073 + MASK_DRET: 0xffffffff + MATCH_SFENCE_VMA: 0x12000073 + MASK_SFENCE_VMA: 0xfe007fff + MATCH_WFI: 0x10500073 + MASK_WFI: 0xffffffff + MATCH_CSRRW: 0x1073 + MASK_CSRRW: 0x707f + MATCH_CSRRS: 0x2073 + MASK_CSRRS: 0x707f + MATCH_CSRRC: 0x3073 + MASK_CSRRC: 0x707f + MATCH_CSRRWI: 0x5073 + MASK_CSRRWI: 0x707f + MATCH_CSRRSI: 0x6073 + MASK_CSRRSI: 0x707f + MATCH_CSRRCI: 0x7073 + MASK_CSRRCI: 0x707f + MATCH_FADD_S: 0x53 + MASK_FADD_S: 0xfe00007f + MATCH_FSUB_S: 0x8000053 + MASK_FSUB_S: 0xfe00007f + MATCH_FMUL_S: 0x10000053 + MASK_FMUL_S: 0xfe00007f + MATCH_FDIV_S: 0x18000053 + MASK_FDIV_S: 0xfe00007f + MATCH_FSGNJ_S: 0x20000053 + MASK_FSGNJ_S: 0xfe00707f + MATCH_FSGNJN_S: 0x20001053 + MASK_FSGNJN_S: 0xfe00707f + MATCH_FSGNJX_S: 0x20002053 + MASK_FSGNJX_S: 0xfe00707f + MATCH_FMIN_S: 0x28000053 + MASK_FMIN_S: 0xfe00707f + MATCH_FMAX_S: 0x28001053 + MASK_FMAX_S: 0xfe00707f + MATCH_FSQRT_S: 0x58000053 + MASK_FSQRT_S: 0xfff0007f + MATCH_FADD_D: 0x2000053 + MASK_FADD_D: 0xfe00007f + MATCH_FSUB_D: 0xa000053 + MASK_FSUB_D: 0xfe00007f + MATCH_FMUL_D: 0x12000053 + MASK_FMUL_D: 0xfe00007f + MATCH_FDIV_D: 0x1a000053 + MASK_FDIV_D: 0xfe00007f + MATCH_FSGNJ_D: 0x22000053 + MASK_FSGNJ_D: 0xfe00707f + MATCH_FSGNJN_D: 0x22001053 + MASK_FSGNJN_D: 0xfe00707f + MATCH_FSGNJX_D: 0x22002053 + MASK_FSGNJX_D: 0xfe00707f + MATCH_FMIN_D: 0x2a000053 + MASK_FMIN_D: 0xfe00707f + MATCH_FMAX_D: 0x2a001053 + MASK_FMAX_D: 0xfe00707f + MATCH_FCVT_S_D: 0x40100053 + MASK_FCVT_S_D: 0xfff0007f + MATCH_FCVT_D_S: 0x42000053 + MASK_FCVT_D_S: 0xfff0007f + MATCH_FSQRT_D: 0x5a000053 + MASK_FSQRT_D: 0xfff0007f + MATCH_FADD_Q: 0x6000053 + MASK_FADD_Q: 0xfe00007f + MATCH_FSUB_Q: 0xe000053 + MASK_FSUB_Q: 0xfe00007f + MATCH_FMUL_Q: 0x16000053 + MASK_FMUL_Q: 0xfe00007f + MATCH_FDIV_Q: 0x1e000053 + MASK_FDIV_Q: 0xfe00007f + MATCH_FSGNJ_Q: 0x26000053 + MASK_FSGNJ_Q: 0xfe00707f + MATCH_FSGNJN_Q: 0x26001053 + MASK_FSGNJN_Q: 0xfe00707f + MATCH_FSGNJX_Q: 0x26002053 + MASK_FSGNJX_Q: 0xfe00707f + MATCH_FMIN_Q: 0x2e000053 + MASK_FMIN_Q: 0xfe00707f + MATCH_FMAX_Q: 0x2e001053 + MASK_FMAX_Q: 0xfe00707f + MATCH_FCVT_S_Q: 0x40300053 + MASK_FCVT_S_Q: 0xfff0007f + MATCH_FCVT_Q_S: 0x46000053 + MASK_FCVT_Q_S: 0xfff0007f + MATCH_FCVT_D_Q: 0x42300053 + MASK_FCVT_D_Q: 0xfff0007f + MATCH_FCVT_Q_D: 0x46100053 + MASK_FCVT_Q_D: 0xfff0007f + MATCH_FSQRT_Q: 0x5e000053 + MASK_FSQRT_Q: 0xfff0007f + MATCH_FLE_S: 0xa0000053 + MASK_FLE_S: 0xfe00707f + MATCH_FLT_S: 0xa0001053 + MASK_FLT_S: 0xfe00707f + MATCH_FEQ_S: 0xa0002053 + MASK_FEQ_S: 0xfe00707f + MATCH_FLE_D: 0xa2000053 + MASK_FLE_D: 0xfe00707f + MATCH_FLT_D: 0xa2001053 + MASK_FLT_D: 0xfe00707f + MATCH_FEQ_D: 0xa2002053 + MASK_FEQ_D: 0xfe00707f + MATCH_FLE_Q: 0xa6000053 + MASK_FLE_Q: 0xfe00707f + MATCH_FLT_Q: 0xa6001053 + MASK_FLT_Q: 0xfe00707f + MATCH_FEQ_Q: 0xa6002053 + MASK_FEQ_Q: 0xfe00707f + MATCH_FCVT_W_S: 0xc0000053 + MASK_FCVT_W_S: 0xfff0007f + MATCH_FCVT_WU_S: 0xc0100053 + MASK_FCVT_WU_S: 0xfff0007f + MATCH_FCVT_L_S: 0xc0200053 + MASK_FCVT_L_S: 0xfff0007f + MATCH_FCVT_LU_S: 0xc0300053 + MASK_FCVT_LU_S: 0xfff0007f + MATCH_FMV_X_W: 0xe0000053 + MASK_FMV_X_W: 0xfff0707f + MATCH_FCLASS_S: 0xe0001053 + MASK_FCLASS_S: 0xfff0707f + MATCH_FCVT_W_D: 0xc2000053 + MASK_FCVT_W_D: 0xfff0007f + MATCH_FCVT_WU_D: 0xc2100053 + MASK_FCVT_WU_D: 0xfff0007f + MATCH_FCVT_L_D: 0xc2200053 + MASK_FCVT_L_D: 0xfff0007f + MATCH_FCVT_LU_D: 0xc2300053 + MASK_FCVT_LU_D: 0xfff0007f + MATCH_FMV_X_D: 0xe2000053 + MASK_FMV_X_D: 0xfff0707f + MATCH_FCLASS_D: 0xe2001053 + MASK_FCLASS_D: 0xfff0707f + MATCH_FCVT_W_Q: 0xc6000053 + MASK_FCVT_W_Q: 0xfff0007f + MATCH_FCVT_WU_Q: 0xc6100053 + MASK_FCVT_WU_Q: 0xfff0007f + MATCH_FCVT_L_Q: 0xc6200053 + MASK_FCVT_L_Q: 0xfff0007f + MATCH_FCVT_LU_Q: 0xc6300053 + MASK_FCVT_LU_Q: 0xfff0007f + MATCH_FMV_X_Q: 0xe6000053 + MASK_FMV_X_Q: 0xfff0707f + MATCH_FCLASS_Q: 0xe6001053 + MASK_FCLASS_Q: 0xfff0707f + MATCH_FCVT_S_W: 0xd0000053 + MASK_FCVT_S_W: 0xfff0007f + MATCH_FCVT_S_WU: 0xd0100053 + MASK_FCVT_S_WU: 0xfff0007f + MATCH_FCVT_S_L: 0xd0200053 + MASK_FCVT_S_L: 0xfff0007f + MATCH_FCVT_S_LU: 0xd0300053 + MASK_FCVT_S_LU: 0xfff0007f + MATCH_FMV_W_X: 0xf0000053 + MASK_FMV_W_X: 0xfff0707f + MATCH_FCVT_D_W: 0xd2000053 + MASK_FCVT_D_W: 0xfff0007f + MATCH_FCVT_D_WU: 0xd2100053 + MASK_FCVT_D_WU: 0xfff0007f + MATCH_FCVT_D_L: 0xd2200053 + MASK_FCVT_D_L: 0xfff0007f + MATCH_FCVT_D_LU: 0xd2300053 + MASK_FCVT_D_LU: 0xfff0007f + MATCH_FMV_D_X: 0xf2000053 + MASK_FMV_D_X: 0xfff0707f + MATCH_FCVT_Q_W: 0xd6000053 + MASK_FCVT_Q_W: 0xfff0007f + MATCH_FCVT_Q_WU: 0xd6100053 + MASK_FCVT_Q_WU: 0xfff0007f + MATCH_FCVT_Q_L: 0xd6200053 + MASK_FCVT_Q_L: 0xfff0007f + MATCH_FCVT_Q_LU: 0xd6300053 + MASK_FCVT_Q_LU: 0xfff0007f + MATCH_FMV_Q_X: 0xf6000053 + MASK_FMV_Q_X: 0xfff0707f + MATCH_FLW: 0x2007 + MASK_FLW: 0x707f + MATCH_FLD: 0x3007 + MASK_FLD: 0x707f + MATCH_FLQ: 0x4007 + MASK_FLQ: 0x707f + MATCH_FSW: 0x2027 + MASK_FSW: 0x707f + MATCH_FSD: 0x3027 + MASK_FSD: 0x707f + MATCH_FSQ: 0x4027 + MASK_FSQ: 0x707f + MATCH_FMADD_S: 0x43 + MASK_FMADD_S: 0x600007f + MATCH_FMSUB_S: 0x47 + MASK_FMSUB_S: 0x600007f + MATCH_FNMSUB_S: 0x4b + MASK_FNMSUB_S: 0x600007f + MATCH_FNMADD_S: 0x4f + MASK_FNMADD_S: 0x600007f + MATCH_FMADD_D: 0x2000043 + MASK_FMADD_D: 0x600007f + MATCH_FMSUB_D: 0x2000047 + MASK_FMSUB_D: 0x600007f + MATCH_FNMSUB_D: 0x200004b + MASK_FNMSUB_D: 0x600007f + MATCH_FNMADD_D: 0x200004f + MASK_FNMADD_D: 0x600007f + MATCH_FMADD_Q: 0x6000043 + MASK_FMADD_Q: 0x600007f + MATCH_FMSUB_Q: 0x6000047 + MASK_FMSUB_Q: 0x600007f + MATCH_FNMSUB_Q: 0x600004b + MASK_FNMSUB_Q: 0x600007f + MATCH_FNMADD_Q: 0x600004f + MASK_FNMADD_Q: 0x600007f + MATCH_C_NOP: 0x1 + MASK_C_NOP: 0xffff + MATCH_C_ADDI16SP: 0x6101 + MASK_C_ADDI16SP: 0xef83 + MATCH_C_JR: 0x8002 + MASK_C_JR: 0xf07f + MATCH_C_JALR: 0x9002 + MASK_C_JALR: 0xf07f + MATCH_C_EBREAK: 0x9002 + MASK_C_EBREAK: 0xffff + MATCH_C_LD: 0x6000 + MASK_C_LD: 0xe003 + MATCH_C_SD: 0xe000 + MASK_C_SD: 0xe003 + MATCH_C_ADDIW: 0x2001 + MASK_C_ADDIW: 0xe003 + MATCH_C_LDSP: 0x6002 + MASK_C_LDSP: 0xe003 + MATCH_C_SDSP: 0xe002 + MASK_C_SDSP: 0xe003 + MATCH_C_ADDI4SPN: 0x0 + MASK_C_ADDI4SPN: 0xe003 + MATCH_C_FLD: 0x2000 + MASK_C_FLD: 0xe003 + MATCH_C_LW: 0x4000 + MASK_C_LW: 0xe003 + MATCH_C_FLW: 0x6000 + MASK_C_FLW: 0xe003 + MATCH_C_FSD: 0xa000 + MASK_C_FSD: 0xe003 + MATCH_C_SW: 0xc000 + MASK_C_SW: 0xe003 + MATCH_C_FSW: 0xe000 + MASK_C_FSW: 0xe003 + MATCH_C_ADDI: 0x1 + MASK_C_ADDI: 0xe003 + MATCH_C_JAL: 0x2001 + MASK_C_JAL: 0xe003 + MATCH_C_LI: 0x4001 + MASK_C_LI: 0xe003 + MATCH_C_LUI: 0x6001 + MASK_C_LUI: 0xe003 + MATCH_C_SRLI: 0x8001 + MASK_C_SRLI: 0xec03 + MATCH_C_SRAI: 0x8401 + MASK_C_SRAI: 0xec03 + MATCH_C_ANDI: 0x8801 + MASK_C_ANDI: 0xec03 + MATCH_C_SUB: 0x8c01 + MASK_C_SUB: 0xfc63 + MATCH_C_XOR: 0x8c21 + MASK_C_XOR: 0xfc63 + MATCH_C_OR: 0x8c41 + MASK_C_OR: 0xfc63 + MATCH_C_AND: 0x8c61 + MASK_C_AND: 0xfc63 + MATCH_C_SUBW: 0x9c01 + MASK_C_SUBW: 0xfc63 + MATCH_C_ADDW: 0x9c21 + MASK_C_ADDW: 0xfc63 + MATCH_C_J: 0xa001 + MASK_C_J: 0xe003 + MATCH_C_BEQZ: 0xc001 + MASK_C_BEQZ: 0xe003 + MATCH_C_BNEZ: 0xe001 + MASK_C_BNEZ: 0xe003 + MATCH_C_SLLI: 0x2 + MASK_C_SLLI: 0xe003 + MATCH_C_FLDSP: 0x2002 + MASK_C_FLDSP: 0xe003 + MATCH_C_LWSP: 0x4002 + MASK_C_LWSP: 0xe003 + MATCH_C_FLWSP: 0x6002 + MASK_C_FLWSP: 0xe003 + MATCH_C_MV: 0x8002 + MASK_C_MV: 0xf003 + MATCH_C_ADD: 0x9002 + MASK_C_ADD: 0xf003 + MATCH_C_FSDSP: 0xa002 + MASK_C_FSDSP: 0xe003 + MATCH_C_SWSP: 0xc002 + MASK_C_SWSP: 0xe003 + MATCH_C_FSWSP: 0xe002 + MASK_C_FSWSP: 0xe003 + MATCH_CUSTOM0: 0xb + MASK_CUSTOM0: 0x707f + MATCH_CUSTOM0_RS1: 0x200b + MASK_CUSTOM0_RS1: 0x707f + MATCH_CUSTOM0_RS1_RS2: 0x300b + MASK_CUSTOM0_RS1_RS2: 0x707f + MATCH_CUSTOM0_RD: 0x400b + MASK_CUSTOM0_RD: 0x707f + MATCH_CUSTOM0_RD_RS1: 0x600b + MASK_CUSTOM0_RD_RS1: 0x707f + MATCH_CUSTOM0_RD_RS1_RS2: 0x700b + MASK_CUSTOM0_RD_RS1_RS2: 0x707f + MATCH_CUSTOM1: 0x2b + MASK_CUSTOM1: 0x707f + MATCH_CUSTOM1_RS1: 0x202b + MASK_CUSTOM1_RS1: 0x707f + MATCH_CUSTOM1_RS1_RS2: 0x302b + MASK_CUSTOM1_RS1_RS2: 0x707f + MATCH_CUSTOM1_RD: 0x402b + MASK_CUSTOM1_RD: 0x707f + MATCH_CUSTOM1_RD_RS1: 0x602b + MASK_CUSTOM1_RD_RS1: 0x707f + MATCH_CUSTOM1_RD_RS1_RS2: 0x702b + MASK_CUSTOM1_RD_RS1_RS2: 0x707f + MATCH_CUSTOM2: 0x5b + MASK_CUSTOM2: 0x707f + MATCH_CUSTOM2_RS1: 0x205b + MASK_CUSTOM2_RS1: 0x707f + MATCH_CUSTOM2_RS1_RS2: 0x305b + MASK_CUSTOM2_RS1_RS2: 0x707f + MATCH_CUSTOM2_RD: 0x405b + MASK_CUSTOM2_RD: 0x707f + MATCH_CUSTOM2_RD_RS1: 0x605b + MASK_CUSTOM2_RD_RS1: 0x707f + MATCH_CUSTOM2_RD_RS1_RS2: 0x705b + MASK_CUSTOM2_RD_RS1_RS2: 0x707f + MATCH_CUSTOM3: 0x7b + MASK_CUSTOM3: 0x707f + MATCH_CUSTOM3_RS1: 0x207b + MASK_CUSTOM3_RS1: 0x707f + MATCH_CUSTOM3_RS1_RS2: 0x307b + MASK_CUSTOM3_RS1_RS2: 0x707f + MATCH_CUSTOM3_RD: 0x407b + MASK_CUSTOM3_RD: 0x707f + MATCH_CUSTOM3_RD_RS1: 0x607b + MASK_CUSTOM3_RD_RS1: 0x707f + MATCH_CUSTOM3_RD_RS1_RS2: 0x707b + MASK_CUSTOM3_RD_RS1_RS2: 0x707f + CSR_FFLAGS: 0x1 + CSR_FRM: 0x2 + CSR_FCSR: 0x3 + CSR_CYCLE: 0xc00 + CSR_TIME: 0xc01 + CSR_INSTRET: 0xc02 + CSR_HEDELEG: 0x602 + CSR_HPMCOUNTER3: 0xc03 + CSR_HPMCOUNTER4: 0xc04 + CSR_HPMCOUNTER5: 0xc05 + CSR_HPMCOUNTER6: 0xc06 + CSR_HPMCOUNTER7: 0xc07 + CSR_HPMCOUNTER8: 0xc08 + CSR_HPMCOUNTER9: 0xc09 + CSR_HPMCOUNTER10: 0xc0a + CSR_HPMCOUNTER11: 0xc0b + CSR_HPMCOUNTER12: 0xc0c + CSR_HPMCOUNTER13: 0xc0d + CSR_HPMCOUNTER14: 0xc0e + CSR_HPMCOUNTER15: 0xc0f + CSR_HPMCOUNTER16: 0xc10 + CSR_HPMCOUNTER17: 0xc11 + CSR_HPMCOUNTER18: 0xc12 + CSR_HPMCOUNTER19: 0xc13 + CSR_HPMCOUNTER20: 0xc14 + CSR_HPMCOUNTER21: 0xc15 + CSR_HPMCOUNTER22: 0xc16 + CSR_HPMCOUNTER23: 0xc17 + CSR_HPMCOUNTER24: 0xc18 + CSR_HPMCOUNTER25: 0xc19 + CSR_HPMCOUNTER26: 0xc1a + CSR_HPMCOUNTER27: 0xc1b + CSR_HPMCOUNTER28: 0xc1c + CSR_HPMCOUNTER29: 0xc1d + CSR_HPMCOUNTER30: 0xc1e + CSR_HPMCOUNTER31: 0xc1f + CSR_VSATP: 0x280 + CSR_HSTATUS: 0x600 + CSR_SSTATUS: 0x100 + CSR_SIE: 0x104 + CSR_STVEC: 0x105 + CSR_SCOUNTEREN: 0x106 + CSR_SSCRATCH: 0x140 + CSR_SEPC: 0x141 + CSR_SCAUSE: 0x142 + CSR_STVAL: 0x143 + CSR_SIP: 0x144 + CSR_SATP: 0x180 + CSR_SEDELEG: 0x102 + CSR_MSTATUS: 0x300 + CSR_MSTATUSH: 0x310 + CSR_MISA: 0x301 + CSR_MEDELEG: 0x302 + CSR_MIDELEG: 0x303 + CSR_MIE: 0x304 + CSR_MTVEC: 0x305 + CSR_MCOUNTEREN: 0x306 + CSR_MSCRATCH: 0x340 + CSR_MEPC: 0x341 + CSR_MCAUSE: 0x342 + CSR_MTVAL: 0x343 + CSR_MIP: 0x344 + CSR_PMPCFG0: 0x3a0 + CSR_PMPCFG1: 0x3a1 + CSR_PMPCFG2: 0x3a2 + CSR_PMPCFG3: 0x3a3 + CSR_PMPADDR0: 0x3b0 + CSR_PMPADDR1: 0x3b1 + CSR_PMPADDR2: 0x3b2 + CSR_PMPADDR3: 0x3b3 + CSR_PMPADDR4: 0x3b4 + CSR_PMPADDR5: 0x3b5 + CSR_PMPADDR6: 0x3b6 + CSR_PMPADDR7: 0x3b7 + CSR_PMPADDR8: 0x3b8 + CSR_PMPADDR9: 0x3b9 + CSR_PMPADDR10: 0x3ba + CSR_PMPADDR11: 0x3bb + CSR_PMPADDR12: 0x3bc + CSR_PMPADDR13: 0x3bd + CSR_PMPADDR14: 0x3be + CSR_PMPADDR15: 0x3bf + CSR_TSELECT: 0x7a0 + CSR_TDATA1: 0x7a1 + CSR_TDATA2: 0x7a2 + CSR_TDATA3: 0x7a3 + CSR_DCSR: 0x7b0 + CSR_DPC: 0x7b1 + CSR_DSCRATCH: 0x7b2 + CSR_MCYCLE: 0xb00 + CSR_MINSTRET: 0xb02 + CSR_MHPMCOUNTER3: 0xb03 + CSR_MHPMCOUNTER4: 0xb04 + CSR_MHPMCOUNTER5: 0xb05 + CSR_MHPMCOUNTER6: 0xb06 + CSR_MHPMCOUNTER7: 0xb07 + CSR_MHPMCOUNTER8: 0xb08 + CSR_MHPMCOUNTER9: 0xb09 + CSR_MHPMCOUNTER10: 0xb0a + CSR_MHPMCOUNTER11: 0xb0b + CSR_MHPMCOUNTER12: 0xb0c + CSR_MHPMCOUNTER13: 0xb0d + CSR_MHPMCOUNTER14: 0xb0e + CSR_MHPMCOUNTER15: 0xb0f + CSR_MHPMCOUNTER16: 0xb10 + CSR_MHPMCOUNTER17: 0xb11 + CSR_MHPMCOUNTER18: 0xb12 + CSR_MHPMCOUNTER19: 0xb13 + CSR_MHPMCOUNTER20: 0xb14 + CSR_MHPMCOUNTER21: 0xb15 + CSR_MHPMCOUNTER22: 0xb16 + CSR_MHPMCOUNTER23: 0xb17 + CSR_MHPMCOUNTER24: 0xb18 + CSR_MHPMCOUNTER25: 0xb19 + CSR_MHPMCOUNTER26: 0xb1a + CSR_MHPMCOUNTER27: 0xb1b + CSR_MHPMCOUNTER28: 0xb1c + CSR_MHPMCOUNTER29: 0xb1d + CSR_MHPMCOUNTER30: 0xb1e + CSR_MHPMCOUNTER31: 0xb1f + CSR_MHPMEVENT3: 0x323 + CSR_MHPMEVENT4: 0x324 + CSR_MHPMEVENT5: 0x325 + CSR_MHPMEVENT6: 0x326 + CSR_MHPMEVENT7: 0x327 + CSR_MHPMEVENT8: 0x328 + CSR_MHPMEVENT9: 0x329 + CSR_MHPMEVENT10: 0x32a + CSR_MHPMEVENT11: 0x32b + CSR_MHPMEVENT12: 0x32c + CSR_MHPMEVENT13: 0x32d + CSR_MHPMEVENT14: 0x32e + CSR_MHPMEVENT15: 0x32f + CSR_MHPMEVENT16: 0x330 + CSR_MHPMEVENT17: 0x331 + CSR_MHPMEVENT18: 0x332 + CSR_MHPMEVENT19: 0x333 + CSR_MHPMEVENT20: 0x334 + CSR_MHPMEVENT21: 0x335 + CSR_MHPMEVENT22: 0x336 + CSR_MHPMEVENT23: 0x337 + CSR_MHPMEVENT24: 0x338 + CSR_MHPMEVENT25: 0x339 + CSR_MHPMEVENT26: 0x33a + CSR_MHPMEVENT27: 0x33b + CSR_MHPMEVENT28: 0x33c + CSR_MHPMEVENT29: 0x33d + CSR_MHPMEVENT30: 0x33e + CSR_MHPMEVENT31: 0x33f + CSR_MVENDORID: 0xf11 + CSR_MARCHID: 0xf12 + CSR_MIMPID: 0xf13 + CSR_MHARTID: 0xf14 + CSR_CYCLEH: 0xc80 + CSR_TIMEH: 0xc81 + CSR_INSTRETH: 0xc82 + CSR_HPMCOUNTER3H: 0xc83 + CSR_HPMCOUNTER4H: 0xc84 + CSR_HPMCOUNTER5H: 0xc85 + CSR_HPMCOUNTER6H: 0xc86 + CSR_HPMCOUNTER7H: 0xc87 + CSR_HPMCOUNTER8H: 0xc88 + CSR_HPMCOUNTER9H: 0xc89 + CSR_HPMCOUNTER10H: 0xc8a + CSR_HPMCOUNTER11H: 0xc8b + CSR_HPMCOUNTER12H: 0xc8c + CSR_HPMCOUNTER13H: 0xc8d + CSR_HPMCOUNTER14H: 0xc8e + CSR_HPMCOUNTER15H: 0xc8f + CSR_HPMCOUNTER16H: 0xc90 + CSR_HPMCOUNTER17H: 0xc91 + CSR_HPMCOUNTER18H: 0xc92 + CSR_HPMCOUNTER19H: 0xc93 + CSR_HPMCOUNTER20H: 0xc94 + CSR_HPMCOUNTER21H: 0xc95 + CSR_HPMCOUNTER22H: 0xc96 + CSR_HPMCOUNTER23H: 0xc97 + CSR_HPMCOUNTER24H: 0xc98 + CSR_HPMCOUNTER25H: 0xc99 + CSR_HPMCOUNTER26H: 0xc9a + CSR_HPMCOUNTER27H: 0xc9b + CSR_HPMCOUNTER28H: 0xc9c + CSR_HPMCOUNTER29H: 0xc9d + CSR_HPMCOUNTER30H: 0xc9e + CSR_HPMCOUNTER31H: 0xc9f + CSR_MCYCLEH: 0xb80 + CSR_MINSTRETH: 0xb82 + CSR_MHPMCOUNTER3H: 0xb83 + CSR_MHPMCOUNTER4H: 0xb84 + CSR_MHPMCOUNTER5H: 0xb85 + CSR_MHPMCOUNTER6H: 0xb86 + CSR_MHPMCOUNTER7H: 0xb87 + CSR_MHPMCOUNTER8H: 0xb88 + CSR_MHPMCOUNTER9H: 0xb89 + CSR_MHPMCOUNTER10H: 0xb8a + CSR_MHPMCOUNTER11H: 0xb8b + CSR_MHPMCOUNTER12H: 0xb8c + CSR_MHPMCOUNTER13H: 0xb8d + CSR_MHPMCOUNTER14H: 0xb8e + CSR_MHPMCOUNTER15H: 0xb8f + CSR_MHPMCOUNTER16H: 0xb90 + CSR_MHPMCOUNTER17H: 0xb91 + CSR_MHPMCOUNTER18H: 0xb92 + CSR_MHPMCOUNTER19H: 0xb93 + CSR_MHPMCOUNTER20H: 0xb94 + CSR_MHPMCOUNTER21H: 0xb95 + CSR_MHPMCOUNTER22H: 0xb96 + CSR_MHPMCOUNTER23H: 0xb97 + CSR_MHPMCOUNTER24H: 0xb98 + CSR_MHPMCOUNTER25H: 0xb99 + CSR_MHPMCOUNTER26H: 0xb9a + CSR_MHPMCOUNTER27H: 0xb9b + CSR_MHPMCOUNTER28H: 0xb9c + CSR_MHPMCOUNTER29H: 0xb9d + CSR_MHPMCOUNTER30H: 0xb9e + CSR_MHPMCOUNTER31H: 0xb9f + CAUSE_MISALIGNED_FETCH: 0x0 + CAUSE_FETCH_ACCESS: 0x1 + CAUSE_ILLEGAL_INSTRUCTION: 0x2 + CAUSE_BREAKPOINT: 0x3 + CAUSE_MISALIGNED_LOAD: 0x4 + CAUSE_LOAD_ACCESS: 0x5 + CAUSE_MISALIGNED_STORE: 0x6 + CAUSE_STORE_ACCESS: 0x7 + CAUSE_USER_ECALL: 0x8 + CAUSE_SUPERVISOR_ECALL: 0x9 + CAUSE_HYPERVISOR_ECALL: 0xa + CAUSE_MACHINE_ECALL: 0xb + CAUSE_FETCH_PAGE_FAULT: 0xc + CAUSE_LOAD_PAGE_FAULT: 0xd + CAUSE_STORE_PAGE_FAULT: 0xf + CSR_MENTROPY: 0xF15 + CSR_MNOISE: 0x7A9 + DCSR_XDEBUGVER: (3U<<30) + DCSR_NDRESET: (1<<29) + DCSR_FULLRESET: (1<<28) + DCSR_EBREAKM: (1<<15) + DCSR_EBREAKH: (1<<14) + DCSR_EBREAKS: (1<<13) + DCSR_EBREAKU: (1<<12) + DCSR_STOPCYCLE: (1<<10) + DCSR_STOPTIME: (1<<9) + DCSR_CAUSE: (7<<6) + DCSR_DEBUGINT: (1<<5) + DCSR_HALT: (1<<3) + DCSR_STEP: (1<<2) + DCSR_PRV: (3<<0) + MCONTROL_SELECT: (1<<19) + MCONTROL_TIMING: (1<<18) + MCONTROL_ACTION: (0x3f<<12) + MCONTROL_CHAIN: (1<<11) + MCONTROL_MATCH: (0xf<<7) + MCONTROL_M: (1<<6) + MCONTROL_H: (1<<5) + MCONTROL_S: (1<<4) + MCONTROL_U: (1<<3) + MCONTROL_EXECUTE: (1<<2) + MCONTROL_STORE: (1<<1) + MCONTROL_LOAD: (1<<0) + MIP_SSIP: (1 << IRQ_S_SOFT) + MIP_HSIP: (1 << IRQ_H_SOFT) + MIP_MSIP: (1 << IRQ_M_SOFT) + MIP_STIP: (1 << IRQ_S_TIMER) + MIP_HTIP: (1 << IRQ_H_TIMER) + MIP_MTIP: (1 << IRQ_M_TIMER) + MIP_SEIP: (1 << IRQ_S_EXT) + MIP_HEIP: (1 << IRQ_H_EXT) + MIP_MEIP: (1 << IRQ_M_EXT) + RISCV_PGSIZE: (1 << RISCV_PGSHIFT) \ No newline at end of file diff --git a/sample_cgfs/rv32i_pmp.cgf b/sample_cgfs/rv32i_pmp.cgf index 63e18d09..ee302b95 100644 --- a/sample_cgfs/rv32i_pmp.cgf +++ b/sample_cgfs/rv32i_pmp.cgf @@ -1,418 +1,702 @@ -# *- Write to pmpcfg with L=1 and check that: -# *- Writes are ignored -# *- Writes to other, unrelated entries in the same CSR are not ignored" -pmp_cfg_locked_write_unrelated: +#Load access fault --> ${CAUSE_LOAD_ACCESS} +#Store access fault --> ${CAUSE_STORE_ACCESS} +#Fetch access fault --> ${CAUSE_FETCH_ACCESS} +PMP_NAPOT_r: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + #0x99 & 0xF9 = 0x99 | 0x9A & 0xF9 = 0x98 | 0x9C & 0xF9 = 0x98 + ((pmpcfg0 >> 8) & {0x99, 0x9A, 0x9C}) == (0xF9 & $1): 0 #No write, Execute permission + pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated + pmpaddr{0 ... 3} != 0 and ((old("pmpaddr$1")) ^ (pmpaddr$1) != 0x00): 0 #pmpaddr have been updated + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #Check the napot region is accessed at least once + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x99) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + +PMP_NAPOT_x: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg0 >> 8) & {0x99, 0x9A, 0x9C}) == (0xFC & $1): 0 #No Read, Write permission + pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated + pmpaddr{0 ... 3} != 0 and ((old("pmpaddr$1")) ^ (pmpaddr$1) != 0x00): 0 #pmpaddr have been updated + val_comb: + # Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault + mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #read, write fault + #Check the napot region is accessed at least once + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + +PMP_NAPOT_rw: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg0 >> 8) & {0x99, 0x9A, 0x9C}) == (0xFB & $1): 0 #No Execute permission + pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated + pmpaddr{0 ... 3} != 0 and ((old("pmpaddr$1")) ^ (pmpaddr$1) != 0x00): 0 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #Check the napot region is accessed at least once + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + +PMP_NAPOT_rx: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg0 >> 8) & {0x99, 0x9A, 0x9C}) == (0xFD & $1): 0 #No Write permission + pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated + pmpaddr{0 ... 3} != 0 and ((old("pmpaddr$1")) ^ (pmpaddr$1) != 0x00): 0 #pmpaddr have been updated + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No read, Execute fault + mode == 'M' and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault + #Check the napot region is accessed at least once + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + +PMP_NAPOT_rwx: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg0 >> 8) & {0x9C, 0x9A, 0x99}) == (0xFF & $1): 0 #All permissions given + pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated + (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write or execute fault + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9F) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + +PMP_TOR_r: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg0 >> 16) & {0x8C, 0x8A, 0x89}) == (0x89 & $1): 0 #Only Read Permission given + pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated + (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + '(mnemonic == "lw" or mnemonic == "sw") and (((pmpcfg0 >> 16) & 0x9F == 0x89) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)))': 0 + +PMP_TOR_x: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg0 >> 16) & {0x8C, 0x8A, 0x89}) == (0x8C & $1): 0 #Only Execute Permission given + pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated + (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault + mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #Read, Write fault + #check for the read, write access + '(mnemonic == "lw" or mnemonic == "sw") and (((pmpcfg0 >> 16) & 0x9F == 0x8C) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)))': 0 + +PMP_TOR_rw: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg0 >> 16) & {0x9C, 0x9A, 0x99}) == (0x8B & $1): 0 #Only Read, Write Permission given + pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated + (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + '(mnemonic == "lw" or mnemonic == "sw") and (((pmpcfg0 >> 16) & 0x9F == 0x8B) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)))': 0 + +PMP_TOR_rx: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg0 >> 16) & {0x8C, 0x8A, 0x89}) == (0x8D & $1): 0 #Only Read, Execute Permission given + pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated + (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No read, execute fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault + #check for the read, write access + '(mnemonic == "lw" or mnemonic == "sw") and (((pmpcfg0 >> 16) & 0x9F == 0x8D) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)))': 0 + +PMP_TOR_rwx: config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - csrrw: 0 - csrrs: 0 - csr_comb: - (pmpcfg0 & 0x80 == 0x80) and (old("pmpcfg0") & 0xFF) ^ (pmpcfg0 & 0xFF) == 0x00: 0 #any other write ignored - (pmpcfg0 & 0x80 == 0x80) and (old("pmpaddr0")) ^ (pmpaddr0) == 0x00: 0 #any other write ignored - (pmpcfg0>>8 & 0x80 == 0x80) and (old("pmpcfg0") & (0xFF<<8)) ^ (pmpcfg0 & (0xFF<<8)) == 0x00: 0 #any other write ignored - (pmpcfg0>>8 & 0x80 == 0x80) and (old("pmpaddr1")) ^ (pmpaddr1) == 0x00: 0 #any other write ignored - (pmpcfg0>>16 & 0x80 == 0x80) and (old("pmpcfg0") & (0xFF<<16)) ^ (pmpcfg0 & (0xFF<<16)) == 0x00: 0 #any other write ignored - (pmpcfg0>>16 & 0x80 == 0x80) and (old("pmpaddr2")) ^ (pmpaddr2) == 0x00: 0 #any other write ignored - (pmpcfg0>>24 & 0x80 == 0x80) and (old("pmpcfg0") & (0xFF<<24)) ^ (pmpcfg0 & (0xFF<<24)) == 0x00: 0 #any other write ignored - (pmpcfg0>>24 & 0x80 == 0x80) and (old("pmpaddr3")) ^ (pmpaddr3) == 0x00: 0 #any other write ignored - (pmpcfg1 & 0x80 == 0x80) and (old("pmpcfg1") & 0xFF) ^ (pmpcfg1 & 0xFF) == 0x00: 0 #any other write ignored - (pmpcfg1 & 0x80 == 0x80) and (old("pmpaddr4")) ^ (pmpaddr4) == 0x00: 0 #any other write ignored - (pmpcfg1>>8 & 0x80 == 0x80) and (old("pmpcfg1") & (0xFF<<8)) ^ (pmpcfg1 & (0xFF<<8)) == 0x00: 0 #any other write ignored - (pmpcfg1>>8 & 0x80 == 0x80) and (old("pmpaddr5")) ^ (pmpaddr5) == 0x00: 0 #any other write ignored - (pmpcfg1>>16 & 0x80 == 0x80) and (old("pmpcfg1") & (0xFF<<16)) ^ (pmpcfg1 & (0xFF<<16)) == 0x00: 0 #any other write ignored - (pmpcfg1>>16 & 0x80 == 0x80) and (old("pmpaddr6")) ^ (pmpaddr6) == 0x00: 0 #any other write ignored - (pmpcfg1>>24 & 0x80 == 0x80) and (old("pmpcfg1") & (0xFF<<24)) ^ (pmpcfg1 & (0xFF<<24)) == 0x00: 0 #any other write ignored - (pmpcfg1>>24 & 0x80 == 0x80) and (old("pmpaddr7")) ^ (pmpaddr7) == 0x00: 0 #any other write ignored - (pmpcfg2 & 0x80 == 0x80) and (old("pmpcfg2") & 0xFF) ^ (pmpcfg2 & 0xFF) == 0x00: 0 #any other write ignored - (pmpcfg2 & 0x80 == 0x80) and (old("pmpaddr8")) ^ (pmpaddr8) == 0x00: 0 #any other write ignored - (pmpcfg2>>8 & 0x80 == 0x80) and (old("pmpcfg2") & (0xFF<<8)) ^ (pmpcfg2 & (0xFF<<8)) == 0x00: 0 #any other write ignored - (pmpcfg2>>8 & 0x80 == 0x80) and (old("pmpaddr9")) ^ (pmpaddr9) == 0x00: 0 #any other write ignored - (pmpcfg2>>16 & 0x80 == 0x80) and (old("pmpcfg2") & (0xFF<<16)) ^ (pmpcfg2 & (0xFF<<16)) == 0x00: 0 #any other write ignored - (pmpcfg2>>16 & 0x80 == 0x80) and (old("pmpaddr10")) ^ (pmpaddr10) == 0x00: 0 #any other write ignored - (pmpcfg2>>24 & 0x80 == 0x80) and (old("pmpcfg2") & (0xFF<<24)) ^ (pmpcfg2 & (0xFF<<24)) == 0x00: 0 #any other write ignored - (pmpcfg2>>24 & 0x80 == 0x80) and (old("pmpaddr11")) ^ (pmpaddr11) == 0x00: 0 #any other write ignored - (pmpcfg3 & 0x80 == 0x80) and (old("pmpcfg3") & 0xFF) ^ (pmpcfg3 & 0xFF) == 0x00: 0 #any other write ignored - (pmpcfg3 & 0x80 == 0x80) and (old("pmpaddr12")) ^ (pmpaddr12) == 0x00: 0 #any other write ignored - (pmpcfg3>>8 & 0x80 == 0x80) and (old("pmpcfg3") & (0xFF<<8)) ^ (pmpcfg3 & (0xFF<<8)) == 0x00: 0 #any other write ignored - (pmpcfg3>>8 & 0x80 == 0x80) and (old("pmpaddr13")) ^ (pmpaddr13) == 0x00: 0 #any other write ignored - (pmpcfg3>>16 & 0x80 == 0x80) and (old("pmpcfg3") & (0xFF<<16)) ^ (pmpcfg3 & (0xFF<<16)) == 0x00: 0 #any other write ignored - (pmpcfg3>>16 & 0x80 == 0x80) and (old("pmpaddr14")) ^ (pmpaddr14) == 0x00: 0 #any other write ignored - (pmpcfg3>>24 & 0x80 == 0x80) and (old("pmpcfg3") & (0xFF<<24)) ^ (pmpcfg3 & (0xFF<<24)) == 0x00: 0 #any other write ignored - (pmpcfg3>>24 & 0x80 == 0x80) and (old("pmpaddr15")) ^ (pmpaddr15) == 0x00: 0 #any other write ignored -# #------------------------------------------------------------------------------ -# #PMP Permission. Check csrrw. csrrs and csrrc in all 3 modes -# # *No exception in Machine mode -# # *Page 57 -- pmp csrs accessible only in M mode. So, exception in Supervisor mode -# # *Page 57 -- pmp csrs accessible only in M mode. So, exception in User mode -pmp_access_permission: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - csrrw : 0 - csrrs : 0 - sw : 0 - csr_comb: - (mstatus & 0x1800 != 0x0800) and ((old("pmpcfg0")) ^ (pmpcfg0) != 0x00): 0 #any other write ignored - (mstatus & 0x1800 != 0x0800) and ((old("pmpaddr0")) ^ (pmpaddr0) != 0x00): 0 #any other write ignored - 'mstatus & 0x1800 == 0x800 and (read_csr("mcause") == 0x00000002)' : 0 #Start of mtrap_sigptr - 'mstatus & 0x1800 == 0x000 and (read_csr("mcause") == 0x00000002)' : 0 #Start of mtrap_sigptr -pmp_NA4_RWX: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - csrrw: 0 - csrrs: 0 - lw: 0 - sw: 0 - csr_comb: - ((pmpcfg0 >> 8) & 0x9C) == 0x94: 0 - ((pmpcfg0 >> 8) & 0x9A) == 0x92: 0 - ((pmpcfg0 >> 8) & 0x99) == 0x91: 0 - ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 - #No exception in M Mode - '(read_csr("mcause") != 0x00000007)': 0 - '(read_csr("mcause") != 0x00000005)': 0 - '(read_csr("mcause") != 0x00000001)': 0 - #No exception in S and U Mode - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 - val_comb: - #address should be in range of PMP - '((pmpcfg0 >> 8) & 0x9F == 0x97) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 -pmp_NAPOT_RWX: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - csrrw: 0 - csrrs: 0 - lw: 0 - sw: 0 - csr_comb: - ((pmpcfg0 >> 8) & 0x9C) == 0x9C: 0 - ((pmpcfg0 >> 8) & 0x9A) == 0x9A: 0 - ((pmpcfg0 >> 8) & 0x99) == 0x99: 0 - ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 - '(read_csr("mcause") != 0x00000007)': 0 - '(read_csr("mcause") != 0x00000005)': 0 - '(read_csr("mcause") != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 - val_comb: - '((pmpcfg0 >> 8) & 0x9F == 0x9F) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -pmp_TOR_RWX: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - csrrw: 0 - csrrs: 0 - lw: 0 - sw: 0 - csr_comb: - ((pmpcfg0 >> 16) & 0x9C) == 0x8C: 0 - ((pmpcfg0 >> 16) & 0x9A) == 0x8A: 0 - ((pmpcfg0 >> 16) & 0x99) == 0x89: 0 - ((pmpaddr2) >= 0x00000000) and ((pmpaddr2) <= 0xFFFFFFFF): 0 - '(read_csr("mcause") != 0x00000007)': 0 - '(read_csr("mcause") != 0x00000005)': 0 - '(read_csr("mcause") != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 - val_comb: - '((pmpcfg0 >> 16) & 0x9F == 0x8F) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2))': 0 - -pmp_NA4_RW: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - csrrw: 0 - csrrs: 0 - lw: 0 - sw: 0 - csr_comb: - ((pmpcfg0 >> 8) & 0x9C) == 0x90: 0 - ((pmpcfg0 >> 8) & 0x9A) == 0x92: 0 - ((pmpcfg0 >> 8) & 0x99) == 0x91: 0 #No execute permissions - ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 - '(read_csr("mcause") != 0x00000007)': 0 - '(read_csr("mcause") != 0x00000005)': 0 - '(read_csr("mcause") == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000001)': 0 - val_comb: - '((pmpcfg0 >> 8) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 - -pmp_NAPOT_RW: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - csrrw: 0 - csrrs: 0 - lw: 0 - sw: 0 - csr_comb: - ((pmpcfg0 >> 8) & 0x9C) == 0x98: 0 - ((pmpcfg0 >> 8) & 0x9A) == 0x9A: 0 - ((pmpcfg0 >> 8) & 0x99) == 0x99: 0 - ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 - '(read_csr("mcause") != 0x00000007)': 0 - '(read_csr("mcause") != 0x00000005)': 0 - '(read_csr("mcause") == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000001)': 0 + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg0 >> 16) & {0x9C, 0x9A, 0x99}) == (0x8F & $1): 0 #Only Read, Write Permission given + pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated + (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 val_comb: - '((pmpcfg0 >> 8) & 0x9F == 0x9B) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 -pmp_TOR_RW: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write, execute fault + '(mnemonic == "lw" or mnemonic == "sw") and (((pmpcfg0 >> 16) & 0x9F == 0x8F) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)))': 0 + +PMP_NA4_r: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; mnemonics: - csrrw: 0 - csrrs: 0 - lw: 0 - sw: 0 - csr_comb: - ((pmpcfg0 >> 16) & 0x9C) == 0x88: 0 - ((pmpcfg0 >> 16) & 0x9A) == 0x8A: 0 - ((pmpcfg0 >> 16) & 0x99) == 0x89: 0 - ((pmpaddr2) >= 0x00000000) and ((pmpaddr2) <= 0xFFFFFFFF): 0 - '(read_csr("mcause") != 0x00000007)': 0 - '(read_csr("mcause") != 0x00000005)': 0 - '(read_csr("mcause") == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000001)': 0 + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x91 & $1): 0 #Only Read Permission given + pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated + (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 val_comb: - '((pmpcfg0 >> 16) & 0x9F == 0x8B) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2))': 0 + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #check for the read, write access + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 -pmp_NA4_R: +PMP_NA4_x: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; mnemonics: - csrrw: 0 - csrrs: 0 - lw: 0 - sw: 0 - csr_comb: - ((pmpcfg0 >> 8) & 0x9C) == 0x90: 0 - ((pmpcfg0 >> 8) & 0x9A) == 0x90: 0 - ((pmpcfg0 >> 8) & 0x99) == 0x91: 0 #No execute permissions - ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 - '(read_csr("mcause") == 0x00000007)': 0 - '(read_csr("mcause") != 0x00000005)': 0 - '(read_csr("mcause") == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000001)': 0 + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x94 & $1): 0 #Only Execute Permission given + pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated + (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 val_comb: - '((pmpcfg0 >> 8) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 -pmp_NAPOT_R: + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault + mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #read, write fault + #check for the read, write access + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 + +PMP_NA4_rw: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x93 & $1): 0 #Only Read, Write Permission given + pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated + (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #check for the read, write access + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 + +PMP_NA4_rx: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; mnemonics: - csrrw: 0 - csrrs: 0 - lw: 0 - sw: 0 - csr_comb: - ((pmpcfg0 >> 8) & 0x9C) == 0x98: 0 - ((pmpcfg0 >> 8) & 0x9A) == 0x98: 0 - ((pmpcfg0 >> 8) & 0x99) == 0x99: 0 - ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 - '(read_csr("mcause") == 0x00000007)': 0 - '(read_csr("mcause") != 0x00000005)': 0 - '(read_csr("mcause") == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000001)': 0 - val_comb: - '((pmpcfg0 >> 8) & 0x9F == 0x99) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x95 & $1): 0 #Only Read, Execute Permission given + pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated + (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No read, execute fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #write fault + #check for the read, write access + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 -pmp_TOR_R: +PMP_NA4_rwx: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; mnemonics: - csrrw: 0 - csrrs: 0 - lw: 0 - sw: 0 - csr_comb: - ((pmpcfg0 >> 16) & 0x9C) == 0x88: 0 - ((pmpcfg0 >> 16) & 0x9A) == 0x88: 0 - ((pmpcfg0 >> 16) & 0x99) == 0x89: 0 - ((pmpaddr2) >= 0x00000000) and ((pmpaddr2) <= 0xFFFFFFFF): 0 - '(read_csr("mcause") == 0x00000007)': 0 - '(read_csr("mcause") != 0x00000005)': 0 - '(read_csr("mcause") == 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000001)': 0 - val_comb: - '((pmpcfg0 >> 16) & 0x9F == 0x89) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2))': 0 + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x97 & $1): 0 #Only Read, Write, Execute Permission given + pmpcfg{0 ... 1} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg have been updated + (old("pmpaddr{0 ... 3}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr0 has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, execute fault + #check for the read, write access + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x97) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 -pmp_NA4_X: +PMP_TOR_priority_r: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; mnemonics: - csrrw: 0 - csrrs: 0 - lw: 0 - sw: 0 - csr_comb: - ((pmpcfg0 >> 8) & 0x9C) == 0x94: 0 - ((pmpcfg0 >> 8) & 0x9A) == 0x90: 0 - ((pmpcfg0 >> 8) & 0x99) == 0x90: 0 #No execute permissions - ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 - '(read_csr("mcause") == 0x00000007)': 0 - '(read_csr("mcause") == 0x00000005)': 0 - '(read_csr("mcause") != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x89 & $1): 0 #Read Permission given to high priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.P0) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 val_comb: - '((pmpcfg0 >> 8) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x89) and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 << 2))': 0 -pmp_NAPOT_X: +PMP_TOR_priority_x: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; mnemonics: - csrrw: 0 - csrrs: 0 - lw: 0 - sw: 0 - csr_comb: - ((pmpcfg0 >> 8) & 0x9C) == 0x9C: 0 - ((pmpcfg0 >> 8) & 0x9A) == 0x98: 0 - ((pmpcfg0 >> 8) & 0x99) == 0x98: 0 - ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 - '(read_csr("mcause") == 0x00000007)': 0 - '(read_csr("mcause") == 0x00000005)': 0 - '(read_csr("mcause") != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 - val_comb: - '((pmpcfg0 >> 8) & 0x9F == 0x9C) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 - -pmp_TOR_X: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8C & $1): 0 #Read Permission given to high priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.P0) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault + mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #read, write fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x8C) and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 << 2))': 0 + +PMP_TOR_priority_rw: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - csrrw: 0 - csrrs: 0 - lw: 0 - sw: 0 - csr_comb: - ((pmpcfg0 >> 16) & 0x9C) == 0x8C: 0 - ((pmpcfg0 >> 16) & 0x9A) == 0x88: 0 - ((pmpcfg0 >> 16) & 0x99) == 0x88: 0 - ((pmpaddr2) >= 0x00000000) and ((pmpaddr2) <= 0xFFFFFFFF): 0 - '(read_csr("mcause") == 0x00000007)': 0 - '(read_csr("mcause") == 0x00000005)': 0 - '(read_csr("mcause") != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8B & $1): 0 #Read, Write Permission given to high priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.P0) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 val_comb: - '((pmpcfg0 >> 16) & 0x9F == 0x8C) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2))': 0 + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x8B) and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 << 2))': 0 -pmp_NA4_RX: +PMP_TOR_priority_rx: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; mnemonics: - csrrw: 0 - csrrs: 0 - lw: 0 - sw: 0 - csr_comb: - ((pmpcfg0 >> 8) & 0x9C) == 0x94: 0 - ((pmpcfg0 >> 8) & 0x9A) == 0x90: 0 - ((pmpcfg0 >> 8) & 0x99) == 0x91: 0 #No execute permissions - ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 - '(read_csr("mcause") == 0x00000007)': 0 - '(read_csr("mcause") != 0x00000005)': 0 - '(read_csr("mcause") != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8D & $1): 0 #Read, Execute Permission given to high priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.P0) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 val_comb: - '((pmpcfg0 >> 8) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr1 << 2))': 0 + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No read, execute fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x8D) and (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 << 2))': 0 -pmp_NAPOT_RX: +PMP_TOR_priority_r_level_2: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; mnemonics: - csrrw: 0 - csrrs: 0 - lw: 0 - sw: 0 - csr_comb: - ((pmpcfg0 >> 8) & 0x9C) == 0x9C: 0 - ((pmpcfg0 >> 8) & 0x9A) == 0x98: 0 - ((pmpcfg0 >> 8) & 0x99) == 0x99: 0 - ((pmpaddr1) >= 0x00000000) and ((pmpaddr1) <= 0xFFFFFFFF): 0 - '(read_csr("mcause") == 0x00000007)': 0 - '(read_csr("mcause") != 0x00000005)': 0 - '(read_csr("mcause") != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region + ((pmpcfg0 >> 8) & {0x8C, 0x8A, 0x89}) == (0x89 & $1): 0 #Read Permission given to highest priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15, 0, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 val_comb: - '((pmpcfg0 >> 8) & 0x9F == 0x9D) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x89) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 -pmp_TOR_RX: +PMP_TOR_priority_rw_level_2: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; mnemonics: - csrrw: 0 - csrrs: 0 - lw: 0 - sw: 0 - csr_comb: - ((pmpcfg0 >> 16) & 0x9C) == 0x8C: 0 - ((pmpcfg0 >> 16) & 0x9A) == 0x88: 0 - ((pmpcfg0 >> 16) & 0x99) == 0x89: 0 - ((pmpaddr2) >= 0x00000000) and ((pmpaddr2) <= 0xFFFFFFFF): 0 - '(read_csr("mcause") == 0x00000007)': 0 - '(read_csr("mcause") != 0x00000005)': 0 - '(read_csr("mcause") != 0x00000001)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x800) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") == 0x00000007)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000005)': 0 - '((mstatus & 0x1800 == 0x000) and read_csr("mcause") != 0x00000001)': 0 + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region + ((pmpcfg0 >> 8) & {0x8C, 0x8A, 0x89}) == (0x8B & $1): 0 #Read, Write Permission given to highest priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15, 0, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8B) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 + +PMP_TOR_priority_x_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region + ((pmpcfg0 >> 8) & {0x8C, 0x8A, 0x89}) == (0x8C & $1): 0 #Execute Permission given to highest priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15, 0, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault + mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #read, write fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8C) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 + +PMP_TOR_priority_rx_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region + ((pmpcfg0 >> 8) & {0x8C, 0x8A, 0x89}) == (0x8D & $1): 0 #Read, Execute Permission given to highest priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15, 0, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_FETCH_ACCESS}}): 0 #No read, execute fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #write fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8D) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 + +PMP_TOR_priority_rwx_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region + ((pmpcfg0 >> 8) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Execute Permission given to highest priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15, 0, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_FETCH_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, execute fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x8F) and (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))': 0 + +PMP_NAPOT_priority_r: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x9C, 0x9A, 0x99}) == (0x99 & $1): 0 #Read Permission given to high priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x99) and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1)))': 0 + +PMP_NAPOT_priority_rw: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x9C, 0x9A, 0x99}) == (0x9B & $1): 0 #Read, Write Permission given to high priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x9B) and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1)))': 0 + +PMP_NAPOT_priority_x: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x9C, 0x9A, 0x99}) == (0x9C & $1): 0 #Execute Permission given to high priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No Execute fault + mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #read, write fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x9C) and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1)))': 0 + +PMP_NAPOT_priority_rx: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x9C, 0x9A, 0x99}) == (0x9D & $1): 0 #Read, Execute Permission given to high priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No Read, Execute fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #write fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x9D) and (rs1_val + imm_val >= (pmpaddr3 << 2)) and (rs1_val + imm_val < ((((((pmpaddr3 << 2) | 3) + 1) | (((pmpaddr3 << 2) | 3))) + 1)))': 0 + +PMP_NAPOT_priority_r_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region + ((pmpcfg0 >> 8) & {0x9C, 0x9A, 0x99}) == (0x99 & $1): 0 #Read Permission given to highest priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No read fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x99) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + +PMP_NAPOT_priority_rw_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region + ((pmpcfg0 >> 8) & {0x9C, 0x9A, 0x99}) == (0x9B & $1): 0 #Read, Write Permission given to highest priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No read, write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + +PMP_NAPOT_priority_x_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region + ((pmpcfg0 >> 8) & {0x9C, 0x9A, 0x99}) == (0x9C & $1): 0 #Execute Permission given to highest priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No execute fault + mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #Read, write fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + +PMP_NAPOT_priority_rx_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region + ((pmpcfg0 >> 8) & {0x9C, 0x9A, 0x99}) == (0x9D & $1): 0 #Read, Execute Permission given to highest priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No read, execute fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Read, write fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < ((((((pmpaddr1 << 2) | 3) + 1) | (((pmpaddr1 << 2) | 3))) + 1)))': 0 + +PMP_NA4_priority_r: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x94, 0x92, 0x91}) == (0x91 & $1): 0 #Read Permission given to high priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No Read fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr3 << 2))' : 0 + +PMP_NA4_priority_rw: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x94, 0x92, 0x91}) == (0x93 & $1): 0 #Read, Write Permission given to high priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No Read, Write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr3 << 2))' : 0 + +PMP_NA4_priority_x: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x94, 0x92, 0x91}) == (0x94 & $1): 0 #Execute Permission given to high priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No Execute fault + mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #Read, Write fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr3 << 2))' : 0 + +PMP_NA4_priority_rx: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #TOR -- Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x94, 0x92, 0x91}) == (0x95 & $1): 0 #Read, Execute Permission given to high priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{3, 14, 15}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_FETCH_ACCESS}, ${CAUSE_LOAD_ACCESS}}): 0 #No Read, Execute fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 24) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr3 << 2))' : 0 + +PMP_NA4_priority_r_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region + ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x91 & $1): 0 #Read Permission given to highest priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_LOAD_ACCESS}): 0 #No Read fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x91) and (rs1_val + imm_val == (pmpaddr1 << 2))' : 0 + +PMP_NA4_priority_rw_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region + ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x93 & $1): 0 #Read, Write Permission given to highest priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #No Read, Write fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 #execute fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x93) and (rs1_val + imm_val == (pmpaddr1 << 2))' : 0 + +PMP_NA4_priority_x_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region + ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x94 & $1): 0 #Execute Permission given to highest priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != ${CAUSE_FETCH_ACCESS}): 0 #No Execute fault + mode == {'M','S','U'} and (mcause == {${CAUSE_LOAD_ACCESS}, ${CAUSE_STORE_ACCESS}}): 0 #Read, Write fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x94) and (rs1_val + imm_val == (pmpaddr1 << 2))' : 0 + +PMP_NA4_priority_rx_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + ((pmpcfg3 >> 24) & {0x8C, 0x8A, 0x89}) == (0x8F & $1): 0 #Read, Write, execute Permission given to low priority region + ((pmpcfg0 >> 24) & {0x8C, 0x8A, 0x89}) == (0x88 & $1): 0 #No Permission given to high priority region + ((pmpcfg0 >> 8) & {0x94, 0x92, 0x91}) == (0x95 & $1): 0 #Read, Execute Permission given to highest priority region + pmpcfg{0, 3} != 0 and ((old("pmpcfg$1")) ^ (pmpcfg$1) != 0x00): 0 #pmpcfg0(H.S.P) and pmpcfg0(H.P) and pmpcfg3(L.P) have been updated + (old("pmpaddr{2, 3, 14, 15, 1}")) ^ (pmpaddr$1) != 0x00: 0 #pmpaddr has been used and updated from the previous value i.e., 0x000 + val_comb: + #Test for exceptions + mode == {'M','S','U'} and (mcause != {${CAUSE_LOAD_ACCESS},${CAUSE_FETCH_ACCESS}}): 0 #No Read, Execute fault + mode == {'M','S','U'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 #Write fault + #check for the accesses + '(mnemonic == "lw" or mnemonic == "sw") and ((pmpcfg0 >> 8) & 0x9F == 0x95) and (rs1_val + imm_val == (pmpaddr1 << 2))' : 0 + +pmp_cfg_locked_write_unrelated: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + (pmpcfg{0 ... 3} >> {0, 8, 16, 24} & 0x80 == 0x80) and ((old("pmpcfg$1") & (0xFF << $2)) ^ (pmpcfg$1 & (0xFF << $2)) == 0x00) and old("pmpcfg$1") != 0: 0 + ((old("pmpaddr{0 ... 15}")) ^ (pmpaddr$1) == 0x00) and (pmpcfg{0,1,2,3}{[$1/4]} >> {0, 8, 16, 24}{[$1/4]} & 0x80 == 0x80): 0 + +PMP_access_permission: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw}" : 0 + csr_comb: + mode == 'M' and (((old("pmpcfg{0 ... 3}") ^ (pmpcfg$1)) != 0x00) and pmpcfg$1 != 0x0): 0 #pmpcfg successfully updated in M mode + mode == 'M' and (((old("pmpaddr{0 ... 15}") ^ (pmpaddr$1)) != 0x00) and pmpaddr$1 != 0x0): 0 #pmpaddr successfully updated in M mode val_comb: - '((pmpcfg0 >> 16) & 0x9F == 0x8D) and (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2))': 0 \ No newline at end of file + mnemonic == {"csrrs", "csrrw"} and mode == {'S', 'U'} and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}: 0 #check for illegal instruction fault \ No newline at end of file