From 92923d1db696eeb2d32f576455adfd463ba73201 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Sat, 5 Mar 2022 14:55:54 +0530 Subject: [PATCH 01/41] CLI to clone riscv-opcodes and set path --- riscv_isac/plugins/rv_opcodes_decoder.py | 49 ++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 riscv_isac/plugins/rv_opcodes_decoder.py diff --git a/riscv_isac/plugins/rv_opcodes_decoder.py b/riscv_isac/plugins/rv_opcodes_decoder.py new file mode 100644 index 0000000..7f572d3 --- /dev/null +++ b/riscv_isac/plugins/rv_opcodes_decoder.py @@ -0,0 +1,49 @@ +import os +import click +from git import Repo + +import riscv_isac.plugins as plugins + +# Path to riscv-opcodes +path_to_opcodes = '' + +@click.group() +@click.option('--setup', + is_flag=True, + help='Setup decoder from riscv-opcodes') +def cli(setup): + pass + +@cli.command(help = 'URL to the riscv-opcodes github repo') +@click.option('--url', + type = str, + default='https://github.com/incoresemi/riscv-opcodes', + required=False) +def clone(url): + Repo.clone_from(url, './riscv-opcodes/') + path_to_opcodes = os.getcwd() + '/riscv-opcodes/' + print(path_to_opcodes) + +# Temporary CLI command to clean the cloned repo +@cli.command(help = 'Clean cloned repo') +@click.option('--clean', + default='./riscv-opcodes') +def clean(clean): + os.system('rm -r -f ' + clean) + +# Disassembler implementation +class rvopcodes_decoder: + ''' + This class implements the decoder plugin + ''' + @plugins.decoderHookImpl + def setup(self, arch): + self.arch = arch + + @plugins.decoderHookImpl + def decoder(self, instrObj_temp): + pass + + +if __name__ == '__main__': + cli() \ No newline at end of file From 61bc3e6168fe69af76d08fdb06132a4d60a748b3 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Sat, 5 Mar 2022 15:02:08 +0530 Subject: [PATCH 02/41] CLI usage --- riscv_isac/plugins/rv_opcodes_decoder.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/riscv_isac/plugins/rv_opcodes_decoder.py b/riscv_isac/plugins/rv_opcodes_decoder.py index 7f572d3..f1192fb 100644 --- a/riscv_isac/plugins/rv_opcodes_decoder.py +++ b/riscv_isac/plugins/rv_opcodes_decoder.py @@ -46,4 +46,8 @@ def decoder(self, instrObj_temp): if __name__ == '__main__': + + # Run python3 rv_opcodes_decoder.py --build clone + # to clone the repository + cli() \ No newline at end of file From 399120f891c5a76819bb8f09429179153219d017 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Sat, 5 Mar 2022 15:07:53 +0530 Subject: [PATCH 03/41] CLI: clone and get path @pawks --- riscv_isac/plugins/rv_opcodes_decoder.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/riscv_isac/plugins/rv_opcodes_decoder.py b/riscv_isac/plugins/rv_opcodes_decoder.py index f1192fb..104c62a 100644 --- a/riscv_isac/plugins/rv_opcodes_decoder.py +++ b/riscv_isac/plugins/rv_opcodes_decoder.py @@ -22,7 +22,6 @@ def cli(setup): def clone(url): Repo.clone_from(url, './riscv-opcodes/') path_to_opcodes = os.getcwd() + '/riscv-opcodes/' - print(path_to_opcodes) # Temporary CLI command to clean the cloned repo @cli.command(help = 'Clean cloned repo') @@ -49,5 +48,5 @@ def decoder(self, instrObj_temp): # Run python3 rv_opcodes_decoder.py --build clone # to clone the repository - + cli() \ No newline at end of file From 7e0ff3df284793bb6f95134d432039fe2d80fc74 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Thu, 10 Mar 2022 11:50:25 +0530 Subject: [PATCH 04/41] Including CLI commands for riscv-opcodes --- riscv_isac/main.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/riscv_isac/main.py b/riscv_isac/main.py index 74bc205..2841329 100644 --- a/riscv_isac/main.py +++ b/riscv_isac/main.py @@ -1,7 +1,9 @@ # See LICENSE.incore for details """Console script for riscv_isac.""" +import os import click +from git import Repo from riscv_isac.isac import isac from riscv_isac.__init__ import __version__ @@ -171,3 +173,18 @@ def normalize(cgf_file,output_file,xlen): utils.dump_yaml(expand_cgf(cgf_file,int(xlen)),outfile) + +@cli.command(help = 'Clone from the riscv-opcodes repo') +@click.option('--url', + type = str, + default='https://github.com/incoresemi/riscv-opcodes', + required=False, + help='URL to the riscv-opcodes repo') +# Clone repo +def setup(url): + ''' + Clone from a specified url + Input argument: + url: (string) url to the riscv-opcodes repo + ''' + Repo.clone_from(url, './plugins/riscv-opcodes/') \ No newline at end of file From 09f615d68badd5b6d3a0c17a9711f367131f2683 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Thu, 10 Mar 2022 12:27:22 +0530 Subject: [PATCH 05/41] __init__.py generation for riscv-opcodes --- riscv_isac/main.py | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/riscv_isac/main.py b/riscv_isac/main.py index 2841329..11d2edc 100644 --- a/riscv_isac/main.py +++ b/riscv_isac/main.py @@ -180,11 +180,22 @@ def normalize(cgf_file,output_file,xlen): default='https://github.com/incoresemi/riscv-opcodes', required=False, help='URL to the riscv-opcodes repo') +@click.option('--clean', + is_flag=True, + help='Clean cloned repo' + ) # Clone repo -def setup(url): +def setup(url, clean): ''' Clone from a specified url Input argument: url: (string) url to the riscv-opcodes repo ''' - Repo.clone_from(url, './plugins/riscv-opcodes/') \ No newline at end of file + path = os.getcwd() + '/plugins/riscv_opcodes/' + if(clean): + os.system('rm -rf ' + path) + else: + Repo.clone_from(url, './plugins/riscv_opcodes/') + f = open(path + '__init__.py', 'w+') + f.write('#Top Level package for riscv-opcodes') + f.close() \ No newline at end of file From 7d675b9419165660938900255b0e375864c75ba6 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Thu, 17 Mar 2022 16:10:28 +0530 Subject: [PATCH 06/41] Constants for rvopcodes --- riscv_isac/plugins/constants.py | 591 ++++++++++++++++++++++++++++++++ 1 file changed, 591 insertions(+) create mode 100644 riscv_isac/plugins/constants.py diff --git a/riscv_isac/plugins/constants.py b/riscv_isac/plugins/constants.py new file mode 100644 index 0000000..e23f3d4 --- /dev/null +++ b/riscv_isac/plugins/constants.py @@ -0,0 +1,591 @@ +import re + + +isa_regex = \ +re.compile("^RV(32|64|128)[IE]+[ABCDEFGHJKLMNPQSTUVX]*(Zicsr|Zifencei|Zihintpause|Zam|Ztso|Zkne|Zknd|Zknh|Zkse|Zksh|Zkg|Zkb|Zkr|Zks|Zkn|Zba|Zbc|Zbb|Zbp|Zbr|Zbm|Zbs|Zbe|Zbf|Zbt|Zmmul|Zbpbo){,1}(_Zicsr){,1}(_Zifencei){,1}(_Zihintpause){,1}(_Zmmul){,1}(_Zam){,1}(_Zba){,1}(_Zbb){,1}(_Zbc){,1}(_Zbe){,1}(_Zbf){,1}(_Zbm){,1}(_Zbp){,1}(_Zbpbo){,1}(_Zbr){,1}(_Zbs){,1}(_Zbt){,1}(_Zkb){,1}(_Zkg){,1}(_Zkr){,1}(_Zks){,1}(_Zkn){,1}(_Zknd){,1}(_Zkne){,1}(_Zknh){,1}(_Zkse){,1}(_Zksh){,1}(_Ztso){,1}$") + +# regex to find ..= patterns in instruction +fixed_ranges = re.compile( + '\s*(?P\d+.?)\.\.(?P\d+.?)\s*=\s*(?P\d[\w]*)[\s$]*', re.M) + +# regex to find = patterns in instructions +#single_fixed = re.compile('\s+(?P\d+)=(?P[\w\d]*)[\s$]*', re.M) +single_fixed = re.compile('(?:^|[\s])(?P\d+)=(?P[\w]*)((?=\s|$))', re.M) + +# regex to find the overloading condition variable +var_regex = re.compile('(?P[a-zA-Z][\w\d]*)\s*=\s*.*?[\s$]*', re.M) + +# regex for pseudo op instructions returns the dependent filename, dependent +# instruction, the pseudo op name and the encoding string +pseudo_regex = re.compile( + '^\$pseudo_op\s+(?Prv[\d]*_[\w].*)::\s*(?P.*?)\s+(?P.*?)\s+(?P.*)$' +, re.M) + + +# +# Trap cause codes +causes = [ + (0x00, 'misaligned fetch'), + (0x01, 'fetch access'), + (0x02, 'illegal instruction'), + (0x03, 'breakpoint'), + (0x04, 'misaligned load'), + (0x05, 'load access'), + (0x06, 'misaligned store'), + (0x07, 'store access'), + (0x08, 'user_ecall'), + (0x09, 'supervisor_ecall'), + (0x0A, 'virtual_supervisor_ecall'), + (0x0B, 'machine_ecall'), + (0x0C, 'fetch page fault'), + (0x0D, 'load page fault'), + (0x0F, 'store page fault'), + (0x14, 'fetch guest page fault'), + (0x15, 'load guest page fault'), + (0x16, 'virtual instruction'), + (0x17, 'store guest page fault'), +] + +csrs = [ + # Standard User R/W + (0x001, 'fflags'), + (0x002, 'frm'), + (0x003, 'fcsr'), + (0x008, 'vstart'), + (0x009, 'vxsat'), + (0x00A, 'vxrm'), + (0x00F, 'vcsr'), + (0x015, 'seed'), # Zkr + + # Standard User RO + (0xC00, 'cycle'), + (0xC01, 'time'), + (0xC02, 'instret'), + (0xC03, 'hpmcounter3'), + (0xC04, 'hpmcounter4'), + (0xC05, 'hpmcounter5'), + (0xC06, 'hpmcounter6'), + (0xC07, 'hpmcounter7'), + (0xC08, 'hpmcounter8'), + (0xC09, 'hpmcounter9'), + (0xC0A, 'hpmcounter10'), + (0xC0B, 'hpmcounter11'), + (0xC0C, 'hpmcounter12'), + (0xC0D, 'hpmcounter13'), + (0xC0E, 'hpmcounter14'), + (0xC0F, 'hpmcounter15'), + (0xC10, 'hpmcounter16'), + (0xC11, 'hpmcounter17'), + (0xC12, 'hpmcounter18'), + (0xC13, 'hpmcounter19'), + (0xC14, 'hpmcounter20'), + (0xC15, 'hpmcounter21'), + (0xC16, 'hpmcounter22'), + (0xC17, 'hpmcounter23'), + (0xC18, 'hpmcounter24'), + (0xC19, 'hpmcounter25'), + (0xC1A, 'hpmcounter26'), + (0xC1B, 'hpmcounter27'), + (0xC1C, 'hpmcounter28'), + (0xC1D, 'hpmcounter29'), + (0xC1E, 'hpmcounter30'), + (0xC1F, 'hpmcounter31'), + (0xC20, 'vl'), + (0xC21, 'vtype'), + (0xC22, 'vlenb'), + + # Standard Supervisor R/W + (0x100, 'sstatus'), + (0x102, 'sedeleg'), + (0x103, 'sideleg'), + (0x104, 'sie'), + (0x105, 'stvec'), + (0x106, 'scounteren'), + (0x10A, 'senvcfg'), + (0x140, 'sscratch'), + (0x141, 'sepc'), + (0x142, 'scause'), + (0x143, 'stval'), + (0x144, 'sip'), + (0x180, 'satp'), + (0x5A8, 'scontext'), + + # Standard Hypervisor R/w + (0x200, 'vsstatus'), + (0x204, 'vsie'), + (0x205, 'vstvec'), + (0x240, 'vsscratch'), + (0x241, 'vsepc'), + (0x242, 'vscause'), + (0x243, 'vstval'), + (0x244, 'vsip'), + (0x280, 'vsatp'), + (0x600, 'hstatus'), + (0x602, 'hedeleg'), + (0x603, 'hideleg'), + (0x604, 'hie'), + (0x605, 'htimedelta'), + (0x606, 'hcounteren'), + (0x607, 'hgeie'), + (0x60A, 'henvcfg'), + (0x643, 'htval'), + (0x644, 'hip'), + (0x645, 'hvip'), + (0x64A, 'htinst'), + (0x680, 'hgatp'), + (0x6A8, 'hcontext'), + (0xE12, 'hgeip'), + + # Tentative CSR assignment for CLIC + (0x007, 'utvt'), + (0x045, 'unxti'), + (0x046, 'uintstatus'), + (0x048, 'uscratchcsw'), + (0x049, 'uscratchcswl'), + (0x107, 'stvt'), + (0x145, 'snxti'), + (0x146, 'sintstatus'), + (0x148, 'sscratchcsw'), + (0x149, 'sscratchcswl'), + (0x307, 'mtvt'), + (0x345, 'mnxti'), + (0x346, 'mintstatus'), + (0x348, 'mscratchcsw'), + (0x349, 'mscratchcswl'), + + # Standard Machine R/W + (0x300, 'mstatus'), + (0x301, 'misa'), + (0x302, 'medeleg'), + (0x303, 'mideleg'), + (0x304, 'mie'), + (0x305, 'mtvec'), + (0x306, 'mcounteren'), + (0x30a, 'menvcfg'), + (0x320, 'mcountinhibit'), + (0x340, 'mscratch'), + (0x341, 'mepc'), + (0x342, 'mcause'), + (0x343, 'mtval'), + (0x344, 'mip'), + (0x34a, 'mtinst'), + (0x34b, 'mtval2'), + (0x3a0, 'pmpcfg0'), + (0x3a1, 'pmpcfg1'), + (0x3a2, 'pmpcfg2'), + (0x3a3, 'pmpcfg3'), + (0x3a4, 'pmpcfg4'), + (0x3a5, 'pmpcfg5'), + (0x3a6, 'pmpcfg6'), + (0x3a7, 'pmpcfg7'), + (0x3a8, 'pmpcfg8'), + (0x3a9, 'pmpcfg9'), + (0x3aa, 'pmpcfg10'), + (0x3ab, 'pmpcfg11'), + (0x3ac, 'pmpcfg12'), + (0x3ad, 'pmpcfg13'), + (0x3ae, 'pmpcfg14'), + (0x3af, 'pmpcfg15'), + (0x3b0, 'pmpaddr0'), + (0x3b1, 'pmpaddr1'), + (0x3b2, 'pmpaddr2'), + (0x3b3, 'pmpaddr3'), + (0x3b4, 'pmpaddr4'), + (0x3b5, 'pmpaddr5'), + (0x3b6, 'pmpaddr6'), + (0x3b7, 'pmpaddr7'), + (0x3b8, 'pmpaddr8'), + (0x3b9, 'pmpaddr9'), + (0x3ba, 'pmpaddr10'), + (0x3bb, 'pmpaddr11'), + (0x3bc, 'pmpaddr12'), + (0x3bd, 'pmpaddr13'), + (0x3be, 'pmpaddr14'), + (0x3bf, 'pmpaddr15'), + (0x3c0, 'pmpaddr16'), + (0x3c1, 'pmpaddr17'), + (0x3c2, 'pmpaddr18'), + (0x3c3, 'pmpaddr19'), + (0x3c4, 'pmpaddr20'), + (0x3c5, 'pmpaddr21'), + (0x3c6, 'pmpaddr22'), + (0x3c7, 'pmpaddr23'), + (0x3c8, 'pmpaddr24'), + (0x3c9, 'pmpaddr25'), + (0x3ca, 'pmpaddr26'), + (0x3cb, 'pmpaddr27'), + (0x3cc, 'pmpaddr28'), + (0x3cd, 'pmpaddr29'), + (0x3ce, 'pmpaddr30'), + (0x3cf, 'pmpaddr31'), + (0x3d0, 'pmpaddr32'), + (0x3d1, 'pmpaddr33'), + (0x3d2, 'pmpaddr34'), + (0x3d3, 'pmpaddr35'), + (0x3d4, 'pmpaddr36'), + (0x3d5, 'pmpaddr37'), + (0x3d6, 'pmpaddr38'), + (0x3d7, 'pmpaddr39'), + (0x3d8, 'pmpaddr40'), + (0x3d9, 'pmpaddr41'), + (0x3da, 'pmpaddr42'), + (0x3db, 'pmpaddr43'), + (0x3dc, 'pmpaddr44'), + (0x3dd, 'pmpaddr45'), + (0x3de, 'pmpaddr46'), + (0x3df, 'pmpaddr47'), + (0x3e0, 'pmpaddr48'), + (0x3e1, 'pmpaddr49'), + (0x3e2, 'pmpaddr50'), + (0x3e3, 'pmpaddr51'), + (0x3e4, 'pmpaddr52'), + (0x3e5, 'pmpaddr53'), + (0x3e6, 'pmpaddr54'), + (0x3e7, 'pmpaddr55'), + (0x3e8, 'pmpaddr56'), + (0x3e9, 'pmpaddr57'), + (0x3ea, 'pmpaddr58'), + (0x3eb, 'pmpaddr59'), + (0x3ec, 'pmpaddr60'), + (0x3ed, 'pmpaddr61'), + (0x3ee, 'pmpaddr62'), + (0x3ef, 'pmpaddr63'), + (0x747, 'mseccfg'), + (0x7a0, 'tselect'), + (0x7a1, 'tdata1'), + (0x7a2, 'tdata2'), + (0x7a3, 'tdata3'), + (0x7a4, 'tinfo'), + (0x7a5, 'tcontrol'), + (0x7a8, 'mcontext'), + (0x7aa, 'mscontext'), + (0x7b0, 'dcsr'), + (0x7b1, 'dpc'), + (0x7b2, 'dscratch0'), + (0x7b3, 'dscratch1'), + (0xB00, 'mcycle'), + (0xB02, 'minstret'), + (0xB03, 'mhpmcounter3'), + (0xB04, 'mhpmcounter4'), + (0xB05, 'mhpmcounter5'), + (0xB06, 'mhpmcounter6'), + (0xB07, 'mhpmcounter7'), + (0xB08, 'mhpmcounter8'), + (0xB09, 'mhpmcounter9'), + (0xB0A, 'mhpmcounter10'), + (0xB0B, 'mhpmcounter11'), + (0xB0C, 'mhpmcounter12'), + (0xB0D, 'mhpmcounter13'), + (0xB0E, 'mhpmcounter14'), + (0xB0F, 'mhpmcounter15'), + (0xB10, 'mhpmcounter16'), + (0xB11, 'mhpmcounter17'), + (0xB12, 'mhpmcounter18'), + (0xB13, 'mhpmcounter19'), + (0xB14, 'mhpmcounter20'), + (0xB15, 'mhpmcounter21'), + (0xB16, 'mhpmcounter22'), + (0xB17, 'mhpmcounter23'), + (0xB18, 'mhpmcounter24'), + (0xB19, 'mhpmcounter25'), + (0xB1A, 'mhpmcounter26'), + (0xB1B, 'mhpmcounter27'), + (0xB1C, 'mhpmcounter28'), + (0xB1D, 'mhpmcounter29'), + (0xB1E, 'mhpmcounter30'), + (0xB1F, 'mhpmcounter31'), + (0x323, 'mhpmevent3'), + (0x324, 'mhpmevent4'), + (0x325, 'mhpmevent5'), + (0x326, 'mhpmevent6'), + (0x327, 'mhpmevent7'), + (0x328, 'mhpmevent8'), + (0x329, 'mhpmevent9'), + (0x32A, 'mhpmevent10'), + (0x32B, 'mhpmevent11'), + (0x32C, 'mhpmevent12'), + (0x32D, 'mhpmevent13'), + (0x32E, 'mhpmevent14'), + (0x32F, 'mhpmevent15'), + (0x330, 'mhpmevent16'), + (0x331, 'mhpmevent17'), + (0x332, 'mhpmevent18'), + (0x333, 'mhpmevent19'), + (0x334, 'mhpmevent20'), + (0x335, 'mhpmevent21'), + (0x336, 'mhpmevent22'), + (0x337, 'mhpmevent23'), + (0x338, 'mhpmevent24'), + (0x339, 'mhpmevent25'), + (0x33A, 'mhpmevent26'), + (0x33B, 'mhpmevent27'), + (0x33C, 'mhpmevent28'), + (0x33D, 'mhpmevent29'), + (0x33E, 'mhpmevent30'), + (0x33F, 'mhpmevent31'), + + # Standard Machine RO + (0xF11, 'mvendorid'), + (0xF12, 'marchid'), + (0xF13, 'mimpid'), + (0xF14, 'mhartid'), + (0xF15, 'mconfigptr'), +] + +csrs32 = [ + # Standard Hypervisor R/w + (0x615, 'htimedeltah'), + (0x61A, 'henvcfgh'), + + # Standard User RO + (0xC80, 'cycleh'), + (0xC81, 'timeh'), + (0xC82, 'instreth'), + (0xC83, 'hpmcounter3h'), + (0xC84, 'hpmcounter4h'), + (0xC85, 'hpmcounter5h'), + (0xC86, 'hpmcounter6h'), + (0xC87, 'hpmcounter7h'), + (0xC88, 'hpmcounter8h'), + (0xC89, 'hpmcounter9h'), + (0xC8A, 'hpmcounter10h'), + (0xC8B, 'hpmcounter11h'), + (0xC8C, 'hpmcounter12h'), + (0xC8D, 'hpmcounter13h'), + (0xC8E, 'hpmcounter14h'), + (0xC8F, 'hpmcounter15h'), + (0xC90, 'hpmcounter16h'), + (0xC91, 'hpmcounter17h'), + (0xC92, 'hpmcounter18h'), + (0xC93, 'hpmcounter19h'), + (0xC94, 'hpmcounter20h'), + (0xC95, 'hpmcounter21h'), + (0xC96, 'hpmcounter22h'), + (0xC97, 'hpmcounter23h'), + (0xC98, 'hpmcounter24h'), + (0xC99, 'hpmcounter25h'), + (0xC9A, 'hpmcounter26h'), + (0xC9B, 'hpmcounter27h'), + (0xC9C, 'hpmcounter28h'), + (0xC9D, 'hpmcounter29h'), + (0xC9E, 'hpmcounter30h'), + (0xC9F, 'hpmcounter31h'), + + # Standard Machine RW + (0x310, 'mstatush'), + (0x31A, 'menvcfgh'), + (0x757, 'mseccfgh'), + (0xB80, 'mcycleh'), + (0xB82, 'minstreth'), + (0xB83, 'mhpmcounter3h'), + (0xB84, 'mhpmcounter4h'), + (0xB85, 'mhpmcounter5h'), + (0xB86, 'mhpmcounter6h'), + (0xB87, 'mhpmcounter7h'), + (0xB88, 'mhpmcounter8h'), + (0xB89, 'mhpmcounter9h'), + (0xB8A, 'mhpmcounter10h'), + (0xB8B, 'mhpmcounter11h'), + (0xB8C, 'mhpmcounter12h'), + (0xB8D, 'mhpmcounter13h'), + (0xB8E, 'mhpmcounter14h'), + (0xB8F, 'mhpmcounter15h'), + (0xB90, 'mhpmcounter16h'), + (0xB91, 'mhpmcounter17h'), + (0xB92, 'mhpmcounter18h'), + (0xB93, 'mhpmcounter19h'), + (0xB94, 'mhpmcounter20h'), + (0xB95, 'mhpmcounter21h'), + (0xB96, 'mhpmcounter22h'), + (0xB97, 'mhpmcounter23h'), + (0xB98, 'mhpmcounter24h'), + (0xB99, 'mhpmcounter25h'), + (0xB9A, 'mhpmcounter26h'), + (0xB9B, 'mhpmcounter27h'), + (0xB9C, 'mhpmcounter28h'), + (0xB9D, 'mhpmcounter29h'), + (0xB9E, 'mhpmcounter30h'), + (0xB9F, 'mhpmcounter31h'), +] + +# look up table of position of various arguments that are used by the +# instructions in the encoding files. +arg_lut = {} +arg_lut['rd'] = (11, 7) +arg_lut['rt'] = (19, 15) # source+dest register address. Overlaps rs1. +arg_lut['rs1'] = (19, 15) +arg_lut['rs2'] = (24, 20) +arg_lut['rs3'] = (31, 27) +arg_lut['aqrl'] = (26, 25) +arg_lut['aq'] = (26, 26) +arg_lut['rl'] = (25, 25) +arg_lut['fm'] = (31, 28) +arg_lut['pred'] = (27, 24) +arg_lut['succ'] = (23, 20) +arg_lut['rm'] = (14, 12) +arg_lut['funct3'] = (14, 12) +arg_lut['funct2'] = (26, 25) + +arg_lut['funct12'] = (31, 20) + +arg_lut['imm20'] = (31, 12) +arg_lut['jimm20'] = (31, 12) +arg_lut['imm12'] = (31, 20) +arg_lut['imm12hi'] = (31, 25) +arg_lut['bimm12hi'] = (31, 25) +arg_lut['imm12lo'] = (11, 7) +arg_lut['bimm12lo'] = (11, 7) +arg_lut['zimm'] = (19, 15) +arg_lut['shamt'] = (25, 20) +arg_lut['shamtw'] = (24, 20) +arg_lut['shamtw4'] = (23, 20) +arg_lut['bs'] = (31, 30) # byte select for RV32K AES +arg_lut['rnum'] = (23, 20) # round constant for RV64 AES +arg_lut['rc'] = (29, 25) +arg_lut['imm2'] = (21, 20) +arg_lut['imm3'] = (22, 20) +arg_lut['imm4'] = (23, 20) +arg_lut['imm5'] = (24, 20) +arg_lut['imm6'] = (25, 20) +arg_lut['zimm'] = (19, 15) +arg_lut['opcode'] = (6,0) +arg_lut['funct7'] = (31,25) + +# for vectors +arg_lut['vd'] = (11, 7) +arg_lut['vs3'] = (11, 7) +arg_lut['vs1'] = (19, 15) +arg_lut['vs2'] = (24, 20) +arg_lut['vm'] = (25, 25) +arg_lut['wd'] = (26, 26) +arg_lut['amoop'] = (31, 27) +arg_lut['nf'] = (31, 29) +arg_lut['simm5'] = (19, 15) +arg_lut['zimm10'] = (29, 20) +arg_lut['zimm11'] = (30, 20) + + +#compressed immediates and fields +arg_lut['c_nzuimm10'] = (12,5) +arg_lut['c_uimm7lo'] = (6,5) +arg_lut['c_uimm7hi'] = (12,10) +arg_lut['c_uimm8lo'] = (6,5) +arg_lut['c_uimm8hi'] = (12,10) +arg_lut['c_uimm9lo'] = (6,5) +arg_lut['c_uimm9hi'] = (12,10) +arg_lut['c_nzimm6lo'] = (6,2) +arg_lut['c_nzimm6hi'] = (12,12) +arg_lut['c_imm6lo'] = (6,2) +arg_lut['c_imm6hi'] = (12,12) +arg_lut['c_nzimm10hi'] = (12,12) +arg_lut['c_nzimm10lo'] = (6,2) +arg_lut['c_nzimm18hi'] = (12,12) +arg_lut['c_nzimm18lo'] = (6,2) +arg_lut['c_imm12'] = (12,2) +arg_lut['c_bimm9lo'] = (6,2) +arg_lut['c_bimm9hi'] = (12,10) +arg_lut['c_nzuimm5'] = (6,2) +arg_lut['c_nzuimm6lo'] = (6,2) +arg_lut['c_nzuimm6hi'] = (12, 12) +arg_lut['c_uimm8splo'] = (6,2) +arg_lut['c_uimm8sphi'] = (12, 12) +arg_lut['c_uimm8sp_s'] = (12,7) +arg_lut['c_uimm10splo'] = (6,2) +arg_lut['c_uimm10sphi'] = (12, 12) +arg_lut['c_uimm9splo'] = (6,2) +arg_lut['c_uimm9sphi'] = (12, 12) +arg_lut['c_uimm10sp_s'] = (12,7) +arg_lut['c_uimm9sp_s'] = (12,7) + +arg_lut['rs1_p'] = (9,7) +arg_lut['rs2_p'] = (4,2) +arg_lut['rd_p'] = (4,2) +arg_lut['rd_rs1_n0'] = (11,7) +arg_lut['rd_rs1_p'] = (9,7) +arg_lut['rd_rs1'] = (11,7) +arg_lut['rd_n2'] = (11,7) +arg_lut['rd_n0'] = (11,7) +arg_lut['rs1_n0'] = (11,7) +arg_lut['c_rs2_n0'] = (6,2) +arg_lut['c_rs1_n0'] = (11,7) +arg_lut['c_rs2'] = (6,2) + +# dictionary containing the mapping of the argument to the what the fields in +# the latex table should be +latex_mapping = {} +latex_mapping['imm12'] = 'imm[11:0]' +latex_mapping['rs1'] = 'rs1' +latex_mapping['rs2'] = 'rs2' +latex_mapping['rd'] = 'rd' +latex_mapping['imm20'] = 'imm[31:12]' +latex_mapping['bimm12hi'] = 'imm[12$\\vert$10:5]' +latex_mapping['bimm12lo'] = 'imm[4:1$\\vert$11]' +latex_mapping['imm12hi'] = 'imm[11:5]' +latex_mapping['imm12lo'] = 'imm[4:0]' +latex_mapping['jimm20'] = 'imm[20$\\vert$10:1$\\vert$11$\\vert$19:12]' +latex_mapping['zimm'] = 'uimm' +latex_mapping['shamtw'] = 'shamt' +latex_mapping['rd_p'] = "rd\\,$'$" +latex_mapping['rs1_p'] = "rs1\\,$'$" +latex_mapping['rs2_p'] = "rs2\\,$'$" +latex_mapping['rd_rs1_n0'] = 'rd/rs$\\neq$0' +latex_mapping['rd_rs1_p'] = "rs1\\,$'$/rs2\\,$'$" +latex_mapping['c_rs2'] = 'rs2' +latex_mapping['c_rs2_n0'] = 'rs2$\\neq$0' +latex_mapping['rd_n0'] = 'rd$\\neq$0' +latex_mapping['rs1_n0'] = 'rs1$\\neq$0' +latex_mapping['c_rs1_n0'] = 'rs1$\\neq$0' +latex_mapping['rd_rs1'] = 'rd/rs1' +latex_mapping['c_nzuimm10'] = "nzuimm[5:4$\\vert$9:6$\\vert$2$\\vert$3]" +latex_mapping['c_uimm7lo'] = 'uimm[2$\\vert$6]' +latex_mapping['c_uimm7hi'] = 'uimm[5:3]' +latex_mapping['c_uimm8lo'] = 'uimm[7:6]' +latex_mapping['c_uimm8hi'] = 'uimm[5:3]' +latex_mapping['c_uimm9lo'] = 'uimm[7:6]' +latex_mapping['c_uimm9hi'] = 'uimm[5:4$\\vert$8]' +latex_mapping['c_nzimm6lo'] = 'nzimm[4:0]' +latex_mapping['c_nzimm6hi'] = 'nzimm[5]' +latex_mapping['c_imm6lo'] = 'imm[4:0]' +latex_mapping['c_imm6hi'] = 'imm[5]' +latex_mapping['c_nzimm10hi'] = 'nzimm[9]' +latex_mapping['c_nzimm10lo'] = 'nzimm[4$\\vert$6$\\vert$8:7$\\vert$5]' +latex_mapping['c_nzimm18hi'] = 'nzimm[17]' +latex_mapping['c_nzimm18lo'] = 'nzimm[16:12]' +latex_mapping['c_imm12'] = 'imm[11$\\vert$4$\\vert$9:8$\\vert$10$\\vert$6$\\vert$7$\\vert$3:1$\\vert$5]' +latex_mapping['c_bimm9lo'] = 'imm[7:6$\\vert$2:1$\\vert$5]' +latex_mapping['c_bimm9hi'] = 'imm[8$\\vert$4:3]' +latex_mapping['c_nzuimm5'] = 'nzuimm[4:0]' +latex_mapping['c_nzuimm6lo'] = 'nzuimm[4:0]' +latex_mapping['c_nzuimm6hi'] = 'nzuimm[5]' +latex_mapping['c_uimm8splo'] = 'uimm[4:2$\\vert$7:6]' +latex_mapping['c_uimm8sphi'] = 'uimm[5]' +latex_mapping['c_uimm8sp_s'] = 'uimm[5:2$\\vert$7:6]' +latex_mapping['c_uimm10splo'] = 'uimm[4$\\vert$9:6]' +latex_mapping['c_uimm10sphi'] = 'uimm[5]' +latex_mapping['c_uimm9splo'] = 'uimm[4:3$\\vert$8:6]' +latex_mapping['c_uimm9sphi'] = 'uimm[5]' +latex_mapping['c_uimm10sp_s'] = 'uimm[5:4$\\vert$9:6]' +latex_mapping['c_uimm9sp_s'] = 'uimm[5:3$\\vert$8:6]' + +# created a dummy instruction-dictionary like dictionary for all the instruction +# types so that the same logic can be used to create their tables +latex_inst_type = {} +latex_inst_type['R-type'] = {} +latex_inst_type['R-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ + 'rs1', 'rs2', 'funct7'] +latex_inst_type['I-type'] = {} +latex_inst_type['I-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ + 'rs1', 'imm12'] +latex_inst_type['S-type'] = {} +latex_inst_type['S-type']['variable_fields'] = ['opcode', 'imm12lo', 'funct3', \ + 'rs1', 'rs2', 'imm12hi'] +latex_inst_type['B-type'] = {} +latex_inst_type['B-type']['variable_fields'] = ['opcode', 'bimm12lo', 'funct3', \ + 'rs1', 'rs2', 'bimm12hi'] +latex_inst_type['U-type'] = {} +latex_inst_type['U-type']['variable_fields'] = ['opcode', 'rd', 'imm20'] +latex_inst_type['J-type'] = {} +latex_inst_type['J-type']['variable_fields'] = ['opcode', 'rd', 'jimm20'] +latex_inst_type['R4-type'] = {} +latex_inst_type['R4-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ + 'rs1', 'rs2', 'funct2', 'rs3'] From 2f327e944313cfcdde689e752e2c64d12ff12a96 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Thu, 17 Mar 2022 16:11:08 +0530 Subject: [PATCH 07/41] Hierarchical Decoder @pawks --- riscv_isac/plugins/rv_opcodes_decoder.py | 310 +++++++++++++++++++---- 1 file changed, 263 insertions(+), 47 deletions(-) diff --git a/riscv_isac/plugins/rv_opcodes_decoder.py b/riscv_isac/plugins/rv_opcodes_decoder.py index 104c62a..8f6bb58 100644 --- a/riscv_isac/plugins/rv_opcodes_decoder.py +++ b/riscv_isac/plugins/rv_opcodes_decoder.py @@ -1,52 +1,268 @@ -import os -import click -from git import Repo - -import riscv_isac.plugins as plugins - -# Path to riscv-opcodes -path_to_opcodes = '' - -@click.group() -@click.option('--setup', - is_flag=True, - help='Setup decoder from riscv-opcodes') -def cli(setup): - pass - -@cli.command(help = 'URL to the riscv-opcodes github repo') -@click.option('--url', - type = str, - default='https://github.com/incoresemi/riscv-opcodes', - required=False) -def clone(url): - Repo.clone_from(url, './riscv-opcodes/') - path_to_opcodes = os.getcwd() + '/riscv-opcodes/' - -# Temporary CLI command to clean the cloned repo -@cli.command(help = 'Clean cloned repo') -@click.option('--clean', - default='./riscv-opcodes') -def clean(clean): - os.system('rm -r -f ' + clean) - -# Disassembler implementation -class rvopcodes_decoder: - ''' - This class implements the decoder plugin - ''' - @plugins.decoderHookImpl - def setup(self, arch): - self.arch = arch - - @plugins.decoderHookImpl - def decoder(self, instrObj_temp): - pass +import glob +from operator import itemgetter +from collections import defaultdict +import pprint + +from constants import * +from riscv_isac.InstructionObject import instructionObject + +from riscv_isac.plugins.internaldecoder import disassembler + +#export PYTHONPATH=/home/edwin/myrepos/riscv-isac/ + +# Closure to get argument value +# TODO Handle special immediates +def get_arg_val(arg: str): + (msb, lsb) = arg_lut[arg] + mask = int(''.join('1' * (msb - lsb + 1)), 2) << lsb + def mcode_in(mcode: int): + val = (mask & mcode) >> lsb + return val + return mcode_in + +# Standard functs +def func2(mcode: int): + (msb, lsb) = arg_lut['funct2'] + mask = int(''.join('1' * (msb - lsb + 1)), 2) << lsb + val = (mask & mcode) >> lsb + + return val + +def func3(mcode: int): + (msb, lsb) = arg_lut['funct3'] + mask = int(''.join('1' * (msb - lsb + 1)), 2) << lsb + val = (mask & mcode) >> lsb + + return val + +def func7(mcode: int): + (msb, lsb) = arg_lut['funct7'] + mask = int(''.join('1' * (msb - lsb + 1)), 2) << lsb + val = (mask & mcode) >> lsb + + return val + +# For Non standard functs +def get_funct(pos_tuple: tuple, mcode: int): + msb = pos_tuple[0] + lsb = pos_tuple[1] + mask = int(''.join('1' * (msb - lsb + 1)), 2) << lsb + val = (mask & mcode) >> lsb + + return val + +# For rd check: +def rd_check(mcode: int): + mask = 0x00000f80 + val = (mask & mcode) >> 7 + return val + +class rvOpcodesDecoder: + + FIRST_TWO = 0x00000003 + OPCODE_MASK = 0x0000007f + + def __init__(self, file_filter: str): + + # Create nested dictionary + nested_dict = lambda: defaultdict(nested_dict) + rvOpcodesDecoder.INS_DICT = nested_dict() + rvOpcodesDecoder.create_inst_dict(file_filter) + + def process_enc_line(line: str): + + functs = [] + args = [] + + # get the name of instruction by splitting based on the first space + [name, remaining] = line.split(' ', 1) + + # replace dots with underscores as dot doesn't work with C/Sverilog, etc + name = name.replace('.', '_') + + # remove leading whitespaces + remaining = remaining.lstrip() + + # extract bit pattern assignments of the form hi..lo=val. fixed_ranges is a + # regex expression present in constants.py. The extracted patterns are + # captured as a list in args where each entry is a tuple (msb, lsb, value) + opcode = '' + id = 0 + opcode_parsed = fixed_ranges.findall(remaining) + opcode_functs = [] + for func in opcode_parsed: + opcode_functs.append([int(a, 0) for a in func]) + + # Sort in ascending order of lsb + opcode_functs = sorted(opcode_functs, key=itemgetter(1)) + for (msb, lsb, value) in opcode_functs: + flen = msb - lsb + 1 + value = f"{value:0{flen}b}" + if lsb == id: + opcode = value + opcode + id = id + flen + else: + # Standard functs + if flen == 2: + if lsb == arg_lut['funct2'][1]: + func_len = func2 + else: + func_len = (msb, lsb) + elif flen == 3: + if lsb == arg_lut['funct3'][1]: + func_len = func3 + else: + func_len = (msb, lsb) + elif flen == 7: + if lsb == arg_lut['funct7'][1]: + func_len = func7 + else: + func_len = (msb, lsb) + + # Non standard functs + else: + func_len = (msb, lsb) + functs.append((func_len, int(value, 2))) + + # parse through the args + args_list = fixed_ranges.sub(' ', remaining) + args_list = single_fixed.sub(' ', args_list).split() + for arg in args_list: + if arg == 'rd': + functs.insert(0, (rd_check, True)) + args.append(get_arg_val(arg)) + + if len(opcode) > 7: + functs.insert(0, (rd_check, False)) + + opcode = int(opcode, 2) + first_two = opcode & rvOpcodesDecoder.FIRST_TWO + if first_two == 3: + is_compressed = False + else: + is_compressed = True + + # do the same as above but for = pattern. single_fixed is a regex + # expression present in constants.py + for (lsb, value, drop) in single_fixed.findall(remaining): + lsb = int(lsb, 0) + value = int(value, 0) + functs.append(((lsb, lsb), value)) + + # update the fields of the instruction as a dict and return back along with + # the name of the instruction + return (is_compressed, opcode, functs, (name, args)) + + def create_inst_dict(file_filter): + opcodes_dir = f'./riscv_opcodes/' + + # file_names contains all files to be parsed in the riscv-opcodes directory + file_names = glob.glob(f'{opcodes_dir}rv{file_filter}') + + # first pass if for standard/original instructions + for f in file_names: + with open(f) as fp: + lines = (line.rstrip() + for line in fp) # All lines including the blank ones + lines = list(line for line in lines if line) # Non-blank lines + lines = list( + line for line in lines + if not line.startswith("#")) # remove comment lines + + # go through each line of the file + for line in lines: + # if the an instruction needs to be imported then go to the + # respective file and pick the line that has the instruction. + # The variable 'line' will now point to the new line from the + # imported file + + # ignore all lines starting with $import and $pseudo + if '$import' in line or '$pseudo' in line: + continue + + # call process_enc_line to get the data about the current + # instruction + (is_compressed, opcode, functs, (name, args)) = rvOpcodesDecoder.process_enc_line(line) + + + func_dict = rvOpcodesDecoder.INS_DICT[is_compressed][opcode] + for func in functs: + func_dict = func_dict[func[0]] + func_dict = func_dict[func[-1]] + + func_dict[name] = args + + def get_instr(func_dict, mcode: int): + # Get list of functions + keys = func_dict.keys() + print(keys) + for key in keys: + if type(key) == str: + return func_dict + if type(key) == tuple: + val = get_funct(key, mcode) # Non standard fields + else: + val = key(mcode) # Standard fields + print(val) + if key == rd_check: + val = True if val else False + temp_func_dict = func_dict[key][val] + if temp_func_dict.keys(): + return rvOpcodesDecoder.get_instr(temp_func_dict, mcode) + else: + continue + def decoder(self, mcode): + inst_type = False + if (mcode & rvOpcodesDecoder.FIRST_TWO != 3): + inst_type = True + + op_code = mcode & rvOpcodesDecoder.OPCODE_MASK + func_dict = rvOpcodesDecoder.INS_DICT[inst_type][op_code] + + name_args = rvOpcodesDecoder.get_instr(func_dict, mcode) + + #TODO Create instruction object + + return name_args + + def print_instr_dict(): + + printer = pprint.PrettyPrinter(indent=1, width=800, depth=None, stream=None, + compact=False, sort_dicts=False) + + s = printer.pformat(rvOpcodesDecoder.INS_DICT) + f = open('dict_tree.txt', 'w+') + f.write(s) + f.close() if __name__ == '__main__': - # Run python3 rv_opcodes_decoder.py --build clone - # to clone the repository + decoder = rvOpcodesDecoder('*') + rvOpcodesDecoder.print_instr_dict() + + # Tests + decoder.decoder(0x0a001033) + + '''f1 = open('./tests/none_result.txt', 'w+') + f2 = open('./tests/yes_result.txt' , 'w+') - cli() \ No newline at end of file + with open('./tests/ratified.txt', 'r') as fp: + for line in fp: + line = line.strip('\n') + code = int(line, 16) + ins_obj = instructionObject(code, '', '') + + old_decoder = disassembler() + old_decoder.setup('rv32') + res = old_decoder.decode(ins_obj) + if res == None: + continue + old_res = res.instr_name + result = decoder.decoder(code) + if result == None: + f1.write(f'None for {line} and {old_res} for internal decoder\n') + else: + f2.write(f'{str(result.keys())} for {line} and {old_res} for internal decoder\n') + f1.close() + f2.close()''' \ No newline at end of file From 01b967dafd8c4dbf1e7ea6fdb9dee3bca391f97c Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Thu, 17 Mar 2022 16:12:34 +0530 Subject: [PATCH 08/41] __init__.py not required --- riscv_isac/main.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/riscv_isac/main.py b/riscv_isac/main.py index 11d2edc..b45763d 100644 --- a/riscv_isac/main.py +++ b/riscv_isac/main.py @@ -195,7 +195,4 @@ def setup(url, clean): if(clean): os.system('rm -rf ' + path) else: - Repo.clone_from(url, './plugins/riscv_opcodes/') - f = open(path + '__init__.py', 'w+') - f.write('#Top Level package for riscv-opcodes') - f.close() \ No newline at end of file + Repo.clone_from(url, './plugins/riscv_opcodes/') \ No newline at end of file From b49051128c6ddba3fc214a7ba963ff0ae5c1b6fe Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Thu, 17 Mar 2022 16:15:01 +0530 Subject: [PATCH 09/41] rv-opcodes --- .../.github/workflows/python-app.yml | 21 + riscv_isac/plugins/riscv_opcodes/LICENSE | 24 + riscv_isac/plugins/riscv_opcodes/Makefile | 44 + riscv_isac/plugins/riscv_opcodes/README.md | 19 + riscv_isac/plugins/riscv_opcodes/__init__.py | 0 riscv_isac/plugins/riscv_opcodes/constants.py | 588 ++++++++ riscv_isac/plugins/riscv_opcodes/encoding.h | 306 +++++ riscv_isac/plugins/riscv_opcodes/instrs.txt | 1221 +++++++++++++++++ .../plugins/riscv_opcodes/opcodes-rvv-pseudo | 18 + riscv_isac/plugins/riscv_opcodes/parse.py | 779 +++++++++++ riscv_isac/plugins/riscv_opcodes/rv128_c | 15 + riscv_isac/plugins/riscv_opcodes/rv32_c | 5 + riscv_isac/plugins/riscv_opcodes/rv32_c_f | 8 + riscv_isac/plugins/riscv_opcodes/rv32_i | 4 + riscv_isac/plugins/riscv_opcodes/rv32_p | 3 + riscv_isac/plugins/riscv_opcodes/rv32_zbb | 3 + riscv_isac/plugins/riscv_opcodes/rv32_zbkb | 4 + riscv_isac/plugins/riscv_opcodes/rv32_zbp | 7 + riscv_isac/plugins/riscv_opcodes/rv32_zbpbo | 5 + riscv_isac/plugins/riscv_opcodes/rv32_zbs | 5 + riscv_isac/plugins/riscv_opcodes/rv32_zbt | 2 + riscv_isac/plugins/riscv_opcodes/rv32_zk | 25 + riscv_isac/plugins/riscv_opcodes/rv32_zkn | 25 + riscv_isac/plugins/riscv_opcodes/rv32_zknd | 4 + riscv_isac/plugins/riscv_opcodes/rv32_zkne | 5 + riscv_isac/plugins/riscv_opcodes/rv32_zknh | 8 + riscv_isac/plugins/riscv_opcodes/rv32_zks | 6 + riscv_isac/plugins/riscv_opcodes/rv64_a | 12 + riscv_isac/plugins/riscv_opcodes/rv64_b | 9 + riscv_isac/plugins/riscv_opcodes/rv64_c | 17 + riscv_isac/plugins/riscv_opcodes/rv64_d | 7 + riscv_isac/plugins/riscv_opcodes/rv64_f | 7 + riscv_isac/plugins/riscv_opcodes/rv64_h | 5 + riscv_isac/plugins/riscv_opcodes/rv64_i | 17 + riscv_isac/plugins/riscv_opcodes/rv64_m | 6 + riscv_isac/plugins/riscv_opcodes/rv64_p | 81 ++ riscv_isac/plugins/riscv_opcodes/rv64_q | 8 + riscv_isac/plugins/riscv_opcodes/rv64_zba | 5 + riscv_isac/plugins/riscv_opcodes/rv64_zbb | 9 + riscv_isac/plugins/riscv_opcodes/rv64_zbe | 4 + riscv_isac/plugins/riscv_opcodes/rv64_zbf | 3 + riscv_isac/plugins/riscv_opcodes/rv64_zbkb | 6 + riscv_isac/plugins/riscv_opcodes/rv64_zbm | 7 + riscv_isac/plugins/riscv_opcodes/rv64_zbp | 17 + riscv_isac/plugins/riscv_opcodes/rv64_zbpbo | 2 + riscv_isac/plugins/riscv_opcodes/rv64_zbr | 3 + riscv_isac/plugins/riscv_opcodes/rv64_zbs | 5 + riscv_isac/plugins/riscv_opcodes/rv64_zbt | 6 + riscv_isac/plugins/riscv_opcodes/rv64_zfh | 7 + riscv_isac/plugins/riscv_opcodes/rv64_zk | 28 + riscv_isac/plugins/riscv_opcodes/rv64_zkn | 28 + riscv_isac/plugins/riscv_opcodes/rv64_zknd | 7 + riscv_isac/plugins/riscv_opcodes/rv64_zkne | 5 + riscv_isac/plugins/riscv_opcodes/rv64_zknh | 6 + riscv_isac/plugins/riscv_opcodes/rv64_zks | 7 + riscv_isac/plugins/riscv_opcodes/rv_a | 11 + riscv_isac/plugins/riscv_opcodes/rv_b | 12 + riscv_isac/plugins/riscv_opcodes/rv_c | 32 + riscv_isac/plugins/riscv_opcodes/rv_c_d | 8 + riscv_isac/plugins/riscv_opcodes/rv_custom | 27 + riscv_isac/plugins/riscv_opcodes/rv_d | 26 + riscv_isac/plugins/riscv_opcodes/rv_d_zfh | 2 + riscv_isac/plugins/riscv_opcodes/rv_f | 26 + riscv_isac/plugins/riscv_opcodes/rv_h | 15 + riscv_isac/plugins/riscv_opcodes/rv_i | 46 + riscv_isac/plugins/riscv_opcodes/rv_m | 8 + riscv_isac/plugins/riscv_opcodes/rv_p | 245 ++++ riscv_isac/plugins/riscv_opcodes/rv_pseudo | 26 + riscv_isac/plugins/riscv_opcodes/rv_q | 28 + riscv_isac/plugins/riscv_opcodes/rv_q_zfh | 2 + riscv_isac/plugins/riscv_opcodes/rv_s | 3 + riscv_isac/plugins/riscv_opcodes/rv_svinval | 7 + riscv_isac/plugins/riscv_opcodes/rv_system | 5 + riscv_isac/plugins/riscv_opcodes/rv_v | 528 +++++++ riscv_isac/plugins/riscv_opcodes/rv_zba | 3 + riscv_isac/plugins/riscv_opcodes/rv_zbb | 15 + riscv_isac/plugins/riscv_opcodes/rv_zbc | 4 + riscv_isac/plugins/riscv_opcodes/rv_zbe | 5 + riscv_isac/plugins/riscv_opcodes/rv_zbf | 4 + riscv_isac/plugins/riscv_opcodes/rv_zbkb | 8 + riscv_isac/plugins/riscv_opcodes/rv_zbkc | 2 + riscv_isac/plugins/riscv_opcodes/rv_zbkx | 3 + riscv_isac/plugins/riscv_opcodes/rv_zbp | 15 + riscv_isac/plugins/riscv_opcodes/rv_zbpbo | 6 + riscv_isac/plugins/riscv_opcodes/rv_zbr | 7 + riscv_isac/plugins/riscv_opcodes/rv_zbs | 5 + riscv_isac/plugins/riscv_opcodes/rv_zbt | 6 + riscv_isac/plugins/riscv_opcodes/rv_zfh | 30 + riscv_isac/plugins/riscv_opcodes/rv_zicbo | 12 + riscv_isac/plugins/riscv_opcodes/rv_zicsr | 7 + riscv_isac/plugins/riscv_opcodes/rv_zifencei | 2 + riscv_isac/plugins/riscv_opcodes/rv_zk | 24 + riscv_isac/plugins/riscv_opcodes/rv_zkn | 24 + riscv_isac/plugins/riscv_opcodes/rv_zknh | 5 + riscv_isac/plugins/riscv_opcodes/rv_zks | 26 + riscv_isac/plugins/riscv_opcodes/rv_zksed | 4 + riscv_isac/plugins/riscv_opcodes/rv_zksh | 4 + 97 files changed, 4756 insertions(+) create mode 100644 riscv_isac/plugins/riscv_opcodes/.github/workflows/python-app.yml create mode 100644 riscv_isac/plugins/riscv_opcodes/LICENSE create mode 100644 riscv_isac/plugins/riscv_opcodes/Makefile create mode 100644 riscv_isac/plugins/riscv_opcodes/README.md create mode 100644 riscv_isac/plugins/riscv_opcodes/__init__.py create mode 100644 riscv_isac/plugins/riscv_opcodes/constants.py create mode 100644 riscv_isac/plugins/riscv_opcodes/encoding.h create mode 100644 riscv_isac/plugins/riscv_opcodes/instrs.txt create mode 100644 riscv_isac/plugins/riscv_opcodes/opcodes-rvv-pseudo create mode 100755 riscv_isac/plugins/riscv_opcodes/parse.py create mode 100644 riscv_isac/plugins/riscv_opcodes/rv128_c create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_c create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_c_f create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_i create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_p create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zbb create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zbkb create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zbp create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zbpbo create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zbs create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zbt create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zk create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zkn create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zknd create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zkne create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zknh create mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zks create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_a create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_b create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_c create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_d create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_f create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_h create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_i create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_m create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_p create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_q create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zba create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbb create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbe create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbf create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbkb create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbm create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbp create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbpbo create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbr create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbs create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbt create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zfh create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zk create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zkn create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zknd create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zkne create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zknh create mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zks create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_a create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_b create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_c create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_c_d create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_custom create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_d create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_d_zfh create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_f create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_h create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_i create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_m create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_p create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_pseudo create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_q create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_q_zfh create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_s create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_svinval create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_system create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_v create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zba create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbb create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbc create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbe create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbf create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbkb create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbkc create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbkx create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbp create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbpbo create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbr create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbs create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbt create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zfh create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zicbo create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zicsr create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zifencei create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zk create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zkn create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zknh create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zks create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zksed create mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zksh diff --git a/riscv_isac/plugins/riscv_opcodes/.github/workflows/python-app.yml b/riscv_isac/plugins/riscv_opcodes/.github/workflows/python-app.yml new file mode 100644 index 0000000..e259c3e --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/.github/workflows/python-app.yml @@ -0,0 +1,21 @@ +name: Opcodes generation + +on: + push: + branches: [ master ] + pull_request: + branches: [ master ] + +jobs: + build: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - name: Set up Python 3.8 + uses: actions/setup-python@v2 + with: + python-version: 3.8 + - name: Generation C code + run: cat opcodes-* | ./parse_opcodes -c > result.h + - name: Check C output + run: cat result.h | cpp diff --git a/riscv_isac/plugins/riscv_opcodes/LICENSE b/riscv_isac/plugins/riscv_opcodes/LICENSE new file mode 100644 index 0000000..34f576b --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/LICENSE @@ -0,0 +1,24 @@ +Copyright (c) 2010-2017, The Regents of the University of California +(Regents). All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the Regents nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, +SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING +OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS +BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED +HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE +MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. diff --git a/riscv_isac/plugins/riscv_opcodes/Makefile b/riscv_isac/plugins/riscv_opcodes/Makefile new file mode 100644 index 0000000..5a03913 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/Makefile @@ -0,0 +1,44 @@ +SHELL := /bin/sh + +ISASIM_H := ../riscv-isa-sim/riscv/encoding.h +PK_H := ../riscv-pk/machine/encoding.h +ENV_H := ../riscv-tests/env/encoding.h +OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h +INSTALL_HEADER_FILES := $(ISASIM_H) $(PK_H) $(ENV_H) $(OPENOCD_H) + +ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-rv32b opcodes-rv64b opcodes-system opcodes-svinval opcodes-rv32zfh opcodes-rv32d-zfh opcodes-rv32q-zfh opcodes-rv64zfh opcodes-rvk opcodes-rv32k opcodes-rv64k opcodes-zicbo +ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-custom opcodes-rvv opcodes-rvp + +ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) opcodes-rvv-pseudo + +install: encoding.out.h inst.chisel instr-table.tex priv-instr-table.tex + set -e; for FILE in $(INSTALL_HEADER_FILES); do cp -f encoding.out.h $$FILE; done + +encoding.out.h: $(ALL_OPCODES) parse_opcodes encoding.h + echo "/*" > $@ + echo " * This file is auto-generated by running 'make' in" >> $@ + echo " * https://github.com/riscv/riscv-opcodes (`git log -1 --format="format:%h"`)" >> $@ + echo " */" >> $@ + echo >> $@ + cat encoding.h >> $@ + cat $(ALL_OPCODES) | python ./parse_opcodes -c >> $@ + +inst.chisel: $(ALL_OPCODES) parse_opcodes + cat $(ALL_OPCODES) | ./parse_opcodes -chisel > $@ + +inst.go: $(ALL_REAL_ILEN32_OPCODES) parse_opcodes + cat $(ALL_REAL_ILEN32_OPCODES) | ./parse_opcodes -go > $@ + +inst.rs: $(ALL_OPCODES) parse_opcodes + cat $(ALL_OPCODES) | ./parse_opcodes -rust > $@ + +inst.sverilog: $(ALL_OPCODES) parse_opcodes + cat $(ALL_OPCODES) | ./parse_opcodes -sverilog > $@ + +instr-table.tex: $(ALL_OPCODES) parse_opcodes + cat $(ALL_OPCODES) | ./parse_opcodes -tex > $@ + +priv-instr-table.tex: $(ALL_OPCODES) parse_opcodes + cat $(ALL_OPCODES) | ./parse_opcodes -privtex > $@ + +.PHONY : install diff --git a/riscv_isac/plugins/riscv_opcodes/README.md b/riscv_isac/plugins/riscv_opcodes/README.md new file mode 100644 index 0000000..5f4b98a --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/README.md @@ -0,0 +1,19 @@ +# riscv-opcodes + +This repo enumerates standard RISC-V instruction opcodes and control and +status registers. It also contains a script to convert them into several +formats (C, Scala, LaTeX). + +This repo is not meant to stand alone; it is a subcomponent of +[riscv-tools](https://github.com/riscv/riscv-tools) and assumes that it +is part of that directory structure. + +## File Convention + +1. `rv_x_y` - contains instructions common within the 32-bit and 64-bit modes when both x and y extensions are enabled (note in majority of the cases y will not exist). +2. `rv32_x_y` - contains instructions present in rv32xy only (absent in rv64X_Y eg. ???) +3. `rv64_x_y` - contains instructions present in rv64xy only (absent in rv32X_Y, eg. addw) +4. `_y` in the above is optional and can be null +5. for instructions present in multiple extensions, unless the spec allocates the instruction in a specific subset, the instruction encoding must be present in the first extension when canonically ordered. All other extensions can simply include a `$import prefix` followed by `` and `` separate by `::` . For e.g `pack` would be present in the `rv32_zbe` file as +`pack rd rs1 rs2 31..25=4 14..12=4 6..2=0x0C 1..0=3` and `rv32_zbf` and `rv32_zbp` files would have the following entries : `$import rv32_zbe::pack` +6. For pseudo ops we use `$pseudo_op :: ` to indicate the original instruction that this pseudo op depends on and the pseudo instructions encoding in the entirety For e.g. the pseudo op `frflags` will be represented as `pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3` diff --git a/riscv_isac/plugins/riscv_opcodes/__init__.py b/riscv_isac/plugins/riscv_opcodes/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/riscv_isac/plugins/riscv_opcodes/constants.py b/riscv_isac/plugins/riscv_opcodes/constants.py new file mode 100644 index 0000000..4a268cd --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/constants.py @@ -0,0 +1,588 @@ +import re + + +isa_regex = \ +re.compile("^RV(32|64|128)[IE]+[ABCDEFGHJKLMNPQSTUVX]*(Zicsr|Zifencei|Zihintpause|Zam|Ztso|Zkne|Zknd|Zknh|Zkse|Zksh|Zkg|Zkb|Zkr|Zks|Zkn|Zba|Zbc|Zbb|Zbp|Zbr|Zbm|Zbs|Zbe|Zbf|Zbt|Zmmul|Zbpbo){,1}(_Zicsr){,1}(_Zifencei){,1}(_Zihintpause){,1}(_Zmmul){,1}(_Zam){,1}(_Zba){,1}(_Zbb){,1}(_Zbc){,1}(_Zbe){,1}(_Zbf){,1}(_Zbm){,1}(_Zbp){,1}(_Zbpbo){,1}(_Zbr){,1}(_Zbs){,1}(_Zbt){,1}(_Zkb){,1}(_Zkg){,1}(_Zkr){,1}(_Zks){,1}(_Zkn){,1}(_Zknd){,1}(_Zkne){,1}(_Zknh){,1}(_Zkse){,1}(_Zksh){,1}(_Ztso){,1}$") + +# regex to find ..= patterns in instruction +fixed_ranges = re.compile( + '\s*(?P\d+.?)\.\.(?P\d+.?)\s*=\s*(?P\d[\w]*)[\s$]*', re.M) + +# regex to find = patterns in instructions +#single_fixed = re.compile('\s+(?P\d+)=(?P[\w\d]*)[\s$]*', re.M) +single_fixed = re.compile('(?:^|[\s])(?P\d+)=(?P[\w]*)((?=\s|$))', re.M) + +# regex to find the overloading condition variable +var_regex = re.compile('(?P[a-zA-Z][\w\d]*)\s*=\s*.*?[\s$]*', re.M) + +# regex for pseudo op instructions returns the dependent filename, dependent +# instruction, the pseudo op name and the encoding string +pseudo_regex = re.compile( + '^\$pseudo_op\s+(?Prv[\d]*_[\w].*)::\s*(?P.*?)\s+(?P.*?)\s+(?P.*)$' +, re.M) + + +# +# Trap cause codes +causes = [ + (0x00, 'misaligned fetch'), + (0x01, 'fetch access'), + (0x02, 'illegal instruction'), + (0x03, 'breakpoint'), + (0x04, 'misaligned load'), + (0x05, 'load access'), + (0x06, 'misaligned store'), + (0x07, 'store access'), + (0x08, 'user_ecall'), + (0x09, 'supervisor_ecall'), + (0x0A, 'virtual_supervisor_ecall'), + (0x0B, 'machine_ecall'), + (0x0C, 'fetch page fault'), + (0x0D, 'load page fault'), + (0x0F, 'store page fault'), + (0x14, 'fetch guest page fault'), + (0x15, 'load guest page fault'), + (0x16, 'virtual instruction'), + (0x17, 'store guest page fault'), +] + +csrs = [ + # Standard User R/W + (0x001, 'fflags'), + (0x002, 'frm'), + (0x003, 'fcsr'), + (0x008, 'vstart'), + (0x009, 'vxsat'), + (0x00A, 'vxrm'), + (0x00F, 'vcsr'), + (0x015, 'seed'), # Zkr + + # Standard User RO + (0xC00, 'cycle'), + (0xC01, 'time'), + (0xC02, 'instret'), + (0xC03, 'hpmcounter3'), + (0xC04, 'hpmcounter4'), + (0xC05, 'hpmcounter5'), + (0xC06, 'hpmcounter6'), + (0xC07, 'hpmcounter7'), + (0xC08, 'hpmcounter8'), + (0xC09, 'hpmcounter9'), + (0xC0A, 'hpmcounter10'), + (0xC0B, 'hpmcounter11'), + (0xC0C, 'hpmcounter12'), + (0xC0D, 'hpmcounter13'), + (0xC0E, 'hpmcounter14'), + (0xC0F, 'hpmcounter15'), + (0xC10, 'hpmcounter16'), + (0xC11, 'hpmcounter17'), + (0xC12, 'hpmcounter18'), + (0xC13, 'hpmcounter19'), + (0xC14, 'hpmcounter20'), + (0xC15, 'hpmcounter21'), + (0xC16, 'hpmcounter22'), + (0xC17, 'hpmcounter23'), + (0xC18, 'hpmcounter24'), + (0xC19, 'hpmcounter25'), + (0xC1A, 'hpmcounter26'), + (0xC1B, 'hpmcounter27'), + (0xC1C, 'hpmcounter28'), + (0xC1D, 'hpmcounter29'), + (0xC1E, 'hpmcounter30'), + (0xC1F, 'hpmcounter31'), + (0xC20, 'vl'), + (0xC21, 'vtype'), + (0xC22, 'vlenb'), + + # Standard Supervisor R/W + (0x100, 'sstatus'), + (0x102, 'sedeleg'), + (0x103, 'sideleg'), + (0x104, 'sie'), + (0x105, 'stvec'), + (0x106, 'scounteren'), + (0x10A, 'senvcfg'), + (0x140, 'sscratch'), + (0x141, 'sepc'), + (0x142, 'scause'), + (0x143, 'stval'), + (0x144, 'sip'), + (0x180, 'satp'), + (0x5A8, 'scontext'), + + # Standard Hypervisor R/w + (0x200, 'vsstatus'), + (0x204, 'vsie'), + (0x205, 'vstvec'), + (0x240, 'vsscratch'), + (0x241, 'vsepc'), + (0x242, 'vscause'), + (0x243, 'vstval'), + (0x244, 'vsip'), + (0x280, 'vsatp'), + (0x600, 'hstatus'), + (0x602, 'hedeleg'), + (0x603, 'hideleg'), + (0x604, 'hie'), + (0x605, 'htimedelta'), + (0x606, 'hcounteren'), + (0x607, 'hgeie'), + (0x60A, 'henvcfg'), + (0x643, 'htval'), + (0x644, 'hip'), + (0x645, 'hvip'), + (0x64A, 'htinst'), + (0x680, 'hgatp'), + (0x6A8, 'hcontext'), + (0xE12, 'hgeip'), + + # Tentative CSR assignment for CLIC + (0x007, 'utvt'), + (0x045, 'unxti'), + (0x046, 'uintstatus'), + (0x048, 'uscratchcsw'), + (0x049, 'uscratchcswl'), + (0x107, 'stvt'), + (0x145, 'snxti'), + (0x146, 'sintstatus'), + (0x148, 'sscratchcsw'), + (0x149, 'sscratchcswl'), + (0x307, 'mtvt'), + (0x345, 'mnxti'), + (0x346, 'mintstatus'), + (0x348, 'mscratchcsw'), + (0x349, 'mscratchcswl'), + + # Standard Machine R/W + (0x300, 'mstatus'), + (0x301, 'misa'), + (0x302, 'medeleg'), + (0x303, 'mideleg'), + (0x304, 'mie'), + (0x305, 'mtvec'), + (0x306, 'mcounteren'), + (0x30a, 'menvcfg'), + (0x320, 'mcountinhibit'), + (0x340, 'mscratch'), + (0x341, 'mepc'), + (0x342, 'mcause'), + (0x343, 'mtval'), + (0x344, 'mip'), + (0x34a, 'mtinst'), + (0x34b, 'mtval2'), + (0x3a0, 'pmpcfg0'), + (0x3a1, 'pmpcfg1'), + (0x3a2, 'pmpcfg2'), + (0x3a3, 'pmpcfg3'), + (0x3a4, 'pmpcfg4'), + (0x3a5, 'pmpcfg5'), + (0x3a6, 'pmpcfg6'), + (0x3a7, 'pmpcfg7'), + (0x3a8, 'pmpcfg8'), + (0x3a9, 'pmpcfg9'), + (0x3aa, 'pmpcfg10'), + (0x3ab, 'pmpcfg11'), + (0x3ac, 'pmpcfg12'), + (0x3ad, 'pmpcfg13'), + (0x3ae, 'pmpcfg14'), + (0x3af, 'pmpcfg15'), + (0x3b0, 'pmpaddr0'), + (0x3b1, 'pmpaddr1'), + (0x3b2, 'pmpaddr2'), + (0x3b3, 'pmpaddr3'), + (0x3b4, 'pmpaddr4'), + (0x3b5, 'pmpaddr5'), + (0x3b6, 'pmpaddr6'), + (0x3b7, 'pmpaddr7'), + (0x3b8, 'pmpaddr8'), + (0x3b9, 'pmpaddr9'), + (0x3ba, 'pmpaddr10'), + (0x3bb, 'pmpaddr11'), + (0x3bc, 'pmpaddr12'), + (0x3bd, 'pmpaddr13'), + (0x3be, 'pmpaddr14'), + (0x3bf, 'pmpaddr15'), + (0x3c0, 'pmpaddr16'), + (0x3c1, 'pmpaddr17'), + (0x3c2, 'pmpaddr18'), + (0x3c3, 'pmpaddr19'), + (0x3c4, 'pmpaddr20'), + (0x3c5, 'pmpaddr21'), + (0x3c6, 'pmpaddr22'), + (0x3c7, 'pmpaddr23'), + (0x3c8, 'pmpaddr24'), + (0x3c9, 'pmpaddr25'), + (0x3ca, 'pmpaddr26'), + (0x3cb, 'pmpaddr27'), + (0x3cc, 'pmpaddr28'), + (0x3cd, 'pmpaddr29'), + (0x3ce, 'pmpaddr30'), + (0x3cf, 'pmpaddr31'), + (0x3d0, 'pmpaddr32'), + (0x3d1, 'pmpaddr33'), + (0x3d2, 'pmpaddr34'), + (0x3d3, 'pmpaddr35'), + (0x3d4, 'pmpaddr36'), + (0x3d5, 'pmpaddr37'), + (0x3d6, 'pmpaddr38'), + (0x3d7, 'pmpaddr39'), + (0x3d8, 'pmpaddr40'), + (0x3d9, 'pmpaddr41'), + (0x3da, 'pmpaddr42'), + (0x3db, 'pmpaddr43'), + (0x3dc, 'pmpaddr44'), + (0x3dd, 'pmpaddr45'), + (0x3de, 'pmpaddr46'), + (0x3df, 'pmpaddr47'), + (0x3e0, 'pmpaddr48'), + (0x3e1, 'pmpaddr49'), + (0x3e2, 'pmpaddr50'), + (0x3e3, 'pmpaddr51'), + (0x3e4, 'pmpaddr52'), + (0x3e5, 'pmpaddr53'), + (0x3e6, 'pmpaddr54'), + (0x3e7, 'pmpaddr55'), + (0x3e8, 'pmpaddr56'), + (0x3e9, 'pmpaddr57'), + (0x3ea, 'pmpaddr58'), + (0x3eb, 'pmpaddr59'), + (0x3ec, 'pmpaddr60'), + (0x3ed, 'pmpaddr61'), + (0x3ee, 'pmpaddr62'), + (0x3ef, 'pmpaddr63'), + (0x747, 'mseccfg'), + (0x7a0, 'tselect'), + (0x7a1, 'tdata1'), + (0x7a2, 'tdata2'), + (0x7a3, 'tdata3'), + (0x7a4, 'tinfo'), + (0x7a5, 'tcontrol'), + (0x7a8, 'mcontext'), + (0x7aa, 'mscontext'), + (0x7b0, 'dcsr'), + (0x7b1, 'dpc'), + (0x7b2, 'dscratch0'), + (0x7b3, 'dscratch1'), + (0xB00, 'mcycle'), + (0xB02, 'minstret'), + (0xB03, 'mhpmcounter3'), + (0xB04, 'mhpmcounter4'), + (0xB05, 'mhpmcounter5'), + (0xB06, 'mhpmcounter6'), + (0xB07, 'mhpmcounter7'), + (0xB08, 'mhpmcounter8'), + (0xB09, 'mhpmcounter9'), + (0xB0A, 'mhpmcounter10'), + (0xB0B, 'mhpmcounter11'), + (0xB0C, 'mhpmcounter12'), + (0xB0D, 'mhpmcounter13'), + (0xB0E, 'mhpmcounter14'), + (0xB0F, 'mhpmcounter15'), + (0xB10, 'mhpmcounter16'), + (0xB11, 'mhpmcounter17'), + (0xB12, 'mhpmcounter18'), + (0xB13, 'mhpmcounter19'), + (0xB14, 'mhpmcounter20'), + (0xB15, 'mhpmcounter21'), + (0xB16, 'mhpmcounter22'), + (0xB17, 'mhpmcounter23'), + (0xB18, 'mhpmcounter24'), + (0xB19, 'mhpmcounter25'), + (0xB1A, 'mhpmcounter26'), + (0xB1B, 'mhpmcounter27'), + (0xB1C, 'mhpmcounter28'), + (0xB1D, 'mhpmcounter29'), + (0xB1E, 'mhpmcounter30'), + (0xB1F, 'mhpmcounter31'), + (0x323, 'mhpmevent3'), + (0x324, 'mhpmevent4'), + (0x325, 'mhpmevent5'), + (0x326, 'mhpmevent6'), + (0x327, 'mhpmevent7'), + (0x328, 'mhpmevent8'), + (0x329, 'mhpmevent9'), + (0x32A, 'mhpmevent10'), + (0x32B, 'mhpmevent11'), + (0x32C, 'mhpmevent12'), + (0x32D, 'mhpmevent13'), + (0x32E, 'mhpmevent14'), + (0x32F, 'mhpmevent15'), + (0x330, 'mhpmevent16'), + (0x331, 'mhpmevent17'), + (0x332, 'mhpmevent18'), + (0x333, 'mhpmevent19'), + (0x334, 'mhpmevent20'), + (0x335, 'mhpmevent21'), + (0x336, 'mhpmevent22'), + (0x337, 'mhpmevent23'), + (0x338, 'mhpmevent24'), + (0x339, 'mhpmevent25'), + (0x33A, 'mhpmevent26'), + (0x33B, 'mhpmevent27'), + (0x33C, 'mhpmevent28'), + (0x33D, 'mhpmevent29'), + (0x33E, 'mhpmevent30'), + (0x33F, 'mhpmevent31'), + + # Standard Machine RO + (0xF11, 'mvendorid'), + (0xF12, 'marchid'), + (0xF13, 'mimpid'), + (0xF14, 'mhartid'), + (0xF15, 'mconfigptr'), +] + +csrs32 = [ + # Standard Hypervisor R/w + (0x615, 'htimedeltah'), + (0x61A, 'henvcfgh'), + + # Standard User RO + (0xC80, 'cycleh'), + (0xC81, 'timeh'), + (0xC82, 'instreth'), + (0xC83, 'hpmcounter3h'), + (0xC84, 'hpmcounter4h'), + (0xC85, 'hpmcounter5h'), + (0xC86, 'hpmcounter6h'), + (0xC87, 'hpmcounter7h'), + (0xC88, 'hpmcounter8h'), + (0xC89, 'hpmcounter9h'), + (0xC8A, 'hpmcounter10h'), + (0xC8B, 'hpmcounter11h'), + (0xC8C, 'hpmcounter12h'), + (0xC8D, 'hpmcounter13h'), + (0xC8E, 'hpmcounter14h'), + (0xC8F, 'hpmcounter15h'), + (0xC90, 'hpmcounter16h'), + (0xC91, 'hpmcounter17h'), + (0xC92, 'hpmcounter18h'), + (0xC93, 'hpmcounter19h'), + (0xC94, 'hpmcounter20h'), + (0xC95, 'hpmcounter21h'), + (0xC96, 'hpmcounter22h'), + (0xC97, 'hpmcounter23h'), + (0xC98, 'hpmcounter24h'), + (0xC99, 'hpmcounter25h'), + (0xC9A, 'hpmcounter26h'), + (0xC9B, 'hpmcounter27h'), + (0xC9C, 'hpmcounter28h'), + (0xC9D, 'hpmcounter29h'), + (0xC9E, 'hpmcounter30h'), + (0xC9F, 'hpmcounter31h'), + + # Standard Machine RW + (0x310, 'mstatush'), + (0x31A, 'menvcfgh'), + (0x757, 'mseccfgh'), + (0xB80, 'mcycleh'), + (0xB82, 'minstreth'), + (0xB83, 'mhpmcounter3h'), + (0xB84, 'mhpmcounter4h'), + (0xB85, 'mhpmcounter5h'), + (0xB86, 'mhpmcounter6h'), + (0xB87, 'mhpmcounter7h'), + (0xB88, 'mhpmcounter8h'), + (0xB89, 'mhpmcounter9h'), + (0xB8A, 'mhpmcounter10h'), + (0xB8B, 'mhpmcounter11h'), + (0xB8C, 'mhpmcounter12h'), + (0xB8D, 'mhpmcounter13h'), + (0xB8E, 'mhpmcounter14h'), + (0xB8F, 'mhpmcounter15h'), + (0xB90, 'mhpmcounter16h'), + (0xB91, 'mhpmcounter17h'), + (0xB92, 'mhpmcounter18h'), + (0xB93, 'mhpmcounter19h'), + (0xB94, 'mhpmcounter20h'), + (0xB95, 'mhpmcounter21h'), + (0xB96, 'mhpmcounter22h'), + (0xB97, 'mhpmcounter23h'), + (0xB98, 'mhpmcounter24h'), + (0xB99, 'mhpmcounter25h'), + (0xB9A, 'mhpmcounter26h'), + (0xB9B, 'mhpmcounter27h'), + (0xB9C, 'mhpmcounter28h'), + (0xB9D, 'mhpmcounter29h'), + (0xB9E, 'mhpmcounter30h'), + (0xB9F, 'mhpmcounter31h'), +] + +# look up table of position of various arguments that are used by the +# instructions in the encoding files. +arg_lut = {} +arg_lut['rd'] = (11, 7) +arg_lut['rt'] = (19, 15) # source+dest register address. Overlaps rs1. +arg_lut['rs1'] = (19, 15) +arg_lut['rs2'] = (24, 20) +arg_lut['rs3'] = (31, 27) +arg_lut['aqrl'] = (26, 25) +arg_lut['aq'] = (26, 26) +arg_lut['rl'] = (25, 25) +arg_lut['fm'] = (31, 28) +arg_lut['pred'] = (27, 24) +arg_lut['succ'] = (23, 20) +arg_lut['rm'] = (14, 12) +arg_lut['funct3'] = (14, 12) +arg_lut['funct2'] = (26, 25) +arg_lut['imm20'] = (31, 12) +arg_lut['jimm20'] = (31, 12) +arg_lut['imm12'] = (31, 20) +arg_lut['imm12hi'] = (31, 25) +arg_lut['bimm12hi'] = (31, 25) +arg_lut['imm12lo'] = (11, 7) +arg_lut['bimm12lo'] = (11, 7) +arg_lut['zimm'] = (19, 15) +arg_lut['shamt'] = (25, 20) +arg_lut['shamtw'] = (24, 20) +arg_lut['shamtw4'] = (23, 20) +arg_lut['bs'] = (31, 30) # byte select for RV32K AES +arg_lut['rnum'] = (23, 20) # round constant for RV64 AES +arg_lut['rc'] = (29, 25) +arg_lut['imm2'] = (21, 20) +arg_lut['imm3'] = (22, 20) +arg_lut['imm4'] = (23, 20) +arg_lut['imm5'] = (24, 20) +arg_lut['imm6'] = (25, 20) +arg_lut['zimm'] = (19, 15) +arg_lut['opcode'] = (6,0) +arg_lut['funct7'] = (31,25) + +# for vectors +arg_lut['vd'] = (11, 7) +arg_lut['vs3'] = (11, 7) +arg_lut['vs1'] = (19, 15) +arg_lut['vs2'] = (24, 20) +arg_lut['vm'] = (25, 25) +arg_lut['wd'] = (26, 26) +arg_lut['amoop'] = (31, 27) +arg_lut['nf'] = (31, 29) +arg_lut['simm5'] = (19, 15) +arg_lut['zimm10'] = (29, 20) +arg_lut['zimm11'] = (30, 20) + + +#compressed immediates and fields +arg_lut['c_nzuimm10'] = (12,5) +arg_lut['c_uimm7lo'] = (6,5) +arg_lut['c_uimm7hi'] = (12,10) +arg_lut['c_uimm8lo'] = (6,5) +arg_lut['c_uimm8hi'] = (12,10) +arg_lut['c_uimm9lo'] = (6,5) +arg_lut['c_uimm9hi'] = (12,10) +arg_lut['c_nzimm6lo'] = (6,2) +arg_lut['c_nzimm6hi'] = (12,12) +arg_lut['c_imm6lo'] = (6,2) +arg_lut['c_imm6hi'] = (12,12) +arg_lut['c_nzimm10hi'] = (12,12) +arg_lut['c_nzimm10lo'] = (6,2) +arg_lut['c_nzimm18hi'] = (12,12) +arg_lut['c_nzimm18lo'] = (6,2) +arg_lut['c_imm12'] = (12,2) +arg_lut['c_bimm9lo'] = (6,2) +arg_lut['c_bimm9hi'] = (12,10) +arg_lut['c_nzuimm5'] = (6,2) +arg_lut['c_nzuimm6lo'] = (6,2) +arg_lut['c_nzuimm6hi'] = (12, 12) +arg_lut['c_uimm8splo'] = (6,2) +arg_lut['c_uimm8sphi'] = (12, 12) +arg_lut['c_uimm8sp_s'] = (12,7) +arg_lut['c_uimm10splo'] = (6,2) +arg_lut['c_uimm10sphi'] = (12, 12) +arg_lut['c_uimm9splo'] = (6,2) +arg_lut['c_uimm9sphi'] = (12, 12) +arg_lut['c_uimm10sp_s'] = (12,7) +arg_lut['c_uimm9sp_s'] = (12,7) + +arg_lut['rs1_p'] = (9,7) +arg_lut['rs2_p'] = (4,2) +arg_lut['rd_p'] = (4,2) +arg_lut['rd_rs1_n0'] = (11,7) +arg_lut['rd_rs1_p'] = (9,7) +arg_lut['rd_rs1'] = (11,7) +arg_lut['rd_n2'] = (11,7) +arg_lut['rd_n0'] = (11,7) +arg_lut['rs1_n0'] = (11,7) +arg_lut['c_rs2_n0'] = (6,2) +arg_lut['c_rs1_n0'] = (11,7) +arg_lut['c_rs2'] = (6,2) + +# dictionary containing the mapping of the argument to the what the fields in +# the latex table should be +latex_mapping = {} +latex_mapping['imm12'] = 'imm[11:0]' +latex_mapping['rs1'] = 'rs1' +latex_mapping['rs2'] = 'rs2' +latex_mapping['rd'] = 'rd' +latex_mapping['imm20'] = 'imm[31:12]' +latex_mapping['bimm12hi'] = 'imm[12$\\vert$10:5]' +latex_mapping['bimm12lo'] = 'imm[4:1$\\vert$11]' +latex_mapping['imm12hi'] = 'imm[11:5]' +latex_mapping['imm12lo'] = 'imm[4:0]' +latex_mapping['jimm20'] = 'imm[20$\\vert$10:1$\\vert$11$\\vert$19:12]' +latex_mapping['zimm'] = 'uimm' +latex_mapping['shamtw'] = 'shamt' +latex_mapping['rd_p'] = "rd\\,$'$" +latex_mapping['rs1_p'] = "rs1\\,$'$" +latex_mapping['rs2_p'] = "rs2\\,$'$" +latex_mapping['rd_rs1_n0'] = 'rd/rs$\\neq$0' +latex_mapping['rd_rs1_p'] = "rs1\\,$'$/rs2\\,$'$" +latex_mapping['c_rs2'] = 'rs2' +latex_mapping['c_rs2_n0'] = 'rs2$\\neq$0' +latex_mapping['rd_n0'] = 'rd$\\neq$0' +latex_mapping['rs1_n0'] = 'rs1$\\neq$0' +latex_mapping['c_rs1_n0'] = 'rs1$\\neq$0' +latex_mapping['rd_rs1'] = 'rd/rs1' +latex_mapping['c_nzuimm10'] = "nzuimm[5:4$\\vert$9:6$\\vert$2$\\vert$3]" +latex_mapping['c_uimm7lo'] = 'uimm[2$\\vert$6]' +latex_mapping['c_uimm7hi'] = 'uimm[5:3]' +latex_mapping['c_uimm8lo'] = 'uimm[7:6]' +latex_mapping['c_uimm8hi'] = 'uimm[5:3]' +latex_mapping['c_uimm9lo'] = 'uimm[7:6]' +latex_mapping['c_uimm9hi'] = 'uimm[5:4$\\vert$8]' +latex_mapping['c_nzimm6lo'] = 'nzimm[4:0]' +latex_mapping['c_nzimm6hi'] = 'nzimm[5]' +latex_mapping['c_imm6lo'] = 'imm[4:0]' +latex_mapping['c_imm6hi'] = 'imm[5]' +latex_mapping['c_nzimm10hi'] = 'nzimm[9]' +latex_mapping['c_nzimm10lo'] = 'nzimm[4$\\vert$6$\\vert$8:7$\\vert$5]' +latex_mapping['c_nzimm18hi'] = 'nzimm[17]' +latex_mapping['c_nzimm18lo'] = 'nzimm[16:12]' +latex_mapping['c_imm12'] = 'imm[11$\\vert$4$\\vert$9:8$\\vert$10$\\vert$6$\\vert$7$\\vert$3:1$\\vert$5]' +latex_mapping['c_bimm9lo'] = 'imm[7:6$\\vert$2:1$\\vert$5]' +latex_mapping['c_bimm9hi'] = 'imm[8$\\vert$4:3]' +latex_mapping['c_nzuimm5'] = 'nzuimm[4:0]' +latex_mapping['c_nzuimm6lo'] = 'nzuimm[4:0]' +latex_mapping['c_nzuimm6hi'] = 'nzuimm[5]' +latex_mapping['c_uimm8splo'] = 'uimm[4:2$\\vert$7:6]' +latex_mapping['c_uimm8sphi'] = 'uimm[5]' +latex_mapping['c_uimm8sp_s'] = 'uimm[5:2$\\vert$7:6]' +latex_mapping['c_uimm10splo'] = 'uimm[4$\\vert$9:6]' +latex_mapping['c_uimm10sphi'] = 'uimm[5]' +latex_mapping['c_uimm9splo'] = 'uimm[4:3$\\vert$8:6]' +latex_mapping['c_uimm9sphi'] = 'uimm[5]' +latex_mapping['c_uimm10sp_s'] = 'uimm[5:4$\\vert$9:6]' +latex_mapping['c_uimm9sp_s'] = 'uimm[5:3$\\vert$8:6]' + +# created a dummy instruction-dictionary like dictionary for all the instruction +# types so that the same logic can be used to create their tables +latex_inst_type = {} +latex_inst_type['R-type'] = {} +latex_inst_type['R-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ + 'rs1', 'rs2', 'funct7'] +latex_inst_type['I-type'] = {} +latex_inst_type['I-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ + 'rs1', 'imm12'] +latex_inst_type['S-type'] = {} +latex_inst_type['S-type']['variable_fields'] = ['opcode', 'imm12lo', 'funct3', \ + 'rs1', 'rs2', 'imm12hi'] +latex_inst_type['B-type'] = {} +latex_inst_type['B-type']['variable_fields'] = ['opcode', 'bimm12lo', 'funct3', \ + 'rs1', 'rs2', 'bimm12hi'] +latex_inst_type['U-type'] = {} +latex_inst_type['U-type']['variable_fields'] = ['opcode', 'rd', 'imm20'] +latex_inst_type['J-type'] = {} +latex_inst_type['J-type']['variable_fields'] = ['opcode', 'rd', 'jimm20'] +latex_inst_type['R4-type'] = {} +latex_inst_type['R4-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ + 'rs1', 'rs2', 'funct2', 'rs3'] diff --git a/riscv_isac/plugins/riscv_opcodes/encoding.h b/riscv_isac/plugins/riscv_opcodes/encoding.h new file mode 100644 index 0000000..66358b7 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/encoding.h @@ -0,0 +1,306 @@ +/* See LICENSE for license details. */ + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_UBE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_VS 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS_SBE 0x0000001000000000 +#define MSTATUS_MBE 0x0000002000000000 +#define MSTATUS_GVA 0x0000004000000000 +#define MSTATUS_MPV 0x0000008000000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define MSTATUSH_SBE 0x00000010 +#define MSTATUSH_MBE 0x00000020 +#define MSTATUSH_GVA 0x00000040 +#define MSTATUSH_MPV 0x00000080 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_UBE 0x00000040 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_VS 0x00000600 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define HSTATUS_VSXL 0x300000000 +#define HSTATUS_VTSR 0x00400000 +#define HSTATUS_VTW 0x00200000 +#define HSTATUS_VTVM 0x00100000 +#define HSTATUS_VGEIN 0x0003f000 +#define HSTATUS_HU 0x00000200 +#define HSTATUS_SPVP 0x00000100 +#define HSTATUS_SPV 0x00000080 +#define HSTATUS_GVA 0x00000040 +#define HSTATUS_VSBE 0x00000020 + +#define USTATUS_UIE 0x00000001 +#define USTATUS_UPIE 0x00000010 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 +#define DCSR_CAUSE_GROUP 6 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_USIP (1 << IRQ_U_SOFT) +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_VSSIP (1 << IRQ_VS_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_UTIP (1 << IRQ_U_TIMER) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_VSTIP (1 << IRQ_VS_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_UEIP (1 << IRQ_U_EXT) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_VSEIP (1 << IRQ_VS_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) +#define MIP_SGEIP (1 << IRQ_S_GEXT) + +#define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP) +#define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) +#define MIP_HS_MASK (MIP_VS_MASK | MIP_SGEIP) + +#define MIDELEG_FORCED_MASK MIP_HS_MASK + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define MENVCFG_FIOM 0x00000001 +#define MENVCFG_CBIE 0x00000030 +#define MENVCFG_CBCFE 0x00000040 +#define MENVCFG_CBZE 0x00000080 +#define MENVCFG_PBMTE 0x4000000000000000 +#define MENVCFG_STCE 0x8000000000000000 + +#define MENVCFGH_PBMTE 0x40000000 +#define MENVCFGH_STCE 0x80000000 + +#define HENVCFG_FIOM 0x00000001 +#define HENVCFG_CBIE 0x00000030 +#define HENVCFG_CBCFE 0x00000040 +#define HENVCFG_CBZE 0x00000080 +#define HENVCFG_PBMTE 0x4000000000000000 +#define HENVCFG_STCE 0x8000000000000000 + +#define HENVCFGH_PBMTE 0x40000000 +#define HENVCFGH_STCE 0x80000000 + +#define SENVCFG_FIOM 0x00000001 +#define SENVCFG_CBIE 0x00000030 +#define SENVCFG_CBCFE 0x00000040 +#define SENVCFG_CBZE 0x00000080 + +#define MSECCFG_MML 0x00000001 +#define MSECCFG_MMWP 0x00000002 +#define MSECCFG_RLB 0x00000004 +#define MSECCFG_USEED 0x00000100 +#define MSECCFG_SSEED 0x00000200 + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_M 3 + +#define PRV_HS (PRV_S + 1) + +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define HGATP32_MODE 0x80000000 +#define HGATP32_VMID 0x1FC00000 +#define HGATP32_PPN 0x003FFFFF + +#define HGATP64_MODE 0xF000000000000000 +#define HGATP64_VMID 0x03FFF00000000000 +#define HGATP64_PPN 0x00000FFFFFFFFFFF + +#define HGATP_MODE_OFF 0 +#define HGATP_MODE_SV32X4 1 +#define HGATP_MODE_SV39X4 8 +#define HGATP_MODE_SV48X4 9 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define IRQ_U_SOFT 0 +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_U_TIMER 4 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_U_EXT 8 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +/* page table entry (PTE) fields */ +#define PTE_V 0x001 /* Valid */ +#define PTE_R 0x002 /* Read */ +#define PTE_W 0x004 /* Write */ +#define PTE_X 0x008 /* Execute */ +#define PTE_U 0x010 /* User */ +#define PTE_G 0x020 /* Global */ +#define PTE_A 0x040 /* Accessed */ +#define PTE_D 0x080 /* Dirty */ +#define PTE_SOFT 0x300 /* Reserved for Software */ +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ +#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ +#define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ +#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#if __riscv_xlen == 64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif diff --git a/riscv_isac/plugins/riscv_opcodes/instrs.txt b/riscv_isac/plugins/riscv_opcodes/instrs.txt new file mode 100644 index 0000000..88e0001 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/instrs.txt @@ -0,0 +1,1221 @@ +lwu : {'encoding': '-----------------110-----0000011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv64_i'], 'match': '0x6003', 'mask': '0x707f'} +ld : {'encoding': '-----------------011-----0000011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv64_i'], 'match': '0x3003', 'mask': '0x707f'} +sd : {'encoding': '-----------------011-----0100011', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv64_i'], 'match': '0x3023', 'mask': '0x707f'} +slli : {'encoding': '000000-----------001-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_i'], 'match': '0x1013', 'mask': '0xfc00707f'} +srli : {'encoding': '000000-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_i'], 'match': '0x5013', 'mask': '0xfc00707f'} +srai : {'encoding': '010000-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_i'], 'match': '0x40005013', 'mask': '0xfc00707f'} +addiw : {'encoding': '-----------------000-----0011011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv64_i'], 'match': '0x1b', 'mask': '0x707f'} +slliw : {'encoding': '0000000----------001-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_i'], 'match': '0x101b', 'mask': '0xfe00707f'} +srliw : {'encoding': '0000000----------101-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_i'], 'match': '0x501b', 'mask': '0xfe00707f'} +sraiw : {'encoding': '0100000----------101-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_i'], 'match': '0x4000501b', 'mask': '0xfe00707f'} +addw : {'encoding': '0000000----------000-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_i'], 'match': '0x3b', 'mask': '0xfe00707f'} +subw : {'encoding': '0100000----------000-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_i'], 'match': '0x4000003b', 'mask': '0xfe00707f'} +sllw : {'encoding': '0000000----------001-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_i'], 'match': '0x103b', 'mask': '0xfe00707f'} +srlw : {'encoding': '0000000----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_i'], 'match': '0x503b', 'mask': '0xfe00707f'} +sraw : {'encoding': '0100000----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_i'], 'match': '0x4000503b', 'mask': '0xfe00707f'} +bclri : {'encoding': '010010-----------001-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zbs'], 'match': '0x48001013', 'mask': '0xfc00707f'} +bexti : {'encoding': '010010-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zbs'], 'match': '0x48005013', 'mask': '0xfc00707f'} +binvi : {'encoding': '011010-----------001-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zbs'], 'match': '0x68001013', 'mask': '0xfc00707f'} +bseti : {'encoding': '001010-----------001-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zbs'], 'match': '0x28001013', 'mask': '0xfc00707f'} +sha512sum0r : {'encoding': '0101000----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv32_zknh'], 'match': '0x50000033', 'mask': '0xfe00707f'} +sha512sum1r : {'encoding': '0101001----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv32_zknh'], 'match': '0x52000033', 'mask': '0xfe00707f'} +sha512sig0l : {'encoding': '0101010----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv32_zknh'], 'match': '0x54000033', 'mask': '0xfe00707f'} +sha512sig0h : {'encoding': '0101110----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv32_zknh'], 'match': '0x5c000033', 'mask': '0xfe00707f'} +sha512sig1l : {'encoding': '0101011----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv32_zknh'], 'match': '0x56000033', 'mask': '0xfe00707f'} +sha512sig1h : {'encoding': '0101111----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv32_zknh'], 'match': '0x5e000033', 'mask': '0xfe00707f'} +cmix : {'encoding': '-----11----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3'], 'extension': ['rv_zbt'], 'match': '0x6001033', 'mask': '0x600707f'} +cmov : {'encoding': '-----11----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3'], 'extension': ['rv_zbt'], 'match': '0x6005033', 'mask': '0x600707f'} +fsl : {'encoding': '-----10----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3'], 'extension': ['rv_zbt'], 'match': '0x4001033', 'mask': '0x600707f'} +fsr : {'encoding': '-----10----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3'], 'extension': ['rv_zbt'], 'match': '0x4005033', 'mask': '0x600707f'} +aes32esmi : {'encoding': '--10011----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'bs'], 'extension': ['rv32_zkne'], 'match': '0x26000033', 'mask': '0x3e00707f'} +aes32esi : {'encoding': '--10001----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'bs'], 'extension': ['rv32_zkne'], 'match': '0x22000033', 'mask': '0x3e00707f'} +c_addi4spn : {'encoding': '----------------000-----------00', 'variable_fields': ['rd_p', 'c_nzuimm10'], 'extension': ['rv_c'], 'match': '0x0', 'mask': '0xe003'} +c_lw : {'encoding': '----------------010-----------00', 'variable_fields': ['rd_p', 'rs1_p', 'c_uimm7lo', 'c_uimm7hi'], 'extension': ['rv_c'], 'match': '0x4000', 'mask': '0xe003'} +c_sw : {'encoding': '----------------110-----------00', 'variable_fields': ['rs1_p', 'rs2_p', 'c_uimm7lo', 'c_uimm7hi'], 'extension': ['rv_c'], 'match': '0xc000', 'mask': '0xe003'} +c_nop : {'encoding': '----------------000-00000-----01', 'variable_fields': ['c_nzimm6hi', 'c_nzimm6lo'], 'extension': ['rv_c'], 'match': '0x1', 'mask': '0xef83'} +c_addi : {'encoding': '----------------000-----------01', 'variable_fields': ['rd_rs1_n0', 'c_nzimm6lo', 'c_nzimm6hi'], 'extension': ['rv_c'], 'match': '0x1', 'mask': '0xe003'} +c_li : {'encoding': '----------------010-----------01', 'variable_fields': ['rd', 'c_imm6lo', 'c_imm6hi'], 'extension': ['rv_c'], 'match': '0x4001', 'mask': '0xe003'} +c_addi16sp : {'encoding': '----------------011-00010-----01', 'variable_fields': ['c_nzimm10hi', 'c_nzimm10lo'], 'extension': ['rv_c'], 'match': '0x6101', 'mask': '0xef83'} +c_lui : {'encoding': '----------------011-----------01', 'variable_fields': ['rd_n2', 'c_nzimm18hi', 'c_nzimm18lo'], 'extension': ['rv_c'], 'match': '0x6001', 'mask': '0xe003'} +c_andi : {'encoding': '----------------100-10--------01', 'variable_fields': ['rd_rs1_p', 'c_imm6hi', 'c_imm6lo'], 'extension': ['rv_c'], 'match': '0x8801', 'mask': '0xec03'} +c_sub : {'encoding': '----------------100011---00---01', 'variable_fields': ['rd_rs1_p', 'rs2_p'], 'extension': ['rv_c'], 'match': '0x8c01', 'mask': '0xfc63'} +c_xor : {'encoding': '----------------100011---01---01', 'variable_fields': ['rd_rs1_p', 'rs2_p'], 'extension': ['rv_c'], 'match': '0x8c21', 'mask': '0xfc63'} +c_or : {'encoding': '----------------100011---10---01', 'variable_fields': ['rd_rs1_p', 'rs2_p'], 'extension': ['rv_c'], 'match': '0x8c41', 'mask': '0xfc63'} +c_and : {'encoding': '----------------100011---11---01', 'variable_fields': ['rd_rs1_p', 'rs2_p'], 'extension': ['rv_c'], 'match': '0x8c61', 'mask': '0xfc63'} +c_j : {'encoding': '----------------101-----------01', 'variable_fields': ['c_imm12'], 'extension': ['rv_c'], 'match': '0xa001', 'mask': '0xe003'} +c_beqz : {'encoding': '----------------110-----------01', 'variable_fields': ['rs1_p', 'c_bimm9lo', 'c_bimm9hi'], 'extension': ['rv_c'], 'match': '0xc001', 'mask': '0xe003'} +c_bnez : {'encoding': '----------------111-----------01', 'variable_fields': ['rs1_p', 'c_bimm9lo', 'c_bimm9hi'], 'extension': ['rv_c'], 'match': '0xe001', 'mask': '0xe003'} +c_lwsp : {'encoding': '----------------010-----------10', 'variable_fields': ['rd_n0', 'c_uimm8sphi', 'c_uimm8splo'], 'extension': ['rv_c'], 'match': '0x4002', 'mask': '0xe003'} +c_jr : {'encoding': '----------------1000-----0000010', 'variable_fields': ['rs1_n0'], 'extension': ['rv_c'], 'match': '0x8002', 'mask': '0xf07f'} +c_mv : {'encoding': '----------------1000----------10', 'variable_fields': ['rd', 'c_rs2_n0'], 'extension': ['rv_c'], 'match': '0x8002', 'mask': '0xf003'} +c_ebreak : {'encoding': '----------------1001000000000010', 'variable_fields': [], 'extension': ['rv_c'], 'match': '0x9002', 'mask': '0xffff'} +c_jalr : {'encoding': '----------------1001-----0000010', 'variable_fields': ['c_rs1_n0'], 'extension': ['rv_c'], 'match': '0x9002', 'mask': '0xf07f'} +c_add : {'encoding': '----------------1001----------10', 'variable_fields': ['rd_rs1', 'c_rs2_n0'], 'extension': ['rv_c'], 'match': '0x9002', 'mask': '0xf003'} +c_swsp : {'encoding': '----------------110-----------10', 'variable_fields': ['c_rs2', 'c_uimm8sp_s'], 'extension': ['rv_c'], 'match': '0xc002', 'mask': '0xe003'} +fcvt_q_h : {'encoding': '010001100010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q_zfh'], 'match': '0x46200053', 'mask': '0xfff0007f'} +fcvt_h_q : {'encoding': '010001000011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q_zfh'], 'match': '0x44300053', 'mask': '0xfff0007f'} +sha256sum0 : {'encoding': '000100000000-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zknh'], 'match': '0x10001013', 'mask': '0xfff0707f'} +sha256sum1 : {'encoding': '000100000001-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zknh'], 'match': '0x10101013', 'mask': '0xfff0707f'} +sha256sig0 : {'encoding': '000100000010-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zknh'], 'match': '0x10201013', 'mask': '0xfff0707f'} +sha256sig1 : {'encoding': '000100000011-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zknh'], 'match': '0x10301013', 'mask': '0xfff0707f'} +bfp : {'encoding': '0100100----------111-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbf'], 'match': '0x48007033', 'mask': '0xfe00707f'} +c_flw : {'encoding': '----------------011-----------00', 'variable_fields': ['rd_p', 'rs1_p', 'c_uimm7lo', 'c_uimm7hi'], 'extension': ['rv32_c_f'], 'match': '0x6000', 'mask': '0xe003'} +c_fsw : {'encoding': '----------------111-----------00', 'variable_fields': ['rs1_p', 'rs2_p', 'c_uimm7lo', 'c_uimm7hi'], 'extension': ['rv32_c_f'], 'match': '0xe000', 'mask': '0xe003'} +c_flwsp : {'encoding': '----------------011-----------10', 'variable_fields': ['rd', 'c_uimm8sphi', 'c_uimm8splo'], 'extension': ['rv32_c_f'], 'match': '0x6002', 'mask': '0xe003'} +c_fswsp : {'encoding': '----------------111-----------10', 'variable_fields': ['c_rs2', 'c_uimm8sp_s'], 'extension': ['rv32_c_f'], 'match': '0xe002', 'mask': '0xe003'} +fcvt_l_s : {'encoding': '110000000010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_f'], 'match': '0xc0200053', 'mask': '0xfff0007f'} +fcvt_lu_s : {'encoding': '110000000011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_f'], 'match': '0xc0300053', 'mask': '0xfff0007f'} +fcvt_s_l : {'encoding': '110100000010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_f'], 'match': '0xd0200053', 'mask': '0xfff0007f'} +fcvt_s_lu : {'encoding': '110100000011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_f'], 'match': '0xd0300053', 'mask': '0xfff0007f'} +add8 : {'encoding': '0100100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x48000077', 'mask': '0xfe00707f'} +add16 : {'encoding': '0100000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x40000077', 'mask': '0xfe00707f'} +ave : {'encoding': '1110000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xe0000077', 'mask': '0xfe00707f'} +bitrev : {'encoding': '1110011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xe6000077', 'mask': '0xfe00707f'} +bitrevi : {'encoding': '111010-----------000-----1110111', 'variable_fields': ['imm6', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xe8000077', 'mask': '0xfc00707f'} +bpick : {'encoding': '-----00----------011-----1110111', 'variable_fields': ['rs3', 'rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x3077', 'mask': '0x600707f'} +clrs8 : {'encoding': '101011100000-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xae000077', 'mask': '0xfff0707f'} +clrs16 : {'encoding': '101011101000-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xae800077', 'mask': '0xfff0707f'} +clrs32 : {'encoding': '101011111000-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xaf800077', 'mask': '0xfff0707f'} +clo8 : {'encoding': '101011100011-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xae300077', 'mask': '0xfff0707f'} +clo16 : {'encoding': '101011101011-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xaeb00077', 'mask': '0xfff0707f'} +clo32 : {'encoding': '101011111011-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xafb00077', 'mask': '0xfff0707f'} +clz8 : {'encoding': '101011100001-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xae100077', 'mask': '0xfff0707f'} +clz16 : {'encoding': '101011101001-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xae900077', 'mask': '0xfff0707f'} +clz32 : {'encoding': '101011111001-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xaf900077', 'mask': '0xfff0707f'} +cmpeq8 : {'encoding': '0100111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x4e000077', 'mask': '0xfe00707f'} +cmpeq16 : {'encoding': '0100110----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x4c000077', 'mask': '0xfe00707f'} +cras16 : {'encoding': '0100010----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x44000077', 'mask': '0xfe00707f'} +crsa16 : {'encoding': '0100011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x46000077', 'mask': '0xfe00707f'} +insb : {'encoding': '101011000--------000-----1110111', 'variable_fields': ['imm3', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xac000077', 'mask': '0xff80707f'} +kabs8 : {'encoding': '101011010000-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xad000077', 'mask': '0xfff0707f'} +kabs16 : {'encoding': '101011010001-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xad100077', 'mask': '0xfff0707f'} +kabsw : {'encoding': '101011010100-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xad400077', 'mask': '0xfff0707f'} +kadd8 : {'encoding': '0001100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x18000077', 'mask': '0xfe00707f'} +kadd16 : {'encoding': '0001000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x10000077', 'mask': '0xfe00707f'} +kadd64 : {'encoding': '1001000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x90001077', 'mask': '0xfe00707f'} +kaddh : {'encoding': '0000010----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x4001077', 'mask': '0xfe00707f'} +kaddw : {'encoding': '0000000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x1077', 'mask': '0xfe00707f'} +kcras16 : {'encoding': '0001010----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x14000077', 'mask': '0xfe00707f'} +kcrsa16 : {'encoding': '0001011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x16000077', 'mask': '0xfe00707f'} +kdmbb : {'encoding': '0000101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xa001077', 'mask': '0xfe00707f'} +kdmbt : {'encoding': '0001101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x1a001077', 'mask': '0xfe00707f'} +kdmtt : {'encoding': '0010101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x2a001077', 'mask': '0xfe00707f'} +kdmabb : {'encoding': '1101001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xd2001077', 'mask': '0xfe00707f'} +kdmabt : {'encoding': '1110001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xe2001077', 'mask': '0xfe00707f'} +kdmatt : {'encoding': '1111001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xf2001077', 'mask': '0xfe00707f'} +khm8 : {'encoding': '1000111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x8e000077', 'mask': '0xfe00707f'} +khmx8 : {'encoding': '1001111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x9e000077', 'mask': '0xfe00707f'} +khm16 : {'encoding': '1000011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x86000077', 'mask': '0xfe00707f'} +khmx16 : {'encoding': '1001011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x96000077', 'mask': '0xfe00707f'} +khmbb : {'encoding': '0000110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xc001077', 'mask': '0xfe00707f'} +khmbt : {'encoding': '0001110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x1c001077', 'mask': '0xfe00707f'} +khmtt : {'encoding': '0010110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x2c001077', 'mask': '0xfe00707f'} +kmabb : {'encoding': '0101101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x5a001077', 'mask': '0xfe00707f'} +kmabt : {'encoding': '0110101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x6a001077', 'mask': '0xfe00707f'} +kmatt : {'encoding': '0111101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x7a001077', 'mask': '0xfe00707f'} +kmada : {'encoding': '0100100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x48001077', 'mask': '0xfe00707f'} +kmaxda : {'encoding': '0100101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x4a001077', 'mask': '0xfe00707f'} +kmads : {'encoding': '0101110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x5c001077', 'mask': '0xfe00707f'} +kmadrs : {'encoding': '0110110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x6c001077', 'mask': '0xfe00707f'} +kmaxds : {'encoding': '0111110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x7c001077', 'mask': '0xfe00707f'} +kmar64 : {'encoding': '1001010----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x94001077', 'mask': '0xfe00707f'} +kmda : {'encoding': '0011100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x38001077', 'mask': '0xfe00707f'} +kmxda : {'encoding': '0011101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x3a001077', 'mask': '0xfe00707f'} +kmmac : {'encoding': '0110000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x60001077', 'mask': '0xfe00707f'} +kmmac_u : {'encoding': '0111000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x70001077', 'mask': '0xfe00707f'} +kmmawb : {'encoding': '0100011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x46001077', 'mask': '0xfe00707f'} +kmmawb_u : {'encoding': '0101011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x56001077', 'mask': '0xfe00707f'} +kmmawb2 : {'encoding': '1100111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xce001077', 'mask': '0xfe00707f'} +kmmawb2_u : {'encoding': '1101111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xde001077', 'mask': '0xfe00707f'} +kmmawt : {'encoding': '0110011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x66001077', 'mask': '0xfe00707f'} +kmmawt_u : {'encoding': '0111011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x76001077', 'mask': '0xfe00707f'} +kmmawt2 : {'encoding': '1110111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xee001077', 'mask': '0xfe00707f'} +kmmawt2_u : {'encoding': '1111111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xfe001077', 'mask': '0xfe00707f'} +kmmsb : {'encoding': '0100001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x42001077', 'mask': '0xfe00707f'} +kmmsb_u : {'encoding': '0101001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x52001077', 'mask': '0xfe00707f'} +kmmwb2 : {'encoding': '1000111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x8e001077', 'mask': '0xfe00707f'} +kmmwb2_u : {'encoding': '1001111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x9e001077', 'mask': '0xfe00707f'} +kmmwt2 : {'encoding': '1010111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xae001077', 'mask': '0xfe00707f'} +kmmwt2_u : {'encoding': '1011111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xbe001077', 'mask': '0xfe00707f'} +kmsda : {'encoding': '0100110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x4c001077', 'mask': '0xfe00707f'} +kmsxda : {'encoding': '0100111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x4e001077', 'mask': '0xfe00707f'} +kmsr64 : {'encoding': '1001011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x96001077', 'mask': '0xfe00707f'} +ksllw : {'encoding': '0010011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x26001077', 'mask': '0xfe00707f'} +kslliw : {'encoding': '0011011----------001-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x36001077', 'mask': '0xfe00707f'} +ksll8 : {'encoding': '0110110----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x6c000077', 'mask': '0xfe00707f'} +kslli8 : {'encoding': '011111001--------000-----1110111', 'variable_fields': ['imm3', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x7c800077', 'mask': '0xff80707f'} +ksll16 : {'encoding': '0110010----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x64000077', 'mask': '0xfe00707f'} +kslli16 : {'encoding': '01110101---------000-----1110111', 'variable_fields': ['imm4', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x75000077', 'mask': '0xff00707f'} +kslra8 : {'encoding': '0101111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x5e000077', 'mask': '0xfe00707f'} +kslra8_u : {'encoding': '0110111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x6e000077', 'mask': '0xfe00707f'} +kslra16 : {'encoding': '0101011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x56000077', 'mask': '0xfe00707f'} +kslra16_u : {'encoding': '0110011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x66000077', 'mask': '0xfe00707f'} +kslraw : {'encoding': '0110111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x6e001077', 'mask': '0xfe00707f'} +kslraw_u : {'encoding': '0111111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x7e001077', 'mask': '0xfe00707f'} +kstas16 : {'encoding': '1100010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xc4002077', 'mask': '0xfe00707f'} +kstsa16 : {'encoding': '1100011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xc6002077', 'mask': '0xfe00707f'} +ksub8 : {'encoding': '0001101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x1a000077', 'mask': '0xfe00707f'} +ksub16 : {'encoding': '0001001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x12000077', 'mask': '0xfe00707f'} +ksub64 : {'encoding': '1001001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x92001077', 'mask': '0xfe00707f'} +ksubh : {'encoding': '0000011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x6001077', 'mask': '0xfe00707f'} +ksubw : {'encoding': '0000001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x2001077', 'mask': '0xfe00707f'} +kwmmul : {'encoding': '0110001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x62001077', 'mask': '0xfe00707f'} +kwmmul_u : {'encoding': '0111001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x72001077', 'mask': '0xfe00707f'} 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'mask': '0xfe00707f'} +radd8 : {'encoding': '0000100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x8000077', 'mask': '0xfe00707f'} +radd16 : {'encoding': '0000000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x77', 'mask': '0xfe00707f'} +radd64 : {'encoding': '1000000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x80001077', 'mask': '0xfe00707f'} +raddw : {'encoding': '0010000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x20001077', 'mask': '0xfe00707f'} +rcras16 : {'encoding': '0000010----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x4000077', 'mask': '0xfe00707f'} +rcrsa16 : {'encoding': '0000011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x6000077', 'mask': '0xfe00707f'} +rstas16 : {'encoding': '1011010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xb4002077', 'mask': '0xfe00707f'} +rstsa16 : {'encoding': '1011011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xb6002077', 'mask': '0xfe00707f'} +rsub8 : {'encoding': '0000101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xa000077', 'mask': '0xfe00707f'} +rsub16 : {'encoding': '0000001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x2000077', 'mask': '0xfe00707f'} +rsub64 : {'encoding': '1000001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x82001077', 'mask': '0xfe00707f'} +rsubw : {'encoding': '0010001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x22001077', 'mask': '0xfe00707f'} +sclip8 : {'encoding': '100011000--------000-----1110111', 'variable_fields': ['imm3', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x8c000077', 'mask': '0xff80707f'} +sclip16 : {'encoding': '10000100---------000-----1110111', 'variable_fields': ['imm4', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x84000077', 'mask': '0xff00707f'} +sclip32 : {'encoding': '1110010----------000-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xe4000077', 'mask': '0xfe00707f'} +scmple8 : {'encoding': '0001111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x1e000077', 'mask': '0xfe00707f'} +scmple16 : {'encoding': '0001110----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x1c000077', 'mask': '0xfe00707f'} +scmplt8 : {'encoding': '0000111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xe000077', 'mask': '0xfe00707f'} +scmplt16 : {'encoding': '0000110----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xc000077', 'mask': '0xfe00707f'} +sll8 : {'encoding': '0101110----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x5c000077', 'mask': '0xfe00707f'} +slli8 : {'encoding': '011111000--------000-----1110111', 'variable_fields': ['imm3', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x7c000077', 'mask': '0xff80707f'} +sll16 : {'encoding': '0101010----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x54000077', 'mask': '0xfe00707f'} +slli16 : {'encoding': '01110100---------000-----1110111', 'variable_fields': ['imm4', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x74000077', 'mask': '0xff00707f'} +smal : {'encoding': '0101111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x5e001077', 'mask': '0xfe00707f'} +smalbb : {'encoding': '1000100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x88001077', 'mask': '0xfe00707f'} +smalbt : {'encoding': '1001100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x98001077', 'mask': '0xfe00707f'} +smaltt : {'encoding': '1010100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xa8001077', 'mask': '0xfe00707f'} +smalda : {'encoding': '1000110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x8c001077', 'mask': '0xfe00707f'} +smalxda : {'encoding': '1001110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x9c001077', 'mask': '0xfe00707f'} +smalds : {'encoding': '1000101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x8a001077', 'mask': '0xfe00707f'} +smaldrs : {'encoding': '1001101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x9a001077', 'mask': '0xfe00707f'} +smalxds : {'encoding': '1010101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xaa001077', 'mask': '0xfe00707f'} +smar64 : {'encoding': '1000010----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x84001077', 'mask': '0xfe00707f'} +smaqa : {'encoding': '1100100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xc8000077', 'mask': '0xfe00707f'} +smaqa_su : {'encoding': '1100101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xca000077', 'mask': '0xfe00707f'} +smax8 : {'encoding': '1000101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x8a000077', 'mask': '0xfe00707f'} +smax16 : {'encoding': '1000001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x82000077', 'mask': '0xfe00707f'} +smbb16 : {'encoding': '0000100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x8001077', 'mask': '0xfe00707f'} +smbt16 : {'encoding': '0001100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x18001077', 'mask': '0xfe00707f'} +smtt16 : {'encoding': '0010100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x28001077', 'mask': '0xfe00707f'} +smds : {'encoding': '0101100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x58001077', 'mask': '0xfe00707f'} +smdrs : {'encoding': '0110100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x68001077', 'mask': '0xfe00707f'} +smxds : {'encoding': '0111100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x78001077', 'mask': '0xfe00707f'} +smin8 : {'encoding': '1000100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x88000077', 'mask': '0xfe00707f'} +smin16 : {'encoding': '1000000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x80000077', 'mask': '0xfe00707f'} +smmul : {'encoding': '0100000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x40001077', 'mask': '0xfe00707f'} +smmul_u : {'encoding': '0101000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x50001077', 'mask': '0xfe00707f'} +smmwb : {'encoding': '0100010----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x44001077', 'mask': '0xfe00707f'} +smmwb_u : {'encoding': '0101010----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x54001077', 'mask': '0xfe00707f'} +smmwt : {'encoding': '0110010----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x64001077', 'mask': '0xfe00707f'} +smmwt_u : {'encoding': '0111010----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x74001077', 'mask': '0xfe00707f'} +smslda : {'encoding': '1010110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xac001077', 'mask': '0xfe00707f'} +smslxda : {'encoding': '1011110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xbc001077', 'mask': '0xfe00707f'} +smsr64 : {'encoding': '1000011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x86001077', 'mask': '0xfe00707f'} +smul8 : {'encoding': '1010100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xa8000077', 'mask': '0xfe00707f'} +smulx8 : {'encoding': '1010101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xaa000077', 'mask': '0xfe00707f'} +smul16 : {'encoding': '1010000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xa0000077', 'mask': '0xfe00707f'} +smulx16 : {'encoding': '1010001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xa2000077', 'mask': '0xfe00707f'} +sra_u : {'encoding': '0010010----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x24001077', 'mask': '0xfe00707f'} +srai_u : {'encoding': '110101-----------001-----1110111', 'variable_fields': ['imm6', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xd4001077', 'mask': '0xfc00707f'} +sra8 : {'encoding': '0101100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x58000077', 'mask': '0xfe00707f'} +sra8_u : {'encoding': '0110100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x68000077', 'mask': '0xfe00707f'} +srai8 : {'encoding': '011110000--------000-----1110111', 'variable_fields': ['imm3', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x78000077', 'mask': '0xff80707f'} +srai8_u : {'encoding': '011110001--------000-----1110111', 'variable_fields': ['imm3', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x78800077', 'mask': '0xff80707f'} +sra16 : {'encoding': '0101000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x50000077', 'mask': '0xfe00707f'} +sra16_u : {'encoding': '0110000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x60000077', 'mask': '0xfe00707f'} +srai16 : {'encoding': '01110000---------000-----1110111', 'variable_fields': ['imm4', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x70000077', 'mask': '0xff00707f'} +srai16_u : {'encoding': '01110001---------000-----1110111', 'variable_fields': ['imm4', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x71000077', 'mask': '0xff00707f'} +srl8 : {'encoding': '0101101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x5a000077', 'mask': '0xfe00707f'} +srl8_u : {'encoding': '0110101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x6a000077', 'mask': '0xfe00707f'} +srli8 : {'encoding': '011110100--------000-----1110111', 'variable_fields': ['imm3', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x7a000077', 'mask': '0xff80707f'} +srli8_u : {'encoding': '011110101--------000-----1110111', 'variable_fields': ['imm3', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x7a800077', 'mask': '0xff80707f'} +srl16 : {'encoding': '0101001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x52000077', 'mask': '0xfe00707f'} +srl16_u : {'encoding': '0110001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x62000077', 'mask': '0xfe00707f'} +srli16 : {'encoding': '01110010---------000-----1110111', 'variable_fields': ['imm4', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x72000077', 'mask': '0xff00707f'} +srli16_u : {'encoding': '01110011---------000-----1110111', 'variable_fields': ['imm4', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x73000077', 'mask': '0xff00707f'} +stas16 : {'encoding': '1111010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xf4002077', 'mask': '0xfe00707f'} +stsa16 : {'encoding': '1111011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xf6002077', 'mask': '0xfe00707f'} +sub8 : {'encoding': '0100101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x4a000077', 'mask': '0xfe00707f'} +sub16 : {'encoding': '0100001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x42000077', 'mask': '0xfe00707f'} +sunpkd810 : {'encoding': '101011001000-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xac800077', 'mask': '0xfff0707f'} +sunpkd820 : {'encoding': '101011001001-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xac900077', 'mask': '0xfff0707f'} +sunpkd830 : {'encoding': '101011001010-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xaca00077', 'mask': '0xfff0707f'} +sunpkd831 : {'encoding': '101011001011-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xacb00077', 'mask': '0xfff0707f'} +sunpkd832 : {'encoding': '101011010011-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xad300077', 'mask': '0xfff0707f'} +swap8 : {'encoding': '101011011000-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xad800077', 'mask': '0xfff0707f'} +uclip8 : {'encoding': '100011010--------000-----1110111', 'variable_fields': ['imm3', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x8d000077', 'mask': '0xff80707f'} +uclip16 : {'encoding': '10000101---------000-----1110111', 'variable_fields': ['imm4', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x85000077', 'mask': '0xff00707f'} +uclip32 : {'encoding': '1111010----------000-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xf4000077', 'mask': '0xfe00707f'} +ucmple8 : {'encoding': '0011111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x3e000077', 'mask': '0xfe00707f'} +ucmple16 : {'encoding': '0011110----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x3c000077', 'mask': '0xfe00707f'} +ucmplt8 : {'encoding': '0010111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x2e000077', 'mask': '0xfe00707f'} +ucmplt16 : {'encoding': '0010110----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x2c000077', 'mask': '0xfe00707f'} +ukadd8 : {'encoding': '0011100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x38000077', 'mask': '0xfe00707f'} +ukadd16 : {'encoding': '0011000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x30000077', 'mask': '0xfe00707f'} +ukadd64 : {'encoding': '1011000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xb0001077', 'mask': '0xfe00707f'} +ukaddh : {'encoding': '0001010----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x14001077', 'mask': '0xfe00707f'} +ukaddw : {'encoding': '0001000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x10001077', 'mask': '0xfe00707f'} +ukcras16 : {'encoding': '0011010----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x34000077', 'mask': '0xfe00707f'} +ukcrsa16 : {'encoding': '0011011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x36000077', 'mask': '0xfe00707f'} +ukmar64 : {'encoding': '1011010----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xb4001077', 'mask': '0xfe00707f'} +ukmsr64 : {'encoding': '1011011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xb6001077', 'mask': '0xfe00707f'} +ukstas16 : {'encoding': '1110010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xe4002077', 'mask': '0xfe00707f'} +ukstsa16 : {'encoding': '1110011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xe6002077', 'mask': '0xfe00707f'} +uksub8 : {'encoding': '0011101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x3a000077', 'mask': '0xfe00707f'} +uksub16 : {'encoding': '0011001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x32000077', 'mask': '0xfe00707f'} +uksub64 : {'encoding': '1011001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xb2001077', 'mask': '0xfe00707f'} +uksubh : {'encoding': '0001011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x16001077', 'mask': '0xfe00707f'} +uksubw : {'encoding': '0001001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x12001077', 'mask': '0xfe00707f'} +umar64 : {'encoding': '1010010----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xa4001077', 'mask': '0xfe00707f'} +umaqa : {'encoding': '1100110----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xcc000077', 'mask': '0xfe00707f'} +umax8 : {'encoding': '1001101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x9a000077', 'mask': '0xfe00707f'} +umax16 : {'encoding': '1001001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x92000077', 'mask': '0xfe00707f'} +umin8 : {'encoding': '1001100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x98000077', 'mask': '0xfe00707f'} +umin16 : {'encoding': '1001000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x90000077', 'mask': '0xfe00707f'} +umsr64 : {'encoding': '1010011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xa6001077', 'mask': '0xfe00707f'} +umul8 : {'encoding': '1011100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xb8000077', 'mask': '0xfe00707f'} +umulx8 : {'encoding': '1011101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xba000077', 'mask': '0xfe00707f'} +umul16 : {'encoding': '1011000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xb0000077', 'mask': '0xfe00707f'} +umulx16 : {'encoding': '1011001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xb2000077', 'mask': '0xfe00707f'} +uradd8 : {'encoding': '0010100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x28000077', 'mask': '0xfe00707f'} +uradd16 : {'encoding': '0010000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x20000077', 'mask': '0xfe00707f'} +uradd64 : {'encoding': '1010000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xa0001077', 'mask': '0xfe00707f'} +uraddw : {'encoding': '0011000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x30001077', 'mask': '0xfe00707f'} +urcras16 : {'encoding': '0010010----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x24000077', 'mask': '0xfe00707f'} +urcrsa16 : {'encoding': '0010011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x26000077', 'mask': '0xfe00707f'} +urstas16 : {'encoding': '1101010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xd4002077', 'mask': '0xfe00707f'} +urstsa16 : {'encoding': '1101011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xd6002077', 'mask': '0xfe00707f'} +ursub8 : {'encoding': '0010101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x2a000077', 'mask': '0xfe00707f'} +ursub16 : {'encoding': '0010001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x22000077', 'mask': '0xfe00707f'} +ursub64 : {'encoding': '1010001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xa2001077', 'mask': '0xfe00707f'} +ursubw : {'encoding': '0011001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x32001077', 'mask': '0xfe00707f'} +wexti : {'encoding': '1101111----------000-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xde000077', 'mask': '0xfe00707f'} +wext : {'encoding': '1100111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xce000077', 'mask': '0xfe00707f'} +zunpkd810 : {'encoding': '101011001100-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xacc00077', 'mask': '0xfff0707f'} +zunpkd820 : {'encoding': '101011001101-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xacd00077', 'mask': '0xfff0707f'} +zunpkd830 : {'encoding': '101011001110-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xace00077', 'mask': '0xfff0707f'} +zunpkd831 : {'encoding': '101011001111-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xacf00077', 'mask': '0xfff0707f'} +zunpkd832 : {'encoding': '101011010111-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xad700077', 'mask': '0xfff0707f'} +add64 : {'encoding': '1100000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv32_p'], 'match': '0xc0001077', 'mask': '0xfe00707f'} +sub64 : {'encoding': '1100001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv32_p'], 'match': '0xc2001077', 'mask': '0xfe00707f'} +sha512sum0 : {'encoding': '000100000100-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zknh'], 'match': '0x10401013', 'mask': '0xfff0707f'} +sha512sum1 : {'encoding': '000100000101-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zknh'], 'match': '0x10501013', 'mask': '0xfff0707f'} +sha512sig0 : {'encoding': '000100000110-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zknh'], 'match': '0x10601013', 'mask': '0xfff0707f'} +sha512sig1 : {'encoding': '000100000111-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zknh'], 'match': '0x10701013', 'mask': '0xfff0707f'} +fcvt_l_d : {'encoding': '110000100010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_d'], 'match': '0xc2200053', 'mask': '0xfff0007f'} +fcvt_lu_d : {'encoding': '110000100011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_d'], 'match': '0xc2300053', 'mask': '0xfff0007f'} +fmv_x_d : {'encoding': '111000100000-----000-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_d'], 'match': '0xe2000053', 'mask': '0xfff0707f'} +fcvt_d_l : {'encoding': '110100100010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_d'], 'match': '0xd2200053', 'mask': '0xfff0007f'} +fcvt_d_lu : {'encoding': '110100100011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_d'], 'match': '0xd2300053', 'mask': '0xfff0007f'} +fmv_d_x : {'encoding': '111100100000-----000-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_d'], 'match': '0xf2000053', 'mask': '0xfff0707f'} +fld : {'encoding': '-----------------011-----0000111', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_d'], 'match': '0x3007', 'mask': '0x707f'} +fsd : {'encoding': '-----------------011-----0100111', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv_d'], 'match': '0x3027', 'mask': '0x707f'} +fmadd_d : {'encoding': '-----01------------------1000011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_d'], 'match': '0x2000043', 'mask': '0x600007f'} +fmsub_d : {'encoding': '-----01------------------1000111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_d'], 'match': '0x2000047', 'mask': '0x600007f'} +fnmsub_d : {'encoding': '-----01------------------1001011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_d'], 'match': '0x200004b', 'mask': '0x600007f'} +fnmadd_d : {'encoding': '-----01------------------1001111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_d'], 'match': '0x200004f', 'mask': '0x600007f'} +fadd_d : {'encoding': '0000001------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_d'], 'match': '0x2000053', 'mask': '0xfe00007f'} +fsub_d : {'encoding': '0000101------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_d'], 'match': '0xa000053', 'mask': '0xfe00007f'} +fmul_d : {'encoding': '0001001------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_d'], 'match': '0x12000053', 'mask': '0xfe00007f'} +fdiv_d : {'encoding': '0001101------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_d'], 'match': '0x1a000053', 'mask': '0xfe00007f'} +fsqrt_d : {'encoding': '010110100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d'], 'match': '0x5a000053', 'mask': '0xfff0007f'} +fsgnj_d : {'encoding': '0010001----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0x22000053', 'mask': '0xfe00707f'} +fsgnjn_d : {'encoding': '0010001----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0x22001053', 'mask': '0xfe00707f'} +fsgnjx_d : {'encoding': '0010001----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0x22002053', 'mask': '0xfe00707f'} +fmin_d : {'encoding': '0010101----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0x2a000053', 'mask': '0xfe00707f'} +fmax_d : {'encoding': '0010101----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0x2a001053', 'mask': '0xfe00707f'} +fcvt_s_d : {'encoding': '010000000001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d'], 'match': '0x40100053', 'mask': '0xfff0007f'} +fcvt_d_s : {'encoding': '010000100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d'], 'match': '0x42000053', 'mask': '0xfff0007f'} +feq_d : {'encoding': '1010001----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0xa2002053', 'mask': '0xfe00707f'} +flt_d : {'encoding': '1010001----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0xa2001053', 'mask': '0xfe00707f'} +fle_d : {'encoding': '1010001----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0xa2000053', 'mask': '0xfe00707f'} +fclass_d : {'encoding': '111000100000-----001-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_d'], 'match': '0xe2001053', 'mask': '0xfff0707f'} +fcvt_w_d : {'encoding': '110000100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d'], 'match': '0xc2000053', 'mask': '0xfff0007f'} +fcvt_wu_d : {'encoding': '110000100001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d'], 'match': '0xc2100053', 'mask': '0xfff0007f'} +fcvt_d_w : {'encoding': '110100100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d'], 'match': '0xd2000053', 'mask': '0xfff0007f'} +fcvt_d_wu : {'encoding': '110100100001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d'], 'match': '0xd2100053', 'mask': '0xfff0007f'} +flh : {'encoding': '-----------------001-----0000111', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_zfh'], 'match': '0x1007', 'mask': '0x707f'} +fsh : {'encoding': '-----------------001-----0100111', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv_zfh'], 'match': '0x1027', 'mask': '0x707f'} +fmadd_h : {'encoding': '-----10------------------1000011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_zfh'], 'match': '0x4000043', 'mask': '0x600007f'} +fmsub_h : {'encoding': '-----10------------------1000111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_zfh'], 'match': '0x4000047', 'mask': '0x600007f'} +fnmsub_h : {'encoding': '-----10------------------1001011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_zfh'], 'match': '0x400004b', 'mask': '0x600007f'} +fnmadd_h : {'encoding': '-----10------------------1001111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_zfh'], 'match': '0x400004f', 'mask': '0x600007f'} +fadd_h : {'encoding': '0000010------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_zfh'], 'match': '0x4000053', 'mask': '0xfe00007f'} +fsub_h : {'encoding': '0000110------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_zfh'], 'match': '0xc000053', 'mask': '0xfe00007f'} +fmul_h : {'encoding': '0001010------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_zfh'], 'match': '0x14000053', 'mask': '0xfe00007f'} +fdiv_h : {'encoding': '0001110------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_zfh'], 'match': '0x1c000053', 'mask': '0xfe00007f'} +fsqrt_h : {'encoding': '010111000000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_zfh'], 'match': '0x5c000053', 'mask': '0xfff0007f'} +fsgnj_h : {'encoding': '0010010----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0x24000053', 'mask': '0xfe00707f'} +fsgnjn_h : {'encoding': '0010010----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0x24001053', 'mask': '0xfe00707f'} +fsgnjx_h : {'encoding': '0010010----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0x24002053', 'mask': '0xfe00707f'} +fmin_h : {'encoding': '0010110----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0x2c000053', 'mask': '0xfe00707f'} +fmax_h : {'encoding': '0010110----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0x2c001053', 'mask': '0xfe00707f'} +fcvt_s_h : {'encoding': '010000000010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_zfh'], 'match': '0x40200053', 'mask': '0xfff0007f'} +fcvt_h_s : {'encoding': '010001000000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_zfh'], 'match': '0x44000053', 'mask': '0xfff0007f'} +feq_h : {'encoding': '1010010----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0xa4002053', 'mask': '0xfe00707f'} +flt_h : {'encoding': '1010010----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0xa4001053', 'mask': '0xfe00707f'} +fle_h : {'encoding': '1010010----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0xa4000053', 'mask': '0xfe00707f'} +fclass_h : {'encoding': '111001000000-----001-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zfh'], 'match': '0xe4001053', 'mask': '0xfff0707f'} +fcvt_w_h : {'encoding': '110001000000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_zfh'], 'match': '0xc4000053', 'mask': '0xfff0007f'} +fcvt_wu_h : {'encoding': '110001000001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_zfh'], 'match': '0xc4100053', 'mask': '0xfff0007f'} +fmv_x_h : {'encoding': '111001000000-----000-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zfh'], 'match': '0xe4000053', 'mask': '0xfff0707f'} +fcvt_h_w : {'encoding': '110101000000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_zfh'], 'match': '0xd4000053', 'mask': '0xfff0007f'} +fcvt_h_wu : {'encoding': '110101000001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_zfh'], 'match': '0xd4100053', 'mask': '0xfff0007f'} +fmv_h_x : {'encoding': '111101000000-----000-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zfh'], 'match': '0xf4000053', 'mask': '0xfff0707f'} +fcvt_d_h : {'encoding': '010000100010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d_zfh'], 'match': '0x42200053', 'mask': '0xfff0007f'} +fcvt_h_d : {'encoding': '010001000001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d_zfh'], 'match': '0x44100053', 'mask': '0xfff0007f'} +lr_d : {'encoding': '00010--00000-----011-----0101111', 'variable_fields': ['rd', 'rs1', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x1000302f', 'mask': '0xf9f0707f'} +sc_d : {'encoding': '00011------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x1800302f', 'mask': '0xf800707f'} +amoswap_d : {'encoding': '00001------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x800302f', 'mask': '0xf800707f'} +amoadd_d : {'encoding': '00000------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x302f', 'mask': '0xf800707f'} +amoxor_d : {'encoding': '00100------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x2000302f', 'mask': '0xf800707f'} +amoand_d : {'encoding': '01100------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x6000302f', 'mask': '0xf800707f'} +amoor_d : {'encoding': '01000------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x4000302f', 'mask': '0xf800707f'} +amomin_d : {'encoding': '10000------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x8000302f', 'mask': '0xf800707f'} +amomax_d : {'encoding': '10100------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0xa000302f', 'mask': '0xf800707f'} +amominu_d : {'encoding': '11000------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0xc000302f', 'mask': '0xf800707f'} +amomaxu_d : {'encoding': '11100------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0xe000302f', 'mask': '0xf800707f'} +bclr : {'encoding': '0100100----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbs'], 'match': '0x48001033', 'mask': '0xfe00707f'} +bext : {'encoding': '0100100----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbs'], 'match': '0x48005033', 'mask': '0xfe00707f'} +binv : {'encoding': '0110100----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbs'], 'match': '0x68001033', 'mask': '0xfe00707f'} +bset : {'encoding': '0010100----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbs'], 'match': '0x28001033', 'mask': '0xfe00707f'} +sm3p0 : {'encoding': '000100001000-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zksh'], 'match': '0x10801013', 'mask': '0xfff0707f'} +sm3p1 : {'encoding': '000100001001-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zksh'], 'match': '0x10901013', 'mask': '0xfff0707f'} +sinval_vma : {'encoding': '0001011----------000000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_svinval'], 'match': '0x16000073', 'mask': '0xfe007fff'} +sfence_w_inval : {'encoding': '00011000000000000000000001110011', 'variable_fields': [], 'extension': ['rv_svinval'], 'match': '0x18000073', 'mask': '0xffffffff'} +sfence_inval_ir : {'encoding': '00011000000100000000000001110011', 'variable_fields': [], 'extension': ['rv_svinval'], 'match': '0x18100073', 'mask': '0xffffffff'} +hinval_vvma : {'encoding': '0010011----------000000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_svinval'], 'match': '0x26000073', 'mask': '0xfe007fff'} +hinval_gvma : {'encoding': '0110011----------000000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_svinval'], 'match': '0x66000073', 'mask': '0xfe007fff'} +slow : {'encoding': '0010000----------001-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_b'], 'match': '0x2000103b', 'mask': '0xfe00707f'} +srow : {'encoding': '0010000----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_b'], 'match': '0x2000503b', 'mask': '0xfe00707f'} +sloiw : {'encoding': '0010000----------001-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_b'], 'match': '0x2000101b', 'mask': '0xfe00707f'} +sroiw : {'encoding': '0010000----------101-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_b'], 'match': '0x2000501b', 'mask': '0xfe00707f'} +clzw : {'encoding': '011000000000-----001-----0011011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zbb'], 'match': '0x6000101b', 'mask': '0xfff0707f'} +ctzw : {'encoding': '011000000001-----001-----0011011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zbb'], 'match': '0x6010101b', 'mask': '0xfff0707f'} +cpopw : {'encoding': '011000000010-----001-----0011011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zbb'], 'match': '0x6020101b', 'mask': '0xfff0707f'} +rolw : {'encoding': '0110000----------001-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbb'], 'match': '0x6000103b', 'mask': '0xfe00707f'} +rorw : {'encoding': '0110000----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbb'], 'match': '0x6000503b', 'mask': '0xfe00707f'} +roriw : {'encoding': '0110000----------101-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_zbb'], 'match': '0x6000501b', 'mask': '0xfe00707f'} +rori : {'encoding': '011000-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zbb'], 'match': '0x60005013', 'mask': '0xfc00707f'} +add_uw : {'encoding': '0000100----------000-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zba'], 'match': '0x800003b', 'mask': '0xfe00707f'} +sh1add_uw : {'encoding': '0010000----------010-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zba'], 'match': '0x2000203b', 'mask': '0xfe00707f'} +sh2add_uw : {'encoding': '0010000----------100-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zba'], 'match': '0x2000403b', 'mask': '0xfe00707f'} +sh3add_uw : {'encoding': '0010000----------110-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zba'], 'match': '0x2000603b', 'mask': '0xfe00707f'} +slli_uw : {'encoding': '000010-----------001-----0011011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zba'], 'match': '0x800101b', 'mask': '0xfc00707f'} +add32 : {'encoding': '0100000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x40002077', 'mask': '0xfe00707f'} +radd32 : {'encoding': '0000000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x2077', 'mask': '0xfe00707f'} +uradd32 : {'encoding': '0010000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x20002077', 'mask': '0xfe00707f'} +kadd32 : {'encoding': '0001000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x10002077', 'mask': '0xfe00707f'} +ukadd32 : {'encoding': '0011000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x30002077', 'mask': '0xfe00707f'} +sub32 : {'encoding': '0100001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x42002077', 'mask': '0xfe00707f'} +rsub32 : {'encoding': '0000001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x2002077', 'mask': '0xfe00707f'} +ursub32 : {'encoding': '0010001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x22002077', 'mask': '0xfe00707f'} +ksub32 : {'encoding': '0001001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x12002077', 'mask': '0xfe00707f'} +uksub32 : {'encoding': '0011001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x32002077', 'mask': '0xfe00707f'} +cras32 : {'encoding': '0100010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x44002077', 'mask': '0xfe00707f'} +rcras32 : {'encoding': '0000010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x4002077', 'mask': '0xfe00707f'} +urcras32 : {'encoding': '0010010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x24002077', 'mask': '0xfe00707f'} +kcras32 : {'encoding': '0001010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x14002077', 'mask': '0xfe00707f'} +ukcras32 : {'encoding': '0011010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x34002077', 'mask': '0xfe00707f'} +crsa32 : {'encoding': '0100011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x46002077', 'mask': '0xfe00707f'} +rcrsa32 : {'encoding': '0000011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x6002077', 'mask': '0xfe00707f'} +urcrsa32 : {'encoding': '0010011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x26002077', 'mask': '0xfe00707f'} +kcrsa32 : {'encoding': '0001011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x16002077', 'mask': '0xfe00707f'} +ukcrsa32 : {'encoding': '0011011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x36002077', 'mask': '0xfe00707f'} +stas32 : {'encoding': '1111000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xf0002077', 'mask': '0xfe00707f'} +rstas32 : {'encoding': '1011000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xb0002077', 'mask': '0xfe00707f'} +urstas32 : {'encoding': '1101000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xd0002077', 'mask': '0xfe00707f'} +kstas32 : {'encoding': '1100000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xc0002077', 'mask': '0xfe00707f'} +ukstas32 : {'encoding': '1110000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xe0002077', 'mask': '0xfe00707f'} +stsa32 : {'encoding': '1111001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xf2002077', 'mask': '0xfe00707f'} +rstsa32 : {'encoding': '1011001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xb2002077', 'mask': '0xfe00707f'} +urstsa32 : {'encoding': '1101001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xd2002077', 'mask': '0xfe00707f'} +kstsa32 : {'encoding': '1100001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xc2002077', 'mask': '0xfe00707f'} +ukstsa32 : {'encoding': '1110001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xe2002077', 'mask': '0xfe00707f'} +sra32 : {'encoding': '0101000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x50002077', 'mask': '0xfe00707f'} +srai32 : {'encoding': '0111000----------010-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x70002077', 'mask': '0xfe00707f'} +sra32_u : {'encoding': '0110000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x60002077', 'mask': '0xfe00707f'} +srai32_u : {'encoding': '1000000----------010-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x80002077', 'mask': '0xfe00707f'} +srl32 : {'encoding': '0101001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x52002077', 'mask': '0xfe00707f'} +srli32 : {'encoding': '0111001----------010-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x72002077', 'mask': '0xfe00707f'} +srl32_u : {'encoding': '0110001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x62002077', 'mask': '0xfe00707f'} +srli32_u : {'encoding': '1000001----------010-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x82002077', 'mask': '0xfe00707f'} +sll32 : {'encoding': '0101010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x54002077', 'mask': '0xfe00707f'} +slli32 : {'encoding': '0111010----------010-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x74002077', 'mask': '0xfe00707f'} +ksll32 : {'encoding': '0110010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x64002077', 'mask': '0xfe00707f'} +kslli32 : {'encoding': '1000010----------010-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x84002077', 'mask': '0xfe00707f'} +kslra32 : {'encoding': '0101011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x56002077', 'mask': '0xfe00707f'} +kslra32_u : {'encoding': '0110011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x66002077', 'mask': '0xfe00707f'} +smin32 : {'encoding': '1001000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x90002077', 'mask': '0xfe00707f'} +umin32 : {'encoding': '1010000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xa0002077', 'mask': '0xfe00707f'} +smax32 : {'encoding': '1001001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x92002077', 'mask': '0xfe00707f'} +umax32 : {'encoding': '1010001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xa2002077', 'mask': '0xfe00707f'} +kabs32 : {'encoding': '101011010010-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xad200077', 'mask': '0xfff0707f'} +khmbb16 : {'encoding': '1101110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xdc001077', 'mask': '0xfe00707f'} +khmbt16 : {'encoding': '1110110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xec001077', 'mask': '0xfe00707f'} +khmtt16 : {'encoding': '1111110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xfc001077', 'mask': '0xfe00707f'} +kdmbb16 : {'encoding': '1101101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xda001077', 'mask': '0xfe00707f'} +kdmbt16 : {'encoding': '1110101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xea001077', 'mask': '0xfe00707f'} +kdmtt16 : {'encoding': '1111101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xfa001077', 'mask': '0xfe00707f'} +kdmabb16 : {'encoding': '1101100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xd8001077', 'mask': '0xfe00707f'} +kdmabt16 : {'encoding': '1110100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xe8001077', 'mask': '0xfe00707f'} +kdmatt16 : {'encoding': '1111100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xf8001077', 'mask': '0xfe00707f'} +smbt32 : {'encoding': '0001100----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x18002077', 'mask': '0xfe00707f'} +smtt32 : {'encoding': '0010100----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x28002077', 'mask': '0xfe00707f'} +kmabb32 : {'encoding': '0101101----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x5a002077', 'mask': '0xfe00707f'} +kmabt32 : {'encoding': '0110101----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x6a002077', 'mask': '0xfe00707f'} +kmatt32 : {'encoding': '0111101----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x7a002077', 'mask': '0xfe00707f'} +kmda32 : {'encoding': '0011100----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x38002077', 'mask': '0xfe00707f'} +kmxda32 : {'encoding': '0011101----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x3a002077', 'mask': '0xfe00707f'} +kmaxda32 : {'encoding': '0100101----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x4a002077', 'mask': '0xfe00707f'} +kmads32 : {'encoding': '0101110----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x5c002077', 'mask': '0xfe00707f'} +kmadrs32 : {'encoding': '0110110----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x6c002077', 'mask': '0xfe00707f'} +kmaxds32 : {'encoding': '0111110----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x7c002077', 'mask': '0xfe00707f'} +kmsda32 : {'encoding': '0100110----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x4c002077', 'mask': '0xfe00707f'} +kmsxda32 : {'encoding': '0100111----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x4e002077', 'mask': '0xfe00707f'} +smds32 : {'encoding': '0101100----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x58002077', 'mask': '0xfe00707f'} +smdrs32 : {'encoding': '0110100----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x68002077', 'mask': '0xfe00707f'} +smxds32 : {'encoding': '0111100----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x78002077', 'mask': '0xfe00707f'} +sraiw_u : {'encoding': '0011010----------001-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x34001077', 'mask': '0xfe00707f'} +pkbb32 : {'encoding': '0000111----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xe002077', 'mask': '0xfe00707f'} +pkbt32 : {'encoding': '0001111----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x1e002077', 'mask': '0xfe00707f'} +pktt32 : {'encoding': '0010111----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x2e002077', 'mask': '0xfe00707f'} +pktb32 : {'encoding': '0011111----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x3e002077', 'mask': '0xfe00707f'} +mulw : {'encoding': '0000001----------000-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_m'], 'match': '0x200003b', 'mask': '0xfe00707f'} +divw : {'encoding': '0000001----------100-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_m'], 'match': '0x200403b', 'mask': '0xfe00707f'} +divuw : {'encoding': '0000001----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_m'], 'match': '0x200503b', 'mask': '0xfe00707f'} +remw : {'encoding': '0000001----------110-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_m'], 'match': '0x200603b', 'mask': '0xfe00707f'} +remuw : {'encoding': '0000001----------111-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_m'], 'match': '0x200703b', 'mask': '0xfe00707f'} +sh1add : {'encoding': '0010000----------010-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zba'], 'match': '0x20002033', 'mask': '0xfe00707f'} +sh2add : {'encoding': '0010000----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zba'], 'match': '0x20004033', 'mask': '0xfe00707f'} +sh3add : {'encoding': '0010000----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zba'], 'match': '0x20006033', 'mask': '0xfe00707f'} +bmatflip : {'encoding': '011000000011-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zbm'], 'match': '0x60301013', 'mask': '0xfff0707f'} +bmator : {'encoding': '0000100----------011-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbm'], 'match': '0x8003033', 'mask': '0xfe00707f'} +bmatxor : {'encoding': '0100100----------011-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbm'], 'match': '0x48003033', 'mask': '0xfe00707f'} +vsetivli : {'encoding': '11---------------111-----1010111', 'variable_fields': ['zimm10', 'zimm', 'rd'], 'extension': ['rv_v'], 'match': '0xc0007057', 'mask': '0xc000707f'} +vsetvli : {'encoding': '0----------------111-----1010111', 'variable_fields': ['zimm11', 'rs1', 'rd'], 'extension': ['rv_v'], 'match': '0x7057', 'mask': '0x8000707f'} +vsetvl : {'encoding': '1000000----------111-----1010111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_v'], 'match': '0x80007057', 'mask': '0xfe00707f'} +vlm_v : {'encoding': '000000101011-----000-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2b00007', 'mask': '0xfff0707f'} +vsm_v : {'encoding': '000000101011-----000-----0100111', 'variable_fields': ['rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x2b00027', 'mask': '0xfff0707f'} +vle8_v : {'encoding': '---000-00000-----000-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x7', 'mask': '0x1df0707f'} +vle16_v : {'encoding': '---000-00000-----101-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5007', 'mask': '0x1df0707f'} +vle32_v : {'encoding': '---000-00000-----110-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6007', 'mask': '0x1df0707f'} +vle64_v : {'encoding': '---000-00000-----111-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x7007', 'mask': '0x1df0707f'} +vle128_v : {'encoding': '---100-00000-----000-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10000007', 'mask': '0x1df0707f'} +vle256_v : {'encoding': '---100-00000-----101-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10005007', 'mask': '0x1df0707f'} +vle512_v : {'encoding': '---100-00000-----110-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10006007', 'mask': '0x1df0707f'} +vle1024_v : {'encoding': '---100-00000-----111-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10007007', 'mask': '0x1df0707f'} +vse8_v : {'encoding': '---000-00000-----000-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x27', 'mask': '0x1df0707f'} +vse16_v : {'encoding': '---000-00000-----101-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x5027', 'mask': '0x1df0707f'} +vse32_v : {'encoding': '---000-00000-----110-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x6027', 'mask': '0x1df0707f'} +vse64_v : {'encoding': '---000-00000-----111-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x7027', 'mask': '0x1df0707f'} +vse128_v : {'encoding': '---100-00000-----000-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x10000027', 'mask': '0x1df0707f'} +vse256_v : {'encoding': '---100-00000-----101-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x10005027', 'mask': '0x1df0707f'} +vse512_v : {'encoding': '---100-00000-----110-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x10006027', 'mask': '0x1df0707f'} +vse1024_v : {'encoding': '---100-00000-----111-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x10007027', 'mask': '0x1df0707f'} +vluxei8_v : {'encoding': '---001-----------000-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4000007', 'mask': '0x1c00707f'} +vluxei16_v : {'encoding': '---001-----------101-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4005007', 'mask': '0x1c00707f'} +vluxei32_v : {'encoding': '---001-----------110-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4006007', 'mask': '0x1c00707f'} +vluxei64_v : {'encoding': '---001-----------111-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4007007', 'mask': '0x1c00707f'} +vluxei128_v : {'encoding': '---101-----------000-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14000007', 'mask': '0x1c00707f'} +vluxei256_v : {'encoding': '---101-----------101-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14005007', 'mask': '0x1c00707f'} +vluxei512_v : {'encoding': '---101-----------110-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14006007', 'mask': '0x1c00707f'} +vluxei1024_v : {'encoding': '---101-----------111-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14007007', 'mask': '0x1c00707f'} +vsuxei8_v : {'encoding': '---001-----------000-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x4000027', 'mask': '0x1c00707f'} +vsuxei16_v : {'encoding': '---001-----------101-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x4005027', 'mask': '0x1c00707f'} +vsuxei32_v : {'encoding': '---001-----------110-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x4006027', 'mask': '0x1c00707f'} +vsuxei64_v : {'encoding': '---001-----------111-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x4007027', 'mask': '0x1c00707f'} +vsuxei128_v : {'encoding': '---101-----------000-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x14000027', 'mask': '0x1c00707f'} +vsuxei256_v : {'encoding': '---101-----------101-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x14005027', 'mask': '0x1c00707f'} +vsuxei512_v : {'encoding': '---101-----------110-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x14006027', 'mask': '0x1c00707f'} +vsuxei1024_v : {'encoding': '---101-----------111-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x14007027', 'mask': '0x1c00707f'} +vlse8_v : {'encoding': '---010-----------000-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8000007', 'mask': '0x1c00707f'} +vlse16_v : {'encoding': '---010-----------101-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8005007', 'mask': '0x1c00707f'} +vlse32_v : {'encoding': '---010-----------110-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8006007', 'mask': '0x1c00707f'} +vlse64_v : {'encoding': '---010-----------111-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8007007', 'mask': '0x1c00707f'} +vlse128_v : {'encoding': '---110-----------000-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18000007', 'mask': '0x1c00707f'} +vlse256_v : {'encoding': '---110-----------101-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18005007', 'mask': '0x1c00707f'} +vlse512_v : {'encoding': '---110-----------110-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18006007', 'mask': '0x1c00707f'} +vlse1024_v : {'encoding': '---110-----------111-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18007007', 'mask': '0x1c00707f'} +vsse8_v : {'encoding': '---010-----------000-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x8000027', 'mask': '0x1c00707f'} +vsse16_v : {'encoding': '---010-----------101-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x8005027', 'mask': '0x1c00707f'} +vsse32_v : {'encoding': '---010-----------110-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x8006027', 'mask': '0x1c00707f'} +vsse64_v : {'encoding': '---010-----------111-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x8007027', 'mask': '0x1c00707f'} +vsse128_v : {'encoding': '---110-----------000-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x18000027', 'mask': '0x1c00707f'} +vsse256_v : {'encoding': '---110-----------101-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x18005027', 'mask': '0x1c00707f'} +vsse512_v : {'encoding': '---110-----------110-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x18006027', 'mask': '0x1c00707f'} +vsse1024_v : {'encoding': '---110-----------111-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x18007027', 'mask': '0x1c00707f'} +vloxei8_v : {'encoding': '---011-----------000-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc000007', 'mask': '0x1c00707f'} +vloxei16_v : {'encoding': '---011-----------101-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc005007', 'mask': '0x1c00707f'} +vloxei32_v : {'encoding': '---011-----------110-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc006007', 'mask': '0x1c00707f'} +vloxei64_v : {'encoding': '---011-----------111-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc007007', 'mask': '0x1c00707f'} +vloxei128_v : {'encoding': '---111-----------000-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c000007', 'mask': '0x1c00707f'} +vloxei256_v : {'encoding': '---111-----------101-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c005007', 'mask': '0x1c00707f'} +vloxei512_v : {'encoding': '---111-----------110-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c006007', 'mask': '0x1c00707f'} +vloxei1024_v : {'encoding': '---111-----------111-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c007007', 'mask': '0x1c00707f'} +vsoxei8_v : {'encoding': '---011-----------000-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0xc000027', 'mask': '0x1c00707f'} +vsoxei16_v : {'encoding': '---011-----------101-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0xc005027', 'mask': '0x1c00707f'} +vsoxei32_v : {'encoding': '---011-----------110-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0xc006027', 'mask': '0x1c00707f'} +vsoxei64_v : {'encoding': '---011-----------111-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0xc007027', 'mask': '0x1c00707f'} +vsoxei128_v : {'encoding': '---111-----------000-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x1c000027', 'mask': '0x1c00707f'} +vsoxei256_v : {'encoding': '---111-----------101-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x1c005027', 'mask': '0x1c00707f'} +vsoxei512_v : {'encoding': '---111-----------110-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x1c006027', 'mask': '0x1c00707f'} +vsoxei1024_v : {'encoding': '---111-----------111-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x1c007027', 'mask': '0x1c00707f'} +vle8ff_v : {'encoding': '---000-10000-----000-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1000007', 'mask': '0x1df0707f'} +vle16ff_v : {'encoding': '---000-10000-----101-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1005007', 'mask': '0x1df0707f'} +vle32ff_v : {'encoding': '---000-10000-----110-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1006007', 'mask': '0x1df0707f'} +vle64ff_v : {'encoding': '---000-10000-----111-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1007007', 'mask': '0x1df0707f'} +vle128ff_v : {'encoding': '---100-10000-----000-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x11000007', 'mask': '0x1df0707f'} +vle256ff_v : {'encoding': '---100-10000-----101-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x11005007', 'mask': '0x1df0707f'} +vle512ff_v : {'encoding': '---100-10000-----110-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x11006007', 'mask': '0x1df0707f'} +vle1024ff_v : {'encoding': '---100-10000-----111-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x11007007', 'mask': '0x1df0707f'} +vl1re8_v : {'encoding': '000000101000-----000-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2800007', 'mask': '0xfff0707f'} +vl1re16_v : {'encoding': '000000101000-----101-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2805007', 'mask': '0xfff0707f'} +vl1re32_v : {'encoding': '000000101000-----110-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2806007', 'mask': '0xfff0707f'} +vl1re64_v : {'encoding': '000000101000-----111-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2807007', 'mask': '0xfff0707f'} +vl2re8_v : {'encoding': '001000101000-----000-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x22800007', 'mask': '0xfff0707f'} +vl2re16_v : {'encoding': '001000101000-----101-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x22805007', 'mask': '0xfff0707f'} +vl2re32_v : {'encoding': '001000101000-----110-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x22806007', 'mask': '0xfff0707f'} +vl2re64_v : {'encoding': '001000101000-----111-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x22807007', 'mask': '0xfff0707f'} +vl4re8_v : {'encoding': '011000101000-----000-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x62800007', 'mask': '0xfff0707f'} +vl4re16_v : {'encoding': '011000101000-----101-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x62805007', 'mask': '0xfff0707f'} +vl4re32_v : {'encoding': '011000101000-----110-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x62806007', 'mask': '0xfff0707f'} +vl4re64_v : {'encoding': '011000101000-----111-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x62807007', 'mask': '0xfff0707f'} +vl8re8_v : {'encoding': '111000101000-----000-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe2800007', 'mask': '0xfff0707f'} +vl8re16_v : {'encoding': '111000101000-----101-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe2805007', 'mask': '0xfff0707f'} +vl8re32_v : {'encoding': '111000101000-----110-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe2806007', 'mask': '0xfff0707f'} +vl8re64_v : {'encoding': '111000101000-----111-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe2807007', 'mask': '0xfff0707f'} +vs1r_v : {'encoding': '000000101000-----000-----0100111', 'variable_fields': ['rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x2800027', 'mask': '0xfff0707f'} +vs2r_v : {'encoding': '001000101000-----000-----0100111', 'variable_fields': ['rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x22800027', 'mask': '0xfff0707f'} +vs4r_v : {'encoding': '011000101000-----000-----0100111', 'variable_fields': ['rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x62800027', 'mask': '0xfff0707f'} +vs8r_v : {'encoding': '111000101000-----000-----0100111', 'variable_fields': ['rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0xe2800027', 'mask': '0xfff0707f'} +vfadd_vf : {'encoding': '000000-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5057', 'mask': '0xfc00707f'} +vfsub_vf : {'encoding': '000010-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8005057', 'mask': '0xfc00707f'} +vfmin_vf : {'encoding': '000100-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10005057', 'mask': '0xfc00707f'} +vfmax_vf : {'encoding': '000110-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18005057', 'mask': '0xfc00707f'} +vfsgnj_vf : {'encoding': '001000-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x20005057', 'mask': '0xfc00707f'} +vfsgnjn_vf : {'encoding': '001001-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x24005057', 'mask': '0xfc00707f'} +vfsgnjx_vf : {'encoding': '001010-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x28005057', 'mask': '0xfc00707f'} +vfslide1up_vf : {'encoding': '001110-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x38005057', 'mask': '0xfc00707f'} +vfslide1down_vf : {'encoding': '001111-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x3c005057', 'mask': '0xfc00707f'} +vfmv_s_f : {'encoding': '010000100000-----101-----1010111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x42005057', 'mask': '0xfff0707f'} +vfmerge_vfm : {'encoding': '0101110----------101-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5c005057', 'mask': '0xfe00707f'} +vfmv_v_f : {'encoding': '010111100000-----101-----1010111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5e005057', 'mask': '0xfff0707f'} +vmfeq_vf : {'encoding': '011000-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x60005057', 'mask': '0xfc00707f'} +vmfle_vf : {'encoding': '011001-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x64005057', 'mask': '0xfc00707f'} +vmflt_vf : {'encoding': '011011-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6c005057', 'mask': '0xfc00707f'} +vmfne_vf : {'encoding': '011100-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x70005057', 'mask': '0xfc00707f'} +vmfgt_vf : {'encoding': '011101-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x74005057', 'mask': '0xfc00707f'} +vmfge_vf : {'encoding': '011111-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x7c005057', 'mask': '0xfc00707f'} +vfdiv_vf : {'encoding': '100000-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x80005057', 'mask': '0xfc00707f'} +vfrdiv_vf : {'encoding': '100001-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x84005057', 'mask': '0xfc00707f'} +vfmul_vf : {'encoding': '100100-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x90005057', 'mask': '0xfc00707f'} +vfrsub_vf : {'encoding': '100111-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x9c005057', 'mask': '0xfc00707f'} +vfmadd_vf : {'encoding': '101000-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa0005057', 'mask': '0xfc00707f'} +vfnmadd_vf : {'encoding': '101001-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa4005057', 'mask': '0xfc00707f'} +vfmsub_vf : {'encoding': '101010-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa8005057', 'mask': '0xfc00707f'} +vfnmsub_vf : {'encoding': '101011-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xac005057', 'mask': '0xfc00707f'} +vfmacc_vf : {'encoding': '101100-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb0005057', 'mask': '0xfc00707f'} +vfnmacc_vf : {'encoding': '101101-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb4005057', 'mask': '0xfc00707f'} +vfmsac_vf : {'encoding': '101110-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb8005057', 'mask': '0xfc00707f'} +vfnmsac_vf : {'encoding': '101111-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xbc005057', 'mask': '0xfc00707f'} +vfwadd_vf : {'encoding': '110000-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc0005057', 'mask': '0xfc00707f'} +vfwsub_vf : {'encoding': '110010-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc8005057', 'mask': '0xfc00707f'} +vfwadd_wf : {'encoding': '110100-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd0005057', 'mask': '0xfc00707f'} +vfwsub_wf : {'encoding': '110110-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd8005057', 'mask': '0xfc00707f'} +vfwmul_vf : {'encoding': '111000-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe0005057', 'mask': '0xfc00707f'} +vfwmacc_vf : {'encoding': '111100-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf0005057', 'mask': '0xfc00707f'} +vfwnmacc_vf : {'encoding': '111101-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf4005057', 'mask': '0xfc00707f'} +vfwmsac_vf : {'encoding': '111110-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf8005057', 'mask': '0xfc00707f'} +vfwnmsac_vf : {'encoding': '111111-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xfc005057', 'mask': '0xfc00707f'} +vfadd_vv : {'encoding': '000000-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1057', 'mask': '0xfc00707f'} +vfredusum_vs : {'encoding': '000001-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4001057', 'mask': '0xfc00707f'} +vfsub_vv : {'encoding': '000010-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8001057', 'mask': '0xfc00707f'} +vfredosum_vs : {'encoding': '000011-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc001057', 'mask': '0xfc00707f'} +vfmin_vv : {'encoding': '000100-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10001057', 'mask': '0xfc00707f'} +vfredmin_vs : {'encoding': '000101-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14001057', 'mask': '0xfc00707f'} +vfmax_vv : {'encoding': '000110-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18001057', 'mask': '0xfc00707f'} +vfredmax_vs : {'encoding': '000111-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c001057', 'mask': '0xfc00707f'} +vfsgnj_vv : {'encoding': '001000-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x20001057', 'mask': '0xfc00707f'} +vfsgnjn_vv : {'encoding': '001001-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x24001057', 'mask': '0xfc00707f'} +vfsgnjx_vv : {'encoding': '001010-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x28001057', 'mask': '0xfc00707f'} +vfmv_f_s : {'encoding': '0100001-----00000001-----1010111', 'variable_fields': ['vs2', 'rd'], 'extension': ['rv_v'], 'match': '0x42001057', 'mask': '0xfe0ff07f'} +vmfeq_vv : {'encoding': '011000-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x60001057', 'mask': '0xfc00707f'} +vmfle_vv : {'encoding': '011001-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x64001057', 'mask': '0xfc00707f'} +vmflt_vv : {'encoding': '011011-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6c001057', 'mask': '0xfc00707f'} +vmfne_vv : {'encoding': '011100-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x70001057', 'mask': '0xfc00707f'} +vfdiv_vv : {'encoding': '100000-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x80001057', 'mask': '0xfc00707f'} +vfmul_vv : {'encoding': '100100-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x90001057', 'mask': '0xfc00707f'} +vfmadd_vv : {'encoding': '101000-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa0001057', 'mask': '0xfc00707f'} +vfnmadd_vv : {'encoding': '101001-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa4001057', 'mask': '0xfc00707f'} +vfmsub_vv : {'encoding': '101010-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa8001057', 'mask': '0xfc00707f'} +vfnmsub_vv : {'encoding': '101011-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xac001057', 'mask': '0xfc00707f'} +vfmacc_vv : {'encoding': '101100-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb0001057', 'mask': '0xfc00707f'} +vfnmacc_vv : {'encoding': '101101-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb4001057', 'mask': '0xfc00707f'} +vfmsac_vv : {'encoding': '101110-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb8001057', 'mask': '0xfc00707f'} +vfnmsac_vv : {'encoding': '101111-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xbc001057', 'mask': '0xfc00707f'} +vfcvt_xu_f_v : {'encoding': '010010------00000001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48001057', 'mask': '0xfc0ff07f'} +vfcvt_x_f_v : {'encoding': '010010------00001001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48009057', 'mask': '0xfc0ff07f'} +vfcvt_f_xu_v : {'encoding': '010010------00010001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48011057', 'mask': '0xfc0ff07f'} +vfcvt_f_x_v : {'encoding': '010010------00011001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48019057', 'mask': '0xfc0ff07f'} +vfcvt_rtz_xu_f_v : {'encoding': '010010------00110001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48031057', 'mask': '0xfc0ff07f'} +vfcvt_rtz_x_f_v : {'encoding': '010010------00111001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48039057', 'mask': '0xfc0ff07f'} +vfwcvt_xu_f_v : {'encoding': '010010------01000001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48041057', 'mask': '0xfc0ff07f'} +vfwcvt_x_f_v : {'encoding': '010010------01001001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48049057', 'mask': '0xfc0ff07f'} +vfwcvt_f_xu_v : {'encoding': '010010------01010001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48051057', 'mask': '0xfc0ff07f'} +vfwcvt_f_x_v : {'encoding': '010010------01011001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48059057', 'mask': '0xfc0ff07f'} +vfwcvt_f_f_v : {'encoding': '010010------01100001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48061057', 'mask': '0xfc0ff07f'} +vfwcvt_rtz_xu_f_v : {'encoding': '010010------01110001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48071057', 'mask': '0xfc0ff07f'} +vfwcvt_rtz_x_f_v : {'encoding': '010010------01111001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48079057', 'mask': '0xfc0ff07f'} +vfncvt_xu_f_w : {'encoding': '010010------10000001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48081057', 'mask': '0xfc0ff07f'} +vfncvt_x_f_w : {'encoding': '010010------10001001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48089057', 'mask': '0xfc0ff07f'} +vfncvt_f_xu_w : {'encoding': '010010------10010001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48091057', 'mask': '0xfc0ff07f'} +vfncvt_f_x_w : {'encoding': '010010------10011001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48099057', 'mask': '0xfc0ff07f'} +vfncvt_f_f_w : {'encoding': '010010------10100001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x480a1057', 'mask': '0xfc0ff07f'} +vfncvt_rod_f_f_w : {'encoding': '010010------10101001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x480a9057', 'mask': '0xfc0ff07f'} +vfncvt_rtz_xu_f_w : {'encoding': '010010------10110001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x480b1057', 'mask': '0xfc0ff07f'} +vfncvt_rtz_x_f_w : {'encoding': '010010------10111001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x480b9057', 'mask': '0xfc0ff07f'} +vfsqrt_v : {'encoding': '010011------00000001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x4c001057', 'mask': '0xfc0ff07f'} +vfrsqrt7_v : {'encoding': '010011------00100001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x4c021057', 'mask': '0xfc0ff07f'} +vfrec7_v : {'encoding': '010011------00101001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x4c029057', 'mask': '0xfc0ff07f'} +vfclass_v : {'encoding': '010011------10000001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x4c081057', 'mask': '0xfc0ff07f'} +vfwadd_vv : {'encoding': '110000-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc0001057', 'mask': '0xfc00707f'} +vfwredusum_vs : {'encoding': '110001-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc4001057', 'mask': '0xfc00707f'} +vfwsub_vv : {'encoding': '110010-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc8001057', 'mask': '0xfc00707f'} +vfwredosum_vs : {'encoding': '110011-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xcc001057', 'mask': '0xfc00707f'} +vfwadd_wv : {'encoding': '110100-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd0001057', 'mask': '0xfc00707f'} +vfwsub_wv : {'encoding': '110110-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd8001057', 'mask': '0xfc00707f'} +vfwmul_vv : {'encoding': '111000-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe0001057', 'mask': '0xfc00707f'} +vfwmacc_vv : {'encoding': '111100-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf0001057', 'mask': '0xfc00707f'} +vfwnmacc_vv : {'encoding': '111101-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf4001057', 'mask': '0xfc00707f'} +vfwmsac_vv : {'encoding': '111110-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf8001057', 'mask': '0xfc00707f'} +vfwnmsac_vv : {'encoding': '111111-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xfc001057', 'mask': '0xfc00707f'} +vadd_vx : {'encoding': '000000-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4057', 'mask': '0xfc00707f'} +vsub_vx : {'encoding': '000010-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8004057', 'mask': '0xfc00707f'} +vrsub_vx : {'encoding': '000011-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc004057', 'mask': '0xfc00707f'} +vminu_vx : {'encoding': '000100-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10004057', 'mask': '0xfc00707f'} +vmin_vx : {'encoding': '000101-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14004057', 'mask': '0xfc00707f'} +vmaxu_vx : {'encoding': '000110-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18004057', 'mask': '0xfc00707f'} +vmax_vx : {'encoding': '000111-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c004057', 'mask': '0xfc00707f'} +vand_vx : {'encoding': '001001-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x24004057', 'mask': '0xfc00707f'} +vor_vx : {'encoding': '001010-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x28004057', 'mask': '0xfc00707f'} +vxor_vx : {'encoding': '001011-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2c004057', 'mask': '0xfc00707f'} +vrgather_vx : {'encoding': '001100-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x30004057', 'mask': '0xfc00707f'} +vslideup_vx : {'encoding': '001110-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x38004057', 'mask': '0xfc00707f'} +vslidedown_vx : {'encoding': '001111-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x3c004057', 'mask': '0xfc00707f'} +vadc_vxm : {'encoding': '0100000----------100-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x40004057', 'mask': '0xfe00707f'} +vmadc_vxm : {'encoding': '0100010----------100-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x44004057', 'mask': '0xfe00707f'} +vmadc_vx : {'encoding': '0100011----------100-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x46004057', 'mask': '0xfe00707f'} +vsbc_vxm : {'encoding': '0100100----------100-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x48004057', 'mask': '0xfe00707f'} +vmsbc_vxm : {'encoding': '0100110----------100-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4c004057', 'mask': '0xfe00707f'} +vmsbc_vx : {'encoding': '0100111----------100-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4e004057', 'mask': '0xfe00707f'} +vmerge_vxm : {'encoding': '0101110----------100-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5c004057', 'mask': '0xfe00707f'} +vmv_v_x : {'encoding': '010111100000-----100-----1010111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5e004057', 'mask': '0xfff0707f'} +vmseq_vx : {'encoding': '011000-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x60004057', 'mask': '0xfc00707f'} +vmsne_vx : {'encoding': '011001-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x64004057', 'mask': '0xfc00707f'} +vmsltu_vx : {'encoding': '011010-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x68004057', 'mask': '0xfc00707f'} +vmslt_vx : {'encoding': '011011-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6c004057', 'mask': '0xfc00707f'} +vmsleu_vx : {'encoding': '011100-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x70004057', 'mask': '0xfc00707f'} +vmsle_vx : {'encoding': '011101-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x74004057', 'mask': '0xfc00707f'} +vmsgtu_vx : {'encoding': '011110-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x78004057', 'mask': '0xfc00707f'} +vmsgt_vx : {'encoding': '011111-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x7c004057', 'mask': '0xfc00707f'} +vsaddu_vx : {'encoding': '100000-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x80004057', 'mask': '0xfc00707f'} +vsadd_vx : {'encoding': '100001-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x84004057', 'mask': '0xfc00707f'} +vssubu_vx : {'encoding': '100010-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x88004057', 'mask': '0xfc00707f'} +vssub_vx : {'encoding': '100011-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8c004057', 'mask': '0xfc00707f'} +vsll_vx : {'encoding': '100101-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x94004057', 'mask': '0xfc00707f'} +vsmul_vx : {'encoding': '100111-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x9c004057', 'mask': '0xfc00707f'} +vsrl_vx : {'encoding': '101000-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa0004057', 'mask': '0xfc00707f'} +vsra_vx : {'encoding': '101001-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa4004057', 'mask': '0xfc00707f'} +vssrl_vx : {'encoding': '101010-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa8004057', 'mask': '0xfc00707f'} +vssra_vx : {'encoding': '101011-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xac004057', 'mask': '0xfc00707f'} +vnsrl_wx : {'encoding': '101100-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb0004057', 'mask': '0xfc00707f'} +vnsra_wx : {'encoding': '101101-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb4004057', 'mask': '0xfc00707f'} +vnclipu_wx : {'encoding': '101110-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb8004057', 'mask': '0xfc00707f'} +vnclip_wx : {'encoding': '101111-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xbc004057', 'mask': '0xfc00707f'} +vadd_vv : {'encoding': '000000-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x57', 'mask': '0xfc00707f'} +vsub_vv : {'encoding': '000010-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8000057', 'mask': '0xfc00707f'} +vminu_vv : {'encoding': '000100-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10000057', 'mask': '0xfc00707f'} +vmin_vv : {'encoding': '000101-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14000057', 'mask': '0xfc00707f'} +vmaxu_vv : {'encoding': '000110-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18000057', 'mask': '0xfc00707f'} +vmax_vv : {'encoding': '000111-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c000057', 'mask': '0xfc00707f'} +vand_vv : {'encoding': '001001-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x24000057', 'mask': '0xfc00707f'} +vor_vv : {'encoding': '001010-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x28000057', 'mask': '0xfc00707f'} +vxor_vv : {'encoding': '001011-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2c000057', 'mask': '0xfc00707f'} +vrgather_vv : {'encoding': '001100-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x30000057', 'mask': '0xfc00707f'} +vrgatherei16_vv : {'encoding': '001110-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x38000057', 'mask': '0xfc00707f'} +vadc_vvm : {'encoding': '0100000----------000-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x40000057', 'mask': '0xfe00707f'} +vmadc_vvm : {'encoding': '0100010----------000-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x44000057', 'mask': '0xfe00707f'} +vmadc_vv : {'encoding': '0100011----------000-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x46000057', 'mask': '0xfe00707f'} +vsbc_vvm : {'encoding': '0100100----------000-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x48000057', 'mask': '0xfe00707f'} +vmsbc_vvm : {'encoding': '0100110----------000-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4c000057', 'mask': '0xfe00707f'} +vmsbc_vv : {'encoding': '0100111----------000-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4e000057', 'mask': '0xfe00707f'} +vmerge_vvm : {'encoding': '0101110----------000-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5c000057', 'mask': '0xfe00707f'} +vmv_v_v : {'encoding': '010111100000-----000-----1010111', 'variable_fields': ['vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5e000057', 'mask': '0xfff0707f'} +vmseq_vv : {'encoding': '011000-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x60000057', 'mask': '0xfc00707f'} +vmsne_vv : {'encoding': '011001-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x64000057', 'mask': '0xfc00707f'} +vmsltu_vv : {'encoding': '011010-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x68000057', 'mask': '0xfc00707f'} +vmslt_vv : {'encoding': '011011-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6c000057', 'mask': '0xfc00707f'} +vmsleu_vv : {'encoding': '011100-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x70000057', 'mask': '0xfc00707f'} +vmsle_vv : {'encoding': '011101-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x74000057', 'mask': '0xfc00707f'} +vsaddu_vv : {'encoding': '100000-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x80000057', 'mask': '0xfc00707f'} +vsadd_vv : {'encoding': '100001-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x84000057', 'mask': '0xfc00707f'} +vssubu_vv : {'encoding': '100010-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x88000057', 'mask': '0xfc00707f'} +vssub_vv : {'encoding': '100011-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8c000057', 'mask': '0xfc00707f'} +vsll_vv : {'encoding': '100101-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x94000057', 'mask': '0xfc00707f'} +vsmul_vv : {'encoding': '100111-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x9c000057', 'mask': '0xfc00707f'} +vsrl_vv : {'encoding': '101000-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa0000057', 'mask': '0xfc00707f'} +vsra_vv : {'encoding': '101001-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa4000057', 'mask': '0xfc00707f'} +vssrl_vv : {'encoding': '101010-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa8000057', 'mask': '0xfc00707f'} +vssra_vv : {'encoding': '101011-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xac000057', 'mask': '0xfc00707f'} +vnsrl_wv : {'encoding': '101100-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb0000057', 'mask': '0xfc00707f'} +vnsra_wv : {'encoding': '101101-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb4000057', 'mask': '0xfc00707f'} +vnclipu_wv : {'encoding': '101110-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb8000057', 'mask': '0xfc00707f'} +vnclip_wv : {'encoding': '101111-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xbc000057', 'mask': '0xfc00707f'} +vwredsumu_vs : {'encoding': '110000-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc0000057', 'mask': '0xfc00707f'} +vwredsum_vs : {'encoding': '110001-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc4000057', 'mask': '0xfc00707f'} +vadd_vi : {'encoding': '000000-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x3057', 'mask': '0xfc00707f'} +vrsub_vi : {'encoding': '000011-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xc003057', 'mask': '0xfc00707f'} +vand_vi : {'encoding': '001001-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x24003057', 'mask': '0xfc00707f'} +vor_vi : {'encoding': '001010-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x28003057', 'mask': '0xfc00707f'} +vxor_vi : {'encoding': '001011-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x2c003057', 'mask': '0xfc00707f'} +vrgather_vi : {'encoding': '001100-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x30003057', 'mask': '0xfc00707f'} +vslideup_vi : {'encoding': '001110-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x38003057', 'mask': '0xfc00707f'} +vslidedown_vi : {'encoding': '001111-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x3c003057', 'mask': '0xfc00707f'} +vadc_vim : {'encoding': '0100000----------011-----1010111', 'variable_fields': ['vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x40003057', 'mask': '0xfe00707f'} +vmadc_vim : {'encoding': '0100010----------011-----1010111', 'variable_fields': ['vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x44003057', 'mask': '0xfe00707f'} +vmadc_vi : {'encoding': '0100011----------011-----1010111', 'variable_fields': ['vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x46003057', 'mask': '0xfe00707f'} +vmerge_vim : {'encoding': '0101110----------011-----1010111', 'variable_fields': ['vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x5c003057', 'mask': '0xfe00707f'} +vmv_v_i : {'encoding': '010111100000-----011-----1010111', 'variable_fields': ['simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x5e003057', 'mask': '0xfff0707f'} +vmseq_vi : {'encoding': '011000-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x60003057', 'mask': '0xfc00707f'} +vmsne_vi : {'encoding': '011001-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x64003057', 'mask': '0xfc00707f'} +vmsleu_vi : {'encoding': '011100-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x70003057', 'mask': '0xfc00707f'} +vmsle_vi : {'encoding': '011101-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x74003057', 'mask': '0xfc00707f'} +vmsgtu_vi : {'encoding': '011110-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x78003057', 'mask': '0xfc00707f'} +vmsgt_vi : {'encoding': '011111-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x7c003057', 'mask': '0xfc00707f'} +vsaddu_vi : {'encoding': '100000-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x80003057', 'mask': '0xfc00707f'} +vsadd_vi : {'encoding': '100001-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x84003057', 'mask': '0xfc00707f'} +vsll_vi : {'encoding': '100101-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x94003057', 'mask': '0xfc00707f'} +vmv1r_v : {'encoding': '1001111-----00000011-----1010111', 'variable_fields': ['vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x9e003057', 'mask': '0xfe0ff07f'} +vmv2r_v : {'encoding': '1001111-----00001011-----1010111', 'variable_fields': ['vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x9e00b057', 'mask': '0xfe0ff07f'} +vmv4r_v : {'encoding': '1001111-----00011011-----1010111', 'variable_fields': ['vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x9e01b057', 'mask': '0xfe0ff07f'} +vmv8r_v : {'encoding': '1001111-----00111011-----1010111', 'variable_fields': ['vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x9e03b057', 'mask': '0xfe0ff07f'} +vsrl_vi : {'encoding': '101000-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xa0003057', 'mask': '0xfc00707f'} +vsra_vi : {'encoding': '101001-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xa4003057', 'mask': '0xfc00707f'} +vssrl_vi : {'encoding': '101010-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xa8003057', 'mask': '0xfc00707f'} +vssra_vi : {'encoding': '101011-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xac003057', 'mask': '0xfc00707f'} +vnsrl_wi : {'encoding': '101100-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xb0003057', 'mask': '0xfc00707f'} +vnsra_wi : {'encoding': '101101-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xb4003057', 'mask': '0xfc00707f'} +vnclipu_wi : {'encoding': '101110-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xb8003057', 'mask': '0xfc00707f'} +vnclip_wi : {'encoding': '101111-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xbc003057', 'mask': '0xfc00707f'} +vredsum_vs : {'encoding': '000000-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2057', 'mask': '0xfc00707f'} +vredand_vs : {'encoding': '000001-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4002057', 'mask': '0xfc00707f'} +vredor_vs : {'encoding': '000010-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8002057', 'mask': '0xfc00707f'} +vredxor_vs : {'encoding': '000011-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc002057', 'mask': '0xfc00707f'} +vredminu_vs : {'encoding': '000100-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10002057', 'mask': '0xfc00707f'} +vredmin_vs : {'encoding': '000101-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14002057', 'mask': '0xfc00707f'} +vredmaxu_vs : {'encoding': '000110-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18002057', 'mask': '0xfc00707f'} +vredmax_vs : {'encoding': '000111-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c002057', 'mask': '0xfc00707f'} +vaaddu_vv : {'encoding': '001000-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x20002057', 'mask': '0xfc00707f'} +vaadd_vv : {'encoding': '001001-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x24002057', 'mask': '0xfc00707f'} +vasubu_vv : {'encoding': '001010-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x28002057', 'mask': '0xfc00707f'} +vasub_vv : {'encoding': '001011-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2c002057', 'mask': '0xfc00707f'} +vmv_x_s : {'encoding': '0100001-----00000010-----1010111', 'variable_fields': ['vs2', 'rd'], 'extension': ['rv_v'], 'match': '0x42002057', 'mask': '0xfe0ff07f'} +vzext_vf8 : {'encoding': '010010------00010010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48012057', 'mask': '0xfc0ff07f'} +vsext_vf8 : {'encoding': '010010------00011010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x4801a057', 'mask': '0xfc0ff07f'} +vzext_vf4 : {'encoding': '010010------00100010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48022057', 'mask': '0xfc0ff07f'} +vsext_vf4 : {'encoding': '010010------00101010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x4802a057', 'mask': '0xfc0ff07f'} +vzext_vf2 : {'encoding': '010010------00110010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48032057', 'mask': '0xfc0ff07f'} +vsext_vf2 : {'encoding': '010010------00111010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x4803a057', 'mask': '0xfc0ff07f'} +vcompress_vm : {'encoding': '0101111----------010-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5e002057', 'mask': '0xfe00707f'} +vmandn_mm : {'encoding': '011000-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x60002057', 'mask': '0xfc00707f'} +vmand_mm : {'encoding': '011001-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x64002057', 'mask': '0xfc00707f'} +vmor_mm : {'encoding': '011010-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x68002057', 'mask': '0xfc00707f'} +vmxor_mm : {'encoding': '011011-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6c002057', 'mask': '0xfc00707f'} +vmorn_mm : {'encoding': '011100-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x70002057', 'mask': '0xfc00707f'} +vmnand_mm : {'encoding': '011101-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x74002057', 'mask': '0xfc00707f'} +vmnor_mm : {'encoding': '011110-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x78002057', 'mask': '0xfc00707f'} +vmxnor_mm : {'encoding': '011111-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x7c002057', 'mask': '0xfc00707f'} +vmsbf_m : {'encoding': '010100------00001010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x5000a057', 'mask': '0xfc0ff07f'} +vmsof_m : {'encoding': '010100------00010010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x50012057', 'mask': '0xfc0ff07f'} +vmsif_m : {'encoding': '010100------00011010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x5001a057', 'mask': '0xfc0ff07f'} +viota_m : {'encoding': '010100------10000010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x50082057', 'mask': '0xfc0ff07f'} +vid_v : {'encoding': '010100-0000010001010-----1010111', 'variable_fields': ['vm', 'vd'], 'extension': ['rv_v'], 'match': '0x5008a057', 'mask': '0xfdfff07f'} +vcpop_m : {'encoding': '010000------10000010-----1010111', 'variable_fields': ['vm', 'vs2', 'rd'], 'extension': ['rv_v'], 'match': '0x40082057', 'mask': '0xfc0ff07f'} +vfirst_m : {'encoding': '010000------10001010-----1010111', 'variable_fields': ['vm', 'vs2', 'rd'], 'extension': ['rv_v'], 'match': '0x4008a057', 'mask': '0xfc0ff07f'} +vdivu_vv : {'encoding': '100000-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x80002057', 'mask': '0xfc00707f'} +vdiv_vv : {'encoding': '100001-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x84002057', 'mask': '0xfc00707f'} +vremu_vv : {'encoding': '100010-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x88002057', 'mask': '0xfc00707f'} +vrem_vv : {'encoding': '100011-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8c002057', 'mask': '0xfc00707f'} +vmulhu_vv : {'encoding': '100100-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x90002057', 'mask': '0xfc00707f'} +vmul_vv : {'encoding': '100101-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x94002057', 'mask': '0xfc00707f'} +vmulhsu_vv : {'encoding': '100110-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x98002057', 'mask': '0xfc00707f'} +vmulh_vv : {'encoding': '100111-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x9c002057', 'mask': '0xfc00707f'} +vmadd_vv : {'encoding': '101001-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa4002057', 'mask': '0xfc00707f'} +vnmsub_vv : {'encoding': '101011-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xac002057', 'mask': '0xfc00707f'} +vmacc_vv : {'encoding': '101101-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb4002057', 'mask': '0xfc00707f'} +vnmsac_vv : {'encoding': '101111-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xbc002057', 'mask': '0xfc00707f'} +vwaddu_vv : {'encoding': '110000-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc0002057', 'mask': '0xfc00707f'} +vwadd_vv : {'encoding': '110001-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc4002057', 'mask': '0xfc00707f'} +vwsubu_vv : {'encoding': '110010-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc8002057', 'mask': '0xfc00707f'} +vwsub_vv : {'encoding': '110011-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xcc002057', 'mask': '0xfc00707f'} +vwaddu_wv : {'encoding': '110100-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd0002057', 'mask': '0xfc00707f'} +vwadd_wv : {'encoding': '110101-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd4002057', 'mask': '0xfc00707f'} +vwsubu_wv : {'encoding': '110110-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd8002057', 'mask': '0xfc00707f'} +vwsub_wv : {'encoding': '110111-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xdc002057', 'mask': '0xfc00707f'} +vwmulu_vv : {'encoding': '111000-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe0002057', 'mask': '0xfc00707f'} +vwmulsu_vv : {'encoding': '111010-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe8002057', 'mask': '0xfc00707f'} +vwmul_vv : {'encoding': '111011-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xec002057', 'mask': '0xfc00707f'} +vwmaccu_vv : {'encoding': '111100-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf0002057', 'mask': '0xfc00707f'} +vwmacc_vv : {'encoding': '111101-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf4002057', 'mask': '0xfc00707f'} +vwmaccsu_vv : {'encoding': '111111-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xfc002057', 'mask': '0xfc00707f'} +vaaddu_vx : {'encoding': '001000-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x20006057', 'mask': '0xfc00707f'} +vaadd_vx : {'encoding': '001001-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x24006057', 'mask': '0xfc00707f'} +vasubu_vx : {'encoding': '001010-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x28006057', 'mask': '0xfc00707f'} +vasub_vx : {'encoding': '001011-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2c006057', 'mask': '0xfc00707f'} +vmv_s_x : {'encoding': '010000100000-----110-----1010111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x42006057', 'mask': '0xfff0707f'} +vslide1up_vx : {'encoding': '001110-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x38006057', 'mask': '0xfc00707f'} +vslide1down_vx : {'encoding': '001111-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x3c006057', 'mask': '0xfc00707f'} +vdivu_vx : {'encoding': '100000-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x80006057', 'mask': '0xfc00707f'} +vdiv_vx : {'encoding': '100001-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x84006057', 'mask': '0xfc00707f'} +vremu_vx : {'encoding': '100010-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x88006057', 'mask': '0xfc00707f'} +vrem_vx : {'encoding': '100011-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8c006057', 'mask': '0xfc00707f'} +vmulhu_vx : {'encoding': '100100-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x90006057', 'mask': '0xfc00707f'} +vmul_vx : {'encoding': '100101-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x94006057', 'mask': '0xfc00707f'} +vmulhsu_vx : {'encoding': '100110-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x98006057', 'mask': '0xfc00707f'} +vmulh_vx : {'encoding': '100111-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x9c006057', 'mask': '0xfc00707f'} +vmadd_vx : {'encoding': '101001-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa4006057', 'mask': '0xfc00707f'} +vnmsub_vx : {'encoding': '101011-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xac006057', 'mask': '0xfc00707f'} +vmacc_vx : {'encoding': '101101-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb4006057', 'mask': '0xfc00707f'} +vnmsac_vx : {'encoding': '101111-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xbc006057', 'mask': '0xfc00707f'} +vwaddu_vx : {'encoding': '110000-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc0006057', 'mask': '0xfc00707f'} +vwadd_vx : {'encoding': '110001-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc4006057', 'mask': '0xfc00707f'} +vwsubu_vx : {'encoding': '110010-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc8006057', 'mask': '0xfc00707f'} +vwsub_vx : {'encoding': '110011-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xcc006057', 'mask': '0xfc00707f'} +vwaddu_wx : {'encoding': '110100-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd0006057', 'mask': '0xfc00707f'} +vwadd_wx : {'encoding': '110101-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd4006057', 'mask': '0xfc00707f'} +vwsubu_wx : {'encoding': '110110-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd8006057', 'mask': '0xfc00707f'} +vwsub_wx : {'encoding': '110111-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xdc006057', 'mask': '0xfc00707f'} +vwmulu_vx : {'encoding': '111000-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe0006057', 'mask': '0xfc00707f'} +vwmulsu_vx : {'encoding': '111010-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe8006057', 'mask': '0xfc00707f'} +vwmul_vx : {'encoding': '111011-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xec006057', 'mask': '0xfc00707f'} +vwmaccu_vx : {'encoding': '111100-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf0006057', 'mask': '0xfc00707f'} +vwmacc_vx : {'encoding': '111101-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf4006057', 'mask': '0xfc00707f'} +vwmaccus_vx : {'encoding': '111110-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf8006057', 'mask': '0xfc00707f'} +vwmaccsu_vx : {'encoding': '111111-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xfc006057', 'mask': '0xfc00707f'} +vamoswapei8_v : {'encoding': '00001------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x800002f', 'mask': '0xf800707f'} +vamoaddei8_v : {'encoding': '00000------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2f', 'mask': '0xf800707f'} +vamoxorei8_v : {'encoding': '00100------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2000002f', 'mask': '0xf800707f'} +vamoandei8_v : {'encoding': '01100------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6000002f', 'mask': '0xf800707f'} +vamoorei8_v : {'encoding': '01000------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4000002f', 'mask': '0xf800707f'} +vamominei8_v : {'encoding': '10000------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8000002f', 'mask': '0xf800707f'} +vamomaxei8_v : {'encoding': '10100------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa000002f', 'mask': '0xf800707f'} +vamominuei8_v : {'encoding': '11000------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc000002f', 'mask': '0xf800707f'} +vamomaxuei8_v : {'encoding': '11100------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe000002f', 'mask': '0xf800707f'} +vamoswapei16_v : {'encoding': '00001------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x800502f', 'mask': '0xf800707f'} +vamoaddei16_v : {'encoding': '00000------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x502f', 'mask': '0xf800707f'} +vamoxorei16_v : {'encoding': '00100------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2000502f', 'mask': '0xf800707f'} +vamoandei16_v : {'encoding': '01100------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6000502f', 'mask': '0xf800707f'} +vamoorei16_v : {'encoding': '01000------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4000502f', 'mask': '0xf800707f'} +vamominei16_v : {'encoding': '10000------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8000502f', 'mask': '0xf800707f'} +vamomaxei16_v : {'encoding': '10100------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa000502f', 'mask': '0xf800707f'} +vamominuei16_v : {'encoding': '11000------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc000502f', 'mask': '0xf800707f'} +vamomaxuei16_v : {'encoding': '11100------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe000502f', 'mask': '0xf800707f'} +vamoswapei32_v : {'encoding': '00001------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x800602f', 'mask': '0xf800707f'} +vamoaddei32_v : {'encoding': '00000------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x602f', 'mask': '0xf800707f'} +vamoxorei32_v : {'encoding': '00100------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2000602f', 'mask': '0xf800707f'} +vamoandei32_v : {'encoding': '01100------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6000602f', 'mask': '0xf800707f'} +vamoorei32_v : {'encoding': '01000------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4000602f', 'mask': '0xf800707f'} +vamominei32_v : {'encoding': '10000------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8000602f', 'mask': '0xf800707f'} +vamomaxei32_v : {'encoding': '10100------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa000602f', 'mask': '0xf800707f'} +vamominuei32_v : {'encoding': '11000------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc000602f', 'mask': '0xf800707f'} +vamomaxuei32_v : {'encoding': '11100------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe000602f', 'mask': '0xf800707f'} +vamoswapei64_v : {'encoding': '00001------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x800702f', 'mask': '0xf800707f'} +vamoaddei64_v : {'encoding': '00000------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x702f', 'mask': '0xf800707f'} +vamoxorei64_v : {'encoding': '00100------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2000702f', 'mask': '0xf800707f'} +vamoandei64_v : {'encoding': '01100------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6000702f', 'mask': '0xf800707f'} +vamoorei64_v : {'encoding': '01000------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4000702f', 'mask': '0xf800707f'} +vamominei64_v : {'encoding': '10000------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8000702f', 'mask': '0xf800707f'} +vamomaxei64_v : {'encoding': '10100------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa000702f', 'mask': '0xf800707f'} +vamominuei64_v : {'encoding': '11000------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc000702f', 'mask': '0xf800707f'} +vamomaxuei64_v : {'encoding': '11100------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe000702f', 'mask': '0xf800707f'} +c_lq : {'encoding': '----------------001-----------00', 'variable_fields': ['rd_p', 'rs1_p', 'c_uimm9lo', 'c_uimm9hi'], 'extension': ['rv128_c'], 'match': '0x2000', 'mask': '0xe003'} +c_ld : {'encoding': '----------------011-----------00', 'variable_fields': ['rd_p', 'rs1_p', 'c_uimm8lo', 'c_uimm8hi'], 'extension': ['rv64_c'], 'match': '0x6000', 'mask': '0xe003'} +c_sq : {'encoding': '----------------101-----------00', 'variable_fields': ['rs1_p', 'rs2_p', 'c_uimm9hi', 'c_uimm9lo'], 'extension': ['rv128_c'], 'match': '0xa000', 'mask': '0xe003'} +c_sd : {'encoding': '----------------111-----------00', 'variable_fields': ['rs1_p', 'rs2_p', 'c_uimm8hi', 'c_uimm8lo'], 'extension': ['rv64_c'], 'match': '0xe000', 'mask': '0xe003'} +c_addiw : {'encoding': '----------------001-----------01', 'variable_fields': ['rd_rs1', 'c_imm6lo', 'c_imm6hi'], 'extension': ['rv64_c'], 'match': '0x2001', 'mask': '0xe003'} +c_lqsp : {'encoding': '----------------001-----------10', 'variable_fields': ['rd', 'c_uimm10sphi', 'c_uimm10splo'], 'extension': ['rv128_c'], 'match': '0x2002', 'mask': '0xe003'} +c_ldsp : {'encoding': '----------------011-----------10', 'variable_fields': ['rd_n0', 'c_uimm9sphi', 'c_uimm9splo'], 'extension': ['rv64_c'], 'match': '0x6002', 'mask': '0xe003'} +c_sqsp : {'encoding': '----------------101-----------10', 'variable_fields': ['c_rs2', 'c_uimm10sp_s'], 'extension': ['rv128_c'], 'match': '0xa002', 'mask': '0xe003'} +c_sdsp : {'encoding': '----------------111-----------10', 'variable_fields': ['c_rs2', 'c_uimm9sp_s'], 'extension': ['rv64_c'], 'match': '0xe002', 'mask': '0xe003'} +grev : {'encoding': '0110100----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x68005033', 'mask': '0xfe00707f'} +gorc : {'encoding': '0010100----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x28005033', 'mask': '0xfe00707f'} +shfl : {'encoding': '0000100----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x8001033', 'mask': '0xfe00707f'} +unshfl : {'encoding': '0000100----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x8005033', 'mask': '0xfe00707f'} +xperm4 : {'encoding': '0010100----------010-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x28002033', 'mask': '0xfe00707f'} +xperm8 : {'encoding': '0010100----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x28004033', 'mask': '0xfe00707f'} +xperm16 : {'encoding': '0010100----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x28006033', 'mask': '0xfe00707f'} +packu : {'encoding': '0100100----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x48004033', 'mask': '0xfe00707f'} +fence_i : {'encoding': '-----------------001-----0001111', 'variable_fields': ['imm12', 'rs1', 'rd'], 'extension': ['rv_zifencei'], 'match': '0x100f', 'mask': '0x707f'} +crc32_b : {'encoding': '011000010000-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbr'], 'match': '0x61001013', 'mask': '0xfff0707f'} +crc32_h : {'encoding': '011000010001-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbr'], 'match': '0x61101013', 'mask': '0xfff0707f'} +crc32_w : {'encoding': '011000010010-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbr'], 'match': '0x61201013', 'mask': '0xfff0707f'} +crc32c_b : {'encoding': '011000011000-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbr'], 'match': '0x61801013', 'mask': '0xfff0707f'} +crc32c_h : {'encoding': '011000011001-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbr'], 'match': '0x61901013', 'mask': '0xfff0707f'} +crc32c_w : {'encoding': '011000011010-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbr'], 'match': '0x61a01013', 'mask': '0xfff0707f'} +c_srli : {'encoding': '----------------100-00--------01', 'variable_fields': ['rd_rs1_p', 'c_nzuimm6lo', 'c_nzuimm6hi'], 'extension': ['rv64_c'], 'match': '0x8001', 'mask': '0xec03'} +c_srai : {'encoding': '----------------100-01--------01', 'variable_fields': ['rd_rs1_p', 'c_nzuimm6lo', 'c_nzuimm6hi'], 'extension': ['rv64_c'], 'match': '0x8401', 'mask': '0xec03'} +c_subw : {'encoding': '----------------100111---00---01', 'variable_fields': ['rd_rs1_p', 'rs2_p'], 'extension': ['rv64_c'], 'match': '0x9c01', 'mask': '0xfc63'} +c_addw : {'encoding': '----------------100111---01---01', 'variable_fields': ['rd_rs1_p', 'rs2_p'], 'extension': ['rv64_c'], 'match': '0x9c21', 'mask': '0xfc63'} +c_slli : {'encoding': '----------------000-----------10', 'variable_fields': ['rd_rs1_n0', 'c_nzuimm6hi', 'c_nzuimm6lo'], 'extension': ['rv64_c'], 'match': '0x2', 'mask': '0xe003'} +c_fld : {'encoding': '----------------001-----------00', 'variable_fields': ['rd_p', 'rs1_p', 'c_uimm8lo', 'c_uimm8hi'], 'extension': ['rv_c_d'], 'match': '0x2000', 'mask': '0xe003'} +c_fsd : {'encoding': '----------------101-----------00', 'variable_fields': ['rs1_p', 'rs2_p', 'c_uimm8lo', 'c_uimm8hi'], 'extension': ['rv_c_d'], 'match': '0xa000', 'mask': '0xe003'} +c_fldsp : {'encoding': '----------------001-----------10', 'variable_fields': ['rd', 'c_uimm9sphi', 'c_uimm9splo'], 'extension': ['rv_c_d'], 'match': '0x2002', 'mask': '0xe003'} +c_fsdsp : {'encoding': '----------------101-----------10', 'variable_fields': ['c_rs2', 'c_uimm9sp_s'], 'extension': ['rv_c_d'], 'match': '0xa002', 'mask': '0xe003'} +flq : {'encoding': '-----------------100-----0000111', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_q'], 'match': '0x4007', 'mask': '0x707f'} +fsq : {'encoding': '-----------------100-----0100111', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv_q'], 'match': '0x4027', 'mask': '0x707f'} +fmadd_q : {'encoding': '-----11------------------1000011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_q'], 'match': '0x6000043', 'mask': '0x600007f'} +fmsub_q : {'encoding': '-----11------------------1000111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_q'], 'match': '0x6000047', 'mask': '0x600007f'} +fnmsub_q : {'encoding': '-----11------------------1001011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_q'], 'match': '0x600004b', 'mask': '0x600007f'} +fnmadd_q : {'encoding': '-----11------------------1001111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_q'], 'match': '0x600004f', 'mask': '0x600007f'} +fadd_q : {'encoding': '0000011------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_q'], 'match': '0x6000053', 'mask': '0xfe00007f'} +fsub_q : {'encoding': '0000111------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_q'], 'match': '0xe000053', 'mask': '0xfe00007f'} +fmul_q : {'encoding': '0001011------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_q'], 'match': '0x16000053', 'mask': '0xfe00007f'} +fdiv_q : {'encoding': '0001111------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_q'], 'match': '0x1e000053', 'mask': '0xfe00007f'} +fsqrt_q : {'encoding': '010111100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0x5e000053', 'mask': '0xfff0007f'} +fsgnj_q : {'encoding': '0010011----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0x26000053', 'mask': '0xfe00707f'} +fsgnjn_q : {'encoding': '0010011----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0x26001053', 'mask': '0xfe00707f'} +fsgnjx_q : {'encoding': '0010011----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0x26002053', 'mask': '0xfe00707f'} +fmin_q : {'encoding': '0010111----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0x2e000053', 'mask': '0xfe00707f'} +fmax_q : {'encoding': '0010111----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0x2e001053', 'mask': '0xfe00707f'} +fcvt_s_q : {'encoding': '010000000011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0x40300053', 'mask': '0xfff0007f'} +fcvt_q_s : {'encoding': '010001100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0x46000053', 'mask': '0xfff0007f'} +fcvt_d_q : {'encoding': '010000100011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0x42300053', 'mask': '0xfff0007f'} +fcvt_q_d : {'encoding': '010001100001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0x46100053', 'mask': '0xfff0007f'} +feq_q : {'encoding': '1010011----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0xa6002053', 'mask': '0xfe00707f'} +flt_q : {'encoding': '1010011----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0xa6001053', 'mask': '0xfe00707f'} +fle_q : {'encoding': '1010011----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0xa6000053', 'mask': '0xfe00707f'} +fclass_q : {'encoding': '111001100000-----001-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_q'], 'match': '0xe6001053', 'mask': '0xfff0707f'} +fcvt_w_q : {'encoding': '110001100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0xc6000053', 'mask': '0xfff0007f'} +fcvt_wu_q : {'encoding': '110001100001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0xc6100053', 'mask': '0xfff0007f'} +fcvt_q_w : {'encoding': '110101100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0xd6000053', 'mask': '0xfff0007f'} +fcvt_q_wu : {'encoding': '110101100001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0xd6100053', 'mask': '0xfff0007f'} +hlv_wu : {'encoding': '011010000001-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_h'], 'match': '0x68104073', 'mask': '0xfff0707f'} +hlv_d : {'encoding': '011011000000-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_h'], 'match': '0x6c004073', 'mask': '0xfff0707f'} +hsv_d : {'encoding': '0110111----------100000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv64_h'], 'match': '0x6e004073', 'mask': '0xfe007fff'} +hfence_vvma : {'encoding': '0010001----------000000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_h'], 'match': '0x22000073', 'mask': '0xfe007fff'} +hfence_gvma : {'encoding': '0110001----------000000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_h'], 'match': '0x62000073', 'mask': '0xfe007fff'} +hlv_b : {'encoding': '011000000000-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_h'], 'match': '0x60004073', 'mask': '0xfff0707f'} +hlv_bu : {'encoding': '011000000001-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_h'], 'match': '0x60104073', 'mask': '0xfff0707f'} +hlv_h : {'encoding': '011001000000-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_h'], 'match': '0x64004073', 'mask': '0xfff0707f'} +hlv_hu : {'encoding': '011001000001-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_h'], 'match': '0x64104073', 'mask': '0xfff0707f'} +hlvx_hu : {'encoding': '011001000011-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_h'], 'match': '0x64304073', 'mask': '0xfff0707f'} +hlv_w : {'encoding': '011010000000-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_h'], 'match': '0x68004073', 'mask': '0xfff0707f'} +hlvx_wu : {'encoding': '011010000011-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_h'], 'match': '0x68304073', 'mask': '0xfff0707f'} +hsv_b : {'encoding': '0110001----------100000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_h'], 'match': '0x62004073', 'mask': '0xfe007fff'} +hsv_h : {'encoding': '0110011----------100000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_h'], 'match': '0x66004073', 'mask': '0xfe007fff'} +hsv_w : {'encoding': '0110101----------100000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_h'], 'match': '0x6a004073', 'mask': '0xfe007fff'} +aes32dsmi : {'encoding': '--10111----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'bs'], 'extension': ['rv32_zknd'], 'match': '0x2e000033', 'mask': '0x3e00707f'} +aes32dsi : {'encoding': '--10101----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'bs'], 'extension': ['rv32_zknd'], 'match': '0x2a000033', 'mask': '0x3e00707f'} +fslw : {'encoding': '-----10----------001-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3'], 'extension': ['rv64_zbt'], 'match': '0x400103b', 'mask': '0x600707f'} +fsrw : {'encoding': '-----10----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3'], 'extension': ['rv64_zbt'], 'match': '0x400503b', 'mask': '0x600707f'} +fsriw : {'encoding': '-----10----------101-----0011011', 'variable_fields': ['rd', 'rs1', 'rs3', 'shamtw'], 'extension': ['rv64_zbt'], 'match': '0x400501b', 'mask': '0x600707f'} +fsri : {'encoding': '-----1-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'rs3', 'shamt'], 'extension': ['rv64_zbt'], 'match': '0x4005013', 'mask': '0x400707f'} +custom0 : {'encoding': '-----------------000-----0001011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0xb', 'mask': '0x707f'} +custom0_rs1 : {'encoding': '-----------------010-----0001011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x200b', 'mask': '0x707f'} +custom0_rs1_rs2 : {'encoding': '-----------------011-----0001011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x300b', 'mask': '0x707f'} +custom0_rd : {'encoding': '-----------------100-----0001011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x400b', 'mask': '0x707f'} +custom0_rd_rs1 : {'encoding': '-----------------110-----0001011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x600b', 'mask': '0x707f'} +custom0_rd_rs1_rs2 : {'encoding': '-----------------111-----0001011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x700b', 'mask': '0x707f'} +custom1 : {'encoding': '-----------------000-----0101011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x2b', 'mask': '0x707f'} +custom1_rs1 : {'encoding': '-----------------010-----0101011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x202b', 'mask': '0x707f'} +custom1_rs1_rs2 : {'encoding': '-----------------011-----0101011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x302b', 'mask': '0x707f'} +custom1_rd : {'encoding': '-----------------100-----0101011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x402b', 'mask': '0x707f'} +custom1_rd_rs1 : {'encoding': '-----------------110-----0101011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x602b', 'mask': '0x707f'} +custom1_rd_rs1_rs2 : {'encoding': '-----------------111-----0101011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x702b', 'mask': '0x707f'} +custom2 : {'encoding': '-----------------000-----1011011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x5b', 'mask': '0x707f'} +custom2_rs1 : {'encoding': '-----------------010-----1011011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x205b', 'mask': '0x707f'} +custom2_rs1_rs2 : {'encoding': '-----------------011-----1011011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x305b', 'mask': '0x707f'} +custom2_rd : {'encoding': '-----------------100-----1011011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x405b', 'mask': '0x707f'} +custom2_rd_rs1 : {'encoding': '-----------------110-----1011011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x605b', 'mask': '0x707f'} +custom2_rd_rs1_rs2 : {'encoding': '-----------------111-----1011011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x705b', 'mask': '0x707f'} +custom3 : {'encoding': '-----------------000-----1111011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x7b', 'mask': '0x707f'} +custom3_rs1 : {'encoding': '-----------------010-----1111011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x207b', 'mask': '0x707f'} +custom3_rs1_rs2 : {'encoding': '-----------------011-----1111011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x307b', 'mask': '0x707f'} +custom3_rd : {'encoding': '-----------------100-----1111011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x407b', 'mask': '0x707f'} +custom3_rd_rs1 : {'encoding': '-----------------110-----1111011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x607b', 'mask': '0x707f'} +custom3_rd_rs1_rs2 : {'encoding': '-----------------111-----1111011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x707b', 'mask': '0x707f'} +sm4ed : {'encoding': '--11000----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'bs'], 'extension': ['rv_zksed'], 'match': '0x30000033', 'mask': '0x3e00707f'} +sm4ks : {'encoding': '--11010----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'bs'], 'extension': ['rv_zksed'], 'match': '0x34000033', 'mask': '0x3e00707f'} +slo : {'encoding': '0010000----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_b'], 'match': '0x20001033', 'mask': '0xfe00707f'} +sro : {'encoding': '0010000----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_b'], 'match': '0x20005033', 'mask': '0xfe00707f'} +sloi : {'encoding': '001000-----------001-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv_b'], 'match': '0x20001013', 'mask': '0xfc00707f'} +sroi : {'encoding': '001000-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv_b'], 'match': '0x20005013', 'mask': '0xfc00707f'} +lui : {'encoding': '-------------------------0110111', 'variable_fields': ['rd', 'imm20'], 'extension': ['rv_i'], 'match': '0x37', 'mask': '0x7f'} +auipc : {'encoding': '-------------------------0010111', 'variable_fields': ['rd', 'imm20'], 'extension': ['rv_i'], 'match': '0x17', 'mask': '0x7f'} +jal : {'encoding': '-------------------------1101111', 'variable_fields': ['rd', 'jimm20'], 'extension': ['rv_i'], 'match': '0x6f', 'mask': '0x7f'} +jalr : {'encoding': '-----------------000-----1100111', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x67', 'mask': '0x707f'} +beq : {'encoding': '-----------------000-----1100011', 'variable_fields': ['bimm12hi', 'rs1', 'rs2', 'bimm12lo'], 'extension': ['rv_i'], 'match': '0x63', 'mask': '0x707f'} +bne : {'encoding': '-----------------001-----1100011', 'variable_fields': ['bimm12hi', 'rs1', 'rs2', 'bimm12lo'], 'extension': ['rv_i'], 'match': '0x1063', 'mask': '0x707f'} +blt : {'encoding': '-----------------100-----1100011', 'variable_fields': ['bimm12hi', 'rs1', 'rs2', 'bimm12lo'], 'extension': ['rv_i'], 'match': '0x4063', 'mask': '0x707f'} +bge : {'encoding': '-----------------101-----1100011', 'variable_fields': ['bimm12hi', 'rs1', 'rs2', 'bimm12lo'], 'extension': ['rv_i'], 'match': '0x5063', 'mask': '0x707f'} +bltu : {'encoding': '-----------------110-----1100011', 'variable_fields': ['bimm12hi', 'rs1', 'rs2', 'bimm12lo'], 'extension': ['rv_i'], 'match': '0x6063', 'mask': '0x707f'} +bgeu : {'encoding': '-----------------111-----1100011', 'variable_fields': ['bimm12hi', 'rs1', 'rs2', 'bimm12lo'], 'extension': ['rv_i'], 'match': '0x7063', 'mask': '0x707f'} +lb : {'encoding': '-----------------000-----0000011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x3', 'mask': '0x707f'} +lh : {'encoding': '-----------------001-----0000011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x1003', 'mask': '0x707f'} +lw : {'encoding': '-----------------010-----0000011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x2003', 'mask': '0x707f'} +lbu : {'encoding': '-----------------100-----0000011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x4003', 'mask': '0x707f'} +lhu : {'encoding': '-----------------101-----0000011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x5003', 'mask': '0x707f'} +sb : {'encoding': '-----------------000-----0100011', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv_i'], 'match': '0x23', 'mask': '0x707f'} +sh : {'encoding': '-----------------001-----0100011', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv_i'], 'match': '0x1023', 'mask': '0x707f'} +sw : {'encoding': '-----------------010-----0100011', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv_i'], 'match': '0x2023', 'mask': '0x707f'} +addi : {'encoding': '-----------------000-----0010011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x13', 'mask': '0x707f'} +slti : {'encoding': '-----------------010-----0010011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x2013', 'mask': '0x707f'} +sltiu : {'encoding': '-----------------011-----0010011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x3013', 'mask': '0x707f'} +xori : {'encoding': '-----------------100-----0010011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x4013', 'mask': '0x707f'} +ori : {'encoding': '-----------------110-----0010011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x6013', 'mask': '0x707f'} +andi : {'encoding': '-----------------111-----0010011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x7013', 'mask': '0x707f'} +add : {'encoding': '0000000----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x33', 'mask': '0xfe00707f'} +sub : {'encoding': '0100000----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x40000033', 'mask': '0xfe00707f'} +sll : {'encoding': '0000000----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x1033', 'mask': '0xfe00707f'} +slt : {'encoding': '0000000----------010-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x2033', 'mask': '0xfe00707f'} +sltu : {'encoding': '0000000----------011-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x3033', 'mask': '0xfe00707f'} +xor : {'encoding': '0000000----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x4033', 'mask': '0xfe00707f'} +srl : {'encoding': '0000000----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x5033', 'mask': '0xfe00707f'} +sra : {'encoding': '0100000----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x40005033', 'mask': '0xfe00707f'} +or : {'encoding': '0000000----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x6033', 'mask': '0xfe00707f'} +and : {'encoding': '0000000----------111-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x7033', 'mask': '0xfe00707f'} +fence : {'encoding': '-----------------000-----0001111', 'variable_fields': ['fm', 'pred', 'succ', 'rs1', 'rd'], 'extension': ['rv_i'], 'match': '0xf', 'mask': '0x707f'} +ecall : {'encoding': '00000000000000000000000001110011', 'variable_fields': [], 'extension': ['rv_i'], 'match': '0x73', 'mask': '0xffffffff'} +ebreak : {'encoding': '00000000000100000000000001110011', 'variable_fields': [], 'extension': ['rv_i'], 'match': '0x100073', 'mask': '0xffffffff'} +andn : {'encoding': '0100000----------111-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0x40007033', 'mask': '0xfe00707f'} +orn : {'encoding': '0100000----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0x40006033', 'mask': '0xfe00707f'} +xnor : {'encoding': '0100000----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0x40004033', 'mask': '0xfe00707f'} +clz : {'encoding': '011000000000-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbb'], 'match': '0x60001013', 'mask': '0xfff0707f'} +ctz : {'encoding': '011000000001-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbb'], 'match': '0x60101013', 'mask': '0xfff0707f'} +cpop : {'encoding': '011000000010-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbb'], 'match': '0x60201013', 'mask': '0xfff0707f'} +max : {'encoding': '0000101----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0xa006033', 'mask': '0xfe00707f'} +maxu : {'encoding': '0000101----------111-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0xa007033', 'mask': '0xfe00707f'} +min : {'encoding': '0000101----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0xa004033', 'mask': '0xfe00707f'} +minu : {'encoding': '0000101----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0xa005033', 'mask': '0xfe00707f'} +sext_b : {'encoding': '011000000100-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbb'], 'match': '0x60401013', 'mask': '0xfff0707f'} +sext_h : {'encoding': '011000000101-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbb'], 'match': '0x60501013', 'mask': '0xfff0707f'} +rol : {'encoding': '0110000----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0x60001033', 'mask': '0xfe00707f'} +ror : {'encoding': '0110000----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0x60005033', 'mask': '0xfe00707f'} +bfpw : {'encoding': '0100100----------111-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbf'], 'match': '0x4800703b', 'mask': '0xfe00707f'} +mul : {'encoding': '0000001----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2000033', 'mask': '0xfe00707f'} +mulh : {'encoding': '0000001----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2001033', 'mask': '0xfe00707f'} +mulhsu : {'encoding': '0000001----------010-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2002033', 'mask': '0xfe00707f'} +mulhu : {'encoding': '0000001----------011-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2003033', 'mask': '0xfe00707f'} +div : {'encoding': '0000001----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2004033', 'mask': '0xfe00707f'} +divu : {'encoding': '0000001----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2005033', 'mask': '0xfe00707f'} +rem : {'encoding': '0000001----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2006033', 'mask': '0xfe00707f'} +remu : {'encoding': '0000001----------111-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2007033', 'mask': '0xfe00707f'} +aes64esm : {'encoding': '0011011----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zkne'], 'match': '0x36000033', 'mask': '0xfe00707f'} +aes64es : {'encoding': '0011001----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zkne'], 'match': '0x32000033', 'mask': '0xfe00707f'} +bcompress : {'encoding': '0000100----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbe'], 'match': '0x8006033', 'mask': '0xfe00707f'} +bdecompress : {'encoding': '0100100----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbe'], 'match': '0x48006033', 'mask': '0xfe00707f'} +pack : {'encoding': '0000100----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbe'], 'match': '0x8004033', 'mask': '0xfe00707f'} +packh : {'encoding': '0000100----------111-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbe'], 'match': '0x8007033', 'mask': '0xfe00707f'} +c_jal : {'encoding': '----------------001-----------01', 'variable_fields': ['c_imm12'], 'extension': ['rv32_c'], 'match': '0x2001', 'mask': '0xe003'} +clmul : {'encoding': '0000101----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbc'], 'match': '0xa001033', 'mask': '0xfe00707f'} +clmulr : {'encoding': '0000101----------010-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbc'], 'match': '0xa002033', 'mask': '0xfe00707f'} +clmulh : {'encoding': '0000101----------011-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbc'], 'match': '0xa003033', 'mask': '0xfe00707f'} +cbo_clean : {'encoding': '000000000001-----010000000001111', 'variable_fields': ['rs1'], 'extension': ['rv_zicbo'], 'match': '0x10200f', 'mask': '0xfff07fff'} +cbo_flush : {'encoding': '000000000010-----010000000001111', 'variable_fields': ['rs1'], 'extension': ['rv_zicbo'], 'match': '0x20200f', 'mask': '0xfff07fff'} +cbo_inval : {'encoding': '000000000000-----010000000001111', 'variable_fields': ['rs1'], 'extension': ['rv_zicbo'], 'match': '0x200f', 'mask': '0xfff07fff'} +cbo_zero : {'encoding': '000000000100-----010000000001111', 'variable_fields': ['rs1'], 'extension': ['rv_zicbo'], 'match': '0x40200f', 'mask': '0xfff07fff'} +csrrw : {'encoding': '-----------------001-----1110011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_zicsr'], 'match': '0x1073', 'mask': '0x707f'} +csrrs : {'encoding': '-----------------010-----1110011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_zicsr'], 'match': '0x2073', 'mask': '0x707f'} +csrrc : {'encoding': '-----------------011-----1110011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_zicsr'], 'match': '0x3073', 'mask': '0x707f'} +csrrwi : {'encoding': '-----------------101-----1110011', 'variable_fields': ['rd', 'imm12', 'zimm'], 'extension': ['rv_zicsr'], 'match': '0x5073', 'mask': '0x707f'} +csrrsi : {'encoding': '-----------------110-----1110011', 'variable_fields': ['rd', 'imm12', 'zimm'], 'extension': ['rv_zicsr'], 'match': '0x6073', 'mask': '0x707f'} +csrrci : {'encoding': '-----------------111-----1110011', 'variable_fields': ['rd', 'imm12', 'zimm'], 'extension': ['rv_zicsr'], 'match': '0x7073', 'mask': '0x707f'} +crc32_d : {'encoding': '011000010011-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zbr'], 'match': '0x61301013', 'mask': '0xfff0707f'} +crc32c_d : {'encoding': '011000011011-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zbr'], 'match': '0x61b01013', 'mask': '0xfff0707f'} +mret : {'encoding': '00110000001000000000000001110011', 'variable_fields': [], 'extension': ['rv_system'], 'match': '0x30200073', 'mask': '0xffffffff'} +dret : {'encoding': '01111011001000000000000001110011', 'variable_fields': [], 'extension': ['rv_system'], 'match': '0x7b200073', 'mask': '0xffffffff'} +wfi : {'encoding': '00010000010100000000000001110011', 'variable_fields': [], 'extension': ['rv_system'], 'match': '0x10500073', 'mask': '0xffffffff'} +flw : {'encoding': '-----------------010-----0000111', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_f'], 'match': '0x2007', 'mask': '0x707f'} +fsw : {'encoding': '-----------------010-----0100111', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv_f'], 'match': '0x2027', 'mask': '0x707f'} +fmadd_s : {'encoding': '-----00------------------1000011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_f'], 'match': '0x43', 'mask': '0x600007f'} +fmsub_s : {'encoding': '-----00------------------1000111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_f'], 'match': '0x47', 'mask': '0x600007f'} +fnmsub_s : {'encoding': '-----00------------------1001011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_f'], 'match': '0x4b', 'mask': '0x600007f'} +fnmadd_s : {'encoding': '-----00------------------1001111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_f'], 'match': '0x4f', 'mask': '0x600007f'} +fadd_s : {'encoding': '0000000------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_f'], 'match': '0x53', 'mask': '0xfe00007f'} +fsub_s : {'encoding': '0000100------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_f'], 'match': '0x8000053', 'mask': '0xfe00007f'} +fmul_s : {'encoding': '0001000------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_f'], 'match': '0x10000053', 'mask': '0xfe00007f'} +fdiv_s : {'encoding': '0001100------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_f'], 'match': '0x18000053', 'mask': '0xfe00007f'} +fsqrt_s : {'encoding': '010110000000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_f'], 'match': '0x58000053', 'mask': '0xfff0007f'} +fsgnj_s : {'encoding': '0010000----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0x20000053', 'mask': '0xfe00707f'} +fsgnjn_s : {'encoding': '0010000----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0x20001053', 'mask': '0xfe00707f'} +fsgnjx_s : {'encoding': '0010000----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0x20002053', 'mask': '0xfe00707f'} +fmin_s : {'encoding': '0010100----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0x28000053', 'mask': '0xfe00707f'} +fmax_s : {'encoding': '0010100----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0x28001053', 'mask': '0xfe00707f'} +fcvt_w_s : {'encoding': '110000000000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_f'], 'match': '0xc0000053', 'mask': '0xfff0007f'} +fcvt_wu_s : {'encoding': '110000000001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_f'], 'match': '0xc0100053', 'mask': '0xfff0007f'} +fmv_x_w : {'encoding': '111000000000-----000-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_f'], 'match': '0xe0000053', 'mask': '0xfff0707f'} +feq_s : {'encoding': '1010000----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0xa0002053', 'mask': '0xfe00707f'} +flt_s : {'encoding': '1010000----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0xa0001053', 'mask': '0xfe00707f'} +fle_s : {'encoding': '1010000----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0xa0000053', 'mask': '0xfe00707f'} +fclass_s : {'encoding': '111000000000-----001-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_f'], 'match': '0xe0001053', 'mask': '0xfff0707f'} +fcvt_s_w : {'encoding': '110100000000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_f'], 'match': '0xd0000053', 'mask': '0xfff0007f'} +fcvt_s_wu : {'encoding': '110100000001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_f'], 'match': '0xd0100053', 'mask': '0xfff0007f'} +fmv_w_x : {'encoding': '111100000000-----000-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_f'], 'match': '0xf0000053', 'mask': '0xfff0707f'} +grevi : {'encoding': '011010-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zbp'], 'match': '0x68005013', 'mask': '0xfc00707f'} +gorci : {'encoding': '001010-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zbp'], 'match': '0x28005013', 'mask': '0xfc00707f'} +shfli : {'encoding': '0000100----------001-----0010011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_zbp'], 'match': '0x8001013', 'mask': '0xfe00707f'} +unshfli : {'encoding': '0000100----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_zbp'], 'match': '0x8005013', 'mask': '0xfe00707f'} +packuw : {'encoding': '0100100----------100-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbp'], 'match': '0x4800403b', 'mask': '0xfe00707f'} +gorcw : {'encoding': '0010100----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbp'], 'match': '0x2800503b', 'mask': '0xfe00707f'} +grevw : {'encoding': '0110100----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbp'], 'match': '0x6800503b', 'mask': '0xfe00707f'} +gorciw : {'encoding': '0010100----------101-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_zbp'], 'match': '0x2800501b', 'mask': '0xfe00707f'} +greviw : {'encoding': '0110100----------101-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_zbp'], 'match': '0x6800501b', 'mask': '0xfe00707f'} +shflw : {'encoding': '0000100----------001-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbp'], 'match': '0x800103b', 'mask': '0xfe00707f'} +unshflw : {'encoding': '0000100----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbp'], 'match': '0x800503b', 'mask': '0xfe00707f'} +xperm32 : {'encoding': '0010100----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbp'], 'match': '0x28000033', 'mask': '0xfe00707f'} +fcvt_l_q : {'encoding': '110001100010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_q'], 'match': '0xc6200053', 'mask': '0xfff0007f'} +fcvt_lu_q : {'encoding': '110001100011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_q'], 'match': '0xc6300053', 'mask': '0xfff0007f'} +fcvt_q_l : {'encoding': '110101100010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_q'], 'match': '0xd6200053', 'mask': '0xfff0007f'} +fcvt_q_lu : {'encoding': '110101100011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_q'], 'match': '0xd6300053', 'mask': '0xfff0007f'} +lr_w : {'encoding': '00010--00000-----010-----0101111', 'variable_fields': ['rd', 'rs1', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x1000202f', 'mask': '0xf9f0707f'} +sc_w : {'encoding': '00011------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x1800202f', 'mask': '0xf800707f'} +amoswap_w : {'encoding': '00001------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x800202f', 'mask': '0xf800707f'} +amoadd_w : {'encoding': '00000------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x202f', 'mask': '0xf800707f'} +amoxor_w : {'encoding': '00100------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x2000202f', 'mask': '0xf800707f'} +amoand_w : {'encoding': '01100------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x6000202f', 'mask': '0xf800707f'} +amoor_w : {'encoding': '01000------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x4000202f', 'mask': '0xf800707f'} +amomin_w : {'encoding': '10000------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x8000202f', 'mask': '0xf800707f'} +amomax_w : {'encoding': '10100------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0xa000202f', 'mask': '0xf800707f'} +amominu_w : {'encoding': '11000------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0xc000202f', 'mask': '0xf800707f'} +amomaxu_w : {'encoding': '11100------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0xe000202f', 'mask': '0xf800707f'} +fcvt_l_h : {'encoding': '110001000010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_zfh'], 'match': '0xc4200053', 'mask': '0xfff0007f'} +fcvt_lu_h : {'encoding': '110001000011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_zfh'], 'match': '0xc4300053', 'mask': '0xfff0007f'} +fcvt_h_l : {'encoding': '110101000010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_zfh'], 'match': '0xd4200053', 'mask': '0xfff0007f'} +fcvt_h_lu : {'encoding': '110101000011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_zfh'], 'match': '0xd4300053', 'mask': '0xfff0007f'} +bcompressw : {'encoding': '0000100----------110-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbe'], 'match': '0x800603b', 'mask': '0xfe00707f'} +bdecompressw : {'encoding': '0100100----------110-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbe'], 'match': '0x4800603b', 'mask': '0xfe00707f'} +packw : {'encoding': '0000100----------100-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbe'], 'match': '0x800403b', 'mask': '0xfe00707f'} +sfence_vma : {'encoding': '0001001----------000000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_s'], 'match': '0x12000073', 'mask': '0xfe007fff'} +sret : {'encoding': '00010000001000000000000001110011', 'variable_fields': [], 'extension': ['rv_s'], 'match': '0x10200073', 'mask': '0xffffffff'} +aes64dsm : {'encoding': '0011111----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zknd'], 'match': '0x3e000033', 'mask': '0xfe00707f'} +aes64ds : {'encoding': '0011101----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zknd'], 'match': '0x3a000033', 'mask': '0xfe00707f'} +aes64ks1i : {'encoding': '00110001---------001-----0010011', 'variable_fields': ['rd', 'rs1', 'rnum'], 'extension': ['rv64_zknd'], 'match': '0x31001013', 'mask': '0xff00707f'} +aes64im : {'encoding': '001100000000-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zknd'], 'match': '0x30001013', 'mask': '0xfff0707f'} +aes64ks2 : {'encoding': '0111111----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zknd'], 'match': '0x7e000033', 'mask': '0xfe00707f'} diff --git a/riscv_isac/plugins/riscv_opcodes/opcodes-rvv-pseudo b/riscv_isac/plugins/riscv_opcodes/opcodes-rvv-pseudo new file mode 100644 index 0000000..35cf095 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/opcodes-rvv-pseudo @@ -0,0 +1,18 @@ +# vmv1r.v, vmv2r.v, vmv4r.v, vmv8r.v +@vmvnfr.v 31..26=0x27 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 + +@vl1r.v 31..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +@vl2r.v 31..26=1 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +@vl4r.v 31..26=3 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +@vl8r.v 31..26=7 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 + +@vle1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 +@vse1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 + +@vfredsum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +@vfwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 + +@vpopc.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 + +@vmornot.mm 31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +@vmandnot.mm 31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 diff --git a/riscv_isac/plugins/riscv_opcodes/parse.py b/riscv_isac/plugins/riscv_opcodes/parse.py new file mode 100755 index 0000000..7044d6d --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/parse.py @@ -0,0 +1,779 @@ +#!/usr/bin/env python + +import json +from constants import * +import re +import glob +import os +import pprint +import logging +import collections +import yaml + +pp = pprint.PrettyPrinter(indent=2) +logging.basicConfig(level=logging.INFO, format='%(levelname)s:: %(message)s') + +def process_enc_line(line, ext): + ''' + This function processes each line of the encoding files (rv*). As part of + the processing, the function ensures that the encoding is legal through the + following checks:: + + - there is no over specification (same bits assigned different values) + - there is no under specification (some bits not assigned values) + - bit ranges are in the format hi..lo=val where hi > lo + - value assigned is representable in the bit range + - also checks that the mapping of arguments of an instruction exists in + arg_lut. + + If the above checks pass, then the function returns a tuple of the name and + a dictionary containing basic information of the instruction which includes: + - variables: list of arguments used by the instruction whose mapping + exists in the arg_lut dictionary + - encoding: this contains the 32-bit encoding of the instruction where + '-' is used to represent position of arguments and 1/0 is used to + reprsent the static encoding of the bits + - extension: this field contains the rv* filename from which this + instruction was included + - match: hex value representing the bits that need to match to detect + this instruction + - mask: hex value representin the bits that need to be masked to extract + the value required for matching. + ''' + single_dict = {} + + # fill all bits with don't care. we use '-' to represent don't care + # TODO: hardcoded for 32-bits. + encoding = ['-'] * 32 + + # get the name of instruction by splitting based on the first space + [name, remaining] = line.split(' ', 1) + + # replace dots with underscores as dot doesn't work with C/Sverilog, etc + name = name.replace('.', '_') + + # remove leading whitespaces + remaining = remaining.lstrip() + + # check each field for it's length and overlapping bits + # ex: 1..0=5 will result in an error --> x overlapping bits + temp_instr = ['-'] * 32 + entries = [ + x[0] for x in re.findall( + r'((\d)+\.\.(\d)+\=((0b\d+)|(0x\d+)|(\d)+))*', + remaining) if x[0] != '' + ] + for temp_entry in entries: + entry = temp_entry.split('=')[0] + f1, f2 = entry.split('..') + for ind in range(int(f1), int(f2)): + + # overlapping bits + if temp_instr[ind] == 'X': + logging.error( + f'{line.split(" ")[0]:<10} has {ind} bit overlapping in it\'s opcodes' + ) + raise SystemExit(1) + temp_instr[ind] = 'X' + + # check x < y + if int(f1) < int(f2): + logging.error( + f'{line.split(" ")[0]:<10} has position {f1} less than position {f2} in it\'s encoding' + ) + raise SystemExit(1) + + # illegal value assigned as per bit width + entry_value = temp_entry.split('=')[1] + temp_base = 16 if 'x' in entry_value else 2 if 'b' in entry_value else 10 + if len(str(int(entry_value, + temp_base))[2:]) > (int(f1) - int(f2)): + logging.error( + f'{line.split(" ")[0]:<10} has an illegal value {entry_value} assigned as per the bit width {f1 - f2}' + ) + raise SystemExit(1) + + # extract bit pattern assignments of the form hi..lo=val. fixed_ranges is a + # regex expression present in constants.py. The extracted patterns are + # captured as a list in args where each entry is a tuple (msb, lsb, value) + args = fixed_ranges.sub(' ', remaining) + + # parse through the args and assign constants 1/0 to bits which need to be + # hardcoded for this instruction + for (msb, lsb, value) in fixed_ranges.findall(remaining): + value = int(value, 0) + msb = int(msb, 0) + lsb = int(lsb, 0) + value = f"{value:032b}" + for i in range(0, msb - lsb + 1): + encoding[31 - (i + lsb)] = value[31 - i] + + # do the same as above but for = pattern. single_fixed is a regex + # expression present in constants.py + for (lsb, value, drop) in single_fixed.findall(remaining): + lsb = int(lsb, 0) + value = int(value, 0) + encoding[31 - lsb] = str(value) + + # convert the list of encodings into a single string for match and mask + match = "".join(encoding).replace('-','0') + mask = "".join(encoding).replace('0','1').replace('-','0') + + # check if all args of the instruction are present in arg_lut present in + # constants.py + args = single_fixed.sub(' ', args).split() + for a in args: + if a not in arg_lut: + logging.error(f' Found variable {a} in instruction {name} whose mapping in arg_lut does not exist') + raise SystemExit(1) + + # update the fields of the instruction as a dict and return back along with + # the name of the instruction + single_dict['encoding'] = "".join(encoding) + single_dict['variable_fields'] = args + single_dict['extension'] = [ext.split('/')[-1]] + single_dict['match']=hex(int(match,2)) + single_dict['mask']=hex(int(mask,2)) + + return (name, single_dict) + + +def create_inst_dict(file_filter): + ''' + This function return a dictionary containing all instructions associated + with an extension defined by the file_filter input. The file_filter input + needs to be rv* file name with out the 'rv' prefix i.e. '_i', '32_i', etc. + + Each node of the dictionary will correspond to an instruction which again is + a dictionary. The dictionary contents of each instruction includes: + - variables: list of arguments used by the instruction whose mapping + exists in the arg_lut dictionary + - encoding: this contains the 32-bit encoding of the instruction where + '-' is used to represent position of arguments and 1/0 is used to + reprsent the static encoding of the bits + - extension: this field contains the rv* filename from which this + instruction was included + - match: hex value representing the bits that need to match to detect + this instruction + - mask: hex value representin the bits that need to be masked to extract + the value required for matching. + + In order to build this dictionary, the function does 2 passes over the same + rv file. The first pass is to extract all standard + instructions. In this pass, all pseudo ops and imported instructions are + skipped. For each selected line of the file, we call process_enc_line + function to create the above mentioned dictionary contents of the + instruction. Checks are performed in this function to ensure that the same + instruction is not added twice to the overall dictionary. + + In the second pass, this function parses only pseudo_ops. For each pseudo_op + this function checks if the dependent extension and instruction, both, exit + before parsing it. The pseudo op is only added to the overall dictionary is + the dependent instruction is not present in the dictionary, else its + skipped. + + + ''' + opcodes_dir = f'./' + filtered_inst = {} + + # file_names contains all files to be parsed in the riscv-opcodes directory + file_names = glob.glob(f'{opcodes_dir}rv{file_filter}') + + # first pass if for standard/original instructions + logging.debug('Collecting standard instructions first') + for f in file_names: + logging.debug(f'Parsing File: {f}') + with open(f) as fp: + lines = (line.rstrip() + for line in fp) # All lines including the blank ones + lines = list(line for line in lines if line) # Non-blank lines + lines = list( + line for line in lines + if not line.startswith("#")) # remove comment lines + + # go through each line of the file + for line in lines: + # if the an instruction needs to be imported then go to the + # respective file and pick the line that has the instruction. + # The variable 'line' will now point to the new line from the + # imported file + + # ignore all lines starting with $import and $pseudo + if '$import' in line or '$pseudo' in line: + continue + logging.debug(f' Processing line: {line}') + + # call process_enc_line to get the data about the current + # instruction + (name, single_dict) = process_enc_line(line, f) + + # if an instruction has already been added to the filtered + # instruction dictionary throw an error saying the given + # instruction is already imported and raise SystemExit + if name in filtered_inst: + var = filtered_inst[name]["extension"] + if filtered_inst[name]['encoding'] != single_dict['encoding']: + err_msg = f'instruction : {name} from ' + err_msg += f'{f.split("/")[-1]} is already ' + err_msg += f'added from {var} but each have different encodings for the same instruction' + logging.error(err_msg) + raise SystemExit(1) + filtered_inst[name]['extension'].append(single_dict['extension']) + + # update the final dict with the instruction + filtered_inst[name] = single_dict + + # second pass if for pseudo instructions + logging.debug('Collecting pseudo instructions now') + for f in file_names: + logging.debug(f'Parsing File: {f}') + with open(f) as fp: + lines = (line.rstrip() + for line in fp) # All lines including the blank ones + lines = list(line for line in lines if line) # Non-blank lines + lines = list( + line for line in lines + if not line.startswith("#")) # remove comment lines + + # go through each line of the file + for line in lines: + + # ignore all lines not starting with $pseudo + if '$pseudo' not in line: + continue + logging.debug(f' Processing line: {line}') + + # use the regex pseudo_regex from constants.py to find the dependent + # extension, dependent instruction, the pseudo_op in question and + # its encoding + (ext, orig_inst, pseudo_inst, line) = pseudo_regex.findall(line)[0] + + # check if the file of the dependent extension exist. Throw error if + # it doesn't + if not os.path.exists(ext): + logging.error(f'Pseudo op {pseudo_inst} in {f} depends on {ext} which is not available') + raise SystemExit(1) + + # check if the dependent instruction exist in the dependent + # extension. Else throw error. + found = False + for oline in open(ext): + if not re.findall(f'^\s*{orig_inst}',oline): + continue + else: + found = True + break + if not found: + logging.error(f'Orig instruction {orig_inst} not found in {ext}. Required by pseudo_op {pseudo_inst} present in {f}') + raise SystemExit(1) + + + # add the pseudo_op to the dictionary only if the original + # instruction is not already in the dictionary. + if orig_inst.replace('.','_') not in filtered_inst: + (name, single_dict) = process_enc_line(pseudo_inst + ' ' + line, f) + + if name in filtered_inst: + var = filtered_inst[name]["extension"] + if filtered_inst[name]['encoding'] != single_dict['encoding']: + err_msg = f'instruction : {name} from ' + err_msg += f'{f.split("/")[-1]} is already ' + err_msg += f'added from {var} but each have different encodings for the same instruction' + logging.error(err_msg) + raise SystemExit(1) + filtered_inst[name]['extension'].append(single_dict['extension']) + + # update the final dict with the instruction + filtered_inst[name] = single_dict + else: + logging.debug(f'Skipping pseudo_op {pseudo_inst} since original instruction {orig_inst} already selected in list') + return filtered_inst + +def make_priv_latex_table(): + latex_file = open('priv-instr-table.tex','w') + type_list = ['R-type','I-type'] + system_instr = ['_h','_s','_system','_svinval', '64_h'] + dataset_list = [ (system_instr, 'Trap-Return Instructions',['sret','mret']) ] + dataset_list.append((system_instr, 'Interrupt-Management Instructions',['wfi'])) + dataset_list.append((system_instr, 'Supervisor Memory-Management Instructions',['sfence_vma'])) + dataset_list.append((system_instr, 'Hypervisor Memory-Management Instructions',['hfence_vvma', 'hfence_gvma'])) + dataset_list.append((system_instr, 'Hypervisor Virtual-Machine Load and Store Instructions', + ['hlv_b','hlv_bu', 'hlv_h','hlv_hu', 'hlv_w', 'hlvx_hu', 'hlvx_wu', 'hsv_b', 'hsv_h','hsv_w'])) + dataset_list.append((system_instr, 'Hypervisor Virtual-Machine Load and Store Instructions, RV64 only', ['hlv_wu','hlv_d','hsv_d'])) + dataset_list.append((system_instr, 'Svinval Memory-Management Instructions', ['sinval_vma', 'sfence_w_inval','sfence_inval_ir', 'hinval_vvma','hinval_gvma'])) + caption = '\\caption{RISC-V Privileged Instructions}' + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + latex_file.close() + +def make_latex_table(): + ''' + This function is mean to create the instr-table.tex that is meant to be used + by the riscv-isa-manual. This function basically creates a single latext + file of multiple tables with each table limited to a single page. Only the + last table is assigned a latex-caption. + + For each table we assign a type-list which capture the different instruction + types (R, I, B, etc) that will be required for the table. Then we select the + list of extensions ('_i, '32_i', etc) whose instructions are required to + populate the table. For each extension or collection of extension we can + assign Title, such that in the end they appear as subheadings within + the table (note these are inlined headings and not captions of the table). + + All of the above information is collected/created and sent to + make_ext_latex_table function to dump out the latex contents into a file. + + The last table only has to be given a caption - as per the policy of the + riscv-isa-manual. + ''' + # open the file and use it as a pointer for all further dumps + latex_file = open('instr-table.tex','w') + + # create the rv32i table first. Here we set the caption to empty. We use the + # files rv_i and rv32_i to capture instructions relevant for rv32i + # configuration. The dataset is a list of 3-element tuples : + # (list_of_extensions, title, list_of_instructions). If list_of_instructions + # is empty then it indicates that all instructions of the all the extensions + # in list_of_extensions need to be dumped. If not empty, then only the + # instructions listed in list_of_instructions will be dumped into latex. + caption = '' + type_list = ['R-type','I-type','S-type','B-type','U-type','J-type'] + dataset_list = [(['_i','32_i'], 'RV32I Base Instruction Set', [])] + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + type_list = ['R-type','I-type','S-type'] + dataset_list = [(['64_i'], 'RV64I Base Instruction Set (in addition to RV32I)', [])] + dataset_list.append((['_zifencei'], 'RV32/RV64 Zifencei Standard Extension', [])) + dataset_list.append((['_zicsr'], 'RV32/RV64 Zicsr Standard Extension', [])) + dataset_list.append((['_m','32_m'], 'RV32M Standard Extension', [])) + dataset_list.append((['64_m'],'RV64M Standard Extension (in addition to RV32M)', [])) + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + type_list = ['R-type'] + dataset_list = [(['_a'],'RV32A Standard Extension', [])] + dataset_list.append((['64_a'],'RV64A Standard Extension (in addition to RV32A)', [])) + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + type_list = ['R-type','R4-type','I-type','S-type'] + dataset_list = [(['_f'],'RV32F Standard Extension', [])] + dataset_list.append((['64_f'],'RV64F Standard Extension (in addition to RV32F)', [])) + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + type_list = ['R-type','R4-type','I-type','S-type'] + dataset_list = [(['_d'],'RV32D Standard Extension', [])] + dataset_list.append((['64_d'],'RV64D Standard Extension (in addition to RV32D)', [])) + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + type_list = ['R-type','R4-type','I-type','S-type'] + dataset_list = [(['_q'],'RV32Q Standard Extension', [])] + dataset_list.append((['64_q'],'RV64Q Standard Extension (in addition to RV32Q)', [])) + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + caption = '\\caption{Instruction listing for RISC-V}' + type_list = ['R-type','R4-type','I-type','S-type'] + dataset_list = [(['_zfh', '_d_zfh','_q_zfh'],'RV32Zfh Standard Extension', [])] + dataset_list.append((['64_zfh'],'RV64Zfh Standard Extension (in addition to RV32Zfh)', [])) + make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) + + ## The following is demo to show that Compressed instructions can also be + # dumped in the same manner as above + #type_list = [''] + #dataset_list = [(['_c', '32_c', '32_c_f','_c_d'],'RV32C Standard Extension', [])] + #dataset_list.append((['64_c'],'RV64C Standard Extension (in addition to RV32C)', [])) + #make_ext_latex_table(type_list, dataset_list, latex_file, 16, caption) + + latex_file.close() + +def make_ext_latex_table(type_list, dataset, latex_file, ilen, caption): + ''' + For a given collection of extensions this function dumps out a complete + latex table which includes the encodings of the instructions. + + The ilen input indicates the length of the instruction for which the table + is created. + + The caption input is used to create the latex-table caption. + + The type_list input is a list of instruction types (R, I, B, etc) that are + treated as header for each table. Each table will have its own requirements + and type_list must include all the instruction-types that the table needs. + Note, all elements of this list must be present in the latex_inst_type + dictionary defined in constants.py + + The latex_file is a file pointer to which the latex-table will dumped into + + The dataset is a list of 3-element tuples containing: + (list_of_extensions, title, list_of_instructions) + The list_of_extensions must contain all the set of extensions whose + instructions must be populated under a given title. If list_of_instructions + is not empty, then only those instructions mentioned in list_of_instructions + present in the extension will be dumped into the latex-table, other + instructions will be ignored. + + Once the above inputs are received then function first creates table entries + for the instruction types. To simplify things, we maintain a dictionary + called latex_inst_type in constants.py which is created in the same way the + instruction dictionary is created. This allows us to re-use the same logic + to create the instruction types table as well + + Once the header is created, we then parse through every entry in the + dataset. For each list dataset entry we use the create_inst_dict function to + create an exhaustive list of instructions associated with the respective + collection of the extension of that dataset. Then we apply the instruction + filter, if any, indicated by the list_of_instructions of that dataset. + Thereon, for each instruction we create a latex table entry. + + Latex table specification for ilen sized instructions: + Each table is created with ilen+1 columns - ilen columns for each bit of the + instruction and one column to hold the name of the instruction. + + For each argument of an instruction we use the arg_lut from constants.py + to identify its position in the encoding, and thus create a multicolumn + entry with the name of the argument as the data. For hardcoded bits, we + do the same where we capture a string of continuous 1s and 0s, identify + the position and assign the same string as the data of the + multicolumn entry in the table. + + ''' + column_size = "".join(['p{0.002in}']*(ilen+1)) + + type_entries = ''' + \\multicolumn{3}{l}{31} & + \\multicolumn{2}{r}{27} & + \\multicolumn{1}{c}{26} & + \\multicolumn{1}{r}{25} & + \\multicolumn{3}{l}{24} & + \\multicolumn{2}{r}{20} & + \\multicolumn{3}{l}{19} & + \\multicolumn{2}{r}{15} & + \\multicolumn{2}{l}{14} & + \\multicolumn{1}{r}{12} & + \\multicolumn{4}{l}{11} & + \\multicolumn{1}{r}{7} & + \\multicolumn{6}{l}{6} & + \\multicolumn{1}{r}{0} \\\\ + \\cline{2-33}\n& \n\n +''' if ilen == 32 else ''' + \\multicolumn{1}{c}{15} & + \\multicolumn{1}{c}{14} & + \\multicolumn{1}{c}{13} & + \\multicolumn{1}{c}{12} & + \\multicolumn{1}{c}{11} & + \\multicolumn{1}{c}{10} & + \\multicolumn{1}{c}{9} & + \\multicolumn{1}{c}{8} & + \\multicolumn{1}{c}{7} & + \\multicolumn{1}{c}{6} & + \\multicolumn{1}{c}{5} & + \\multicolumn{1}{c}{4} & + \\multicolumn{1}{c}{3} & + \\multicolumn{1}{c}{2} & + \\multicolumn{1}{c}{1} & + \\multicolumn{1}{c}{0} \\\\ + \\cline{2-17}\n& \n\n +''' + + # depending on the type_list input we create a subset dictionary of + # latex_inst_type dictionary present in constants.py + type_dict = {key: value for key, value in latex_inst_type.items() if key in type_list} + + # iterate ovr each instruction type and create a table entry + for t in type_dict: + fields = [] + + # first capture all "arguments" of the type (funct3, funct7, rd, etc) + # and capture their positions using arg_lut. + for f in type_dict[t]['variable_fields']: + (msb, lsb) = arg_lut[f] + name = f if f not in latex_mapping else latex_mapping[f] + fields.append((msb, lsb, name)) + + # iterate through the 32 bits, starting from the msb, and assign + # argument names to the relevant portions of the instructions. This + # information is stored as a 3-element tuple containing the msb, lsb + # position of the arugment and the name of the argument. + msb = ilen - 1 + y = '' + for r in range(0,ilen): + if y != '': + fields.append((msb,ilen-1-r+1,y)) + y = '' + msb = ilen-1-r-1 + if r == 31: + if y != '': + fields.append((msb, 0, y)) + y = '' + + # sort the arguments in decreasing order of msb position + fields.sort(key=lambda y: y[0], reverse=True) + + # for each argument/string of 1s or 0s, create a multicolumn latex table + # entry + entry = '' + for r in range(len(fields)): + (msb, lsb, name) = fields[r] + if r == len(fields)-1: + entry += f'\\multicolumn{{ {msb -lsb +1} }}{{|c|}}{{ {name} }} & {t} \\\\ \n' + elif r == 0: + entry += f'\\multicolumn{{ {msb- lsb + 1} }}{{|c|}}{{ {name} }} &\n' + else: + entry += f'\\multicolumn{{ {msb -lsb + 1} }}{{c|}}{{ {name} }} &\n' + entry += f'\\cline{{2-{ilen+1}}}\n&\n\n' + type_entries += entry + + # for each entry in the dataset create a table + content = '' + for (ext_list, title, filter_list) in dataset: + filtered_inst = {} + + # for all extensions list in ext_list, create a dictionary of + # instructions associated with those extensions. + for e in ext_list: + filtered_inst.update(create_inst_dict(e)) + + # if filter_list is not empty then use that as the official set of + # instructions that need to be dumped into the latex table + inst_list = list(filtered_inst.keys()) if not filter_list else filter_list + + # for each instruction create an latex table entry just like how we did + # above with the instruction-type table. + instr_entries = '' + for inst in inst_list: + if inst not in filtered_inst: + logging.error(f'in make_ext_latex_table: Instruction: {inst} not found in filtered_inst dict') + raise SystemExit(1) + fields = [] + + # only if the argument is available in arg_lut we consume it, else + # throw error. + for f in filtered_inst[inst]['variable_fields']: + if f not in arg_lut: + logging.error(f'Found variable {f} in instruction {inst} whose mapping is not available') + raise SystemExit(1) + (msb,lsb) = arg_lut[f] + name = f.replace('_','.') if f not in latex_mapping else latex_mapping[f] + fields.append((msb, lsb, name)) + + msb = ilen -1 + y = '' + for r in range(0,ilen): + if ilen == 16: + encoding = filtered_inst[inst]['encoding'][16:] + else: + encoding = filtered_inst[inst]['encoding'] + x = encoding [r] + if x == '-': + if y != '': + fields.append((msb,ilen-1-r+1,y)) + y = '' + msb = ilen-1-r-1 + else: + y += str(x) + if r == ilen-1: + if y != '': + fields.append((msb, 0, y)) + y = '' + fields.sort(key=lambda y: y[0], reverse=True) + entry = '' + for r in range(len(fields)): + (msb, lsb, name) = fields[r] + if r == len(fields)-1: + entry += f'\\multicolumn{{ {msb -lsb +1} }}{{|c|}}{{ {name} }} & {inst.upper().replace("_",".")} \\\\ \n' + elif r == 0: + entry += f'\\multicolumn{{ {msb- lsb + 1} }}{{|c|}}{{ {name} }} &\n' + else: + entry += f'\\multicolumn{{ {msb -lsb + 1} }}{{c|}}{{ {name} }} &\n' + entry += f'\\cline{{2-{ilen+1}}}\n&\n\n' + instr_entries += entry + + # once an entry of the dataset is completed we create the whole table + # with the title of that dataset as sub-heading (sort-of) + content += f''' + +\\multicolumn{{{ilen}}}{{c}}{{}} & \\\\ +\\multicolumn{{{ilen}}}{{c}}{{\\bf {title} }} & \\\\ +\\cline{{2-{ilen+1}}} + + & +{instr_entries} +''' + + + header = f''' +\\newpage + +\\begin{{table}}[p] +\\begin{{small}} +\\begin{{center}} + \\begin{{tabular}} {{{column_size}l}} + {" ".join(['&']*ilen)} \\\\ + + & +{type_entries} +''' + endtable=f''' + +\\end{{tabular}} +\\end{{center}} +\\end{{small}} +{caption} +\\end{{table}} +''' + # dump the contents and return + latex_file.write(header+content+endtable) + + +def make_chisel(filtered_inst): + + chisel_names='' + cause_names_str='' + csr_names_str = '' + for i in filtered_inst: + chisel_names += f' def {i.upper().replace(".","_"):<18s} = BitPat("b{filtered_inst[i]["encoding"].replace("-","?")}")\n' + for num, name in causes: + cause_names_str += f' val {name.lower().replace(" ","_")} = {hex(num)}\n' + cause_names_str += ''' val all = { + val res = collection.mutable.ArrayBuffer[Int]() +''' + for num, name in causes: + cause_names_str += f' res += {name.lower().replace(" ","_")}\n' + cause_names_str += ''' res.toArray + }''' + + for num, name in csrs+csrs32: + csr_names_str += f' val {name} = {hex(num)}\n' + csr_names_str += ''' val all = { + val res = collection.mutable.ArrayBuffer[Int]() +''' + for num, name in csrs: + csr_names_str += f''' res += {name}\n''' + csr_names_str += ''' res.toArray + } + val all32 = { + val res = collection.mutable.ArrayBuffer(all:_*) +''' + for num, name in csrs32: + csr_names_str += f''' res += {name}\n''' + csr_names_str += ''' res.toArray + }''' + + chisel_file = open('inst.chisel','w') + chisel_file.write(f''' +/* Automatically generated by parse_opcodes */ +object Instructions {{ +{chisel_names} +}} +object Causes {{ +{cause_names_str} +}} +object CSRs {{ +{csr_names_str} +}} +''') + chisel_file.close() + +def make_rust(filtered_inst): + mask_match_str= '' + for i in filtered_inst: + mask_match_str += f'const MATCH_{i.upper().replace(".","_")}: u32 = {(filtered_inst[i]["match"])};\n' + mask_match_str += f'const MASK_{i.upper().replace(".","_")}: u32 = {(filtered_inst[i]["mask"])};\n' + for num, name in csrs+csrs32: + mask_match_str += f'const CSR_{name.upper()}: u16 = {hex(num)};\n' + for num, name in causes: + mask_match_str += f'const CAUSE_{name.upper().replace(" ","_")}: u8 = {hex(num)};\n' + rust_file = open('inst.rs','w') + rust_file.write(f''' +/* Automatically generated by parse_opcodes */ +{mask_match_str} +''') + rust_file.close() + +def make_sverilog(filtered_inst): + names_str = '' + for i in filtered_inst: + names_str += f" localparam [31:0] {i.upper().replace('.','_'):<18s} = 32'b{filtered_inst[i]['encoding'].replace('-','?')};\n" + names_str += ' /* CSR Addresses */\n' + for num, name in csrs+csrs32: + names_str += f" localparam logic [11:0] CSR_{name.upper()} = 12'h{hex(num)[2:]};\n" + + sverilog_file = open('inst.sverilog','w') + sverilog_file.write(f''' +/* Automatically generated by parse_opcodes */ +package riscv_instr; +{names_str} +endpackage +''') + sverilog_file.close() +def make_c(filtered_inst): + mask_match_str = '' + declare_insn_str = '' + for i in filtered_inst: + mask_match_str += f'#define MATCH_{i.upper().replace(".","_")} {filtered_inst[i]["match"]}\n' + mask_match_str += f'#define MASK_{i.upper().replace(".","_")} {filtered_inst[i]["mask"]}\n' + declare_insn_str += f'DECLARE_INSN({i.replace(".","_")}, MATCH_{i.upper().replace(".","_")}, MASK_{i.upper().replace(".","_")})\n' + + csr_names_str = '' + declare_csr_str = '' + for num, name in csrs+csrs32: + csr_names_str += f'#define CSR_{name.upper()} {hex(num)}\n' + declare_csr_str += f'DECLARE_CSR({name}, CSR_{name.upper()})\n' + + causes_str= '' + declare_cause_str = '' + for num, name in causes: + causes_str += f"#define CAUSE_{name.upper().replace(' ', '_')} {hex(num)}\n" + declare_cause_str += f"DECLARE_CAUSE(\"{name}\", CAUSE_{name.upper().replace(' ','_')})\n" + + with open('encoding.h', 'r') as file: + enc_header = file.read() + + enc_file = open('encoding.out.h','w') + enc_file.write(f''' +/* +* This file is auto-generated by running xxx in +* https://github.com/riscv/riscv-opcodes (xxxxxx) +*/ +{enc_header} +/* Automatically generated by parse_opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +{mask_match_str} +{csr_names_str} +{causes_str} +#endif +#ifdef DECLARE_INSN +{declare_insn_str} +#endif +#ifdef DECLARE_CSR +{declare_csr_str} +#endif +#ifdef DECLARE_CAUSE +{declare_cause_str} +#endif +''') + enc_file.close() + +if __name__ == "__main__": + filtered_inst = create_inst_dict('*') + f = open('convert.txt', 'w+') + for key, val in filtered_inst.items(): + f.write(f'{key} : {val}\n') + f.close() + + with open('filtered_inst.yaml', 'w') as outfile: + yaml.dump(filtered_inst, outfile, default_flow_style=False) + filtered_inst = collections.OrderedDict(sorted(filtered_inst.items())) + make_c(filtered_inst) + logging.info('encoding.out.h generated successfully') + make_chisel(filtered_inst) + logging.info('inst.chisel generated successfully') + make_sverilog(filtered_inst) + logging.info('inst.sverilog generated successfully') + make_rust(filtered_inst) + logging.info('inst.rs generated successfully') + make_latex_table() + logging.info('instr-table.tex generated successfully') + make_priv_latex_table() + logging.info('priv-instr-table.tex generated Successfully') diff --git a/riscv_isac/plugins/riscv_opcodes/rv128_c b/riscv_isac/plugins/riscv_opcodes/rv128_c new file mode 100644 index 0000000..beb6cd6 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv128_c @@ -0,0 +1,15 @@ +# quadrant 0 +c.lq rd_p rs1_p c_uimm9lo c_uimm9hi 1..0=0 15..13=1 +c.ld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=3 +c.sq rs1_p rs2_p c_uimm9hi c_uimm9lo 1..0=0 15..13=5 +c.sd rs1_p rs2_p c_uimm8hi c_uimm8lo 1..0=0 15..13=7 + +#quadrant 1 +c.addiw rd_rs1 c_imm6lo c_imm6hi 1..0=1 15..13=1 + +#quadrant 2 +c.lqsp rd c_uimm10sphi c_uimm10splo 1..0=2 15..13=1 +c.ldsp rd_n0 c_uimm9sphi c_uimm9splo 1..0=2 15..13=3 +c.sqsp c_rs2 c_uimm10sp_s 1..0=2 15..13=5 +c.sdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=7 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_c b/riscv_isac/plugins/riscv_opcodes/rv32_c new file mode 100644 index 0000000..d9a9072 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_c @@ -0,0 +1,5 @@ +# quadrant 1 +c.jal c_imm12 1..0=1 15..13=1 +$pseudo_op rv64_c::c.srli c.srli rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=0 +$pseudo_op rv64_c::c.srai c.srai rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=1 +$pseudo_op rv64_c::c.slli c.slli rd_rs1_n0 c_nzuimm6lo 1..0=2 15..12=0 diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_c_f b/riscv_isac/plugins/riscv_opcodes/rv32_c_f new file mode 100644 index 0000000..8487c9a --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_c_f @@ -0,0 +1,8 @@ +# quadrant 0 +c.flw rd_p rs1_p c_uimm7lo c_uimm7hi 1..0=0 15..13=3 +c.fsw rs1_p rs2_p c_uimm7lo c_uimm7hi 1..0=0 15..13=7 + +#quadrant 2 +c.flwsp rd c_uimm8sphi c_uimm8splo 1..0=2 15..13=3 +c.fswsp c_rs2 c_uimm8sp_s 1..0=2 15..13=7 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_i b/riscv_isac/plugins/riscv_opcodes/rv32_i new file mode 100644 index 0000000..28d371a --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_i @@ -0,0 +1,4 @@ +$pseudo_op rv64_i::slli slli rd rs1 shamtw 31..25=0 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv64_i::srli srli rd rs1 shamtw 31..25=0 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_i::srai srai rd rs1 shamtw 31..25=32 14..12=5 6..2=0x04 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_p b/riscv_isac/plugins/riscv_opcodes/rv32_p new file mode 100644 index 0000000..b2172f5 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_p @@ -0,0 +1,3 @@ +add64 31..25=0b1100000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +sub64 31..25=0b1100001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zbb b/riscv_isac/plugins/riscv_opcodes/rv32_zbb new file mode 100644 index 0000000..cadea09 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_zbb @@ -0,0 +1,3 @@ +$pseudo_op rv_zbe::pack zext.h rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..0=0x33 +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13 +$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zbkb b/riscv_isac/plugins/riscv_opcodes/rv32_zbkb new file mode 100644 index 0000000..f791453 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_zbkb @@ -0,0 +1,4 @@ +$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 +$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13 diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zbp b/riscv_isac/plugins/riscv_opcodes/rv32_zbp new file mode 100644 index 0000000..ac8a564 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_zbp @@ -0,0 +1,7 @@ +$pseudo_op rv64_zbp::grevi grevi rd rs1 31..25=0x34 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::gorci gorci rd rs1 31..25=0x14 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::shfli shfli rd rs1 31..25=4 24=0 shamtw4 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::unshfli unshfli rd rs1 31..25=4 24=0 shamtw4 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 + + diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zbpbo b/riscv_isac/plugins/riscv_opcodes/rv32_zbpbo new file mode 100644 index 0000000..6ecc566 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_zbpbo @@ -0,0 +1,5 @@ +$import rv_zbb::clz +$import rv_zbt::fsr +$import rv32_zbt::fsri +$pseudo_op rv64_zbp::grevi rev rd rs1 31..20=0x69F 14..12=5 6..0=0x13 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zbs b/riscv_isac/plugins/riscv_opcodes/rv32_zbs new file mode 100644 index 0000000..14ac441 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_zbs @@ -0,0 +1,5 @@ +$pseudo_op rv64_zbs::bclri bclri rd rs1 31..25=0x24 shamtw 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv64_zbs::bexti bexti rd rs1 31..25=0x24 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbs::binvi binvi rd rs1 31..25=0x34 shamtw 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv64_zbs::bseti bseti rd rs1 31..25=0x14 shamtw 14..12=1 6..2=0x04 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zbt b/riscv_isac/plugins/riscv_opcodes/rv32_zbt new file mode 100644 index 0000000..4b5a286 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_zbt @@ -0,0 +1,2 @@ +$pseudo_op rv64_zbt::fsri fsri rd rs1 rs3 26=1 25=0 shamtw 14..12=5 6..2=0x04 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zk b/riscv_isac/plugins/riscv_opcodes/rv32_zk new file mode 100644 index 0000000..e491103 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_zk @@ -0,0 +1,25 @@ +#import zbkb +$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 +$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13 + +#import zkne +$import rv32_zkne::aes32esmi +$import rv32_zkne::aes32esi + +#import zknd +# Scalar AES - RV32 +$import rv32_zknd::aes32dsmi +$import rv32_zknd::aes32dsi + + +#import zknh +# Scalar SHA512 - RV32 +$import rv32_zknh::sha512sum0r +$import rv32_zknh::sha512sum1r +$import rv32_zknh::sha512sig0l +$import rv32_zknh::sha512sig0h +$import rv32_zknh::sha512sig1l +$import rv32_zknh::sha512sig1h + diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zkn b/riscv_isac/plugins/riscv_opcodes/rv32_zkn new file mode 100644 index 0000000..e491103 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_zkn @@ -0,0 +1,25 @@ +#import zbkb +$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 +$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13 + +#import zkne +$import rv32_zkne::aes32esmi +$import rv32_zkne::aes32esi + +#import zknd +# Scalar AES - RV32 +$import rv32_zknd::aes32dsmi +$import rv32_zknd::aes32dsi + + +#import zknh +# Scalar SHA512 - RV32 +$import rv32_zknh::sha512sum0r +$import rv32_zknh::sha512sum1r +$import rv32_zknh::sha512sig0l +$import rv32_zknh::sha512sig0h +$import rv32_zknh::sha512sig1l +$import rv32_zknh::sha512sig1h + diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zknd b/riscv_isac/plugins/riscv_opcodes/rv32_zknd new file mode 100644 index 0000000..f367d5e --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_zknd @@ -0,0 +1,4 @@ +# Scalar AES - RV32 +aes32dsmi rd rs1 rs2 bs 29..25=0b10111 14..12=0 6..0=0x33 +aes32dsi rd rs1 rs2 bs 29..25=0b10101 14..12=0 6..0=0x33 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zkne b/riscv_isac/plugins/riscv_opcodes/rv32_zkne new file mode 100644 index 0000000..72bd617 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_zkne @@ -0,0 +1,5 @@ +# Scalar AES - RV32 + +aes32esmi rd rs1 rs2 bs 29..25=0b10011 14..12=0 6..0=0x33 +aes32esi rd rs1 rs2 bs 29..25=0b10001 14..12=0 6..0=0x33 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zknh b/riscv_isac/plugins/riscv_opcodes/rv32_zknh new file mode 100644 index 0000000..675bf54 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_zknh @@ -0,0 +1,8 @@ +# Scalar SHA512 - RV32 +sha512sum0r rd rs1 rs2 31..30=1 29..25=0b01000 14..12=0 6..0=0x33 +sha512sum1r rd rs1 rs2 31..30=1 29..25=0b01001 14..12=0 6..0=0x33 +sha512sig0l rd rs1 rs2 31..30=1 29..25=0b01010 14..12=0 6..0=0x33 +sha512sig0h rd rs1 rs2 31..30=1 29..25=0b01110 14..12=0 6..0=0x33 +sha512sig1l rd rs1 rs2 31..30=1 29..25=0b01011 14..12=0 6..0=0x33 +sha512sig1h rd rs1 rs2 31..30=1 29..25=0b01111 14..12=0 6..0=0x33 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zks b/riscv_isac/plugins/riscv_opcodes/rv32_zks new file mode 100644 index 0000000..034c532 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv32_zks @@ -0,0 +1,6 @@ +#import zbkb +$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 +$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_a b/riscv_isac/plugins/riscv_opcodes/rv64_a new file mode 100644 index 0000000..fe208e9 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_a @@ -0,0 +1,12 @@ +# RV64A additions to RV32A +lr.d rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=3 6..2=0x0B 1..0=3 +sc.d rd rs1 rs2 aq rl 31..29=0 28..27=3 14..12=3 6..2=0x0B 1..0=3 +amoswap.d rd rs1 rs2 aq rl 31..29=0 28..27=1 14..12=3 6..2=0x0B 1..0=3 +amoadd.d rd rs1 rs2 aq rl 31..29=0 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amoxor.d rd rs1 rs2 aq rl 31..29=1 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amoand.d rd rs1 rs2 aq rl 31..29=3 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amoor.d rd rs1 rs2 aq rl 31..29=2 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amomin.d rd rs1 rs2 aq rl 31..29=4 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amomax.d rd rs1 rs2 aq rl 31..29=5 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amominu.d rd rs1 rs2 aq rl 31..29=6 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amomaxu.d rd rs1 rs2 aq rl 31..29=7 28..27=0 14..12=3 6..2=0x0B 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_b b/riscv_isac/plugins/riscv_opcodes/rv64_b new file mode 100644 index 0000000..3d01b8c --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_b @@ -0,0 +1,9 @@ +# RV64B additions to RV32B + + +slow rd rs1 rs2 31..25=16 14..12=1 6..2=0x0E 1..0=3 +srow rd rs1 rs2 31..25=16 14..12=5 6..2=0x0E 1..0=3 + +sloiw rd rs1 31..26=8 25=0 shamtw 14..12=1 6..2=0x06 1..0=3 +sroiw rd rs1 31..26=8 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_c b/riscv_isac/plugins/riscv_opcodes/rv64_c new file mode 100644 index 0000000..39d087a --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_c @@ -0,0 +1,17 @@ +# quadrant 0 +c.ld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=3 +c.sd rs1_p rs2_p c_uimm8hi c_uimm8lo 1..0=0 15..13=7 + +#quadrant 1 +c.addiw rd_rs1 c_imm6lo c_imm6hi 1..0=1 15..13=1 +c.srli rd_rs1_p c_nzuimm6lo c_nzuimm6hi 1..0=1 15..13=4 11..10=0 +c.srai rd_rs1_p c_nzuimm6lo c_nzuimm6hi 1..0=1 15..13=4 11..10=1 +c.subw rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b111 6..5=0 +c.addw rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b111 6..5=1 + + +#quadrant 2 +c.slli rd_rs1_n0 c_nzuimm6hi c_nzuimm6lo 1..0=2 15..13=0 +c.ldsp rd_n0 c_uimm9sphi c_uimm9splo 1..0=2 15..13=3 +c.sdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=7 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_d b/riscv_isac/plugins/riscv_opcodes/rv64_d new file mode 100644 index 0000000..d8c8299 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_d @@ -0,0 +1,7 @@ +# RV64D additions to RV32D +fcvt.l.d rd rs1 24..20=2 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.lu.d rd rs1 24..20=3 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 +fmv.x.d rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=1 6..2=0x14 1..0=3 +fcvt.d.l rd rs1 24..20=2 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 +fcvt.d.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 +fmv.d.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=1 6..2=0x14 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_f b/riscv_isac/plugins/riscv_opcodes/rv64_f new file mode 100644 index 0000000..787677c --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_f @@ -0,0 +1,7 @@ +# RV64F additions to RV32F + +fcvt.l.s rd rs1 24..20=2 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.lu.s rd rs1 24..20=3 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.s.l rd rs1 24..20=2 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 +fcvt.s.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_h b/riscv_isac/plugins/riscv_opcodes/rv64_h new file mode 100644 index 0000000..488dcd4 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_h @@ -0,0 +1,5 @@ +# Hypervisor extension +hlv.wu rd rs1 24..20=0x1 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 +hlv.d rd rs1 24..20=0x0 31..25=0x36 14..12=4 6..2=0x1C 1..0=3 +hsv.d 11..7=0 rs1 rs2 31..25=0x37 14..12=4 6..2=0x1C 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_i b/riscv_isac/plugins/riscv_opcodes/rv64_i new file mode 100644 index 0000000..1d88e59 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_i @@ -0,0 +1,17 @@ +# RV64I additions to RV32I + +lwu rd rs1 imm12 14..12=6 6..2=0x00 1..0=3 +ld rd rs1 imm12 14..12=3 6..2=0x00 1..0=3 +sd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x08 1..0=3 +slli rd rs1 31..26=0 shamt 14..12=1 6..2=0x04 1..0=3 +srli rd rs1 31..26=0 shamt 14..12=5 6..2=0x04 1..0=3 +srai rd rs1 31..26=16 shamt 14..12=5 6..2=0x04 1..0=3 +addiw rd rs1 imm12 14..12=0 6..2=0x06 1..0=3 +slliw rd rs1 31..25=0 shamtw 14..12=1 6..2=0x06 1..0=3 +srliw rd rs1 31..25=0 shamtw 14..12=5 6..2=0x06 1..0=3 +sraiw rd rs1 31..25=32 shamtw 14..12=5 6..2=0x06 1..0=3 +addw rd rs1 rs2 31..25=0 14..12=0 6..2=0x0E 1..0=3 +subw rd rs1 rs2 31..25=32 14..12=0 6..2=0x0E 1..0=3 +sllw rd rs1 rs2 31..25=0 14..12=1 6..2=0x0E 1..0=3 +srlw rd rs1 rs2 31..25=0 14..12=5 6..2=0x0E 1..0=3 +sraw rd rs1 rs2 31..25=32 14..12=5 6..2=0x0E 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_m b/riscv_isac/plugins/riscv_opcodes/rv64_m new file mode 100644 index 0000000..cfac0b1 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_m @@ -0,0 +1,6 @@ +# RV64M additions to RV32M +mulw rd rs1 rs2 31..25=1 14..12=0 6..2=0x0E 1..0=3 +divw rd rs1 rs2 31..25=1 14..12=4 6..2=0x0E 1..0=3 +divuw rd rs1 rs2 31..25=1 14..12=5 6..2=0x0E 1..0=3 +remw rd rs1 rs2 31..25=1 14..12=6 6..2=0x0E 1..0=3 +remuw rd rs1 rs2 31..25=1 14..12=7 6..2=0x0E 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_p b/riscv_isac/plugins/riscv_opcodes/rv64_p new file mode 100644 index 0000000..db8ec29 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_p @@ -0,0 +1,81 @@ +add32 31..25=0b0100000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +radd32 31..25=0b0000000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +uradd32 31..25=0b0010000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kadd32 31..25=0b0001000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ukadd32 31..25=0b0011000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +sub32 31..25=0b0100001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +rsub32 31..25=0b0000001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ursub32 31..25=0b0010001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ksub32 31..25=0b0001001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +uksub32 31..25=0b0011001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +cras32 31..25=0b0100010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +rcras32 31..25=0b0000010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +urcras32 31..25=0b0010010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kcras32 31..25=0b0001010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ukcras32 31..25=0b0011010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +crsa32 31..25=0b0100011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +rcrsa32 31..25=0b0000011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +urcrsa32 31..25=0b0010011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kcrsa32 31..25=0b0001011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ukcrsa32 31..25=0b0011011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +stas32 31..25=0b1111000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +rstas32 31..25=0b1011000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +urstas32 31..25=0b1101000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kstas32 31..25=0b1100000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ukstas32 31..25=0b1110000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +stsa32 31..25=0b1111001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +rstsa32 31..25=0b1011001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +urstsa32 31..25=0b1101001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kstsa32 31..25=0b1100001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ukstsa32 31..25=0b1110001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +sra32 31..25=0b0101000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +srai32 31..25=0b0111000 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 +sra32.u 31..25=0b0110000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +srai32.u 31..25=0b1000000 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 +srl32 31..25=0b0101001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +srli32 31..25=0b0111001 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 +srl32.u 31..25=0b0110001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +srli32.u 31..25=0b1000001 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 +sll32 31..25=0b0101010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +slli32 31..25=0b0111010 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 +ksll32 31..25=0b0110010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kslli32 31..25=0b1000010 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 +kslra32 31..25=0b0101011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kslra32.u 31..25=0b0110011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +smin32 31..25=0b1001000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +umin32 31..25=0b1010000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +smax32 31..25=0b1001001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +umax32 31..25=0b1010001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kabs32 31..25=0b1010110 24..20=0b10010 rs1 14..12=0b000 rd 6..0=0b1110111 +khmbb16 31..25=0b1101110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +khmbt16 31..25=0b1110110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +khmtt16 31..25=0b1111110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmbb16 31..25=0b1101101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmbt16 31..25=0b1110101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmtt16 31..25=0b1111101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmabb16 31..25=0b1101100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmabt16 31..25=0b1110100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmatt16 31..25=0b1111100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +# smbb32 is missing +smbt32 31..25=0b0001100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +smtt32 31..25=0b0010100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmabb32 31..25=0b0101101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmabt32 31..25=0b0110101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmatt32 31..25=0b0111101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmda32 31..25=0b0011100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmxda32 31..25=0b0011101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +# kmada32 is missing +kmaxda32 31..25=0b0100101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmads32 31..25=0b0101110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmadrs32 31..25=0b0110110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmaxds32 31..25=0b0111110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmsda32 31..25=0b0100110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kmsxda32 31..25=0b0100111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +smds32 31..25=0b0101100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +smdrs32 31..25=0b0110100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +smxds32 31..25=0b0111100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +sraiw.u 31..25=0b0011010 imm5 rs1 14..12=0b001 rd 6..0=0b1110111 +pkbb32 31..25=0b0000111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +pkbt32 31..25=0b0001111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +pktt32 31..25=0b0010111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +pktb32 31..25=0b0011111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_q b/riscv_isac/plugins/riscv_opcodes/rv64_q new file mode 100644 index 0000000..32019aa --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_q @@ -0,0 +1,8 @@ +# RV64Q additions to RV32Q + +fcvt.l.q rd rs1 24..20=2 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 +fcvt.lu.q rd rs1 24..20=3 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 + +fcvt.q.l rd rs1 24..20=2 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 +fcvt.q.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zba b/riscv_isac/plugins/riscv_opcodes/rv64_zba new file mode 100644 index 0000000..52d9dcd --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zba @@ -0,0 +1,5 @@ +add.uw rd rs1 rs2 31..25=4 14..12=0 6..2=0x0E 1..0=3 +sh1add.uw rd rs1 rs2 31..25=16 14..12=2 6..2=0x0E 1..0=3 +sh2add.uw rd rs1 rs2 31..25=16 14..12=4 6..2=0x0E 1..0=3 +sh3add.uw rd rs1 rs2 31..25=16 14..12=6 6..2=0x0E 1..0=3 +slli.uw rd rs1 31..26=2 shamt 14..12=1 6..2=0x06 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbb b/riscv_isac/plugins/riscv_opcodes/rv64_zbb new file mode 100644 index 0000000..fc19561 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zbb @@ -0,0 +1,9 @@ +clzw rd rs1 31..20=0x600 14..12=1 6..2=0x06 1..0=3 +ctzw rd rs1 31..20=0x601 14..12=1 6..2=0x06 1..0=3 +cpopw rd rs1 31..20=0x602 14..12=1 6..2=0x06 1..0=3 +rolw rd rs1 rs2 31..25=0x30 14..12=1 6..2=0x0E 1..0=3 +rorw rd rs1 rs2 31..25=0x30 14..12=5 6..2=0x0E 1..0=3 +roriw rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x06 1..0=3 +rori rd rs1 31..26=0x18 shamt 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbe::packw zext.h rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..2=0xE 1..0=0x3 +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbe b/riscv_isac/plugins/riscv_opcodes/rv64_zbe new file mode 100644 index 0000000..d36b80c --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zbe @@ -0,0 +1,4 @@ +bcompressw rd rs1 rs2 31..25=4 14..12=6 6..2=0x0E 1..0=3 +bdecompressw rd rs1 rs2 31..25=36 14..12=6 6..2=0x0E 1..0=3 +packw rd rs1 rs2 31..25=4 14..12=4 6..2=0x0E 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbf b/riscv_isac/plugins/riscv_opcodes/rv64_zbf new file mode 100644 index 0000000..d02b59d --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zbf @@ -0,0 +1,3 @@ +bfpw rd rs1 rs2 31..25=36 14..12=7 6..2=0x0E 1..0=3 +$import rv64_zbe::packw + diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbkb b/riscv_isac/plugins/riscv_opcodes/rv64_zbkb new file mode 100644 index 0000000..ad2f4a9 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zbkb @@ -0,0 +1,6 @@ +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 +$import rv64_zbb::rolw +$import rv64_zbb::rorw +$import rv64_zbb::roriw +$import rv64_zbb::rori +$import rv64_zbe::packw diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbm b/riscv_isac/plugins/riscv_opcodes/rv64_zbm new file mode 100644 index 0000000..46a5ebf --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zbm @@ -0,0 +1,7 @@ +bmatflip rd rs1 31..20=0x603 14..12=1 6..2=0x04 1..0=3 +bmator rd rs1 rs2 31..25=4 14..12=3 6..2=0x0C 1..0=3 +bmatxor rd rs1 rs2 31..25=36 14..12=3 6..2=0x0C 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip16 rd rs1 31..25=4 24..20=16 14..12=5 6..2=4 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip8 rd rs1 31..25=4 24..20=24 14..12=5 6..2=4 1..0=3 +$import rv_zbe::pack +$import rv_zbp::packu diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbp b/riscv_isac/plugins/riscv_opcodes/rv64_zbp new file mode 100644 index 0000000..f8c06bd --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zbp @@ -0,0 +1,17 @@ +grevi rd rs1 31..26=26 shamt 14..12=5 6..2=0x04 1..0=3 +gorci rd rs1 31..26=10 shamt 14..12=5 6..2=0x04 1..0=3 +shfli rd rs1 31..26=2 25=0 shamtw 14..12=1 6..2=0x04 1..0=3 +unshfli rd rs1 31..26=2 25=0 shamtw 14..12=5 6..2=0x04 1..0=3 +$import rv64_zbe::packw +packuw rd rs1 rs2 31..25=36 14..12=4 6..2=0x0E 1..0=3 +$import rv64_zbb::rolw +$import rv64_zbb::rorw +$import rv64_zbb::roriw +$import rv64_zbb::rori +gorcw rd rs1 rs2 31..25=20 14..12=5 6..2=0x0E 1..0=3 +grevw rd rs1 rs2 31..25=52 14..12=5 6..2=0x0E 1..0=3 +gorciw rd rs1 31..26=10 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 +greviw rd rs1 31..26=26 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 +shflw rd rs1 rs2 31..25=4 14..12=1 6..2=0x0E 1..0=3 +unshflw rd rs1 rs2 31..25=4 14..12=5 6..2=0x0E 1..0=3 +xperm32 rd rs1 rs2 31..25=20 14..12=0 6..2=0x0C 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbpbo b/riscv_isac/plugins/riscv_opcodes/rv64_zbpbo new file mode 100644 index 0000000..f88bd03 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zbpbo @@ -0,0 +1,2 @@ +$import rv64_zbt::fsrw +$pseudo_op rv64_zbp::grevi rev rd rs1 31..20=0x6BF 14..12=5 6..0=0x13 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbr b/riscv_isac/plugins/riscv_opcodes/rv64_zbr new file mode 100644 index 0000000..3b470f1 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zbr @@ -0,0 +1,3 @@ +crc32.d rd rs1 31..20=0x613 14..12=1 6..2=0x04 1..0=3 +crc32c.d rd rs1 31..20=0x61B 14..12=1 6..2=0x04 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbs b/riscv_isac/plugins/riscv_opcodes/rv64_zbs new file mode 100644 index 0000000..d3203a6 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zbs @@ -0,0 +1,5 @@ +bclri rd rs1 31..26=0x12 shamt 14..12=1 6..2=0x04 1..0=3 +bexti rd rs1 31..26=0x12 shamt 14..12=5 6..2=0x04 1..0=3 +binvi rd rs1 31..26=0x1a shamt 14..12=1 6..2=0x04 1..0=3 +bseti rd rs1 31..26=0x0a shamt 14..12=1 6..2=0x04 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbt b/riscv_isac/plugins/riscv_opcodes/rv64_zbt new file mode 100644 index 0000000..fcb84b5 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zbt @@ -0,0 +1,6 @@ +fslw rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0E 1..0=3 +fsrw rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0E 1..0=3 +fsriw rd rs1 rs3 26..25=2 shamtw 14..12=5 6..2=0x06 1..0=3 +fsri rd rs1 rs3 26=1 shamt 14..12=5 6..2=0x04 1..0=3 + + diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zfh b/riscv_isac/plugins/riscv_opcodes/rv64_zfh new file mode 100644 index 0000000..5cc9f25 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zfh @@ -0,0 +1,7 @@ +# RV64Zfh additions to RV32Zfh + +fcvt.l.h rd rs1 24..20=2 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.lu.h rd rs1 24..20=3 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 + +fcvt.h.l rd rs1 24..20=2 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +fcvt.h.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zk b/riscv_isac/plugins/riscv_opcodes/rv64_zk new file mode 100644 index 0000000..0ebf71d --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zk @@ -0,0 +1,28 @@ +#import zbkb +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 +$import rv64_zbb::rolw +$import rv64_zbb::rorw +$import rv64_zbb::roriw +$import rv64_zbb::rori +$import rv64_zbe::packw + +#import zkne +# Scalar AES - RV64 +$import rv64_zkne::aes64esm +$import rv64_zkne::aes64es +$import rv64_zknd::aes64ks1i +$import rv64_zknd::aes64ks2 + +#import zknd +# Scalar AES - RV64 +$import rv64_zknd::aes64dsm +$import rv64_zknd::aes64ds +$import rv64_zknd::aes64im + +#import zknh +# Scalar SHA512 - RV64 +$import rv64_zknh::sha512sum0 +$import rv64_zknh::sha512sum1 +$import rv64_zknh::sha512sig0 +$import rv64_zknh::sha512sig1 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zkn b/riscv_isac/plugins/riscv_opcodes/rv64_zkn new file mode 100644 index 0000000..0ebf71d --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zkn @@ -0,0 +1,28 @@ +#import zbkb +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 +$import rv64_zbb::rolw +$import rv64_zbb::rorw +$import rv64_zbb::roriw +$import rv64_zbb::rori +$import rv64_zbe::packw + +#import zkne +# Scalar AES - RV64 +$import rv64_zkne::aes64esm +$import rv64_zkne::aes64es +$import rv64_zknd::aes64ks1i +$import rv64_zknd::aes64ks2 + +#import zknd +# Scalar AES - RV64 +$import rv64_zknd::aes64dsm +$import rv64_zknd::aes64ds +$import rv64_zknd::aes64im + +#import zknh +# Scalar SHA512 - RV64 +$import rv64_zknh::sha512sum0 +$import rv64_zknh::sha512sum1 +$import rv64_zknh::sha512sig0 +$import rv64_zknh::sha512sig1 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zknd b/riscv_isac/plugins/riscv_opcodes/rv64_zknd new file mode 100644 index 0000000..f1507d6 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zknd @@ -0,0 +1,7 @@ +# Scalar AES - RV64 +aes64dsm rd rs1 rs2 31..30=0 29..25=0b11111 14..12=0b000 6..0=0x33 +aes64ds rd rs1 rs2 31..30=0 29..25=0b11101 14..12=0b000 6..0=0x33 +aes64ks1i rd rs1 rnum 31..30=0 29..25=0b11000 24=1 14..12=0b001 6..0=0x13 +aes64im rd rs1 31..30=0 29..25=0b11000 24..20=0b0000 14..12=0b001 6..0=0x13 +aes64ks2 rd rs1 rs2 31..30=1 29..25=0b11111 14..12=0b000 6..0=0x33 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zkne b/riscv_isac/plugins/riscv_opcodes/rv64_zkne new file mode 100644 index 0000000..3323b7f --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zkne @@ -0,0 +1,5 @@ +# Scalar AES - RV64 +aes64esm rd rs1 rs2 31..30=0 29..25=0b11011 14..12=0b000 6..0=0x33 +aes64es rd rs1 rs2 31..30=0 29..25=0b11001 14..12=0b000 6..0=0x33 +$import rv64_zknd::aes64ks1i +$import rv64_zknd::aes64ks2 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zknh b/riscv_isac/plugins/riscv_opcodes/rv64_zknh new file mode 100644 index 0000000..431a1bc --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zknh @@ -0,0 +1,6 @@ +# Scalar SHA512 - RV64 +sha512sum0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00100 14..12=1 6..0=0x13 +sha512sum1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00101 14..12=1 6..0=0x13 +sha512sig0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00110 14..12=1 6..0=0x13 +sha512sig1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00111 14..12=1 6..0=0x13 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zks b/riscv_isac/plugins/riscv_opcodes/rv64_zks new file mode 100644 index 0000000..6bbad27 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv64_zks @@ -0,0 +1,7 @@ +#import zbkb +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 +$import rv64_zbb::rolw +$import rv64_zbb::rorw +$import rv64_zbb::roriw +$import rv64_zbb::rori +$import rv64_zbe::packw diff --git a/riscv_isac/plugins/riscv_opcodes/rv_a b/riscv_isac/plugins/riscv_opcodes/rv_a new file mode 100644 index 0000000..1a70e40 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_a @@ -0,0 +1,11 @@ +lr.w rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=2 6..2=0x0B 1..0=3 +sc.w rd rs1 rs2 aq rl 31..29=0 28..27=3 14..12=2 6..2=0x0B 1..0=3 +amoswap.w rd rs1 rs2 aq rl 31..29=0 28..27=1 14..12=2 6..2=0x0B 1..0=3 +amoadd.w rd rs1 rs2 aq rl 31..29=0 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amoxor.w rd rs1 rs2 aq rl 31..29=1 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amoand.w rd rs1 rs2 aq rl 31..29=3 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amoor.w rd rs1 rs2 aq rl 31..29=2 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amomin.w rd rs1 rs2 aq rl 31..29=4 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amomax.w rd rs1 rs2 aq rl 31..29=5 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amominu.w rd rs1 rs2 aq rl 31..29=6 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amomaxu.w rd rs1 rs2 aq rl 31..29=7 28..27=0 14..12=2 6..2=0x0B 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_b b/riscv_isac/plugins/riscv_opcodes/rv_b new file mode 100644 index 0000000..4fe7ef0 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_b @@ -0,0 +1,12 @@ + +slo rd rs1 rs2 31..25=16 14..12=1 6..2=0x0C 1..0=3 +sro rd rs1 rs2 31..25=16 14..12=5 6..2=0x0C 1..0=3 + + +sloi rd rs1 31..26=8 shamt 14..12=1 6..2=0x04 1..0=3 +sroi rd rs1 31..26=8 shamt 14..12=5 6..2=0x04 1..0=3 + + + + + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_c b/riscv_isac/plugins/riscv_opcodes/rv_c new file mode 100644 index 0000000..46b1e1c --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_c @@ -0,0 +1,32 @@ +# quadrant 0 +c.addi4spn rd_p c_nzuimm10 1..0=0 15..13=0 +c.lw rd_p rs1_p c_uimm7lo c_uimm7hi 1..0=0 15..13=2 +c.sw rs1_p rs2_p c_uimm7lo c_uimm7hi 1..0=0 15..13=6 + +#quadrant 1 +c.nop c_nzimm6hi c_nzimm6lo 1..0=1 15..13=0 11..7=0 +c.addi rd_rs1_n0 c_nzimm6lo c_nzimm6hi 1..0=1 15..13=0 +c.li rd c_imm6lo c_imm6hi 1..0=1 15..13=2 +c.addi16sp c_nzimm10hi c_nzimm10lo 1..0=1 15..13=3 11..7=2 +c.lui rd_n2 c_nzimm18hi c_nzimm18lo 1..0=1 15..13=3 +c.andi rd_rs1_p c_imm6hi c_imm6lo 1..0=1 15..13=4 11..10=2 +c.sub rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=0 +c.xor rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=1 +c.or rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=2 +c.and rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=3 +c.j c_imm12 1..0=1 15..13=5 +c.beqz rs1_p c_bimm9lo c_bimm9hi 1..0=1 15..13=6 +c.bnez rs1_p c_bimm9lo c_bimm9hi 1..0=1 15..13=7 + +#quadrant 2 +c.lwsp rd_n0 c_uimm8sphi c_uimm8splo 1..0=2 15..13=2 +c.jr rs1_n0 1..0=2 15..13=4 12=0 6..2=0 +c.mv rd c_rs2_n0 1..0=2 15..13=4 12=0 +c.ebreak 1..0=2 15..13=4 12=1 11..2=0 +c.jalr c_rs1_n0 1..0=2 15..13=4 12=1 6..2=0 +c.add rd_rs1 c_rs2_n0 1..0=2 15..13=4 12=1 +c.swsp c_rs2 c_uimm8sp_s 1..0=2 15..13=6 + + + + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_c_d b/riscv_isac/plugins/riscv_opcodes/rv_c_d new file mode 100644 index 0000000..cd49b44 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_c_d @@ -0,0 +1,8 @@ +#quadrant 0 +c.fld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=1 +c.fsd rs1_p rs2_p c_uimm8lo c_uimm8hi 1..0=0 15..13=5 + +#quadrant 2 +c.fldsp rd c_uimm9sphi c_uimm9splo 1..0=2 15..13=1 +c.fsdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=5 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_custom b/riscv_isac/plugins/riscv_opcodes/rv_custom new file mode 100644 index 0000000..036bc4b --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_custom @@ -0,0 +1,27 @@ +custom0 rd rs1 imm12 14..12=0 6..2=0x02 1..0=3 +custom0.rs1 rd rs1 imm12 14..12=2 6..2=0x02 1..0=3 +custom0.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x02 1..0=3 +custom0.rd rd rs1 imm12 14..12=4 6..2=0x02 1..0=3 +custom0.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x02 1..0=3 +custom0.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x02 1..0=3 + +custom1 rd rs1 imm12 14..12=0 6..2=0x0A 1..0=3 +custom1.rs1 rd rs1 imm12 14..12=2 6..2=0x0A 1..0=3 +custom1.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x0A 1..0=3 +custom1.rd rd rs1 imm12 14..12=4 6..2=0x0A 1..0=3 +custom1.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x0A 1..0=3 +custom1.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x0A 1..0=3 + +custom2 rd rs1 imm12 14..12=0 6..2=0x16 1..0=3 +custom2.rs1 rd rs1 imm12 14..12=2 6..2=0x16 1..0=3 +custom2.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x16 1..0=3 +custom2.rd rd rs1 imm12 14..12=4 6..2=0x16 1..0=3 +custom2.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x16 1..0=3 +custom2.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x16 1..0=3 + +custom3 rd rs1 imm12 14..12=0 6..2=0x1E 1..0=3 +custom3.rs1 rd rs1 imm12 14..12=2 6..2=0x1E 1..0=3 +custom3.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x1E 1..0=3 +custom3.rd rd rs1 imm12 14..12=4 6..2=0x1E 1..0=3 +custom3.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x1E 1..0=3 +custom3.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x1E 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_d b/riscv_isac/plugins/riscv_opcodes/rv_d new file mode 100644 index 0000000..8c3a3d3 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_d @@ -0,0 +1,26 @@ +fld rd rs1 imm12 14..12=3 6..2=0x01 1..0=3 +fsd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x09 1..0=3 +fmadd.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x10 1..0=3 +fmsub.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x11 1..0=3 +fnmsub.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x12 1..0=3 +fnmadd.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x13 1..0=3 +fadd.d rd rs1 rs2 31..27=0x00 rm 26..25=1 6..2=0x14 1..0=3 +fsub.d rd rs1 rs2 31..27=0x01 rm 26..25=1 6..2=0x14 1..0=3 +fmul.d rd rs1 rs2 31..27=0x02 rm 26..25=1 6..2=0x14 1..0=3 +fdiv.d rd rs1 rs2 31..27=0x03 rm 26..25=1 6..2=0x14 1..0=3 +fsqrt.d rd rs1 24..20=0 31..27=0x0B rm 26..25=1 6..2=0x14 1..0=3 +fsgnj.d rd rs1 rs2 31..27=0x04 14..12=0 26..25=1 6..2=0x14 1..0=3 +fsgnjn.d rd rs1 rs2 31..27=0x04 14..12=1 26..25=1 6..2=0x14 1..0=3 +fsgnjx.d rd rs1 rs2 31..27=0x04 14..12=2 26..25=1 6..2=0x14 1..0=3 +fmin.d rd rs1 rs2 31..27=0x05 14..12=0 26..25=1 6..2=0x14 1..0=3 +fmax.d rd rs1 rs2 31..27=0x05 14..12=1 26..25=1 6..2=0x14 1..0=3 +fcvt.s.d rd rs1 24..20=1 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.d.s rd rs1 24..20=0 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 +feq.d rd rs1 rs2 31..27=0x14 14..12=2 26..25=1 6..2=0x14 1..0=3 +flt.d rd rs1 rs2 31..27=0x14 14..12=1 26..25=1 6..2=0x14 1..0=3 +fle.d rd rs1 rs2 31..27=0x14 14..12=0 26..25=1 6..2=0x14 1..0=3 +fclass.d rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=1 6..2=0x14 1..0=3 +fcvt.w.d rd rs1 24..20=0 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.wu.d rd rs1 24..20=1 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.d.w rd rs1 24..20=0 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 +fcvt.d.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_d_zfh b/riscv_isac/plugins/riscv_opcodes/rv_d_zfh new file mode 100644 index 0000000..80d3765 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_d_zfh @@ -0,0 +1,2 @@ +fcvt.d.h rd rs1 24..20=2 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.h.d rd rs1 24..20=1 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_f b/riscv_isac/plugins/riscv_opcodes/rv_f new file mode 100644 index 0000000..c148dd2 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_f @@ -0,0 +1,26 @@ +flw rd rs1 imm12 14..12=2 6..2=0x01 1..0=3 +fsw imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x09 1..0=3 +fmadd.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x10 1..0=3 +fmsub.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x11 1..0=3 +fnmsub.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x12 1..0=3 +fnmadd.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x13 1..0=3 +fadd.s rd rs1 rs2 31..27=0x00 rm 26..25=0 6..2=0x14 1..0=3 +fsub.s rd rs1 rs2 31..27=0x01 rm 26..25=0 6..2=0x14 1..0=3 +fmul.s rd rs1 rs2 31..27=0x02 rm 26..25=0 6..2=0x14 1..0=3 +fdiv.s rd rs1 rs2 31..27=0x03 rm 26..25=0 6..2=0x14 1..0=3 +fsqrt.s rd rs1 24..20=0 31..27=0x0B rm 26..25=0 6..2=0x14 1..0=3 +fsgnj.s rd rs1 rs2 31..27=0x04 14..12=0 26..25=0 6..2=0x14 1..0=3 +fsgnjn.s rd rs1 rs2 31..27=0x04 14..12=1 26..25=0 6..2=0x14 1..0=3 +fsgnjx.s rd rs1 rs2 31..27=0x04 14..12=2 26..25=0 6..2=0x14 1..0=3 +fmin.s rd rs1 rs2 31..27=0x05 14..12=0 26..25=0 6..2=0x14 1..0=3 +fmax.s rd rs1 rs2 31..27=0x05 14..12=1 26..25=0 6..2=0x14 1..0=3 +fcvt.w.s rd rs1 24..20=0 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.wu.s rd rs1 24..20=1 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 +fmv.x.w rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 +feq.s rd rs1 rs2 31..27=0x14 14..12=2 26..25=0 6..2=0x14 1..0=3 +flt.s rd rs1 rs2 31..27=0x14 14..12=1 26..25=0 6..2=0x14 1..0=3 +fle.s rd rs1 rs2 31..27=0x14 14..12=0 26..25=0 6..2=0x14 1..0=3 +fclass.s rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=0 6..2=0x14 1..0=3 +fcvt.s.w rd rs1 24..20=0 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 +fcvt.s.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 +fmv.w.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_h b/riscv_isac/plugins/riscv_opcodes/rv_h new file mode 100644 index 0000000..63b9efc --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_h @@ -0,0 +1,15 @@ +# Hypervisor extension +hfence.vvma 11..7=0 rs1 rs2 31..25=0x11 14..12=0 6..2=0x1C 1..0=3 +hfence.gvma 11..7=0 rs1 rs2 31..25=0x31 14..12=0 6..2=0x1C 1..0=3 + +hlv.b rd rs1 24..20=0x0 31..25=0x30 14..12=4 6..2=0x1C 1..0=3 +hlv.bu rd rs1 24..20=0x1 31..25=0x30 14..12=4 6..2=0x1C 1..0=3 +hlv.h rd rs1 24..20=0x0 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 +hlv.hu rd rs1 24..20=0x1 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 +hlvx.hu rd rs1 24..20=0x3 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 +hlv.w rd rs1 24..20=0x0 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 +hlvx.wu rd rs1 24..20=0x3 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 +hsv.b 11..7=0 rs1 rs2 31..25=0x31 14..12=4 6..2=0x1C 1..0=3 +hsv.h 11..7=0 rs1 rs2 31..25=0x33 14..12=4 6..2=0x1C 1..0=3 +hsv.w 11..7=0 rs1 rs2 31..25=0x35 14..12=4 6..2=0x1C 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_i b/riscv_isac/plugins/riscv_opcodes/rv_i new file mode 100644 index 0000000..4afb288 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_i @@ -0,0 +1,46 @@ +# format of a line in this file: +# +# +# is given by specifying one or more range/value pairs: +# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) +# +# is one of rd, rs1, rs2, rs3, imm20, imm12, imm12lo, imm12hi, +# shamtw, shamt, rm + +lui rd imm20 6..2=0x0D 1..0=3 +auipc rd imm20 6..2=0x05 1..0=3 +jal rd jimm20 6..2=0x1b 1..0=3 +jalr rd rs1 imm12 14..12=0 6..2=0x19 1..0=3 +beq bimm12hi rs1 rs2 bimm12lo 14..12=0 6..2=0x18 1..0=3 +bne bimm12hi rs1 rs2 bimm12lo 14..12=1 6..2=0x18 1..0=3 +blt bimm12hi rs1 rs2 bimm12lo 14..12=4 6..2=0x18 1..0=3 +bge bimm12hi rs1 rs2 bimm12lo 14..12=5 6..2=0x18 1..0=3 +bltu bimm12hi rs1 rs2 bimm12lo 14..12=6 6..2=0x18 1..0=3 +bgeu bimm12hi rs1 rs2 bimm12lo 14..12=7 6..2=0x18 1..0=3 +lb rd rs1 imm12 14..12=0 6..2=0x00 1..0=3 +lh rd rs1 imm12 14..12=1 6..2=0x00 1..0=3 +lw rd rs1 imm12 14..12=2 6..2=0x00 1..0=3 +lbu rd rs1 imm12 14..12=4 6..2=0x00 1..0=3 +lhu rd rs1 imm12 14..12=5 6..2=0x00 1..0=3 +sb imm12hi rs1 rs2 imm12lo 14..12=0 6..2=0x08 1..0=3 +sh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x08 1..0=3 +sw imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x08 1..0=3 +addi rd rs1 imm12 14..12=0 6..2=0x04 1..0=3 +slti rd rs1 imm12 14..12=2 6..2=0x04 1..0=3 +sltiu rd rs1 imm12 14..12=3 6..2=0x04 1..0=3 +xori rd rs1 imm12 14..12=4 6..2=0x04 1..0=3 +ori rd rs1 imm12 14..12=6 6..2=0x04 1..0=3 +andi rd rs1 imm12 14..12=7 6..2=0x04 1..0=3 +add rd rs1 rs2 31..25=0 14..12=0 6..2=0x0C 1..0=3 +sub rd rs1 rs2 31..25=32 14..12=0 6..2=0x0C 1..0=3 +sll rd rs1 rs2 31..25=0 14..12=1 6..2=0x0C 1..0=3 +slt rd rs1 rs2 31..25=0 14..12=2 6..2=0x0C 1..0=3 +sltu rd rs1 rs2 31..25=0 14..12=3 6..2=0x0C 1..0=3 +xor rd rs1 rs2 31..25=0 14..12=4 6..2=0x0C 1..0=3 +srl rd rs1 rs2 31..25=0 14..12=5 6..2=0x0C 1..0=3 +sra rd rs1 rs2 31..25=32 14..12=5 6..2=0x0C 1..0=3 +or rd rs1 rs2 31..25=0 14..12=6 6..2=0x0C 1..0=3 +and rd rs1 rs2 31..25=0 14..12=7 6..2=0x0C 1..0=3 +fence fm pred succ rs1 14..12=0 rd 6..2=0x03 1..0=3 +ecall 31..20=0x000 19..7=0 6..2=0x1C 1..0=3 +ebreak 31..20=0x001 19..7=0 6..2=0x1C 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_m b/riscv_isac/plugins/riscv_opcodes/rv_m new file mode 100644 index 0000000..51e6786 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_m @@ -0,0 +1,8 @@ +mul rd rs1 rs2 31..25=1 14..12=0 6..2=0x0C 1..0=3 +mulh rd rs1 rs2 31..25=1 14..12=1 6..2=0x0C 1..0=3 +mulhsu rd rs1 rs2 31..25=1 14..12=2 6..2=0x0C 1..0=3 +mulhu rd rs1 rs2 31..25=1 14..12=3 6..2=0x0C 1..0=3 +div rd rs1 rs2 31..25=1 14..12=4 6..2=0x0C 1..0=3 +divu rd rs1 rs2 31..25=1 14..12=5 6..2=0x0C 1..0=3 +rem rd rs1 rs2 31..25=1 14..12=6 6..2=0x0C 1..0=3 +remu rd rs1 rs2 31..25=1 14..12=7 6..2=0x0C 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_p b/riscv_isac/plugins/riscv_opcodes/rv_p new file mode 100644 index 0000000..c239c10 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_p @@ -0,0 +1,245 @@ +add8 31..25=0b0100100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +add16 31..25=0b0100000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ave 31..25=0b1110000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +bitrev 31..25=0b1110011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +bitrevi 31..26=0b111010 imm6 rs1 14..12=0b000 rd 6..0=0b1110111 +bpick rs3 26..25=0b00 rs2 rs1 14..12=0b011 rd 6..0=0b1110111 +clrs8 31..25=0b1010111 24..20=0b00000 rs1 14..12=0b000 rd 6..0=0b1110111 +clrs16 31..25=0b1010111 24..20=0b01000 rs1 14..12=0b000 rd 6..0=0b1110111 +clrs32 31..25=0b1010111 24..20=0b11000 rs1 14..12=0b000 rd 6..0=0b1110111 +clo8 31..25=0b1010111 24..20=0b00011 rs1 14..12=0b000 rd 6..0=0b1110111 +clo16 31..25=0b1010111 24..20=0b01011 rs1 14..12=0b000 rd 6..0=0b1110111 +clo32 31..25=0b1010111 24..20=0b11011 rs1 14..12=0b000 rd 6..0=0b1110111 +clz8 31..25=0b1010111 24..20=0b00001 rs1 14..12=0b000 rd 6..0=0b1110111 +clz16 31..25=0b1010111 24..20=0b01001 rs1 14..12=0b000 rd 6..0=0b1110111 +clz32 31..25=0b1010111 24..20=0b11001 rs1 14..12=0b000 rd 6..0=0b1110111 +cmpeq8 31..25=0b0100111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +cmpeq16 31..25=0b0100110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +cras16 31..25=0b0100010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +crsa16 31..25=0b0100011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +insb 31..25=0b1010110 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +kabs8 31..25=0b1010110 24..20=0b10000 rs1 14..12=0b000 rd 6..0=0b1110111 +kabs16 31..25=0b1010110 24..20=0b10001 rs1 14..12=0b000 rd 6..0=0b1110111 +kabsw 31..25=0b1010110 24..20=0b10100 rs1 14..12=0b000 rd 6..0=0b1110111 +kadd8 31..25=0b0001100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kadd16 31..25=0b0001000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kadd64 31..25=0b1001000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kaddh 31..25=0b0000010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kaddw 31..25=0b0000000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kcras16 31..25=0b0001010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kcrsa16 31..25=0b0001011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kdmbb 31..25=0b0000101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmbt 31..25=0b0001101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmtt 31..25=0b0010101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmabb 31..25=0b1101001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmabt 31..25=0b1110001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kdmatt 31..25=0b1111001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +khm8 31..25=0b1000111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +khmx8 31..25=0b1001111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +khm16 31..25=0b1000011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +khmx16 31..25=0b1001011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +khmbb 31..25=0b0000110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +khmbt 31..25=0b0001110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +khmtt 31..25=0b0010110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmabb 31..25=0b0101101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmabt 31..25=0b0110101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmatt 31..25=0b0111101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmada 31..25=0b0100100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmaxda 31..25=0b0100101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmads 31..25=0b0101110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmadrs 31..25=0b0110110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmaxds 31..25=0b0111110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmar64 31..25=0b1001010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmda 31..25=0b0011100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmxda 31..25=0b0011101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmac 31..25=0b0110000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmac.u 31..25=0b0111000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawb 31..25=0b0100011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawb.u 31..25=0b0101011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawb2 31..25=0b1100111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawb2.u 31..25=0b1101111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawt 31..25=0b0110011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawt.u 31..25=0b0111011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawt2 31..25=0b1110111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmawt2.u 31..25=0b1111111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmsb 31..25=0b0100001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmsb.u 31..25=0b0101001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmwb2 31..25=0b1000111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmwb2.u 31..25=0b1001111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmwt2 31..25=0b1010111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmmwt2.u 31..25=0b1011111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmsda 31..25=0b0100110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmsxda 31..25=0b0100111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kmsr64 31..25=0b1001011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ksllw 31..25=0b0010011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kslliw 31..25=0b0011011 imm5 rs1 14..12=0b001 rd 6..0=0b1110111 +ksll8 31..25=0b0110110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kslli8 31..25=0b0111110 24..23=0b01 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +ksll16 31..25=0b0110010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kslli16 31..25=0b0111010 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +kslra8 31..25=0b0101111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kslra8.u 31..25=0b0110111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kslra16 31..25=0b0101011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kslra16.u 31..25=0b0110011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +kslraw 31..25=0b0110111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kslraw.u 31..25=0b0111111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kstas16 31..25=0b1100010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +kstsa16 31..25=0b1100011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ksub8 31..25=0b0001101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ksub16 31..25=0b0001001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ksub64 31..25=0b1001001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ksubh 31..25=0b0000011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ksubw 31..25=0b0000001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kwmmul 31..25=0b0110001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +kwmmul.u 31..25=0b0111001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +maddr32 31..25=0b1100010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +maxw 31..25=0b1111001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +minw 31..25=0b1111000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +msubr32 31..25=0b1100011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +mulr64 31..25=0b1111000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +mulsr64 31..25=0b1110000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +pbsad 31..25=0b1111110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +pbsada 31..25=0b1111111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +pkbb16 31..25=0b0000111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +pkbt16 31..25=0b0001111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +pktt16 31..25=0b0010111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +pktb16 31..25=0b0011111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +radd8 31..25=0b0000100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +radd16 31..25=0b0000000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +radd64 31..25=0b1000000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +raddw 31..25=0b0010000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +rcras16 31..25=0b0000010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +rcrsa16 31..25=0b0000011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +rstas16 31..25=0b1011010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +rstsa16 31..25=0b1011011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +rsub8 31..25=0b0000101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +rsub16 31..25=0b0000001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +rsub64 31..25=0b1000001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +rsubw 31..25=0b0010001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +sclip8 31..25=0b1000110 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +sclip16 31..25=0b1000010 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +sclip32 31..25=0b1110010 imm5 rs1 14..12=0b000 rd 6..0=0b1110111 +scmple8 31..25=0b0001111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +scmple16 31..25=0b0001110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +scmplt8 31..25=0b0000111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +scmplt16 31..25=0b0000110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +sll8 31..25=0b0101110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +slli8 31..25=0b0111110 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +sll16 31..25=0b0101010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +slli16 31..25=0b0111010 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +smal 31..25=0b0101111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smalbb 31..25=0b1000100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smalbt 31..25=0b1001100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smaltt 31..25=0b1010100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smalda 31..25=0b1000110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smalxda 31..25=0b1001110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smalds 31..25=0b1000101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smaldrs 31..25=0b1001101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smalxds 31..25=0b1010101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smar64 31..25=0b1000010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smaqa 31..25=0b1100100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smaqa.su 31..25=0b1100101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smax8 31..25=0b1000101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smax16 31..25=0b1000001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smbb16 31..25=0b0000100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smbt16 31..25=0b0001100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smtt16 31..25=0b0010100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smds 31..25=0b0101100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smdrs 31..25=0b0110100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smxds 31..25=0b0111100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smin8 31..25=0b1000100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smin16 31..25=0b1000000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smmul 31..25=0b0100000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smmul.u 31..25=0b0101000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smmwb 31..25=0b0100010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smmwb.u 31..25=0b0101010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smmwt 31..25=0b0110010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smmwt.u 31..25=0b0111010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smslda 31..25=0b1010110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smslxda 31..25=0b1011110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smsr64 31..25=0b1000011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +smul8 31..25=0b1010100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smulx8 31..25=0b1010101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smul16 31..25=0b1010000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +smulx16 31..25=0b1010001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +sra.u 31..25=0b0010010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +srai.u 31..26=0b110101 imm6 rs1 14..12=0b001 rd 6..0=0b1110111 +sra8 31..25=0b0101100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +sra8.u 31..25=0b0110100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +srai8 31..25=0b0111100 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +srai8.u 31..25=0b0111100 24..23=0b01 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +sra16 31..25=0b0101000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +sra16.u 31..25=0b0110000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +srai16 31..25=0b0111000 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +srai16.u 31..25=0b0111000 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +srl8 31..25=0b0101101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +srl8.u 31..25=0b0110101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +srli8 31..25=0b0111101 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +srli8.u 31..25=0b0111101 24..23=0b01 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +srl16 31..25=0b0101001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +srl16.u 31..25=0b0110001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +srli16 31..25=0b0111001 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +srli16.u 31..25=0b0111001 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +stas16 31..25=0b1111010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +stsa16 31..25=0b1111011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +sub8 31..25=0b0100101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +sub16 31..25=0b0100001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +sunpkd810 31..25=0b1010110 24..20=0b01000 rs1 14..12=0b000 rd 6..0=0b1110111 +sunpkd820 31..25=0b1010110 24..20=0b01001 rs1 14..12=0b000 rd 6..0=0b1110111 +sunpkd830 31..25=0b1010110 24..20=0b01010 rs1 14..12=0b000 rd 6..0=0b1110111 +sunpkd831 31..25=0b1010110 24..20=0b01011 rs1 14..12=0b000 rd 6..0=0b1110111 +sunpkd832 31..25=0b1010110 24..20=0b10011 rs1 14..12=0b000 rd 6..0=0b1110111 +swap8 31..25=0b1010110 24..20=0b11000 rs1 14..12=0b000 rd 6..0=0b1110111 +uclip8 31..25=0b1000110 24..23=0b10 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 +uclip16 31..25=0b1000010 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 +uclip32 31..25=0b1111010 imm5 rs1 14..12=0b000 rd 6..0=0b1110111 +ucmple8 31..25=0b0011111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ucmple16 31..25=0b0011110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ucmplt8 31..25=0b0010111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ucmplt16 31..25=0b0010110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ukadd8 31..25=0b0011100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ukadd16 31..25=0b0011000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ukadd64 31..25=0b1011000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ukaddh 31..25=0b0001010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ukaddw 31..25=0b0001000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ukcras16 31..25=0b0011010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ukcrsa16 31..25=0b0011011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ukmar64 31..25=0b1011010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ukmsr64 31..25=0b1011011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ukstas16 31..25=0b1110010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ukstsa16 31..25=0b1110011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +uksub8 31..25=0b0011101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +uksub16 31..25=0b0011001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +uksub64 31..25=0b1011001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +uksubh 31..25=0b0001011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +uksubw 31..25=0b0001001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +umar64 31..25=0b1010010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +umaqa 31..25=0b1100110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umax8 31..25=0b1001101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umax16 31..25=0b1001001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umin8 31..25=0b1001100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umin16 31..25=0b1001000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umsr64 31..25=0b1010011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +umul8 31..25=0b1011100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umulx8 31..25=0b1011101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umul16 31..25=0b1011000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +umulx16 31..25=0b1011001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +uradd8 31..25=0b0010100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +uradd16 31..25=0b0010000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +uradd64 31..25=0b1010000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +uraddw 31..25=0b0011000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +urcras16 31..25=0b0010010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +urcrsa16 31..25=0b0010011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +urstas16 31..25=0b1101010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +urstsa16 31..25=0b1101011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +ursub8 31..25=0b0010101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ursub16 31..25=0b0010001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +ursub64 31..25=0b1010001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +ursubw 31..25=0b0011001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 +wexti 31..25=0b1101111 imm5 rs1 14..12=0b000 rd 6..0=0b1110111 +wext 31..25=0b1100111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 +zunpkd810 31..25=0b1010110 24..20=0b01100 rs1 14..12=0b000 rd 6..0=0b1110111 +zunpkd820 31..25=0b1010110 24..20=0b01101 rs1 14..12=0b000 rd 6..0=0b1110111 +zunpkd830 31..25=0b1010110 24..20=0b01110 rs1 14..12=0b000 rd 6..0=0b1110111 +zunpkd831 31..25=0b1010110 24..20=0b01111 rs1 14..12=0b000 rd 6..0=0b1110111 +zunpkd832 31..25=0b1010110 24..20=0b10111 rs1 14..12=0b000 rd 6..0=0b1110111 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_pseudo b/riscv_isac/plugins/riscv_opcodes/rv_pseudo new file mode 100644 index 0000000..c186ca5 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_pseudo @@ -0,0 +1,26 @@ +$pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrwi fsflagsi rd zimm 31..20=0x001 14..12=5 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs frrm rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrwi fsrmi rd zimm 31..20=0x002 14..12=5 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fscsr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs frcsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs rdcycle rd 19..15=0 31..20=0xC00 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs rdtime rd 19..15=0 31..20=0xC01 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs rdinstret rd 19..15=0 31..20=0xC02 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs rdcycleh rd 19..15=0 31..20=0xC80 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs rdtimeh rd 19..15=0 31..20=0xC81 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs rdinstreth rd 19..15=0 31..20=0xC82 14..12=2 6..2=0x1C 1..0=3 + +#Old names for ecall/ebreak +$pseudo_op rv_i::ecall scall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 +$pseudo_op rv_i::ebreak sbreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 + +#Old names for fmv.x.w/fmv.w.x +$pseudo_op rv_f::fmv.x.w fmv.x.s rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 +$pseudo_op rv_f::fmv.w.x fmv.s.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 + +#specialized fences +$pseudo_op rv_i::fence fence.tso 31..28=8 27..24=3 23..20=3 19..15=ignore 14..12=0 11..7=ignore 6..2=0x03 1..0=3 +$pseudo_op rv_i::fence pause 31..28=0 27..24=1 23..20=0 19..15=0 14..12=0 11..7=0 6..2=0x03 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_q b/riscv_isac/plugins/riscv_opcodes/rv_q new file mode 100644 index 0000000..298ae87 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_q @@ -0,0 +1,28 @@ +flq rd rs1 imm12 14..12=4 6..2=0x01 1..0=3 +fsq imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x09 1..0=3 +fmadd.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x10 1..0=3 +fmsub.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x11 1..0=3 +fnmsub.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x12 1..0=3 +fnmadd.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x13 1..0=3 +fadd.q rd rs1 rs2 31..27=0x00 rm 26..25=3 6..2=0x14 1..0=3 +fsub.q rd rs1 rs2 31..27=0x01 rm 26..25=3 6..2=0x14 1..0=3 +fmul.q rd rs1 rs2 31..27=0x02 rm 26..25=3 6..2=0x14 1..0=3 +fdiv.q rd rs1 rs2 31..27=0x03 rm 26..25=3 6..2=0x14 1..0=3 +fsqrt.q rd rs1 24..20=0 31..27=0x0B rm 26..25=3 6..2=0x14 1..0=3 +fsgnj.q rd rs1 rs2 31..27=0x04 14..12=0 26..25=3 6..2=0x14 1..0=3 +fsgnjn.q rd rs1 rs2 31..27=0x04 14..12=1 26..25=3 6..2=0x14 1..0=3 +fsgnjx.q rd rs1 rs2 31..27=0x04 14..12=2 26..25=3 6..2=0x14 1..0=3 +fmin.q rd rs1 rs2 31..27=0x05 14..12=0 26..25=3 6..2=0x14 1..0=3 +fmax.q rd rs1 rs2 31..27=0x05 14..12=1 26..25=3 6..2=0x14 1..0=3 +fcvt.s.q rd rs1 24..20=3 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.q.s rd rs1 24..20=0 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 +fcvt.d.q rd rs1 24..20=3 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.q.d rd rs1 24..20=1 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 +feq.q rd rs1 rs2 31..27=0x14 14..12=2 26..25=3 6..2=0x14 1..0=3 +flt.q rd rs1 rs2 31..27=0x14 14..12=1 26..25=3 6..2=0x14 1..0=3 +fle.q rd rs1 rs2 31..27=0x14 14..12=0 26..25=3 6..2=0x14 1..0=3 +fclass.q rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=3 6..2=0x14 1..0=3 +fcvt.w.q rd rs1 24..20=0 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 +fcvt.wu.q rd rs1 24..20=1 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 +fcvt.q.w rd rs1 24..20=0 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 +fcvt.q.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_q_zfh b/riscv_isac/plugins/riscv_opcodes/rv_q_zfh new file mode 100644 index 0000000..24548d5 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_q_zfh @@ -0,0 +1,2 @@ +fcvt.q.h rd rs1 24..20=2 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 +fcvt.h.q rd rs1 24..20=3 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_s b/riscv_isac/plugins/riscv_opcodes/rv_s new file mode 100644 index 0000000..25f3532 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_s @@ -0,0 +1,3 @@ +sfence.vma 11..7=0 rs1 rs2 31..25=0x09 14..12=0 6..2=0x1C 1..0=3 +sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_svinval b/riscv_isac/plugins/riscv_opcodes/rv_svinval new file mode 100644 index 0000000..b35ae7c --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_svinval @@ -0,0 +1,7 @@ +# Svinval +sinval.vma 11..7=0 rs1 rs2 31..25=0x0b 14..12=0 6..2=0x1C 1..0=3 +sfence.w.inval 11..7=0 19..15=0x0 24..20=0x0 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 +sfence.inval.ir 11..7=0 19..15=0x0 24..20=0x1 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 +hinval.vvma 11..7=0 rs1 rs2 31..25=0x13 14..12=0 6..2=0x1C 1..0=3 +hinval.gvma 11..7=0 rs1 rs2 31..25=0x33 14..12=0 6..2=0x1C 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_system b/riscv_isac/plugins/riscv_opcodes/rv_system new file mode 100644 index 0000000..f94c4cf --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_system @@ -0,0 +1,5 @@ +# SYSTEM +mret 11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3 +dret 11..7=0 19..15=0 31..20=0x7b2 14..12=0 6..2=0x1C 1..0=3 +wfi 11..7=0 19..15=0 31..20=0x105 14..12=0 6..2=0x1C 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_v b/riscv_isac/plugins/riscv_opcodes/rv_v new file mode 100644 index 0000000..29a0ff8 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_v @@ -0,0 +1,528 @@ +# format of a line in this file: +# +# +# is given by specifying one or more range/value pairs: +# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) +# +# is one of vd, vs3, vs1, vs2, vm, nf, wd, simm5, zimm10, zimm11 + +# configuration setting +# https://github.com/riscv/riscv-v-spec/blob/master/vcfg-format.adoc +vsetivli 31=1 30=1 zimm10 zimm 14..12=0x7 rd 6..0=0x57 +vsetvli 31=0 zimm11 rs1 14..12=0x7 rd 6..0=0x57 +vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57 + +# +# Vector Loads and Store +# https://github.com/riscv/riscv-v-spec/blob/master/vmem-format.adoc +# +# Vector Unit-Stride Instructions (including segment part) +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#74-vector-unit-stride-instructions +vlm.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 +vsm.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 +vle8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 +vle16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 +vle32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 +vle64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07 +vle128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 +vle256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 +vle512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 +vle1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07 +vse8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27 +vse16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27 +vse32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27 +vse64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27 +vse128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27 +vse256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27 +vse512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27 +vse1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27 + +# Vector Indexed-Unordered Instructions (including segment part) +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions +vluxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 +vluxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 +vluxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 +vluxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 +vluxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 +vluxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 +vluxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 +vluxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 +vsuxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 +vsuxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 +vsuxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 +vsuxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 +vsuxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 +vsuxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 +vsuxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 +vsuxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 + +# Vector Strided Instructions (including segment part) +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#75-vector-strided-instructions +vlse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07 +vlse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07 +vlse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07 +vlse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07 +vlse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07 +vlse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07 +vlse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07 +vlse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07 +vsse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27 +vsse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27 +vsse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27 +vsse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27 +vsse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27 +vsse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27 +vsse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27 +vsse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27 + +# Vector Indexed-Ordered Instructions (including segment part) +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions +vloxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 +vloxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 +vloxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 +vloxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 +vloxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 +vloxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 +vloxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 +vloxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 +vsoxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 +vsoxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 +vsoxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 +vsoxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 +vsoxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 +vsoxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 +vsoxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 +vsoxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 + +# Unit-stride F31..29=0ault-Only-First Loads +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#77-unit-stride-fault-only-first-loads +vle8ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 +vle16ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 +vle32ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 +vle64ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 +vle128ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 +vle256ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 +vle512ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 +vle1024ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 + +# Vector Load/Store Whole Registers +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#79-vector-loadstore-whole-register-instructions +vl1re8.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl1re16.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl1re32.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl1re64.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vl2re8.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl2re16.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl2re32.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl2re64.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vl4re8.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl4re16.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl4re32.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl4re64.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vl8re8.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl8re16.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl8re32.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl8re64.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vs1r.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +vs2r.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +vs4r.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +vs8r.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 + +# Vector Floating-Point Instructions +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#14-vector-floating-point-instructions +# OPFVF +vfadd.vf 31..26=0x00 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfsub.vf 31..26=0x02 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmin.vf 31..26=0x04 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmax.vf 31..26=0x06 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfsgnj.vf 31..26=0x08 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfsgnjn.vf 31..26=0x09 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfsgnjx.vf 31..26=0x0a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfslide1up.vf 31..26=0x0e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfslide1down.vf 31..26=0x0f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmv.s.f 31..26=0x10 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 + +vfmerge.vfm 31..26=0x17 25=0 vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmv.v.f 31..26=0x17 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 +vmfeq.vf 31..26=0x18 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vmfle.vf 31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vmflt.vf 31..26=0x1b vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vmfne.vf 31..26=0x1c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vmfgt.vf 31..26=0x1d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vmfge.vf 31..26=0x1f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 + +vfdiv.vf 31..26=0x20 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfrdiv.vf 31..26=0x21 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmul.vf 31..26=0x24 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfrsub.vf 31..26=0x27 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmadd.vf 31..26=0x28 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfnmadd.vf 31..26=0x29 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmsub.vf 31..26=0x2a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfnmsub.vf 31..26=0x2b vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmacc.vf 31..26=0x2c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfnmacc.vf 31..26=0x2d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmsac.vf 31..26=0x2e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfnmsac.vf 31..26=0x2f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 + +vfwadd.vf 31..26=0x30 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwsub.vf 31..26=0x32 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwadd.wf 31..26=0x34 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwsub.wf 31..26=0x36 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwmul.vf 31..26=0x38 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwmacc.vf 31..26=0x3c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwnmacc.vf 31..26=0x3d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwmsac.vf 31..26=0x3e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwnmsac.vf 31..26=0x3f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 + +# OPFVV +vfadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfredusum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfredosum.vs 31..26=0x03 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmin.vv 31..26=0x04 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmax.vv 31..26=0x06 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfsgnj.vv 31..26=0x08 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfsgnjn.vv 31..26=0x09 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfsgnjx.vv 31..26=0x0a vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmv.f.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x1 rd 6..0=0x57 + +vmfeq.vv 31..26=0x18 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vmfle.vv 31..26=0x19 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vmflt.vv 31..26=0x1b vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vmfne.vv 31..26=0x1c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 + +vfdiv.vv 31..26=0x20 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmul.vv 31..26=0x24 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmadd.vv 31..26=0x28 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfnmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmsub.vv 31..26=0x2a vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmacc.vv 31..26=0x2c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfnmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmsac.vv 31..26=0x2e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 + +vfcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 +vfcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x01 14..12=0x1 vd 6..0=0x57 +vfcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x02 14..12=0x1 vd 6..0=0x57 +vfcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x03 14..12=0x1 vd 6..0=0x57 +vfcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x06 14..12=0x1 vd 6..0=0x57 +vfcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x07 14..12=0x1 vd 6..0=0x57 + +vfwcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x08 14..12=0x1 vd 6..0=0x57 +vfwcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x09 14..12=0x1 vd 6..0=0x57 +vfwcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x0A 14..12=0x1 vd 6..0=0x57 +vfwcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x0B 14..12=0x1 vd 6..0=0x57 +vfwcvt.f.f.v 31..26=0x12 vm vs2 19..15=0x0C 14..12=0x1 vd 6..0=0x57 +vfwcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x0E 14..12=0x1 vd 6..0=0x57 +vfwcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x0F 14..12=0x1 vd 6..0=0x57 + +vfncvt.xu.f.w 31..26=0x12 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 +vfncvt.x.f.w 31..26=0x12 vm vs2 19..15=0x11 14..12=0x1 vd 6..0=0x57 +vfncvt.f.xu.w 31..26=0x12 vm vs2 19..15=0x12 14..12=0x1 vd 6..0=0x57 +vfncvt.f.x.w 31..26=0x12 vm vs2 19..15=0x13 14..12=0x1 vd 6..0=0x57 +vfncvt.f.f.w 31..26=0x12 vm vs2 19..15=0x14 14..12=0x1 vd 6..0=0x57 +vfncvt.rod.f.f.w 31..26=0x12 vm vs2 19..15=0x15 14..12=0x1 vd 6..0=0x57 +vfncvt.rtz.xu.f.w 31..26=0x12 vm vs2 19..15=0x16 14..12=0x1 vd 6..0=0x57 +vfncvt.rtz.x.f.w 31..26=0x12 vm vs2 19..15=0x17 14..12=0x1 vd 6..0=0x57 + +vfsqrt.v 31..26=0x13 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 +vfrsqrt7.v 31..26=0x13 vm vs2 19..15=0x04 14..12=0x1 vd 6..0=0x57 +vfrec7.v 31..26=0x13 vm vs2 19..15=0x05 14..12=0x1 vd 6..0=0x57 +vfclass.v 31..26=0x13 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 + +vfwadd.vv 31..26=0x30 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwredusum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwsub.vv 31..26=0x32 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwredosum.vs 31..26=0x33 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwadd.wv 31..26=0x34 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwsub.wv 31..26=0x36 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwmul.vv 31..26=0x38 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwmacc.vv 31..26=0x3c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwnmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwmsac.vv 31..26=0x3e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwnmsac.vv 31..26=0x3f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 + +# OPIVX +vadd.vx 31..26=0x00 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsub.vx 31..26=0x02 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vrsub.vx 31..26=0x03 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vminu.vx 31..26=0x04 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmin.vx 31..26=0x05 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmaxu.vx 31..26=0x06 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmax.vx 31..26=0x07 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vand.vx 31..26=0x09 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vor.vx 31..26=0x0a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vxor.vx 31..26=0x0b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vrgather.vx 31..26=0x0c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vslideup.vx 31..26=0x0e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vslidedown.vx 31..26=0x0f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 + +vadc.vxm 31..26=0x10 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmadc.vxm 31..26=0x11 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmadc.vx 31..26=0x11 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsbc.vxm 31..26=0x12 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsbc.vxm 31..26=0x13 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsbc.vx 31..26=0x13 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmerge.vxm 31..26=0x17 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmv.v.x 31..26=0x17 25=1 24..20=0 rs1 14..12=0x4 vd 6..0=0x57 +vmseq.vx 31..26=0x18 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsne.vx 31..26=0x19 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsltu.vx 31..26=0x1a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmslt.vx 31..26=0x1b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsleu.vx 31..26=0x1c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsle.vx 31..26=0x1d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsgtu.vx 31..26=0x1e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsgt.vx 31..26=0x1f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 + +vsaddu.vx 31..26=0x20 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsadd.vx 31..26=0x21 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vssubu.vx 31..26=0x22 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vssub.vx 31..26=0x23 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsll.vx 31..26=0x25 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsmul.vx 31..26=0x27 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsrl.vx 31..26=0x28 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsra.vx 31..26=0x29 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vssrl.vx 31..26=0x2a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vssra.vx 31..26=0x2b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vnsrl.wx 31..26=0x2c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vnsra.wx 31..26=0x2d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vnclipu.wx 31..26=0x2e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vnclip.wx 31..26=0x2f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 + +# OPIVV +vadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vminu.vv 31..26=0x04 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmin.vv 31..26=0x05 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmaxu.vv 31..26=0x06 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmax.vv 31..26=0x07 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vand.vv 31..26=0x09 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vor.vv 31..26=0x0a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vxor.vv 31..26=0x0b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vrgather.vv 31..26=0x0c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vrgatherei16.vv 31..26=0x0e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +vadc.vvm 31..26=0x10 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmadc.vvm 31..26=0x11 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmadc.vv 31..26=0x11 25=1 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsbc.vvm 31..26=0x12 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsbc.vvm 31..26=0x13 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsbc.vv 31..26=0x13 25=1 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmerge.vvm 31..26=0x17 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmv.v.v 31..26=0x17 25=1 24..20=0 vs1 14..12=0x0 vd 6..0=0x57 +vmseq.vv 31..26=0x18 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsne.vv 31..26=0x19 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsltu.vv 31..26=0x1a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmslt.vv 31..26=0x1b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsleu.vv 31..26=0x1c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsle.vv 31..26=0x1d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +vsaddu.vv 31..26=0x20 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsadd.vv 31..26=0x21 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssubu.vv 31..26=0x22 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssub.vv 31..26=0x23 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsll.vv 31..26=0x25 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsmul.vv 31..26=0x27 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsrl.vv 31..26=0x28 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsra.vv 31..26=0x29 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssrl.vv 31..26=0x2a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssra.vv 31..26=0x2b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnsrl.wv 31..26=0x2c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnsra.wv 31..26=0x2d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnclipu.wv 31..26=0x2e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnclip.wv 31..26=0x2f vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +vwredsumu.vs 31..26=0x30 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +# OPIVI +vadd.vi 31..26=0x00 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vrsub.vi 31..26=0x03 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vand.vi 31..26=0x09 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vor.vi 31..26=0x0a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vxor.vi 31..26=0x0b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vrgather.vi 31..26=0x0c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vslideup.vi 31..26=0x0e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vslidedown.vi 31..26=0x0f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 + +vadc.vim 31..26=0x10 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmadc.vim 31..26=0x11 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmadc.vi 31..26=0x11 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmerge.vim 31..26=0x17 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmv.v.i 31..26=0x17 25=1 24..20=0 simm5 14..12=0x3 vd 6..0=0x57 +vmseq.vi 31..26=0x18 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmsne.vi 31..26=0x19 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmsleu.vi 31..26=0x1c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmsle.vi 31..26=0x1d vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmsgtu.vi 31..26=0x1e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmsgt.vi 31..26=0x1f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 + +vsaddu.vi 31..26=0x20 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vsadd.vi 31..26=0x21 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vsll.vi 31..26=0x25 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmv1r.v 31..26=0x27 25=1 vs2 19..15=0 14..12=0x3 vd 6..0=0x57 +vmv2r.v 31..26=0x27 25=1 vs2 19..15=1 14..12=0x3 vd 6..0=0x57 +vmv4r.v 31..26=0x27 25=1 vs2 19..15=3 14..12=0x3 vd 6..0=0x57 +vmv8r.v 31..26=0x27 25=1 vs2 19..15=7 14..12=0x3 vd 6..0=0x57 +vsrl.vi 31..26=0x28 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vsra.vi 31..26=0x29 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vssrl.vi 31..26=0x2a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vssra.vi 31..26=0x2b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vnsrl.wi 31..26=0x2c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vnsra.wi 31..26=0x2d vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vnclipu.wi 31..26=0x2e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vnclip.wi 31..26=0x2f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 + +# OPMVV +vredsum.vs 31..26=0x00 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredand.vs 31..26=0x01 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredor.vs 31..26=0x02 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredxor.vs 31..26=0x03 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredminu.vs 31..26=0x04 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredmaxu.vs 31..26=0x06 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vaaddu.vv 31..26=0x08 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vaadd.vv 31..26=0x09 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vasubu.vv 31..26=0x0a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vasub.vv 31..26=0x0b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 + +vmv.x.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x2 rd 6..0=0x57 + +# Vector Integer Extension Instructions +# https://github.com/riscv/riscv-v-spec/blob/e49574c92b072fd4d71e6cb20f7e8154de5b83fe/v-spec.adoc#123-vector-integer-extension +vzext.vf8 31..26=0x12 vm vs2 19..15=2 14..12=0x2 vd 6..0=0x57 +vsext.vf8 31..26=0x12 vm vs2 19..15=3 14..12=0x2 vd 6..0=0x57 +vzext.vf4 31..26=0x12 vm vs2 19..15=4 14..12=0x2 vd 6..0=0x57 +vsext.vf4 31..26=0x12 vm vs2 19..15=5 14..12=0x2 vd 6..0=0x57 +vzext.vf2 31..26=0x12 vm vs2 19..15=6 14..12=0x2 vd 6..0=0x57 +vsext.vf2 31..26=0x12 vm vs2 19..15=7 14..12=0x2 vd 6..0=0x57 + +vcompress.vm 31..26=0x17 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmandn.mm 31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmand.mm 31..26=0x19 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmor.mm 31..26=0x1a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmxor.mm 31..26=0x1b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmorn.mm 31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmnand.mm 31..26=0x1d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmnor.mm 31..26=0x1e vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmxnor.mm 31..26=0x1f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 + +vmsbf.m 31..26=0x14 vm vs2 19..15=0x01 14..12=0x2 vd 6..0=0x57 +vmsof.m 31..26=0x14 vm vs2 19..15=0x02 14..12=0x2 vd 6..0=0x57 +vmsif.m 31..26=0x14 vm vs2 19..15=0x03 14..12=0x2 vd 6..0=0x57 +viota.m 31..26=0x14 vm vs2 19..15=0x10 14..12=0x2 vd 6..0=0x57 +vid.v 31..26=0x14 vm 24..20=0 19..15=0x11 14..12=0x2 vd 6..0=0x57 +vcpop.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 +vfirst.m 31..26=0x10 vm vs2 19..15=0x11 14..12=0x2 rd 6..0=0x57 + +vdivu.vv 31..26=0x20 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vdiv.vv 31..26=0x21 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vremu.vv 31..26=0x22 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vrem.vv 31..26=0x23 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmulhu.vv 31..26=0x24 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmul.vv 31..26=0x25 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmulhsu.vv 31..26=0x26 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmulh.vv 31..26=0x27 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 + +vwaddu.vv 31..26=0x30 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwadd.vv 31..26=0x31 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwsubu.vv 31..26=0x32 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwsub.vv 31..26=0x33 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwaddu.wv 31..26=0x34 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwadd.wv 31..26=0x35 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwsubu.wv 31..26=0x36 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwsub.wv 31..26=0x37 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmulu.vv 31..26=0x38 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmulsu.vv 31..26=0x3a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmul.vv 31..26=0x3b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 + +# OPMVX +vaaddu.vx 31..26=0x08 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vaadd.vx 31..26=0x09 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vasubu.vx 31..26=0x0a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vasub.vx 31..26=0x0b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 + +vmv.s.x 31..26=0x10 25=1 24..20=0 rs1 14..12=0x6 vd 6..0=0x57 +vslide1up.vx 31..26=0x0e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vslide1down.vx 31..26=0x0f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 + +vdivu.vx 31..26=0x20 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vdiv.vx 31..26=0x21 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vremu.vx 31..26=0x22 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vrem.vx 31..26=0x23 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmulhu.vx 31..26=0x24 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmul.vx 31..26=0x25 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmulhsu.vx 31..26=0x26 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmulh.vx 31..26=0x27 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmadd.vx 31..26=0x29 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vnmsub.vx 31..26=0x2b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmacc.vx 31..26=0x2d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vnmsac.vx 31..26=0x2f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 + +vwaddu.vx 31..26=0x30 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwadd.vx 31..26=0x31 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwsubu.vx 31..26=0x32 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwsub.vx 31..26=0x33 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwaddu.wx 31..26=0x34 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwadd.wx 31..26=0x35 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwsubu.wx 31..26=0x36 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwsub.wx 31..26=0x37 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmulu.vx 31..26=0x38 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmulsu.vx 31..26=0x3a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmul.vx 31..26=0x3b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmaccu.vx 31..26=0x3c vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmacc.vx 31..26=0x3d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 + +# Zvamo +vamoswapei8.v 31..27=0x01 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamoaddei8.v 31..27=0x00 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamoxorei8.v 31..27=0x04 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamoandei8.v 31..27=0x0c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamoorei8.v 31..27=0x08 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamominei8.v 31..27=0x10 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamomaxei8.v 31..27=0x14 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamominuei8.v 31..27=0x18 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f +vamomaxuei8.v 31..27=0x1c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f + +vamoswapei16.v 31..27=0x01 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamoaddei16.v 31..27=0x00 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamoxorei16.v 31..27=0x04 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamoandei16.v 31..27=0x0c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamoorei16.v 31..27=0x08 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamominei16.v 31..27=0x10 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamomaxei16.v 31..27=0x14 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamominuei16.v 31..27=0x18 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f +vamomaxuei16.v 31..27=0x1c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f + +vamoswapei32.v 31..27=0x01 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamoaddei32.v 31..27=0x00 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamoxorei32.v 31..27=0x04 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamoandei32.v 31..27=0x0c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamoorei32.v 31..27=0x08 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamominei32.v 31..27=0x10 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamomaxei32.v 31..27=0x14 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamominuei32.v 31..27=0x18 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f +vamomaxuei32.v 31..27=0x1c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f + +vamoswapei64.v 31..27=0x01 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamoaddei64.v 31..27=0x00 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamoxorei64.v 31..27=0x04 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamoandei64.v 31..27=0x0c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamoorei64.v 31..27=0x08 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamominei64.v 31..27=0x10 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamomaxei64.v 31..27=0x14 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamominuei64.v 31..27=0x18 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f +vamomaxuei64.v 31..27=0x1c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zba b/riscv_isac/plugins/riscv_opcodes/rv_zba new file mode 100644 index 0000000..65eb420 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zba @@ -0,0 +1,3 @@ +sh1add rd rs1 rs2 31..25=16 14..12=2 6..2=0x0C 1..0=3 +sh2add rd rs1 rs2 31..25=16 14..12=4 6..2=0x0C 1..0=3 +sh3add rd rs1 rs2 31..25=16 14..12=6 6..2=0x0C 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbb b/riscv_isac/plugins/riscv_opcodes/rv_zbb new file mode 100644 index 0000000..9f384f6 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zbb @@ -0,0 +1,15 @@ +andn rd rs1 rs2 31..25=32 14..12=7 6..2=0x0C 1..0=3 +orn rd rs1 rs2 31..25=32 14..12=6 6..2=0x0C 1..0=3 +xnor rd rs1 rs2 31..25=32 14..12=4 6..2=0x0C 1..0=3 +clz rd rs1 31..20=0x600 14..12=1 6..2=0x04 1..0=3 +ctz rd rs1 31..20=0x601 14..12=1 6..2=0x04 1..0=3 +cpop rd rs1 31..20=0x602 14..12=1 6..2=0x04 1..0=3 +max rd rs1 rs2 31..25=5 14..12=6 6..2=0x0C 1..0=3 +maxu rd rs1 rs2 31..25=5 14..12=7 6..2=0x0C 1..0=3 +min rd rs1 rs2 31..25=5 14..12=4 6..2=0x0C 1..0=3 +minu rd rs1 rs2 31..25=5 14..12=5 6..2=0x0C 1..0=3 +sext.b rd rs1 31..20=0x604 14..12=1 6..2=0x04 1..0=3 +sext.h rd rs1 31..20=0x605 14..12=1 6..2=0x04 1..0=3 +rol rd rs1 rs2 31..25=0x30 14..12=1 6..2=0x0C 1..0=3 +ror rd rs1 rs2 31..25=0x30 14..12=5 6..2=0x0C 1..0=3 +$pseudo_op rv64_zbp::gorci orc.b rd rs1 31..20=0x287 14..12=0x5 6..0=0x13 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbc b/riscv_isac/plugins/riscv_opcodes/rv_zbc new file mode 100644 index 0000000..c2494bd --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zbc @@ -0,0 +1,4 @@ +clmul rd rs1 rs2 31..25=5 14..12=1 6..2=0x0C 1..0=3 +clmulr rd rs1 rs2 31..25=5 14..12=2 6..2=0x0C 1..0=3 +clmulh rd rs1 rs2 31..25=5 14..12=3 6..2=0x0C 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbe b/riscv_isac/plugins/riscv_opcodes/rv_zbe new file mode 100644 index 0000000..1e8a037 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zbe @@ -0,0 +1,5 @@ +bcompress rd rs1 rs2 31..25=4 14..12=6 6..2=0x0C 1..0=3 +bdecompress rd rs1 rs2 31..25=36 14..12=6 6..2=0x0C 1..0=3 +pack rd rs1 rs2 31..25=4 14..12=4 6..2=0x0C 1..0=3 +packh rd rs1 rs2 31..25=4 14..12=7 6..2=0x0C 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbf b/riscv_isac/plugins/riscv_opcodes/rv_zbf new file mode 100644 index 0000000..33dd0a6 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zbf @@ -0,0 +1,4 @@ +bfp rd rs1 rs2 31..25=36 14..12=7 6..2=0x0C 1..0=3 +$import rv_zbe::pack +$import rv_zbe::packh + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbkb b/riscv_isac/plugins/riscv_opcodes/rv_zbkb new file mode 100644 index 0000000..1499d78 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zbkb @@ -0,0 +1,8 @@ +$import rv_zbb::rol +$import rv_zbb::ror +$import rv_zbb::andn +$import rv_zbb::orn +$import rv_zbb::xnor +$import rv_zbe::pack +$import rv_zbe::packh +$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbkc b/riscv_isac/plugins/riscv_opcodes/rv_zbkc new file mode 100644 index 0000000..b82588f --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zbkc @@ -0,0 +1,2 @@ +$import rv_zbc::clmul +$import rv_zbc::clmulh diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbkx b/riscv_isac/plugins/riscv_opcodes/rv_zbkx new file mode 100644 index 0000000..b035a6b --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zbkx @@ -0,0 +1,3 @@ +# TODO - confirm if below 4 instructions should be imported ops since zbp is not ratified +$import rv_zbp::xperm4 +$import rv_zbp::xperm8 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbp b/riscv_isac/plugins/riscv_opcodes/rv_zbp new file mode 100644 index 0000000..b66d6b4 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zbp @@ -0,0 +1,15 @@ +$import rv_zbb::andn +$import rv_zbb::orn +$import rv_zbb::xnor +$import rv_zbe::pack +$import rv_zbe::packh +$import rv_zbb::rol +$import rv_zbb::ror +grev rd rs1 rs2 31..25=52 14..12=5 6..2=0x0C 1..0=3 +gorc rd rs1 rs2 31..25=20 14..12=5 6..2=0x0C 1..0=3 +shfl rd rs1 rs2 31..25=4 14..12=1 6..2=0x0C 1..0=3 +unshfl rd rs1 rs2 31..25=4 14..12=5 6..2=0x0C 1..0=3 +xperm4 rd rs1 rs2 31..25=20 14..12=2 6..2=0x0C 1..0=3 +xperm8 rd rs1 rs2 31..25=20 14..12=4 6..2=0x0C 1..0=3 +xperm16 rd rs1 rs2 31..25=20 14..12=6 6..2=0x0C 1..0=3 +packu rd rs1 rs2 31..25=36 14..12=4 6..2=0x0C 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbpbo b/riscv_isac/plugins/riscv_opcodes/rv_zbpbo new file mode 100644 index 0000000..356fbb2 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zbpbo @@ -0,0 +1,6 @@ +$import rv_zbe::pack +$import rv_zbp::packu +$import rv_zbb::max +$import rv_zbb::min +$import rv_zbt::cmix +$pseudo_op rv64_zbp::grevi rev8.h rd rs1 31..20=0x688 14..12=5 6..0=0x13 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbr b/riscv_isac/plugins/riscv_opcodes/rv_zbr new file mode 100644 index 0000000..3cfd5a7 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zbr @@ -0,0 +1,7 @@ +crc32.b rd rs1 31..20=0x610 14..12=1 6..2=0x04 1..0=3 +crc32.h rd rs1 31..20=0x611 14..12=1 6..2=0x04 1..0=3 +crc32.w rd rs1 31..20=0x612 14..12=1 6..2=0x04 1..0=3 +crc32c.b rd rs1 31..20=0x618 14..12=1 6..2=0x04 1..0=3 +crc32c.h rd rs1 31..20=0x619 14..12=1 6..2=0x04 1..0=3 +crc32c.w rd rs1 31..20=0x61A 14..12=1 6..2=0x04 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbs b/riscv_isac/plugins/riscv_opcodes/rv_zbs new file mode 100644 index 0000000..1949072 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zbs @@ -0,0 +1,5 @@ +bclr rd rs1 rs2 31..25=0x24 14..12=1 6..2=0x0C 1..0=3 +bext rd rs1 rs2 31..25=36 14..12=5 6..2=0x0C 1..0=3 +binv rd rs1 rs2 31..25=52 14..12=1 6..2=0x0C 1..0=3 +bset rd rs1 rs2 31..25=20 14..12=1 6..2=0x0C 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbt b/riscv_isac/plugins/riscv_opcodes/rv_zbt new file mode 100644 index 0000000..9e7b98b --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zbt @@ -0,0 +1,6 @@ +cmix rd rs1 rs2 rs3 26..25=3 14..12=1 6..2=0x0C 1..0=3 +cmov rd rs1 rs2 rs3 26..25=3 14..12=5 6..2=0x0C 1..0=3 + +fsl rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0C 1..0=3 +fsr rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0C 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zfh b/riscv_isac/plugins/riscv_opcodes/rv_zfh new file mode 100644 index 0000000..532dde5 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zfh @@ -0,0 +1,30 @@ +flh rd rs1 imm12 14..12=1 6..2=0x01 1..0=3 +fsh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x09 1..0=3 +fmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x10 1..0=3 +fmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x11 1..0=3 +fnmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x12 1..0=3 +fnmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x13 1..0=3 +fadd.h rd rs1 rs2 31..27=0x00 rm 26..25=2 6..2=0x14 1..0=3 +fsub.h rd rs1 rs2 31..27=0x01 rm 26..25=2 6..2=0x14 1..0=3 +fmul.h rd rs1 rs2 31..27=0x02 rm 26..25=2 6..2=0x14 1..0=3 +fdiv.h rd rs1 rs2 31..27=0x03 rm 26..25=2 6..2=0x14 1..0=3 +fsqrt.h rd rs1 24..20=0 31..27=0x0B rm 26..25=2 6..2=0x14 1..0=3 +fsgnj.h rd rs1 rs2 31..27=0x04 14..12=0 26..25=2 6..2=0x14 1..0=3 +fsgnjn.h rd rs1 rs2 31..27=0x04 14..12=1 26..25=2 6..2=0x14 1..0=3 +fsgnjx.h rd rs1 rs2 31..27=0x04 14..12=2 26..25=2 6..2=0x14 1..0=3 +fmin.h rd rs1 rs2 31..27=0x05 14..12=0 26..25=2 6..2=0x14 1..0=3 +fmax.h rd rs1 rs2 31..27=0x05 14..12=1 26..25=2 6..2=0x14 1..0=3 +fcvt.s.h rd rs1 24..20=2 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.h.s rd rs1 24..20=0 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 + +feq.h rd rs1 rs2 31..27=0x14 14..12=2 26..25=2 6..2=0x14 1..0=3 +flt.h rd rs1 rs2 31..27=0x14 14..12=1 26..25=2 6..2=0x14 1..0=3 +fle.h rd rs1 rs2 31..27=0x14 14..12=0 26..25=2 6..2=0x14 1..0=3 +fclass.h rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=2 6..2=0x14 1..0=3 +fcvt.w.h rd rs1 24..20=0 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.wu.h rd rs1 24..20=1 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fmv.x.h rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=2 6..2=0x14 1..0=3 +fcvt.h.w rd rs1 24..20=0 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +fcvt.h.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +fmv.h.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=2 6..2=0x14 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zicbo b/riscv_isac/plugins/riscv_opcodes/rv_zicbo new file mode 100644 index 0000000..65a4567 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zicbo @@ -0,0 +1,12 @@ +# Zicbom: cache-block management instructions +cbo.clean rs1 31..20=1 14..12=2 11..7=0 6..2=0x03 1..0=3 +cbo.flush rs1 31..20=2 14..12=2 11..7=0 6..2=0x03 1..0=3 +cbo.inval rs1 31..20=0 14..12=2 11..7=0 6..2=0x03 1..0=3 + +# Zicboz: cache-block zero instruction +cbo.zero rs1 31..20=4 14..12=2 11..7=0 6..2=0x03 1..0=3 + +# Zicbop: prefetch hint pseudoinstructions +$pseudo_op rv_i::ori prefetch.i rs1 imm12hi 24..20=0 14..12=6 11..7=0 6..2=0x04 1..0=3 +$pseudo_op rv_i::ori prefetch.r rs1 imm12hi 24..20=1 14..12=6 11..7=0 6..2=0x04 1..0=3 +$pseudo_op rv_i::ori prefetch.w rs1 imm12hi 24..20=3 14..12=6 11..7=0 6..2=0x04 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zicsr b/riscv_isac/plugins/riscv_opcodes/rv_zicsr new file mode 100644 index 0000000..9d54aff --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zicsr @@ -0,0 +1,7 @@ +csrrw rd rs1 imm12 14..12=1 6..2=0x1C 1..0=3 +csrrs rd rs1 imm12 14..12=2 6..2=0x1C 1..0=3 +csrrc rd rs1 imm12 14..12=3 6..2=0x1C 1..0=3 +csrrwi rd imm12 zimm 14..12=5 6..2=0x1C 1..0=3 +csrrsi rd imm12 zimm 14..12=6 6..2=0x1C 1..0=3 +csrrci rd imm12 zimm 14..12=7 6..2=0x1C 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zifencei b/riscv_isac/plugins/riscv_opcodes/rv_zifencei new file mode 100644 index 0000000..8f9ec85 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zifencei @@ -0,0 +1,2 @@ +fence.i imm12 rs1 14..12=1 rd 6..2=0x03 1..0=3 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zk b/riscv_isac/plugins/riscv_opcodes/rv_zk new file mode 100644 index 0000000..c4dc854 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zk @@ -0,0 +1,24 @@ +# import zbkb +$import rv_zbb::rol +$import rv_zbb::ror +$import rv_zbb::andn +$import rv_zbb::orn +$import rv_zbb::xnor +$import rv_zbe::pack +$import rv_zbe::packh +$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 + +#import zbkc +$import rv_zbc::clmul +$import rv_zbc::clmulh + +#import zbkx +$import rv_zbp::xperm4 +$import rv_zbp::xperm8 + +#import zknh +# Scalar SHA256 - RV32/RV64 +$import rv_zknh::sha256sum0 +$import rv_zknh::sha256sum1 +$import rv_zknh::sha256sig0 +$import rv_zknh::sha256sig1 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zkn b/riscv_isac/plugins/riscv_opcodes/rv_zkn new file mode 100644 index 0000000..c4dc854 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zkn @@ -0,0 +1,24 @@ +# import zbkb +$import rv_zbb::rol +$import rv_zbb::ror +$import rv_zbb::andn +$import rv_zbb::orn +$import rv_zbb::xnor +$import rv_zbe::pack +$import rv_zbe::packh +$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 + +#import zbkc +$import rv_zbc::clmul +$import rv_zbc::clmulh + +#import zbkx +$import rv_zbp::xperm4 +$import rv_zbp::xperm8 + +#import zknh +# Scalar SHA256 - RV32/RV64 +$import rv_zknh::sha256sum0 +$import rv_zknh::sha256sum1 +$import rv_zknh::sha256sig0 +$import rv_zknh::sha256sig1 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zknh b/riscv_isac/plugins/riscv_opcodes/rv_zknh new file mode 100644 index 0000000..2079628 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zknh @@ -0,0 +1,5 @@ +# Scalar SHA256 - RV32/RV64 +sha256sum0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00000 14..12=1 6..0=0x13 +sha256sum1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00001 14..12=1 6..0=0x13 +sha256sig0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00010 14..12=1 6..0=0x13 +sha256sig1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00011 14..12=1 6..0=0x13 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zks b/riscv_isac/plugins/riscv_opcodes/rv_zks new file mode 100644 index 0000000..f88a09b --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zks @@ -0,0 +1,26 @@ +# import zbkb +$import rv_zbb::rol +$import rv_zbb::ror +$import rv_zbb::andn +$import rv_zbb::orn +$import rv_zbb::xnor +$import rv_zbe::pack +$import rv_zbe::packh +$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 + +#import zbkc +$import rv_zbc::clmul +$import rv_zbc::clmulh + +#import zbkx +$import rv_zbp::xperm4 +$import rv_zbp::xperm8 + +# Scalar SM4 - RV32, RV64 +$import rv_zksed::sm4ed +$import rv_zksed::sm4ks + +# Scalar SM3 - RV32, RV64 +$import rv_zksh::sm3p0 +$import rv_zksh::sm3p1 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zksed b/riscv_isac/plugins/riscv_opcodes/rv_zksed new file mode 100644 index 0000000..92e17c5 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zksed @@ -0,0 +1,4 @@ +# Scalar SM4 - RV32, RV64 +sm4ed rd rs1 rs2 bs 29..25=0b11000 14..12=0 6..0=0x33 +sm4ks rd rs1 rs2 bs 29..25=0b11010 14..12=0 6..0=0x33 + diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zksh b/riscv_isac/plugins/riscv_opcodes/rv_zksh new file mode 100644 index 0000000..f21eaa8 --- /dev/null +++ b/riscv_isac/plugins/riscv_opcodes/rv_zksh @@ -0,0 +1,4 @@ +# Scalar SM3 - RV32, RV64 +sm3p0 rd rs1 31..30=0 29..25=0b01000 24..20=0b01000 14..12=1 6..0=0x13 +sm3p1 rd rs1 31..30=0 29..25=0b01000 24..20=0b01001 14..12=1 6..0=0x13 + From 0357555d26e8d9aa1b942506618839e834246660 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Sat, 19 Mar 2022 10:03:51 +0530 Subject: [PATCH 10/41] Beter file management --- riscv_isac/plugins/rv_opcodes_decoder.py | 131 +++++++++++------------ 1 file changed, 61 insertions(+), 70 deletions(-) diff --git a/riscv_isac/plugins/rv_opcodes_decoder.py b/riscv_isac/plugins/rv_opcodes_decoder.py index 8f6bb58..b358345 100644 --- a/riscv_isac/plugins/rv_opcodes_decoder.py +++ b/riscv_isac/plugins/rv_opcodes_decoder.py @@ -86,8 +86,7 @@ def process_enc_line(line: str): # extract bit pattern assignments of the form hi..lo=val. fixed_ranges is a # regex expression present in constants.py. The extracted patterns are # captured as a list in args where each entry is a tuple (msb, lsb, value) - opcode = '' - id = 0 + opcode_parsed = fixed_ranges.findall(remaining) opcode_functs = [] for func in opcode_parsed: @@ -98,50 +97,34 @@ def process_enc_line(line: str): for (msb, lsb, value) in opcode_functs: flen = msb - lsb + 1 value = f"{value:0{flen}b}" - if lsb == id: - opcode = value + opcode - id = id + flen - else: - # Standard functs - if flen == 2: - if lsb == arg_lut['funct2'][1]: - func_len = func2 - else: - func_len = (msb, lsb) - elif flen == 3: - if lsb == arg_lut['funct3'][1]: - func_len = func3 - else: - func_len = (msb, lsb) - elif flen == 7: - if lsb == arg_lut['funct7'][1]: - func_len = func7 - else: - func_len = (msb, lsb) - - # Non standard functs + # Standard functs + if flen == 2: + if lsb == arg_lut['funct2'][1]: + func_len = func2 + else: + func_len = (msb, lsb) + elif flen == 3: + if lsb == arg_lut['funct3'][1]: + func_len = func3 + else: + func_len = (msb, lsb) + elif flen == 7: + if lsb == arg_lut['funct7'][1]: + func_len = func7 else: func_len = (msb, lsb) - functs.append((func_len, int(value, 2))) + + # Non standard functs + else: + func_len = (msb, lsb) + functs.append((func_len, int(value, 2))) # parse through the args args_list = fixed_ranges.sub(' ', remaining) args_list = single_fixed.sub(' ', args_list).split() for arg in args_list: - if arg == 'rd': - functs.insert(0, (rd_check, True)) args.append(get_arg_val(arg)) - - if len(opcode) > 7: - functs.insert(0, (rd_check, False)) - - opcode = int(opcode, 2) - first_two = opcode & rvOpcodesDecoder.FIRST_TWO - if first_two == 3: - is_compressed = False - else: - is_compressed = True - + # do the same as above but for = pattern. single_fixed is a regex # expression present in constants.py for (lsb, value, drop) in single_fixed.findall(remaining): @@ -149,9 +132,7 @@ def process_enc_line(line: str): value = int(value, 0) functs.append(((lsb, lsb), value)) - # update the fields of the instruction as a dict and return back along with - # the name of the instruction - return (is_compressed, opcode, functs, (name, args)) + return (functs, (name, args)) def create_inst_dict(file_filter): opcodes_dir = f'./riscv_opcodes/' @@ -180,12 +161,9 @@ def create_inst_dict(file_filter): if '$import' in line or '$pseudo' in line: continue - # call process_enc_line to get the data about the current - # instruction - (is_compressed, opcode, functs, (name, args)) = rvOpcodesDecoder.process_enc_line(line) - + (functs, (name, args)) = rvOpcodesDecoder.process_enc_line(line) - func_dict = rvOpcodesDecoder.INS_DICT[is_compressed][opcode] + func_dict = rvOpcodesDecoder.INS_DICT for func in functs: func_dict = func_dict[func[0]] func_dict = func_dict[func[-1]] @@ -195,31 +173,26 @@ def create_inst_dict(file_filter): def get_instr(func_dict, mcode: int): # Get list of functions keys = func_dict.keys() - print(keys) for key in keys: - if type(key) == str: + if type(key) == str: return func_dict if type(key) == tuple: val = get_funct(key, mcode) # Non standard fields else: val = key(mcode) # Standard fields - print(val) - if key == rd_check: - val = True if val else False temp_func_dict = func_dict[key][val] if temp_func_dict.keys(): - return rvOpcodesDecoder.get_instr(temp_func_dict, mcode) + a = rvOpcodesDecoder.get_instr(temp_func_dict, mcode) + if a == None: + continue + else: + return a else: continue def decoder(self, mcode): - inst_type = False - if (mcode & rvOpcodesDecoder.FIRST_TWO != 3): - inst_type = True - - op_code = mcode & rvOpcodesDecoder.OPCODE_MASK - func_dict = rvOpcodesDecoder.INS_DICT[inst_type][op_code] - + + func_dict = rvOpcodesDecoder.INS_DICT name_args = rvOpcodesDecoder.get_instr(func_dict, mcode) #TODO Create instruction object @@ -242,10 +215,12 @@ def print_instr_dict(): rvOpcodesDecoder.print_instr_dict() # Tests - decoder.decoder(0x0a001033) + name = decoder.decoder(0x8000202f).keys() + print(name) - '''f1 = open('./tests/none_result.txt', 'w+') - f2 = open('./tests/yes_result.txt' , 'w+') + f1 = open('./tests/none_result.txt', 'w+') + f2 = open('./tests/matches_results.txt' , 'w+') + f3 = open('./tests/no_matches_results.txt' , 'w+') with open('./tests/ratified.txt', 'r') as fp: for line in fp: @@ -255,14 +230,30 @@ def print_instr_dict(): old_decoder = disassembler() old_decoder.setup('rv32') - res = old_decoder.decode(ins_obj) - if res == None: - continue - old_res = res.instr_name + + old_res = old_decoder.decode(ins_obj).instr_name result = decoder.decoder(code) - if result == None: - f1.write(f'None for {line} and {old_res} for internal decoder\n') + + if old_res: + old_res = old_res.replace('.', '_') + else: + old_res = None + + if result != None: + result = list(decoder.decoder(code).keys())[0] + + if result and old_res: + if old_res == result: + f2.write(f'Match found! {result} for {line}\n') + else: + f3.write(f'Not matching! {line}: {result} for rvopcodes-decoder; {old_res} for internal decoder\n') else: - f2.write(f'{str(result.keys())} for {line} and {old_res} for internal decoder\n') + if not result: + result = 'None' + if not old_res: + old_res = 'None' + f1.write(f'{line}: {result} for rvopcodes-decoder; {old_res} for internal decoder\n') + f1.close() - f2.close()''' \ No newline at end of file + f2.close() + f3.close() \ No newline at end of file From 9b7348639a78ee8ba443c3f7e34f8c568ed91d16 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Sat, 19 Mar 2022 11:40:12 +0530 Subject: [PATCH 11/41] Corrected funct3 for csrrci instruction --- riscv_isac/plugins/internaldecoder.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv_isac/plugins/internaldecoder.py b/riscv_isac/plugins/internaldecoder.py index 7b2a43b..d9cb288 100644 --- a/riscv_isac/plugins/internaldecoder.py +++ b/riscv_isac/plugins/internaldecoder.py @@ -1363,7 +1363,7 @@ def priviledged_ops(self, instrObj): instrObj.instr_name = 'csrrsi' instrObj.rs1 = None instrObj.zimm = rs1[0] - if funct3 == 0b101: + if funct3 == 0b111: instrObj.instr_name = 'csrrci' instrObj.rs1 = None instrObj.zimm = rs1[0] From e80a5f38faee8718d447c56c3daeedc06fb5d97c Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Wed, 23 Mar 2022 09:28:25 +0530 Subject: [PATCH 12/41] Occurrence based prioritization --- riscv_isac/plugins/rv_opcodes_decoder.py | 91 ++++++++++++++++-------- 1 file changed, 62 insertions(+), 29 deletions(-) diff --git a/riscv_isac/plugins/rv_opcodes_decoder.py b/riscv_isac/plugins/rv_opcodes_decoder.py index b358345..f375f59 100644 --- a/riscv_isac/plugins/rv_opcodes_decoder.py +++ b/riscv_isac/plugins/rv_opcodes_decoder.py @@ -1,8 +1,11 @@ import glob +from lib2to3.pgen2.token import VBAREQUAL from operator import itemgetter from collections import defaultdict import pprint +from attr import field + from constants import * from riscv_isac.InstructionObject import instructionObject @@ -94,30 +97,13 @@ def process_enc_line(line: str): # Sort in ascending order of lsb opcode_functs = sorted(opcode_functs, key=itemgetter(1)) + for (msb, lsb, value) in opcode_functs: flen = msb - lsb + 1 value = f"{value:0{flen}b}" - # Standard functs - if flen == 2: - if lsb == arg_lut['funct2'][1]: - func_len = func2 - else: - func_len = (msb, lsb) - elif flen == 3: - if lsb == arg_lut['funct3'][1]: - func_len = func3 - else: - func_len = (msb, lsb) - elif flen == 7: - if lsb == arg_lut['funct7'][1]: - func_len = func7 - else: - func_len = (msb, lsb) - - # Non standard functs - else: - func_len = (msb, lsb) - functs.append((func_len, int(value, 2))) + value = int(value, 2) + funct = (msb, lsb) + functs.append((funct, value)) # parse through the args args_list = fixed_ranges.sub(' ', remaining) @@ -140,6 +126,9 @@ def create_inst_dict(file_filter): # file_names contains all files to be parsed in the riscv-opcodes directory file_names = glob.glob(f'{opcodes_dir}rv{file_filter}') + funct_priority = dict() + instr_list = list() + # first pass if for standard/original instructions for f in file_names: with open(f) as fp: @@ -163,16 +152,58 @@ def create_inst_dict(file_filter): (functs, (name, args)) = rvOpcodesDecoder.process_enc_line(line) - func_dict = rvOpcodesDecoder.INS_DICT + # Priority dictionary + for funct in functs: + if funct[0] in funct_priority: + count = funct_priority[funct[0]] + count += 1 + funct_priority[funct[0]] = count + else: + funct_priority[funct[0]] = 1 + + # [ [(funct, val)], name, [args] ] + instr_list.append([functs, name, args]) + + + '''func_dict = rvOpcodesDecoder.INS_DICT for func in functs: func_dict = func_dict[func[0]] func_dict = func_dict[func[-1]] - func_dict[name] = args - + func_dict[name] = args''' + + op_end = 2 + # Sort functions for each instruction + for i in range(len(instr_list)): + op = instr_list[i][0][0:op_end] + functs = instr_list[i][0][op_end:] + p_list = [] + for funct in functs: + p_list.append(funct_priority[funct[0]]) + + functs_sorted = [x for _,x in sorted(zip(p_list, functs), key=lambda key: key[0], reverse=True)] + fields = op + functs_sorted + instr_list[i][0] = fields + + + if instr_list[i][1] == 'lr_w': + print(functs) + print(p_list) + print(fields) + print(fields) + + for instr in instr_list: + funct_dict = rvOpcodesDecoder.INS_DICT + for funct in instr[0]: + funct_dict = funct_dict[funct[0]] + funct_dict = funct_dict[funct[-1]] + + funct_dict[instr[1]] = instr[2] + def get_instr(func_dict, mcode: int): # Get list of functions keys = func_dict.keys() + print(keys) for key in keys: if type(key) == str: return func_dict @@ -180,13 +211,14 @@ def get_instr(func_dict, mcode: int): val = get_funct(key, mcode) # Non standard fields else: val = key(mcode) # Standard fields + print(val) temp_func_dict = func_dict[key][val] if temp_func_dict.keys(): a = rvOpcodesDecoder.get_instr(temp_func_dict, mcode) - if a == None: - continue - else: - return a + #if a == None: + # continue + #else: + return a else: continue @@ -218,6 +250,7 @@ def print_instr_dict(): name = decoder.decoder(0x8000202f).keys() print(name) + ''' f1 = open('./tests/none_result.txt', 'w+') f2 = open('./tests/matches_results.txt' , 'w+') f3 = open('./tests/no_matches_results.txt' , 'w+') @@ -256,4 +289,4 @@ def print_instr_dict(): f1.close() f2.close() - f3.close() \ No newline at end of file + f3.close()''' \ No newline at end of file From 5ba0c3cdfe2971ec52c5879363cacbb989ce1d66 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Sat, 26 Mar 2022 08:27:16 +0530 Subject: [PATCH 13/41] Insertion optimization --- riscv_isac/plugins/rv_opcodes_decoder.py | 255 ++++++++++++++--------- 1 file changed, 153 insertions(+), 102 deletions(-) diff --git a/riscv_isac/plugins/rv_opcodes_decoder.py b/riscv_isac/plugins/rv_opcodes_decoder.py index f375f59..30631dc 100644 --- a/riscv_isac/plugins/rv_opcodes_decoder.py +++ b/riscv_isac/plugins/rv_opcodes_decoder.py @@ -1,14 +1,13 @@ import glob -from lib2to3.pgen2.token import VBAREQUAL from operator import itemgetter from collections import defaultdict import pprint +from statistics import mode -from attr import field +from ruamel import yaml as YAML from constants import * from riscv_isac.InstructionObject import instructionObject - from riscv_isac.plugins.internaldecoder import disassembler #export PYTHONPATH=/home/edwin/myrepos/riscv-isac/ @@ -23,29 +22,7 @@ def mcode_in(mcode: int): return val return mcode_in -# Standard functs -def func2(mcode: int): - (msb, lsb) = arg_lut['funct2'] - mask = int(''.join('1' * (msb - lsb + 1)), 2) << lsb - val = (mask & mcode) >> lsb - - return val - -def func3(mcode: int): - (msb, lsb) = arg_lut['funct3'] - mask = int(''.join('1' * (msb - lsb + 1)), 2) << lsb - val = (mask & mcode) >> lsb - - return val - -def func7(mcode: int): - (msb, lsb) = arg_lut['funct7'] - mask = int(''.join('1' * (msb - lsb + 1)), 2) << lsb - val = (mask & mcode) >> lsb - - return val - -# For Non standard functs +# Functs handler def get_funct(pos_tuple: tuple, mcode: int): msb = pos_tuple[0] lsb = pos_tuple[1] @@ -54,22 +31,19 @@ def get_funct(pos_tuple: tuple, mcode: int): return val -# For rd check: -def rd_check(mcode: int): - mask = 0x00000f80 - val = (mask & mcode) >> 7 - return val - class rvOpcodesDecoder: FIRST_TWO = 0x00000003 OPCODE_MASK = 0x0000007f + INST_LIST = [] + def __init__(self, file_filter: str): # Create nested dictionary nested_dict = lambda: defaultdict(nested_dict) - rvOpcodesDecoder.INS_DICT = nested_dict() + rvOpcodesDecoder.INST_DICT = nested_dict() + rvOpcodesDecoder.create_inst_dict(file_filter) def process_enc_line(line: str): @@ -97,19 +71,19 @@ def process_enc_line(line: str): # Sort in ascending order of lsb opcode_functs = sorted(opcode_functs, key=itemgetter(1)) - for (msb, lsb, value) in opcode_functs: flen = msb - lsb + 1 value = f"{value:0{flen}b}" value = int(value, 2) funct = (msb, lsb) + functs.append((funct, value)) # parse through the args args_list = fixed_ranges.sub(' ', remaining) args_list = single_fixed.sub(' ', args_list).split() for arg in args_list: - args.append(get_arg_val(arg)) + args.append(arg) # do the same as above but for = pattern. single_fixed is a regex # expression present in constants.py @@ -125,9 +99,6 @@ def create_inst_dict(file_filter): # file_names contains all files to be parsed in the riscv-opcodes directory file_names = glob.glob(f'{opcodes_dir}rv{file_filter}') - - funct_priority = dict() - instr_list = list() # first pass if for standard/original instructions for f in file_names: @@ -152,91 +123,167 @@ def create_inst_dict(file_filter): (functs, (name, args)) = rvOpcodesDecoder.process_enc_line(line) - # Priority dictionary - for funct in functs: - if funct[0] in funct_priority: - count = funct_priority[funct[0]] - count += 1 - funct_priority[funct[0]] = count - else: - funct_priority[funct[0]] = 1 - # [ [(funct, val)], name, [args] ] - instr_list.append([functs, name, args]) - + rvOpcodesDecoder.INST_LIST.append([functs, name, args]) - '''func_dict = rvOpcodesDecoder.INS_DICT - for func in functs: - func_dict = func_dict[func[0]] - func_dict = func_dict[func[-1]] - - func_dict[name] = args''' + rvOpcodesDecoder.INST_DICT['root'] = rvOpcodesDecoder.INST_LIST + rvOpcodesDecoder.build_instr_dict(rvOpcodesDecoder.INST_DICT) + + def build_instr_dict(inst_dict): - op_end = 2 - # Sort functions for each instruction - for i in range(len(instr_list)): - op = instr_list[i][0][0:op_end] - functs = instr_list[i][0][op_end:] - p_list = [] - for funct in functs: - p_list.append(funct_priority[funct[0]]) - - functs_sorted = [x for _,x in sorted(zip(p_list, functs), key=lambda key: key[0], reverse=True)] - fields = op + functs_sorted - instr_list[i][0] = fields - - - if instr_list[i][1] == 'lr_w': - print(functs) - print(p_list) - print(fields) - print(fields) - - for instr in instr_list: - funct_dict = rvOpcodesDecoder.INS_DICT - for funct in instr[0]: - funct_dict = funct_dict[funct[0]] - funct_dict = funct_dict[funct[-1]] + # Get all instructions in the level + val = inst_dict['root'] + + # Gather all functs + funct_list = [item[0] for item in val] + funct_occ = [funct[0] for ins in funct_list for funct in ins] + + # Path recoder + funct_path = set() + # Check if there are functions remaining + while funct_occ: + if (1, 0) in funct_occ: + max_funct = (1, 0) + else: + max_funct = mode(funct_occ) + + funct_occ = list(filter(lambda a: a != max_funct, funct_occ)) + + i = 0 + # For each instruciton... + while i < len(val): + # For each funct of each instruction... + for funct in val[i][0]: + if funct[0] == max_funct: + # Max funct found! + + # Push into path recorder + funct_path.add(funct) + + # Push funct and its value into the dict + temp_dict = inst_dict[funct[0]][funct[1]] + + # Create empty list in the path + if not temp_dict: + inst_dict[funct[0]][funct[1]]['root'] = [] + + # Delete appended funct + temp = val[i] + temp[0].remove(funct) + + if temp[0]: + # Add to the path + inst_dict[funct[0]][funct[1]]['root'].append(temp) + + # Remove the copied instruction from previous list + inst_dict['root'].remove(val[i]) + else: + # Append name and args + temp_dict[temp[1]] = temp[2] + + i = i - 1 + + i = i + 1 + else: + # Remove previous root + del inst_dict['root'] + + for funct in funct_path: + + new_path = inst_dict[funct[0]][funct[1]] + a = rvOpcodesDecoder.build_instr_dict(new_path) + if a == None: + continue + else: + return a + return - funct_dict[instr[1]] = instr[2] - def get_instr(func_dict, mcode: int): # Get list of functions keys = func_dict.keys() - print(keys) for key in keys: if type(key) == str: return func_dict if type(key) == tuple: - val = get_funct(key, mcode) # Non standard fields - else: - val = key(mcode) # Standard fields - print(val) + val = get_funct(key, mcode) temp_func_dict = func_dict[key][val] if temp_func_dict.keys(): a = rvOpcodesDecoder.get_instr(temp_func_dict, mcode) - #if a == None: - # continue - #else: - return a + if a == None: + continue + else: + return a else: continue - def decoder(self, mcode): + def decoder(self, temp_instrobj: instructionObject): - func_dict = rvOpcodesDecoder.INS_DICT - name_args = rvOpcodesDecoder.get_instr(func_dict, mcode) - #TODO Create instruction object + mcode = temp_instrobj.instr + + name_args = rvOpcodesDecoder.get_instr(rvOpcodesDecoder.INST_DICT, mcode) + + # Fill out the partially filled instructionObject + if name_args: + instr_names = list(name_args.keys()) + if len(instr_names) <= 1: + # Fill instruction name + temp_instrobj.instr_name = instr_names[0] + + # Fill arguments + args = name_args[instr_names[0]] + imm = '' + for arg in args: + if arg == 'rd': + temp_instrobj.rd = get_arg_val(arg)(mcode) + if arg == 'rs1': + temp_instrobj.rs1 = get_arg_val(arg)(mcode) + if arg == 'rs2': + temp_instrobj.rs2 = get_arg_val(arg)(mcode) + if arg == 'rs3': + temp_instrobj.rs3 = get_arg_val(arg)(mcode) + if arg == 'csr': + temp_instrobj.csr = get_arg_val(arg)(mcode) + if arg == 'shamt': + temp_instrobj.shamt = get_arg_val(arg)(mcode) + if arg == 'succ': + temp_instrobj.succ = get_arg_val(arg)(mcode) + if arg == 'pred': + temp_instrobj.pred = get_arg_val(arg)(mcode) + if arg == 'rl': + temp_instrobj.rl = get_arg_val(arg)(mcode) + if arg == 'aq': + temp_instrobj.aq = get_arg_val(arg)(mcode) + if arg == 'rm': + temp_instrobj.rm = get_arg_val(arg)(mcode) + + if arg in ['imm12', 'imm20', 'zimm', 'imm2', 'imm3', 'imm4', 'imm5', 'imm']: + temp_instrobj.imm = get_arg_val(arg)(mcode) + if arg == 'jimm20': + imm_temp = get_arg_val(arg)(mcode) + print(imm_temp) + imm_temp = f'{imm_temp:0{20}b}' + #imm_temp = '123456789abcdefghijkl' + print(imm_temp) + imm = imm_temp[0] + imm_temp[12:21] + imm_temp[12] + imm_temp[1:11] + print(imm) + temp_instrobj.imm = int(imm, 2) + return temp_instrobj - return name_args + else: + print('Found two instructions in the leaf node') + def default_to_regular(d): + if isinstance(d, defaultdict): + d = {k: rvOpcodesDecoder.default_to_regular(v) for k, v in d.items()} + return d + def print_instr_dict(): printer = pprint.PrettyPrinter(indent=1, width=800, depth=None, stream=None, compact=False, sort_dicts=False) - s = printer.pformat(rvOpcodesDecoder.INS_DICT) + s = printer.pformat(rvOpcodesDecoder.default_to_regular(rvOpcodesDecoder.INST_DICT)) f = open('dict_tree.txt', 'w+') f.write(s) f.close() @@ -245,13 +292,17 @@ def print_instr_dict(): decoder = rvOpcodesDecoder('*') rvOpcodesDecoder.print_instr_dict() - + + ins = instructionObject(0x095050ef, '', '') + # Tests - name = decoder.decoder(0x8000202f).keys() - print(name) + name = decoder.decoder(ins).imm + print(hex(name)) + + #name = decoder.decoder(0x00000073).keys() + - ''' - f1 = open('./tests/none_result.txt', 'w+') + '''f1 = open('./tests/none_result.txt', 'w+') f2 = open('./tests/matches_results.txt' , 'w+') f3 = open('./tests/no_matches_results.txt' , 'w+') From 372a635dc19f637d06544df93cfee0e52c31d1b8 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Sat, 26 Mar 2022 10:38:49 +0530 Subject: [PATCH 14/41] Code cleanup --- .../.github/workflows/python-app.yml | 21 - riscv_isac/plugins/riscv_opcodes/LICENSE | 24 - riscv_isac/plugins/riscv_opcodes/Makefile | 44 - riscv_isac/plugins/riscv_opcodes/README.md | 19 - riscv_isac/plugins/riscv_opcodes/__init__.py | 0 riscv_isac/plugins/riscv_opcodes/constants.py | 588 -------- riscv_isac/plugins/riscv_opcodes/encoding.h | 306 ----- riscv_isac/plugins/riscv_opcodes/instrs.txt | 1221 ----------------- .../plugins/riscv_opcodes/opcodes-rvv-pseudo | 18 - riscv_isac/plugins/riscv_opcodes/parse.py | 779 ----------- riscv_isac/plugins/riscv_opcodes/rv128_c | 15 - riscv_isac/plugins/riscv_opcodes/rv32_c | 5 - riscv_isac/plugins/riscv_opcodes/rv32_c_f | 8 - riscv_isac/plugins/riscv_opcodes/rv32_i | 4 - riscv_isac/plugins/riscv_opcodes/rv32_p | 3 - riscv_isac/plugins/riscv_opcodes/rv32_zbb | 3 - riscv_isac/plugins/riscv_opcodes/rv32_zbkb | 4 - riscv_isac/plugins/riscv_opcodes/rv32_zbp | 7 - riscv_isac/plugins/riscv_opcodes/rv32_zbpbo | 5 - riscv_isac/plugins/riscv_opcodes/rv32_zbs | 5 - riscv_isac/plugins/riscv_opcodes/rv32_zbt | 2 - riscv_isac/plugins/riscv_opcodes/rv32_zk | 25 - riscv_isac/plugins/riscv_opcodes/rv32_zkn | 25 - riscv_isac/plugins/riscv_opcodes/rv32_zknd | 4 - riscv_isac/plugins/riscv_opcodes/rv32_zkne | 5 - riscv_isac/plugins/riscv_opcodes/rv32_zknh | 8 - riscv_isac/plugins/riscv_opcodes/rv32_zks | 6 - riscv_isac/plugins/riscv_opcodes/rv64_a | 12 - riscv_isac/plugins/riscv_opcodes/rv64_b | 9 - riscv_isac/plugins/riscv_opcodes/rv64_c | 17 - riscv_isac/plugins/riscv_opcodes/rv64_d | 7 - riscv_isac/plugins/riscv_opcodes/rv64_f | 7 - riscv_isac/plugins/riscv_opcodes/rv64_h | 5 - riscv_isac/plugins/riscv_opcodes/rv64_i | 17 - riscv_isac/plugins/riscv_opcodes/rv64_m | 6 - riscv_isac/plugins/riscv_opcodes/rv64_p | 81 -- riscv_isac/plugins/riscv_opcodes/rv64_q | 8 - riscv_isac/plugins/riscv_opcodes/rv64_zba | 5 - riscv_isac/plugins/riscv_opcodes/rv64_zbb | 9 - riscv_isac/plugins/riscv_opcodes/rv64_zbe | 4 - riscv_isac/plugins/riscv_opcodes/rv64_zbf | 3 - riscv_isac/plugins/riscv_opcodes/rv64_zbkb | 6 - riscv_isac/plugins/riscv_opcodes/rv64_zbm | 7 - riscv_isac/plugins/riscv_opcodes/rv64_zbp | 17 - riscv_isac/plugins/riscv_opcodes/rv64_zbpbo | 2 - riscv_isac/plugins/riscv_opcodes/rv64_zbr | 3 - riscv_isac/plugins/riscv_opcodes/rv64_zbs | 5 - riscv_isac/plugins/riscv_opcodes/rv64_zbt | 6 - riscv_isac/plugins/riscv_opcodes/rv64_zfh | 7 - riscv_isac/plugins/riscv_opcodes/rv64_zk | 28 - riscv_isac/plugins/riscv_opcodes/rv64_zkn | 28 - riscv_isac/plugins/riscv_opcodes/rv64_zknd | 7 - riscv_isac/plugins/riscv_opcodes/rv64_zkne | 5 - riscv_isac/plugins/riscv_opcodes/rv64_zknh | 6 - riscv_isac/plugins/riscv_opcodes/rv64_zks | 7 - riscv_isac/plugins/riscv_opcodes/rv_a | 11 - riscv_isac/plugins/riscv_opcodes/rv_b | 12 - riscv_isac/plugins/riscv_opcodes/rv_c | 32 - riscv_isac/plugins/riscv_opcodes/rv_c_d | 8 - riscv_isac/plugins/riscv_opcodes/rv_custom | 27 - riscv_isac/plugins/riscv_opcodes/rv_d | 26 - riscv_isac/plugins/riscv_opcodes/rv_d_zfh | 2 - riscv_isac/plugins/riscv_opcodes/rv_f | 26 - riscv_isac/plugins/riscv_opcodes/rv_h | 15 - riscv_isac/plugins/riscv_opcodes/rv_i | 46 - riscv_isac/plugins/riscv_opcodes/rv_m | 8 - riscv_isac/plugins/riscv_opcodes/rv_p | 245 ---- riscv_isac/plugins/riscv_opcodes/rv_pseudo | 26 - riscv_isac/plugins/riscv_opcodes/rv_q | 28 - riscv_isac/plugins/riscv_opcodes/rv_q_zfh | 2 - riscv_isac/plugins/riscv_opcodes/rv_s | 3 - riscv_isac/plugins/riscv_opcodes/rv_svinval | 7 - riscv_isac/plugins/riscv_opcodes/rv_system | 5 - riscv_isac/plugins/riscv_opcodes/rv_v | 528 ------- riscv_isac/plugins/riscv_opcodes/rv_zba | 3 - riscv_isac/plugins/riscv_opcodes/rv_zbb | 15 - riscv_isac/plugins/riscv_opcodes/rv_zbc | 4 - riscv_isac/plugins/riscv_opcodes/rv_zbe | 5 - riscv_isac/plugins/riscv_opcodes/rv_zbf | 4 - riscv_isac/plugins/riscv_opcodes/rv_zbkb | 8 - riscv_isac/plugins/riscv_opcodes/rv_zbkc | 2 - riscv_isac/plugins/riscv_opcodes/rv_zbkx | 3 - riscv_isac/plugins/riscv_opcodes/rv_zbp | 15 - riscv_isac/plugins/riscv_opcodes/rv_zbpbo | 6 - riscv_isac/plugins/riscv_opcodes/rv_zbr | 7 - riscv_isac/plugins/riscv_opcodes/rv_zbs | 5 - riscv_isac/plugins/riscv_opcodes/rv_zbt | 6 - riscv_isac/plugins/riscv_opcodes/rv_zfh | 30 - riscv_isac/plugins/riscv_opcodes/rv_zicbo | 12 - riscv_isac/plugins/riscv_opcodes/rv_zicsr | 7 - riscv_isac/plugins/riscv_opcodes/rv_zifencei | 2 - riscv_isac/plugins/riscv_opcodes/rv_zk | 24 - riscv_isac/plugins/riscv_opcodes/rv_zkn | 24 - riscv_isac/plugins/riscv_opcodes/rv_zknh | 5 - riscv_isac/plugins/riscv_opcodes/rv_zks | 26 - riscv_isac/plugins/riscv_opcodes/rv_zksed | 4 - riscv_isac/plugins/riscv_opcodes/rv_zksh | 4 - ...opcodes_decoder.py => rvopcodesdecoder.py} | 204 ++- 98 files changed, 101 insertions(+), 4859 deletions(-) delete mode 100644 riscv_isac/plugins/riscv_opcodes/.github/workflows/python-app.yml delete mode 100644 riscv_isac/plugins/riscv_opcodes/LICENSE delete mode 100644 riscv_isac/plugins/riscv_opcodes/Makefile delete mode 100644 riscv_isac/plugins/riscv_opcodes/README.md delete mode 100644 riscv_isac/plugins/riscv_opcodes/__init__.py delete mode 100644 riscv_isac/plugins/riscv_opcodes/constants.py delete mode 100644 riscv_isac/plugins/riscv_opcodes/encoding.h delete mode 100644 riscv_isac/plugins/riscv_opcodes/instrs.txt delete mode 100644 riscv_isac/plugins/riscv_opcodes/opcodes-rvv-pseudo delete mode 100755 riscv_isac/plugins/riscv_opcodes/parse.py delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv128_c delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_c delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_c_f delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_i delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_p delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zbb delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zbkb delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zbp delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zbpbo delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zbs delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zbt delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zk delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zkn delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zknd delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zkne delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zknh delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv32_zks delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_a delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_b delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_c delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_d delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_f delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_h delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_i delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_m delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_p delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_q delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zba delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbb delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbe delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbf delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbkb delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbm delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbp delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbpbo delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbr delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbs delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zbt delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zfh delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zk delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zkn delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zknd delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zkne delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zknh delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv64_zks delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_a delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_b delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_c delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_c_d delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_custom delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_d delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_d_zfh delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_f delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_h delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_i delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_m delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_p delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_pseudo delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_q delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_q_zfh delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_s delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_svinval delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_system delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_v delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zba delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbb delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbc delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbe delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbf delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbkb delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbkc delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbkx delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbp delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbpbo delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbr delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbs delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zbt delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zfh delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zicbo delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zicsr delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zifencei delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zk delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zkn delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zknh delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zks delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zksed delete mode 100644 riscv_isac/plugins/riscv_opcodes/rv_zksh rename riscv_isac/plugins/{rv_opcodes_decoder.py => rvopcodesdecoder.py} (65%) diff --git a/riscv_isac/plugins/riscv_opcodes/.github/workflows/python-app.yml b/riscv_isac/plugins/riscv_opcodes/.github/workflows/python-app.yml deleted file mode 100644 index e259c3e..0000000 --- a/riscv_isac/plugins/riscv_opcodes/.github/workflows/python-app.yml +++ /dev/null @@ -1,21 +0,0 @@ -name: Opcodes generation - -on: - push: - branches: [ master ] - pull_request: - branches: [ master ] - -jobs: - build: - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v2 - - name: Set up Python 3.8 - uses: actions/setup-python@v2 - with: - python-version: 3.8 - - name: Generation C code - run: cat opcodes-* | ./parse_opcodes -c > result.h - - name: Check C output - run: cat result.h | cpp diff --git a/riscv_isac/plugins/riscv_opcodes/LICENSE b/riscv_isac/plugins/riscv_opcodes/LICENSE deleted file mode 100644 index 34f576b..0000000 --- a/riscv_isac/plugins/riscv_opcodes/LICENSE +++ /dev/null @@ -1,24 +0,0 @@ -Copyright (c) 2010-2017, The Regents of the University of California -(Regents). All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: -1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. -3. Neither the name of the Regents nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - -IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING -OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS -BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED -HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE -MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. diff --git a/riscv_isac/plugins/riscv_opcodes/Makefile b/riscv_isac/plugins/riscv_opcodes/Makefile deleted file mode 100644 index 5a03913..0000000 --- a/riscv_isac/plugins/riscv_opcodes/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -SHELL := /bin/sh - -ISASIM_H := ../riscv-isa-sim/riscv/encoding.h -PK_H := ../riscv-pk/machine/encoding.h -ENV_H := ../riscv-tests/env/encoding.h -OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h -INSTALL_HEADER_FILES := $(ISASIM_H) $(PK_H) $(ENV_H) $(OPENOCD_H) - -ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-rv32b opcodes-rv64b opcodes-system opcodes-svinval opcodes-rv32zfh opcodes-rv32d-zfh opcodes-rv32q-zfh opcodes-rv64zfh opcodes-rvk opcodes-rv32k opcodes-rv64k opcodes-zicbo -ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-custom opcodes-rvv opcodes-rvp - -ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) opcodes-rvv-pseudo - -install: encoding.out.h inst.chisel instr-table.tex priv-instr-table.tex - set -e; for FILE in $(INSTALL_HEADER_FILES); do cp -f encoding.out.h $$FILE; done - -encoding.out.h: $(ALL_OPCODES) parse_opcodes encoding.h - echo "/*" > $@ - echo " * This file is auto-generated by running 'make' in" >> $@ - echo " * https://github.com/riscv/riscv-opcodes (`git log -1 --format="format:%h"`)" >> $@ - echo " */" >> $@ - echo >> $@ - cat encoding.h >> $@ - cat $(ALL_OPCODES) | python ./parse_opcodes -c >> $@ - -inst.chisel: $(ALL_OPCODES) parse_opcodes - cat $(ALL_OPCODES) | ./parse_opcodes -chisel > $@ - -inst.go: $(ALL_REAL_ILEN32_OPCODES) parse_opcodes - cat $(ALL_REAL_ILEN32_OPCODES) | ./parse_opcodes -go > $@ - -inst.rs: $(ALL_OPCODES) parse_opcodes - cat $(ALL_OPCODES) | ./parse_opcodes -rust > $@ - -inst.sverilog: $(ALL_OPCODES) parse_opcodes - cat $(ALL_OPCODES) | ./parse_opcodes -sverilog > $@ - -instr-table.tex: $(ALL_OPCODES) parse_opcodes - cat $(ALL_OPCODES) | ./parse_opcodes -tex > $@ - -priv-instr-table.tex: $(ALL_OPCODES) parse_opcodes - cat $(ALL_OPCODES) | ./parse_opcodes -privtex > $@ - -.PHONY : install diff --git a/riscv_isac/plugins/riscv_opcodes/README.md b/riscv_isac/plugins/riscv_opcodes/README.md deleted file mode 100644 index 5f4b98a..0000000 --- a/riscv_isac/plugins/riscv_opcodes/README.md +++ /dev/null @@ -1,19 +0,0 @@ -# riscv-opcodes - -This repo enumerates standard RISC-V instruction opcodes and control and -status registers. It also contains a script to convert them into several -formats (C, Scala, LaTeX). - -This repo is not meant to stand alone; it is a subcomponent of -[riscv-tools](https://github.com/riscv/riscv-tools) and assumes that it -is part of that directory structure. - -## File Convention - -1. `rv_x_y` - contains instructions common within the 32-bit and 64-bit modes when both x and y extensions are enabled (note in majority of the cases y will not exist). -2. `rv32_x_y` - contains instructions present in rv32xy only (absent in rv64X_Y eg. ???) -3. `rv64_x_y` - contains instructions present in rv64xy only (absent in rv32X_Y, eg. addw) -4. `_y` in the above is optional and can be null -5. for instructions present in multiple extensions, unless the spec allocates the instruction in a specific subset, the instruction encoding must be present in the first extension when canonically ordered. All other extensions can simply include a `$import prefix` followed by `` and `` separate by `::` . For e.g `pack` would be present in the `rv32_zbe` file as -`pack rd rs1 rs2 31..25=4 14..12=4 6..2=0x0C 1..0=3` and `rv32_zbf` and `rv32_zbp` files would have the following entries : `$import rv32_zbe::pack` -6. For pseudo ops we use `$pseudo_op :: ` to indicate the original instruction that this pseudo op depends on and the pseudo instructions encoding in the entirety For e.g. the pseudo op `frflags` will be represented as `pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3` diff --git a/riscv_isac/plugins/riscv_opcodes/__init__.py b/riscv_isac/plugins/riscv_opcodes/__init__.py deleted file mode 100644 index e69de29..0000000 diff --git a/riscv_isac/plugins/riscv_opcodes/constants.py b/riscv_isac/plugins/riscv_opcodes/constants.py deleted file mode 100644 index 4a268cd..0000000 --- a/riscv_isac/plugins/riscv_opcodes/constants.py +++ /dev/null @@ -1,588 +0,0 @@ -import re - - -isa_regex = \ -re.compile("^RV(32|64|128)[IE]+[ABCDEFGHJKLMNPQSTUVX]*(Zicsr|Zifencei|Zihintpause|Zam|Ztso|Zkne|Zknd|Zknh|Zkse|Zksh|Zkg|Zkb|Zkr|Zks|Zkn|Zba|Zbc|Zbb|Zbp|Zbr|Zbm|Zbs|Zbe|Zbf|Zbt|Zmmul|Zbpbo){,1}(_Zicsr){,1}(_Zifencei){,1}(_Zihintpause){,1}(_Zmmul){,1}(_Zam){,1}(_Zba){,1}(_Zbb){,1}(_Zbc){,1}(_Zbe){,1}(_Zbf){,1}(_Zbm){,1}(_Zbp){,1}(_Zbpbo){,1}(_Zbr){,1}(_Zbs){,1}(_Zbt){,1}(_Zkb){,1}(_Zkg){,1}(_Zkr){,1}(_Zks){,1}(_Zkn){,1}(_Zknd){,1}(_Zkne){,1}(_Zknh){,1}(_Zkse){,1}(_Zksh){,1}(_Ztso){,1}$") - -# regex to find ..= patterns in instruction -fixed_ranges = re.compile( - '\s*(?P\d+.?)\.\.(?P\d+.?)\s*=\s*(?P\d[\w]*)[\s$]*', re.M) - -# regex to find = patterns in instructions -#single_fixed = re.compile('\s+(?P\d+)=(?P[\w\d]*)[\s$]*', re.M) -single_fixed = re.compile('(?:^|[\s])(?P\d+)=(?P[\w]*)((?=\s|$))', re.M) - -# regex to find the overloading condition variable -var_regex = re.compile('(?P[a-zA-Z][\w\d]*)\s*=\s*.*?[\s$]*', re.M) - -# regex for pseudo op instructions returns the dependent filename, dependent -# instruction, the pseudo op name and the encoding string -pseudo_regex = re.compile( - '^\$pseudo_op\s+(?Prv[\d]*_[\w].*)::\s*(?P.*?)\s+(?P.*?)\s+(?P.*)$' -, re.M) - - -# -# Trap cause codes -causes = [ - (0x00, 'misaligned fetch'), - (0x01, 'fetch access'), - (0x02, 'illegal instruction'), - (0x03, 'breakpoint'), - (0x04, 'misaligned load'), - (0x05, 'load access'), - (0x06, 'misaligned store'), - (0x07, 'store access'), - (0x08, 'user_ecall'), - (0x09, 'supervisor_ecall'), - (0x0A, 'virtual_supervisor_ecall'), - (0x0B, 'machine_ecall'), - (0x0C, 'fetch page fault'), - (0x0D, 'load page fault'), - (0x0F, 'store page fault'), - (0x14, 'fetch guest page fault'), - (0x15, 'load guest page fault'), - (0x16, 'virtual instruction'), - (0x17, 'store guest page fault'), -] - -csrs = [ - # Standard User R/W - (0x001, 'fflags'), - (0x002, 'frm'), - (0x003, 'fcsr'), - (0x008, 'vstart'), - (0x009, 'vxsat'), - (0x00A, 'vxrm'), - (0x00F, 'vcsr'), - (0x015, 'seed'), # Zkr - - # Standard User RO - (0xC00, 'cycle'), - (0xC01, 'time'), - (0xC02, 'instret'), - (0xC03, 'hpmcounter3'), - (0xC04, 'hpmcounter4'), - (0xC05, 'hpmcounter5'), - (0xC06, 'hpmcounter6'), - (0xC07, 'hpmcounter7'), - (0xC08, 'hpmcounter8'), - (0xC09, 'hpmcounter9'), - (0xC0A, 'hpmcounter10'), - (0xC0B, 'hpmcounter11'), - (0xC0C, 'hpmcounter12'), - (0xC0D, 'hpmcounter13'), - (0xC0E, 'hpmcounter14'), - (0xC0F, 'hpmcounter15'), - (0xC10, 'hpmcounter16'), - (0xC11, 'hpmcounter17'), - (0xC12, 'hpmcounter18'), - (0xC13, 'hpmcounter19'), - (0xC14, 'hpmcounter20'), - (0xC15, 'hpmcounter21'), - (0xC16, 'hpmcounter22'), - (0xC17, 'hpmcounter23'), - (0xC18, 'hpmcounter24'), - (0xC19, 'hpmcounter25'), - (0xC1A, 'hpmcounter26'), - (0xC1B, 'hpmcounter27'), - (0xC1C, 'hpmcounter28'), - (0xC1D, 'hpmcounter29'), - (0xC1E, 'hpmcounter30'), - (0xC1F, 'hpmcounter31'), - (0xC20, 'vl'), - (0xC21, 'vtype'), - (0xC22, 'vlenb'), - - # Standard Supervisor R/W - (0x100, 'sstatus'), - (0x102, 'sedeleg'), - (0x103, 'sideleg'), - (0x104, 'sie'), - (0x105, 'stvec'), - (0x106, 'scounteren'), - (0x10A, 'senvcfg'), - (0x140, 'sscratch'), - (0x141, 'sepc'), - (0x142, 'scause'), - (0x143, 'stval'), - (0x144, 'sip'), - (0x180, 'satp'), - (0x5A8, 'scontext'), - - # Standard Hypervisor R/w - (0x200, 'vsstatus'), - (0x204, 'vsie'), - (0x205, 'vstvec'), - (0x240, 'vsscratch'), - (0x241, 'vsepc'), - (0x242, 'vscause'), - (0x243, 'vstval'), - (0x244, 'vsip'), - (0x280, 'vsatp'), - (0x600, 'hstatus'), - (0x602, 'hedeleg'), - (0x603, 'hideleg'), - (0x604, 'hie'), - (0x605, 'htimedelta'), - (0x606, 'hcounteren'), - (0x607, 'hgeie'), - (0x60A, 'henvcfg'), - (0x643, 'htval'), - (0x644, 'hip'), - (0x645, 'hvip'), - (0x64A, 'htinst'), - (0x680, 'hgatp'), - (0x6A8, 'hcontext'), - (0xE12, 'hgeip'), - - # Tentative CSR assignment for CLIC - (0x007, 'utvt'), - (0x045, 'unxti'), - (0x046, 'uintstatus'), - (0x048, 'uscratchcsw'), - (0x049, 'uscratchcswl'), - (0x107, 'stvt'), - (0x145, 'snxti'), - (0x146, 'sintstatus'), - (0x148, 'sscratchcsw'), - (0x149, 'sscratchcswl'), - (0x307, 'mtvt'), - (0x345, 'mnxti'), - (0x346, 'mintstatus'), - (0x348, 'mscratchcsw'), - (0x349, 'mscratchcswl'), - - # Standard Machine R/W - (0x300, 'mstatus'), - (0x301, 'misa'), - (0x302, 'medeleg'), - (0x303, 'mideleg'), - (0x304, 'mie'), - (0x305, 'mtvec'), - (0x306, 'mcounteren'), - (0x30a, 'menvcfg'), - (0x320, 'mcountinhibit'), - (0x340, 'mscratch'), - (0x341, 'mepc'), - (0x342, 'mcause'), - (0x343, 'mtval'), - (0x344, 'mip'), - (0x34a, 'mtinst'), - (0x34b, 'mtval2'), - (0x3a0, 'pmpcfg0'), - (0x3a1, 'pmpcfg1'), - (0x3a2, 'pmpcfg2'), - (0x3a3, 'pmpcfg3'), - (0x3a4, 'pmpcfg4'), - (0x3a5, 'pmpcfg5'), - (0x3a6, 'pmpcfg6'), - (0x3a7, 'pmpcfg7'), - (0x3a8, 'pmpcfg8'), - (0x3a9, 'pmpcfg9'), - (0x3aa, 'pmpcfg10'), - (0x3ab, 'pmpcfg11'), - (0x3ac, 'pmpcfg12'), - (0x3ad, 'pmpcfg13'), - (0x3ae, 'pmpcfg14'), - (0x3af, 'pmpcfg15'), - (0x3b0, 'pmpaddr0'), - (0x3b1, 'pmpaddr1'), - (0x3b2, 'pmpaddr2'), - (0x3b3, 'pmpaddr3'), - (0x3b4, 'pmpaddr4'), - (0x3b5, 'pmpaddr5'), - (0x3b6, 'pmpaddr6'), - (0x3b7, 'pmpaddr7'), - (0x3b8, 'pmpaddr8'), - (0x3b9, 'pmpaddr9'), - (0x3ba, 'pmpaddr10'), - (0x3bb, 'pmpaddr11'), - (0x3bc, 'pmpaddr12'), - (0x3bd, 'pmpaddr13'), - (0x3be, 'pmpaddr14'), - (0x3bf, 'pmpaddr15'), - (0x3c0, 'pmpaddr16'), - (0x3c1, 'pmpaddr17'), - (0x3c2, 'pmpaddr18'), - (0x3c3, 'pmpaddr19'), - (0x3c4, 'pmpaddr20'), - (0x3c5, 'pmpaddr21'), - (0x3c6, 'pmpaddr22'), - (0x3c7, 'pmpaddr23'), - (0x3c8, 'pmpaddr24'), - (0x3c9, 'pmpaddr25'), - (0x3ca, 'pmpaddr26'), - (0x3cb, 'pmpaddr27'), - (0x3cc, 'pmpaddr28'), - (0x3cd, 'pmpaddr29'), - (0x3ce, 'pmpaddr30'), - (0x3cf, 'pmpaddr31'), - (0x3d0, 'pmpaddr32'), - (0x3d1, 'pmpaddr33'), - (0x3d2, 'pmpaddr34'), - (0x3d3, 'pmpaddr35'), - (0x3d4, 'pmpaddr36'), - (0x3d5, 'pmpaddr37'), - (0x3d6, 'pmpaddr38'), - (0x3d7, 'pmpaddr39'), - (0x3d8, 'pmpaddr40'), - (0x3d9, 'pmpaddr41'), - (0x3da, 'pmpaddr42'), - (0x3db, 'pmpaddr43'), - (0x3dc, 'pmpaddr44'), - (0x3dd, 'pmpaddr45'), - (0x3de, 'pmpaddr46'), - (0x3df, 'pmpaddr47'), - (0x3e0, 'pmpaddr48'), - (0x3e1, 'pmpaddr49'), - (0x3e2, 'pmpaddr50'), - (0x3e3, 'pmpaddr51'), - (0x3e4, 'pmpaddr52'), - (0x3e5, 'pmpaddr53'), - (0x3e6, 'pmpaddr54'), - (0x3e7, 'pmpaddr55'), - (0x3e8, 'pmpaddr56'), - (0x3e9, 'pmpaddr57'), - (0x3ea, 'pmpaddr58'), - (0x3eb, 'pmpaddr59'), - (0x3ec, 'pmpaddr60'), - (0x3ed, 'pmpaddr61'), - (0x3ee, 'pmpaddr62'), - (0x3ef, 'pmpaddr63'), - (0x747, 'mseccfg'), - (0x7a0, 'tselect'), - (0x7a1, 'tdata1'), - (0x7a2, 'tdata2'), - (0x7a3, 'tdata3'), - (0x7a4, 'tinfo'), - (0x7a5, 'tcontrol'), - (0x7a8, 'mcontext'), - (0x7aa, 'mscontext'), - (0x7b0, 'dcsr'), - (0x7b1, 'dpc'), - (0x7b2, 'dscratch0'), - (0x7b3, 'dscratch1'), - (0xB00, 'mcycle'), - (0xB02, 'minstret'), - (0xB03, 'mhpmcounter3'), - (0xB04, 'mhpmcounter4'), - (0xB05, 'mhpmcounter5'), - (0xB06, 'mhpmcounter6'), - (0xB07, 'mhpmcounter7'), - (0xB08, 'mhpmcounter8'), - (0xB09, 'mhpmcounter9'), - (0xB0A, 'mhpmcounter10'), - (0xB0B, 'mhpmcounter11'), - (0xB0C, 'mhpmcounter12'), - (0xB0D, 'mhpmcounter13'), - (0xB0E, 'mhpmcounter14'), - (0xB0F, 'mhpmcounter15'), - (0xB10, 'mhpmcounter16'), - (0xB11, 'mhpmcounter17'), - (0xB12, 'mhpmcounter18'), - (0xB13, 'mhpmcounter19'), - (0xB14, 'mhpmcounter20'), - (0xB15, 'mhpmcounter21'), - (0xB16, 'mhpmcounter22'), - (0xB17, 'mhpmcounter23'), - (0xB18, 'mhpmcounter24'), - (0xB19, 'mhpmcounter25'), - (0xB1A, 'mhpmcounter26'), - (0xB1B, 'mhpmcounter27'), - (0xB1C, 'mhpmcounter28'), - (0xB1D, 'mhpmcounter29'), - (0xB1E, 'mhpmcounter30'), - (0xB1F, 'mhpmcounter31'), - (0x323, 'mhpmevent3'), - (0x324, 'mhpmevent4'), - (0x325, 'mhpmevent5'), - (0x326, 'mhpmevent6'), - (0x327, 'mhpmevent7'), - (0x328, 'mhpmevent8'), - (0x329, 'mhpmevent9'), - (0x32A, 'mhpmevent10'), - (0x32B, 'mhpmevent11'), - (0x32C, 'mhpmevent12'), - (0x32D, 'mhpmevent13'), - (0x32E, 'mhpmevent14'), - (0x32F, 'mhpmevent15'), - (0x330, 'mhpmevent16'), - (0x331, 'mhpmevent17'), - (0x332, 'mhpmevent18'), - (0x333, 'mhpmevent19'), - (0x334, 'mhpmevent20'), - (0x335, 'mhpmevent21'), - (0x336, 'mhpmevent22'), - (0x337, 'mhpmevent23'), - (0x338, 'mhpmevent24'), - (0x339, 'mhpmevent25'), - (0x33A, 'mhpmevent26'), - (0x33B, 'mhpmevent27'), - (0x33C, 'mhpmevent28'), - (0x33D, 'mhpmevent29'), - (0x33E, 'mhpmevent30'), - (0x33F, 'mhpmevent31'), - - # Standard Machine RO - (0xF11, 'mvendorid'), - (0xF12, 'marchid'), - (0xF13, 'mimpid'), - (0xF14, 'mhartid'), - (0xF15, 'mconfigptr'), -] - -csrs32 = [ - # Standard Hypervisor R/w - (0x615, 'htimedeltah'), - (0x61A, 'henvcfgh'), - - # Standard User RO - (0xC80, 'cycleh'), - (0xC81, 'timeh'), - (0xC82, 'instreth'), - (0xC83, 'hpmcounter3h'), - (0xC84, 'hpmcounter4h'), - (0xC85, 'hpmcounter5h'), - (0xC86, 'hpmcounter6h'), - (0xC87, 'hpmcounter7h'), - (0xC88, 'hpmcounter8h'), - (0xC89, 'hpmcounter9h'), - (0xC8A, 'hpmcounter10h'), - (0xC8B, 'hpmcounter11h'), - (0xC8C, 'hpmcounter12h'), - (0xC8D, 'hpmcounter13h'), - (0xC8E, 'hpmcounter14h'), - (0xC8F, 'hpmcounter15h'), - (0xC90, 'hpmcounter16h'), - (0xC91, 'hpmcounter17h'), - (0xC92, 'hpmcounter18h'), - (0xC93, 'hpmcounter19h'), - (0xC94, 'hpmcounter20h'), - (0xC95, 'hpmcounter21h'), - (0xC96, 'hpmcounter22h'), - (0xC97, 'hpmcounter23h'), - (0xC98, 'hpmcounter24h'), - (0xC99, 'hpmcounter25h'), - (0xC9A, 'hpmcounter26h'), - (0xC9B, 'hpmcounter27h'), - (0xC9C, 'hpmcounter28h'), - (0xC9D, 'hpmcounter29h'), - (0xC9E, 'hpmcounter30h'), - (0xC9F, 'hpmcounter31h'), - - # Standard Machine RW - (0x310, 'mstatush'), - (0x31A, 'menvcfgh'), - (0x757, 'mseccfgh'), - (0xB80, 'mcycleh'), - (0xB82, 'minstreth'), - (0xB83, 'mhpmcounter3h'), - (0xB84, 'mhpmcounter4h'), - (0xB85, 'mhpmcounter5h'), - (0xB86, 'mhpmcounter6h'), - (0xB87, 'mhpmcounter7h'), - (0xB88, 'mhpmcounter8h'), - (0xB89, 'mhpmcounter9h'), - (0xB8A, 'mhpmcounter10h'), - (0xB8B, 'mhpmcounter11h'), - (0xB8C, 'mhpmcounter12h'), - (0xB8D, 'mhpmcounter13h'), - (0xB8E, 'mhpmcounter14h'), - (0xB8F, 'mhpmcounter15h'), - (0xB90, 'mhpmcounter16h'), - (0xB91, 'mhpmcounter17h'), - (0xB92, 'mhpmcounter18h'), - (0xB93, 'mhpmcounter19h'), - (0xB94, 'mhpmcounter20h'), - (0xB95, 'mhpmcounter21h'), - (0xB96, 'mhpmcounter22h'), - (0xB97, 'mhpmcounter23h'), - (0xB98, 'mhpmcounter24h'), - (0xB99, 'mhpmcounter25h'), - (0xB9A, 'mhpmcounter26h'), - (0xB9B, 'mhpmcounter27h'), - (0xB9C, 'mhpmcounter28h'), - (0xB9D, 'mhpmcounter29h'), - (0xB9E, 'mhpmcounter30h'), - (0xB9F, 'mhpmcounter31h'), -] - -# look up table of position of various arguments that are used by the -# instructions in the encoding files. -arg_lut = {} -arg_lut['rd'] = (11, 7) -arg_lut['rt'] = (19, 15) # source+dest register address. Overlaps rs1. -arg_lut['rs1'] = (19, 15) -arg_lut['rs2'] = (24, 20) -arg_lut['rs3'] = (31, 27) -arg_lut['aqrl'] = (26, 25) -arg_lut['aq'] = (26, 26) -arg_lut['rl'] = (25, 25) -arg_lut['fm'] = (31, 28) -arg_lut['pred'] = (27, 24) -arg_lut['succ'] = (23, 20) -arg_lut['rm'] = (14, 12) -arg_lut['funct3'] = (14, 12) -arg_lut['funct2'] = (26, 25) -arg_lut['imm20'] = (31, 12) -arg_lut['jimm20'] = (31, 12) -arg_lut['imm12'] = (31, 20) -arg_lut['imm12hi'] = (31, 25) -arg_lut['bimm12hi'] = (31, 25) -arg_lut['imm12lo'] = (11, 7) -arg_lut['bimm12lo'] = (11, 7) -arg_lut['zimm'] = (19, 15) -arg_lut['shamt'] = (25, 20) -arg_lut['shamtw'] = (24, 20) -arg_lut['shamtw4'] = (23, 20) -arg_lut['bs'] = (31, 30) # byte select for RV32K AES -arg_lut['rnum'] = (23, 20) # round constant for RV64 AES -arg_lut['rc'] = (29, 25) -arg_lut['imm2'] = (21, 20) -arg_lut['imm3'] = (22, 20) -arg_lut['imm4'] = (23, 20) -arg_lut['imm5'] = (24, 20) -arg_lut['imm6'] = (25, 20) -arg_lut['zimm'] = (19, 15) -arg_lut['opcode'] = (6,0) -arg_lut['funct7'] = (31,25) - -# for vectors -arg_lut['vd'] = (11, 7) -arg_lut['vs3'] = (11, 7) -arg_lut['vs1'] = (19, 15) -arg_lut['vs2'] = (24, 20) -arg_lut['vm'] = (25, 25) -arg_lut['wd'] = (26, 26) -arg_lut['amoop'] = (31, 27) -arg_lut['nf'] = (31, 29) -arg_lut['simm5'] = (19, 15) -arg_lut['zimm10'] = (29, 20) -arg_lut['zimm11'] = (30, 20) - - -#compressed immediates and fields -arg_lut['c_nzuimm10'] = (12,5) -arg_lut['c_uimm7lo'] = (6,5) -arg_lut['c_uimm7hi'] = (12,10) -arg_lut['c_uimm8lo'] = (6,5) -arg_lut['c_uimm8hi'] = (12,10) -arg_lut['c_uimm9lo'] = (6,5) -arg_lut['c_uimm9hi'] = (12,10) -arg_lut['c_nzimm6lo'] = (6,2) -arg_lut['c_nzimm6hi'] = (12,12) -arg_lut['c_imm6lo'] = (6,2) -arg_lut['c_imm6hi'] = (12,12) -arg_lut['c_nzimm10hi'] = (12,12) -arg_lut['c_nzimm10lo'] = (6,2) -arg_lut['c_nzimm18hi'] = (12,12) -arg_lut['c_nzimm18lo'] = (6,2) -arg_lut['c_imm12'] = (12,2) -arg_lut['c_bimm9lo'] = (6,2) -arg_lut['c_bimm9hi'] = (12,10) -arg_lut['c_nzuimm5'] = (6,2) -arg_lut['c_nzuimm6lo'] = (6,2) -arg_lut['c_nzuimm6hi'] = (12, 12) -arg_lut['c_uimm8splo'] = (6,2) -arg_lut['c_uimm8sphi'] = (12, 12) -arg_lut['c_uimm8sp_s'] = (12,7) -arg_lut['c_uimm10splo'] = (6,2) -arg_lut['c_uimm10sphi'] = (12, 12) -arg_lut['c_uimm9splo'] = (6,2) -arg_lut['c_uimm9sphi'] = (12, 12) -arg_lut['c_uimm10sp_s'] = (12,7) -arg_lut['c_uimm9sp_s'] = (12,7) - -arg_lut['rs1_p'] = (9,7) -arg_lut['rs2_p'] = (4,2) -arg_lut['rd_p'] = (4,2) -arg_lut['rd_rs1_n0'] = (11,7) -arg_lut['rd_rs1_p'] = (9,7) -arg_lut['rd_rs1'] = (11,7) -arg_lut['rd_n2'] = (11,7) -arg_lut['rd_n0'] = (11,7) -arg_lut['rs1_n0'] = (11,7) -arg_lut['c_rs2_n0'] = (6,2) -arg_lut['c_rs1_n0'] = (11,7) -arg_lut['c_rs2'] = (6,2) - -# dictionary containing the mapping of the argument to the what the fields in -# the latex table should be -latex_mapping = {} -latex_mapping['imm12'] = 'imm[11:0]' -latex_mapping['rs1'] = 'rs1' -latex_mapping['rs2'] = 'rs2' -latex_mapping['rd'] = 'rd' -latex_mapping['imm20'] = 'imm[31:12]' -latex_mapping['bimm12hi'] = 'imm[12$\\vert$10:5]' -latex_mapping['bimm12lo'] = 'imm[4:1$\\vert$11]' -latex_mapping['imm12hi'] = 'imm[11:5]' -latex_mapping['imm12lo'] = 'imm[4:0]' -latex_mapping['jimm20'] = 'imm[20$\\vert$10:1$\\vert$11$\\vert$19:12]' -latex_mapping['zimm'] = 'uimm' -latex_mapping['shamtw'] = 'shamt' -latex_mapping['rd_p'] = "rd\\,$'$" -latex_mapping['rs1_p'] = "rs1\\,$'$" -latex_mapping['rs2_p'] = "rs2\\,$'$" -latex_mapping['rd_rs1_n0'] = 'rd/rs$\\neq$0' -latex_mapping['rd_rs1_p'] = "rs1\\,$'$/rs2\\,$'$" -latex_mapping['c_rs2'] = 'rs2' -latex_mapping['c_rs2_n0'] = 'rs2$\\neq$0' -latex_mapping['rd_n0'] = 'rd$\\neq$0' -latex_mapping['rs1_n0'] = 'rs1$\\neq$0' -latex_mapping['c_rs1_n0'] = 'rs1$\\neq$0' -latex_mapping['rd_rs1'] = 'rd/rs1' -latex_mapping['c_nzuimm10'] = "nzuimm[5:4$\\vert$9:6$\\vert$2$\\vert$3]" -latex_mapping['c_uimm7lo'] = 'uimm[2$\\vert$6]' -latex_mapping['c_uimm7hi'] = 'uimm[5:3]' -latex_mapping['c_uimm8lo'] = 'uimm[7:6]' -latex_mapping['c_uimm8hi'] = 'uimm[5:3]' -latex_mapping['c_uimm9lo'] = 'uimm[7:6]' -latex_mapping['c_uimm9hi'] = 'uimm[5:4$\\vert$8]' -latex_mapping['c_nzimm6lo'] = 'nzimm[4:0]' -latex_mapping['c_nzimm6hi'] = 'nzimm[5]' -latex_mapping['c_imm6lo'] = 'imm[4:0]' -latex_mapping['c_imm6hi'] = 'imm[5]' -latex_mapping['c_nzimm10hi'] = 'nzimm[9]' -latex_mapping['c_nzimm10lo'] = 'nzimm[4$\\vert$6$\\vert$8:7$\\vert$5]' -latex_mapping['c_nzimm18hi'] = 'nzimm[17]' -latex_mapping['c_nzimm18lo'] = 'nzimm[16:12]' -latex_mapping['c_imm12'] = 'imm[11$\\vert$4$\\vert$9:8$\\vert$10$\\vert$6$\\vert$7$\\vert$3:1$\\vert$5]' -latex_mapping['c_bimm9lo'] = 'imm[7:6$\\vert$2:1$\\vert$5]' -latex_mapping['c_bimm9hi'] = 'imm[8$\\vert$4:3]' -latex_mapping['c_nzuimm5'] = 'nzuimm[4:0]' -latex_mapping['c_nzuimm6lo'] = 'nzuimm[4:0]' -latex_mapping['c_nzuimm6hi'] = 'nzuimm[5]' -latex_mapping['c_uimm8splo'] = 'uimm[4:2$\\vert$7:6]' -latex_mapping['c_uimm8sphi'] = 'uimm[5]' -latex_mapping['c_uimm8sp_s'] = 'uimm[5:2$\\vert$7:6]' -latex_mapping['c_uimm10splo'] = 'uimm[4$\\vert$9:6]' -latex_mapping['c_uimm10sphi'] = 'uimm[5]' -latex_mapping['c_uimm9splo'] = 'uimm[4:3$\\vert$8:6]' -latex_mapping['c_uimm9sphi'] = 'uimm[5]' -latex_mapping['c_uimm10sp_s'] = 'uimm[5:4$\\vert$9:6]' -latex_mapping['c_uimm9sp_s'] = 'uimm[5:3$\\vert$8:6]' - -# created a dummy instruction-dictionary like dictionary for all the instruction -# types so that the same logic can be used to create their tables -latex_inst_type = {} -latex_inst_type['R-type'] = {} -latex_inst_type['R-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ - 'rs1', 'rs2', 'funct7'] -latex_inst_type['I-type'] = {} -latex_inst_type['I-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ - 'rs1', 'imm12'] -latex_inst_type['S-type'] = {} -latex_inst_type['S-type']['variable_fields'] = ['opcode', 'imm12lo', 'funct3', \ - 'rs1', 'rs2', 'imm12hi'] -latex_inst_type['B-type'] = {} -latex_inst_type['B-type']['variable_fields'] = ['opcode', 'bimm12lo', 'funct3', \ - 'rs1', 'rs2', 'bimm12hi'] -latex_inst_type['U-type'] = {} -latex_inst_type['U-type']['variable_fields'] = ['opcode', 'rd', 'imm20'] -latex_inst_type['J-type'] = {} -latex_inst_type['J-type']['variable_fields'] = ['opcode', 'rd', 'jimm20'] -latex_inst_type['R4-type'] = {} -latex_inst_type['R4-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ - 'rs1', 'rs2', 'funct2', 'rs3'] diff --git a/riscv_isac/plugins/riscv_opcodes/encoding.h b/riscv_isac/plugins/riscv_opcodes/encoding.h deleted file mode 100644 index 66358b7..0000000 --- a/riscv_isac/plugins/riscv_opcodes/encoding.h +++ /dev/null @@ -1,306 +0,0 @@ -/* See LICENSE for license details. */ - -#ifndef RISCV_CSR_ENCODING_H -#define RISCV_CSR_ENCODING_H - -#define MSTATUS_UIE 0x00000001 -#define MSTATUS_SIE 0x00000002 -#define MSTATUS_HIE 0x00000004 -#define MSTATUS_MIE 0x00000008 -#define MSTATUS_UPIE 0x00000010 -#define MSTATUS_SPIE 0x00000020 -#define MSTATUS_UBE 0x00000040 -#define MSTATUS_MPIE 0x00000080 -#define MSTATUS_SPP 0x00000100 -#define MSTATUS_VS 0x00000600 -#define MSTATUS_MPP 0x00001800 -#define MSTATUS_FS 0x00006000 -#define MSTATUS_XS 0x00018000 -#define MSTATUS_MPRV 0x00020000 -#define MSTATUS_SUM 0x00040000 -#define MSTATUS_MXR 0x00080000 -#define MSTATUS_TVM 0x00100000 -#define MSTATUS_TW 0x00200000 -#define MSTATUS_TSR 0x00400000 -#define MSTATUS32_SD 0x80000000 -#define MSTATUS_UXL 0x0000000300000000 -#define MSTATUS_SXL 0x0000000C00000000 -#define MSTATUS_SBE 0x0000001000000000 -#define MSTATUS_MBE 0x0000002000000000 -#define MSTATUS_GVA 0x0000004000000000 -#define MSTATUS_MPV 0x0000008000000000 -#define MSTATUS64_SD 0x8000000000000000 - -#define MSTATUSH_SBE 0x00000010 -#define MSTATUSH_MBE 0x00000020 -#define MSTATUSH_GVA 0x00000040 -#define MSTATUSH_MPV 0x00000080 - -#define SSTATUS_UIE 0x00000001 -#define SSTATUS_SIE 0x00000002 -#define SSTATUS_UPIE 0x00000010 -#define SSTATUS_SPIE 0x00000020 -#define SSTATUS_UBE 0x00000040 -#define SSTATUS_SPP 0x00000100 -#define SSTATUS_VS 0x00000600 -#define SSTATUS_FS 0x00006000 -#define SSTATUS_XS 0x00018000 -#define SSTATUS_SUM 0x00040000 -#define SSTATUS_MXR 0x00080000 -#define SSTATUS32_SD 0x80000000 -#define SSTATUS_UXL 0x0000000300000000 -#define SSTATUS64_SD 0x8000000000000000 - -#define HSTATUS_VSXL 0x300000000 -#define HSTATUS_VTSR 0x00400000 -#define HSTATUS_VTW 0x00200000 -#define HSTATUS_VTVM 0x00100000 -#define HSTATUS_VGEIN 0x0003f000 -#define HSTATUS_HU 0x00000200 -#define HSTATUS_SPVP 0x00000100 -#define HSTATUS_SPV 0x00000080 -#define HSTATUS_GVA 0x00000040 -#define HSTATUS_VSBE 0x00000020 - -#define USTATUS_UIE 0x00000001 -#define USTATUS_UPIE 0x00000010 - -#define DCSR_XDEBUGVER (3U<<30) -#define DCSR_NDRESET (1<<29) -#define DCSR_FULLRESET (1<<28) -#define DCSR_EBREAKM (1<<15) -#define DCSR_EBREAKH (1<<14) -#define DCSR_EBREAKS (1<<13) -#define DCSR_EBREAKU (1<<12) -#define DCSR_STOPCYCLE (1<<10) -#define DCSR_STOPTIME (1<<9) -#define DCSR_CAUSE (7<<6) -#define DCSR_DEBUGINT (1<<5) -#define DCSR_HALT (1<<3) -#define DCSR_STEP (1<<2) -#define DCSR_PRV (3<<0) - -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 -#define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEP 4 -#define DCSR_CAUSE_HALT 5 -#define DCSR_CAUSE_GROUP 6 - -#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) -#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) -#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) - -#define MCONTROL_SELECT (1<<19) -#define MCONTROL_TIMING (1<<18) -#define MCONTROL_ACTION (0x3f<<12) -#define MCONTROL_CHAIN (1<<11) -#define MCONTROL_MATCH (0xf<<7) -#define MCONTROL_M (1<<6) -#define MCONTROL_H (1<<5) -#define MCONTROL_S (1<<4) -#define MCONTROL_U (1<<3) -#define MCONTROL_EXECUTE (1<<2) -#define MCONTROL_STORE (1<<1) -#define MCONTROL_LOAD (1<<0) - -#define MCONTROL_TYPE_NONE 0 -#define MCONTROL_TYPE_MATCH 2 - -#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 -#define MCONTROL_ACTION_DEBUG_MODE 1 -#define MCONTROL_ACTION_TRACE_START 2 -#define MCONTROL_ACTION_TRACE_STOP 3 -#define MCONTROL_ACTION_TRACE_EMIT 4 - -#define MCONTROL_MATCH_EQUAL 0 -#define MCONTROL_MATCH_NAPOT 1 -#define MCONTROL_MATCH_GE 2 -#define MCONTROL_MATCH_LT 3 -#define MCONTROL_MATCH_MASK_LOW 4 -#define MCONTROL_MATCH_MASK_HIGH 5 - -#define MIP_USIP (1 << IRQ_U_SOFT) -#define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_VSSIP (1 << IRQ_VS_SOFT) -#define MIP_MSIP (1 << IRQ_M_SOFT) -#define MIP_UTIP (1 << IRQ_U_TIMER) -#define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_VSTIP (1 << IRQ_VS_TIMER) -#define MIP_MTIP (1 << IRQ_M_TIMER) -#define MIP_UEIP (1 << IRQ_U_EXT) -#define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_VSEIP (1 << IRQ_VS_EXT) -#define MIP_MEIP (1 << IRQ_M_EXT) -#define MIP_SGEIP (1 << IRQ_S_GEXT) - -#define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP) -#define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) -#define MIP_HS_MASK (MIP_VS_MASK | MIP_SGEIP) - -#define MIDELEG_FORCED_MASK MIP_HS_MASK - -#define SIP_SSIP MIP_SSIP -#define SIP_STIP MIP_STIP - -#define MENVCFG_FIOM 0x00000001 -#define MENVCFG_CBIE 0x00000030 -#define MENVCFG_CBCFE 0x00000040 -#define MENVCFG_CBZE 0x00000080 -#define MENVCFG_PBMTE 0x4000000000000000 -#define MENVCFG_STCE 0x8000000000000000 - -#define MENVCFGH_PBMTE 0x40000000 -#define MENVCFGH_STCE 0x80000000 - -#define HENVCFG_FIOM 0x00000001 -#define HENVCFG_CBIE 0x00000030 -#define HENVCFG_CBCFE 0x00000040 -#define HENVCFG_CBZE 0x00000080 -#define HENVCFG_PBMTE 0x4000000000000000 -#define HENVCFG_STCE 0x8000000000000000 - -#define HENVCFGH_PBMTE 0x40000000 -#define HENVCFGH_STCE 0x80000000 - -#define SENVCFG_FIOM 0x00000001 -#define SENVCFG_CBIE 0x00000030 -#define SENVCFG_CBCFE 0x00000040 -#define SENVCFG_CBZE 0x00000080 - -#define MSECCFG_MML 0x00000001 -#define MSECCFG_MMWP 0x00000002 -#define MSECCFG_RLB 0x00000004 -#define MSECCFG_USEED 0x00000100 -#define MSECCFG_SSEED 0x00000200 - -#define PRV_U 0 -#define PRV_S 1 -#define PRV_M 3 - -#define PRV_HS (PRV_S + 1) - -#define SATP32_MODE 0x80000000 -#define SATP32_ASID 0x7FC00000 -#define SATP32_PPN 0x003FFFFF -#define SATP64_MODE 0xF000000000000000 -#define SATP64_ASID 0x0FFFF00000000000 -#define SATP64_PPN 0x00000FFFFFFFFFFF - -#define SATP_MODE_OFF 0 -#define SATP_MODE_SV32 1 -#define SATP_MODE_SV39 8 -#define SATP_MODE_SV48 9 -#define SATP_MODE_SV57 10 -#define SATP_MODE_SV64 11 - -#define HGATP32_MODE 0x80000000 -#define HGATP32_VMID 0x1FC00000 -#define HGATP32_PPN 0x003FFFFF - -#define HGATP64_MODE 0xF000000000000000 -#define HGATP64_VMID 0x03FFF00000000000 -#define HGATP64_PPN 0x00000FFFFFFFFFFF - -#define HGATP_MODE_OFF 0 -#define HGATP_MODE_SV32X4 1 -#define HGATP_MODE_SV39X4 8 -#define HGATP_MODE_SV48X4 9 - -#define PMP_R 0x01 -#define PMP_W 0x02 -#define PMP_X 0x04 -#define PMP_A 0x18 -#define PMP_L 0x80 -#define PMP_SHIFT 2 - -#define PMP_TOR 0x08 -#define PMP_NA4 0x10 -#define PMP_NAPOT 0x18 - -#define IRQ_U_SOFT 0 -#define IRQ_S_SOFT 1 -#define IRQ_VS_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_U_TIMER 4 -#define IRQ_S_TIMER 5 -#define IRQ_VS_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_U_EXT 8 -#define IRQ_S_EXT 9 -#define IRQ_VS_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_S_GEXT 12 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -/* page table entry (PTE) fields */ -#define PTE_V 0x001 /* Valid */ -#define PTE_R 0x002 /* Read */ -#define PTE_W 0x004 /* Write */ -#define PTE_X 0x008 /* Execute */ -#define PTE_U 0x010 /* User */ -#define PTE_G 0x020 /* Global */ -#define PTE_A 0x040 /* Accessed */ -#define PTE_D 0x080 /* Dirty */ -#define PTE_SOFT 0x300 /* Reserved for Software */ -#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ -#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ -#define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ -#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ - -#define PTE_PPN_SHIFT 10 - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) - -#ifdef __riscv - -#if __riscv_xlen == 64 -# define MSTATUS_SD MSTATUS64_SD -# define SSTATUS_SD SSTATUS64_SD -# define RISCV_PGLEVEL_BITS 9 -# define SATP_MODE SATP64_MODE -#else -# define MSTATUS_SD MSTATUS32_SD -# define SSTATUS_SD SSTATUS32_SD -# define RISCV_PGLEVEL_BITS 10 -# define SATP_MODE SATP32_MODE -#endif -#define RISCV_PGSHIFT 12 -#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) - -#ifndef __ASSEMBLER__ - -#ifdef __GNUC__ - -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_csr(reg, val) ({ \ - asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) - -#define swap_csr(reg, val) ({ unsigned long __tmp; \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ - __tmp; }) - -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) - -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) - -#define rdtime() read_csr(time) -#define rdcycle() read_csr(cycle) -#define rdinstret() read_csr(instret) - -#endif - -#endif - -#endif - -#endif diff --git a/riscv_isac/plugins/riscv_opcodes/instrs.txt b/riscv_isac/plugins/riscv_opcodes/instrs.txt deleted file mode 100644 index 88e0001..0000000 --- a/riscv_isac/plugins/riscv_opcodes/instrs.txt +++ /dev/null @@ -1,1221 +0,0 @@ -lwu : {'encoding': '-----------------110-----0000011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv64_i'], 'match': '0x6003', 'mask': '0x707f'} -ld : {'encoding': '-----------------011-----0000011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv64_i'], 'match': '0x3003', 'mask': '0x707f'} -sd : {'encoding': '-----------------011-----0100011', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv64_i'], 'match': '0x3023', 'mask': '0x707f'} -slli : {'encoding': '000000-----------001-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_i'], 'match': '0x1013', 'mask': '0xfc00707f'} -srli : {'encoding': '000000-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_i'], 'match': '0x5013', 'mask': '0xfc00707f'} -srai : {'encoding': '010000-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_i'], 'match': '0x40005013', 'mask': '0xfc00707f'} -addiw : {'encoding': '-----------------000-----0011011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv64_i'], 'match': '0x1b', 'mask': '0x707f'} -slliw : {'encoding': '0000000----------001-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_i'], 'match': '0x101b', 'mask': '0xfe00707f'} -srliw : {'encoding': '0000000----------101-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_i'], 'match': '0x501b', 'mask': '0xfe00707f'} -sraiw : {'encoding': '0100000----------101-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_i'], 'match': '0x4000501b', 'mask': '0xfe00707f'} -addw : {'encoding': '0000000----------000-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_i'], 'match': '0x3b', 'mask': '0xfe00707f'} -subw : {'encoding': '0100000----------000-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_i'], 'match': '0x4000003b', 'mask': '0xfe00707f'} -sllw : {'encoding': '0000000----------001-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_i'], 'match': '0x103b', 'mask': '0xfe00707f'} -srlw : {'encoding': '0000000----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_i'], 'match': '0x503b', 'mask': '0xfe00707f'} -sraw : {'encoding': '0100000----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_i'], 'match': '0x4000503b', 'mask': '0xfe00707f'} -bclri : {'encoding': '010010-----------001-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zbs'], 'match': '0x48001013', 'mask': '0xfc00707f'} -bexti : {'encoding': '010010-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zbs'], 'match': '0x48005013', 'mask': '0xfc00707f'} -binvi : {'encoding': '011010-----------001-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zbs'], 'match': '0x68001013', 'mask': '0xfc00707f'} -bseti : {'encoding': '001010-----------001-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zbs'], 'match': '0x28001013', 'mask': '0xfc00707f'} -sha512sum0r : {'encoding': '0101000----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv32_zknh'], 'match': '0x50000033', 'mask': '0xfe00707f'} -sha512sum1r : {'encoding': '0101001----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv32_zknh'], 'match': '0x52000033', 'mask': '0xfe00707f'} -sha512sig0l : {'encoding': '0101010----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv32_zknh'], 'match': '0x54000033', 'mask': '0xfe00707f'} -sha512sig0h : {'encoding': '0101110----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv32_zknh'], 'match': '0x5c000033', 'mask': '0xfe00707f'} -sha512sig1l : {'encoding': '0101011----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv32_zknh'], 'match': '0x56000033', 'mask': '0xfe00707f'} -sha512sig1h : {'encoding': '0101111----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv32_zknh'], 'match': '0x5e000033', 'mask': '0xfe00707f'} -cmix : {'encoding': '-----11----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3'], 'extension': ['rv_zbt'], 'match': '0x6001033', 'mask': '0x600707f'} -cmov : {'encoding': '-----11----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3'], 'extension': ['rv_zbt'], 'match': '0x6005033', 'mask': '0x600707f'} -fsl : {'encoding': '-----10----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3'], 'extension': ['rv_zbt'], 'match': '0x4001033', 'mask': '0x600707f'} -fsr : {'encoding': '-----10----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3'], 'extension': ['rv_zbt'], 'match': '0x4005033', 'mask': '0x600707f'} -aes32esmi : {'encoding': '--10011----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'bs'], 'extension': ['rv32_zkne'], 'match': '0x26000033', 'mask': '0x3e00707f'} -aes32esi : {'encoding': '--10001----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'bs'], 'extension': ['rv32_zkne'], 'match': '0x22000033', 'mask': '0x3e00707f'} -c_addi4spn : {'encoding': '----------------000-----------00', 'variable_fields': ['rd_p', 'c_nzuimm10'], 'extension': ['rv_c'], 'match': '0x0', 'mask': '0xe003'} -c_lw : {'encoding': '----------------010-----------00', 'variable_fields': ['rd_p', 'rs1_p', 'c_uimm7lo', 'c_uimm7hi'], 'extension': ['rv_c'], 'match': '0x4000', 'mask': '0xe003'} -c_sw : {'encoding': '----------------110-----------00', 'variable_fields': ['rs1_p', 'rs2_p', 'c_uimm7lo', 'c_uimm7hi'], 'extension': ['rv_c'], 'match': '0xc000', 'mask': '0xe003'} -c_nop : {'encoding': '----------------000-00000-----01', 'variable_fields': ['c_nzimm6hi', 'c_nzimm6lo'], 'extension': ['rv_c'], 'match': '0x1', 'mask': '0xef83'} -c_addi : {'encoding': '----------------000-----------01', 'variable_fields': ['rd_rs1_n0', 'c_nzimm6lo', 'c_nzimm6hi'], 'extension': ['rv_c'], 'match': '0x1', 'mask': '0xe003'} -c_li : {'encoding': '----------------010-----------01', 'variable_fields': ['rd', 'c_imm6lo', 'c_imm6hi'], 'extension': ['rv_c'], 'match': '0x4001', 'mask': '0xe003'} -c_addi16sp : {'encoding': '----------------011-00010-----01', 'variable_fields': ['c_nzimm10hi', 'c_nzimm10lo'], 'extension': ['rv_c'], 'match': '0x6101', 'mask': '0xef83'} -c_lui : {'encoding': '----------------011-----------01', 'variable_fields': ['rd_n2', 'c_nzimm18hi', 'c_nzimm18lo'], 'extension': ['rv_c'], 'match': '0x6001', 'mask': '0xe003'} -c_andi : {'encoding': '----------------100-10--------01', 'variable_fields': ['rd_rs1_p', 'c_imm6hi', 'c_imm6lo'], 'extension': ['rv_c'], 'match': '0x8801', 'mask': '0xec03'} -c_sub : {'encoding': '----------------100011---00---01', 'variable_fields': ['rd_rs1_p', 'rs2_p'], 'extension': ['rv_c'], 'match': '0x8c01', 'mask': '0xfc63'} -c_xor : {'encoding': '----------------100011---01---01', 'variable_fields': ['rd_rs1_p', 'rs2_p'], 'extension': ['rv_c'], 'match': '0x8c21', 'mask': '0xfc63'} -c_or : {'encoding': '----------------100011---10---01', 'variable_fields': ['rd_rs1_p', 'rs2_p'], 'extension': ['rv_c'], 'match': '0x8c41', 'mask': '0xfc63'} -c_and : {'encoding': '----------------100011---11---01', 'variable_fields': ['rd_rs1_p', 'rs2_p'], 'extension': ['rv_c'], 'match': '0x8c61', 'mask': '0xfc63'} -c_j : {'encoding': '----------------101-----------01', 'variable_fields': ['c_imm12'], 'extension': ['rv_c'], 'match': '0xa001', 'mask': '0xe003'} -c_beqz : {'encoding': '----------------110-----------01', 'variable_fields': ['rs1_p', 'c_bimm9lo', 'c_bimm9hi'], 'extension': ['rv_c'], 'match': '0xc001', 'mask': '0xe003'} -c_bnez : {'encoding': '----------------111-----------01', 'variable_fields': ['rs1_p', 'c_bimm9lo', 'c_bimm9hi'], 'extension': ['rv_c'], 'match': '0xe001', 'mask': '0xe003'} -c_lwsp : {'encoding': '----------------010-----------10', 'variable_fields': ['rd_n0', 'c_uimm8sphi', 'c_uimm8splo'], 'extension': ['rv_c'], 'match': '0x4002', 'mask': '0xe003'} -c_jr : {'encoding': '----------------1000-----0000010', 'variable_fields': ['rs1_n0'], 'extension': ['rv_c'], 'match': '0x8002', 'mask': '0xf07f'} -c_mv : {'encoding': '----------------1000----------10', 'variable_fields': ['rd', 'c_rs2_n0'], 'extension': ['rv_c'], 'match': '0x8002', 'mask': '0xf003'} -c_ebreak : {'encoding': '----------------1001000000000010', 'variable_fields': [], 'extension': ['rv_c'], 'match': '0x9002', 'mask': '0xffff'} -c_jalr : {'encoding': '----------------1001-----0000010', 'variable_fields': ['c_rs1_n0'], 'extension': ['rv_c'], 'match': '0x9002', 'mask': '0xf07f'} -c_add : {'encoding': '----------------1001----------10', 'variable_fields': ['rd_rs1', 'c_rs2_n0'], 'extension': ['rv_c'], 'match': '0x9002', 'mask': '0xf003'} -c_swsp : {'encoding': '----------------110-----------10', 'variable_fields': ['c_rs2', 'c_uimm8sp_s'], 'extension': ['rv_c'], 'match': '0xc002', 'mask': '0xe003'} -fcvt_q_h : {'encoding': '010001100010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q_zfh'], 'match': '0x46200053', 'mask': '0xfff0007f'} -fcvt_h_q : {'encoding': '010001000011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q_zfh'], 'match': '0x44300053', 'mask': '0xfff0007f'} -sha256sum0 : {'encoding': '000100000000-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zknh'], 'match': '0x10001013', 'mask': '0xfff0707f'} -sha256sum1 : {'encoding': '000100000001-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zknh'], 'match': '0x10101013', 'mask': '0xfff0707f'} -sha256sig0 : {'encoding': '000100000010-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zknh'], 'match': '0x10201013', 'mask': '0xfff0707f'} -sha256sig1 : {'encoding': '000100000011-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zknh'], 'match': '0x10301013', 'mask': '0xfff0707f'} -bfp : {'encoding': '0100100----------111-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbf'], 'match': '0x48007033', 'mask': '0xfe00707f'} -c_flw : {'encoding': '----------------011-----------00', 'variable_fields': ['rd_p', 'rs1_p', 'c_uimm7lo', 'c_uimm7hi'], 'extension': ['rv32_c_f'], 'match': '0x6000', 'mask': '0xe003'} -c_fsw : {'encoding': '----------------111-----------00', 'variable_fields': ['rs1_p', 'rs2_p', 'c_uimm7lo', 'c_uimm7hi'], 'extension': ['rv32_c_f'], 'match': '0xe000', 'mask': '0xe003'} -c_flwsp : {'encoding': '----------------011-----------10', 'variable_fields': ['rd', 'c_uimm8sphi', 'c_uimm8splo'], 'extension': ['rv32_c_f'], 'match': '0x6002', 'mask': '0xe003'} -c_fswsp : {'encoding': '----------------111-----------10', 'variable_fields': ['c_rs2', 'c_uimm8sp_s'], 'extension': ['rv32_c_f'], 'match': '0xe002', 'mask': '0xe003'} -fcvt_l_s : {'encoding': '110000000010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_f'], 'match': '0xc0200053', 'mask': '0xfff0007f'} -fcvt_lu_s : {'encoding': '110000000011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_f'], 'match': '0xc0300053', 'mask': '0xfff0007f'} -fcvt_s_l : {'encoding': '110100000010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_f'], 'match': '0xd0200053', 'mask': '0xfff0007f'} -fcvt_s_lu : {'encoding': '110100000011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_f'], 'match': '0xd0300053', 'mask': '0xfff0007f'} -add8 : {'encoding': '0100100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x48000077', 'mask': '0xfe00707f'} -add16 : {'encoding': '0100000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x40000077', 'mask': '0xfe00707f'} -ave : {'encoding': '1110000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xe0000077', 'mask': '0xfe00707f'} -bitrev : {'encoding': '1110011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xe6000077', 'mask': '0xfe00707f'} -bitrevi : {'encoding': '111010-----------000-----1110111', 'variable_fields': ['imm6', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xe8000077', 'mask': '0xfc00707f'} -bpick : {'encoding': '-----00----------011-----1110111', 'variable_fields': ['rs3', 'rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x3077', 'mask': '0x600707f'} -clrs8 : {'encoding': '101011100000-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xae000077', 'mask': '0xfff0707f'} -clrs16 : {'encoding': '101011101000-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xae800077', 'mask': '0xfff0707f'} -clrs32 : {'encoding': '101011111000-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xaf800077', 'mask': '0xfff0707f'} -clo8 : {'encoding': '101011100011-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xae300077', 'mask': '0xfff0707f'} -clo16 : {'encoding': '101011101011-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xaeb00077', 'mask': '0xfff0707f'} -clo32 : {'encoding': '101011111011-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xafb00077', 'mask': '0xfff0707f'} -clz8 : {'encoding': '101011100001-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xae100077', 'mask': '0xfff0707f'} -clz16 : {'encoding': '101011101001-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xae900077', 'mask': '0xfff0707f'} -clz32 : {'encoding': '101011111001-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xaf900077', 'mask': '0xfff0707f'} -cmpeq8 : {'encoding': '0100111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x4e000077', 'mask': '0xfe00707f'} -cmpeq16 : {'encoding': '0100110----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x4c000077', 'mask': '0xfe00707f'} -cras16 : {'encoding': '0100010----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x44000077', 'mask': '0xfe00707f'} -crsa16 : {'encoding': '0100011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x46000077', 'mask': '0xfe00707f'} -insb : {'encoding': '101011000--------000-----1110111', 'variable_fields': ['imm3', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xac000077', 'mask': '0xff80707f'} -kabs8 : {'encoding': '101011010000-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xad000077', 'mask': '0xfff0707f'} -kabs16 : {'encoding': '101011010001-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xad100077', 'mask': '0xfff0707f'} -kabsw : {'encoding': '101011010100-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xad400077', 'mask': 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'mask': '0xfe00707f'} -kdmatt : {'encoding': '1111001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xf2001077', 'mask': '0xfe00707f'} -khm8 : {'encoding': '1000111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x8e000077', 'mask': '0xfe00707f'} -khmx8 : {'encoding': '1001111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x9e000077', 'mask': '0xfe00707f'} -khm16 : {'encoding': '1000011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x86000077', 'mask': '0xfe00707f'} -khmx16 : {'encoding': '1001011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x96000077', 'mask': '0xfe00707f'} -khmbb : {'encoding': '0000110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': 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'match': '0x38001077', 'mask': '0xfe00707f'} -kmxda : {'encoding': '0011101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x3a001077', 'mask': '0xfe00707f'} -kmmac : {'encoding': '0110000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x60001077', 'mask': '0xfe00707f'} -kmmac_u : {'encoding': '0111000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x70001077', 'mask': '0xfe00707f'} -kmmawb : {'encoding': '0100011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x46001077', 'mask': '0xfe00707f'} -kmmawb_u : {'encoding': '0101011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x56001077', 'mask': '0xfe00707f'} -kmmawb2 : {'encoding': '1100111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': 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'rd'], 'extension': ['rv_p'], 'match': '0x42001077', 'mask': '0xfe00707f'} -kmmsb_u : {'encoding': '0101001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x52001077', 'mask': '0xfe00707f'} -kmmwb2 : {'encoding': '1000111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x8e001077', 'mask': '0xfe00707f'} -kmmwb2_u : {'encoding': '1001111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x9e001077', 'mask': '0xfe00707f'} -kmmwt2 : {'encoding': '1010111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xae001077', 'mask': '0xfe00707f'} -kmmwt2_u : {'encoding': '1011111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xbe001077', 'mask': '0xfe00707f'} -kmsda : {'encoding': '0100110----------001-----1110111', 'variable_fields': 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'variable_fields': ['imm3', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x7c800077', 'mask': '0xff80707f'} -ksll16 : {'encoding': '0110010----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x64000077', 'mask': '0xfe00707f'} -kslli16 : {'encoding': '01110101---------000-----1110111', 'variable_fields': ['imm4', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x75000077', 'mask': '0xff00707f'} -kslra8 : {'encoding': '0101111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x5e000077', 'mask': '0xfe00707f'} -kslra8_u : {'encoding': '0110111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x6e000077', 'mask': '0xfe00707f'} -kslra16 : {'encoding': '0101011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x56000077', 'mask': '0xfe00707f'} -kslra16_u : {'encoding': '0110011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x66000077', 'mask': '0xfe00707f'} -kslraw : {'encoding': '0110111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x6e001077', 'mask': '0xfe00707f'} -kslraw_u : {'encoding': '0111111----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x7e001077', 'mask': '0xfe00707f'} -kstas16 : {'encoding': '1100010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xc4002077', 'mask': '0xfe00707f'} -kstsa16 : {'encoding': '1100011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xc6002077', 'mask': '0xfe00707f'} -ksub8 : {'encoding': '0001101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x1a000077', 'mask': '0xfe00707f'} -ksub16 : {'encoding': '0001001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x12000077', 'mask': '0xfe00707f'} -ksub64 : {'encoding': '1001001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x92001077', 'mask': '0xfe00707f'} -ksubh : {'encoding': '0000011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x6001077', 'mask': '0xfe00707f'} -ksubw : {'encoding': '0000001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x2001077', 'mask': '0xfe00707f'} -kwmmul : {'encoding': '0110001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x62001077', 'mask': '0xfe00707f'} -kwmmul_u : {'encoding': '0111001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x72001077', 'mask': '0xfe00707f'} -maddr32 : {'encoding': '1100010----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xc4001077', 'mask': '0xfe00707f'} -maxw : {'encoding': '1111001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xf2000077', 'mask': '0xfe00707f'} -minw : {'encoding': '1111000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xf0000077', 'mask': '0xfe00707f'} -msubr32 : {'encoding': '1100011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xc6001077', 'mask': '0xfe00707f'} -mulr64 : {'encoding': '1111000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xf0001077', 'mask': '0xfe00707f'} -mulsr64 : {'encoding': '1110000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xe0001077', 'mask': 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'mask': '0xfe00707f'} -sra16_u : {'encoding': '0110000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x60000077', 'mask': '0xfe00707f'} -srai16 : {'encoding': '01110000---------000-----1110111', 'variable_fields': ['imm4', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x70000077', 'mask': '0xff00707f'} -srai16_u : {'encoding': '01110001---------000-----1110111', 'variable_fields': ['imm4', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x71000077', 'mask': '0xff00707f'} -srl8 : {'encoding': '0101101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x5a000077', 'mask': '0xfe00707f'} -srl8_u : {'encoding': '0110101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x6a000077', 'mask': '0xfe00707f'} -srli8 : {'encoding': '011110100--------000-----1110111', 'variable_fields': ['imm3', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': 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'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xb2001077', 'mask': '0xfe00707f'} -uksubh : {'encoding': '0001011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x16001077', 'mask': '0xfe00707f'} -uksubw : {'encoding': '0001001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x12001077', 'mask': '0xfe00707f'} -umar64 : {'encoding': '1010010----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xa4001077', 'mask': '0xfe00707f'} -umaqa : {'encoding': '1100110----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xcc000077', 'mask': '0xfe00707f'} -umax8 : {'encoding': '1001101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x9a000077', 'mask': '0xfe00707f'} -umax16 : {'encoding': '1001001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x92000077', 'mask': '0xfe00707f'} -umin8 : {'encoding': '1001100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x98000077', 'mask': '0xfe00707f'} -umin16 : {'encoding': '1001000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x90000077', 'mask': '0xfe00707f'} -umsr64 : {'encoding': '1010011----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xa6001077', 'mask': '0xfe00707f'} -umul8 : {'encoding': '1011100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xb8000077', 'mask': '0xfe00707f'} -umulx8 : {'encoding': '1011101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xba000077', 'mask': '0xfe00707f'} -umul16 : {'encoding': '1011000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xb0000077', 'mask': '0xfe00707f'} -umulx16 : {'encoding': '1011001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xb2000077', 'mask': '0xfe00707f'} -uradd8 : {'encoding': '0010100----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x28000077', 'mask': '0xfe00707f'} -uradd16 : {'encoding': '0010000----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x20000077', 'mask': '0xfe00707f'} -uradd64 : {'encoding': '1010000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xa0001077', 'mask': '0xfe00707f'} -uraddw : {'encoding': '0011000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x30001077', 'mask': '0xfe00707f'} -urcras16 : {'encoding': '0010010----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x24000077', 'mask': '0xfe00707f'} -urcrsa16 : {'encoding': '0010011----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x26000077', 'mask': '0xfe00707f'} -urstas16 : {'encoding': '1101010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xd4002077', 'mask': '0xfe00707f'} -urstsa16 : {'encoding': '1101011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xd6002077', 'mask': '0xfe00707f'} -ursub8 : {'encoding': '0010101----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x2a000077', 'mask': '0xfe00707f'} -ursub16 : {'encoding': '0010001----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x22000077', 'mask': '0xfe00707f'} -ursub64 : {'encoding': '1010001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xa2001077', 'mask': '0xfe00707f'} -ursubw : {'encoding': '0011001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0x32001077', 'mask': '0xfe00707f'} -wexti : {'encoding': '1101111----------000-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xde000077', 'mask': '0xfe00707f'} -wext : {'encoding': '1100111----------000-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xce000077', 'mask': '0xfe00707f'} -zunpkd810 : {'encoding': '101011001100-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xacc00077', 'mask': '0xfff0707f'} -zunpkd820 : {'encoding': '101011001101-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xacd00077', 'mask': '0xfff0707f'} -zunpkd830 : {'encoding': '101011001110-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xace00077', 'mask': '0xfff0707f'} -zunpkd831 : {'encoding': '101011001111-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xacf00077', 'mask': '0xfff0707f'} -zunpkd832 : {'encoding': '101011010111-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv_p'], 'match': '0xad700077', 'mask': '0xfff0707f'} -add64 : {'encoding': '1100000----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv32_p'], 'match': '0xc0001077', 'mask': '0xfe00707f'} -sub64 : {'encoding': '1100001----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv32_p'], 'match': '0xc2001077', 'mask': '0xfe00707f'} -sha512sum0 : {'encoding': '000100000100-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zknh'], 'match': '0x10401013', 'mask': '0xfff0707f'} -sha512sum1 : {'encoding': '000100000101-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zknh'], 'match': '0x10501013', 'mask': '0xfff0707f'} -sha512sig0 : {'encoding': '000100000110-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zknh'], 'match': '0x10601013', 'mask': '0xfff0707f'} -sha512sig1 : {'encoding': '000100000111-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zknh'], 'match': '0x10701013', 'mask': '0xfff0707f'} -fcvt_l_d : {'encoding': '110000100010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_d'], 'match': '0xc2200053', 'mask': '0xfff0007f'} -fcvt_lu_d : {'encoding': '110000100011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_d'], 'match': '0xc2300053', 'mask': '0xfff0007f'} -fmv_x_d : {'encoding': '111000100000-----000-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_d'], 'match': '0xe2000053', 'mask': '0xfff0707f'} -fcvt_d_l : {'encoding': '110100100010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_d'], 'match': '0xd2200053', 'mask': '0xfff0007f'} -fcvt_d_lu : {'encoding': '110100100011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_d'], 'match': '0xd2300053', 'mask': '0xfff0007f'} -fmv_d_x : {'encoding': '111100100000-----000-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_d'], 'match': '0xf2000053', 'mask': '0xfff0707f'} -fld : {'encoding': '-----------------011-----0000111', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_d'], 'match': '0x3007', 'mask': '0x707f'} -fsd : {'encoding': '-----------------011-----0100111', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv_d'], 'match': '0x3027', 'mask': '0x707f'} -fmadd_d : {'encoding': '-----01------------------1000011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_d'], 'match': '0x2000043', 'mask': '0x600007f'} -fmsub_d : {'encoding': '-----01------------------1000111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_d'], 'match': '0x2000047', 'mask': '0x600007f'} -fnmsub_d : {'encoding': '-----01------------------1001011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_d'], 'match': '0x200004b', 'mask': '0x600007f'} -fnmadd_d : {'encoding': '-----01------------------1001111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_d'], 'match': '0x200004f', 'mask': '0x600007f'} -fadd_d : {'encoding': '0000001------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_d'], 'match': '0x2000053', 'mask': '0xfe00007f'} -fsub_d : {'encoding': '0000101------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_d'], 'match': '0xa000053', 'mask': '0xfe00007f'} -fmul_d : {'encoding': '0001001------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_d'], 'match': '0x12000053', 'mask': '0xfe00007f'} -fdiv_d : {'encoding': '0001101------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_d'], 'match': '0x1a000053', 'mask': '0xfe00007f'} -fsqrt_d : {'encoding': '010110100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d'], 'match': '0x5a000053', 'mask': '0xfff0007f'} -fsgnj_d : {'encoding': '0010001----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0x22000053', 'mask': '0xfe00707f'} -fsgnjn_d : {'encoding': '0010001----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0x22001053', 'mask': '0xfe00707f'} -fsgnjx_d : {'encoding': '0010001----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0x22002053', 'mask': '0xfe00707f'} -fmin_d : {'encoding': '0010101----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0x2a000053', 'mask': '0xfe00707f'} -fmax_d : {'encoding': '0010101----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0x2a001053', 'mask': '0xfe00707f'} -fcvt_s_d : {'encoding': '010000000001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d'], 'match': '0x40100053', 'mask': '0xfff0007f'} -fcvt_d_s : {'encoding': '010000100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d'], 'match': '0x42000053', 'mask': '0xfff0007f'} -feq_d : {'encoding': '1010001----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0xa2002053', 'mask': '0xfe00707f'} -flt_d : {'encoding': '1010001----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0xa2001053', 'mask': '0xfe00707f'} -fle_d : {'encoding': '1010001----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_d'], 'match': '0xa2000053', 'mask': '0xfe00707f'} -fclass_d : {'encoding': '111000100000-----001-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_d'], 'match': '0xe2001053', 'mask': '0xfff0707f'} -fcvt_w_d : {'encoding': '110000100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d'], 'match': '0xc2000053', 'mask': '0xfff0007f'} -fcvt_wu_d : {'encoding': '110000100001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d'], 'match': '0xc2100053', 'mask': '0xfff0007f'} -fcvt_d_w : {'encoding': '110100100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d'], 'match': '0xd2000053', 'mask': '0xfff0007f'} -fcvt_d_wu : {'encoding': '110100100001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d'], 'match': '0xd2100053', 'mask': '0xfff0007f'} -flh : {'encoding': '-----------------001-----0000111', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_zfh'], 'match': '0x1007', 'mask': '0x707f'} -fsh : {'encoding': '-----------------001-----0100111', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv_zfh'], 'match': '0x1027', 'mask': '0x707f'} -fmadd_h : {'encoding': '-----10------------------1000011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_zfh'], 'match': '0x4000043', 'mask': '0x600007f'} -fmsub_h : {'encoding': '-----10------------------1000111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_zfh'], 'match': '0x4000047', 'mask': '0x600007f'} -fnmsub_h : {'encoding': '-----10------------------1001011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_zfh'], 'match': '0x400004b', 'mask': '0x600007f'} -fnmadd_h : {'encoding': '-----10------------------1001111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_zfh'], 'match': '0x400004f', 'mask': '0x600007f'} -fadd_h : {'encoding': '0000010------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_zfh'], 'match': '0x4000053', 'mask': '0xfe00007f'} -fsub_h : {'encoding': '0000110------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_zfh'], 'match': '0xc000053', 'mask': '0xfe00007f'} -fmul_h : {'encoding': '0001010------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_zfh'], 'match': '0x14000053', 'mask': '0xfe00007f'} -fdiv_h : {'encoding': '0001110------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_zfh'], 'match': '0x1c000053', 'mask': '0xfe00007f'} -fsqrt_h : {'encoding': '010111000000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_zfh'], 'match': '0x5c000053', 'mask': '0xfff0007f'} -fsgnj_h : {'encoding': '0010010----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0x24000053', 'mask': '0xfe00707f'} -fsgnjn_h : {'encoding': '0010010----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0x24001053', 'mask': '0xfe00707f'} -fsgnjx_h : {'encoding': '0010010----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0x24002053', 'mask': '0xfe00707f'} -fmin_h : {'encoding': '0010110----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0x2c000053', 'mask': '0xfe00707f'} -fmax_h : {'encoding': '0010110----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0x2c001053', 'mask': '0xfe00707f'} -fcvt_s_h : {'encoding': '010000000010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_zfh'], 'match': '0x40200053', 'mask': '0xfff0007f'} -fcvt_h_s : {'encoding': '010001000000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_zfh'], 'match': '0x44000053', 'mask': '0xfff0007f'} -feq_h : {'encoding': '1010010----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0xa4002053', 'mask': '0xfe00707f'} -flt_h : {'encoding': '1010010----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0xa4001053', 'mask': '0xfe00707f'} -fle_h : {'encoding': '1010010----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zfh'], 'match': '0xa4000053', 'mask': '0xfe00707f'} -fclass_h : {'encoding': '111001000000-----001-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zfh'], 'match': '0xe4001053', 'mask': '0xfff0707f'} -fcvt_w_h : {'encoding': '110001000000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_zfh'], 'match': '0xc4000053', 'mask': '0xfff0007f'} -fcvt_wu_h : {'encoding': '110001000001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_zfh'], 'match': '0xc4100053', 'mask': '0xfff0007f'} -fmv_x_h : {'encoding': '111001000000-----000-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zfh'], 'match': '0xe4000053', 'mask': '0xfff0707f'} -fcvt_h_w : {'encoding': '110101000000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_zfh'], 'match': '0xd4000053', 'mask': '0xfff0007f'} -fcvt_h_wu : {'encoding': '110101000001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_zfh'], 'match': '0xd4100053', 'mask': '0xfff0007f'} -fmv_h_x : {'encoding': '111101000000-----000-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zfh'], 'match': '0xf4000053', 'mask': '0xfff0707f'} -fcvt_d_h : {'encoding': '010000100010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d_zfh'], 'match': '0x42200053', 'mask': '0xfff0007f'} -fcvt_h_d : {'encoding': '010001000001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_d_zfh'], 'match': '0x44100053', 'mask': '0xfff0007f'} -lr_d : {'encoding': '00010--00000-----011-----0101111', 'variable_fields': ['rd', 'rs1', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x1000302f', 'mask': '0xf9f0707f'} -sc_d : {'encoding': '00011------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x1800302f', 'mask': '0xf800707f'} -amoswap_d : {'encoding': '00001------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x800302f', 'mask': '0xf800707f'} -amoadd_d : {'encoding': '00000------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x302f', 'mask': '0xf800707f'} -amoxor_d : {'encoding': '00100------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x2000302f', 'mask': '0xf800707f'} -amoand_d : {'encoding': '01100------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x6000302f', 'mask': '0xf800707f'} -amoor_d : {'encoding': '01000------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x4000302f', 'mask': '0xf800707f'} -amomin_d : {'encoding': '10000------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0x8000302f', 'mask': '0xf800707f'} -amomax_d : {'encoding': '10100------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0xa000302f', 'mask': '0xf800707f'} -amominu_d : {'encoding': '11000------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0xc000302f', 'mask': '0xf800707f'} -amomaxu_d : {'encoding': '11100------------011-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv64_a'], 'match': '0xe000302f', 'mask': '0xf800707f'} -bclr : {'encoding': '0100100----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbs'], 'match': '0x48001033', 'mask': '0xfe00707f'} -bext : {'encoding': '0100100----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbs'], 'match': '0x48005033', 'mask': '0xfe00707f'} -binv : {'encoding': '0110100----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbs'], 'match': '0x68001033', 'mask': '0xfe00707f'} -bset : {'encoding': '0010100----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbs'], 'match': '0x28001033', 'mask': '0xfe00707f'} -sm3p0 : {'encoding': '000100001000-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zksh'], 'match': '0x10801013', 'mask': '0xfff0707f'} -sm3p1 : {'encoding': '000100001001-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zksh'], 'match': '0x10901013', 'mask': '0xfff0707f'} -sinval_vma : {'encoding': '0001011----------000000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_svinval'], 'match': '0x16000073', 'mask': '0xfe007fff'} -sfence_w_inval : {'encoding': '00011000000000000000000001110011', 'variable_fields': [], 'extension': ['rv_svinval'], 'match': '0x18000073', 'mask': '0xffffffff'} -sfence_inval_ir : {'encoding': '00011000000100000000000001110011', 'variable_fields': [], 'extension': ['rv_svinval'], 'match': '0x18100073', 'mask': '0xffffffff'} -hinval_vvma : {'encoding': '0010011----------000000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_svinval'], 'match': '0x26000073', 'mask': '0xfe007fff'} -hinval_gvma : {'encoding': '0110011----------000000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_svinval'], 'match': '0x66000073', 'mask': '0xfe007fff'} -slow : {'encoding': '0010000----------001-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_b'], 'match': '0x2000103b', 'mask': '0xfe00707f'} -srow : {'encoding': '0010000----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_b'], 'match': '0x2000503b', 'mask': '0xfe00707f'} -sloiw : {'encoding': '0010000----------001-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_b'], 'match': '0x2000101b', 'mask': '0xfe00707f'} -sroiw : {'encoding': '0010000----------101-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_b'], 'match': '0x2000501b', 'mask': '0xfe00707f'} -clzw : {'encoding': '011000000000-----001-----0011011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zbb'], 'match': '0x6000101b', 'mask': '0xfff0707f'} -ctzw : {'encoding': '011000000001-----001-----0011011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zbb'], 'match': '0x6010101b', 'mask': '0xfff0707f'} -cpopw : {'encoding': '011000000010-----001-----0011011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zbb'], 'match': '0x6020101b', 'mask': '0xfff0707f'} -rolw : {'encoding': '0110000----------001-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbb'], 'match': '0x6000103b', 'mask': '0xfe00707f'} -rorw : {'encoding': '0110000----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbb'], 'match': '0x6000503b', 'mask': '0xfe00707f'} -roriw : {'encoding': '0110000----------101-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_zbb'], 'match': '0x6000501b', 'mask': '0xfe00707f'} -rori : {'encoding': '011000-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zbb'], 'match': '0x60005013', 'mask': '0xfc00707f'} -add_uw : {'encoding': '0000100----------000-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zba'], 'match': '0x800003b', 'mask': '0xfe00707f'} -sh1add_uw : {'encoding': '0010000----------010-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zba'], 'match': '0x2000203b', 'mask': '0xfe00707f'} -sh2add_uw : {'encoding': '0010000----------100-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zba'], 'match': '0x2000403b', 'mask': '0xfe00707f'} -sh3add_uw : {'encoding': '0010000----------110-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zba'], 'match': '0x2000603b', 'mask': '0xfe00707f'} -slli_uw : {'encoding': '000010-----------001-----0011011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zba'], 'match': '0x800101b', 'mask': '0xfc00707f'} -add32 : {'encoding': '0100000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x40002077', 'mask': '0xfe00707f'} -radd32 : {'encoding': '0000000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x2077', 'mask': '0xfe00707f'} -uradd32 : {'encoding': '0010000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x20002077', 'mask': '0xfe00707f'} -kadd32 : {'encoding': '0001000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x10002077', 'mask': '0xfe00707f'} -ukadd32 : {'encoding': '0011000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x30002077', 'mask': '0xfe00707f'} -sub32 : {'encoding': '0100001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x42002077', 'mask': '0xfe00707f'} -rsub32 : {'encoding': '0000001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x2002077', 'mask': '0xfe00707f'} -ursub32 : {'encoding': '0010001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x22002077', 'mask': '0xfe00707f'} -ksub32 : {'encoding': '0001001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x12002077', 'mask': '0xfe00707f'} -uksub32 : {'encoding': '0011001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x32002077', 'mask': '0xfe00707f'} -cras32 : {'encoding': '0100010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x44002077', 'mask': '0xfe00707f'} -rcras32 : {'encoding': '0000010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x4002077', 'mask': '0xfe00707f'} -urcras32 : {'encoding': '0010010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x24002077', 'mask': '0xfe00707f'} -kcras32 : {'encoding': '0001010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x14002077', 'mask': '0xfe00707f'} -ukcras32 : {'encoding': '0011010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x34002077', 'mask': '0xfe00707f'} -crsa32 : {'encoding': '0100011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x46002077', 'mask': '0xfe00707f'} -rcrsa32 : {'encoding': '0000011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x6002077', 'mask': '0xfe00707f'} -urcrsa32 : {'encoding': '0010011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x26002077', 'mask': '0xfe00707f'} -kcrsa32 : {'encoding': '0001011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x16002077', 'mask': '0xfe00707f'} -ukcrsa32 : {'encoding': '0011011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x36002077', 'mask': '0xfe00707f'} -stas32 : {'encoding': '1111000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xf0002077', 'mask': '0xfe00707f'} -rstas32 : {'encoding': '1011000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xb0002077', 'mask': '0xfe00707f'} -urstas32 : {'encoding': '1101000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xd0002077', 'mask': '0xfe00707f'} -kstas32 : {'encoding': '1100000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xc0002077', 'mask': '0xfe00707f'} -ukstas32 : {'encoding': '1110000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xe0002077', 'mask': '0xfe00707f'} -stsa32 : {'encoding': '1111001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xf2002077', 'mask': '0xfe00707f'} -rstsa32 : {'encoding': '1011001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xb2002077', 'mask': '0xfe00707f'} -urstsa32 : {'encoding': '1101001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xd2002077', 'mask': '0xfe00707f'} -kstsa32 : {'encoding': '1100001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xc2002077', 'mask': '0xfe00707f'} -ukstsa32 : {'encoding': '1110001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xe2002077', 'mask': '0xfe00707f'} -sra32 : {'encoding': '0101000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x50002077', 'mask': '0xfe00707f'} -srai32 : {'encoding': '0111000----------010-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x70002077', 'mask': '0xfe00707f'} -sra32_u : {'encoding': '0110000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x60002077', 'mask': '0xfe00707f'} -srai32_u : {'encoding': '1000000----------010-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x80002077', 'mask': '0xfe00707f'} -srl32 : {'encoding': '0101001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x52002077', 'mask': '0xfe00707f'} -srli32 : {'encoding': '0111001----------010-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x72002077', 'mask': '0xfe00707f'} -srl32_u : {'encoding': '0110001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x62002077', 'mask': '0xfe00707f'} -srli32_u : {'encoding': '1000001----------010-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x82002077', 'mask': '0xfe00707f'} -sll32 : {'encoding': '0101010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x54002077', 'mask': '0xfe00707f'} -slli32 : {'encoding': '0111010----------010-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x74002077', 'mask': '0xfe00707f'} -ksll32 : {'encoding': '0110010----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x64002077', 'mask': '0xfe00707f'} -kslli32 : {'encoding': '1000010----------010-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x84002077', 'mask': '0xfe00707f'} -kslra32 : {'encoding': '0101011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x56002077', 'mask': '0xfe00707f'} -kslra32_u : {'encoding': '0110011----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x66002077', 'mask': '0xfe00707f'} -smin32 : {'encoding': '1001000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x90002077', 'mask': '0xfe00707f'} -umin32 : {'encoding': '1010000----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xa0002077', 'mask': '0xfe00707f'} -smax32 : {'encoding': '1001001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x92002077', 'mask': '0xfe00707f'} -umax32 : {'encoding': '1010001----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xa2002077', 'mask': '0xfe00707f'} -kabs32 : {'encoding': '101011010010-----000-----1110111', 'variable_fields': ['rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xad200077', 'mask': '0xfff0707f'} -khmbb16 : {'encoding': '1101110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xdc001077', 'mask': '0xfe00707f'} -khmbt16 : {'encoding': '1110110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xec001077', 'mask': '0xfe00707f'} -khmtt16 : {'encoding': '1111110----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xfc001077', 'mask': '0xfe00707f'} -kdmbb16 : {'encoding': '1101101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xda001077', 'mask': '0xfe00707f'} -kdmbt16 : {'encoding': '1110101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xea001077', 'mask': '0xfe00707f'} -kdmtt16 : {'encoding': '1111101----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xfa001077', 'mask': '0xfe00707f'} -kdmabb16 : {'encoding': '1101100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xd8001077', 'mask': '0xfe00707f'} -kdmabt16 : {'encoding': '1110100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xe8001077', 'mask': '0xfe00707f'} -kdmatt16 : {'encoding': '1111100----------001-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xf8001077', 'mask': '0xfe00707f'} -smbt32 : {'encoding': '0001100----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x18002077', 'mask': '0xfe00707f'} -smtt32 : {'encoding': '0010100----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x28002077', 'mask': '0xfe00707f'} -kmabb32 : {'encoding': '0101101----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x5a002077', 'mask': '0xfe00707f'} -kmabt32 : {'encoding': '0110101----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x6a002077', 'mask': '0xfe00707f'} -kmatt32 : {'encoding': '0111101----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x7a002077', 'mask': '0xfe00707f'} -kmda32 : {'encoding': '0011100----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x38002077', 'mask': '0xfe00707f'} -kmxda32 : {'encoding': '0011101----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x3a002077', 'mask': '0xfe00707f'} -kmaxda32 : {'encoding': '0100101----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x4a002077', 'mask': '0xfe00707f'} -kmads32 : {'encoding': '0101110----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x5c002077', 'mask': '0xfe00707f'} -kmadrs32 : {'encoding': '0110110----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x6c002077', 'mask': '0xfe00707f'} -kmaxds32 : {'encoding': '0111110----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x7c002077', 'mask': '0xfe00707f'} -kmsda32 : {'encoding': '0100110----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x4c002077', 'mask': '0xfe00707f'} -kmsxda32 : {'encoding': '0100111----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x4e002077', 'mask': '0xfe00707f'} -smds32 : {'encoding': '0101100----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x58002077', 'mask': '0xfe00707f'} -smdrs32 : {'encoding': '0110100----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x68002077', 'mask': '0xfe00707f'} -smxds32 : {'encoding': '0111100----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x78002077', 'mask': '0xfe00707f'} -sraiw_u : {'encoding': '0011010----------001-----1110111', 'variable_fields': ['imm5', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x34001077', 'mask': '0xfe00707f'} -pkbb32 : {'encoding': '0000111----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0xe002077', 'mask': '0xfe00707f'} -pkbt32 : {'encoding': '0001111----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x1e002077', 'mask': '0xfe00707f'} -pktt32 : {'encoding': '0010111----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x2e002077', 'mask': '0xfe00707f'} -pktb32 : {'encoding': '0011111----------010-----1110111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv64_p'], 'match': '0x3e002077', 'mask': '0xfe00707f'} -mulw : {'encoding': '0000001----------000-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_m'], 'match': '0x200003b', 'mask': '0xfe00707f'} -divw : {'encoding': '0000001----------100-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_m'], 'match': '0x200403b', 'mask': '0xfe00707f'} -divuw : {'encoding': '0000001----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_m'], 'match': '0x200503b', 'mask': '0xfe00707f'} -remw : {'encoding': '0000001----------110-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_m'], 'match': '0x200603b', 'mask': '0xfe00707f'} -remuw : {'encoding': '0000001----------111-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_m'], 'match': '0x200703b', 'mask': '0xfe00707f'} -sh1add : {'encoding': '0010000----------010-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zba'], 'match': '0x20002033', 'mask': '0xfe00707f'} -sh2add : {'encoding': '0010000----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zba'], 'match': '0x20004033', 'mask': '0xfe00707f'} -sh3add : {'encoding': '0010000----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zba'], 'match': '0x20006033', 'mask': '0xfe00707f'} -bmatflip : {'encoding': '011000000011-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zbm'], 'match': '0x60301013', 'mask': '0xfff0707f'} -bmator : {'encoding': '0000100----------011-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbm'], 'match': '0x8003033', 'mask': '0xfe00707f'} -bmatxor : {'encoding': '0100100----------011-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbm'], 'match': '0x48003033', 'mask': '0xfe00707f'} -vsetivli : {'encoding': '11---------------111-----1010111', 'variable_fields': ['zimm10', 'zimm', 'rd'], 'extension': ['rv_v'], 'match': '0xc0007057', 'mask': '0xc000707f'} -vsetvli : {'encoding': '0----------------111-----1010111', 'variable_fields': ['zimm11', 'rs1', 'rd'], 'extension': ['rv_v'], 'match': '0x7057', 'mask': '0x8000707f'} -vsetvl : {'encoding': '1000000----------111-----1010111', 'variable_fields': ['rs2', 'rs1', 'rd'], 'extension': ['rv_v'], 'match': '0x80007057', 'mask': '0xfe00707f'} -vlm_v : {'encoding': '000000101011-----000-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2b00007', 'mask': '0xfff0707f'} -vsm_v : {'encoding': '000000101011-----000-----0100111', 'variable_fields': ['rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x2b00027', 'mask': '0xfff0707f'} -vle8_v : {'encoding': '---000-00000-----000-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x7', 'mask': '0x1df0707f'} -vle16_v : {'encoding': '---000-00000-----101-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5007', 'mask': '0x1df0707f'} -vle32_v : {'encoding': '---000-00000-----110-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6007', 'mask': '0x1df0707f'} -vle64_v : {'encoding': '---000-00000-----111-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x7007', 'mask': '0x1df0707f'} -vle128_v : {'encoding': '---100-00000-----000-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10000007', 'mask': '0x1df0707f'} -vle256_v : {'encoding': '---100-00000-----101-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10005007', 'mask': '0x1df0707f'} -vle512_v : {'encoding': '---100-00000-----110-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10006007', 'mask': '0x1df0707f'} -vle1024_v : {'encoding': '---100-00000-----111-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10007007', 'mask': '0x1df0707f'} -vse8_v : {'encoding': '---000-00000-----000-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x27', 'mask': '0x1df0707f'} -vse16_v : {'encoding': '---000-00000-----101-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x5027', 'mask': '0x1df0707f'} -vse32_v : {'encoding': '---000-00000-----110-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x6027', 'mask': '0x1df0707f'} -vse64_v : {'encoding': '---000-00000-----111-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x7027', 'mask': '0x1df0707f'} -vse128_v : {'encoding': '---100-00000-----000-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x10000027', 'mask': '0x1df0707f'} -vse256_v : {'encoding': '---100-00000-----101-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x10005027', 'mask': '0x1df0707f'} -vse512_v : {'encoding': '---100-00000-----110-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x10006027', 'mask': '0x1df0707f'} -vse1024_v : {'encoding': '---100-00000-----111-----0100111', 'variable_fields': ['nf', 'vm', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x10007027', 'mask': '0x1df0707f'} -vluxei8_v : {'encoding': '---001-----------000-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4000007', 'mask': '0x1c00707f'} -vluxei16_v : {'encoding': '---001-----------101-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4005007', 'mask': '0x1c00707f'} -vluxei32_v : {'encoding': '---001-----------110-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4006007', 'mask': '0x1c00707f'} -vluxei64_v : {'encoding': '---001-----------111-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4007007', 'mask': '0x1c00707f'} -vluxei128_v : {'encoding': '---101-----------000-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14000007', 'mask': '0x1c00707f'} -vluxei256_v : {'encoding': '---101-----------101-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14005007', 'mask': '0x1c00707f'} -vluxei512_v : {'encoding': '---101-----------110-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14006007', 'mask': '0x1c00707f'} -vluxei1024_v : {'encoding': '---101-----------111-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14007007', 'mask': '0x1c00707f'} -vsuxei8_v : {'encoding': '---001-----------000-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x4000027', 'mask': '0x1c00707f'} -vsuxei16_v : {'encoding': '---001-----------101-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x4005027', 'mask': '0x1c00707f'} -vsuxei32_v : {'encoding': '---001-----------110-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x4006027', 'mask': '0x1c00707f'} -vsuxei64_v : {'encoding': '---001-----------111-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x4007027', 'mask': '0x1c00707f'} -vsuxei128_v : {'encoding': '---101-----------000-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x14000027', 'mask': '0x1c00707f'} -vsuxei256_v : {'encoding': '---101-----------101-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x14005027', 'mask': '0x1c00707f'} -vsuxei512_v : {'encoding': '---101-----------110-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x14006027', 'mask': '0x1c00707f'} -vsuxei1024_v : {'encoding': '---101-----------111-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x14007027', 'mask': '0x1c00707f'} -vlse8_v : {'encoding': '---010-----------000-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8000007', 'mask': '0x1c00707f'} -vlse16_v : {'encoding': '---010-----------101-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8005007', 'mask': '0x1c00707f'} -vlse32_v : {'encoding': '---010-----------110-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8006007', 'mask': '0x1c00707f'} -vlse64_v : {'encoding': '---010-----------111-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8007007', 'mask': '0x1c00707f'} -vlse128_v : {'encoding': '---110-----------000-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18000007', 'mask': '0x1c00707f'} -vlse256_v : {'encoding': '---110-----------101-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18005007', 'mask': '0x1c00707f'} -vlse512_v : {'encoding': '---110-----------110-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18006007', 'mask': '0x1c00707f'} -vlse1024_v : {'encoding': '---110-----------111-----0000111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18007007', 'mask': '0x1c00707f'} -vsse8_v : {'encoding': '---010-----------000-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x8000027', 'mask': '0x1c00707f'} -vsse16_v : {'encoding': '---010-----------101-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x8005027', 'mask': '0x1c00707f'} -vsse32_v : {'encoding': '---010-----------110-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x8006027', 'mask': '0x1c00707f'} -vsse64_v : {'encoding': '---010-----------111-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x8007027', 'mask': '0x1c00707f'} -vsse128_v : {'encoding': '---110-----------000-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x18000027', 'mask': '0x1c00707f'} -vsse256_v : {'encoding': '---110-----------101-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x18005027', 'mask': '0x1c00707f'} -vsse512_v : {'encoding': '---110-----------110-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x18006027', 'mask': '0x1c00707f'} -vsse1024_v : {'encoding': '---110-----------111-----0100111', 'variable_fields': ['nf', 'vm', 'rs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x18007027', 'mask': '0x1c00707f'} -vloxei8_v : {'encoding': '---011-----------000-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc000007', 'mask': '0x1c00707f'} -vloxei16_v : {'encoding': '---011-----------101-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc005007', 'mask': '0x1c00707f'} -vloxei32_v : {'encoding': '---011-----------110-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc006007', 'mask': '0x1c00707f'} -vloxei64_v : {'encoding': '---011-----------111-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc007007', 'mask': '0x1c00707f'} -vloxei128_v : {'encoding': '---111-----------000-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c000007', 'mask': '0x1c00707f'} -vloxei256_v : {'encoding': '---111-----------101-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c005007', 'mask': '0x1c00707f'} -vloxei512_v : {'encoding': '---111-----------110-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c006007', 'mask': '0x1c00707f'} -vloxei1024_v : {'encoding': '---111-----------111-----0000111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c007007', 'mask': '0x1c00707f'} -vsoxei8_v : {'encoding': '---011-----------000-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0xc000027', 'mask': '0x1c00707f'} -vsoxei16_v : {'encoding': '---011-----------101-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0xc005027', 'mask': '0x1c00707f'} -vsoxei32_v : {'encoding': '---011-----------110-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0xc006027', 'mask': '0x1c00707f'} -vsoxei64_v : {'encoding': '---011-----------111-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0xc007027', 'mask': '0x1c00707f'} -vsoxei128_v : {'encoding': '---111-----------000-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x1c000027', 'mask': '0x1c00707f'} -vsoxei256_v : {'encoding': '---111-----------101-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x1c005027', 'mask': '0x1c00707f'} -vsoxei512_v : {'encoding': '---111-----------110-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x1c006027', 'mask': '0x1c00707f'} -vsoxei1024_v : {'encoding': '---111-----------111-----0100111', 'variable_fields': ['nf', 'vm', 'vs2', 'rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x1c007027', 'mask': '0x1c00707f'} -vle8ff_v : {'encoding': '---000-10000-----000-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1000007', 'mask': '0x1df0707f'} -vle16ff_v : {'encoding': '---000-10000-----101-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1005007', 'mask': '0x1df0707f'} -vle32ff_v : {'encoding': '---000-10000-----110-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1006007', 'mask': '0x1df0707f'} -vle64ff_v : {'encoding': '---000-10000-----111-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1007007', 'mask': '0x1df0707f'} -vle128ff_v : {'encoding': '---100-10000-----000-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x11000007', 'mask': '0x1df0707f'} -vle256ff_v : {'encoding': '---100-10000-----101-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x11005007', 'mask': '0x1df0707f'} -vle512ff_v : {'encoding': '---100-10000-----110-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x11006007', 'mask': '0x1df0707f'} -vle1024ff_v : {'encoding': '---100-10000-----111-----0000111', 'variable_fields': ['nf', 'vm', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x11007007', 'mask': '0x1df0707f'} -vl1re8_v : {'encoding': '000000101000-----000-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2800007', 'mask': '0xfff0707f'} -vl1re16_v : {'encoding': '000000101000-----101-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2805007', 'mask': '0xfff0707f'} -vl1re32_v : {'encoding': '000000101000-----110-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2806007', 'mask': '0xfff0707f'} -vl1re64_v : {'encoding': '000000101000-----111-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2807007', 'mask': '0xfff0707f'} -vl2re8_v : {'encoding': '001000101000-----000-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x22800007', 'mask': '0xfff0707f'} -vl2re16_v : {'encoding': '001000101000-----101-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x22805007', 'mask': '0xfff0707f'} -vl2re32_v : {'encoding': '001000101000-----110-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x22806007', 'mask': '0xfff0707f'} -vl2re64_v : {'encoding': '001000101000-----111-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x22807007', 'mask': '0xfff0707f'} -vl4re8_v : {'encoding': '011000101000-----000-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x62800007', 'mask': '0xfff0707f'} -vl4re16_v : {'encoding': '011000101000-----101-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x62805007', 'mask': '0xfff0707f'} -vl4re32_v : {'encoding': '011000101000-----110-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x62806007', 'mask': '0xfff0707f'} -vl4re64_v : {'encoding': '011000101000-----111-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x62807007', 'mask': '0xfff0707f'} -vl8re8_v : {'encoding': '111000101000-----000-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe2800007', 'mask': '0xfff0707f'} -vl8re16_v : {'encoding': '111000101000-----101-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe2805007', 'mask': '0xfff0707f'} -vl8re32_v : {'encoding': '111000101000-----110-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe2806007', 'mask': '0xfff0707f'} -vl8re64_v : {'encoding': '111000101000-----111-----0000111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe2807007', 'mask': '0xfff0707f'} -vs1r_v : {'encoding': '000000101000-----000-----0100111', 'variable_fields': ['rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x2800027', 'mask': '0xfff0707f'} -vs2r_v : {'encoding': '001000101000-----000-----0100111', 'variable_fields': ['rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x22800027', 'mask': '0xfff0707f'} -vs4r_v : {'encoding': '011000101000-----000-----0100111', 'variable_fields': ['rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0x62800027', 'mask': '0xfff0707f'} -vs8r_v : {'encoding': '111000101000-----000-----0100111', 'variable_fields': ['rs1', 'vs3'], 'extension': ['rv_v'], 'match': '0xe2800027', 'mask': '0xfff0707f'} -vfadd_vf : {'encoding': '000000-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5057', 'mask': '0xfc00707f'} -vfsub_vf : {'encoding': '000010-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8005057', 'mask': '0xfc00707f'} -vfmin_vf : {'encoding': '000100-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10005057', 'mask': '0xfc00707f'} -vfmax_vf : {'encoding': '000110-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18005057', 'mask': '0xfc00707f'} -vfsgnj_vf : {'encoding': '001000-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x20005057', 'mask': '0xfc00707f'} -vfsgnjn_vf : {'encoding': '001001-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x24005057', 'mask': '0xfc00707f'} -vfsgnjx_vf : {'encoding': '001010-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x28005057', 'mask': '0xfc00707f'} -vfslide1up_vf : {'encoding': '001110-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x38005057', 'mask': '0xfc00707f'} -vfslide1down_vf : {'encoding': '001111-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x3c005057', 'mask': '0xfc00707f'} -vfmv_s_f : {'encoding': '010000100000-----101-----1010111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x42005057', 'mask': '0xfff0707f'} -vfmerge_vfm : {'encoding': '0101110----------101-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5c005057', 'mask': '0xfe00707f'} -vfmv_v_f : {'encoding': '010111100000-----101-----1010111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5e005057', 'mask': '0xfff0707f'} -vmfeq_vf : {'encoding': '011000-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x60005057', 'mask': '0xfc00707f'} -vmfle_vf : {'encoding': '011001-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x64005057', 'mask': '0xfc00707f'} -vmflt_vf : {'encoding': '011011-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6c005057', 'mask': '0xfc00707f'} -vmfne_vf : {'encoding': '011100-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x70005057', 'mask': '0xfc00707f'} -vmfgt_vf : {'encoding': '011101-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x74005057', 'mask': '0xfc00707f'} -vmfge_vf : {'encoding': '011111-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x7c005057', 'mask': '0xfc00707f'} -vfdiv_vf : {'encoding': '100000-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x80005057', 'mask': '0xfc00707f'} -vfrdiv_vf : {'encoding': '100001-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x84005057', 'mask': '0xfc00707f'} -vfmul_vf : {'encoding': '100100-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x90005057', 'mask': '0xfc00707f'} -vfrsub_vf : {'encoding': '100111-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x9c005057', 'mask': '0xfc00707f'} -vfmadd_vf : {'encoding': '101000-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa0005057', 'mask': '0xfc00707f'} -vfnmadd_vf : {'encoding': '101001-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa4005057', 'mask': '0xfc00707f'} -vfmsub_vf : {'encoding': '101010-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa8005057', 'mask': '0xfc00707f'} -vfnmsub_vf : {'encoding': '101011-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xac005057', 'mask': '0xfc00707f'} -vfmacc_vf : {'encoding': '101100-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb0005057', 'mask': '0xfc00707f'} -vfnmacc_vf : {'encoding': '101101-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb4005057', 'mask': '0xfc00707f'} -vfmsac_vf : {'encoding': '101110-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb8005057', 'mask': '0xfc00707f'} -vfnmsac_vf : {'encoding': '101111-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xbc005057', 'mask': '0xfc00707f'} -vfwadd_vf : {'encoding': '110000-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc0005057', 'mask': '0xfc00707f'} -vfwsub_vf : {'encoding': '110010-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc8005057', 'mask': '0xfc00707f'} -vfwadd_wf : {'encoding': '110100-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd0005057', 'mask': '0xfc00707f'} -vfwsub_wf : {'encoding': '110110-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd8005057', 'mask': '0xfc00707f'} -vfwmul_vf : {'encoding': '111000-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe0005057', 'mask': '0xfc00707f'} -vfwmacc_vf : {'encoding': '111100-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf0005057', 'mask': '0xfc00707f'} -vfwnmacc_vf : {'encoding': '111101-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf4005057', 'mask': '0xfc00707f'} -vfwmsac_vf : {'encoding': '111110-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf8005057', 'mask': '0xfc00707f'} -vfwnmsac_vf : {'encoding': '111111-----------101-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xfc005057', 'mask': '0xfc00707f'} -vfadd_vv : {'encoding': '000000-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1057', 'mask': '0xfc00707f'} -vfredusum_vs : {'encoding': '000001-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4001057', 'mask': '0xfc00707f'} -vfsub_vv : {'encoding': '000010-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8001057', 'mask': '0xfc00707f'} -vfredosum_vs : {'encoding': '000011-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc001057', 'mask': '0xfc00707f'} -vfmin_vv : {'encoding': '000100-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10001057', 'mask': '0xfc00707f'} -vfredmin_vs : {'encoding': '000101-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14001057', 'mask': '0xfc00707f'} -vfmax_vv : {'encoding': '000110-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18001057', 'mask': '0xfc00707f'} -vfredmax_vs : {'encoding': '000111-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c001057', 'mask': '0xfc00707f'} -vfsgnj_vv : {'encoding': '001000-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x20001057', 'mask': '0xfc00707f'} -vfsgnjn_vv : {'encoding': '001001-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x24001057', 'mask': '0xfc00707f'} -vfsgnjx_vv : {'encoding': '001010-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x28001057', 'mask': '0xfc00707f'} -vfmv_f_s : {'encoding': '0100001-----00000001-----1010111', 'variable_fields': ['vs2', 'rd'], 'extension': ['rv_v'], 'match': '0x42001057', 'mask': '0xfe0ff07f'} -vmfeq_vv : {'encoding': '011000-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x60001057', 'mask': '0xfc00707f'} -vmfle_vv : {'encoding': '011001-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x64001057', 'mask': '0xfc00707f'} -vmflt_vv : {'encoding': '011011-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6c001057', 'mask': '0xfc00707f'} -vmfne_vv : {'encoding': '011100-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x70001057', 'mask': '0xfc00707f'} -vfdiv_vv : {'encoding': '100000-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x80001057', 'mask': '0xfc00707f'} -vfmul_vv : {'encoding': '100100-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x90001057', 'mask': '0xfc00707f'} -vfmadd_vv : {'encoding': '101000-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa0001057', 'mask': '0xfc00707f'} -vfnmadd_vv : {'encoding': '101001-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa4001057', 'mask': '0xfc00707f'} -vfmsub_vv : {'encoding': '101010-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa8001057', 'mask': '0xfc00707f'} -vfnmsub_vv : {'encoding': '101011-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xac001057', 'mask': '0xfc00707f'} -vfmacc_vv : {'encoding': '101100-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb0001057', 'mask': '0xfc00707f'} -vfnmacc_vv : {'encoding': '101101-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb4001057', 'mask': '0xfc00707f'} -vfmsac_vv : {'encoding': '101110-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb8001057', 'mask': '0xfc00707f'} -vfnmsac_vv : {'encoding': '101111-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xbc001057', 'mask': '0xfc00707f'} -vfcvt_xu_f_v : {'encoding': '010010------00000001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48001057', 'mask': '0xfc0ff07f'} -vfcvt_x_f_v : {'encoding': '010010------00001001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48009057', 'mask': '0xfc0ff07f'} -vfcvt_f_xu_v : {'encoding': '010010------00010001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48011057', 'mask': '0xfc0ff07f'} -vfcvt_f_x_v : {'encoding': '010010------00011001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48019057', 'mask': '0xfc0ff07f'} -vfcvt_rtz_xu_f_v : {'encoding': '010010------00110001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48031057', 'mask': '0xfc0ff07f'} -vfcvt_rtz_x_f_v : {'encoding': '010010------00111001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48039057', 'mask': '0xfc0ff07f'} -vfwcvt_xu_f_v : {'encoding': '010010------01000001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48041057', 'mask': '0xfc0ff07f'} -vfwcvt_x_f_v : {'encoding': '010010------01001001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48049057', 'mask': '0xfc0ff07f'} -vfwcvt_f_xu_v : {'encoding': '010010------01010001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48051057', 'mask': '0xfc0ff07f'} -vfwcvt_f_x_v : {'encoding': '010010------01011001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48059057', 'mask': '0xfc0ff07f'} -vfwcvt_f_f_v : {'encoding': '010010------01100001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48061057', 'mask': '0xfc0ff07f'} -vfwcvt_rtz_xu_f_v : {'encoding': '010010------01110001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48071057', 'mask': '0xfc0ff07f'} -vfwcvt_rtz_x_f_v : {'encoding': '010010------01111001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48079057', 'mask': '0xfc0ff07f'} -vfncvt_xu_f_w : {'encoding': '010010------10000001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48081057', 'mask': '0xfc0ff07f'} -vfncvt_x_f_w : {'encoding': '010010------10001001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48089057', 'mask': '0xfc0ff07f'} -vfncvt_f_xu_w : {'encoding': '010010------10010001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48091057', 'mask': '0xfc0ff07f'} -vfncvt_f_x_w : {'encoding': '010010------10011001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48099057', 'mask': '0xfc0ff07f'} -vfncvt_f_f_w : {'encoding': '010010------10100001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x480a1057', 'mask': '0xfc0ff07f'} -vfncvt_rod_f_f_w : {'encoding': '010010------10101001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x480a9057', 'mask': '0xfc0ff07f'} -vfncvt_rtz_xu_f_w : {'encoding': '010010------10110001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x480b1057', 'mask': '0xfc0ff07f'} -vfncvt_rtz_x_f_w : {'encoding': '010010------10111001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x480b9057', 'mask': '0xfc0ff07f'} -vfsqrt_v : {'encoding': '010011------00000001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x4c001057', 'mask': '0xfc0ff07f'} -vfrsqrt7_v : {'encoding': '010011------00100001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x4c021057', 'mask': '0xfc0ff07f'} -vfrec7_v : {'encoding': '010011------00101001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x4c029057', 'mask': '0xfc0ff07f'} -vfclass_v : {'encoding': '010011------10000001-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x4c081057', 'mask': '0xfc0ff07f'} -vfwadd_vv : {'encoding': '110000-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc0001057', 'mask': '0xfc00707f'} -vfwredusum_vs : {'encoding': '110001-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc4001057', 'mask': '0xfc00707f'} -vfwsub_vv : {'encoding': '110010-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc8001057', 'mask': '0xfc00707f'} -vfwredosum_vs : {'encoding': '110011-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xcc001057', 'mask': '0xfc00707f'} -vfwadd_wv : {'encoding': '110100-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd0001057', 'mask': '0xfc00707f'} -vfwsub_wv : {'encoding': '110110-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd8001057', 'mask': '0xfc00707f'} -vfwmul_vv : {'encoding': '111000-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe0001057', 'mask': '0xfc00707f'} -vfwmacc_vv : {'encoding': '111100-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf0001057', 'mask': '0xfc00707f'} -vfwnmacc_vv : {'encoding': '111101-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf4001057', 'mask': '0xfc00707f'} -vfwmsac_vv : {'encoding': '111110-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf8001057', 'mask': '0xfc00707f'} -vfwnmsac_vv : {'encoding': '111111-----------001-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xfc001057', 'mask': '0xfc00707f'} -vadd_vx : {'encoding': '000000-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4057', 'mask': '0xfc00707f'} -vsub_vx : {'encoding': '000010-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8004057', 'mask': '0xfc00707f'} -vrsub_vx : {'encoding': '000011-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc004057', 'mask': '0xfc00707f'} -vminu_vx : {'encoding': '000100-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10004057', 'mask': '0xfc00707f'} -vmin_vx : {'encoding': '000101-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14004057', 'mask': '0xfc00707f'} -vmaxu_vx : {'encoding': '000110-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18004057', 'mask': '0xfc00707f'} -vmax_vx : {'encoding': '000111-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c004057', 'mask': '0xfc00707f'} -vand_vx : {'encoding': '001001-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x24004057', 'mask': '0xfc00707f'} -vor_vx : {'encoding': '001010-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x28004057', 'mask': '0xfc00707f'} -vxor_vx : {'encoding': '001011-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2c004057', 'mask': '0xfc00707f'} -vrgather_vx : {'encoding': '001100-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x30004057', 'mask': '0xfc00707f'} -vslideup_vx : {'encoding': '001110-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x38004057', 'mask': '0xfc00707f'} -vslidedown_vx : {'encoding': '001111-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x3c004057', 'mask': '0xfc00707f'} -vadc_vxm : {'encoding': '0100000----------100-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x40004057', 'mask': '0xfe00707f'} -vmadc_vxm : {'encoding': '0100010----------100-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x44004057', 'mask': '0xfe00707f'} -vmadc_vx : {'encoding': '0100011----------100-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x46004057', 'mask': '0xfe00707f'} -vsbc_vxm : {'encoding': '0100100----------100-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x48004057', 'mask': '0xfe00707f'} -vmsbc_vxm : {'encoding': '0100110----------100-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4c004057', 'mask': '0xfe00707f'} -vmsbc_vx : {'encoding': '0100111----------100-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4e004057', 'mask': '0xfe00707f'} -vmerge_vxm : {'encoding': '0101110----------100-----1010111', 'variable_fields': ['vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5c004057', 'mask': '0xfe00707f'} -vmv_v_x : {'encoding': '010111100000-----100-----1010111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5e004057', 'mask': '0xfff0707f'} -vmseq_vx : {'encoding': '011000-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x60004057', 'mask': '0xfc00707f'} -vmsne_vx : {'encoding': '011001-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x64004057', 'mask': '0xfc00707f'} -vmsltu_vx : {'encoding': '011010-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x68004057', 'mask': '0xfc00707f'} -vmslt_vx : {'encoding': '011011-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6c004057', 'mask': '0xfc00707f'} -vmsleu_vx : {'encoding': '011100-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x70004057', 'mask': '0xfc00707f'} -vmsle_vx : {'encoding': '011101-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x74004057', 'mask': '0xfc00707f'} -vmsgtu_vx : {'encoding': '011110-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x78004057', 'mask': '0xfc00707f'} -vmsgt_vx : {'encoding': '011111-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x7c004057', 'mask': '0xfc00707f'} -vsaddu_vx : {'encoding': '100000-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x80004057', 'mask': '0xfc00707f'} -vsadd_vx : {'encoding': '100001-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x84004057', 'mask': '0xfc00707f'} -vssubu_vx : {'encoding': '100010-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x88004057', 'mask': '0xfc00707f'} -vssub_vx : {'encoding': '100011-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8c004057', 'mask': '0xfc00707f'} -vsll_vx : {'encoding': '100101-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x94004057', 'mask': '0xfc00707f'} -vsmul_vx : {'encoding': '100111-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x9c004057', 'mask': '0xfc00707f'} -vsrl_vx : {'encoding': '101000-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa0004057', 'mask': '0xfc00707f'} -vsra_vx : {'encoding': '101001-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa4004057', 'mask': '0xfc00707f'} -vssrl_vx : {'encoding': '101010-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa8004057', 'mask': '0xfc00707f'} -vssra_vx : {'encoding': '101011-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xac004057', 'mask': '0xfc00707f'} -vnsrl_wx : {'encoding': '101100-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb0004057', 'mask': '0xfc00707f'} -vnsra_wx : {'encoding': '101101-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb4004057', 'mask': '0xfc00707f'} -vnclipu_wx : {'encoding': '101110-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb8004057', 'mask': '0xfc00707f'} -vnclip_wx : {'encoding': '101111-----------100-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xbc004057', 'mask': '0xfc00707f'} -vadd_vv : {'encoding': '000000-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x57', 'mask': '0xfc00707f'} -vsub_vv : {'encoding': '000010-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8000057', 'mask': '0xfc00707f'} -vminu_vv : {'encoding': '000100-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10000057', 'mask': '0xfc00707f'} -vmin_vv : {'encoding': '000101-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14000057', 'mask': '0xfc00707f'} -vmaxu_vv : {'encoding': '000110-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18000057', 'mask': '0xfc00707f'} -vmax_vv : {'encoding': '000111-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c000057', 'mask': '0xfc00707f'} -vand_vv : {'encoding': '001001-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x24000057', 'mask': '0xfc00707f'} -vor_vv : {'encoding': '001010-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x28000057', 'mask': '0xfc00707f'} -vxor_vv : {'encoding': '001011-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2c000057', 'mask': '0xfc00707f'} -vrgather_vv : {'encoding': '001100-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x30000057', 'mask': '0xfc00707f'} -vrgatherei16_vv : {'encoding': '001110-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x38000057', 'mask': '0xfc00707f'} -vadc_vvm : {'encoding': '0100000----------000-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x40000057', 'mask': '0xfe00707f'} -vmadc_vvm : {'encoding': '0100010----------000-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x44000057', 'mask': '0xfe00707f'} -vmadc_vv : {'encoding': '0100011----------000-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x46000057', 'mask': '0xfe00707f'} -vsbc_vvm : {'encoding': '0100100----------000-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x48000057', 'mask': '0xfe00707f'} -vmsbc_vvm : {'encoding': '0100110----------000-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4c000057', 'mask': '0xfe00707f'} -vmsbc_vv : {'encoding': '0100111----------000-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4e000057', 'mask': '0xfe00707f'} -vmerge_vvm : {'encoding': '0101110----------000-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5c000057', 'mask': '0xfe00707f'} -vmv_v_v : {'encoding': '010111100000-----000-----1010111', 'variable_fields': ['vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5e000057', 'mask': '0xfff0707f'} -vmseq_vv : {'encoding': '011000-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x60000057', 'mask': '0xfc00707f'} -vmsne_vv : {'encoding': '011001-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x64000057', 'mask': '0xfc00707f'} -vmsltu_vv : {'encoding': '011010-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x68000057', 'mask': '0xfc00707f'} -vmslt_vv : {'encoding': '011011-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6c000057', 'mask': '0xfc00707f'} -vmsleu_vv : {'encoding': '011100-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x70000057', 'mask': '0xfc00707f'} -vmsle_vv : {'encoding': '011101-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x74000057', 'mask': '0xfc00707f'} -vsaddu_vv : {'encoding': '100000-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x80000057', 'mask': '0xfc00707f'} -vsadd_vv : {'encoding': '100001-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x84000057', 'mask': '0xfc00707f'} -vssubu_vv : {'encoding': '100010-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x88000057', 'mask': '0xfc00707f'} -vssub_vv : {'encoding': '100011-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8c000057', 'mask': '0xfc00707f'} -vsll_vv : {'encoding': '100101-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x94000057', 'mask': '0xfc00707f'} -vsmul_vv : {'encoding': '100111-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x9c000057', 'mask': '0xfc00707f'} -vsrl_vv : {'encoding': '101000-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa0000057', 'mask': '0xfc00707f'} -vsra_vv : {'encoding': '101001-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa4000057', 'mask': '0xfc00707f'} -vssrl_vv : {'encoding': '101010-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa8000057', 'mask': '0xfc00707f'} -vssra_vv : {'encoding': '101011-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xac000057', 'mask': '0xfc00707f'} -vnsrl_wv : {'encoding': '101100-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb0000057', 'mask': '0xfc00707f'} -vnsra_wv : {'encoding': '101101-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb4000057', 'mask': '0xfc00707f'} -vnclipu_wv : {'encoding': '101110-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb8000057', 'mask': '0xfc00707f'} -vnclip_wv : {'encoding': '101111-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xbc000057', 'mask': '0xfc00707f'} -vwredsumu_vs : {'encoding': '110000-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc0000057', 'mask': '0xfc00707f'} -vwredsum_vs : {'encoding': '110001-----------000-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc4000057', 'mask': '0xfc00707f'} -vadd_vi : {'encoding': '000000-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x3057', 'mask': '0xfc00707f'} -vrsub_vi : {'encoding': '000011-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xc003057', 'mask': '0xfc00707f'} -vand_vi : {'encoding': '001001-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x24003057', 'mask': '0xfc00707f'} -vor_vi : {'encoding': '001010-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x28003057', 'mask': '0xfc00707f'} -vxor_vi : {'encoding': '001011-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x2c003057', 'mask': '0xfc00707f'} -vrgather_vi : {'encoding': '001100-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x30003057', 'mask': '0xfc00707f'} -vslideup_vi : {'encoding': '001110-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x38003057', 'mask': '0xfc00707f'} -vslidedown_vi : {'encoding': '001111-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x3c003057', 'mask': '0xfc00707f'} -vadc_vim : {'encoding': '0100000----------011-----1010111', 'variable_fields': ['vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x40003057', 'mask': '0xfe00707f'} -vmadc_vim : {'encoding': '0100010----------011-----1010111', 'variable_fields': ['vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x44003057', 'mask': '0xfe00707f'} -vmadc_vi : {'encoding': '0100011----------011-----1010111', 'variable_fields': ['vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x46003057', 'mask': '0xfe00707f'} -vmerge_vim : {'encoding': '0101110----------011-----1010111', 'variable_fields': ['vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x5c003057', 'mask': '0xfe00707f'} -vmv_v_i : {'encoding': '010111100000-----011-----1010111', 'variable_fields': ['simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x5e003057', 'mask': '0xfff0707f'} -vmseq_vi : {'encoding': '011000-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x60003057', 'mask': '0xfc00707f'} -vmsne_vi : {'encoding': '011001-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x64003057', 'mask': '0xfc00707f'} -vmsleu_vi : {'encoding': '011100-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x70003057', 'mask': '0xfc00707f'} -vmsle_vi : {'encoding': '011101-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x74003057', 'mask': '0xfc00707f'} -vmsgtu_vi : {'encoding': '011110-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x78003057', 'mask': '0xfc00707f'} -vmsgt_vi : {'encoding': '011111-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x7c003057', 'mask': '0xfc00707f'} -vsaddu_vi : {'encoding': '100000-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x80003057', 'mask': '0xfc00707f'} -vsadd_vi : {'encoding': '100001-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x84003057', 'mask': '0xfc00707f'} -vsll_vi : {'encoding': '100101-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0x94003057', 'mask': '0xfc00707f'} -vmv1r_v : {'encoding': '1001111-----00000011-----1010111', 'variable_fields': ['vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x9e003057', 'mask': '0xfe0ff07f'} -vmv2r_v : {'encoding': '1001111-----00001011-----1010111', 'variable_fields': ['vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x9e00b057', 'mask': '0xfe0ff07f'} -vmv4r_v : {'encoding': '1001111-----00011011-----1010111', 'variable_fields': ['vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x9e01b057', 'mask': '0xfe0ff07f'} -vmv8r_v : {'encoding': '1001111-----00111011-----1010111', 'variable_fields': ['vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x9e03b057', 'mask': '0xfe0ff07f'} -vsrl_vi : {'encoding': '101000-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xa0003057', 'mask': '0xfc00707f'} -vsra_vi : {'encoding': '101001-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xa4003057', 'mask': '0xfc00707f'} -vssrl_vi : {'encoding': '101010-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xa8003057', 'mask': '0xfc00707f'} -vssra_vi : {'encoding': '101011-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xac003057', 'mask': '0xfc00707f'} -vnsrl_wi : {'encoding': '101100-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xb0003057', 'mask': '0xfc00707f'} -vnsra_wi : {'encoding': '101101-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xb4003057', 'mask': '0xfc00707f'} -vnclipu_wi : {'encoding': '101110-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xb8003057', 'mask': '0xfc00707f'} -vnclip_wi : {'encoding': '101111-----------011-----1010111', 'variable_fields': ['vm', 'vs2', 'simm5', 'vd'], 'extension': ['rv_v'], 'match': '0xbc003057', 'mask': '0xfc00707f'} -vredsum_vs : {'encoding': '000000-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2057', 'mask': '0xfc00707f'} -vredand_vs : {'encoding': '000001-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4002057', 'mask': '0xfc00707f'} -vredor_vs : {'encoding': '000010-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8002057', 'mask': '0xfc00707f'} -vredxor_vs : {'encoding': '000011-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc002057', 'mask': '0xfc00707f'} -vredminu_vs : {'encoding': '000100-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x10002057', 'mask': '0xfc00707f'} -vredmin_vs : {'encoding': '000101-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x14002057', 'mask': '0xfc00707f'} -vredmaxu_vs : {'encoding': '000110-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x18002057', 'mask': '0xfc00707f'} -vredmax_vs : {'encoding': '000111-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x1c002057', 'mask': '0xfc00707f'} -vaaddu_vv : {'encoding': '001000-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x20002057', 'mask': '0xfc00707f'} -vaadd_vv : {'encoding': '001001-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x24002057', 'mask': '0xfc00707f'} -vasubu_vv : {'encoding': '001010-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x28002057', 'mask': '0xfc00707f'} -vasub_vv : {'encoding': '001011-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2c002057', 'mask': '0xfc00707f'} -vmv_x_s : {'encoding': '0100001-----00000010-----1010111', 'variable_fields': ['vs2', 'rd'], 'extension': ['rv_v'], 'match': '0x42002057', 'mask': '0xfe0ff07f'} -vzext_vf8 : {'encoding': '010010------00010010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48012057', 'mask': '0xfc0ff07f'} -vsext_vf8 : {'encoding': '010010------00011010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x4801a057', 'mask': '0xfc0ff07f'} -vzext_vf4 : {'encoding': '010010------00100010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48022057', 'mask': '0xfc0ff07f'} -vsext_vf4 : {'encoding': '010010------00101010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x4802a057', 'mask': '0xfc0ff07f'} -vzext_vf2 : {'encoding': '010010------00110010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x48032057', 'mask': '0xfc0ff07f'} -vsext_vf2 : {'encoding': '010010------00111010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x4803a057', 'mask': '0xfc0ff07f'} -vcompress_vm : {'encoding': '0101111----------010-----1010111', 'variable_fields': ['vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x5e002057', 'mask': '0xfe00707f'} -vmandn_mm : {'encoding': '011000-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x60002057', 'mask': '0xfc00707f'} -vmand_mm : {'encoding': '011001-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x64002057', 'mask': '0xfc00707f'} -vmor_mm : {'encoding': '011010-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x68002057', 'mask': '0xfc00707f'} -vmxor_mm : {'encoding': '011011-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6c002057', 'mask': '0xfc00707f'} -vmorn_mm : {'encoding': '011100-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x70002057', 'mask': '0xfc00707f'} -vmnand_mm : {'encoding': '011101-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x74002057', 'mask': '0xfc00707f'} -vmnor_mm : {'encoding': '011110-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x78002057', 'mask': '0xfc00707f'} -vmxnor_mm : {'encoding': '011111-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x7c002057', 'mask': '0xfc00707f'} -vmsbf_m : {'encoding': '010100------00001010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x5000a057', 'mask': '0xfc0ff07f'} -vmsof_m : {'encoding': '010100------00010010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x50012057', 'mask': '0xfc0ff07f'} -vmsif_m : {'encoding': '010100------00011010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x5001a057', 'mask': '0xfc0ff07f'} -viota_m : {'encoding': '010100------10000010-----1010111', 'variable_fields': ['vm', 'vs2', 'vd'], 'extension': ['rv_v'], 'match': '0x50082057', 'mask': '0xfc0ff07f'} -vid_v : {'encoding': '010100-0000010001010-----1010111', 'variable_fields': ['vm', 'vd'], 'extension': ['rv_v'], 'match': '0x5008a057', 'mask': '0xfdfff07f'} -vcpop_m : {'encoding': '010000------10000010-----1010111', 'variable_fields': ['vm', 'vs2', 'rd'], 'extension': ['rv_v'], 'match': '0x40082057', 'mask': '0xfc0ff07f'} -vfirst_m : {'encoding': '010000------10001010-----1010111', 'variable_fields': ['vm', 'vs2', 'rd'], 'extension': ['rv_v'], 'match': '0x4008a057', 'mask': '0xfc0ff07f'} -vdivu_vv : {'encoding': '100000-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x80002057', 'mask': '0xfc00707f'} -vdiv_vv : {'encoding': '100001-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x84002057', 'mask': '0xfc00707f'} -vremu_vv : {'encoding': '100010-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x88002057', 'mask': '0xfc00707f'} -vrem_vv : {'encoding': '100011-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8c002057', 'mask': '0xfc00707f'} -vmulhu_vv : {'encoding': '100100-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x90002057', 'mask': '0xfc00707f'} -vmul_vv : {'encoding': '100101-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x94002057', 'mask': '0xfc00707f'} -vmulhsu_vv : {'encoding': '100110-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x98002057', 'mask': '0xfc00707f'} -vmulh_vv : {'encoding': '100111-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0x9c002057', 'mask': '0xfc00707f'} -vmadd_vv : {'encoding': '101001-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa4002057', 'mask': '0xfc00707f'} -vnmsub_vv : {'encoding': '101011-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xac002057', 'mask': '0xfc00707f'} -vmacc_vv : {'encoding': '101101-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb4002057', 'mask': '0xfc00707f'} -vnmsac_vv : {'encoding': '101111-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xbc002057', 'mask': '0xfc00707f'} -vwaddu_vv : {'encoding': '110000-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc0002057', 'mask': '0xfc00707f'} -vwadd_vv : {'encoding': '110001-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc4002057', 'mask': '0xfc00707f'} -vwsubu_vv : {'encoding': '110010-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc8002057', 'mask': '0xfc00707f'} -vwsub_vv : {'encoding': '110011-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xcc002057', 'mask': '0xfc00707f'} -vwaddu_wv : {'encoding': '110100-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd0002057', 'mask': '0xfc00707f'} -vwadd_wv : {'encoding': '110101-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd4002057', 'mask': '0xfc00707f'} -vwsubu_wv : {'encoding': '110110-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd8002057', 'mask': '0xfc00707f'} -vwsub_wv : {'encoding': '110111-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xdc002057', 'mask': '0xfc00707f'} -vwmulu_vv : {'encoding': '111000-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe0002057', 'mask': '0xfc00707f'} -vwmulsu_vv : {'encoding': '111010-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe8002057', 'mask': '0xfc00707f'} -vwmul_vv : {'encoding': '111011-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xec002057', 'mask': '0xfc00707f'} -vwmaccu_vv : {'encoding': '111100-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf0002057', 'mask': '0xfc00707f'} -vwmacc_vv : {'encoding': '111101-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf4002057', 'mask': '0xfc00707f'} -vwmaccsu_vv : {'encoding': '111111-----------010-----1010111', 'variable_fields': ['vm', 'vs2', 'vs1', 'vd'], 'extension': ['rv_v'], 'match': '0xfc002057', 'mask': '0xfc00707f'} -vaaddu_vx : {'encoding': '001000-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x20006057', 'mask': '0xfc00707f'} -vaadd_vx : {'encoding': '001001-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x24006057', 'mask': '0xfc00707f'} -vasubu_vx : {'encoding': '001010-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x28006057', 'mask': '0xfc00707f'} -vasub_vx : {'encoding': '001011-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2c006057', 'mask': '0xfc00707f'} -vmv_s_x : {'encoding': '010000100000-----110-----1010111', 'variable_fields': ['rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x42006057', 'mask': '0xfff0707f'} -vslide1up_vx : {'encoding': '001110-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x38006057', 'mask': '0xfc00707f'} -vslide1down_vx : {'encoding': '001111-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x3c006057', 'mask': '0xfc00707f'} -vdivu_vx : {'encoding': '100000-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x80006057', 'mask': '0xfc00707f'} -vdiv_vx : {'encoding': '100001-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x84006057', 'mask': '0xfc00707f'} -vremu_vx : {'encoding': '100010-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x88006057', 'mask': '0xfc00707f'} -vrem_vx : {'encoding': '100011-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8c006057', 'mask': '0xfc00707f'} -vmulhu_vx : {'encoding': '100100-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x90006057', 'mask': '0xfc00707f'} -vmul_vx : {'encoding': '100101-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x94006057', 'mask': '0xfc00707f'} -vmulhsu_vx : {'encoding': '100110-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x98006057', 'mask': '0xfc00707f'} -vmulh_vx : {'encoding': '100111-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x9c006057', 'mask': '0xfc00707f'} -vmadd_vx : {'encoding': '101001-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa4006057', 'mask': '0xfc00707f'} -vnmsub_vx : {'encoding': '101011-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xac006057', 'mask': '0xfc00707f'} -vmacc_vx : {'encoding': '101101-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xb4006057', 'mask': '0xfc00707f'} -vnmsac_vx : {'encoding': '101111-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xbc006057', 'mask': '0xfc00707f'} -vwaddu_vx : {'encoding': '110000-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc0006057', 'mask': '0xfc00707f'} -vwadd_vx : {'encoding': '110001-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc4006057', 'mask': '0xfc00707f'} -vwsubu_vx : {'encoding': '110010-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc8006057', 'mask': '0xfc00707f'} -vwsub_vx : {'encoding': '110011-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xcc006057', 'mask': '0xfc00707f'} -vwaddu_wx : {'encoding': '110100-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd0006057', 'mask': '0xfc00707f'} -vwadd_wx : {'encoding': '110101-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd4006057', 'mask': '0xfc00707f'} -vwsubu_wx : {'encoding': '110110-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xd8006057', 'mask': '0xfc00707f'} -vwsub_wx : {'encoding': '110111-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xdc006057', 'mask': '0xfc00707f'} -vwmulu_vx : {'encoding': '111000-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe0006057', 'mask': '0xfc00707f'} -vwmulsu_vx : {'encoding': '111010-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe8006057', 'mask': '0xfc00707f'} -vwmul_vx : {'encoding': '111011-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xec006057', 'mask': '0xfc00707f'} -vwmaccu_vx : {'encoding': '111100-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf0006057', 'mask': '0xfc00707f'} -vwmacc_vx : {'encoding': '111101-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf4006057', 'mask': '0xfc00707f'} -vwmaccus_vx : {'encoding': '111110-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xf8006057', 'mask': '0xfc00707f'} -vwmaccsu_vx : {'encoding': '111111-----------110-----1010111', 'variable_fields': ['vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xfc006057', 'mask': '0xfc00707f'} -vamoswapei8_v : {'encoding': '00001------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x800002f', 'mask': '0xf800707f'} -vamoaddei8_v : {'encoding': '00000------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2f', 'mask': '0xf800707f'} -vamoxorei8_v : {'encoding': '00100------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2000002f', 'mask': '0xf800707f'} -vamoandei8_v : {'encoding': '01100------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6000002f', 'mask': '0xf800707f'} -vamoorei8_v : {'encoding': '01000------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4000002f', 'mask': '0xf800707f'} -vamominei8_v : {'encoding': '10000------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8000002f', 'mask': '0xf800707f'} -vamomaxei8_v : {'encoding': '10100------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa000002f', 'mask': '0xf800707f'} -vamominuei8_v : {'encoding': '11000------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc000002f', 'mask': '0xf800707f'} -vamomaxuei8_v : {'encoding': '11100------------000-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe000002f', 'mask': '0xf800707f'} -vamoswapei16_v : {'encoding': '00001------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x800502f', 'mask': '0xf800707f'} -vamoaddei16_v : {'encoding': '00000------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x502f', 'mask': '0xf800707f'} -vamoxorei16_v : {'encoding': '00100------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2000502f', 'mask': '0xf800707f'} -vamoandei16_v : {'encoding': '01100------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6000502f', 'mask': '0xf800707f'} -vamoorei16_v : {'encoding': '01000------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4000502f', 'mask': '0xf800707f'} -vamominei16_v : {'encoding': '10000------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8000502f', 'mask': '0xf800707f'} -vamomaxei16_v : {'encoding': '10100------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa000502f', 'mask': '0xf800707f'} -vamominuei16_v : {'encoding': '11000------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc000502f', 'mask': '0xf800707f'} -vamomaxuei16_v : {'encoding': '11100------------101-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe000502f', 'mask': '0xf800707f'} -vamoswapei32_v : {'encoding': '00001------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x800602f', 'mask': '0xf800707f'} -vamoaddei32_v : {'encoding': '00000------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x602f', 'mask': '0xf800707f'} -vamoxorei32_v : {'encoding': '00100------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2000602f', 'mask': '0xf800707f'} -vamoandei32_v : {'encoding': '01100------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6000602f', 'mask': '0xf800707f'} -vamoorei32_v : {'encoding': '01000------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4000602f', 'mask': '0xf800707f'} -vamominei32_v : {'encoding': '10000------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8000602f', 'mask': '0xf800707f'} -vamomaxei32_v : {'encoding': '10100------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa000602f', 'mask': '0xf800707f'} -vamominuei32_v : {'encoding': '11000------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc000602f', 'mask': '0xf800707f'} -vamomaxuei32_v : {'encoding': '11100------------110-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe000602f', 'mask': '0xf800707f'} -vamoswapei64_v : {'encoding': '00001------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x800702f', 'mask': '0xf800707f'} -vamoaddei64_v : {'encoding': '00000------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x702f', 'mask': '0xf800707f'} -vamoxorei64_v : {'encoding': '00100------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x2000702f', 'mask': '0xf800707f'} -vamoandei64_v : {'encoding': '01100------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x6000702f', 'mask': '0xf800707f'} -vamoorei64_v : {'encoding': '01000------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x4000702f', 'mask': '0xf800707f'} -vamominei64_v : {'encoding': '10000------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0x8000702f', 'mask': '0xf800707f'} -vamomaxei64_v : {'encoding': '10100------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xa000702f', 'mask': '0xf800707f'} -vamominuei64_v : {'encoding': '11000------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xc000702f', 'mask': '0xf800707f'} -vamomaxuei64_v : {'encoding': '11100------------111-----0101111', 'variable_fields': ['wd', 'vm', 'vs2', 'rs1', 'vd'], 'extension': ['rv_v'], 'match': '0xe000702f', 'mask': '0xf800707f'} -c_lq : {'encoding': '----------------001-----------00', 'variable_fields': ['rd_p', 'rs1_p', 'c_uimm9lo', 'c_uimm9hi'], 'extension': ['rv128_c'], 'match': '0x2000', 'mask': '0xe003'} -c_ld : {'encoding': '----------------011-----------00', 'variable_fields': ['rd_p', 'rs1_p', 'c_uimm8lo', 'c_uimm8hi'], 'extension': ['rv64_c'], 'match': '0x6000', 'mask': '0xe003'} -c_sq : {'encoding': '----------------101-----------00', 'variable_fields': ['rs1_p', 'rs2_p', 'c_uimm9hi', 'c_uimm9lo'], 'extension': ['rv128_c'], 'match': '0xa000', 'mask': '0xe003'} -c_sd : {'encoding': '----------------111-----------00', 'variable_fields': ['rs1_p', 'rs2_p', 'c_uimm8hi', 'c_uimm8lo'], 'extension': ['rv64_c'], 'match': '0xe000', 'mask': '0xe003'} -c_addiw : {'encoding': '----------------001-----------01', 'variable_fields': ['rd_rs1', 'c_imm6lo', 'c_imm6hi'], 'extension': ['rv64_c'], 'match': '0x2001', 'mask': '0xe003'} -c_lqsp : {'encoding': '----------------001-----------10', 'variable_fields': ['rd', 'c_uimm10sphi', 'c_uimm10splo'], 'extension': ['rv128_c'], 'match': '0x2002', 'mask': '0xe003'} -c_ldsp : {'encoding': '----------------011-----------10', 'variable_fields': ['rd_n0', 'c_uimm9sphi', 'c_uimm9splo'], 'extension': ['rv64_c'], 'match': '0x6002', 'mask': '0xe003'} -c_sqsp : {'encoding': '----------------101-----------10', 'variable_fields': ['c_rs2', 'c_uimm10sp_s'], 'extension': ['rv128_c'], 'match': '0xa002', 'mask': '0xe003'} -c_sdsp : {'encoding': '----------------111-----------10', 'variable_fields': ['c_rs2', 'c_uimm9sp_s'], 'extension': ['rv64_c'], 'match': '0xe002', 'mask': '0xe003'} -grev : {'encoding': '0110100----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x68005033', 'mask': '0xfe00707f'} -gorc : {'encoding': '0010100----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x28005033', 'mask': '0xfe00707f'} -shfl : {'encoding': '0000100----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x8001033', 'mask': '0xfe00707f'} -unshfl : {'encoding': '0000100----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x8005033', 'mask': '0xfe00707f'} -xperm4 : {'encoding': '0010100----------010-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x28002033', 'mask': '0xfe00707f'} -xperm8 : {'encoding': '0010100----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x28004033', 'mask': '0xfe00707f'} -xperm16 : {'encoding': '0010100----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x28006033', 'mask': '0xfe00707f'} -packu : {'encoding': '0100100----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbp'], 'match': '0x48004033', 'mask': '0xfe00707f'} -fence_i : {'encoding': '-----------------001-----0001111', 'variable_fields': ['imm12', 'rs1', 'rd'], 'extension': ['rv_zifencei'], 'match': '0x100f', 'mask': '0x707f'} -crc32_b : {'encoding': '011000010000-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbr'], 'match': '0x61001013', 'mask': '0xfff0707f'} -crc32_h : {'encoding': '011000010001-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbr'], 'match': '0x61101013', 'mask': '0xfff0707f'} -crc32_w : {'encoding': '011000010010-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbr'], 'match': '0x61201013', 'mask': '0xfff0707f'} -crc32c_b : {'encoding': '011000011000-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbr'], 'match': '0x61801013', 'mask': '0xfff0707f'} -crc32c_h : {'encoding': '011000011001-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbr'], 'match': '0x61901013', 'mask': '0xfff0707f'} -crc32c_w : {'encoding': '011000011010-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbr'], 'match': '0x61a01013', 'mask': '0xfff0707f'} -c_srli : {'encoding': '----------------100-00--------01', 'variable_fields': ['rd_rs1_p', 'c_nzuimm6lo', 'c_nzuimm6hi'], 'extension': ['rv64_c'], 'match': '0x8001', 'mask': '0xec03'} -c_srai : {'encoding': '----------------100-01--------01', 'variable_fields': ['rd_rs1_p', 'c_nzuimm6lo', 'c_nzuimm6hi'], 'extension': ['rv64_c'], 'match': '0x8401', 'mask': '0xec03'} -c_subw : {'encoding': '----------------100111---00---01', 'variable_fields': ['rd_rs1_p', 'rs2_p'], 'extension': ['rv64_c'], 'match': '0x9c01', 'mask': '0xfc63'} -c_addw : {'encoding': '----------------100111---01---01', 'variable_fields': ['rd_rs1_p', 'rs2_p'], 'extension': ['rv64_c'], 'match': '0x9c21', 'mask': '0xfc63'} -c_slli : {'encoding': '----------------000-----------10', 'variable_fields': ['rd_rs1_n0', 'c_nzuimm6hi', 'c_nzuimm6lo'], 'extension': ['rv64_c'], 'match': '0x2', 'mask': '0xe003'} -c_fld : {'encoding': '----------------001-----------00', 'variable_fields': ['rd_p', 'rs1_p', 'c_uimm8lo', 'c_uimm8hi'], 'extension': ['rv_c_d'], 'match': '0x2000', 'mask': '0xe003'} -c_fsd : {'encoding': '----------------101-----------00', 'variable_fields': ['rs1_p', 'rs2_p', 'c_uimm8lo', 'c_uimm8hi'], 'extension': ['rv_c_d'], 'match': '0xa000', 'mask': '0xe003'} -c_fldsp : {'encoding': '----------------001-----------10', 'variable_fields': ['rd', 'c_uimm9sphi', 'c_uimm9splo'], 'extension': ['rv_c_d'], 'match': '0x2002', 'mask': '0xe003'} -c_fsdsp : {'encoding': '----------------101-----------10', 'variable_fields': ['c_rs2', 'c_uimm9sp_s'], 'extension': ['rv_c_d'], 'match': '0xa002', 'mask': '0xe003'} -flq : {'encoding': '-----------------100-----0000111', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_q'], 'match': '0x4007', 'mask': '0x707f'} -fsq : {'encoding': '-----------------100-----0100111', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv_q'], 'match': '0x4027', 'mask': '0x707f'} -fmadd_q : {'encoding': '-----11------------------1000011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_q'], 'match': '0x6000043', 'mask': '0x600007f'} -fmsub_q : {'encoding': '-----11------------------1000111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_q'], 'match': '0x6000047', 'mask': '0x600007f'} -fnmsub_q : {'encoding': '-----11------------------1001011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_q'], 'match': '0x600004b', 'mask': '0x600007f'} -fnmadd_q : {'encoding': '-----11------------------1001111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_q'], 'match': '0x600004f', 'mask': '0x600007f'} -fadd_q : {'encoding': '0000011------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_q'], 'match': '0x6000053', 'mask': '0xfe00007f'} -fsub_q : {'encoding': '0000111------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_q'], 'match': '0xe000053', 'mask': '0xfe00007f'} -fmul_q : {'encoding': '0001011------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_q'], 'match': '0x16000053', 'mask': '0xfe00007f'} -fdiv_q : {'encoding': '0001111------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_q'], 'match': '0x1e000053', 'mask': '0xfe00007f'} -fsqrt_q : {'encoding': '010111100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0x5e000053', 'mask': '0xfff0007f'} -fsgnj_q : {'encoding': '0010011----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0x26000053', 'mask': '0xfe00707f'} -fsgnjn_q : {'encoding': '0010011----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0x26001053', 'mask': '0xfe00707f'} -fsgnjx_q : {'encoding': '0010011----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0x26002053', 'mask': '0xfe00707f'} -fmin_q : {'encoding': '0010111----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0x2e000053', 'mask': '0xfe00707f'} -fmax_q : {'encoding': '0010111----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0x2e001053', 'mask': '0xfe00707f'} -fcvt_s_q : {'encoding': '010000000011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0x40300053', 'mask': '0xfff0007f'} -fcvt_q_s : {'encoding': '010001100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0x46000053', 'mask': '0xfff0007f'} -fcvt_d_q : {'encoding': '010000100011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0x42300053', 'mask': '0xfff0007f'} -fcvt_q_d : {'encoding': '010001100001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0x46100053', 'mask': '0xfff0007f'} -feq_q : {'encoding': '1010011----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0xa6002053', 'mask': '0xfe00707f'} -flt_q : {'encoding': '1010011----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0xa6001053', 'mask': '0xfe00707f'} -fle_q : {'encoding': '1010011----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_q'], 'match': '0xa6000053', 'mask': '0xfe00707f'} -fclass_q : {'encoding': '111001100000-----001-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_q'], 'match': '0xe6001053', 'mask': '0xfff0707f'} -fcvt_w_q : {'encoding': '110001100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0xc6000053', 'mask': '0xfff0007f'} -fcvt_wu_q : {'encoding': '110001100001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0xc6100053', 'mask': '0xfff0007f'} -fcvt_q_w : {'encoding': '110101100000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0xd6000053', 'mask': '0xfff0007f'} -fcvt_q_wu : {'encoding': '110101100001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_q'], 'match': '0xd6100053', 'mask': '0xfff0007f'} -hlv_wu : {'encoding': '011010000001-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_h'], 'match': '0x68104073', 'mask': '0xfff0707f'} -hlv_d : {'encoding': '011011000000-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_h'], 'match': '0x6c004073', 'mask': '0xfff0707f'} -hsv_d : {'encoding': '0110111----------100000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv64_h'], 'match': '0x6e004073', 'mask': '0xfe007fff'} -hfence_vvma : {'encoding': '0010001----------000000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_h'], 'match': '0x22000073', 'mask': '0xfe007fff'} -hfence_gvma : {'encoding': '0110001----------000000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_h'], 'match': '0x62000073', 'mask': '0xfe007fff'} -hlv_b : {'encoding': '011000000000-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_h'], 'match': '0x60004073', 'mask': '0xfff0707f'} -hlv_bu : {'encoding': '011000000001-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_h'], 'match': '0x60104073', 'mask': '0xfff0707f'} -hlv_h : {'encoding': '011001000000-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_h'], 'match': '0x64004073', 'mask': '0xfff0707f'} -hlv_hu : {'encoding': '011001000001-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_h'], 'match': '0x64104073', 'mask': '0xfff0707f'} -hlvx_hu : {'encoding': '011001000011-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_h'], 'match': '0x64304073', 'mask': '0xfff0707f'} -hlv_w : {'encoding': '011010000000-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_h'], 'match': '0x68004073', 'mask': '0xfff0707f'} -hlvx_wu : {'encoding': '011010000011-----100-----1110011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_h'], 'match': '0x68304073', 'mask': '0xfff0707f'} -hsv_b : {'encoding': '0110001----------100000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_h'], 'match': '0x62004073', 'mask': '0xfe007fff'} -hsv_h : {'encoding': '0110011----------100000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_h'], 'match': '0x66004073', 'mask': '0xfe007fff'} -hsv_w : {'encoding': '0110101----------100000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_h'], 'match': '0x6a004073', 'mask': '0xfe007fff'} -aes32dsmi : {'encoding': '--10111----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'bs'], 'extension': ['rv32_zknd'], 'match': '0x2e000033', 'mask': '0x3e00707f'} -aes32dsi : {'encoding': '--10101----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'bs'], 'extension': ['rv32_zknd'], 'match': '0x2a000033', 'mask': '0x3e00707f'} -fslw : {'encoding': '-----10----------001-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3'], 'extension': ['rv64_zbt'], 'match': '0x400103b', 'mask': '0x600707f'} -fsrw : {'encoding': '-----10----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3'], 'extension': ['rv64_zbt'], 'match': '0x400503b', 'mask': '0x600707f'} -fsriw : {'encoding': '-----10----------101-----0011011', 'variable_fields': ['rd', 'rs1', 'rs3', 'shamtw'], 'extension': ['rv64_zbt'], 'match': '0x400501b', 'mask': '0x600707f'} -fsri : {'encoding': '-----1-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'rs3', 'shamt'], 'extension': ['rv64_zbt'], 'match': '0x4005013', 'mask': '0x400707f'} -custom0 : {'encoding': '-----------------000-----0001011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0xb', 'mask': '0x707f'} -custom0_rs1 : {'encoding': '-----------------010-----0001011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x200b', 'mask': '0x707f'} -custom0_rs1_rs2 : {'encoding': '-----------------011-----0001011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x300b', 'mask': '0x707f'} -custom0_rd : {'encoding': '-----------------100-----0001011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x400b', 'mask': '0x707f'} -custom0_rd_rs1 : {'encoding': '-----------------110-----0001011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x600b', 'mask': '0x707f'} -custom0_rd_rs1_rs2 : {'encoding': '-----------------111-----0001011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x700b', 'mask': '0x707f'} -custom1 : {'encoding': '-----------------000-----0101011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x2b', 'mask': '0x707f'} -custom1_rs1 : {'encoding': '-----------------010-----0101011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x202b', 'mask': '0x707f'} -custom1_rs1_rs2 : {'encoding': '-----------------011-----0101011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x302b', 'mask': '0x707f'} -custom1_rd : {'encoding': '-----------------100-----0101011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x402b', 'mask': '0x707f'} -custom1_rd_rs1 : {'encoding': '-----------------110-----0101011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x602b', 'mask': '0x707f'} -custom1_rd_rs1_rs2 : {'encoding': '-----------------111-----0101011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x702b', 'mask': '0x707f'} -custom2 : {'encoding': '-----------------000-----1011011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x5b', 'mask': '0x707f'} -custom2_rs1 : {'encoding': '-----------------010-----1011011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x205b', 'mask': '0x707f'} -custom2_rs1_rs2 : {'encoding': '-----------------011-----1011011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x305b', 'mask': '0x707f'} -custom2_rd : {'encoding': '-----------------100-----1011011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x405b', 'mask': '0x707f'} -custom2_rd_rs1 : {'encoding': '-----------------110-----1011011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x605b', 'mask': '0x707f'} -custom2_rd_rs1_rs2 : {'encoding': '-----------------111-----1011011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x705b', 'mask': '0x707f'} -custom3 : {'encoding': '-----------------000-----1111011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x7b', 'mask': '0x707f'} -custom3_rs1 : {'encoding': '-----------------010-----1111011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x207b', 'mask': '0x707f'} -custom3_rs1_rs2 : {'encoding': '-----------------011-----1111011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x307b', 'mask': '0x707f'} -custom3_rd : {'encoding': '-----------------100-----1111011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x407b', 'mask': '0x707f'} -custom3_rd_rs1 : {'encoding': '-----------------110-----1111011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x607b', 'mask': '0x707f'} -custom3_rd_rs1_rs2 : {'encoding': '-----------------111-----1111011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_custom'], 'match': '0x707b', 'mask': '0x707f'} -sm4ed : {'encoding': '--11000----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'bs'], 'extension': ['rv_zksed'], 'match': '0x30000033', 'mask': '0x3e00707f'} -sm4ks : {'encoding': '--11010----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2', 'bs'], 'extension': ['rv_zksed'], 'match': '0x34000033', 'mask': '0x3e00707f'} -slo : {'encoding': '0010000----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_b'], 'match': '0x20001033', 'mask': '0xfe00707f'} -sro : {'encoding': '0010000----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_b'], 'match': '0x20005033', 'mask': '0xfe00707f'} -sloi : {'encoding': '001000-----------001-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv_b'], 'match': '0x20001013', 'mask': '0xfc00707f'} -sroi : {'encoding': '001000-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv_b'], 'match': '0x20005013', 'mask': '0xfc00707f'} -lui : {'encoding': '-------------------------0110111', 'variable_fields': ['rd', 'imm20'], 'extension': ['rv_i'], 'match': '0x37', 'mask': '0x7f'} -auipc : {'encoding': '-------------------------0010111', 'variable_fields': ['rd', 'imm20'], 'extension': ['rv_i'], 'match': '0x17', 'mask': '0x7f'} -jal : {'encoding': '-------------------------1101111', 'variable_fields': ['rd', 'jimm20'], 'extension': ['rv_i'], 'match': '0x6f', 'mask': '0x7f'} -jalr : {'encoding': '-----------------000-----1100111', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x67', 'mask': '0x707f'} -beq : {'encoding': '-----------------000-----1100011', 'variable_fields': ['bimm12hi', 'rs1', 'rs2', 'bimm12lo'], 'extension': ['rv_i'], 'match': '0x63', 'mask': '0x707f'} -bne : {'encoding': '-----------------001-----1100011', 'variable_fields': ['bimm12hi', 'rs1', 'rs2', 'bimm12lo'], 'extension': ['rv_i'], 'match': '0x1063', 'mask': '0x707f'} -blt : {'encoding': '-----------------100-----1100011', 'variable_fields': ['bimm12hi', 'rs1', 'rs2', 'bimm12lo'], 'extension': ['rv_i'], 'match': '0x4063', 'mask': '0x707f'} -bge : {'encoding': '-----------------101-----1100011', 'variable_fields': ['bimm12hi', 'rs1', 'rs2', 'bimm12lo'], 'extension': ['rv_i'], 'match': '0x5063', 'mask': '0x707f'} -bltu : {'encoding': '-----------------110-----1100011', 'variable_fields': ['bimm12hi', 'rs1', 'rs2', 'bimm12lo'], 'extension': ['rv_i'], 'match': '0x6063', 'mask': '0x707f'} -bgeu : {'encoding': '-----------------111-----1100011', 'variable_fields': ['bimm12hi', 'rs1', 'rs2', 'bimm12lo'], 'extension': ['rv_i'], 'match': '0x7063', 'mask': '0x707f'} -lb : {'encoding': '-----------------000-----0000011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x3', 'mask': '0x707f'} -lh : {'encoding': '-----------------001-----0000011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x1003', 'mask': '0x707f'} -lw : {'encoding': '-----------------010-----0000011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x2003', 'mask': '0x707f'} -lbu : {'encoding': '-----------------100-----0000011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x4003', 'mask': '0x707f'} -lhu : {'encoding': '-----------------101-----0000011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x5003', 'mask': '0x707f'} -sb : {'encoding': '-----------------000-----0100011', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv_i'], 'match': '0x23', 'mask': '0x707f'} -sh : {'encoding': '-----------------001-----0100011', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv_i'], 'match': '0x1023', 'mask': '0x707f'} -sw : {'encoding': '-----------------010-----0100011', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv_i'], 'match': '0x2023', 'mask': '0x707f'} -addi : {'encoding': '-----------------000-----0010011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x13', 'mask': '0x707f'} -slti : {'encoding': '-----------------010-----0010011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x2013', 'mask': '0x707f'} -sltiu : {'encoding': '-----------------011-----0010011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x3013', 'mask': '0x707f'} -xori : {'encoding': '-----------------100-----0010011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x4013', 'mask': '0x707f'} -ori : {'encoding': '-----------------110-----0010011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x6013', 'mask': '0x707f'} -andi : {'encoding': '-----------------111-----0010011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_i'], 'match': '0x7013', 'mask': '0x707f'} -add : {'encoding': '0000000----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x33', 'mask': '0xfe00707f'} -sub : {'encoding': '0100000----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x40000033', 'mask': '0xfe00707f'} -sll : {'encoding': '0000000----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x1033', 'mask': '0xfe00707f'} -slt : {'encoding': '0000000----------010-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x2033', 'mask': '0xfe00707f'} -sltu : {'encoding': '0000000----------011-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x3033', 'mask': '0xfe00707f'} -xor : {'encoding': '0000000----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x4033', 'mask': '0xfe00707f'} -srl : {'encoding': '0000000----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x5033', 'mask': '0xfe00707f'} -sra : {'encoding': '0100000----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x40005033', 'mask': '0xfe00707f'} -or : {'encoding': '0000000----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x6033', 'mask': '0xfe00707f'} -and : {'encoding': '0000000----------111-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_i'], 'match': '0x7033', 'mask': '0xfe00707f'} -fence : {'encoding': '-----------------000-----0001111', 'variable_fields': ['fm', 'pred', 'succ', 'rs1', 'rd'], 'extension': ['rv_i'], 'match': '0xf', 'mask': '0x707f'} -ecall : {'encoding': '00000000000000000000000001110011', 'variable_fields': [], 'extension': ['rv_i'], 'match': '0x73', 'mask': '0xffffffff'} -ebreak : {'encoding': '00000000000100000000000001110011', 'variable_fields': [], 'extension': ['rv_i'], 'match': '0x100073', 'mask': '0xffffffff'} -andn : {'encoding': '0100000----------111-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0x40007033', 'mask': '0xfe00707f'} -orn : {'encoding': '0100000----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0x40006033', 'mask': '0xfe00707f'} -xnor : {'encoding': '0100000----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0x40004033', 'mask': '0xfe00707f'} -clz : {'encoding': '011000000000-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbb'], 'match': '0x60001013', 'mask': '0xfff0707f'} -ctz : {'encoding': '011000000001-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbb'], 'match': '0x60101013', 'mask': '0xfff0707f'} -cpop : {'encoding': '011000000010-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbb'], 'match': '0x60201013', 'mask': '0xfff0707f'} -max : {'encoding': '0000101----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0xa006033', 'mask': '0xfe00707f'} -maxu : {'encoding': '0000101----------111-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0xa007033', 'mask': '0xfe00707f'} -min : {'encoding': '0000101----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0xa004033', 'mask': '0xfe00707f'} -minu : {'encoding': '0000101----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0xa005033', 'mask': '0xfe00707f'} -sext_b : {'encoding': '011000000100-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbb'], 'match': '0x60401013', 'mask': '0xfff0707f'} -sext_h : {'encoding': '011000000101-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_zbb'], 'match': '0x60501013', 'mask': '0xfff0707f'} -rol : {'encoding': '0110000----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0x60001033', 'mask': '0xfe00707f'} -ror : {'encoding': '0110000----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbb'], 'match': '0x60005033', 'mask': '0xfe00707f'} -bfpw : {'encoding': '0100100----------111-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbf'], 'match': '0x4800703b', 'mask': '0xfe00707f'} -mul : {'encoding': '0000001----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2000033', 'mask': '0xfe00707f'} -mulh : {'encoding': '0000001----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2001033', 'mask': '0xfe00707f'} -mulhsu : {'encoding': '0000001----------010-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2002033', 'mask': '0xfe00707f'} -mulhu : {'encoding': '0000001----------011-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2003033', 'mask': '0xfe00707f'} -div : {'encoding': '0000001----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2004033', 'mask': '0xfe00707f'} -divu : {'encoding': '0000001----------101-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2005033', 'mask': '0xfe00707f'} -rem : {'encoding': '0000001----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2006033', 'mask': '0xfe00707f'} -remu : {'encoding': '0000001----------111-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_m'], 'match': '0x2007033', 'mask': '0xfe00707f'} -aes64esm : {'encoding': '0011011----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zkne'], 'match': '0x36000033', 'mask': '0xfe00707f'} -aes64es : {'encoding': '0011001----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zkne'], 'match': '0x32000033', 'mask': '0xfe00707f'} -bcompress : {'encoding': '0000100----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbe'], 'match': '0x8006033', 'mask': '0xfe00707f'} -bdecompress : {'encoding': '0100100----------110-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbe'], 'match': '0x48006033', 'mask': '0xfe00707f'} -pack : {'encoding': '0000100----------100-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbe'], 'match': '0x8004033', 'mask': '0xfe00707f'} -packh : {'encoding': '0000100----------111-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbe'], 'match': '0x8007033', 'mask': '0xfe00707f'} -c_jal : {'encoding': '----------------001-----------01', 'variable_fields': ['c_imm12'], 'extension': ['rv32_c'], 'match': '0x2001', 'mask': '0xe003'} -clmul : {'encoding': '0000101----------001-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbc'], 'match': '0xa001033', 'mask': '0xfe00707f'} -clmulr : {'encoding': '0000101----------010-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbc'], 'match': '0xa002033', 'mask': '0xfe00707f'} -clmulh : {'encoding': '0000101----------011-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_zbc'], 'match': '0xa003033', 'mask': '0xfe00707f'} -cbo_clean : {'encoding': '000000000001-----010000000001111', 'variable_fields': ['rs1'], 'extension': ['rv_zicbo'], 'match': '0x10200f', 'mask': '0xfff07fff'} -cbo_flush : {'encoding': '000000000010-----010000000001111', 'variable_fields': ['rs1'], 'extension': ['rv_zicbo'], 'match': '0x20200f', 'mask': '0xfff07fff'} -cbo_inval : {'encoding': '000000000000-----010000000001111', 'variable_fields': ['rs1'], 'extension': ['rv_zicbo'], 'match': '0x200f', 'mask': '0xfff07fff'} -cbo_zero : {'encoding': '000000000100-----010000000001111', 'variable_fields': ['rs1'], 'extension': ['rv_zicbo'], 'match': '0x40200f', 'mask': '0xfff07fff'} -csrrw : {'encoding': '-----------------001-----1110011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_zicsr'], 'match': '0x1073', 'mask': '0x707f'} -csrrs : {'encoding': '-----------------010-----1110011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_zicsr'], 'match': '0x2073', 'mask': '0x707f'} -csrrc : {'encoding': '-----------------011-----1110011', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_zicsr'], 'match': '0x3073', 'mask': '0x707f'} -csrrwi : {'encoding': '-----------------101-----1110011', 'variable_fields': ['rd', 'imm12', 'zimm'], 'extension': ['rv_zicsr'], 'match': '0x5073', 'mask': '0x707f'} -csrrsi : {'encoding': '-----------------110-----1110011', 'variable_fields': ['rd', 'imm12', 'zimm'], 'extension': ['rv_zicsr'], 'match': '0x6073', 'mask': '0x707f'} -csrrci : {'encoding': '-----------------111-----1110011', 'variable_fields': ['rd', 'imm12', 'zimm'], 'extension': ['rv_zicsr'], 'match': '0x7073', 'mask': '0x707f'} -crc32_d : {'encoding': '011000010011-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zbr'], 'match': '0x61301013', 'mask': '0xfff0707f'} -crc32c_d : {'encoding': '011000011011-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zbr'], 'match': '0x61b01013', 'mask': '0xfff0707f'} -mret : {'encoding': '00110000001000000000000001110011', 'variable_fields': [], 'extension': ['rv_system'], 'match': '0x30200073', 'mask': '0xffffffff'} -dret : {'encoding': '01111011001000000000000001110011', 'variable_fields': [], 'extension': ['rv_system'], 'match': '0x7b200073', 'mask': '0xffffffff'} -wfi : {'encoding': '00010000010100000000000001110011', 'variable_fields': [], 'extension': ['rv_system'], 'match': '0x10500073', 'mask': '0xffffffff'} -flw : {'encoding': '-----------------010-----0000111', 'variable_fields': ['rd', 'rs1', 'imm12'], 'extension': ['rv_f'], 'match': '0x2007', 'mask': '0x707f'} -fsw : {'encoding': '-----------------010-----0100111', 'variable_fields': ['imm12hi', 'rs1', 'rs2', 'imm12lo'], 'extension': ['rv_f'], 'match': '0x2027', 'mask': '0x707f'} -fmadd_s : {'encoding': '-----00------------------1000011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_f'], 'match': '0x43', 'mask': '0x600007f'} -fmsub_s : {'encoding': '-----00------------------1000111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_f'], 'match': '0x47', 'mask': '0x600007f'} -fnmsub_s : {'encoding': '-----00------------------1001011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_f'], 'match': '0x4b', 'mask': '0x600007f'} -fnmadd_s : {'encoding': '-----00------------------1001111', 'variable_fields': ['rd', 'rs1', 'rs2', 'rs3', 'rm'], 'extension': ['rv_f'], 'match': '0x4f', 'mask': '0x600007f'} -fadd_s : {'encoding': '0000000------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_f'], 'match': '0x53', 'mask': '0xfe00007f'} -fsub_s : {'encoding': '0000100------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_f'], 'match': '0x8000053', 'mask': '0xfe00007f'} -fmul_s : {'encoding': '0001000------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_f'], 'match': '0x10000053', 'mask': '0xfe00007f'} -fdiv_s : {'encoding': '0001100------------------1010011', 'variable_fields': ['rd', 'rs1', 'rs2', 'rm'], 'extension': ['rv_f'], 'match': '0x18000053', 'mask': '0xfe00007f'} -fsqrt_s : {'encoding': '010110000000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_f'], 'match': '0x58000053', 'mask': '0xfff0007f'} -fsgnj_s : {'encoding': '0010000----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0x20000053', 'mask': '0xfe00707f'} -fsgnjn_s : {'encoding': '0010000----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0x20001053', 'mask': '0xfe00707f'} -fsgnjx_s : {'encoding': '0010000----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0x20002053', 'mask': '0xfe00707f'} -fmin_s : {'encoding': '0010100----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0x28000053', 'mask': '0xfe00707f'} -fmax_s : {'encoding': '0010100----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0x28001053', 'mask': '0xfe00707f'} -fcvt_w_s : {'encoding': '110000000000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_f'], 'match': '0xc0000053', 'mask': '0xfff0007f'} -fcvt_wu_s : {'encoding': '110000000001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_f'], 'match': '0xc0100053', 'mask': '0xfff0007f'} -fmv_x_w : {'encoding': '111000000000-----000-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_f'], 'match': '0xe0000053', 'mask': '0xfff0707f'} -feq_s : {'encoding': '1010000----------010-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0xa0002053', 'mask': '0xfe00707f'} -flt_s : {'encoding': '1010000----------001-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0xa0001053', 'mask': '0xfe00707f'} -fle_s : {'encoding': '1010000----------000-----1010011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv_f'], 'match': '0xa0000053', 'mask': '0xfe00707f'} -fclass_s : {'encoding': '111000000000-----001-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_f'], 'match': '0xe0001053', 'mask': '0xfff0707f'} -fcvt_s_w : {'encoding': '110100000000-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_f'], 'match': '0xd0000053', 'mask': '0xfff0007f'} -fcvt_s_wu : {'encoding': '110100000001-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv_f'], 'match': '0xd0100053', 'mask': '0xfff0007f'} -fmv_w_x : {'encoding': '111100000000-----000-----1010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv_f'], 'match': '0xf0000053', 'mask': '0xfff0707f'} -grevi : {'encoding': '011010-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zbp'], 'match': '0x68005013', 'mask': '0xfc00707f'} -gorci : {'encoding': '001010-----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamt'], 'extension': ['rv64_zbp'], 'match': '0x28005013', 'mask': '0xfc00707f'} -shfli : {'encoding': '0000100----------001-----0010011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_zbp'], 'match': '0x8001013', 'mask': '0xfe00707f'} -unshfli : {'encoding': '0000100----------101-----0010011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_zbp'], 'match': '0x8005013', 'mask': '0xfe00707f'} -packuw : {'encoding': '0100100----------100-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbp'], 'match': '0x4800403b', 'mask': '0xfe00707f'} -gorcw : {'encoding': '0010100----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbp'], 'match': '0x2800503b', 'mask': '0xfe00707f'} -grevw : {'encoding': '0110100----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbp'], 'match': '0x6800503b', 'mask': '0xfe00707f'} -gorciw : {'encoding': '0010100----------101-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_zbp'], 'match': '0x2800501b', 'mask': '0xfe00707f'} -greviw : {'encoding': '0110100----------101-----0011011', 'variable_fields': ['rd', 'rs1', 'shamtw'], 'extension': ['rv64_zbp'], 'match': '0x6800501b', 'mask': '0xfe00707f'} -shflw : {'encoding': '0000100----------001-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbp'], 'match': '0x800103b', 'mask': '0xfe00707f'} -unshflw : {'encoding': '0000100----------101-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbp'], 'match': '0x800503b', 'mask': '0xfe00707f'} -xperm32 : {'encoding': '0010100----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbp'], 'match': '0x28000033', 'mask': '0xfe00707f'} -fcvt_l_q : {'encoding': '110001100010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_q'], 'match': '0xc6200053', 'mask': '0xfff0007f'} -fcvt_lu_q : {'encoding': '110001100011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_q'], 'match': '0xc6300053', 'mask': '0xfff0007f'} -fcvt_q_l : {'encoding': '110101100010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_q'], 'match': '0xd6200053', 'mask': '0xfff0007f'} -fcvt_q_lu : {'encoding': '110101100011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_q'], 'match': '0xd6300053', 'mask': '0xfff0007f'} -lr_w : {'encoding': '00010--00000-----010-----0101111', 'variable_fields': ['rd', 'rs1', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x1000202f', 'mask': '0xf9f0707f'} -sc_w : {'encoding': '00011------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x1800202f', 'mask': '0xf800707f'} -amoswap_w : {'encoding': '00001------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x800202f', 'mask': '0xf800707f'} -amoadd_w : {'encoding': '00000------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x202f', 'mask': '0xf800707f'} -amoxor_w : {'encoding': '00100------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x2000202f', 'mask': '0xf800707f'} -amoand_w : {'encoding': '01100------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x6000202f', 'mask': '0xf800707f'} -amoor_w : {'encoding': '01000------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x4000202f', 'mask': '0xf800707f'} -amomin_w : {'encoding': '10000------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0x8000202f', 'mask': '0xf800707f'} -amomax_w : {'encoding': '10100------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0xa000202f', 'mask': '0xf800707f'} -amominu_w : {'encoding': '11000------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0xc000202f', 'mask': '0xf800707f'} -amomaxu_w : {'encoding': '11100------------010-----0101111', 'variable_fields': ['rd', 'rs1', 'rs2', 'aq', 'rl'], 'extension': ['rv_a'], 'match': '0xe000202f', 'mask': '0xf800707f'} -fcvt_l_h : {'encoding': '110001000010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_zfh'], 'match': '0xc4200053', 'mask': '0xfff0007f'} -fcvt_lu_h : {'encoding': '110001000011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_zfh'], 'match': '0xc4300053', 'mask': '0xfff0007f'} -fcvt_h_l : {'encoding': '110101000010-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_zfh'], 'match': '0xd4200053', 'mask': '0xfff0007f'} -fcvt_h_lu : {'encoding': '110101000011-------------1010011', 'variable_fields': ['rd', 'rs1', 'rm'], 'extension': ['rv64_zfh'], 'match': '0xd4300053', 'mask': '0xfff0007f'} -bcompressw : {'encoding': '0000100----------110-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbe'], 'match': '0x800603b', 'mask': '0xfe00707f'} -bdecompressw : {'encoding': '0100100----------110-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbe'], 'match': '0x4800603b', 'mask': '0xfe00707f'} -packw : {'encoding': '0000100----------100-----0111011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zbe'], 'match': '0x800403b', 'mask': '0xfe00707f'} -sfence_vma : {'encoding': '0001001----------000000001110011', 'variable_fields': ['rs1', 'rs2'], 'extension': ['rv_s'], 'match': '0x12000073', 'mask': '0xfe007fff'} -sret : {'encoding': '00010000001000000000000001110011', 'variable_fields': [], 'extension': ['rv_s'], 'match': '0x10200073', 'mask': '0xffffffff'} -aes64dsm : {'encoding': '0011111----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zknd'], 'match': '0x3e000033', 'mask': '0xfe00707f'} -aes64ds : {'encoding': '0011101----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zknd'], 'match': '0x3a000033', 'mask': '0xfe00707f'} -aes64ks1i : {'encoding': '00110001---------001-----0010011', 'variable_fields': ['rd', 'rs1', 'rnum'], 'extension': ['rv64_zknd'], 'match': '0x31001013', 'mask': '0xff00707f'} -aes64im : {'encoding': '001100000000-----001-----0010011', 'variable_fields': ['rd', 'rs1'], 'extension': ['rv64_zknd'], 'match': '0x30001013', 'mask': '0xfff0707f'} -aes64ks2 : {'encoding': '0111111----------000-----0110011', 'variable_fields': ['rd', 'rs1', 'rs2'], 'extension': ['rv64_zknd'], 'match': '0x7e000033', 'mask': '0xfe00707f'} diff --git a/riscv_isac/plugins/riscv_opcodes/opcodes-rvv-pseudo b/riscv_isac/plugins/riscv_opcodes/opcodes-rvv-pseudo deleted file mode 100644 index 35cf095..0000000 --- a/riscv_isac/plugins/riscv_opcodes/opcodes-rvv-pseudo +++ /dev/null @@ -1,18 +0,0 @@ -# vmv1r.v, vmv2r.v, vmv4r.v, vmv8r.v -@vmvnfr.v 31..26=0x27 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 - -@vl1r.v 31..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 -@vl2r.v 31..26=1 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 -@vl4r.v 31..26=3 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 -@vl8r.v 31..26=7 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 - -@vle1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 -@vse1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 - -@vfredsum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -@vfwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 - -@vpopc.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 - -@vmornot.mm 31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -@vmandnot.mm 31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 diff --git a/riscv_isac/plugins/riscv_opcodes/parse.py b/riscv_isac/plugins/riscv_opcodes/parse.py deleted file mode 100755 index 7044d6d..0000000 --- a/riscv_isac/plugins/riscv_opcodes/parse.py +++ /dev/null @@ -1,779 +0,0 @@ -#!/usr/bin/env python - -import json -from constants import * -import re -import glob -import os -import pprint -import logging -import collections -import yaml - -pp = pprint.PrettyPrinter(indent=2) -logging.basicConfig(level=logging.INFO, format='%(levelname)s:: %(message)s') - -def process_enc_line(line, ext): - ''' - This function processes each line of the encoding files (rv*). As part of - the processing, the function ensures that the encoding is legal through the - following checks:: - - - there is no over specification (same bits assigned different values) - - there is no under specification (some bits not assigned values) - - bit ranges are in the format hi..lo=val where hi > lo - - value assigned is representable in the bit range - - also checks that the mapping of arguments of an instruction exists in - arg_lut. - - If the above checks pass, then the function returns a tuple of the name and - a dictionary containing basic information of the instruction which includes: - - variables: list of arguments used by the instruction whose mapping - exists in the arg_lut dictionary - - encoding: this contains the 32-bit encoding of the instruction where - '-' is used to represent position of arguments and 1/0 is used to - reprsent the static encoding of the bits - - extension: this field contains the rv* filename from which this - instruction was included - - match: hex value representing the bits that need to match to detect - this instruction - - mask: hex value representin the bits that need to be masked to extract - the value required for matching. - ''' - single_dict = {} - - # fill all bits with don't care. we use '-' to represent don't care - # TODO: hardcoded for 32-bits. - encoding = ['-'] * 32 - - # get the name of instruction by splitting based on the first space - [name, remaining] = line.split(' ', 1) - - # replace dots with underscores as dot doesn't work with C/Sverilog, etc - name = name.replace('.', '_') - - # remove leading whitespaces - remaining = remaining.lstrip() - - # check each field for it's length and overlapping bits - # ex: 1..0=5 will result in an error --> x overlapping bits - temp_instr = ['-'] * 32 - entries = [ - x[0] for x in re.findall( - r'((\d)+\.\.(\d)+\=((0b\d+)|(0x\d+)|(\d)+))*', - remaining) if x[0] != '' - ] - for temp_entry in entries: - entry = temp_entry.split('=')[0] - f1, f2 = entry.split('..') - for ind in range(int(f1), int(f2)): - - # overlapping bits - if temp_instr[ind] == 'X': - logging.error( - f'{line.split(" ")[0]:<10} has {ind} bit overlapping in it\'s opcodes' - ) - raise SystemExit(1) - temp_instr[ind] = 'X' - - # check x < y - if int(f1) < int(f2): - logging.error( - f'{line.split(" ")[0]:<10} has position {f1} less than position {f2} in it\'s encoding' - ) - raise SystemExit(1) - - # illegal value assigned as per bit width - entry_value = temp_entry.split('=')[1] - temp_base = 16 if 'x' in entry_value else 2 if 'b' in entry_value else 10 - if len(str(int(entry_value, - temp_base))[2:]) > (int(f1) - int(f2)): - logging.error( - f'{line.split(" ")[0]:<10} has an illegal value {entry_value} assigned as per the bit width {f1 - f2}' - ) - raise SystemExit(1) - - # extract bit pattern assignments of the form hi..lo=val. fixed_ranges is a - # regex expression present in constants.py. The extracted patterns are - # captured as a list in args where each entry is a tuple (msb, lsb, value) - args = fixed_ranges.sub(' ', remaining) - - # parse through the args and assign constants 1/0 to bits which need to be - # hardcoded for this instruction - for (msb, lsb, value) in fixed_ranges.findall(remaining): - value = int(value, 0) - msb = int(msb, 0) - lsb = int(lsb, 0) - value = f"{value:032b}" - for i in range(0, msb - lsb + 1): - encoding[31 - (i + lsb)] = value[31 - i] - - # do the same as above but for = pattern. single_fixed is a regex - # expression present in constants.py - for (lsb, value, drop) in single_fixed.findall(remaining): - lsb = int(lsb, 0) - value = int(value, 0) - encoding[31 - lsb] = str(value) - - # convert the list of encodings into a single string for match and mask - match = "".join(encoding).replace('-','0') - mask = "".join(encoding).replace('0','1').replace('-','0') - - # check if all args of the instruction are present in arg_lut present in - # constants.py - args = single_fixed.sub(' ', args).split() - for a in args: - if a not in arg_lut: - logging.error(f' Found variable {a} in instruction {name} whose mapping in arg_lut does not exist') - raise SystemExit(1) - - # update the fields of the instruction as a dict and return back along with - # the name of the instruction - single_dict['encoding'] = "".join(encoding) - single_dict['variable_fields'] = args - single_dict['extension'] = [ext.split('/')[-1]] - single_dict['match']=hex(int(match,2)) - single_dict['mask']=hex(int(mask,2)) - - return (name, single_dict) - - -def create_inst_dict(file_filter): - ''' - This function return a dictionary containing all instructions associated - with an extension defined by the file_filter input. The file_filter input - needs to be rv* file name with out the 'rv' prefix i.e. '_i', '32_i', etc. - - Each node of the dictionary will correspond to an instruction which again is - a dictionary. The dictionary contents of each instruction includes: - - variables: list of arguments used by the instruction whose mapping - exists in the arg_lut dictionary - - encoding: this contains the 32-bit encoding of the instruction where - '-' is used to represent position of arguments and 1/0 is used to - reprsent the static encoding of the bits - - extension: this field contains the rv* filename from which this - instruction was included - - match: hex value representing the bits that need to match to detect - this instruction - - mask: hex value representin the bits that need to be masked to extract - the value required for matching. - - In order to build this dictionary, the function does 2 passes over the same - rv file. The first pass is to extract all standard - instructions. In this pass, all pseudo ops and imported instructions are - skipped. For each selected line of the file, we call process_enc_line - function to create the above mentioned dictionary contents of the - instruction. Checks are performed in this function to ensure that the same - instruction is not added twice to the overall dictionary. - - In the second pass, this function parses only pseudo_ops. For each pseudo_op - this function checks if the dependent extension and instruction, both, exit - before parsing it. The pseudo op is only added to the overall dictionary is - the dependent instruction is not present in the dictionary, else its - skipped. - - - ''' - opcodes_dir = f'./' - filtered_inst = {} - - # file_names contains all files to be parsed in the riscv-opcodes directory - file_names = glob.glob(f'{opcodes_dir}rv{file_filter}') - - # first pass if for standard/original instructions - logging.debug('Collecting standard instructions first') - for f in file_names: - logging.debug(f'Parsing File: {f}') - with open(f) as fp: - lines = (line.rstrip() - for line in fp) # All lines including the blank ones - lines = list(line for line in lines if line) # Non-blank lines - lines = list( - line for line in lines - if not line.startswith("#")) # remove comment lines - - # go through each line of the file - for line in lines: - # if the an instruction needs to be imported then go to the - # respective file and pick the line that has the instruction. - # The variable 'line' will now point to the new line from the - # imported file - - # ignore all lines starting with $import and $pseudo - if '$import' in line or '$pseudo' in line: - continue - logging.debug(f' Processing line: {line}') - - # call process_enc_line to get the data about the current - # instruction - (name, single_dict) = process_enc_line(line, f) - - # if an instruction has already been added to the filtered - # instruction dictionary throw an error saying the given - # instruction is already imported and raise SystemExit - if name in filtered_inst: - var = filtered_inst[name]["extension"] - if filtered_inst[name]['encoding'] != single_dict['encoding']: - err_msg = f'instruction : {name} from ' - err_msg += f'{f.split("/")[-1]} is already ' - err_msg += f'added from {var} but each have different encodings for the same instruction' - logging.error(err_msg) - raise SystemExit(1) - filtered_inst[name]['extension'].append(single_dict['extension']) - - # update the final dict with the instruction - filtered_inst[name] = single_dict - - # second pass if for pseudo instructions - logging.debug('Collecting pseudo instructions now') - for f in file_names: - logging.debug(f'Parsing File: {f}') - with open(f) as fp: - lines = (line.rstrip() - for line in fp) # All lines including the blank ones - lines = list(line for line in lines if line) # Non-blank lines - lines = list( - line for line in lines - if not line.startswith("#")) # remove comment lines - - # go through each line of the file - for line in lines: - - # ignore all lines not starting with $pseudo - if '$pseudo' not in line: - continue - logging.debug(f' Processing line: {line}') - - # use the regex pseudo_regex from constants.py to find the dependent - # extension, dependent instruction, the pseudo_op in question and - # its encoding - (ext, orig_inst, pseudo_inst, line) = pseudo_regex.findall(line)[0] - - # check if the file of the dependent extension exist. Throw error if - # it doesn't - if not os.path.exists(ext): - logging.error(f'Pseudo op {pseudo_inst} in {f} depends on {ext} which is not available') - raise SystemExit(1) - - # check if the dependent instruction exist in the dependent - # extension. Else throw error. - found = False - for oline in open(ext): - if not re.findall(f'^\s*{orig_inst}',oline): - continue - else: - found = True - break - if not found: - logging.error(f'Orig instruction {orig_inst} not found in {ext}. Required by pseudo_op {pseudo_inst} present in {f}') - raise SystemExit(1) - - - # add the pseudo_op to the dictionary only if the original - # instruction is not already in the dictionary. - if orig_inst.replace('.','_') not in filtered_inst: - (name, single_dict) = process_enc_line(pseudo_inst + ' ' + line, f) - - if name in filtered_inst: - var = filtered_inst[name]["extension"] - if filtered_inst[name]['encoding'] != single_dict['encoding']: - err_msg = f'instruction : {name} from ' - err_msg += f'{f.split("/")[-1]} is already ' - err_msg += f'added from {var} but each have different encodings for the same instruction' - logging.error(err_msg) - raise SystemExit(1) - filtered_inst[name]['extension'].append(single_dict['extension']) - - # update the final dict with the instruction - filtered_inst[name] = single_dict - else: - logging.debug(f'Skipping pseudo_op {pseudo_inst} since original instruction {orig_inst} already selected in list') - return filtered_inst - -def make_priv_latex_table(): - latex_file = open('priv-instr-table.tex','w') - type_list = ['R-type','I-type'] - system_instr = ['_h','_s','_system','_svinval', '64_h'] - dataset_list = [ (system_instr, 'Trap-Return Instructions',['sret','mret']) ] - dataset_list.append((system_instr, 'Interrupt-Management Instructions',['wfi'])) - dataset_list.append((system_instr, 'Supervisor Memory-Management Instructions',['sfence_vma'])) - dataset_list.append((system_instr, 'Hypervisor Memory-Management Instructions',['hfence_vvma', 'hfence_gvma'])) - dataset_list.append((system_instr, 'Hypervisor Virtual-Machine Load and Store Instructions', - ['hlv_b','hlv_bu', 'hlv_h','hlv_hu', 'hlv_w', 'hlvx_hu', 'hlvx_wu', 'hsv_b', 'hsv_h','hsv_w'])) - dataset_list.append((system_instr, 'Hypervisor Virtual-Machine Load and Store Instructions, RV64 only', ['hlv_wu','hlv_d','hsv_d'])) - dataset_list.append((system_instr, 'Svinval Memory-Management Instructions', ['sinval_vma', 'sfence_w_inval','sfence_inval_ir', 'hinval_vvma','hinval_gvma'])) - caption = '\\caption{RISC-V Privileged Instructions}' - make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) - - latex_file.close() - -def make_latex_table(): - ''' - This function is mean to create the instr-table.tex that is meant to be used - by the riscv-isa-manual. This function basically creates a single latext - file of multiple tables with each table limited to a single page. Only the - last table is assigned a latex-caption. - - For each table we assign a type-list which capture the different instruction - types (R, I, B, etc) that will be required for the table. Then we select the - list of extensions ('_i, '32_i', etc) whose instructions are required to - populate the table. For each extension or collection of extension we can - assign Title, such that in the end they appear as subheadings within - the table (note these are inlined headings and not captions of the table). - - All of the above information is collected/created and sent to - make_ext_latex_table function to dump out the latex contents into a file. - - The last table only has to be given a caption - as per the policy of the - riscv-isa-manual. - ''' - # open the file and use it as a pointer for all further dumps - latex_file = open('instr-table.tex','w') - - # create the rv32i table first. Here we set the caption to empty. We use the - # files rv_i and rv32_i to capture instructions relevant for rv32i - # configuration. The dataset is a list of 3-element tuples : - # (list_of_extensions, title, list_of_instructions). If list_of_instructions - # is empty then it indicates that all instructions of the all the extensions - # in list_of_extensions need to be dumped. If not empty, then only the - # instructions listed in list_of_instructions will be dumped into latex. - caption = '' - type_list = ['R-type','I-type','S-type','B-type','U-type','J-type'] - dataset_list = [(['_i','32_i'], 'RV32I Base Instruction Set', [])] - make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) - - type_list = ['R-type','I-type','S-type'] - dataset_list = [(['64_i'], 'RV64I Base Instruction Set (in addition to RV32I)', [])] - dataset_list.append((['_zifencei'], 'RV32/RV64 Zifencei Standard Extension', [])) - dataset_list.append((['_zicsr'], 'RV32/RV64 Zicsr Standard Extension', [])) - dataset_list.append((['_m','32_m'], 'RV32M Standard Extension', [])) - dataset_list.append((['64_m'],'RV64M Standard Extension (in addition to RV32M)', [])) - make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) - - type_list = ['R-type'] - dataset_list = [(['_a'],'RV32A Standard Extension', [])] - dataset_list.append((['64_a'],'RV64A Standard Extension (in addition to RV32A)', [])) - make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) - - type_list = ['R-type','R4-type','I-type','S-type'] - dataset_list = [(['_f'],'RV32F Standard Extension', [])] - dataset_list.append((['64_f'],'RV64F Standard Extension (in addition to RV32F)', [])) - make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) - - type_list = ['R-type','R4-type','I-type','S-type'] - dataset_list = [(['_d'],'RV32D Standard Extension', [])] - dataset_list.append((['64_d'],'RV64D Standard Extension (in addition to RV32D)', [])) - make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) - - type_list = ['R-type','R4-type','I-type','S-type'] - dataset_list = [(['_q'],'RV32Q Standard Extension', [])] - dataset_list.append((['64_q'],'RV64Q Standard Extension (in addition to RV32Q)', [])) - make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) - - caption = '\\caption{Instruction listing for RISC-V}' - type_list = ['R-type','R4-type','I-type','S-type'] - dataset_list = [(['_zfh', '_d_zfh','_q_zfh'],'RV32Zfh Standard Extension', [])] - dataset_list.append((['64_zfh'],'RV64Zfh Standard Extension (in addition to RV32Zfh)', [])) - make_ext_latex_table(type_list, dataset_list, latex_file, 32, caption) - - ## The following is demo to show that Compressed instructions can also be - # dumped in the same manner as above - #type_list = [''] - #dataset_list = [(['_c', '32_c', '32_c_f','_c_d'],'RV32C Standard Extension', [])] - #dataset_list.append((['64_c'],'RV64C Standard Extension (in addition to RV32C)', [])) - #make_ext_latex_table(type_list, dataset_list, latex_file, 16, caption) - - latex_file.close() - -def make_ext_latex_table(type_list, dataset, latex_file, ilen, caption): - ''' - For a given collection of extensions this function dumps out a complete - latex table which includes the encodings of the instructions. - - The ilen input indicates the length of the instruction for which the table - is created. - - The caption input is used to create the latex-table caption. - - The type_list input is a list of instruction types (R, I, B, etc) that are - treated as header for each table. Each table will have its own requirements - and type_list must include all the instruction-types that the table needs. - Note, all elements of this list must be present in the latex_inst_type - dictionary defined in constants.py - - The latex_file is a file pointer to which the latex-table will dumped into - - The dataset is a list of 3-element tuples containing: - (list_of_extensions, title, list_of_instructions) - The list_of_extensions must contain all the set of extensions whose - instructions must be populated under a given title. If list_of_instructions - is not empty, then only those instructions mentioned in list_of_instructions - present in the extension will be dumped into the latex-table, other - instructions will be ignored. - - Once the above inputs are received then function first creates table entries - for the instruction types. To simplify things, we maintain a dictionary - called latex_inst_type in constants.py which is created in the same way the - instruction dictionary is created. This allows us to re-use the same logic - to create the instruction types table as well - - Once the header is created, we then parse through every entry in the - dataset. For each list dataset entry we use the create_inst_dict function to - create an exhaustive list of instructions associated with the respective - collection of the extension of that dataset. Then we apply the instruction - filter, if any, indicated by the list_of_instructions of that dataset. - Thereon, for each instruction we create a latex table entry. - - Latex table specification for ilen sized instructions: - Each table is created with ilen+1 columns - ilen columns for each bit of the - instruction and one column to hold the name of the instruction. - - For each argument of an instruction we use the arg_lut from constants.py - to identify its position in the encoding, and thus create a multicolumn - entry with the name of the argument as the data. For hardcoded bits, we - do the same where we capture a string of continuous 1s and 0s, identify - the position and assign the same string as the data of the - multicolumn entry in the table. - - ''' - column_size = "".join(['p{0.002in}']*(ilen+1)) - - type_entries = ''' - \\multicolumn{3}{l}{31} & - \\multicolumn{2}{r}{27} & - \\multicolumn{1}{c}{26} & - \\multicolumn{1}{r}{25} & - \\multicolumn{3}{l}{24} & - \\multicolumn{2}{r}{20} & - \\multicolumn{3}{l}{19} & - \\multicolumn{2}{r}{15} & - \\multicolumn{2}{l}{14} & - \\multicolumn{1}{r}{12} & - \\multicolumn{4}{l}{11} & - \\multicolumn{1}{r}{7} & - \\multicolumn{6}{l}{6} & - \\multicolumn{1}{r}{0} \\\\ - \\cline{2-33}\n& \n\n -''' if ilen == 32 else ''' - \\multicolumn{1}{c}{15} & - \\multicolumn{1}{c}{14} & - \\multicolumn{1}{c}{13} & - \\multicolumn{1}{c}{12} & - \\multicolumn{1}{c}{11} & - \\multicolumn{1}{c}{10} & - \\multicolumn{1}{c}{9} & - \\multicolumn{1}{c}{8} & - \\multicolumn{1}{c}{7} & - \\multicolumn{1}{c}{6} & - \\multicolumn{1}{c}{5} & - \\multicolumn{1}{c}{4} & - \\multicolumn{1}{c}{3} & - \\multicolumn{1}{c}{2} & - \\multicolumn{1}{c}{1} & - \\multicolumn{1}{c}{0} \\\\ - \\cline{2-17}\n& \n\n -''' - - # depending on the type_list input we create a subset dictionary of - # latex_inst_type dictionary present in constants.py - type_dict = {key: value for key, value in latex_inst_type.items() if key in type_list} - - # iterate ovr each instruction type and create a table entry - for t in type_dict: - fields = [] - - # first capture all "arguments" of the type (funct3, funct7, rd, etc) - # and capture their positions using arg_lut. - for f in type_dict[t]['variable_fields']: - (msb, lsb) = arg_lut[f] - name = f if f not in latex_mapping else latex_mapping[f] - fields.append((msb, lsb, name)) - - # iterate through the 32 bits, starting from the msb, and assign - # argument names to the relevant portions of the instructions. This - # information is stored as a 3-element tuple containing the msb, lsb - # position of the arugment and the name of the argument. - msb = ilen - 1 - y = '' - for r in range(0,ilen): - if y != '': - fields.append((msb,ilen-1-r+1,y)) - y = '' - msb = ilen-1-r-1 - if r == 31: - if y != '': - fields.append((msb, 0, y)) - y = '' - - # sort the arguments in decreasing order of msb position - fields.sort(key=lambda y: y[0], reverse=True) - - # for each argument/string of 1s or 0s, create a multicolumn latex table - # entry - entry = '' - for r in range(len(fields)): - (msb, lsb, name) = fields[r] - if r == len(fields)-1: - entry += f'\\multicolumn{{ {msb -lsb +1} }}{{|c|}}{{ {name} }} & {t} \\\\ \n' - elif r == 0: - entry += f'\\multicolumn{{ {msb- lsb + 1} }}{{|c|}}{{ {name} }} &\n' - else: - entry += f'\\multicolumn{{ {msb -lsb + 1} }}{{c|}}{{ {name} }} &\n' - entry += f'\\cline{{2-{ilen+1}}}\n&\n\n' - type_entries += entry - - # for each entry in the dataset create a table - content = '' - for (ext_list, title, filter_list) in dataset: - filtered_inst = {} - - # for all extensions list in ext_list, create a dictionary of - # instructions associated with those extensions. - for e in ext_list: - filtered_inst.update(create_inst_dict(e)) - - # if filter_list is not empty then use that as the official set of - # instructions that need to be dumped into the latex table - inst_list = list(filtered_inst.keys()) if not filter_list else filter_list - - # for each instruction create an latex table entry just like how we did - # above with the instruction-type table. - instr_entries = '' - for inst in inst_list: - if inst not in filtered_inst: - logging.error(f'in make_ext_latex_table: Instruction: {inst} not found in filtered_inst dict') - raise SystemExit(1) - fields = [] - - # only if the argument is available in arg_lut we consume it, else - # throw error. - for f in filtered_inst[inst]['variable_fields']: - if f not in arg_lut: - logging.error(f'Found variable {f} in instruction {inst} whose mapping is not available') - raise SystemExit(1) - (msb,lsb) = arg_lut[f] - name = f.replace('_','.') if f not in latex_mapping else latex_mapping[f] - fields.append((msb, lsb, name)) - - msb = ilen -1 - y = '' - for r in range(0,ilen): - if ilen == 16: - encoding = filtered_inst[inst]['encoding'][16:] - else: - encoding = filtered_inst[inst]['encoding'] - x = encoding [r] - if x == '-': - if y != '': - fields.append((msb,ilen-1-r+1,y)) - y = '' - msb = ilen-1-r-1 - else: - y += str(x) - if r == ilen-1: - if y != '': - fields.append((msb, 0, y)) - y = '' - fields.sort(key=lambda y: y[0], reverse=True) - entry = '' - for r in range(len(fields)): - (msb, lsb, name) = fields[r] - if r == len(fields)-1: - entry += f'\\multicolumn{{ {msb -lsb +1} }}{{|c|}}{{ {name} }} & {inst.upper().replace("_",".")} \\\\ \n' - elif r == 0: - entry += f'\\multicolumn{{ {msb- lsb + 1} }}{{|c|}}{{ {name} }} &\n' - else: - entry += f'\\multicolumn{{ {msb -lsb + 1} }}{{c|}}{{ {name} }} &\n' - entry += f'\\cline{{2-{ilen+1}}}\n&\n\n' - instr_entries += entry - - # once an entry of the dataset is completed we create the whole table - # with the title of that dataset as sub-heading (sort-of) - content += f''' - -\\multicolumn{{{ilen}}}{{c}}{{}} & \\\\ -\\multicolumn{{{ilen}}}{{c}}{{\\bf {title} }} & \\\\ -\\cline{{2-{ilen+1}}} - - & -{instr_entries} -''' - - - header = f''' -\\newpage - -\\begin{{table}}[p] -\\begin{{small}} -\\begin{{center}} - \\begin{{tabular}} {{{column_size}l}} - {" ".join(['&']*ilen)} \\\\ - - & -{type_entries} -''' - endtable=f''' - -\\end{{tabular}} -\\end{{center}} -\\end{{small}} -{caption} -\\end{{table}} -''' - # dump the contents and return - latex_file.write(header+content+endtable) - - -def make_chisel(filtered_inst): - - chisel_names='' - cause_names_str='' - csr_names_str = '' - for i in filtered_inst: - chisel_names += f' def {i.upper().replace(".","_"):<18s} = BitPat("b{filtered_inst[i]["encoding"].replace("-","?")}")\n' - for num, name in causes: - cause_names_str += f' val {name.lower().replace(" ","_")} = {hex(num)}\n' - cause_names_str += ''' val all = { - val res = collection.mutable.ArrayBuffer[Int]() -''' - for num, name in causes: - cause_names_str += f' res += {name.lower().replace(" ","_")}\n' - cause_names_str += ''' res.toArray - }''' - - for num, name in csrs+csrs32: - csr_names_str += f' val {name} = {hex(num)}\n' - csr_names_str += ''' val all = { - val res = collection.mutable.ArrayBuffer[Int]() -''' - for num, name in csrs: - csr_names_str += f''' res += {name}\n''' - csr_names_str += ''' res.toArray - } - val all32 = { - val res = collection.mutable.ArrayBuffer(all:_*) -''' - for num, name in csrs32: - csr_names_str += f''' res += {name}\n''' - csr_names_str += ''' res.toArray - }''' - - chisel_file = open('inst.chisel','w') - chisel_file.write(f''' -/* Automatically generated by parse_opcodes */ -object Instructions {{ -{chisel_names} -}} -object Causes {{ -{cause_names_str} -}} -object CSRs {{ -{csr_names_str} -}} -''') - chisel_file.close() - -def make_rust(filtered_inst): - mask_match_str= '' - for i in filtered_inst: - mask_match_str += f'const MATCH_{i.upper().replace(".","_")}: u32 = {(filtered_inst[i]["match"])};\n' - mask_match_str += f'const MASK_{i.upper().replace(".","_")}: u32 = {(filtered_inst[i]["mask"])};\n' - for num, name in csrs+csrs32: - mask_match_str += f'const CSR_{name.upper()}: u16 = {hex(num)};\n' - for num, name in causes: - mask_match_str += f'const CAUSE_{name.upper().replace(" ","_")}: u8 = {hex(num)};\n' - rust_file = open('inst.rs','w') - rust_file.write(f''' -/* Automatically generated by parse_opcodes */ -{mask_match_str} -''') - rust_file.close() - -def make_sverilog(filtered_inst): - names_str = '' - for i in filtered_inst: - names_str += f" localparam [31:0] {i.upper().replace('.','_'):<18s} = 32'b{filtered_inst[i]['encoding'].replace('-','?')};\n" - names_str += ' /* CSR Addresses */\n' - for num, name in csrs+csrs32: - names_str += f" localparam logic [11:0] CSR_{name.upper()} = 12'h{hex(num)[2:]};\n" - - sverilog_file = open('inst.sverilog','w') - sverilog_file.write(f''' -/* Automatically generated by parse_opcodes */ -package riscv_instr; -{names_str} -endpackage -''') - sverilog_file.close() -def make_c(filtered_inst): - mask_match_str = '' - declare_insn_str = '' - for i in filtered_inst: - mask_match_str += f'#define MATCH_{i.upper().replace(".","_")} {filtered_inst[i]["match"]}\n' - mask_match_str += f'#define MASK_{i.upper().replace(".","_")} {filtered_inst[i]["mask"]}\n' - declare_insn_str += f'DECLARE_INSN({i.replace(".","_")}, MATCH_{i.upper().replace(".","_")}, MASK_{i.upper().replace(".","_")})\n' - - csr_names_str = '' - declare_csr_str = '' - for num, name in csrs+csrs32: - csr_names_str += f'#define CSR_{name.upper()} {hex(num)}\n' - declare_csr_str += f'DECLARE_CSR({name}, CSR_{name.upper()})\n' - - causes_str= '' - declare_cause_str = '' - for num, name in causes: - causes_str += f"#define CAUSE_{name.upper().replace(' ', '_')} {hex(num)}\n" - declare_cause_str += f"DECLARE_CAUSE(\"{name}\", CAUSE_{name.upper().replace(' ','_')})\n" - - with open('encoding.h', 'r') as file: - enc_header = file.read() - - enc_file = open('encoding.out.h','w') - enc_file.write(f''' -/* -* This file is auto-generated by running xxx in -* https://github.com/riscv/riscv-opcodes (xxxxxx) -*/ -{enc_header} -/* Automatically generated by parse_opcodes. */ -#ifndef RISCV_ENCODING_H -#define RISCV_ENCODING_H -{mask_match_str} -{csr_names_str} -{causes_str} -#endif -#ifdef DECLARE_INSN -{declare_insn_str} -#endif -#ifdef DECLARE_CSR -{declare_csr_str} -#endif -#ifdef DECLARE_CAUSE -{declare_cause_str} -#endif -''') - enc_file.close() - -if __name__ == "__main__": - filtered_inst = create_inst_dict('*') - f = open('convert.txt', 'w+') - for key, val in filtered_inst.items(): - f.write(f'{key} : {val}\n') - f.close() - - with open('filtered_inst.yaml', 'w') as outfile: - yaml.dump(filtered_inst, outfile, default_flow_style=False) - filtered_inst = collections.OrderedDict(sorted(filtered_inst.items())) - make_c(filtered_inst) - logging.info('encoding.out.h generated successfully') - make_chisel(filtered_inst) - logging.info('inst.chisel generated successfully') - make_sverilog(filtered_inst) - logging.info('inst.sverilog generated successfully') - make_rust(filtered_inst) - logging.info('inst.rs generated successfully') - make_latex_table() - logging.info('instr-table.tex generated successfully') - make_priv_latex_table() - logging.info('priv-instr-table.tex generated Successfully') diff --git a/riscv_isac/plugins/riscv_opcodes/rv128_c b/riscv_isac/plugins/riscv_opcodes/rv128_c deleted file mode 100644 index beb6cd6..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv128_c +++ /dev/null @@ -1,15 +0,0 @@ -# quadrant 0 -c.lq rd_p rs1_p c_uimm9lo c_uimm9hi 1..0=0 15..13=1 -c.ld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=3 -c.sq rs1_p rs2_p c_uimm9hi c_uimm9lo 1..0=0 15..13=5 -c.sd rs1_p rs2_p c_uimm8hi c_uimm8lo 1..0=0 15..13=7 - -#quadrant 1 -c.addiw rd_rs1 c_imm6lo c_imm6hi 1..0=1 15..13=1 - -#quadrant 2 -c.lqsp rd c_uimm10sphi c_uimm10splo 1..0=2 15..13=1 -c.ldsp rd_n0 c_uimm9sphi c_uimm9splo 1..0=2 15..13=3 -c.sqsp c_rs2 c_uimm10sp_s 1..0=2 15..13=5 -c.sdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=7 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_c b/riscv_isac/plugins/riscv_opcodes/rv32_c deleted file mode 100644 index d9a9072..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_c +++ /dev/null @@ -1,5 +0,0 @@ -# quadrant 1 -c.jal c_imm12 1..0=1 15..13=1 -$pseudo_op rv64_c::c.srli c.srli rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=0 -$pseudo_op rv64_c::c.srai c.srai rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=1 -$pseudo_op rv64_c::c.slli c.slli rd_rs1_n0 c_nzuimm6lo 1..0=2 15..12=0 diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_c_f b/riscv_isac/plugins/riscv_opcodes/rv32_c_f deleted file mode 100644 index 8487c9a..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_c_f +++ /dev/null @@ -1,8 +0,0 @@ -# quadrant 0 -c.flw rd_p rs1_p c_uimm7lo c_uimm7hi 1..0=0 15..13=3 -c.fsw rs1_p rs2_p c_uimm7lo c_uimm7hi 1..0=0 15..13=7 - -#quadrant 2 -c.flwsp rd c_uimm8sphi c_uimm8splo 1..0=2 15..13=3 -c.fswsp c_rs2 c_uimm8sp_s 1..0=2 15..13=7 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_i b/riscv_isac/plugins/riscv_opcodes/rv32_i deleted file mode 100644 index 28d371a..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_i +++ /dev/null @@ -1,4 +0,0 @@ -$pseudo_op rv64_i::slli slli rd rs1 shamtw 31..25=0 14..12=1 6..2=0x04 1..0=3 -$pseudo_op rv64_i::srli srli rd rs1 shamtw 31..25=0 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_i::srai srai rd rs1 shamtw 31..25=32 14..12=5 6..2=0x04 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_p b/riscv_isac/plugins/riscv_opcodes/rv32_p deleted file mode 100644 index b2172f5..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_p +++ /dev/null @@ -1,3 +0,0 @@ -add64 31..25=0b1100000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -sub64 31..25=0b1100001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zbb b/riscv_isac/plugins/riscv_opcodes/rv32_zbb deleted file mode 100644 index cadea09..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_zbb +++ /dev/null @@ -1,3 +0,0 @@ -$pseudo_op rv_zbe::pack zext.h rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..0=0x33 -$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13 -$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zbkb b/riscv_isac/plugins/riscv_opcodes/rv32_zbkb deleted file mode 100644 index f791453..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_zbkb +++ /dev/null @@ -1,4 +0,0 @@ -$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 -$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 -$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13 diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zbp b/riscv_isac/plugins/riscv_opcodes/rv32_zbp deleted file mode 100644 index ac8a564..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_zbp +++ /dev/null @@ -1,7 +0,0 @@ -$pseudo_op rv64_zbp::grevi grevi rd rs1 31..25=0x34 shamtw 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_zbp::gorci gorci rd rs1 31..25=0x14 shamtw 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_zbp::shfli shfli rd rs1 31..25=4 24=0 shamtw4 14..12=1 6..2=0x04 1..0=3 -$pseudo_op rv64_zbp::unshfli unshfli rd rs1 31..25=4 24=0 shamtw4 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 - - diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zbpbo b/riscv_isac/plugins/riscv_opcodes/rv32_zbpbo deleted file mode 100644 index 6ecc566..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_zbpbo +++ /dev/null @@ -1,5 +0,0 @@ -$import rv_zbb::clz -$import rv_zbt::fsr -$import rv32_zbt::fsri -$pseudo_op rv64_zbp::grevi rev rd rs1 31..20=0x69F 14..12=5 6..0=0x13 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zbs b/riscv_isac/plugins/riscv_opcodes/rv32_zbs deleted file mode 100644 index 14ac441..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_zbs +++ /dev/null @@ -1,5 +0,0 @@ -$pseudo_op rv64_zbs::bclri bclri rd rs1 31..25=0x24 shamtw 14..12=1 6..2=0x04 1..0=3 -$pseudo_op rv64_zbs::bexti bexti rd rs1 31..25=0x24 shamtw 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_zbs::binvi binvi rd rs1 31..25=0x34 shamtw 14..12=1 6..2=0x04 1..0=3 -$pseudo_op rv64_zbs::bseti bseti rd rs1 31..25=0x14 shamtw 14..12=1 6..2=0x04 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zbt b/riscv_isac/plugins/riscv_opcodes/rv32_zbt deleted file mode 100644 index 4b5a286..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_zbt +++ /dev/null @@ -1,2 +0,0 @@ -$pseudo_op rv64_zbt::fsri fsri rd rs1 rs3 26=1 25=0 shamtw 14..12=5 6..2=0x04 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zk b/riscv_isac/plugins/riscv_opcodes/rv32_zk deleted file mode 100644 index e491103..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_zk +++ /dev/null @@ -1,25 +0,0 @@ -#import zbkb -$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 -$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 -$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13 - -#import zkne -$import rv32_zkne::aes32esmi -$import rv32_zkne::aes32esi - -#import zknd -# Scalar AES - RV32 -$import rv32_zknd::aes32dsmi -$import rv32_zknd::aes32dsi - - -#import zknh -# Scalar SHA512 - RV32 -$import rv32_zknh::sha512sum0r -$import rv32_zknh::sha512sum1r -$import rv32_zknh::sha512sig0l -$import rv32_zknh::sha512sig0h -$import rv32_zknh::sha512sig1l -$import rv32_zknh::sha512sig1h - diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zkn b/riscv_isac/plugins/riscv_opcodes/rv32_zkn deleted file mode 100644 index e491103..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_zkn +++ /dev/null @@ -1,25 +0,0 @@ -#import zbkb -$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 -$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 -$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13 - -#import zkne -$import rv32_zkne::aes32esmi -$import rv32_zkne::aes32esi - -#import zknd -# Scalar AES - RV32 -$import rv32_zknd::aes32dsmi -$import rv32_zknd::aes32dsi - - -#import zknh -# Scalar SHA512 - RV32 -$import rv32_zknh::sha512sum0r -$import rv32_zknh::sha512sum1r -$import rv32_zknh::sha512sig0l -$import rv32_zknh::sha512sig0h -$import rv32_zknh::sha512sig1l -$import rv32_zknh::sha512sig1h - diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zknd b/riscv_isac/plugins/riscv_opcodes/rv32_zknd deleted file mode 100644 index f367d5e..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_zknd +++ /dev/null @@ -1,4 +0,0 @@ -# Scalar AES - RV32 -aes32dsmi rd rs1 rs2 bs 29..25=0b10111 14..12=0 6..0=0x33 -aes32dsi rd rs1 rs2 bs 29..25=0b10101 14..12=0 6..0=0x33 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zkne b/riscv_isac/plugins/riscv_opcodes/rv32_zkne deleted file mode 100644 index 72bd617..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_zkne +++ /dev/null @@ -1,5 +0,0 @@ -# Scalar AES - RV32 - -aes32esmi rd rs1 rs2 bs 29..25=0b10011 14..12=0 6..0=0x33 -aes32esi rd rs1 rs2 bs 29..25=0b10001 14..12=0 6..0=0x33 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zknh b/riscv_isac/plugins/riscv_opcodes/rv32_zknh deleted file mode 100644 index 675bf54..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_zknh +++ /dev/null @@ -1,8 +0,0 @@ -# Scalar SHA512 - RV32 -sha512sum0r rd rs1 rs2 31..30=1 29..25=0b01000 14..12=0 6..0=0x33 -sha512sum1r rd rs1 rs2 31..30=1 29..25=0b01001 14..12=0 6..0=0x33 -sha512sig0l rd rs1 rs2 31..30=1 29..25=0b01010 14..12=0 6..0=0x33 -sha512sig0h rd rs1 rs2 31..30=1 29..25=0b01110 14..12=0 6..0=0x33 -sha512sig1l rd rs1 rs2 31..30=1 29..25=0b01011 14..12=0 6..0=0x33 -sha512sig1h rd rs1 rs2 31..30=1 29..25=0b01111 14..12=0 6..0=0x33 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv32_zks b/riscv_isac/plugins/riscv_opcodes/rv32_zks deleted file mode 100644 index 034c532..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv32_zks +++ /dev/null @@ -1,6 +0,0 @@ -#import zbkb -$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 -$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 -$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_a b/riscv_isac/plugins/riscv_opcodes/rv64_a deleted file mode 100644 index fe208e9..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_a +++ /dev/null @@ -1,12 +0,0 @@ -# RV64A additions to RV32A -lr.d rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=3 6..2=0x0B 1..0=3 -sc.d rd rs1 rs2 aq rl 31..29=0 28..27=3 14..12=3 6..2=0x0B 1..0=3 -amoswap.d rd rs1 rs2 aq rl 31..29=0 28..27=1 14..12=3 6..2=0x0B 1..0=3 -amoadd.d rd rs1 rs2 aq rl 31..29=0 28..27=0 14..12=3 6..2=0x0B 1..0=3 -amoxor.d rd rs1 rs2 aq rl 31..29=1 28..27=0 14..12=3 6..2=0x0B 1..0=3 -amoand.d rd rs1 rs2 aq rl 31..29=3 28..27=0 14..12=3 6..2=0x0B 1..0=3 -amoor.d rd rs1 rs2 aq rl 31..29=2 28..27=0 14..12=3 6..2=0x0B 1..0=3 -amomin.d rd rs1 rs2 aq rl 31..29=4 28..27=0 14..12=3 6..2=0x0B 1..0=3 -amomax.d rd rs1 rs2 aq rl 31..29=5 28..27=0 14..12=3 6..2=0x0B 1..0=3 -amominu.d rd rs1 rs2 aq rl 31..29=6 28..27=0 14..12=3 6..2=0x0B 1..0=3 -amomaxu.d rd rs1 rs2 aq rl 31..29=7 28..27=0 14..12=3 6..2=0x0B 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_b b/riscv_isac/plugins/riscv_opcodes/rv64_b deleted file mode 100644 index 3d01b8c..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_b +++ /dev/null @@ -1,9 +0,0 @@ -# RV64B additions to RV32B - - -slow rd rs1 rs2 31..25=16 14..12=1 6..2=0x0E 1..0=3 -srow rd rs1 rs2 31..25=16 14..12=5 6..2=0x0E 1..0=3 - -sloiw rd rs1 31..26=8 25=0 shamtw 14..12=1 6..2=0x06 1..0=3 -sroiw rd rs1 31..26=8 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_c b/riscv_isac/plugins/riscv_opcodes/rv64_c deleted file mode 100644 index 39d087a..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_c +++ /dev/null @@ -1,17 +0,0 @@ -# quadrant 0 -c.ld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=3 -c.sd rs1_p rs2_p c_uimm8hi c_uimm8lo 1..0=0 15..13=7 - -#quadrant 1 -c.addiw rd_rs1 c_imm6lo c_imm6hi 1..0=1 15..13=1 -c.srli rd_rs1_p c_nzuimm6lo c_nzuimm6hi 1..0=1 15..13=4 11..10=0 -c.srai rd_rs1_p c_nzuimm6lo c_nzuimm6hi 1..0=1 15..13=4 11..10=1 -c.subw rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b111 6..5=0 -c.addw rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b111 6..5=1 - - -#quadrant 2 -c.slli rd_rs1_n0 c_nzuimm6hi c_nzuimm6lo 1..0=2 15..13=0 -c.ldsp rd_n0 c_uimm9sphi c_uimm9splo 1..0=2 15..13=3 -c.sdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=7 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_d b/riscv_isac/plugins/riscv_opcodes/rv64_d deleted file mode 100644 index d8c8299..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_d +++ /dev/null @@ -1,7 +0,0 @@ -# RV64D additions to RV32D -fcvt.l.d rd rs1 24..20=2 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 -fcvt.lu.d rd rs1 24..20=3 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 -fmv.x.d rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=1 6..2=0x14 1..0=3 -fcvt.d.l rd rs1 24..20=2 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 -fcvt.d.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 -fmv.d.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=1 6..2=0x14 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_f b/riscv_isac/plugins/riscv_opcodes/rv64_f deleted file mode 100644 index 787677c..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_f +++ /dev/null @@ -1,7 +0,0 @@ -# RV64F additions to RV32F - -fcvt.l.s rd rs1 24..20=2 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 -fcvt.lu.s rd rs1 24..20=3 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 -fcvt.s.l rd rs1 24..20=2 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 -fcvt.s.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_h b/riscv_isac/plugins/riscv_opcodes/rv64_h deleted file mode 100644 index 488dcd4..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_h +++ /dev/null @@ -1,5 +0,0 @@ -# Hypervisor extension -hlv.wu rd rs1 24..20=0x1 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 -hlv.d rd rs1 24..20=0x0 31..25=0x36 14..12=4 6..2=0x1C 1..0=3 -hsv.d 11..7=0 rs1 rs2 31..25=0x37 14..12=4 6..2=0x1C 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_i b/riscv_isac/plugins/riscv_opcodes/rv64_i deleted file mode 100644 index 1d88e59..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_i +++ /dev/null @@ -1,17 +0,0 @@ -# RV64I additions to RV32I - -lwu rd rs1 imm12 14..12=6 6..2=0x00 1..0=3 -ld rd rs1 imm12 14..12=3 6..2=0x00 1..0=3 -sd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x08 1..0=3 -slli rd rs1 31..26=0 shamt 14..12=1 6..2=0x04 1..0=3 -srli rd rs1 31..26=0 shamt 14..12=5 6..2=0x04 1..0=3 -srai rd rs1 31..26=16 shamt 14..12=5 6..2=0x04 1..0=3 -addiw rd rs1 imm12 14..12=0 6..2=0x06 1..0=3 -slliw rd rs1 31..25=0 shamtw 14..12=1 6..2=0x06 1..0=3 -srliw rd rs1 31..25=0 shamtw 14..12=5 6..2=0x06 1..0=3 -sraiw rd rs1 31..25=32 shamtw 14..12=5 6..2=0x06 1..0=3 -addw rd rs1 rs2 31..25=0 14..12=0 6..2=0x0E 1..0=3 -subw rd rs1 rs2 31..25=32 14..12=0 6..2=0x0E 1..0=3 -sllw rd rs1 rs2 31..25=0 14..12=1 6..2=0x0E 1..0=3 -srlw rd rs1 rs2 31..25=0 14..12=5 6..2=0x0E 1..0=3 -sraw rd rs1 rs2 31..25=32 14..12=5 6..2=0x0E 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_m b/riscv_isac/plugins/riscv_opcodes/rv64_m deleted file mode 100644 index cfac0b1..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_m +++ /dev/null @@ -1,6 +0,0 @@ -# RV64M additions to RV32M -mulw rd rs1 rs2 31..25=1 14..12=0 6..2=0x0E 1..0=3 -divw rd rs1 rs2 31..25=1 14..12=4 6..2=0x0E 1..0=3 -divuw rd rs1 rs2 31..25=1 14..12=5 6..2=0x0E 1..0=3 -remw rd rs1 rs2 31..25=1 14..12=6 6..2=0x0E 1..0=3 -remuw rd rs1 rs2 31..25=1 14..12=7 6..2=0x0E 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_p b/riscv_isac/plugins/riscv_opcodes/rv64_p deleted file mode 100644 index db8ec29..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_p +++ /dev/null @@ -1,81 +0,0 @@ -add32 31..25=0b0100000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -radd32 31..25=0b0000000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -uradd32 31..25=0b0010000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kadd32 31..25=0b0001000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukadd32 31..25=0b0011000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -sub32 31..25=0b0100001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rsub32 31..25=0b0000001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ursub32 31..25=0b0010001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ksub32 31..25=0b0001001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -uksub32 31..25=0b0011001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -cras32 31..25=0b0100010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rcras32 31..25=0b0000010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -urcras32 31..25=0b0010010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kcras32 31..25=0b0001010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukcras32 31..25=0b0011010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -crsa32 31..25=0b0100011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rcrsa32 31..25=0b0000011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -urcrsa32 31..25=0b0010011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kcrsa32 31..25=0b0001011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukcrsa32 31..25=0b0011011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -stas32 31..25=0b1111000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rstas32 31..25=0b1011000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -urstas32 31..25=0b1101000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kstas32 31..25=0b1100000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukstas32 31..25=0b1110000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -stsa32 31..25=0b1111001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rstsa32 31..25=0b1011001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -urstsa32 31..25=0b1101001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kstsa32 31..25=0b1100001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukstsa32 31..25=0b1110001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -sra32 31..25=0b0101000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -srai32 31..25=0b0111000 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -sra32.u 31..25=0b0110000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -srai32.u 31..25=0b1000000 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -srl32 31..25=0b0101001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -srli32 31..25=0b0111001 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -srl32.u 31..25=0b0110001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -srli32.u 31..25=0b1000001 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -sll32 31..25=0b0101010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -slli32 31..25=0b0111010 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -ksll32 31..25=0b0110010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kslli32 31..25=0b1000010 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 -kslra32 31..25=0b0101011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kslra32.u 31..25=0b0110011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smin32 31..25=0b1001000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -umin32 31..25=0b1010000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smax32 31..25=0b1001001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -umax32 31..25=0b1010001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kabs32 31..25=0b1010110 24..20=0b10010 rs1 14..12=0b000 rd 6..0=0b1110111 -khmbb16 31..25=0b1101110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khmbt16 31..25=0b1110110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khmtt16 31..25=0b1111110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmbb16 31..25=0b1101101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmbt16 31..25=0b1110101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmtt16 31..25=0b1111101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmabb16 31..25=0b1101100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmabt16 31..25=0b1110100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmatt16 31..25=0b1111100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -# smbb32 is missing -smbt32 31..25=0b0001100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smtt32 31..25=0b0010100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmabb32 31..25=0b0101101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmabt32 31..25=0b0110101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmatt32 31..25=0b0111101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmda32 31..25=0b0011100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmxda32 31..25=0b0011101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -# kmada32 is missing -kmaxda32 31..25=0b0100101 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmads32 31..25=0b0101110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmadrs32 31..25=0b0110110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmaxds32 31..25=0b0111110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmsda32 31..25=0b0100110 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kmsxda32 31..25=0b0100111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smds32 31..25=0b0101100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smdrs32 31..25=0b0110100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -smxds32 31..25=0b0111100 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -sraiw.u 31..25=0b0011010 imm5 rs1 14..12=0b001 rd 6..0=0b1110111 -pkbb32 31..25=0b0000111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -pkbt32 31..25=0b0001111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -pktt32 31..25=0b0010111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -pktb32 31..25=0b0011111 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_q b/riscv_isac/plugins/riscv_opcodes/rv64_q deleted file mode 100644 index 32019aa..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_q +++ /dev/null @@ -1,8 +0,0 @@ -# RV64Q additions to RV32Q - -fcvt.l.q rd rs1 24..20=2 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 -fcvt.lu.q rd rs1 24..20=3 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 - -fcvt.q.l rd rs1 24..20=2 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 -fcvt.q.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zba b/riscv_isac/plugins/riscv_opcodes/rv64_zba deleted file mode 100644 index 52d9dcd..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zba +++ /dev/null @@ -1,5 +0,0 @@ -add.uw rd rs1 rs2 31..25=4 14..12=0 6..2=0x0E 1..0=3 -sh1add.uw rd rs1 rs2 31..25=16 14..12=2 6..2=0x0E 1..0=3 -sh2add.uw rd rs1 rs2 31..25=16 14..12=4 6..2=0x0E 1..0=3 -sh3add.uw rd rs1 rs2 31..25=16 14..12=6 6..2=0x0E 1..0=3 -slli.uw rd rs1 31..26=2 shamt 14..12=1 6..2=0x06 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbb b/riscv_isac/plugins/riscv_opcodes/rv64_zbb deleted file mode 100644 index fc19561..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zbb +++ /dev/null @@ -1,9 +0,0 @@ -clzw rd rs1 31..20=0x600 14..12=1 6..2=0x06 1..0=3 -ctzw rd rs1 31..20=0x601 14..12=1 6..2=0x06 1..0=3 -cpopw rd rs1 31..20=0x602 14..12=1 6..2=0x06 1..0=3 -rolw rd rs1 rs2 31..25=0x30 14..12=1 6..2=0x0E 1..0=3 -rorw rd rs1 rs2 31..25=0x30 14..12=5 6..2=0x0E 1..0=3 -roriw rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x06 1..0=3 -rori rd rs1 31..26=0x18 shamt 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv64_zbe::packw zext.h rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..2=0xE 1..0=0x3 -$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbe b/riscv_isac/plugins/riscv_opcodes/rv64_zbe deleted file mode 100644 index d36b80c..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zbe +++ /dev/null @@ -1,4 +0,0 @@ -bcompressw rd rs1 rs2 31..25=4 14..12=6 6..2=0x0E 1..0=3 -bdecompressw rd rs1 rs2 31..25=36 14..12=6 6..2=0x0E 1..0=3 -packw rd rs1 rs2 31..25=4 14..12=4 6..2=0x0E 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbf b/riscv_isac/plugins/riscv_opcodes/rv64_zbf deleted file mode 100644 index d02b59d..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zbf +++ /dev/null @@ -1,3 +0,0 @@ -bfpw rd rs1 rs2 31..25=36 14..12=7 6..2=0x0E 1..0=3 -$import rv64_zbe::packw - diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbkb b/riscv_isac/plugins/riscv_opcodes/rv64_zbkb deleted file mode 100644 index ad2f4a9..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zbkb +++ /dev/null @@ -1,6 +0,0 @@ -$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 -$import rv64_zbb::rolw -$import rv64_zbb::rorw -$import rv64_zbb::roriw -$import rv64_zbb::rori -$import rv64_zbe::packw diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbm b/riscv_isac/plugins/riscv_opcodes/rv64_zbm deleted file mode 100644 index 46a5ebf..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zbm +++ /dev/null @@ -1,7 +0,0 @@ -bmatflip rd rs1 31..20=0x603 14..12=1 6..2=0x04 1..0=3 -bmator rd rs1 rs2 31..25=4 14..12=3 6..2=0x0C 1..0=3 -bmatxor rd rs1 rs2 31..25=36 14..12=3 6..2=0x0C 1..0=3 -$pseudo_op rv64_zbp::unshfli unzip16 rd rs1 31..25=4 24..20=16 14..12=5 6..2=4 1..0=3 -$pseudo_op rv64_zbp::unshfli unzip8 rd rs1 31..25=4 24..20=24 14..12=5 6..2=4 1..0=3 -$import rv_zbe::pack -$import rv_zbp::packu diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbp b/riscv_isac/plugins/riscv_opcodes/rv64_zbp deleted file mode 100644 index f8c06bd..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zbp +++ /dev/null @@ -1,17 +0,0 @@ -grevi rd rs1 31..26=26 shamt 14..12=5 6..2=0x04 1..0=3 -gorci rd rs1 31..26=10 shamt 14..12=5 6..2=0x04 1..0=3 -shfli rd rs1 31..26=2 25=0 shamtw 14..12=1 6..2=0x04 1..0=3 -unshfli rd rs1 31..26=2 25=0 shamtw 14..12=5 6..2=0x04 1..0=3 -$import rv64_zbe::packw -packuw rd rs1 rs2 31..25=36 14..12=4 6..2=0x0E 1..0=3 -$import rv64_zbb::rolw -$import rv64_zbb::rorw -$import rv64_zbb::roriw -$import rv64_zbb::rori -gorcw rd rs1 rs2 31..25=20 14..12=5 6..2=0x0E 1..0=3 -grevw rd rs1 rs2 31..25=52 14..12=5 6..2=0x0E 1..0=3 -gorciw rd rs1 31..26=10 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 -greviw rd rs1 31..26=26 25=0 shamtw 14..12=5 6..2=0x06 1..0=3 -shflw rd rs1 rs2 31..25=4 14..12=1 6..2=0x0E 1..0=3 -unshflw rd rs1 rs2 31..25=4 14..12=5 6..2=0x0E 1..0=3 -xperm32 rd rs1 rs2 31..25=20 14..12=0 6..2=0x0C 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbpbo b/riscv_isac/plugins/riscv_opcodes/rv64_zbpbo deleted file mode 100644 index f88bd03..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zbpbo +++ /dev/null @@ -1,2 +0,0 @@ -$import rv64_zbt::fsrw -$pseudo_op rv64_zbp::grevi rev rd rs1 31..20=0x6BF 14..12=5 6..0=0x13 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbr b/riscv_isac/plugins/riscv_opcodes/rv64_zbr deleted file mode 100644 index 3b470f1..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zbr +++ /dev/null @@ -1,3 +0,0 @@ -crc32.d rd rs1 31..20=0x613 14..12=1 6..2=0x04 1..0=3 -crc32c.d rd rs1 31..20=0x61B 14..12=1 6..2=0x04 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbs b/riscv_isac/plugins/riscv_opcodes/rv64_zbs deleted file mode 100644 index d3203a6..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zbs +++ /dev/null @@ -1,5 +0,0 @@ -bclri rd rs1 31..26=0x12 shamt 14..12=1 6..2=0x04 1..0=3 -bexti rd rs1 31..26=0x12 shamt 14..12=5 6..2=0x04 1..0=3 -binvi rd rs1 31..26=0x1a shamt 14..12=1 6..2=0x04 1..0=3 -bseti rd rs1 31..26=0x0a shamt 14..12=1 6..2=0x04 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zbt b/riscv_isac/plugins/riscv_opcodes/rv64_zbt deleted file mode 100644 index fcb84b5..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zbt +++ /dev/null @@ -1,6 +0,0 @@ -fslw rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0E 1..0=3 -fsrw rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0E 1..0=3 -fsriw rd rs1 rs3 26..25=2 shamtw 14..12=5 6..2=0x06 1..0=3 -fsri rd rs1 rs3 26=1 shamt 14..12=5 6..2=0x04 1..0=3 - - diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zfh b/riscv_isac/plugins/riscv_opcodes/rv64_zfh deleted file mode 100644 index 5cc9f25..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zfh +++ /dev/null @@ -1,7 +0,0 @@ -# RV64Zfh additions to RV32Zfh - -fcvt.l.h rd rs1 24..20=2 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 -fcvt.lu.h rd rs1 24..20=3 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 - -fcvt.h.l rd rs1 24..20=2 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 -fcvt.h.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zk b/riscv_isac/plugins/riscv_opcodes/rv64_zk deleted file mode 100644 index 0ebf71d..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zk +++ /dev/null @@ -1,28 +0,0 @@ -#import zbkb -$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 -$import rv64_zbb::rolw -$import rv64_zbb::rorw -$import rv64_zbb::roriw -$import rv64_zbb::rori -$import rv64_zbe::packw - -#import zkne -# Scalar AES - RV64 -$import rv64_zkne::aes64esm -$import rv64_zkne::aes64es -$import rv64_zknd::aes64ks1i -$import rv64_zknd::aes64ks2 - -#import zknd -# Scalar AES - RV64 -$import rv64_zknd::aes64dsm -$import rv64_zknd::aes64ds -$import rv64_zknd::aes64im - -#import zknh -# Scalar SHA512 - RV64 -$import rv64_zknh::sha512sum0 -$import rv64_zknh::sha512sum1 -$import rv64_zknh::sha512sig0 -$import rv64_zknh::sha512sig1 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zkn b/riscv_isac/plugins/riscv_opcodes/rv64_zkn deleted file mode 100644 index 0ebf71d..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zkn +++ /dev/null @@ -1,28 +0,0 @@ -#import zbkb -$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 -$import rv64_zbb::rolw -$import rv64_zbb::rorw -$import rv64_zbb::roriw -$import rv64_zbb::rori -$import rv64_zbe::packw - -#import zkne -# Scalar AES - RV64 -$import rv64_zkne::aes64esm -$import rv64_zkne::aes64es -$import rv64_zknd::aes64ks1i -$import rv64_zknd::aes64ks2 - -#import zknd -# Scalar AES - RV64 -$import rv64_zknd::aes64dsm -$import rv64_zknd::aes64ds -$import rv64_zknd::aes64im - -#import zknh -# Scalar SHA512 - RV64 -$import rv64_zknh::sha512sum0 -$import rv64_zknh::sha512sum1 -$import rv64_zknh::sha512sig0 -$import rv64_zknh::sha512sig1 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zknd b/riscv_isac/plugins/riscv_opcodes/rv64_zknd deleted file mode 100644 index f1507d6..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zknd +++ /dev/null @@ -1,7 +0,0 @@ -# Scalar AES - RV64 -aes64dsm rd rs1 rs2 31..30=0 29..25=0b11111 14..12=0b000 6..0=0x33 -aes64ds rd rs1 rs2 31..30=0 29..25=0b11101 14..12=0b000 6..0=0x33 -aes64ks1i rd rs1 rnum 31..30=0 29..25=0b11000 24=1 14..12=0b001 6..0=0x13 -aes64im rd rs1 31..30=0 29..25=0b11000 24..20=0b0000 14..12=0b001 6..0=0x13 -aes64ks2 rd rs1 rs2 31..30=1 29..25=0b11111 14..12=0b000 6..0=0x33 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zkne b/riscv_isac/plugins/riscv_opcodes/rv64_zkne deleted file mode 100644 index 3323b7f..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zkne +++ /dev/null @@ -1,5 +0,0 @@ -# Scalar AES - RV64 -aes64esm rd rs1 rs2 31..30=0 29..25=0b11011 14..12=0b000 6..0=0x33 -aes64es rd rs1 rs2 31..30=0 29..25=0b11001 14..12=0b000 6..0=0x33 -$import rv64_zknd::aes64ks1i -$import rv64_zknd::aes64ks2 diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zknh b/riscv_isac/plugins/riscv_opcodes/rv64_zknh deleted file mode 100644 index 431a1bc..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zknh +++ /dev/null @@ -1,6 +0,0 @@ -# Scalar SHA512 - RV64 -sha512sum0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00100 14..12=1 6..0=0x13 -sha512sum1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00101 14..12=1 6..0=0x13 -sha512sig0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00110 14..12=1 6..0=0x13 -sha512sig1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00111 14..12=1 6..0=0x13 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv64_zks b/riscv_isac/plugins/riscv_opcodes/rv64_zks deleted file mode 100644 index 6bbad27..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv64_zks +++ /dev/null @@ -1,7 +0,0 @@ -#import zbkb -$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 -$import rv64_zbb::rolw -$import rv64_zbb::rorw -$import rv64_zbb::roriw -$import rv64_zbb::rori -$import rv64_zbe::packw diff --git a/riscv_isac/plugins/riscv_opcodes/rv_a b/riscv_isac/plugins/riscv_opcodes/rv_a deleted file mode 100644 index 1a70e40..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_a +++ /dev/null @@ -1,11 +0,0 @@ -lr.w rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=2 6..2=0x0B 1..0=3 -sc.w rd rs1 rs2 aq rl 31..29=0 28..27=3 14..12=2 6..2=0x0B 1..0=3 -amoswap.w rd rs1 rs2 aq rl 31..29=0 28..27=1 14..12=2 6..2=0x0B 1..0=3 -amoadd.w rd rs1 rs2 aq rl 31..29=0 28..27=0 14..12=2 6..2=0x0B 1..0=3 -amoxor.w rd rs1 rs2 aq rl 31..29=1 28..27=0 14..12=2 6..2=0x0B 1..0=3 -amoand.w rd rs1 rs2 aq rl 31..29=3 28..27=0 14..12=2 6..2=0x0B 1..0=3 -amoor.w rd rs1 rs2 aq rl 31..29=2 28..27=0 14..12=2 6..2=0x0B 1..0=3 -amomin.w rd rs1 rs2 aq rl 31..29=4 28..27=0 14..12=2 6..2=0x0B 1..0=3 -amomax.w rd rs1 rs2 aq rl 31..29=5 28..27=0 14..12=2 6..2=0x0B 1..0=3 -amominu.w rd rs1 rs2 aq rl 31..29=6 28..27=0 14..12=2 6..2=0x0B 1..0=3 -amomaxu.w rd rs1 rs2 aq rl 31..29=7 28..27=0 14..12=2 6..2=0x0B 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_b b/riscv_isac/plugins/riscv_opcodes/rv_b deleted file mode 100644 index 4fe7ef0..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_b +++ /dev/null @@ -1,12 +0,0 @@ - -slo rd rs1 rs2 31..25=16 14..12=1 6..2=0x0C 1..0=3 -sro rd rs1 rs2 31..25=16 14..12=5 6..2=0x0C 1..0=3 - - -sloi rd rs1 31..26=8 shamt 14..12=1 6..2=0x04 1..0=3 -sroi rd rs1 31..26=8 shamt 14..12=5 6..2=0x04 1..0=3 - - - - - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_c b/riscv_isac/plugins/riscv_opcodes/rv_c deleted file mode 100644 index 46b1e1c..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_c +++ /dev/null @@ -1,32 +0,0 @@ -# quadrant 0 -c.addi4spn rd_p c_nzuimm10 1..0=0 15..13=0 -c.lw rd_p rs1_p c_uimm7lo c_uimm7hi 1..0=0 15..13=2 -c.sw rs1_p rs2_p c_uimm7lo c_uimm7hi 1..0=0 15..13=6 - -#quadrant 1 -c.nop c_nzimm6hi c_nzimm6lo 1..0=1 15..13=0 11..7=0 -c.addi rd_rs1_n0 c_nzimm6lo c_nzimm6hi 1..0=1 15..13=0 -c.li rd c_imm6lo c_imm6hi 1..0=1 15..13=2 -c.addi16sp c_nzimm10hi c_nzimm10lo 1..0=1 15..13=3 11..7=2 -c.lui rd_n2 c_nzimm18hi c_nzimm18lo 1..0=1 15..13=3 -c.andi rd_rs1_p c_imm6hi c_imm6lo 1..0=1 15..13=4 11..10=2 -c.sub rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=0 -c.xor rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=1 -c.or rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=2 -c.and rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=3 -c.j c_imm12 1..0=1 15..13=5 -c.beqz rs1_p c_bimm9lo c_bimm9hi 1..0=1 15..13=6 -c.bnez rs1_p c_bimm9lo c_bimm9hi 1..0=1 15..13=7 - -#quadrant 2 -c.lwsp rd_n0 c_uimm8sphi c_uimm8splo 1..0=2 15..13=2 -c.jr rs1_n0 1..0=2 15..13=4 12=0 6..2=0 -c.mv rd c_rs2_n0 1..0=2 15..13=4 12=0 -c.ebreak 1..0=2 15..13=4 12=1 11..2=0 -c.jalr c_rs1_n0 1..0=2 15..13=4 12=1 6..2=0 -c.add rd_rs1 c_rs2_n0 1..0=2 15..13=4 12=1 -c.swsp c_rs2 c_uimm8sp_s 1..0=2 15..13=6 - - - - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_c_d b/riscv_isac/plugins/riscv_opcodes/rv_c_d deleted file mode 100644 index cd49b44..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_c_d +++ /dev/null @@ -1,8 +0,0 @@ -#quadrant 0 -c.fld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=1 -c.fsd rs1_p rs2_p c_uimm8lo c_uimm8hi 1..0=0 15..13=5 - -#quadrant 2 -c.fldsp rd c_uimm9sphi c_uimm9splo 1..0=2 15..13=1 -c.fsdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=5 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_custom b/riscv_isac/plugins/riscv_opcodes/rv_custom deleted file mode 100644 index 036bc4b..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_custom +++ /dev/null @@ -1,27 +0,0 @@ -custom0 rd rs1 imm12 14..12=0 6..2=0x02 1..0=3 -custom0.rs1 rd rs1 imm12 14..12=2 6..2=0x02 1..0=3 -custom0.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x02 1..0=3 -custom0.rd rd rs1 imm12 14..12=4 6..2=0x02 1..0=3 -custom0.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x02 1..0=3 -custom0.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x02 1..0=3 - -custom1 rd rs1 imm12 14..12=0 6..2=0x0A 1..0=3 -custom1.rs1 rd rs1 imm12 14..12=2 6..2=0x0A 1..0=3 -custom1.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x0A 1..0=3 -custom1.rd rd rs1 imm12 14..12=4 6..2=0x0A 1..0=3 -custom1.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x0A 1..0=3 -custom1.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x0A 1..0=3 - -custom2 rd rs1 imm12 14..12=0 6..2=0x16 1..0=3 -custom2.rs1 rd rs1 imm12 14..12=2 6..2=0x16 1..0=3 -custom2.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x16 1..0=3 -custom2.rd rd rs1 imm12 14..12=4 6..2=0x16 1..0=3 -custom2.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x16 1..0=3 -custom2.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x16 1..0=3 - -custom3 rd rs1 imm12 14..12=0 6..2=0x1E 1..0=3 -custom3.rs1 rd rs1 imm12 14..12=2 6..2=0x1E 1..0=3 -custom3.rs1.rs2 rd rs1 imm12 14..12=3 6..2=0x1E 1..0=3 -custom3.rd rd rs1 imm12 14..12=4 6..2=0x1E 1..0=3 -custom3.rd.rs1 rd rs1 imm12 14..12=6 6..2=0x1E 1..0=3 -custom3.rd.rs1.rs2 rd rs1 imm12 14..12=7 6..2=0x1E 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_d b/riscv_isac/plugins/riscv_opcodes/rv_d deleted file mode 100644 index 8c3a3d3..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_d +++ /dev/null @@ -1,26 +0,0 @@ -fld rd rs1 imm12 14..12=3 6..2=0x01 1..0=3 -fsd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x09 1..0=3 -fmadd.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x10 1..0=3 -fmsub.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x11 1..0=3 -fnmsub.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x12 1..0=3 -fnmadd.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x13 1..0=3 -fadd.d rd rs1 rs2 31..27=0x00 rm 26..25=1 6..2=0x14 1..0=3 -fsub.d rd rs1 rs2 31..27=0x01 rm 26..25=1 6..2=0x14 1..0=3 -fmul.d rd rs1 rs2 31..27=0x02 rm 26..25=1 6..2=0x14 1..0=3 -fdiv.d rd rs1 rs2 31..27=0x03 rm 26..25=1 6..2=0x14 1..0=3 -fsqrt.d rd rs1 24..20=0 31..27=0x0B rm 26..25=1 6..2=0x14 1..0=3 -fsgnj.d rd rs1 rs2 31..27=0x04 14..12=0 26..25=1 6..2=0x14 1..0=3 -fsgnjn.d rd rs1 rs2 31..27=0x04 14..12=1 26..25=1 6..2=0x14 1..0=3 -fsgnjx.d rd rs1 rs2 31..27=0x04 14..12=2 26..25=1 6..2=0x14 1..0=3 -fmin.d rd rs1 rs2 31..27=0x05 14..12=0 26..25=1 6..2=0x14 1..0=3 -fmax.d rd rs1 rs2 31..27=0x05 14..12=1 26..25=1 6..2=0x14 1..0=3 -fcvt.s.d rd rs1 24..20=1 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 -fcvt.d.s rd rs1 24..20=0 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 -feq.d rd rs1 rs2 31..27=0x14 14..12=2 26..25=1 6..2=0x14 1..0=3 -flt.d rd rs1 rs2 31..27=0x14 14..12=1 26..25=1 6..2=0x14 1..0=3 -fle.d rd rs1 rs2 31..27=0x14 14..12=0 26..25=1 6..2=0x14 1..0=3 -fclass.d rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=1 6..2=0x14 1..0=3 -fcvt.w.d rd rs1 24..20=0 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 -fcvt.wu.d rd rs1 24..20=1 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 -fcvt.d.w rd rs1 24..20=0 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 -fcvt.d.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_d_zfh b/riscv_isac/plugins/riscv_opcodes/rv_d_zfh deleted file mode 100644 index 80d3765..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_d_zfh +++ /dev/null @@ -1,2 +0,0 @@ -fcvt.d.h rd rs1 24..20=2 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 -fcvt.h.d rd rs1 24..20=1 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_f b/riscv_isac/plugins/riscv_opcodes/rv_f deleted file mode 100644 index c148dd2..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_f +++ /dev/null @@ -1,26 +0,0 @@ -flw rd rs1 imm12 14..12=2 6..2=0x01 1..0=3 -fsw imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x09 1..0=3 -fmadd.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x10 1..0=3 -fmsub.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x11 1..0=3 -fnmsub.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x12 1..0=3 -fnmadd.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x13 1..0=3 -fadd.s rd rs1 rs2 31..27=0x00 rm 26..25=0 6..2=0x14 1..0=3 -fsub.s rd rs1 rs2 31..27=0x01 rm 26..25=0 6..2=0x14 1..0=3 -fmul.s rd rs1 rs2 31..27=0x02 rm 26..25=0 6..2=0x14 1..0=3 -fdiv.s rd rs1 rs2 31..27=0x03 rm 26..25=0 6..2=0x14 1..0=3 -fsqrt.s rd rs1 24..20=0 31..27=0x0B rm 26..25=0 6..2=0x14 1..0=3 -fsgnj.s rd rs1 rs2 31..27=0x04 14..12=0 26..25=0 6..2=0x14 1..0=3 -fsgnjn.s rd rs1 rs2 31..27=0x04 14..12=1 26..25=0 6..2=0x14 1..0=3 -fsgnjx.s rd rs1 rs2 31..27=0x04 14..12=2 26..25=0 6..2=0x14 1..0=3 -fmin.s rd rs1 rs2 31..27=0x05 14..12=0 26..25=0 6..2=0x14 1..0=3 -fmax.s rd rs1 rs2 31..27=0x05 14..12=1 26..25=0 6..2=0x14 1..0=3 -fcvt.w.s rd rs1 24..20=0 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 -fcvt.wu.s rd rs1 24..20=1 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 -fmv.x.w rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 -feq.s rd rs1 rs2 31..27=0x14 14..12=2 26..25=0 6..2=0x14 1..0=3 -flt.s rd rs1 rs2 31..27=0x14 14..12=1 26..25=0 6..2=0x14 1..0=3 -fle.s rd rs1 rs2 31..27=0x14 14..12=0 26..25=0 6..2=0x14 1..0=3 -fclass.s rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=0 6..2=0x14 1..0=3 -fcvt.s.w rd rs1 24..20=0 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 -fcvt.s.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 -fmv.w.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_h b/riscv_isac/plugins/riscv_opcodes/rv_h deleted file mode 100644 index 63b9efc..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_h +++ /dev/null @@ -1,15 +0,0 @@ -# Hypervisor extension -hfence.vvma 11..7=0 rs1 rs2 31..25=0x11 14..12=0 6..2=0x1C 1..0=3 -hfence.gvma 11..7=0 rs1 rs2 31..25=0x31 14..12=0 6..2=0x1C 1..0=3 - -hlv.b rd rs1 24..20=0x0 31..25=0x30 14..12=4 6..2=0x1C 1..0=3 -hlv.bu rd rs1 24..20=0x1 31..25=0x30 14..12=4 6..2=0x1C 1..0=3 -hlv.h rd rs1 24..20=0x0 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 -hlv.hu rd rs1 24..20=0x1 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 -hlvx.hu rd rs1 24..20=0x3 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 -hlv.w rd rs1 24..20=0x0 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 -hlvx.wu rd rs1 24..20=0x3 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 -hsv.b 11..7=0 rs1 rs2 31..25=0x31 14..12=4 6..2=0x1C 1..0=3 -hsv.h 11..7=0 rs1 rs2 31..25=0x33 14..12=4 6..2=0x1C 1..0=3 -hsv.w 11..7=0 rs1 rs2 31..25=0x35 14..12=4 6..2=0x1C 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_i b/riscv_isac/plugins/riscv_opcodes/rv_i deleted file mode 100644 index 4afb288..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_i +++ /dev/null @@ -1,46 +0,0 @@ -# format of a line in this file: -# -# -# is given by specifying one or more range/value pairs: -# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) -# -# is one of rd, rs1, rs2, rs3, imm20, imm12, imm12lo, imm12hi, -# shamtw, shamt, rm - -lui rd imm20 6..2=0x0D 1..0=3 -auipc rd imm20 6..2=0x05 1..0=3 -jal rd jimm20 6..2=0x1b 1..0=3 -jalr rd rs1 imm12 14..12=0 6..2=0x19 1..0=3 -beq bimm12hi rs1 rs2 bimm12lo 14..12=0 6..2=0x18 1..0=3 -bne bimm12hi rs1 rs2 bimm12lo 14..12=1 6..2=0x18 1..0=3 -blt bimm12hi rs1 rs2 bimm12lo 14..12=4 6..2=0x18 1..0=3 -bge bimm12hi rs1 rs2 bimm12lo 14..12=5 6..2=0x18 1..0=3 -bltu bimm12hi rs1 rs2 bimm12lo 14..12=6 6..2=0x18 1..0=3 -bgeu bimm12hi rs1 rs2 bimm12lo 14..12=7 6..2=0x18 1..0=3 -lb rd rs1 imm12 14..12=0 6..2=0x00 1..0=3 -lh rd rs1 imm12 14..12=1 6..2=0x00 1..0=3 -lw rd rs1 imm12 14..12=2 6..2=0x00 1..0=3 -lbu rd rs1 imm12 14..12=4 6..2=0x00 1..0=3 -lhu rd rs1 imm12 14..12=5 6..2=0x00 1..0=3 -sb imm12hi rs1 rs2 imm12lo 14..12=0 6..2=0x08 1..0=3 -sh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x08 1..0=3 -sw imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x08 1..0=3 -addi rd rs1 imm12 14..12=0 6..2=0x04 1..0=3 -slti rd rs1 imm12 14..12=2 6..2=0x04 1..0=3 -sltiu rd rs1 imm12 14..12=3 6..2=0x04 1..0=3 -xori rd rs1 imm12 14..12=4 6..2=0x04 1..0=3 -ori rd rs1 imm12 14..12=6 6..2=0x04 1..0=3 -andi rd rs1 imm12 14..12=7 6..2=0x04 1..0=3 -add rd rs1 rs2 31..25=0 14..12=0 6..2=0x0C 1..0=3 -sub rd rs1 rs2 31..25=32 14..12=0 6..2=0x0C 1..0=3 -sll rd rs1 rs2 31..25=0 14..12=1 6..2=0x0C 1..0=3 -slt rd rs1 rs2 31..25=0 14..12=2 6..2=0x0C 1..0=3 -sltu rd rs1 rs2 31..25=0 14..12=3 6..2=0x0C 1..0=3 -xor rd rs1 rs2 31..25=0 14..12=4 6..2=0x0C 1..0=3 -srl rd rs1 rs2 31..25=0 14..12=5 6..2=0x0C 1..0=3 -sra rd rs1 rs2 31..25=32 14..12=5 6..2=0x0C 1..0=3 -or rd rs1 rs2 31..25=0 14..12=6 6..2=0x0C 1..0=3 -and rd rs1 rs2 31..25=0 14..12=7 6..2=0x0C 1..0=3 -fence fm pred succ rs1 14..12=0 rd 6..2=0x03 1..0=3 -ecall 31..20=0x000 19..7=0 6..2=0x1C 1..0=3 -ebreak 31..20=0x001 19..7=0 6..2=0x1C 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_m b/riscv_isac/plugins/riscv_opcodes/rv_m deleted file mode 100644 index 51e6786..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_m +++ /dev/null @@ -1,8 +0,0 @@ -mul rd rs1 rs2 31..25=1 14..12=0 6..2=0x0C 1..0=3 -mulh rd rs1 rs2 31..25=1 14..12=1 6..2=0x0C 1..0=3 -mulhsu rd rs1 rs2 31..25=1 14..12=2 6..2=0x0C 1..0=3 -mulhu rd rs1 rs2 31..25=1 14..12=3 6..2=0x0C 1..0=3 -div rd rs1 rs2 31..25=1 14..12=4 6..2=0x0C 1..0=3 -divu rd rs1 rs2 31..25=1 14..12=5 6..2=0x0C 1..0=3 -rem rd rs1 rs2 31..25=1 14..12=6 6..2=0x0C 1..0=3 -remu rd rs1 rs2 31..25=1 14..12=7 6..2=0x0C 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_p b/riscv_isac/plugins/riscv_opcodes/rv_p deleted file mode 100644 index c239c10..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_p +++ /dev/null @@ -1,245 +0,0 @@ -add8 31..25=0b0100100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -add16 31..25=0b0100000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ave 31..25=0b1110000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -bitrev 31..25=0b1110011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -bitrevi 31..26=0b111010 imm6 rs1 14..12=0b000 rd 6..0=0b1110111 -bpick rs3 26..25=0b00 rs2 rs1 14..12=0b011 rd 6..0=0b1110111 -clrs8 31..25=0b1010111 24..20=0b00000 rs1 14..12=0b000 rd 6..0=0b1110111 -clrs16 31..25=0b1010111 24..20=0b01000 rs1 14..12=0b000 rd 6..0=0b1110111 -clrs32 31..25=0b1010111 24..20=0b11000 rs1 14..12=0b000 rd 6..0=0b1110111 -clo8 31..25=0b1010111 24..20=0b00011 rs1 14..12=0b000 rd 6..0=0b1110111 -clo16 31..25=0b1010111 24..20=0b01011 rs1 14..12=0b000 rd 6..0=0b1110111 -clo32 31..25=0b1010111 24..20=0b11011 rs1 14..12=0b000 rd 6..0=0b1110111 -clz8 31..25=0b1010111 24..20=0b00001 rs1 14..12=0b000 rd 6..0=0b1110111 -clz16 31..25=0b1010111 24..20=0b01001 rs1 14..12=0b000 rd 6..0=0b1110111 -clz32 31..25=0b1010111 24..20=0b11001 rs1 14..12=0b000 rd 6..0=0b1110111 -cmpeq8 31..25=0b0100111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -cmpeq16 31..25=0b0100110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -cras16 31..25=0b0100010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -crsa16 31..25=0b0100011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -insb 31..25=0b1010110 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -kabs8 31..25=0b1010110 24..20=0b10000 rs1 14..12=0b000 rd 6..0=0b1110111 -kabs16 31..25=0b1010110 24..20=0b10001 rs1 14..12=0b000 rd 6..0=0b1110111 -kabsw 31..25=0b1010110 24..20=0b10100 rs1 14..12=0b000 rd 6..0=0b1110111 -kadd8 31..25=0b0001100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kadd16 31..25=0b0001000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kadd64 31..25=0b1001000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kaddh 31..25=0b0000010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kaddw 31..25=0b0000000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kcras16 31..25=0b0001010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kcrsa16 31..25=0b0001011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kdmbb 31..25=0b0000101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmbt 31..25=0b0001101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmtt 31..25=0b0010101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmabb 31..25=0b1101001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmabt 31..25=0b1110001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kdmatt 31..25=0b1111001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khm8 31..25=0b1000111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -khmx8 31..25=0b1001111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -khm16 31..25=0b1000011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -khmx16 31..25=0b1001011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -khmbb 31..25=0b0000110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khmbt 31..25=0b0001110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -khmtt 31..25=0b0010110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmabb 31..25=0b0101101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmabt 31..25=0b0110101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmatt 31..25=0b0111101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmada 31..25=0b0100100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmaxda 31..25=0b0100101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmads 31..25=0b0101110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmadrs 31..25=0b0110110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmaxds 31..25=0b0111110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmar64 31..25=0b1001010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmda 31..25=0b0011100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmxda 31..25=0b0011101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmac 31..25=0b0110000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmac.u 31..25=0b0111000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawb 31..25=0b0100011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawb.u 31..25=0b0101011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawb2 31..25=0b1100111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawb2.u 31..25=0b1101111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawt 31..25=0b0110011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawt.u 31..25=0b0111011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawt2 31..25=0b1110111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmawt2.u 31..25=0b1111111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmsb 31..25=0b0100001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmsb.u 31..25=0b0101001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmwb2 31..25=0b1000111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmwb2.u 31..25=0b1001111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmwt2 31..25=0b1010111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmmwt2.u 31..25=0b1011111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmsda 31..25=0b0100110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmsxda 31..25=0b0100111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kmsr64 31..25=0b1001011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ksllw 31..25=0b0010011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kslliw 31..25=0b0011011 imm5 rs1 14..12=0b001 rd 6..0=0b1110111 -ksll8 31..25=0b0110110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslli8 31..25=0b0111110 24..23=0b01 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -ksll16 31..25=0b0110010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslli16 31..25=0b0111010 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -kslra8 31..25=0b0101111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslra8.u 31..25=0b0110111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslra16 31..25=0b0101011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslra16.u 31..25=0b0110011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -kslraw 31..25=0b0110111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kslraw.u 31..25=0b0111111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kstas16 31..25=0b1100010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -kstsa16 31..25=0b1100011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ksub8 31..25=0b0001101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ksub16 31..25=0b0001001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ksub64 31..25=0b1001001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ksubh 31..25=0b0000011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ksubw 31..25=0b0000001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kwmmul 31..25=0b0110001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -kwmmul.u 31..25=0b0111001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -maddr32 31..25=0b1100010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -maxw 31..25=0b1111001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -minw 31..25=0b1111000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -msubr32 31..25=0b1100011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -mulr64 31..25=0b1111000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -mulsr64 31..25=0b1110000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -pbsad 31..25=0b1111110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -pbsada 31..25=0b1111111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -pkbb16 31..25=0b0000111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -pkbt16 31..25=0b0001111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -pktt16 31..25=0b0010111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -pktb16 31..25=0b0011111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -radd8 31..25=0b0000100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -radd16 31..25=0b0000000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -radd64 31..25=0b1000000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -raddw 31..25=0b0010000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -rcras16 31..25=0b0000010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -rcrsa16 31..25=0b0000011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -rstas16 31..25=0b1011010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rstsa16 31..25=0b1011011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rsub8 31..25=0b0000101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -rsub16 31..25=0b0000001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -rsub64 31..25=0b1000001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -rsubw 31..25=0b0010001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -sclip8 31..25=0b1000110 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -sclip16 31..25=0b1000010 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -sclip32 31..25=0b1110010 imm5 rs1 14..12=0b000 rd 6..0=0b1110111 -scmple8 31..25=0b0001111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -scmple16 31..25=0b0001110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -scmplt8 31..25=0b0000111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -scmplt16 31..25=0b0000110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sll8 31..25=0b0101110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -slli8 31..25=0b0111110 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -sll16 31..25=0b0101010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -slli16 31..25=0b0111010 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -smal 31..25=0b0101111 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalbb 31..25=0b1000100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalbt 31..25=0b1001100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smaltt 31..25=0b1010100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalda 31..25=0b1000110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalxda 31..25=0b1001110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalds 31..25=0b1000101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smaldrs 31..25=0b1001101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smalxds 31..25=0b1010101 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smar64 31..25=0b1000010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smaqa 31..25=0b1100100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smaqa.su 31..25=0b1100101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smax8 31..25=0b1000101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smax16 31..25=0b1000001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smbb16 31..25=0b0000100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smbt16 31..25=0b0001100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smtt16 31..25=0b0010100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smds 31..25=0b0101100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smdrs 31..25=0b0110100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smxds 31..25=0b0111100 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smin8 31..25=0b1000100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smin16 31..25=0b1000000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smmul 31..25=0b0100000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smmul.u 31..25=0b0101000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smmwb 31..25=0b0100010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smmwb.u 31..25=0b0101010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smmwt 31..25=0b0110010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smmwt.u 31..25=0b0111010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smslda 31..25=0b1010110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smslxda 31..25=0b1011110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smsr64 31..25=0b1000011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -smul8 31..25=0b1010100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smulx8 31..25=0b1010101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smul16 31..25=0b1010000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -smulx16 31..25=0b1010001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sra.u 31..25=0b0010010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -srai.u 31..26=0b110101 imm6 rs1 14..12=0b001 rd 6..0=0b1110111 -sra8 31..25=0b0101100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sra8.u 31..25=0b0110100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srai8 31..25=0b0111100 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -srai8.u 31..25=0b0111100 24..23=0b01 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -sra16 31..25=0b0101000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sra16.u 31..25=0b0110000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srai16 31..25=0b0111000 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -srai16.u 31..25=0b0111000 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -srl8 31..25=0b0101101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srl8.u 31..25=0b0110101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srli8 31..25=0b0111101 24..23=0b00 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -srli8.u 31..25=0b0111101 24..23=0b01 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -srl16 31..25=0b0101001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srl16.u 31..25=0b0110001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -srli16 31..25=0b0111001 24=0b0 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -srli16.u 31..25=0b0111001 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -stas16 31..25=0b1111010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -stsa16 31..25=0b1111011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -sub8 31..25=0b0100101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sub16 31..25=0b0100001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -sunpkd810 31..25=0b1010110 24..20=0b01000 rs1 14..12=0b000 rd 6..0=0b1110111 -sunpkd820 31..25=0b1010110 24..20=0b01001 rs1 14..12=0b000 rd 6..0=0b1110111 -sunpkd830 31..25=0b1010110 24..20=0b01010 rs1 14..12=0b000 rd 6..0=0b1110111 -sunpkd831 31..25=0b1010110 24..20=0b01011 rs1 14..12=0b000 rd 6..0=0b1110111 -sunpkd832 31..25=0b1010110 24..20=0b10011 rs1 14..12=0b000 rd 6..0=0b1110111 -swap8 31..25=0b1010110 24..20=0b11000 rs1 14..12=0b000 rd 6..0=0b1110111 -uclip8 31..25=0b1000110 24..23=0b10 imm3 rs1 14..12=0b000 rd 6..0=0b1110111 -uclip16 31..25=0b1000010 24=0b1 imm4 rs1 14..12=0b000 rd 6..0=0b1110111 -uclip32 31..25=0b1111010 imm5 rs1 14..12=0b000 rd 6..0=0b1110111 -ucmple8 31..25=0b0011111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ucmple16 31..25=0b0011110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ucmplt8 31..25=0b0010111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ucmplt16 31..25=0b0010110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukadd8 31..25=0b0011100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukadd16 31..25=0b0011000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukadd64 31..25=0b1011000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ukaddh 31..25=0b0001010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ukaddw 31..25=0b0001000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ukcras16 31..25=0b0011010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukcrsa16 31..25=0b0011011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ukmar64 31..25=0b1011010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ukmsr64 31..25=0b1011011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ukstas16 31..25=0b1110010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ukstsa16 31..25=0b1110011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -uksub8 31..25=0b0011101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uksub16 31..25=0b0011001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uksub64 31..25=0b1011001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -uksubh 31..25=0b0001011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -uksubw 31..25=0b0001001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -umar64 31..25=0b1010010 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -umaqa 31..25=0b1100110 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umax8 31..25=0b1001101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umax16 31..25=0b1001001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umin8 31..25=0b1001100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umin16 31..25=0b1001000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umsr64 31..25=0b1010011 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -umul8 31..25=0b1011100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umulx8 31..25=0b1011101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umul16 31..25=0b1011000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -umulx16 31..25=0b1011001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uradd8 31..25=0b0010100 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uradd16 31..25=0b0010000 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -uradd64 31..25=0b1010000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -uraddw 31..25=0b0011000 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -urcras16 31..25=0b0010010 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -urcrsa16 31..25=0b0010011 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -urstas16 31..25=0b1101010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -urstsa16 31..25=0b1101011 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -ursub8 31..25=0b0010101 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ursub16 31..25=0b0010001 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -ursub64 31..25=0b1010001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -ursubw 31..25=0b0011001 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 -wexti 31..25=0b1101111 imm5 rs1 14..12=0b000 rd 6..0=0b1110111 -wext 31..25=0b1100111 rs2 rs1 14..12=0b000 rd 6..0=0b1110111 -zunpkd810 31..25=0b1010110 24..20=0b01100 rs1 14..12=0b000 rd 6..0=0b1110111 -zunpkd820 31..25=0b1010110 24..20=0b01101 rs1 14..12=0b000 rd 6..0=0b1110111 -zunpkd830 31..25=0b1010110 24..20=0b01110 rs1 14..12=0b000 rd 6..0=0b1110111 -zunpkd831 31..25=0b1010110 24..20=0b01111 rs1 14..12=0b000 rd 6..0=0b1110111 -zunpkd832 31..25=0b1010110 24..20=0b10111 rs1 14..12=0b000 rd 6..0=0b1110111 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_pseudo b/riscv_isac/plugins/riscv_opcodes/rv_pseudo deleted file mode 100644 index c186ca5..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_pseudo +++ /dev/null @@ -1,26 +0,0 @@ -$pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrw fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrwi fsflagsi rd zimm 31..20=0x001 14..12=5 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs frrm rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrw fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrwi fsrmi rd zimm 31..20=0x002 14..12=5 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrw fscsr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs frcsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdcycle rd 19..15=0 31..20=0xC00 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdtime rd 19..15=0 31..20=0xC01 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdinstret rd 19..15=0 31..20=0xC02 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdcycleh rd 19..15=0 31..20=0xC80 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdtimeh rd 19..15=0 31..20=0xC81 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdinstreth rd 19..15=0 31..20=0xC82 14..12=2 6..2=0x1C 1..0=3 - -#Old names for ecall/ebreak -$pseudo_op rv_i::ecall scall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 -$pseudo_op rv_i::ebreak sbreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 - -#Old names for fmv.x.w/fmv.w.x -$pseudo_op rv_f::fmv.x.w fmv.x.s rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 -$pseudo_op rv_f::fmv.w.x fmv.s.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 - -#specialized fences -$pseudo_op rv_i::fence fence.tso 31..28=8 27..24=3 23..20=3 19..15=ignore 14..12=0 11..7=ignore 6..2=0x03 1..0=3 -$pseudo_op rv_i::fence pause 31..28=0 27..24=1 23..20=0 19..15=0 14..12=0 11..7=0 6..2=0x03 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_q b/riscv_isac/plugins/riscv_opcodes/rv_q deleted file mode 100644 index 298ae87..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_q +++ /dev/null @@ -1,28 +0,0 @@ -flq rd rs1 imm12 14..12=4 6..2=0x01 1..0=3 -fsq imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x09 1..0=3 -fmadd.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x10 1..0=3 -fmsub.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x11 1..0=3 -fnmsub.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x12 1..0=3 -fnmadd.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x13 1..0=3 -fadd.q rd rs1 rs2 31..27=0x00 rm 26..25=3 6..2=0x14 1..0=3 -fsub.q rd rs1 rs2 31..27=0x01 rm 26..25=3 6..2=0x14 1..0=3 -fmul.q rd rs1 rs2 31..27=0x02 rm 26..25=3 6..2=0x14 1..0=3 -fdiv.q rd rs1 rs2 31..27=0x03 rm 26..25=3 6..2=0x14 1..0=3 -fsqrt.q rd rs1 24..20=0 31..27=0x0B rm 26..25=3 6..2=0x14 1..0=3 -fsgnj.q rd rs1 rs2 31..27=0x04 14..12=0 26..25=3 6..2=0x14 1..0=3 -fsgnjn.q rd rs1 rs2 31..27=0x04 14..12=1 26..25=3 6..2=0x14 1..0=3 -fsgnjx.q rd rs1 rs2 31..27=0x04 14..12=2 26..25=3 6..2=0x14 1..0=3 -fmin.q rd rs1 rs2 31..27=0x05 14..12=0 26..25=3 6..2=0x14 1..0=3 -fmax.q rd rs1 rs2 31..27=0x05 14..12=1 26..25=3 6..2=0x14 1..0=3 -fcvt.s.q rd rs1 24..20=3 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 -fcvt.q.s rd rs1 24..20=0 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 -fcvt.d.q rd rs1 24..20=3 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 -fcvt.q.d rd rs1 24..20=1 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 -feq.q rd rs1 rs2 31..27=0x14 14..12=2 26..25=3 6..2=0x14 1..0=3 -flt.q rd rs1 rs2 31..27=0x14 14..12=1 26..25=3 6..2=0x14 1..0=3 -fle.q rd rs1 rs2 31..27=0x14 14..12=0 26..25=3 6..2=0x14 1..0=3 -fclass.q rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=3 6..2=0x14 1..0=3 -fcvt.w.q rd rs1 24..20=0 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 -fcvt.wu.q rd rs1 24..20=1 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 -fcvt.q.w rd rs1 24..20=0 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 -fcvt.q.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_q_zfh b/riscv_isac/plugins/riscv_opcodes/rv_q_zfh deleted file mode 100644 index 24548d5..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_q_zfh +++ /dev/null @@ -1,2 +0,0 @@ -fcvt.q.h rd rs1 24..20=2 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 -fcvt.h.q rd rs1 24..20=3 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_s b/riscv_isac/plugins/riscv_opcodes/rv_s deleted file mode 100644 index 25f3532..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_s +++ /dev/null @@ -1,3 +0,0 @@ -sfence.vma 11..7=0 rs1 rs2 31..25=0x09 14..12=0 6..2=0x1C 1..0=3 -sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_svinval b/riscv_isac/plugins/riscv_opcodes/rv_svinval deleted file mode 100644 index b35ae7c..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_svinval +++ /dev/null @@ -1,7 +0,0 @@ -# Svinval -sinval.vma 11..7=0 rs1 rs2 31..25=0x0b 14..12=0 6..2=0x1C 1..0=3 -sfence.w.inval 11..7=0 19..15=0x0 24..20=0x0 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 -sfence.inval.ir 11..7=0 19..15=0x0 24..20=0x1 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 -hinval.vvma 11..7=0 rs1 rs2 31..25=0x13 14..12=0 6..2=0x1C 1..0=3 -hinval.gvma 11..7=0 rs1 rs2 31..25=0x33 14..12=0 6..2=0x1C 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_system b/riscv_isac/plugins/riscv_opcodes/rv_system deleted file mode 100644 index f94c4cf..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_system +++ /dev/null @@ -1,5 +0,0 @@ -# SYSTEM -mret 11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3 -dret 11..7=0 19..15=0 31..20=0x7b2 14..12=0 6..2=0x1C 1..0=3 -wfi 11..7=0 19..15=0 31..20=0x105 14..12=0 6..2=0x1C 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_v b/riscv_isac/plugins/riscv_opcodes/rv_v deleted file mode 100644 index 29a0ff8..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_v +++ /dev/null @@ -1,528 +0,0 @@ -# format of a line in this file: -# -# -# is given by specifying one or more range/value pairs: -# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) -# -# is one of vd, vs3, vs1, vs2, vm, nf, wd, simm5, zimm10, zimm11 - -# configuration setting -# https://github.com/riscv/riscv-v-spec/blob/master/vcfg-format.adoc -vsetivli 31=1 30=1 zimm10 zimm 14..12=0x7 rd 6..0=0x57 -vsetvli 31=0 zimm11 rs1 14..12=0x7 rd 6..0=0x57 -vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57 - -# -# Vector Loads and Store -# https://github.com/riscv/riscv-v-spec/blob/master/vmem-format.adoc -# -# Vector Unit-Stride Instructions (including segment part) -# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#74-vector-unit-stride-instructions -vlm.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 -vsm.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 -vle8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 -vle16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 -vle32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 -vle64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07 -vle128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 -vle256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 -vle512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 -vle1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07 -vse8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27 -vse16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27 -vse32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27 -vse64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27 -vse128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27 -vse256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27 -vse512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27 -vse1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27 - -# Vector Indexed-Unordered Instructions (including segment part) -# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions -vluxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 -vluxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 -vluxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 -vluxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 -vluxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 -vluxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 -vluxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 -vluxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 -vsuxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 -vsuxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 -vsuxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 -vsuxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 -vsuxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 -vsuxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 -vsuxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 -vsuxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 - -# Vector Strided Instructions (including segment part) -# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#75-vector-strided-instructions -vlse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07 -vlse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07 -vlse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07 -vlse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07 -vlse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07 -vlse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07 -vlse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07 -vlse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07 -vsse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27 -vsse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27 -vsse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27 -vsse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27 -vsse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27 -vsse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27 -vsse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27 -vsse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27 - -# Vector Indexed-Ordered Instructions (including segment part) -# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions -vloxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 -vloxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 -vloxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 -vloxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 -vloxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 -vloxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 -vloxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 -vloxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 -vsoxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 -vsoxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 -vsoxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 -vsoxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 -vsoxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 -vsoxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 -vsoxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 -vsoxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 - -# Unit-stride F31..29=0ault-Only-First Loads -# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#77-unit-stride-fault-only-first-loads -vle8ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 -vle16ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 -vle32ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 -vle64ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 -vle128ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 -vle256ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 -vle512ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 -vle1024ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 - -# Vector Load/Store Whole Registers -# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#79-vector-loadstore-whole-register-instructions -vl1re8.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 -vl1re16.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 -vl1re32.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 -vl1re64.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 -vl2re8.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 -vl2re16.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 -vl2re32.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 -vl2re64.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 -vl4re8.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 -vl4re16.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 -vl4re32.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 -vl4re64.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 -vl8re8.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 -vl8re16.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 -vl8re32.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 -vl8re64.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 -vs1r.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 -vs2r.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 -vs4r.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 -vs8r.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 - -# Vector Floating-Point Instructions -# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#14-vector-floating-point-instructions -# OPFVF -vfadd.vf 31..26=0x00 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfsub.vf 31..26=0x02 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmin.vf 31..26=0x04 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmax.vf 31..26=0x06 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfsgnj.vf 31..26=0x08 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfsgnjn.vf 31..26=0x09 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfsgnjx.vf 31..26=0x0a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfslide1up.vf 31..26=0x0e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfslide1down.vf 31..26=0x0f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmv.s.f 31..26=0x10 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 - -vfmerge.vfm 31..26=0x17 25=0 vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmv.v.f 31..26=0x17 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 -vmfeq.vf 31..26=0x18 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vmfle.vf 31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vmflt.vf 31..26=0x1b vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vmfne.vf 31..26=0x1c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vmfgt.vf 31..26=0x1d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vmfge.vf 31..26=0x1f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 - -vfdiv.vf 31..26=0x20 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfrdiv.vf 31..26=0x21 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmul.vf 31..26=0x24 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfrsub.vf 31..26=0x27 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmadd.vf 31..26=0x28 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfnmadd.vf 31..26=0x29 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmsub.vf 31..26=0x2a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfnmsub.vf 31..26=0x2b vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmacc.vf 31..26=0x2c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfnmacc.vf 31..26=0x2d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfmsac.vf 31..26=0x2e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfnmsac.vf 31..26=0x2f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 - -vfwadd.vf 31..26=0x30 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwsub.vf 31..26=0x32 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwadd.wf 31..26=0x34 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwsub.wf 31..26=0x36 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwmul.vf 31..26=0x38 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwmacc.vf 31..26=0x3c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwnmacc.vf 31..26=0x3d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwmsac.vf 31..26=0x3e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 -vfwnmsac.vf 31..26=0x3f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 - -# OPFVV -vfadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfredusum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfredosum.vs 31..26=0x03 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmin.vv 31..26=0x04 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmax.vv 31..26=0x06 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfsgnj.vv 31..26=0x08 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfsgnjn.vv 31..26=0x09 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfsgnjx.vv 31..26=0x0a vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmv.f.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x1 rd 6..0=0x57 - -vmfeq.vv 31..26=0x18 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vmfle.vv 31..26=0x19 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vmflt.vv 31..26=0x1b vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vmfne.vv 31..26=0x1c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 - -vfdiv.vv 31..26=0x20 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmul.vv 31..26=0x24 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmadd.vv 31..26=0x28 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfnmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmsub.vv 31..26=0x2a vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmacc.vv 31..26=0x2c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfnmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfmsac.vv 31..26=0x2e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 - -vfcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 -vfcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x01 14..12=0x1 vd 6..0=0x57 -vfcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x02 14..12=0x1 vd 6..0=0x57 -vfcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x03 14..12=0x1 vd 6..0=0x57 -vfcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x06 14..12=0x1 vd 6..0=0x57 -vfcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x07 14..12=0x1 vd 6..0=0x57 - -vfwcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x08 14..12=0x1 vd 6..0=0x57 -vfwcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x09 14..12=0x1 vd 6..0=0x57 -vfwcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x0A 14..12=0x1 vd 6..0=0x57 -vfwcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x0B 14..12=0x1 vd 6..0=0x57 -vfwcvt.f.f.v 31..26=0x12 vm vs2 19..15=0x0C 14..12=0x1 vd 6..0=0x57 -vfwcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x0E 14..12=0x1 vd 6..0=0x57 -vfwcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x0F 14..12=0x1 vd 6..0=0x57 - -vfncvt.xu.f.w 31..26=0x12 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 -vfncvt.x.f.w 31..26=0x12 vm vs2 19..15=0x11 14..12=0x1 vd 6..0=0x57 -vfncvt.f.xu.w 31..26=0x12 vm vs2 19..15=0x12 14..12=0x1 vd 6..0=0x57 -vfncvt.f.x.w 31..26=0x12 vm vs2 19..15=0x13 14..12=0x1 vd 6..0=0x57 -vfncvt.f.f.w 31..26=0x12 vm vs2 19..15=0x14 14..12=0x1 vd 6..0=0x57 -vfncvt.rod.f.f.w 31..26=0x12 vm vs2 19..15=0x15 14..12=0x1 vd 6..0=0x57 -vfncvt.rtz.xu.f.w 31..26=0x12 vm vs2 19..15=0x16 14..12=0x1 vd 6..0=0x57 -vfncvt.rtz.x.f.w 31..26=0x12 vm vs2 19..15=0x17 14..12=0x1 vd 6..0=0x57 - -vfsqrt.v 31..26=0x13 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 -vfrsqrt7.v 31..26=0x13 vm vs2 19..15=0x04 14..12=0x1 vd 6..0=0x57 -vfrec7.v 31..26=0x13 vm vs2 19..15=0x05 14..12=0x1 vd 6..0=0x57 -vfclass.v 31..26=0x13 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 - -vfwadd.vv 31..26=0x30 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwredusum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwsub.vv 31..26=0x32 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwredosum.vs 31..26=0x33 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwadd.wv 31..26=0x34 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwsub.wv 31..26=0x36 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwmul.vv 31..26=0x38 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwmacc.vv 31..26=0x3c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwnmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwmsac.vv 31..26=0x3e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 -vfwnmsac.vv 31..26=0x3f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 - -# OPIVX -vadd.vx 31..26=0x00 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vsub.vx 31..26=0x02 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vrsub.vx 31..26=0x03 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vminu.vx 31..26=0x04 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmin.vx 31..26=0x05 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmaxu.vx 31..26=0x06 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmax.vx 31..26=0x07 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vand.vx 31..26=0x09 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vor.vx 31..26=0x0a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vxor.vx 31..26=0x0b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vrgather.vx 31..26=0x0c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vslideup.vx 31..26=0x0e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vslidedown.vx 31..26=0x0f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 - -vadc.vxm 31..26=0x10 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmadc.vxm 31..26=0x11 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmadc.vx 31..26=0x11 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vsbc.vxm 31..26=0x12 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsbc.vxm 31..26=0x13 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsbc.vx 31..26=0x13 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmerge.vxm 31..26=0x17 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmv.v.x 31..26=0x17 25=1 24..20=0 rs1 14..12=0x4 vd 6..0=0x57 -vmseq.vx 31..26=0x18 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsne.vx 31..26=0x19 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsltu.vx 31..26=0x1a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmslt.vx 31..26=0x1b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsleu.vx 31..26=0x1c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsle.vx 31..26=0x1d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsgtu.vx 31..26=0x1e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vmsgt.vx 31..26=0x1f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 - -vsaddu.vx 31..26=0x20 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vsadd.vx 31..26=0x21 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vssubu.vx 31..26=0x22 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vssub.vx 31..26=0x23 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vsll.vx 31..26=0x25 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vsmul.vx 31..26=0x27 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vsrl.vx 31..26=0x28 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vsra.vx 31..26=0x29 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vssrl.vx 31..26=0x2a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vssra.vx 31..26=0x2b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vnsrl.wx 31..26=0x2c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vnsra.wx 31..26=0x2d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vnclipu.wx 31..26=0x2e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 -vnclip.wx 31..26=0x2f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 - -# OPIVV -vadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vminu.vv 31..26=0x04 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmin.vv 31..26=0x05 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmaxu.vv 31..26=0x06 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmax.vv 31..26=0x07 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vand.vv 31..26=0x09 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vor.vv 31..26=0x0a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vxor.vv 31..26=0x0b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vrgather.vv 31..26=0x0c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vrgatherei16.vv 31..26=0x0e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 - -vadc.vvm 31..26=0x10 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmadc.vvm 31..26=0x11 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmadc.vv 31..26=0x11 25=1 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vsbc.vvm 31..26=0x12 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmsbc.vvm 31..26=0x13 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmsbc.vv 31..26=0x13 25=1 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmerge.vvm 31..26=0x17 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmv.v.v 31..26=0x17 25=1 24..20=0 vs1 14..12=0x0 vd 6..0=0x57 -vmseq.vv 31..26=0x18 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmsne.vv 31..26=0x19 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmsltu.vv 31..26=0x1a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmslt.vv 31..26=0x1b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmsleu.vv 31..26=0x1c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vmsle.vv 31..26=0x1d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 - -vsaddu.vv 31..26=0x20 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vsadd.vv 31..26=0x21 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vssubu.vv 31..26=0x22 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vssub.vv 31..26=0x23 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vsll.vv 31..26=0x25 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vsmul.vv 31..26=0x27 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vsrl.vv 31..26=0x28 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vsra.vv 31..26=0x29 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vssrl.vv 31..26=0x2a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vssra.vv 31..26=0x2b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vnsrl.wv 31..26=0x2c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vnsra.wv 31..26=0x2d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vnclipu.wv 31..26=0x2e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vnclip.wv 31..26=0x2f vm vs2 vs1 14..12=0x0 vd 6..0=0x57 - -vwredsumu.vs 31..26=0x30 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 -vwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 - -# OPIVI -vadd.vi 31..26=0x00 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vrsub.vi 31..26=0x03 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vand.vi 31..26=0x09 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vor.vi 31..26=0x0a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vxor.vi 31..26=0x0b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vrgather.vi 31..26=0x0c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vslideup.vi 31..26=0x0e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vslidedown.vi 31..26=0x0f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 - -vadc.vim 31..26=0x10 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmadc.vim 31..26=0x11 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmadc.vi 31..26=0x11 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmerge.vim 31..26=0x17 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmv.v.i 31..26=0x17 25=1 24..20=0 simm5 14..12=0x3 vd 6..0=0x57 -vmseq.vi 31..26=0x18 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmsne.vi 31..26=0x19 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmsleu.vi 31..26=0x1c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmsle.vi 31..26=0x1d vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmsgtu.vi 31..26=0x1e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmsgt.vi 31..26=0x1f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 - -vsaddu.vi 31..26=0x20 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vsadd.vi 31..26=0x21 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vsll.vi 31..26=0x25 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vmv1r.v 31..26=0x27 25=1 vs2 19..15=0 14..12=0x3 vd 6..0=0x57 -vmv2r.v 31..26=0x27 25=1 vs2 19..15=1 14..12=0x3 vd 6..0=0x57 -vmv4r.v 31..26=0x27 25=1 vs2 19..15=3 14..12=0x3 vd 6..0=0x57 -vmv8r.v 31..26=0x27 25=1 vs2 19..15=7 14..12=0x3 vd 6..0=0x57 -vsrl.vi 31..26=0x28 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vsra.vi 31..26=0x29 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vssrl.vi 31..26=0x2a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vssra.vi 31..26=0x2b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vnsrl.wi 31..26=0x2c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vnsra.wi 31..26=0x2d vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vnclipu.wi 31..26=0x2e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 -vnclip.wi 31..26=0x2f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 - -# OPMVV -vredsum.vs 31..26=0x00 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vredand.vs 31..26=0x01 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vredor.vs 31..26=0x02 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vredxor.vs 31..26=0x03 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vredminu.vs 31..26=0x04 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vredmaxu.vs 31..26=0x06 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vaaddu.vv 31..26=0x08 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vaadd.vv 31..26=0x09 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vasubu.vv 31..26=0x0a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vasub.vv 31..26=0x0b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 - -vmv.x.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x2 rd 6..0=0x57 - -# Vector Integer Extension Instructions -# https://github.com/riscv/riscv-v-spec/blob/e49574c92b072fd4d71e6cb20f7e8154de5b83fe/v-spec.adoc#123-vector-integer-extension -vzext.vf8 31..26=0x12 vm vs2 19..15=2 14..12=0x2 vd 6..0=0x57 -vsext.vf8 31..26=0x12 vm vs2 19..15=3 14..12=0x2 vd 6..0=0x57 -vzext.vf4 31..26=0x12 vm vs2 19..15=4 14..12=0x2 vd 6..0=0x57 -vsext.vf4 31..26=0x12 vm vs2 19..15=5 14..12=0x2 vd 6..0=0x57 -vzext.vf2 31..26=0x12 vm vs2 19..15=6 14..12=0x2 vd 6..0=0x57 -vsext.vf2 31..26=0x12 vm vs2 19..15=7 14..12=0x2 vd 6..0=0x57 - -vcompress.vm 31..26=0x17 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmandn.mm 31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmand.mm 31..26=0x19 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmor.mm 31..26=0x1a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmxor.mm 31..26=0x1b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmorn.mm 31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmnand.mm 31..26=0x1d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmnor.mm 31..26=0x1e vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmxnor.mm 31..26=0x1f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 - -vmsbf.m 31..26=0x14 vm vs2 19..15=0x01 14..12=0x2 vd 6..0=0x57 -vmsof.m 31..26=0x14 vm vs2 19..15=0x02 14..12=0x2 vd 6..0=0x57 -vmsif.m 31..26=0x14 vm vs2 19..15=0x03 14..12=0x2 vd 6..0=0x57 -viota.m 31..26=0x14 vm vs2 19..15=0x10 14..12=0x2 vd 6..0=0x57 -vid.v 31..26=0x14 vm 24..20=0 19..15=0x11 14..12=0x2 vd 6..0=0x57 -vcpop.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 -vfirst.m 31..26=0x10 vm vs2 19..15=0x11 14..12=0x2 rd 6..0=0x57 - -vdivu.vv 31..26=0x20 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vdiv.vv 31..26=0x21 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vremu.vv 31..26=0x22 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vrem.vv 31..26=0x23 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmulhu.vv 31..26=0x24 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmul.vv 31..26=0x25 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmulhsu.vv 31..26=0x26 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmulh.vv 31..26=0x27 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 - -vwaddu.vv 31..26=0x30 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwadd.vv 31..26=0x31 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwsubu.vv 31..26=0x32 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwsub.vv 31..26=0x33 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwaddu.wv 31..26=0x34 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwadd.wv 31..26=0x35 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwsubu.wv 31..26=0x36 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwsub.wv 31..26=0x37 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwmulu.vv 31..26=0x38 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwmulsu.vv 31..26=0x3a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwmul.vv 31..26=0x3b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 -vwmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 - -# OPMVX -vaaddu.vx 31..26=0x08 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vaadd.vx 31..26=0x09 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vasubu.vx 31..26=0x0a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vasub.vx 31..26=0x0b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 - -vmv.s.x 31..26=0x10 25=1 24..20=0 rs1 14..12=0x6 vd 6..0=0x57 -vslide1up.vx 31..26=0x0e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vslide1down.vx 31..26=0x0f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 - -vdivu.vx 31..26=0x20 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vdiv.vx 31..26=0x21 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vremu.vx 31..26=0x22 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vrem.vx 31..26=0x23 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vmulhu.vx 31..26=0x24 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vmul.vx 31..26=0x25 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vmulhsu.vx 31..26=0x26 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vmulh.vx 31..26=0x27 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vmadd.vx 31..26=0x29 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vnmsub.vx 31..26=0x2b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vmacc.vx 31..26=0x2d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vnmsac.vx 31..26=0x2f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 - -vwaddu.vx 31..26=0x30 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwadd.vx 31..26=0x31 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwsubu.vx 31..26=0x32 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwsub.vx 31..26=0x33 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwaddu.wx 31..26=0x34 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwadd.wx 31..26=0x35 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwsubu.wx 31..26=0x36 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwsub.wx 31..26=0x37 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwmulu.vx 31..26=0x38 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwmulsu.vx 31..26=0x3a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwmul.vx 31..26=0x3b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwmaccu.vx 31..26=0x3c vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwmacc.vx 31..26=0x3d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 -vwmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 - -# Zvamo -vamoswapei8.v 31..27=0x01 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamoaddei8.v 31..27=0x00 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamoxorei8.v 31..27=0x04 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamoandei8.v 31..27=0x0c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamoorei8.v 31..27=0x08 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamominei8.v 31..27=0x10 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamomaxei8.v 31..27=0x14 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamominuei8.v 31..27=0x18 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f -vamomaxuei8.v 31..27=0x1c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f - -vamoswapei16.v 31..27=0x01 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamoaddei16.v 31..27=0x00 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamoxorei16.v 31..27=0x04 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamoandei16.v 31..27=0x0c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamoorei16.v 31..27=0x08 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamominei16.v 31..27=0x10 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamomaxei16.v 31..27=0x14 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamominuei16.v 31..27=0x18 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f -vamomaxuei16.v 31..27=0x1c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f - -vamoswapei32.v 31..27=0x01 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamoaddei32.v 31..27=0x00 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamoxorei32.v 31..27=0x04 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamoandei32.v 31..27=0x0c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamoorei32.v 31..27=0x08 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamominei32.v 31..27=0x10 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamomaxei32.v 31..27=0x14 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamominuei32.v 31..27=0x18 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f -vamomaxuei32.v 31..27=0x1c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f - -vamoswapei64.v 31..27=0x01 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamoaddei64.v 31..27=0x00 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamoxorei64.v 31..27=0x04 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamoandei64.v 31..27=0x0c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamoorei64.v 31..27=0x08 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamominei64.v 31..27=0x10 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamomaxei64.v 31..27=0x14 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamominuei64.v 31..27=0x18 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f -vamomaxuei64.v 31..27=0x1c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zba b/riscv_isac/plugins/riscv_opcodes/rv_zba deleted file mode 100644 index 65eb420..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zba +++ /dev/null @@ -1,3 +0,0 @@ -sh1add rd rs1 rs2 31..25=16 14..12=2 6..2=0x0C 1..0=3 -sh2add rd rs1 rs2 31..25=16 14..12=4 6..2=0x0C 1..0=3 -sh3add rd rs1 rs2 31..25=16 14..12=6 6..2=0x0C 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbb b/riscv_isac/plugins/riscv_opcodes/rv_zbb deleted file mode 100644 index 9f384f6..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zbb +++ /dev/null @@ -1,15 +0,0 @@ -andn rd rs1 rs2 31..25=32 14..12=7 6..2=0x0C 1..0=3 -orn rd rs1 rs2 31..25=32 14..12=6 6..2=0x0C 1..0=3 -xnor rd rs1 rs2 31..25=32 14..12=4 6..2=0x0C 1..0=3 -clz rd rs1 31..20=0x600 14..12=1 6..2=0x04 1..0=3 -ctz rd rs1 31..20=0x601 14..12=1 6..2=0x04 1..0=3 -cpop rd rs1 31..20=0x602 14..12=1 6..2=0x04 1..0=3 -max rd rs1 rs2 31..25=5 14..12=6 6..2=0x0C 1..0=3 -maxu rd rs1 rs2 31..25=5 14..12=7 6..2=0x0C 1..0=3 -min rd rs1 rs2 31..25=5 14..12=4 6..2=0x0C 1..0=3 -minu rd rs1 rs2 31..25=5 14..12=5 6..2=0x0C 1..0=3 -sext.b rd rs1 31..20=0x604 14..12=1 6..2=0x04 1..0=3 -sext.h rd rs1 31..20=0x605 14..12=1 6..2=0x04 1..0=3 -rol rd rs1 rs2 31..25=0x30 14..12=1 6..2=0x0C 1..0=3 -ror rd rs1 rs2 31..25=0x30 14..12=5 6..2=0x0C 1..0=3 -$pseudo_op rv64_zbp::gorci orc.b rd rs1 31..20=0x287 14..12=0x5 6..0=0x13 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbc b/riscv_isac/plugins/riscv_opcodes/rv_zbc deleted file mode 100644 index c2494bd..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zbc +++ /dev/null @@ -1,4 +0,0 @@ -clmul rd rs1 rs2 31..25=5 14..12=1 6..2=0x0C 1..0=3 -clmulr rd rs1 rs2 31..25=5 14..12=2 6..2=0x0C 1..0=3 -clmulh rd rs1 rs2 31..25=5 14..12=3 6..2=0x0C 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbe b/riscv_isac/plugins/riscv_opcodes/rv_zbe deleted file mode 100644 index 1e8a037..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zbe +++ /dev/null @@ -1,5 +0,0 @@ -bcompress rd rs1 rs2 31..25=4 14..12=6 6..2=0x0C 1..0=3 -bdecompress rd rs1 rs2 31..25=36 14..12=6 6..2=0x0C 1..0=3 -pack rd rs1 rs2 31..25=4 14..12=4 6..2=0x0C 1..0=3 -packh rd rs1 rs2 31..25=4 14..12=7 6..2=0x0C 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbf b/riscv_isac/plugins/riscv_opcodes/rv_zbf deleted file mode 100644 index 33dd0a6..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zbf +++ /dev/null @@ -1,4 +0,0 @@ -bfp rd rs1 rs2 31..25=36 14..12=7 6..2=0x0C 1..0=3 -$import rv_zbe::pack -$import rv_zbe::packh - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbkb b/riscv_isac/plugins/riscv_opcodes/rv_zbkb deleted file mode 100644 index 1499d78..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zbkb +++ /dev/null @@ -1,8 +0,0 @@ -$import rv_zbb::rol -$import rv_zbb::ror -$import rv_zbb::andn -$import rv_zbb::orn -$import rv_zbb::xnor -$import rv_zbe::pack -$import rv_zbe::packh -$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbkc b/riscv_isac/plugins/riscv_opcodes/rv_zbkc deleted file mode 100644 index b82588f..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zbkc +++ /dev/null @@ -1,2 +0,0 @@ -$import rv_zbc::clmul -$import rv_zbc::clmulh diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbkx b/riscv_isac/plugins/riscv_opcodes/rv_zbkx deleted file mode 100644 index b035a6b..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zbkx +++ /dev/null @@ -1,3 +0,0 @@ -# TODO - confirm if below 4 instructions should be imported ops since zbp is not ratified -$import rv_zbp::xperm4 -$import rv_zbp::xperm8 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbp b/riscv_isac/plugins/riscv_opcodes/rv_zbp deleted file mode 100644 index b66d6b4..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zbp +++ /dev/null @@ -1,15 +0,0 @@ -$import rv_zbb::andn -$import rv_zbb::orn -$import rv_zbb::xnor -$import rv_zbe::pack -$import rv_zbe::packh -$import rv_zbb::rol -$import rv_zbb::ror -grev rd rs1 rs2 31..25=52 14..12=5 6..2=0x0C 1..0=3 -gorc rd rs1 rs2 31..25=20 14..12=5 6..2=0x0C 1..0=3 -shfl rd rs1 rs2 31..25=4 14..12=1 6..2=0x0C 1..0=3 -unshfl rd rs1 rs2 31..25=4 14..12=5 6..2=0x0C 1..0=3 -xperm4 rd rs1 rs2 31..25=20 14..12=2 6..2=0x0C 1..0=3 -xperm8 rd rs1 rs2 31..25=20 14..12=4 6..2=0x0C 1..0=3 -xperm16 rd rs1 rs2 31..25=20 14..12=6 6..2=0x0C 1..0=3 -packu rd rs1 rs2 31..25=36 14..12=4 6..2=0x0C 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbpbo b/riscv_isac/plugins/riscv_opcodes/rv_zbpbo deleted file mode 100644 index 356fbb2..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zbpbo +++ /dev/null @@ -1,6 +0,0 @@ -$import rv_zbe::pack -$import rv_zbp::packu -$import rv_zbb::max -$import rv_zbb::min -$import rv_zbt::cmix -$pseudo_op rv64_zbp::grevi rev8.h rd rs1 31..20=0x688 14..12=5 6..0=0x13 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbr b/riscv_isac/plugins/riscv_opcodes/rv_zbr deleted file mode 100644 index 3cfd5a7..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zbr +++ /dev/null @@ -1,7 +0,0 @@ -crc32.b rd rs1 31..20=0x610 14..12=1 6..2=0x04 1..0=3 -crc32.h rd rs1 31..20=0x611 14..12=1 6..2=0x04 1..0=3 -crc32.w rd rs1 31..20=0x612 14..12=1 6..2=0x04 1..0=3 -crc32c.b rd rs1 31..20=0x618 14..12=1 6..2=0x04 1..0=3 -crc32c.h rd rs1 31..20=0x619 14..12=1 6..2=0x04 1..0=3 -crc32c.w rd rs1 31..20=0x61A 14..12=1 6..2=0x04 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbs b/riscv_isac/plugins/riscv_opcodes/rv_zbs deleted file mode 100644 index 1949072..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zbs +++ /dev/null @@ -1,5 +0,0 @@ -bclr rd rs1 rs2 31..25=0x24 14..12=1 6..2=0x0C 1..0=3 -bext rd rs1 rs2 31..25=36 14..12=5 6..2=0x0C 1..0=3 -binv rd rs1 rs2 31..25=52 14..12=1 6..2=0x0C 1..0=3 -bset rd rs1 rs2 31..25=20 14..12=1 6..2=0x0C 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zbt b/riscv_isac/plugins/riscv_opcodes/rv_zbt deleted file mode 100644 index 9e7b98b..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zbt +++ /dev/null @@ -1,6 +0,0 @@ -cmix rd rs1 rs2 rs3 26..25=3 14..12=1 6..2=0x0C 1..0=3 -cmov rd rs1 rs2 rs3 26..25=3 14..12=5 6..2=0x0C 1..0=3 - -fsl rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0C 1..0=3 -fsr rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0C 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zfh b/riscv_isac/plugins/riscv_opcodes/rv_zfh deleted file mode 100644 index 532dde5..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zfh +++ /dev/null @@ -1,30 +0,0 @@ -flh rd rs1 imm12 14..12=1 6..2=0x01 1..0=3 -fsh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x09 1..0=3 -fmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x10 1..0=3 -fmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x11 1..0=3 -fnmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x12 1..0=3 -fnmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x13 1..0=3 -fadd.h rd rs1 rs2 31..27=0x00 rm 26..25=2 6..2=0x14 1..0=3 -fsub.h rd rs1 rs2 31..27=0x01 rm 26..25=2 6..2=0x14 1..0=3 -fmul.h rd rs1 rs2 31..27=0x02 rm 26..25=2 6..2=0x14 1..0=3 -fdiv.h rd rs1 rs2 31..27=0x03 rm 26..25=2 6..2=0x14 1..0=3 -fsqrt.h rd rs1 24..20=0 31..27=0x0B rm 26..25=2 6..2=0x14 1..0=3 -fsgnj.h rd rs1 rs2 31..27=0x04 14..12=0 26..25=2 6..2=0x14 1..0=3 -fsgnjn.h rd rs1 rs2 31..27=0x04 14..12=1 26..25=2 6..2=0x14 1..0=3 -fsgnjx.h rd rs1 rs2 31..27=0x04 14..12=2 26..25=2 6..2=0x14 1..0=3 -fmin.h rd rs1 rs2 31..27=0x05 14..12=0 26..25=2 6..2=0x14 1..0=3 -fmax.h rd rs1 rs2 31..27=0x05 14..12=1 26..25=2 6..2=0x14 1..0=3 -fcvt.s.h rd rs1 24..20=2 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 -fcvt.h.s rd rs1 24..20=0 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 - -feq.h rd rs1 rs2 31..27=0x14 14..12=2 26..25=2 6..2=0x14 1..0=3 -flt.h rd rs1 rs2 31..27=0x14 14..12=1 26..25=2 6..2=0x14 1..0=3 -fle.h rd rs1 rs2 31..27=0x14 14..12=0 26..25=2 6..2=0x14 1..0=3 -fclass.h rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=2 6..2=0x14 1..0=3 -fcvt.w.h rd rs1 24..20=0 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 -fcvt.wu.h rd rs1 24..20=1 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 -fmv.x.h rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=2 6..2=0x14 1..0=3 -fcvt.h.w rd rs1 24..20=0 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 -fcvt.h.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 -fmv.h.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=2 6..2=0x14 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zicbo b/riscv_isac/plugins/riscv_opcodes/rv_zicbo deleted file mode 100644 index 65a4567..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zicbo +++ /dev/null @@ -1,12 +0,0 @@ -# Zicbom: cache-block management instructions -cbo.clean rs1 31..20=1 14..12=2 11..7=0 6..2=0x03 1..0=3 -cbo.flush rs1 31..20=2 14..12=2 11..7=0 6..2=0x03 1..0=3 -cbo.inval rs1 31..20=0 14..12=2 11..7=0 6..2=0x03 1..0=3 - -# Zicboz: cache-block zero instruction -cbo.zero rs1 31..20=4 14..12=2 11..7=0 6..2=0x03 1..0=3 - -# Zicbop: prefetch hint pseudoinstructions -$pseudo_op rv_i::ori prefetch.i rs1 imm12hi 24..20=0 14..12=6 11..7=0 6..2=0x04 1..0=3 -$pseudo_op rv_i::ori prefetch.r rs1 imm12hi 24..20=1 14..12=6 11..7=0 6..2=0x04 1..0=3 -$pseudo_op rv_i::ori prefetch.w rs1 imm12hi 24..20=3 14..12=6 11..7=0 6..2=0x04 1..0=3 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zicsr b/riscv_isac/plugins/riscv_opcodes/rv_zicsr deleted file mode 100644 index 9d54aff..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zicsr +++ /dev/null @@ -1,7 +0,0 @@ -csrrw rd rs1 imm12 14..12=1 6..2=0x1C 1..0=3 -csrrs rd rs1 imm12 14..12=2 6..2=0x1C 1..0=3 -csrrc rd rs1 imm12 14..12=3 6..2=0x1C 1..0=3 -csrrwi rd imm12 zimm 14..12=5 6..2=0x1C 1..0=3 -csrrsi rd imm12 zimm 14..12=6 6..2=0x1C 1..0=3 -csrrci rd imm12 zimm 14..12=7 6..2=0x1C 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zifencei b/riscv_isac/plugins/riscv_opcodes/rv_zifencei deleted file mode 100644 index 8f9ec85..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zifencei +++ /dev/null @@ -1,2 +0,0 @@ -fence.i imm12 rs1 14..12=1 rd 6..2=0x03 1..0=3 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zk b/riscv_isac/plugins/riscv_opcodes/rv_zk deleted file mode 100644 index c4dc854..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zk +++ /dev/null @@ -1,24 +0,0 @@ -# import zbkb -$import rv_zbb::rol -$import rv_zbb::ror -$import rv_zbb::andn -$import rv_zbb::orn -$import rv_zbb::xnor -$import rv_zbe::pack -$import rv_zbe::packh -$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 - -#import zbkc -$import rv_zbc::clmul -$import rv_zbc::clmulh - -#import zbkx -$import rv_zbp::xperm4 -$import rv_zbp::xperm8 - -#import zknh -# Scalar SHA256 - RV32/RV64 -$import rv_zknh::sha256sum0 -$import rv_zknh::sha256sum1 -$import rv_zknh::sha256sig0 -$import rv_zknh::sha256sig1 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zkn b/riscv_isac/plugins/riscv_opcodes/rv_zkn deleted file mode 100644 index c4dc854..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zkn +++ /dev/null @@ -1,24 +0,0 @@ -# import zbkb -$import rv_zbb::rol -$import rv_zbb::ror -$import rv_zbb::andn -$import rv_zbb::orn -$import rv_zbb::xnor -$import rv_zbe::pack -$import rv_zbe::packh -$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 - -#import zbkc -$import rv_zbc::clmul -$import rv_zbc::clmulh - -#import zbkx -$import rv_zbp::xperm4 -$import rv_zbp::xperm8 - -#import zknh -# Scalar SHA256 - RV32/RV64 -$import rv_zknh::sha256sum0 -$import rv_zknh::sha256sum1 -$import rv_zknh::sha256sig0 -$import rv_zknh::sha256sig1 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zknh b/riscv_isac/plugins/riscv_opcodes/rv_zknh deleted file mode 100644 index 2079628..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zknh +++ /dev/null @@ -1,5 +0,0 @@ -# Scalar SHA256 - RV32/RV64 -sha256sum0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00000 14..12=1 6..0=0x13 -sha256sum1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00001 14..12=1 6..0=0x13 -sha256sig0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00010 14..12=1 6..0=0x13 -sha256sig1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00011 14..12=1 6..0=0x13 diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zks b/riscv_isac/plugins/riscv_opcodes/rv_zks deleted file mode 100644 index f88a09b..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zks +++ /dev/null @@ -1,26 +0,0 @@ -# import zbkb -$import rv_zbb::rol -$import rv_zbb::ror -$import rv_zbb::andn -$import rv_zbb::orn -$import rv_zbb::xnor -$import rv_zbe::pack -$import rv_zbe::packh -$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 - -#import zbkc -$import rv_zbc::clmul -$import rv_zbc::clmulh - -#import zbkx -$import rv_zbp::xperm4 -$import rv_zbp::xperm8 - -# Scalar SM4 - RV32, RV64 -$import rv_zksed::sm4ed -$import rv_zksed::sm4ks - -# Scalar SM3 - RV32, RV64 -$import rv_zksh::sm3p0 -$import rv_zksh::sm3p1 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zksed b/riscv_isac/plugins/riscv_opcodes/rv_zksed deleted file mode 100644 index 92e17c5..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zksed +++ /dev/null @@ -1,4 +0,0 @@ -# Scalar SM4 - RV32, RV64 -sm4ed rd rs1 rs2 bs 29..25=0b11000 14..12=0 6..0=0x33 -sm4ks rd rs1 rs2 bs 29..25=0b11010 14..12=0 6..0=0x33 - diff --git a/riscv_isac/plugins/riscv_opcodes/rv_zksh b/riscv_isac/plugins/riscv_opcodes/rv_zksh deleted file mode 100644 index f21eaa8..0000000 --- a/riscv_isac/plugins/riscv_opcodes/rv_zksh +++ /dev/null @@ -1,4 +0,0 @@ -# Scalar SM3 - RV32, RV64 -sm3p0 rd rs1 31..30=0 29..25=0b01000 24..20=0b01000 14..12=1 6..0=0x13 -sm3p1 rd rs1 31..30=0 29..25=0b01000 24..20=0b01001 14..12=1 6..0=0x13 - diff --git a/riscv_isac/plugins/rv_opcodes_decoder.py b/riscv_isac/plugins/rvopcodesdecoder.py similarity index 65% rename from riscv_isac/plugins/rv_opcodes_decoder.py rename to riscv_isac/plugins/rvopcodesdecoder.py index 30631dc..f5ee8e8 100644 --- a/riscv_isac/plugins/rv_opcodes_decoder.py +++ b/riscv_isac/plugins/rvopcodesdecoder.py @@ -4,22 +4,21 @@ import pprint from statistics import mode -from ruamel import yaml as YAML - from constants import * from riscv_isac.InstructionObject import instructionObject +from riscv_isac.plugins import internaldecoder from riscv_isac.plugins.internaldecoder import disassembler -#export PYTHONPATH=/home/edwin/myrepos/riscv-isac/ +import riscv_isac.plugins as plugins # Closure to get argument value -# TODO Handle special immediates def get_arg_val(arg: str): (msb, lsb) = arg_lut[arg] - mask = int(''.join('1' * (msb - lsb + 1)), 2) << lsb + len = msb - lsb + 1 + mask = int(''.join('1' * (len)), 2) << lsb def mcode_in(mcode: int): val = (mask & mcode) >> lsb - return val + return f'{val:0{len}b}' return mcode_in # Functs handler @@ -38,12 +37,12 @@ class rvOpcodesDecoder: INST_LIST = [] - def __init__(self, file_filter: str): + @plugins.decoderHookImpl + def setup(self, file_filter: str): - # Create nested dictionary + # Create nested dictionary based on file_filter specified nested_dict = lambda: defaultdict(nested_dict) rvOpcodesDecoder.INST_DICT = nested_dict() - rvOpcodesDecoder.create_inst_dict(file_filter) def process_enc_line(line: str): @@ -55,7 +54,7 @@ def process_enc_line(line: str): [name, remaining] = line.split(' ', 1) # replace dots with underscores as dot doesn't work with C/Sverilog, etc - name = name.replace('.', '_') + name = name # remove leading whitespaces remaining = remaining.lstrip() @@ -95,6 +94,14 @@ def process_enc_line(line: str): return (functs, (name, args)) def create_inst_dict(file_filter): + ''' + Gathers files and generates instruciton list from the filter given + + Input: + file_filter: (string) A file filter + ''' + + # Default riscv-opcodes directory opcodes_dir = f'./riscv_opcodes/' # file_names contains all files to be parsed in the riscv-opcodes directory @@ -104,19 +111,15 @@ def create_inst_dict(file_filter): for f in file_names: with open(f) as fp: lines = (line.rstrip() - for line in fp) # All lines including the blank ones - lines = list(line for line in lines if line) # Non-blank lines + for line in fp) # All lines including the blank ones + lines = list(line for line in lines if line) # Non-blank lines lines = list( line for line in lines - if not line.startswith("#")) # remove comment lines + if not line.startswith("#")) # Remove comment lines # go through each line of the file for line in lines: - # if the an instruction needs to be imported then go to the - # respective file and pick the line that has the instruction. - # The variable 'line' will now point to the new line from the - # imported file - + # ignore all lines starting with $import and $pseudo if '$import' in line or '$pseudo' in line: continue @@ -125,11 +128,18 @@ def create_inst_dict(file_filter): # [ [(funct, val)], name, [args] ] rvOpcodesDecoder.INST_LIST.append([functs, name, args]) - + + # Insert all instructions to the root of the dictionary rvOpcodesDecoder.INST_DICT['root'] = rvOpcodesDecoder.INST_LIST + + # Generate dictionary rvOpcodesDecoder.build_instr_dict(rvOpcodesDecoder.INST_DICT) def build_instr_dict(inst_dict): + ''' + This function recursively generates the dictionary based on + highest occurrence of functs in a particular path + ''' # Get all instructions in the level val = inst_dict['root'] @@ -180,9 +190,7 @@ def build_instr_dict(inst_dict): else: # Append name and args temp_dict[temp[1]] = temp[2] - i = i - 1 - i = i + 1 else: # Remove previous root @@ -199,6 +207,9 @@ def build_instr_dict(inst_dict): return def get_instr(func_dict, mcode: int): + ''' + Recursively extracts the instruction from the dictionary + ''' # Get list of functions keys = func_dict.keys() for key in keys: @@ -216,8 +227,18 @@ def get_instr(func_dict, mcode: int): else: continue - def decoder(self, temp_instrobj: instructionObject): - + @plugins.decoderHookImpl + def decode(self, temp_instrobj: instructionObject): + ''' + Take an instruction object with just machine code and fill + the instruction name and argument fields + + Input: + temp_instrobj: (instructionObject) + Returns: + (instructionObject) : Instruction object with names and arguments filled + None : When the dissassembler fails to decode the machine code + ''' mcode = temp_instrobj.instr @@ -235,109 +256,86 @@ def decoder(self, temp_instrobj: instructionObject): imm = '' for arg in args: if arg == 'rd': - temp_instrobj.rd = get_arg_val(arg)(mcode) + temp_instrobj.rd = int(get_arg_val(arg)(mcode), 2) if arg == 'rs1': - temp_instrobj.rs1 = get_arg_val(arg)(mcode) + temp_instrobj.rs1 = int(get_arg_val(arg)(mcode), 2) if arg == 'rs2': - temp_instrobj.rs2 = get_arg_val(arg)(mcode) + temp_instrobj.rs2 = int(get_arg_val(arg)(mcode), 2) if arg == 'rs3': - temp_instrobj.rs3 = get_arg_val(arg)(mcode) + temp_instrobj.rs3 = int(get_arg_val(arg)(mcode), 2) if arg == 'csr': - temp_instrobj.csr = get_arg_val(arg)(mcode) + temp_instrobj.csr = int(get_arg_val(arg)(mcode), 2) if arg == 'shamt': - temp_instrobj.shamt = get_arg_val(arg)(mcode) + temp_instrobj.shamt = int(get_arg_val(arg)(mcode), 2) if arg == 'succ': - temp_instrobj.succ = get_arg_val(arg)(mcode) + temp_instrobj.succ = int(get_arg_val(arg)(mcode), 2) if arg == 'pred': - temp_instrobj.pred = get_arg_val(arg)(mcode) + temp_instrobj.pred = int(get_arg_val(arg)(mcode), 2) if arg == 'rl': - temp_instrobj.rl = get_arg_val(arg)(mcode) + temp_instrobj.rl = int(get_arg_val(arg)(mcode), 2) if arg == 'aq': - temp_instrobj.aq = get_arg_val(arg)(mcode) + temp_instrobj.aq = int(get_arg_val(arg)(mcode), 2) if arg == 'rm': - temp_instrobj.rm = get_arg_val(arg)(mcode) - - if arg in ['imm12', 'imm20', 'zimm', 'imm2', 'imm3', 'imm4', 'imm5', 'imm']: - temp_instrobj.imm = get_arg_val(arg)(mcode) - if arg == 'jimm20': - imm_temp = get_arg_val(arg)(mcode) - print(imm_temp) - imm_temp = f'{imm_temp:0{20}b}' - #imm_temp = '123456789abcdefghijkl' - print(imm_temp) - imm = imm_temp[0] + imm_temp[12:21] + imm_temp[12] + imm_temp[1:11] - print(imm) - temp_instrobj.imm = int(imm, 2) + temp_instrobj.rm = int(get_arg_val(arg)(mcode), 2) + + if arg.find('imm') != -1: + if arg in ['imm12', 'imm20', 'zimm', 'imm2', 'imm3', 'imm4', 'imm5']: + imm = get_arg_val(arg)(mcode) + if arg == 'jimm20': + imm_temp = get_arg_val(arg)(mcode) + imm = imm_temp[0] + imm_temp[12:21] + imm_temp[11] + imm_temp[1:11] + '0' + if arg == 'imm12hi': + imm_temp = get_arg_val(arg)(mcode) + imm = imm_temp + imm + if arg == 'imm12lo': + imm_temp = get_arg_val(arg)(mcode) + imm = imm + imm_temp + if arg == 'bimm12hi': + imm_temp = get_arg_val(arg)(mcode) + + if imm: + imm = imm_temp[0] + imm[-1] + imm_temp[1:] + imm[0:4] + '0' + else: + imm = imm_temp + imm + if arg == 'bimm12lo': + imm_temp = get_arg_val(arg)(mcode) + if imm: + imm = imm[0] + imm_temp[-1] + imm[1:] + imm_temp[0:4] + '0' + else: + imm = imm + imm_temp + if imm: + numbits = len(imm) + temp_instrobj.imm = rvOpcodesDecoder.twos_comp(int(imm, 2), numbits) + return temp_instrobj - else: print('Found two instructions in the leaf node') + # Utility function + def twos_comp(val, bits): + ''' + Get the two_complement value + ''' + if (val & (1 << (bits - 1))) != 0: + val = val - (1 << bits) + return val + def default_to_regular(d): + ''' + Utility function to convert nested defaultdict to regular dict + ''' if isinstance(d, defaultdict): d = {k: rvOpcodesDecoder.default_to_regular(v) for k, v in d.items()} return d def print_instr_dict(): - + ''' + Print out the dictionary map to a file + ''' printer = pprint.PrettyPrinter(indent=1, width=800, depth=None, stream=None, compact=False, sort_dicts=False) s = printer.pformat(rvOpcodesDecoder.default_to_regular(rvOpcodesDecoder.INST_DICT)) f = open('dict_tree.txt', 'w+') f.write(s) - f.close() - -if __name__ == '__main__': - - decoder = rvOpcodesDecoder('*') - rvOpcodesDecoder.print_instr_dict() - - ins = instructionObject(0x095050ef, '', '') - - # Tests - name = decoder.decoder(ins).imm - print(hex(name)) - - #name = decoder.decoder(0x00000073).keys() - - - '''f1 = open('./tests/none_result.txt', 'w+') - f2 = open('./tests/matches_results.txt' , 'w+') - f3 = open('./tests/no_matches_results.txt' , 'w+') - - with open('./tests/ratified.txt', 'r') as fp: - for line in fp: - line = line.strip('\n') - code = int(line, 16) - ins_obj = instructionObject(code, '', '') - - old_decoder = disassembler() - old_decoder.setup('rv32') - - old_res = old_decoder.decode(ins_obj).instr_name - result = decoder.decoder(code) - - if old_res: - old_res = old_res.replace('.', '_') - else: - old_res = None - - if result != None: - result = list(decoder.decoder(code).keys())[0] - - if result and old_res: - if old_res == result: - f2.write(f'Match found! {result} for {line}\n') - else: - f3.write(f'Not matching! {line}: {result} for rvopcodes-decoder; {old_res} for internal decoder\n') - else: - if not result: - result = 'None' - if not old_res: - old_res = 'None' - f1.write(f'{line}: {result} for rvopcodes-decoder; {old_res} for internal decoder\n') - - f1.close() - f2.close() - f3.close()''' \ No newline at end of file + f.close() \ No newline at end of file From 7046a99da037a11a89570553347907789f8e5204 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Sat, 26 Mar 2022 12:06:36 +0530 Subject: [PATCH 15/41] Code clearnup @pawks --- riscv_isac/plugins/rvopcodesdecoder.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/riscv_isac/plugins/rvopcodesdecoder.py b/riscv_isac/plugins/rvopcodesdecoder.py index f5ee8e8..407947e 100644 --- a/riscv_isac/plugins/rvopcodesdecoder.py +++ b/riscv_isac/plugins/rvopcodesdecoder.py @@ -38,12 +38,13 @@ class rvOpcodesDecoder: INST_LIST = [] @plugins.decoderHookImpl - def setup(self, file_filter: str): + def setup(self, arch: str): + self.arch = arch - # Create nested dictionary based on file_filter specified + # Create nested dictionary nested_dict = lambda: defaultdict(nested_dict) rvOpcodesDecoder.INST_DICT = nested_dict() - rvOpcodesDecoder.create_inst_dict(file_filter) + rvOpcodesDecoder.create_inst_dict('*') def process_enc_line(line: str): @@ -281,6 +282,8 @@ def decode(self, temp_instrobj: instructionObject): if arg.find('imm') != -1: if arg in ['imm12', 'imm20', 'zimm', 'imm2', 'imm3', 'imm4', 'imm5']: imm = get_arg_val(arg)(mcode) + + # Reoder immediates if arg == 'jimm20': imm_temp = get_arg_val(arg)(mcode) imm = imm_temp[0] + imm_temp[12:21] + imm_temp[11] + imm_temp[1:11] + '0' @@ -311,7 +314,8 @@ def decode(self, temp_instrobj: instructionObject): else: print('Found two instructions in the leaf node') - # Utility function + # Utility functions + def twos_comp(val, bits): ''' Get the two_complement value From 5e93ddf2cc3ca9fd311c117f544e2a41c3a8790d Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Fri, 1 Apr 2022 13:18:58 +0530 Subject: [PATCH 16/41] rvopcodesdecoder info --- docs/source/rvopcodesdecoder.rst | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 docs/source/rvopcodesdecoder.rst diff --git a/docs/source/rvopcodesdecoder.rst b/docs/source/rvopcodesdecoder.rst new file mode 100644 index 0000000..2e9c69a --- /dev/null +++ b/docs/source/rvopcodesdecoder.rst @@ -0,0 +1,30 @@ +======================== +rvopcodesdecoder Plugin +======================== + +``rvopcodesdecoder`` is a disassembler for the RISCV-ISAC. It is a decoder plugin dependent +on the `riscv/riscv-opcodes `_ repository. + +Usage +~~~~~ +``rvopcodesdecoder`` uses files from ``riscv/riscv-opcodes`` to parse and generate datastructures +to support the decoder. Manually, these files should be checked into ``riscv_isac/plugins/riscv_opcodes`` directory. +This process is automated using the ``setup`` command of ``riscv_isac`` like this: + +``riscv_isac setup`` + +The above operation, by default clones the ``riscv/riscv-opcodes`` into ``riscv_isac/plugins/riscv_opcodes`` + +In order to clone into a different version of ``riscv_opcodes``, ``--url`` option can be used to enter the url to the +particular version. + +``rirscv_isac setup --url https://github.com/riscv/riscv-opcodes/tree/master`` + +To use ``rvopcodesdecoder`` for coverage computation using RISCV-ISAC, ``rvopcodesdecoder`` should be used for ``--decoder-name`` option. For example, + +``riscv_isac --verbose info coverage -d -t trace.log --parser-name spike --decoder-name rvopcodesdecoder -o coverage.rpt --sig-label main _end --test-label main _end -e a.out -c dataset.cgf -x 64`` + +Plugin Implementation +~~~~~~~~~~~~~~~~~~~~~ +The ``riscvopcodesdecoder`` implements ``setup`` and ``decode`` methods which implements the decoder plugin. The setup +function gathers all the necessary files and creates a nested dictionary which facilitates decoding of machine code instructions hierarchically. \ No newline at end of file From 93cd539a349149be5831fb45d14971a9cbeb8467 Mon Sep 17 00:00:00 2001 From: Edwin Joy <43539365+edwin7026@users.noreply.github.com> Date: Fri, 1 Apr 2022 13:53:48 +0530 Subject: [PATCH 17/41] Code snippets --- docs/source/rvopcodesdecoder.rst | 48 +++++++++++++++++++++++--------- 1 file changed, 35 insertions(+), 13 deletions(-) diff --git a/docs/source/rvopcodesdecoder.rst b/docs/source/rvopcodesdecoder.rst index 2e9c69a..0eb10c1 100644 --- a/docs/source/rvopcodesdecoder.rst +++ b/docs/source/rvopcodesdecoder.rst @@ -2,29 +2,51 @@ rvopcodesdecoder Plugin ======================== -``rvopcodesdecoder`` is a disassembler for the RISCV-ISAC. It is a decoder plugin dependent -on the `riscv/riscv-opcodes `_ repository. +`rvopcodesdecoder` is a disassembler for the RISCV-ISAC. It is a decoder plugin dependent on the `riscv/riscv-opcodes `_ repository. The decoder is implemented in ``riscv_isac/plugins/rvopcodesdecoder.py`` file. Usage ~~~~~ -``rvopcodesdecoder`` uses files from ``riscv/riscv-opcodes`` to parse and generate datastructures +`rvopcodesdecoder` uses files from ``riscv/riscv-opcodes`` repository to parse and generate datastructures to support the decoder. Manually, these files should be checked into ``riscv_isac/plugins/riscv_opcodes`` directory. -This process is automated using the ``setup`` command of ``riscv_isac`` like this: - -``riscv_isac setup`` +This process is automated using the ``setup`` command of `riscv_isac`: :: + + riscv_isac setup The above operation, by default clones the ``riscv/riscv-opcodes`` into ``riscv_isac/plugins/riscv_opcodes`` -In order to clone into a different version of ``riscv_opcodes``, ``--url`` option can be used to enter the url to the -particular version. +In order to clone into a different version of ``riscv_opcodes``, ``--url`` option can be used to enter the url of the +particular version.:: -``rirscv_isac setup --url https://github.com/riscv/riscv-opcodes/tree/master`` + rirscv_isac setup --url https://github.com/riscv/riscv-opcodes/tree/master -To use ``rvopcodesdecoder`` for coverage computation using RISCV-ISAC, ``rvopcodesdecoder`` should be used for ``--decoder-name`` option. For example, +To use `rvopcodesdecoder` for coverage computation using RISCV-ISAC, ``rvopcodesdecoder`` should be supplied as argument for ``--decoder-name`` option. For example, :: -``riscv_isac --verbose info coverage -d -t trace.log --parser-name spike --decoder-name rvopcodesdecoder -o coverage.rpt --sig-label main _end --test-label main _end -e a.out -c dataset.cgf -x 64`` + riscv_isac --verbose info coverage -d -t trace.log --parser-name spike --decoder-name rvopcodesdecoder -o coverage.rpt --sig-label main _end --test-label main _end -e add-01.out -c dataset.cgf -x 64 Plugin Implementation ~~~~~~~~~~~~~~~~~~~~~ -The ``riscvopcodesdecoder`` implements ``setup`` and ``decode`` methods which implements the decoder plugin. The setup -function gathers all the necessary files and creates a nested dictionary which facilitates decoding of machine code instructions hierarchically. \ No newline at end of file +The riscvopcodesdecoder module implements ``setup`` and ``decode`` methods for the decoder plugin. + +Setup +************* +The setup function gathers all the necessary files and creates a nested dictionary by calling ``create_inst_dict`` which facilitates decoding of machine code instructions hierarchically. + +.. code-block:: python + @plugins.decoderHookImpl + def setup(self, arch: str): + self.arch = arch + # Create nested dictionary + nested_dict = lambda: defaultdict(nested_dict) + rvOpcodesDecoder.INST_DICT = nested_dict() + rvOpcodesDecoder.create_inst_dict('*') + +Decoder +******* +The ``decode`` method takes the instruction stored in an ``instructionOjbect`` and decodes the name and arguments associated with the instruction. The ``get_instr()`` method traverses through the dictionary tree recursively till it fetches the required instruction name and arguments. + +.. code-block:: python + @plugins.decoderHookImpl + def decode(self, temp_instrobj: instructionObject): + + mcode = temp_instrobj.instr + name_args = rvOpcodesDecoder.get_instr(rvOpcodesDecoder.INST_DICT, mcode) From a657f4c632df9cd9e6116fbf4b3fb132a9342033 Mon Sep 17 00:00:00 2001 From: Edwin Joy <43539365+edwin7026@users.noreply.github.com> Date: Fri, 1 Apr 2022 14:21:05 +0530 Subject: [PATCH 18/41] Code formatting --- docs/source/rvopcodesdecoder.rst | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/docs/source/rvopcodesdecoder.rst b/docs/source/rvopcodesdecoder.rst index 0eb10c1..13e173f 100644 --- a/docs/source/rvopcodesdecoder.rst +++ b/docs/source/rvopcodesdecoder.rst @@ -19,7 +19,7 @@ particular version.:: rirscv_isac setup --url https://github.com/riscv/riscv-opcodes/tree/master -To use `rvopcodesdecoder` for coverage computation using RISCV-ISAC, ``rvopcodesdecoder`` should be supplied as argument for ``--decoder-name`` option. For example, :: +To use `rvopcodesdecoder` for coverage computation in RISCV-ISAC, ``rvopcodesdecoder`` should be supplied as argument for ``--decoder-name`` option. For example, :: riscv_isac --verbose info coverage -d -t trace.log --parser-name spike --decoder-name rvopcodesdecoder -o coverage.rpt --sig-label main _end --test-label main _end -e add-01.out -c dataset.cgf -x 64 @@ -29,24 +29,28 @@ The riscvopcodesdecoder module implements ``setup`` and ``decode`` methods for t Setup ************* -The setup function gathers all the necessary files and creates a nested dictionary by calling ``create_inst_dict`` which facilitates decoding of machine code instructions hierarchically. +The setup function gathers all the necessary files and creates a nested dictionary by calling ``create_inst_dict`` which facilitates decoding of machine code instructions hierarchically -.. code-block:: python - @plugins.decoderHookImpl - def setup(self, arch: str): - self.arch = arch - # Create nested dictionary - nested_dict = lambda: defaultdict(nested_dict) - rvOpcodesDecoder.INST_DICT = nested_dict() - rvOpcodesDecoder.create_inst_dict('*') +.. code-block:: python + + @plugins.decoderHookImpl + def setup(self, arch: str): + self.arch = arch + # Create nested dictionary + nested_dict = lambda: defaultdict(nested_dict) + rvOpcodesDecoder.INST_DICT = nested_dict() + rvOpcodesDecoder.create_inst_dict('*') Decoder ******* The ``decode`` method takes the instruction stored in an ``instructionOjbect`` and decodes the name and arguments associated with the instruction. The ``get_instr()`` method traverses through the dictionary tree recursively till it fetches the required instruction name and arguments. .. code-block:: python - @plugins.decoderHookImpl + + @plugins.decoderHookImpl def decode(self, temp_instrobj: instructionObject): mcode = temp_instrobj.instr name_args = rvOpcodesDecoder.get_instr(rvOpcodesDecoder.INST_DICT, mcode) + +``riscv_isac/plugins/constants.py`` holds the necessary field position information to decode the arguments. From 1dffd566cf72ab859bce15b8a42fbaad47b4013f Mon Sep 17 00:00:00 2001 From: Edwin Joy <43539365+edwin7026@users.noreply.github.com> Date: Fri, 1 Apr 2022 14:21:52 +0530 Subject: [PATCH 19/41] Update rvopcodesdecoder.rst --- docs/source/rvopcodesdecoder.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/rvopcodesdecoder.rst b/docs/source/rvopcodesdecoder.rst index 13e173f..ed3aef0 100644 --- a/docs/source/rvopcodesdecoder.rst +++ b/docs/source/rvopcodesdecoder.rst @@ -41,7 +41,7 @@ The setup function gathers all the necessary files and creates a nested dictiona rvOpcodesDecoder.INST_DICT = nested_dict() rvOpcodesDecoder.create_inst_dict('*') -Decoder +Decode ******* The ``decode`` method takes the instruction stored in an ``instructionOjbect`` and decodes the name and arguments associated with the instruction. The ``get_instr()`` method traverses through the dictionary tree recursively till it fetches the required instruction name and arguments. From 8f33456bc1a607d52b7a33fd47be5092f4d308f0 Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Sat, 2 Apr 2022 17:29:53 +0530 Subject: [PATCH 20/41] Fixed setup for opcodes decoder. --- MANIFEST.in | 1 + riscv_isac/data/__init__.py | 0 riscv_isac/{plugins => data}/constants.py | 0 .../{plugins => data}/rvopcodesdecoder.py | 58 +++++++++---------- riscv_isac/main.py | 53 ++++++++++++----- 5 files changed, 67 insertions(+), 45 deletions(-) create mode 100644 riscv_isac/data/__init__.py rename riscv_isac/{plugins => data}/constants.py (100%) rename riscv_isac/{plugins => data}/rvopcodesdecoder.py (96%) diff --git a/MANIFEST.in b/MANIFEST.in index 7cbf7d0..b888a5a 100644 --- a/MANIFEST.in +++ b/MANIFEST.in @@ -1,6 +1,7 @@ include LICENSE.incore include README.rst include riscv_isac/requirements.txt +recursive-include riscv_isac/data/* recursive-exclude * __pycache__ recursive-exclude * *.py[co] diff --git a/riscv_isac/data/__init__.py b/riscv_isac/data/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/riscv_isac/plugins/constants.py b/riscv_isac/data/constants.py similarity index 100% rename from riscv_isac/plugins/constants.py rename to riscv_isac/data/constants.py diff --git a/riscv_isac/plugins/rvopcodesdecoder.py b/riscv_isac/data/rvopcodesdecoder.py similarity index 96% rename from riscv_isac/plugins/rvopcodesdecoder.py rename to riscv_isac/data/rvopcodesdecoder.py index 407947e..6337e15 100644 --- a/riscv_isac/plugins/rvopcodesdecoder.py +++ b/riscv_isac/data/rvopcodesdecoder.py @@ -27,7 +27,7 @@ def get_funct(pos_tuple: tuple, mcode: int): lsb = pos_tuple[1] mask = int(''.join('1' * (msb - lsb + 1)), 2) << lsb val = (mask & mcode) >> lsb - + return val class rvOpcodesDecoder: @@ -40,7 +40,7 @@ class rvOpcodesDecoder: @plugins.decoderHookImpl def setup(self, arch: str): self.arch = arch - + # Create nested dictionary nested_dict = lambda: defaultdict(nested_dict) rvOpcodesDecoder.INST_DICT = nested_dict() @@ -59,11 +59,11 @@ def process_enc_line(line: str): # remove leading whitespaces remaining = remaining.lstrip() - + # extract bit pattern assignments of the form hi..lo=val. fixed_ranges is a # regex expression present in constants.py. The extracted patterns are # captured as a list in args where each entry is a tuple (msb, lsb, value) - + opcode_parsed = fixed_ranges.findall(remaining) opcode_functs = [] for func in opcode_parsed: @@ -74,7 +74,7 @@ def process_enc_line(line: str): for (msb, lsb, value) in opcode_functs: flen = msb - lsb + 1 value = f"{value:0{flen}b}" - value = int(value, 2) + value = int(value, 2) funct = (msb, lsb) functs.append((funct, value)) @@ -93,7 +93,7 @@ def process_enc_line(line: str): functs.append(((lsb, lsb), value)) return (functs, (name, args)) - + def create_inst_dict(file_filter): ''' Gathers files and generates instruciton list from the filter given @@ -120,7 +120,7 @@ def create_inst_dict(file_filter): # go through each line of the file for line in lines: - + # ignore all lines starting with $import and $pseudo if '$import' in line or '$pseudo' in line: continue @@ -129,26 +129,26 @@ def create_inst_dict(file_filter): # [ [(funct, val)], name, [args] ] rvOpcodesDecoder.INST_LIST.append([functs, name, args]) - + # Insert all instructions to the root of the dictionary rvOpcodesDecoder.INST_DICT['root'] = rvOpcodesDecoder.INST_LIST # Generate dictionary rvOpcodesDecoder.build_instr_dict(rvOpcodesDecoder.INST_DICT) - + def build_instr_dict(inst_dict): ''' - This function recursively generates the dictionary based on + This function recursively generates the dictionary based on highest occurrence of functs in a particular path ''' - + # Get all instructions in the level val = inst_dict['root'] - + # Gather all functs funct_list = [item[0] for item in val] funct_occ = [funct[0] for ins in funct_list for funct in ins] - + # Path recoder funct_path = set() # Check if there are functions remaining @@ -167,25 +167,25 @@ def build_instr_dict(inst_dict): for funct in val[i][0]: if funct[0] == max_funct: # Max funct found! - + # Push into path recorder funct_path.add(funct) - + # Push funct and its value into the dict temp_dict = inst_dict[funct[0]][funct[1]] - + # Create empty list in the path if not temp_dict: inst_dict[funct[0]][funct[1]]['root'] = [] - + # Delete appended funct temp = val[i] temp[0].remove(funct) - + if temp[0]: # Add to the path inst_dict[funct[0]][funct[1]]['root'].append(temp) - + # Remove the copied instruction from previous list inst_dict['root'].remove(val[i]) else: @@ -206,7 +206,7 @@ def build_instr_dict(inst_dict): else: return a return - + def get_instr(func_dict, mcode: int): ''' Recursively extracts the instruction from the dictionary @@ -214,7 +214,7 @@ def get_instr(func_dict, mcode: int): # Get list of functions keys = func_dict.keys() for key in keys: - if type(key) == str: + if type(key) == str: return func_dict if type(key) == tuple: val = get_funct(key, mcode) @@ -227,11 +227,11 @@ def get_instr(func_dict, mcode: int): return a else: continue - + @plugins.decoderHookImpl def decode(self, temp_instrobj: instructionObject): ''' - Take an instruction object with just machine code and fill + Take an instruction object with just machine code and fill the instruction name and argument fields Input: @@ -282,7 +282,7 @@ def decode(self, temp_instrobj: instructionObject): if arg.find('imm') != -1: if arg in ['imm12', 'imm20', 'zimm', 'imm2', 'imm3', 'imm4', 'imm5']: imm = get_arg_val(arg)(mcode) - + # Reoder immediates if arg == 'jimm20': imm_temp = get_arg_val(arg)(mcode) @@ -309,7 +309,7 @@ def decode(self, temp_instrobj: instructionObject): if imm: numbits = len(imm) temp_instrobj.imm = rvOpcodesDecoder.twos_comp(int(imm, 2), numbits) - + return temp_instrobj else: print('Found two instructions in the leaf node') @@ -323,7 +323,7 @@ def twos_comp(val, bits): if (val & (1 << (bits - 1))) != 0: val = val - (1 << bits) return val - + def default_to_regular(d): ''' Utility function to convert nested defaultdict to regular dict @@ -331,15 +331,15 @@ def default_to_regular(d): if isinstance(d, defaultdict): d = {k: rvOpcodesDecoder.default_to_regular(v) for k, v in d.items()} return d - + def print_instr_dict(): ''' Print out the dictionary map to a file ''' printer = pprint.PrettyPrinter(indent=1, width=800, depth=None, stream=None, compact=False, sort_dicts=False) - + s = printer.pformat(rvOpcodesDecoder.default_to_regular(rvOpcodesDecoder.INST_DICT)) f = open('dict_tree.txt', 'w+') f.write(s) - f.close() \ No newline at end of file + f.close() diff --git a/riscv_isac/main.py b/riscv_isac/main.py index b45763d..b44d71e 100644 --- a/riscv_isac/main.py +++ b/riscv_isac/main.py @@ -3,6 +3,7 @@ import os import click +import shutil from git import Repo from riscv_isac.isac import isac @@ -76,7 +77,8 @@ def cli(verbose): @click.option( '--output-file','-o', type=click.Path(writable=True,resolve_path=True), - help="Coverage Group File" + help="Coverage Group File", + required=True ) @click.option( '--test-label', @@ -174,25 +176,44 @@ def normalize(cgf_file,output_file,xlen): -@cli.command(help = 'Clone from the riscv-opcodes repo') +@cli.command(help = 'Setup the plugin which uses the information from RISCV Opcodes repository to decode.') @click.option('--url', type = str, default='https://github.com/incoresemi/riscv-opcodes', required=False, help='URL to the riscv-opcodes repo') -@click.option('--clean', - is_flag=True, - help='Clean cloned repo' - ) +@click.option('--plugin-path', + type=click.Path(resolve_path=True,writable=True), + help="Target folder to setup the plugin files in. [./]", + default="./rvop_decoder") +@click.option("--rvop-path", + type=click.Path(resolve_path=True,writable=True), + help="Path to RVOpcodes directory.") # Clone repo -def setup(url, clean): - ''' - Clone from a specified url - Input argument: - url: (string) url to the riscv-opcodes repo - ''' - path = os.getcwd() + '/plugins/riscv_opcodes/' - if(clean): - os.system('rm -rf ' + path) +def setup(url, plugin_path, rvop_path): + # path = os.getcwd() + '/plugins/riscv_opcodes/' + if not os.path.exists(plugin_path): + logger.debug("Creating directory: "+str(plugin_path)) + os.mkdir(plugin_path) + target_dir = os.path.join(plugin_path,"riscv_opcodes/") + if rvop_path is not None: + if not os.path.exists(rvop_path): + logger.warning("RISCV Opcodes folder not found at: "+rvop_path) + clone = click.prompt("Do you wish to clone from git?", + default='Y',type=click.Choice(['Y','n','y','N']),show_choices=True) + if clone == 'Y' or clone == 'y': + logger.debug("Cloning from Git.") + Repo.clone_from(url, rvop_path) + else: + logger.error("Exiting Setup.") + raise SystemExit + os.symlink(rvop_path,target_dir[:-1]) else: - Repo.clone_from(url, './plugins/riscv_opcodes/') \ No newline at end of file + logger.debug("Cloning from Git.") + Repo.clone_from(url, target_dir) + plugin_file = os.path.join(os.path.dirname(__file__), "data/rvopcodesdecoder.py") + constants_file = os.path.join(os.path.dirname(__file__), "data/constants.py") + logger.debug("Copying plugin files.") + shutil.copy(plugin_file,plugin_path) + shutil.copy(constants_file,plugin_path) + From 497e3e4f91606ee68841aabd4145240deee1dd54 Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Sat, 2 Apr 2022 18:00:01 +0530 Subject: [PATCH 21/41] Cleanup. Decoder not working. --- riscv_isac/data/rvopcodesdecoder.py | 36 ++++++++++++++--------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/riscv_isac/data/rvopcodesdecoder.py b/riscv_isac/data/rvopcodesdecoder.py index 6337e15..1b96fdb 100644 --- a/riscv_isac/data/rvopcodesdecoder.py +++ b/riscv_isac/data/rvopcodesdecoder.py @@ -6,9 +6,6 @@ from constants import * from riscv_isac.InstructionObject import instructionObject -from riscv_isac.plugins import internaldecoder -from riscv_isac.plugins.internaldecoder import disassembler - import riscv_isac.plugins as plugins # Closure to get argument value @@ -30,7 +27,7 @@ def get_funct(pos_tuple: tuple, mcode: int): return val -class rvOpcodesDecoder: +class disassembler(): FIRST_TWO = 0x00000003 OPCODE_MASK = 0x0000007f @@ -43,8 +40,8 @@ def setup(self, arch: str): # Create nested dictionary nested_dict = lambda: defaultdict(nested_dict) - rvOpcodesDecoder.INST_DICT = nested_dict() - rvOpcodesDecoder.create_inst_dict('*') + disassembler.INST_DICT = nested_dict() + disassembler.create_inst_dict('*') def process_enc_line(line: str): @@ -125,16 +122,16 @@ def create_inst_dict(file_filter): if '$import' in line or '$pseudo' in line: continue - (functs, (name, args)) = rvOpcodesDecoder.process_enc_line(line) + (functs, (name, args)) = disassembler.process_enc_line(line) # [ [(funct, val)], name, [args] ] - rvOpcodesDecoder.INST_LIST.append([functs, name, args]) + disassembler.INST_LIST.append([functs, name, args]) # Insert all instructions to the root of the dictionary - rvOpcodesDecoder.INST_DICT['root'] = rvOpcodesDecoder.INST_LIST + disassembler.INST_DICT['root'] = disassembler.INST_LIST # Generate dictionary - rvOpcodesDecoder.build_instr_dict(rvOpcodesDecoder.INST_DICT) + disassembler.build_instr_dict(disassembler.INST_DICT) def build_instr_dict(inst_dict): ''' @@ -200,7 +197,7 @@ def build_instr_dict(inst_dict): for funct in funct_path: new_path = inst_dict[funct[0]][funct[1]] - a = rvOpcodesDecoder.build_instr_dict(new_path) + a = disassembler.build_instr_dict(new_path) if a == None: continue else: @@ -220,7 +217,7 @@ def get_instr(func_dict, mcode: int): val = get_funct(key, mcode) temp_func_dict = func_dict[key][val] if temp_func_dict.keys(): - a = rvOpcodesDecoder.get_instr(temp_func_dict, mcode) + a = disassembler.get_instr(temp_func_dict, mcode) if a == None: continue else: @@ -229,7 +226,7 @@ def get_instr(func_dict, mcode: int): continue @plugins.decoderHookImpl - def decode(self, temp_instrobj: instructionObject): + def decode(self, instrObj_temp): ''' Take an instruction object with just machine code and fill the instruction name and argument fields @@ -241,9 +238,11 @@ def decode(self, temp_instrobj: instructionObject): None : When the dissassembler fails to decode the machine code ''' + temp_instrobj = instrObj_temp + mcode = temp_instrobj.instr - name_args = rvOpcodesDecoder.get_instr(rvOpcodesDecoder.INST_DICT, mcode) + name_args = disassembler.get_instr(disassembler.INST_DICT, mcode) # Fill out the partially filled instructionObject if name_args: @@ -308,11 +307,12 @@ def decode(self, temp_instrobj: instructionObject): imm = imm + imm_temp if imm: numbits = len(imm) - temp_instrobj.imm = rvOpcodesDecoder.twos_comp(int(imm, 2), numbits) + temp_instrobj.imm = disassembler.twos_comp(int(imm, 2), numbits) return temp_instrobj else: - print('Found two instructions in the leaf node') + logger.error('Found two instructions in the leaf node') + return temp_instrobj # Utility functions @@ -329,7 +329,7 @@ def default_to_regular(d): Utility function to convert nested defaultdict to regular dict ''' if isinstance(d, defaultdict): - d = {k: rvOpcodesDecoder.default_to_regular(v) for k, v in d.items()} + d = {k: disassembler.default_to_regular(v) for k, v in d.items()} return d def print_instr_dict(): @@ -339,7 +339,7 @@ def print_instr_dict(): printer = pprint.PrettyPrinter(indent=1, width=800, depth=None, stream=None, compact=False, sort_dicts=False) - s = printer.pformat(rvOpcodesDecoder.default_to_regular(rvOpcodesDecoder.INST_DICT)) + s = printer.pformat(disassembler.default_to_regular(disassembler.INST_DICT)) f = open('dict_tree.txt', 'w+') f.write(s) f.close() From 08cefc794c9ce28dd70b2a5b2860131886580c23 Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Sat, 2 Apr 2022 18:26:03 +0530 Subject: [PATCH 22/41] Cleanup and remove hardcoded paths. --- riscv_isac/data/rvopcodesdecoder.py | 9 +++++++-- riscv_isac/main.py | 9 ++++++--- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/riscv_isac/data/rvopcodesdecoder.py b/riscv_isac/data/rvopcodesdecoder.py index 1b96fdb..5dd4578 100644 --- a/riscv_isac/data/rvopcodesdecoder.py +++ b/riscv_isac/data/rvopcodesdecoder.py @@ -3,6 +3,7 @@ from collections import defaultdict import pprint from statistics import mode +import os from constants import * from riscv_isac.InstructionObject import instructionObject @@ -100,10 +101,11 @@ def create_inst_dict(file_filter): ''' # Default riscv-opcodes directory - opcodes_dir = f'./riscv_opcodes/' + opcodes_dir = os.path.join(os.path.dirname(__file__),"riscv_opcodes/") + # file_names contains all files to be parsed in the riscv-opcodes directory - file_names = glob.glob(f'{opcodes_dir}rv{file_filter}') + file_names = glob.glob(f'{opcodes_dir}/rv{file_filter}') # first pass if for standard/original instructions for f in file_names: @@ -210,6 +212,7 @@ def get_instr(func_dict, mcode: int): ''' # Get list of functions keys = func_dict.keys() + print(func_dict) for key in keys: if type(key) == str: return func_dict @@ -313,6 +316,8 @@ def decode(self, instrObj_temp): else: logger.error('Found two instructions in the leaf node') return temp_instrobj + else: + return temp_instrobj # Utility functions diff --git a/riscv_isac/main.py b/riscv_isac/main.py index b44d71e..8a81e9f 100644 --- a/riscv_isac/main.py +++ b/riscv_isac/main.py @@ -182,6 +182,7 @@ def normalize(cgf_file,output_file,xlen): default='https://github.com/incoresemi/riscv-opcodes', required=False, help='URL to the riscv-opcodes repo') +@click.option('--branch',type=str,default='master') @click.option('--plugin-path', type=click.Path(resolve_path=True,writable=True), help="Target folder to setup the plugin files in. [./]", @@ -190,12 +191,13 @@ def normalize(cgf_file,output_file,xlen): type=click.Path(resolve_path=True,writable=True), help="Path to RVOpcodes directory.") # Clone repo -def setup(url, plugin_path, rvop_path): +def setup(url,branch, plugin_path, rvop_path): # path = os.getcwd() + '/plugins/riscv_opcodes/' if not os.path.exists(plugin_path): logger.debug("Creating directory: "+str(plugin_path)) os.mkdir(plugin_path) target_dir = os.path.join(plugin_path,"riscv_opcodes/") + repo = None if rvop_path is not None: if not os.path.exists(rvop_path): logger.warning("RISCV Opcodes folder not found at: "+rvop_path) @@ -203,14 +205,15 @@ def setup(url, plugin_path, rvop_path): default='Y',type=click.Choice(['Y','n','y','N']),show_choices=True) if clone == 'Y' or clone == 'y': logger.debug("Cloning from Git.") - Repo.clone_from(url, rvop_path) + repo = Repo.clone_from(url, rvop_path) else: logger.error("Exiting Setup.") raise SystemExit os.symlink(rvop_path,target_dir[:-1]) else: logger.debug("Cloning from Git.") - Repo.clone_from(url, target_dir) + repo = Repo.clone_from(url, target_dir) + repo.git.checkout(branch) plugin_file = os.path.join(os.path.dirname(__file__), "data/rvopcodesdecoder.py") constants_file = os.path.join(os.path.dirname(__file__), "data/constants.py") logger.debug("Copying plugin files.") From ff261c0933583d5d55985d8b0495a8e779e63a2d Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Sat, 2 Apr 2022 19:37:05 +0530 Subject: [PATCH 23/41] Updated documentation for rvopcodes. --- docs/source/add_instr.rst | 5 ++- docs/source/index.rst | 3 +- docs/source/rvopcodesdecoder.rst | 69 ++++++++++++-------------------- 3 files changed, 31 insertions(+), 46 deletions(-) diff --git a/docs/source/add_instr.rst b/docs/source/add_instr.rst index ee6948e..f4781a7 100644 --- a/docs/source/add_instr.rst +++ b/docs/source/add_instr.rst @@ -4,7 +4,10 @@ Adding Support for new Instructions ################################### -This section details the steps for adding support for new instructions in RISCV-ISAC. +This section details the steps for adding support for new instructions in the native python plugins +of RISCV-ISAC. + +.. note:: An alternative is to add support for the new instructions using the ``riscv/riscv-opcodes`` repository. Refer :here:`rvopcodes` for further information. Update the Parser-Module ======================== diff --git a/docs/source/index.rst b/docs/source/index.rst index 94b91a3..65e30f0 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -18,9 +18,10 @@ please refer to the :ref:`Revisions ` documentation. overview quickstart cgf + rvopcodesdecoder add_instr - code contributing revisions licensing python_plugins + code diff --git a/docs/source/rvopcodesdecoder.rst b/docs/source/rvopcodesdecoder.rst index ed3aef0..b25333c 100644 --- a/docs/source/rvopcodesdecoder.rst +++ b/docs/source/rvopcodesdecoder.rst @@ -1,56 +1,37 @@ -======================== -rvopcodesdecoder Plugin -======================== +.. _rvopcodes: -`rvopcodesdecoder` is a disassembler for the RISCV-ISAC. It is a decoder plugin dependent on the `riscv/riscv-opcodes `_ repository. The decoder is implemented in ``riscv_isac/plugins/rvopcodesdecoder.py`` file. +Using the encodings from riscv-opcodes +====================================== + +The `rvopcodesdecoder` is a decoder plugin for RISCV-ISAC, dependent on the official `riscv-opcodes `_ repository. The `rvopcodesdecoder` plugin automatically builds the decode tree and decodes instructions based on the encodings specified in the repository. The plugin will support any instruction/extension as long as it is specified in the format adhereing to the official repository. Usage ~~~~~ -`rvopcodesdecoder` uses files from ``riscv/riscv-opcodes`` repository to parse and generate datastructures -to support the decoder. Manually, these files should be checked into ``riscv_isac/plugins/riscv_opcodes`` directory. -This process is automated using the ``setup`` command of `riscv_isac`: :: - - riscv_isac setup - -The above operation, by default clones the ``riscv/riscv-opcodes`` into ``riscv_isac/plugins/riscv_opcodes`` - -In order to clone into a different version of ``riscv_opcodes``, ``--url`` option can be used to enter the url of the -particular version.:: - - rirscv_isac setup --url https://github.com/riscv/riscv-opcodes/tree/master -To use `rvopcodesdecoder` for coverage computation in RISCV-ISAC, ``rvopcodesdecoder`` should be supplied as argument for ``--decoder-name`` option. For example, :: - - riscv_isac --verbose info coverage -d -t trace.log --parser-name spike --decoder-name rvopcodesdecoder -o coverage.rpt --sig-label main _end --test-label main _end -e add-01.out -c dataset.cgf -x 64 - -Plugin Implementation -~~~~~~~~~~~~~~~~~~~~~ -The riscvopcodesdecoder module implements ``setup`` and ``decode`` methods for the decoder plugin. - -Setup +Initial Setup ************* -The setup function gathers all the necessary files and creates a nested dictionary by calling ``create_inst_dict`` which facilitates decoding of machine code instructions hierarchically +- **Standard version**: This use case is intended for users who want to use the rvopcodes repo as + is from `riscv/riscv-opcodes `_. The command generates a + ``rvop-plugin`` folder with all the necessary files needed for the plugin. This path will have to + be passed via the CLI while running coverage. :: + + riscv_isac setup --plugin-path ./rvop-plugin -.. code-block:: python +- **Custom Version**: This use case is intended for users who have a custom/modified version of the + rvopcodes encodings locally. The ```` in the following command should point to + the path on the system where the custom/modified ``riscv-opcodes`` repository contents are located. + The command generates a symlink to the path inside the plugin folder and hence all changes to + the encodings are picked up automatically. To add an extension, the user has to create a file + with the ``rv`` prefix followed by the extension name. The file can then be populated with + the instruction encodings in the appropriate format. Similar steps can be followed for updating + existing extensions too. :: - @plugins.decoderHookImpl - def setup(self, arch: str): - self.arch = arch - # Create nested dictionary - nested_dict = lambda: defaultdict(nested_dict) - rvOpcodesDecoder.INST_DICT = nested_dict() - rvOpcodesDecoder.create_inst_dict('*') + riscv_isac setup --plugin-path ./rvop-plugin --rvop-path -Decode -******* -The ``decode`` method takes the instruction stored in an ``instructionOjbect`` and decodes the name and arguments associated with the instruction. The ``get_instr()`` method traverses through the dictionary tree recursively till it fetches the required instruction name and arguments. +Using the decoder with ISAC for coverage +**************************************** -.. code-block:: python - - @plugins.decoderHookImpl - def decode(self, temp_instrobj: instructionObject): +To use `rvopcodesdecoder` as the decoder in RISCV-ISAC, ``rvopcodesdecoder`` should be supplied as argument for ``--decoder-name`` option with the ``--decoder-path`` set to the path of ``rvop-plugin`` generated in the previous step.. For example, :: - mcode = temp_instrobj.instr - name_args = rvOpcodesDecoder.get_instr(rvOpcodesDecoder.INST_DICT, mcode) + riscv_isac --verbose info coverage --decoder-name rvopcodesdecoder --decoder-path ./rvop-plugin -t trace.log --parser-name spike -o coverage.rpt -e add-01.out -c rv64i.cgf -x 64 -``riscv_isac/plugins/constants.py`` holds the necessary field position information to decode the arguments. From 2478280ae6806ce1f4d8907c193a04820833b9ee Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Sat, 2 Apr 2022 20:13:03 +0530 Subject: [PATCH 24/41] Removed stray print and update requirements. --- riscv_isac/data/rvopcodesdecoder.py | 1 - riscv_isac/requirements.txt | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv_isac/data/rvopcodesdecoder.py b/riscv_isac/data/rvopcodesdecoder.py index 5dd4578..1e84905 100644 --- a/riscv_isac/data/rvopcodesdecoder.py +++ b/riscv_isac/data/rvopcodesdecoder.py @@ -212,7 +212,6 @@ def get_instr(func_dict, mcode: int): ''' # Get list of functions keys = func_dict.keys() - print(func_dict) for key in keys: if type(key) == str: return func_dict diff --git a/riscv_isac/requirements.txt b/riscv_isac/requirements.txt index bf3e7cc..11b143e 100644 --- a/riscv_isac/requirements.txt +++ b/riscv_isac/requirements.txt @@ -1,4 +1,5 @@ click +gitpython ruamel.yaml>=0.16.0 pyyaml pyelftools==0.26 From 4b28e8c429e0d1e040fb2f07128fcf4196bf4475 Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Sat, 2 Apr 2022 20:28:00 +0530 Subject: [PATCH 25/41] Fixed mode calculation and error reporting on import error. --- riscv_isac/coverage.py | 10 ++++++---- riscv_isac/data/rvopcodesdecoder.py | 3 +-- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/riscv_isac/coverage.py b/riscv_isac/coverage.py index c071da0..6bdc6b5 100644 --- a/riscv_isac/coverage.py +++ b/riscv_isac/coverage.py @@ -922,8 +922,9 @@ def compute(trace_file, test_name, cgf, parser_name, decoder_name, detailed, xle parser_pm.add_hookspecs(ParserSpec) try: parserfile = importlib.import_module(parser_name) - except ImportError: - logger.error('Parser name invalid!') + except ImportError as e: + logger.error('Error while importing Parser!') + logger.error(e) raise SystemExit parserclass = getattr(parserfile, parser_name) parser_pm.register(parserclass()) @@ -934,8 +935,9 @@ def compute(trace_file, test_name, cgf, parser_name, decoder_name, detailed, xle decoder_pm.add_hookspecs(DecoderSpec) try: instructionObjectfile = importlib.import_module(decoder_name) - except ImportError: - logger.error('Decoder name invalid!') + except ImportError as e: + logger.error('Error while importing Decoder!') + logger.error(e) raise SystemExit decoderclass = getattr(instructionObjectfile, "disassembler") decoder_pm.register(decoderclass()) diff --git a/riscv_isac/data/rvopcodesdecoder.py b/riscv_isac/data/rvopcodesdecoder.py index 1e84905..2936ac8 100644 --- a/riscv_isac/data/rvopcodesdecoder.py +++ b/riscv_isac/data/rvopcodesdecoder.py @@ -2,7 +2,6 @@ from operator import itemgetter from collections import defaultdict import pprint -from statistics import mode import os from constants import * @@ -155,7 +154,7 @@ def build_instr_dict(inst_dict): if (1, 0) in funct_occ: max_funct = (1, 0) else: - max_funct = mode(funct_occ) + max_funct = max(set(funct_occ),key=funct_occ.count) funct_occ = list(filter(lambda a: a != max_funct, funct_occ)) From 73a3f2f887f533dc37750168618d40010bd33350 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Sat, 2 Apr 2022 21:32:19 +0530 Subject: [PATCH 26/41] Register type assignment and is_rvp issue --- riscv_isac/data/rvopcodesdecoder.py | 31 +++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/riscv_isac/data/rvopcodesdecoder.py b/riscv_isac/data/rvopcodesdecoder.py index 2936ac8..4eb20d0 100644 --- a/riscv_isac/data/rvopcodesdecoder.py +++ b/riscv_isac/data/rvopcodesdecoder.py @@ -5,7 +5,6 @@ import os from constants import * -from riscv_isac.InstructionObject import instructionObject import riscv_isac.plugins as plugins # Closure to get argument value @@ -124,6 +123,7 @@ def create_inst_dict(file_filter): continue (functs, (name, args)) = disassembler.process_enc_line(line) + args.append(os.path.basename(f)) # [ [(funct, val)], name, [args] ] disassembler.INST_LIST.append([functs, name, args]) @@ -255,19 +255,38 @@ def decode(self, instrObj_temp): # Fill arguments args = name_args[instr_names[0]] imm = '' - for arg in args: + + # Get extension + file_name = args[-1] + + # If instruction from P extension + if file_name in ['rv_p', 'rv32_p', 'rv64_p']: + temp_instrobj.is_rvp = True + + # Register type assignment + reg_type = 'x' + if file_name in ['rv_f', 'rv64_f']: + reg_type = 'f' + + for arg in args[:-1]: if arg == 'rd': - temp_instrobj.rd = int(get_arg_val(arg)(mcode), 2) + temp_instrobj.rd = (int(get_arg_val(arg)(mcode), 2), reg_type) if arg == 'rs1': - temp_instrobj.rs1 = int(get_arg_val(arg)(mcode), 2) + temp_instrobj.rs1 = (int(get_arg_val(arg)(mcode), 2), reg_type) if arg == 'rs2': - temp_instrobj.rs2 = int(get_arg_val(arg)(mcode), 2) + temp_instrobj.rs2 = (int(get_arg_val(arg)(mcode), 2), reg_type) if arg == 'rs3': - temp_instrobj.rs3 = int(get_arg_val(arg)(mcode), 2) + temp_instrobj.rs3 = (int(get_arg_val(arg)(mcode), 2), reg_type) if arg == 'csr': temp_instrobj.csr = int(get_arg_val(arg)(mcode), 2) if arg == 'shamt': temp_instrobj.shamt = int(get_arg_val(arg)(mcode), 2) + if arg == 'shamt': + temp_instrobj.shamt = int(get_arg_val(arg)(mcode), 2) + if arg == 'shamtw': + temp_instrobj.shamt = int(get_arg_val(arg)(mcode), 2) + if arg == 'shamtw4': + temp_instrobj.shamt = int(get_arg_val(arg)(mcode), 2) if arg == 'succ': temp_instrobj.succ = int(get_arg_val(arg)(mcode), 2) if arg == 'pred': From 4211a22353c7a052cea18ebcd02587e777eac883 Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Sun, 3 Apr 2022 14:28:19 +0530 Subject: [PATCH 27/41] fixed link and register types for f instructions. --- riscv_isac/data/rvopcodesdecoder.py | 20 +++++++++++++++----- riscv_isac/main.py | 2 +- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/riscv_isac/data/rvopcodesdecoder.py b/riscv_isac/data/rvopcodesdecoder.py index 4eb20d0..2502e85 100644 --- a/riscv_isac/data/rvopcodesdecoder.py +++ b/riscv_isac/data/rvopcodesdecoder.py @@ -265,18 +265,28 @@ def decode(self, instrObj_temp): # Register type assignment reg_type = 'x' - if file_name in ['rv_f', 'rv64_f']: + if file_name in ['rv_f', 'rv64_f', 'rv_d','rv64_d']: reg_type = 'f' for arg in args[:-1]: if arg == 'rd': - temp_instrobj.rd = (int(get_arg_val(arg)(mcode), 2), reg_type) + treg = reg_type + if any([instr_names[0].startswith(x) for x in [ + 'fcvt.w','fcvt.l','fmv.s','fmv.d','flt','feq','fle','fclass']]): + treg = 'x' + temp_instrobj.rd = (int(get_arg_val(arg)(mcode), 2), treg) if arg == 'rs1': - temp_instrobj.rs1 = (int(get_arg_val(arg)(mcode), 2), reg_type) + treg = reg_type + if any([instr_names[0].startswith(x) for x in [ + 'fsw','fsd','fcvt.s','fcvt.d','fmv.w','fmv.l']]): + treg = 'x' + temp_instrobj.rs1 = (int(get_arg_val(arg)(mcode), 2), treg) if arg == 'rs2': - temp_instrobj.rs2 = (int(get_arg_val(arg)(mcode), 2), reg_type) + treg = reg_type + temp_instrobj.rs2 = (int(get_arg_val(arg)(mcode), 2), treg) if arg == 'rs3': - temp_instrobj.rs3 = (int(get_arg_val(arg)(mcode), 2), reg_type) + treg = reg_type + temp_instrobj.rs3 = (int(get_arg_val(arg)(mcode), 2), treg) if arg == 'csr': temp_instrobj.csr = int(get_arg_val(arg)(mcode), 2) if arg == 'shamt': diff --git a/riscv_isac/main.py b/riscv_isac/main.py index 8a81e9f..d6ffb9b 100644 --- a/riscv_isac/main.py +++ b/riscv_isac/main.py @@ -179,7 +179,7 @@ def normalize(cgf_file,output_file,xlen): @cli.command(help = 'Setup the plugin which uses the information from RISCV Opcodes repository to decode.') @click.option('--url', type = str, - default='https://github.com/incoresemi/riscv-opcodes', + default='https://github.com/riscv/riscv-opcodes', required=False, help='URL to the riscv-opcodes repo') @click.option('--branch',type=str,default='master') From f4661e0790eca334d9fc3083e5df52d861a1ae06 Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Sun, 3 Apr 2022 14:29:11 +0530 Subject: [PATCH 28/41] =?UTF-8?q?Bump=20version:=200.10.1=20=E2=86=92=200.?= =?UTF-8?q?11.0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- CHANGELOG.md | 4 ++++ riscv_isac/__init__.py | 2 +- setup.cfg | 2 +- setup.py | 2 +- 4 files changed, 7 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 7d6ef1b..f71b7c7 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,10 @@ This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). +## [0.11.0] - 2022-04-03 +- Added plugins to use new rvopcode format +- Added CLI option to setup rvopcode plugin + ## [0.10.1] - 2022-02-10 - Added vxsat to supported csr_regs - Added comments to coverpoint functions for P-ext diff --git a/riscv_isac/__init__.py b/riscv_isac/__init__.py index d9a16fc..77fcb97 100644 --- a/riscv_isac/__init__.py +++ b/riscv_isac/__init__.py @@ -4,4 +4,4 @@ __author__ = """InCore Semiconductors Pvt Ltd""" __email__ = 'info@incoresemi.com' -__version__ = '0.10.1' +__version__ = '0.11.0' diff --git a/setup.cfg b/setup.cfg index 9021e1a..6159946 100644 --- a/setup.cfg +++ b/setup.cfg @@ -1,5 +1,5 @@ [bumpversion] -current_version = 0.10.1 +current_version = 0.11.0 commit = True tag = True diff --git a/setup.py b/setup.py index 86c2f8a..ef986dd 100644 --- a/setup.py +++ b/setup.py @@ -26,7 +26,7 @@ def read_requires(): setup( name='riscv_isac', - version='0.10.1', + version='0.11.0', description="RISC-V ISAC", long_description=readme + '\n\n', classifiers=[ From bb90746648fa833398d1dcc1b3e04341e2c01811 Mon Sep 17 00:00:00 2001 From: Anand Kumar S Date: Fri, 18 Feb 2022 01:25:05 +0530 Subject: [PATCH 29/41] Added method to generate cover point combinations for bitmanip xlen=32 0x33333333,0xcccccccc 0xaaaaaaaa,0x55555555 0x66666666,0x99999999, 0,1 for xlen=64 0x3333333333333333, 0xcccccccccccccccc, 0x5555555555555555, 0xaaaaaaaaaaaaaaaa, 0x6666666666666666, 0x9999999999999999,0,1 --- riscv_isac/cgf_normalize.py | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/riscv_isac/cgf_normalize.py b/riscv_isac/cgf_normalize.py index 57c0900..ea796bf 100644 --- a/riscv_isac/cgf_normalize.py +++ b/riscv_isac/cgf_normalize.py @@ -127,6 +127,25 @@ def sp_vals(bit_width,signed): dataset = list(map(conv_func,dataset)) + [int(sqrt(abs(conv_func("0x8"+"".join(["0"]*int((bit_width/4)-1)))))*(-1 if signed else 1))] + [sqrt_min,sqrt_max] return dataset + [x - 1 if x>0 else 0 for x in dataset] + [x+1 for x in dataset] +def bitmanip_dataset(bit_width,var_lst=["rs1_val","rs2_val"],signed=True): + datasets = [] + coverpoints = [] + if signed: + conv_func = lambda x: twos(x,bit_width) + else: + conv_func = lambda x: (int(x,16) if '0x' in x else int(x,2)) if isinstance(x,str) else x + for var in var_lst: + dataset = ["0x"+"".join(["5"]*int(bit_width/4)), "0x"+"".join(["a"]*int(bit_width/4)), "0x"+"".join(["3"]*int(bit_width/4)), "0x"+"".join(["6"]*int(bit_width/4)),"0x"+"".join(["9"]*int(bit_width/4)),"0x"+"".join(["c"]*int(bit_width/4)),"0x"+"".join(["0"]*int(bit_width/4)),"0x"+"".join(["f"]*int(bit_width/4))] + dataset = list(map(conv_func,dataset)) + datasets.append(dataset) + dataset = itertools.product(*datasets) + for entry in dataset: + coverpoints.append(' and '.join([var_lst[i]+"=="+str(entry[i]) for i in range(len(var_lst))])) + #print(' and '.join([var_lst[i]+"=="+str(hex(entry[i])) for i in range(len(var_lst))])) + return [(coverpoint,"Bitmanip Dataset") for coverpoint in coverpoints] + + + def sp_dataset(bit_width,var_lst=["rs1_val","rs2_val"],signed=True): coverpoints = [] datasets = [] From d9e8b7f08315999af7487edce631c0647517123f Mon Sep 17 00:00:00 2001 From: Anand Kumar S Date: Sat, 19 Feb 2022 23:36:08 +0530 Subject: [PATCH 30/41] updated comments for bitmanip_dataset --- riscv_isac/cgf_normalize.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/riscv_isac/cgf_normalize.py b/riscv_isac/cgf_normalize.py index ea796bf..556621c 100644 --- a/riscv_isac/cgf_normalize.py +++ b/riscv_isac/cgf_normalize.py @@ -128,6 +128,18 @@ def sp_vals(bit_width,signed): return dataset + [x - 1 if x>0 else 0 for x in dataset] + [x+1 for x in dataset] def bitmanip_dataset(bit_width,var_lst=["rs1_val","rs2_val"],signed=True): + ''' + Functions creates coverpoints for bitmanip instructions with following patterns + 0x3, 0xc, 0x5,0xa,0x6,0x9 each of the pattern exenteding for bit_width + - +/-1 variants of the above + + :param bit_width: Integer defining the size of the input + :param sign: Boolen value specifying whether the dataset should be interpreted as signed numbers or not. + :type sign: bool + :type bit_width: int + :return: dictionary of coverpoints + ''' + datasets = [] coverpoints = [] if signed: From f41600a1433ceb4c896ff260f58e3f9a4489ab4d Mon Sep 17 00:00:00 2001 From: Anand Kumar S Date: Thu, 10 Mar 2022 00:51:36 +0530 Subject: [PATCH 31/41] updated dataset generated for bitmanip --- riscv_isac/cgf_normalize.py | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/riscv_isac/cgf_normalize.py b/riscv_isac/cgf_normalize.py index 556621c..48ab7bc 100644 --- a/riscv_isac/cgf_normalize.py +++ b/riscv_isac/cgf_normalize.py @@ -131,7 +131,13 @@ def bitmanip_dataset(bit_width,var_lst=["rs1_val","rs2_val"],signed=True): ''' Functions creates coverpoints for bitmanip instructions with following patterns 0x3, 0xc, 0x5,0xa,0x6,0x9 each of the pattern exenteding for bit_width - - +/-1 variants of the above + for 32 bit + 0x33333333,0xcccccccc,0x55555555, 0xaaaaaaaaa,0x66666666,0x99999999 + for 64 bit + 0x3333333333333333,0xcccccccccccccccc,0x5555555555555555, 0xaaaaaaaaaaaaaaaaa, + 0x6666666666666666,0x9999999999999999 + - +1 and -1 variants of the above pattern + :param bit_width: Integer defining the size of the input :param sign: Boolen value specifying whether the dataset should be interpreted as signed numbers or not. @@ -146,14 +152,14 @@ def bitmanip_dataset(bit_width,var_lst=["rs1_val","rs2_val"],signed=True): conv_func = lambda x: twos(x,bit_width) else: conv_func = lambda x: (int(x,16) if '0x' in x else int(x,2)) if isinstance(x,str) else x + dataset = ["0x"+"".join(["5"]*int(bit_width/4)), "0x"+"".join(["a"]*int(bit_width/4)), "0x"+"".join(["3"]*int(bit_width/4)), "0x"+"".join(["c"]*int(bit_width/4)),"0x"+"".join(["6"]*int(bit_width/4)),"0x"+"".join(["9"]*int(bit_width/4)),0] + dataset = list(map(conv_func,dataset)) + dataset = dataset + [x - 1 if x > 0 else 0 for x in dataset] + [x+1 for x in dataset] for var in var_lst: - dataset = ["0x"+"".join(["5"]*int(bit_width/4)), "0x"+"".join(["a"]*int(bit_width/4)), "0x"+"".join(["3"]*int(bit_width/4)), "0x"+"".join(["6"]*int(bit_width/4)),"0x"+"".join(["9"]*int(bit_width/4)),"0x"+"".join(["c"]*int(bit_width/4)),"0x"+"".join(["0"]*int(bit_width/4)),"0x"+"".join(["f"]*int(bit_width/4))] - dataset = list(map(conv_func,dataset)) datasets.append(dataset) dataset = itertools.product(*datasets) for entry in dataset: coverpoints.append(' and '.join([var_lst[i]+"=="+str(entry[i]) for i in range(len(var_lst))])) - #print(' and '.join([var_lst[i]+"=="+str(hex(entry[i])) for i in range(len(var_lst))])) return [(coverpoint,"Bitmanip Dataset") for coverpoint in coverpoints] From 9265b222ddfcbdc55c0b51e017e0fb966865b83a Mon Sep 17 00:00:00 2001 From: Anand Kumar S Date: Thu, 10 Mar 2022 20:17:35 +0530 Subject: [PATCH 32/41] added 0xf pattern (-1) in bitmanip_dataset method --- riscv_isac/cgf_normalize.py | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/riscv_isac/cgf_normalize.py b/riscv_isac/cgf_normalize.py index 48ab7bc..6ee8fdb 100644 --- a/riscv_isac/cgf_normalize.py +++ b/riscv_isac/cgf_normalize.py @@ -130,7 +130,7 @@ def sp_vals(bit_width,signed): def bitmanip_dataset(bit_width,var_lst=["rs1_val","rs2_val"],signed=True): ''' Functions creates coverpoints for bitmanip instructions with following patterns - 0x3, 0xc, 0x5,0xa,0x6,0x9 each of the pattern exenteding for bit_width + 0x3, 0xc, 0x5,0xa,0x6,0x9,0 each of the pattern exenteding for bit_width for 32 bit 0x33333333,0xcccccccc,0x55555555, 0xaaaaaaaaa,0x66666666,0x99999999 for 64 bit @@ -152,9 +152,16 @@ def bitmanip_dataset(bit_width,var_lst=["rs1_val","rs2_val"],signed=True): conv_func = lambda x: twos(x,bit_width) else: conv_func = lambda x: (int(x,16) if '0x' in x else int(x,2)) if isinstance(x,str) else x - dataset = ["0x"+"".join(["5"]*int(bit_width/4)), "0x"+"".join(["a"]*int(bit_width/4)), "0x"+"".join(["3"]*int(bit_width/4)), "0x"+"".join(["c"]*int(bit_width/4)),"0x"+"".join(["6"]*int(bit_width/4)),"0x"+"".join(["9"]*int(bit_width/4)),0] +# dataset for 0x5, 0xa, 0x3, 0xc, 0x6, 0x9 patterns + dataset = ["0x"+"".join(["5"]*int(bit_width/4)), "0x"+"".join(["a"]*int(bit_width/4)), "0x"+"".join(["3"]*int(bit_width/4)), "0x"+"".join(["c"]*int(bit_width/4)),"0x"+"".join(["6"]*int(bit_width/4)),"0x"+"".join(["9"]*int(bit_width/4))] dataset = list(map(conv_func,dataset)) - dataset = dataset + [x - 1 if x > 0 else 0 for x in dataset] + [x+1 for x in dataset] + +# dataset0 is for 0,1 and 0xf pattern. 0xf pattern is added instead of -1 so that code for checking coverpoints in coverage.py +# is kept simple. + + dataset0 = [0,1,"0x"+"".join(["f"]*int(bit_width/4))] + dataset0 = list(map(conv_func,dataset0)) + dataset = dataset + [x - 1 for x in dataset] + [x+1 for x in dataset] + dataset0 for var in var_lst: datasets.append(dataset) dataset = itertools.product(*datasets) From 7a6f45a723566daf05f7592331829be97e266956 Mon Sep 17 00:00:00 2001 From: Anand Kumar S Date: Tue, 15 Mar 2022 11:13:02 +0530 Subject: [PATCH 33/41] bump version from 0.10.1 to 0.10.2 --- CHANGELOG.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index f71b7c7..6f36a97 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,6 +6,9 @@ This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.htm - Added plugins to use new rvopcode format - Added CLI option to setup rvopcode plugin +## [0.10.2] - 2022-03-15 +- Added method to generate data patterns for bitmanip instructions +- ## [0.10.1] - 2022-02-10 - Added vxsat to supported csr_regs - Added comments to coverpoint functions for P-ext From b4335c1b42b4be95296a5afb3167478b80bebf18 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Thu, 7 Apr 2022 15:15:43 +0530 Subject: [PATCH 34/41] Inclusion of unratified extensions @pawks --- riscv_isac/data/rvopcodesdecoder.py | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv_isac/data/rvopcodesdecoder.py b/riscv_isac/data/rvopcodesdecoder.py index 2502e85..a4879fb 100644 --- a/riscv_isac/data/rvopcodesdecoder.py +++ b/riscv_isac/data/rvopcodesdecoder.py @@ -104,6 +104,7 @@ def create_inst_dict(file_filter): # file_names contains all files to be parsed in the riscv-opcodes directory file_names = glob.glob(f'{opcodes_dir}/rv{file_filter}') + file_names += glob.glob(f'{opcodes_dir}/unratified/rv{file_filter}') # first pass if for standard/original instructions for f in file_names: From ce5c5cb9169d539a5083efce0617fae3f1817995 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Tue, 12 Apr 2022 09:51:00 +0530 Subject: [PATCH 35/41] Handling pseudo-ops --- riscv_isac/data/rvopcodesdecoder.py | 244 ++++++++++++++++------------ 1 file changed, 144 insertions(+), 100 deletions(-) diff --git a/riscv_isac/data/rvopcodesdecoder.py b/riscv_isac/data/rvopcodesdecoder.py index a4879fb..ec4af44 100644 --- a/riscv_isac/data/rvopcodesdecoder.py +++ b/riscv_isac/data/rvopcodesdecoder.py @@ -3,9 +3,13 @@ from collections import defaultdict import pprint import os +from unicodedata import name from constants import * import riscv_isac.plugins as plugins +from riscv_isac.log import logger + +from riscv_isac.InstructionObject import instructionObject # Closure to get argument value def get_arg_val(arg: str): @@ -40,7 +44,9 @@ def setup(self, arch: str): # Create nested dictionary nested_dict = lambda: defaultdict(nested_dict) disassembler.INST_DICT = nested_dict() - disassembler.create_inst_dict('*') + disassembler.create_inst_dict('_zicsr') + + disassembler.print_instr_dict() def process_enc_line(line: str): @@ -106,7 +112,7 @@ def create_inst_dict(file_filter): file_names = glob.glob(f'{opcodes_dir}/rv{file_filter}') file_names += glob.glob(f'{opcodes_dir}/unratified/rv{file_filter}') - # first pass if for standard/original instructions + # first pass for standard/original instructions for f in file_names: with open(f) as fp: lines = (line.rstrip() @@ -129,6 +135,37 @@ def create_inst_dict(file_filter): # [ [(funct, val)], name, [args] ] disassembler.INST_LIST.append([functs, name, args]) + # second pass for pseudo-ops + for f in file_names: + with open(f) as fp: + lines = (line.rstrip() + for line in fp) # All lines including the blank ones + lines = list(line for line in lines if line) # Non-blank lines + lines = list( + line for line in lines + if not line.startswith("#")) # Remove comment lines + + # go through each line of the file + for line in lines: + # ignore all lines not starting with $pseudo + if '$pseudo' not in line: + continue + + # use the regex pseudo_regex from constants.py to find the dependent + # extension, dependent instruction, the pseudo_op in question and + # its encoding + (ext, orig_inst, pseudo_inst, line) = pseudo_regex.findall(line)[0] + + # call process_enc_line to get the data about the current + # instruction + (functs, (name, args)) = disassembler.process_enc_line(pseudo_inst + ' ' + line) + args.append(os.path.basename(f)) + + # [ [(funct, val)], name, [args] ] + disassembler.INST_LIST.append([functs, name, args]) + + # third pass for pseudo-ops + # Insert all instructions to the root of the dictionary disassembler.INST_DICT['root'] = disassembler.INST_LIST @@ -210,13 +247,18 @@ def get_instr(func_dict, mcode: int): ''' Recursively extracts the instruction from the dictionary ''' + global instr # Get list of functions keys = func_dict.keys() + num_keys = len(keys) for key in keys: - if type(key) == str: - return func_dict - if type(key) == tuple: + if type(key) == str and num_keys == 1: + return (key, func_dict[key]) + elif type(key) == tuple: val = get_funct(key, mcode) + else: # There must be pseudo-ops + instr = (key, func_dict[key]) + continue temp_func_dict = func_dict[key][val] if temp_func_dict.keys(): a = disassembler.get_instr(temp_func_dict, mcode) @@ -239,111 +281,103 @@ def decode(self, instrObj_temp): (instructionObject) : Instruction object with names and arguments filled None : When the dissassembler fails to decode the machine code ''' - + global instr + instr = None + temp_instrobj = instrObj_temp mcode = temp_instrobj.instr name_args = disassembler.get_instr(disassembler.INST_DICT, mcode) + if not name_args: + name_args = instr # Fill out the partially filled instructionObject if name_args: - instr_names = list(name_args.keys()) - if len(instr_names) <= 1: - # Fill instruction name - temp_instrobj.instr_name = instr_names[0] - - # Fill arguments - args = name_args[instr_names[0]] - imm = '' - - # Get extension - file_name = args[-1] - - # If instruction from P extension - if file_name in ['rv_p', 'rv32_p', 'rv64_p']: - temp_instrobj.is_rvp = True - - # Register type assignment - reg_type = 'x' - if file_name in ['rv_f', 'rv64_f', 'rv_d','rv64_d']: - reg_type = 'f' - - for arg in args[:-1]: - if arg == 'rd': - treg = reg_type - if any([instr_names[0].startswith(x) for x in [ - 'fcvt.w','fcvt.l','fmv.s','fmv.d','flt','feq','fle','fclass']]): - treg = 'x' - temp_instrobj.rd = (int(get_arg_val(arg)(mcode), 2), treg) - if arg == 'rs1': - treg = reg_type - if any([instr_names[0].startswith(x) for x in [ - 'fsw','fsd','fcvt.s','fcvt.d','fmv.w','fmv.l']]): - treg = 'x' - temp_instrobj.rs1 = (int(get_arg_val(arg)(mcode), 2), treg) - if arg == 'rs2': - treg = reg_type - temp_instrobj.rs2 = (int(get_arg_val(arg)(mcode), 2), treg) - if arg == 'rs3': - treg = reg_type - temp_instrobj.rs3 = (int(get_arg_val(arg)(mcode), 2), treg) - if arg == 'csr': - temp_instrobj.csr = int(get_arg_val(arg)(mcode), 2) - if arg == 'shamt': - temp_instrobj.shamt = int(get_arg_val(arg)(mcode), 2) - if arg == 'shamt': - temp_instrobj.shamt = int(get_arg_val(arg)(mcode), 2) - if arg == 'shamtw': - temp_instrobj.shamt = int(get_arg_val(arg)(mcode), 2) - if arg == 'shamtw4': - temp_instrobj.shamt = int(get_arg_val(arg)(mcode), 2) - if arg == 'succ': - temp_instrobj.succ = int(get_arg_val(arg)(mcode), 2) - if arg == 'pred': - temp_instrobj.pred = int(get_arg_val(arg)(mcode), 2) - if arg == 'rl': - temp_instrobj.rl = int(get_arg_val(arg)(mcode), 2) - if arg == 'aq': - temp_instrobj.aq = int(get_arg_val(arg)(mcode), 2) - if arg == 'rm': - temp_instrobj.rm = int(get_arg_val(arg)(mcode), 2) - - if arg.find('imm') != -1: - if arg in ['imm12', 'imm20', 'zimm', 'imm2', 'imm3', 'imm4', 'imm5']: - imm = get_arg_val(arg)(mcode) - - # Reoder immediates - if arg == 'jimm20': - imm_temp = get_arg_val(arg)(mcode) - imm = imm_temp[0] + imm_temp[12:21] + imm_temp[11] + imm_temp[1:11] + '0' - if arg == 'imm12hi': - imm_temp = get_arg_val(arg)(mcode) + instr_name = name_args[0] + + # Fill instruction name + temp_instrobj.instr_name = instr_name + # Fill arguments + args = name_args[1] + imm = '' + # Get extension + file_name = args[-1] + # If instruction from P extension + if file_name in ['rv_p', 'rv32_p', 'rv64_p']: + temp_instrobj.is_rvp = True + # Register type assignment + reg_type = 'x' + if file_name in ['rv_f', 'rv64_f', 'rv_d','rv64_d']: + reg_type = 'f' + for arg in args[:-1]: + if arg == 'rd': + treg = reg_type + if any([instr_name.startswith(x) for x in [ + 'fcvt.w','fcvt.l','fmv.s','fmv.d','flt','feq','fle','fclass']]): + treg = 'x' + temp_instrobj.rd = (int(get_arg_val(arg)(mcode), 2), treg) + if arg == 'rs1': + treg = reg_type + if any([instr_name.startswith(x) for x in [ + 'fsw','fsd','fcvt.s','fcvt.d','fmv.w','fmv.l']]): + treg = 'x' + temp_instrobj.rs1 = (int(get_arg_val(arg)(mcode), 2), treg) + if arg == 'rs2': + treg = reg_type + temp_instrobj.rs2 = (int(get_arg_val(arg)(mcode), 2), treg) + if arg == 'rs3': + treg = reg_type + temp_instrobj.rs3 = (int(get_arg_val(arg)(mcode), 2), treg) + if arg == 'csr': + temp_instrobj.csr = int(get_arg_val(arg)(mcode), 2) + if arg == 'shamt': + temp_instrobj.shamt = int(get_arg_val(arg)(mcode), 2) + if arg == 'shamt': + temp_instrobj.shamt = int(get_arg_val(arg)(mcode), 2) + if arg == 'shamtw': + temp_instrobj.shamt = int(get_arg_val(arg)(mcode), 2) + if arg == 'shamtw4': + temp_instrobj.shamt = int(get_arg_val(arg)(mcode), 2) + if arg == 'succ': + temp_instrobj.succ = int(get_arg_val(arg)(mcode), 2) + if arg == 'pred': + temp_instrobj.pred = int(get_arg_val(arg)(mcode), 2) + if arg == 'rl': + temp_instrobj.rl = int(get_arg_val(arg)(mcode), 2) + if arg == 'aq': + temp_instrobj.aq = int(get_arg_val(arg)(mcode), 2) + if arg == 'rm': + temp_instrobj.rm = int(get_arg_val(arg)(mcode), 2) + if arg.find('imm') != -1: + if arg in ['imm12', 'imm20', 'zimm', 'imm2', 'imm3', 'imm4', 'imm5']: + imm = get_arg_val(arg)(mcode) + # Reoder immediates + if arg == 'jimm20': + imm_temp = get_arg_val(arg)(mcode) + imm = imm_temp[0] + imm_temp[12:21] + imm_temp[11] + imm_temp[1:11] + '0' + if arg == 'imm12hi': + imm_temp = get_arg_val(arg)(mcode) + imm = imm_temp + imm + if arg == 'imm12lo': + imm_temp = get_arg_val(arg)(mcode) + imm = imm + imm_temp + if arg == 'bimm12hi': + imm_temp = get_arg_val(arg)(mcode) + if imm: + imm = imm_temp[0] + imm[-1] + imm_temp[1:] + imm[0:4] + '0' + else: imm = imm_temp + imm - if arg == 'imm12lo': - imm_temp = get_arg_val(arg)(mcode) + if arg == 'bimm12lo': + imm_temp = get_arg_val(arg)(mcode) + if imm: + imm = imm[0] + imm_temp[-1] + imm[1:] + imm_temp[0:4] + '0' + else: imm = imm + imm_temp - if arg == 'bimm12hi': - imm_temp = get_arg_val(arg)(mcode) - - if imm: - imm = imm_temp[0] + imm[-1] + imm_temp[1:] + imm[0:4] + '0' - else: - imm = imm_temp + imm - if arg == 'bimm12lo': - imm_temp = get_arg_val(arg)(mcode) - if imm: - imm = imm[0] + imm_temp[-1] + imm[1:] + imm_temp[0:4] + '0' - else: - imm = imm + imm_temp - if imm: - numbits = len(imm) - temp_instrobj.imm = disassembler.twos_comp(int(imm, 2), numbits) - - return temp_instrobj - else: - logger.error('Found two instructions in the leaf node') - return temp_instrobj + if imm: + numbits = len(imm) + temp_instrobj.imm = disassembler.twos_comp(int(imm, 2), numbits) + return temp_instrobj else: return temp_instrobj @@ -376,3 +410,13 @@ def print_instr_dict(): f = open('dict_tree.txt', 'w+') f.write(s) f.close() + +if __name__ == '__main__': + + intr = instructionObject(0x205073, None, None) + + dec = disassembler() + dec.setup('rv32') + lala = dec.decode(intr) + + print(lala.instr_name) \ No newline at end of file From 254820633a80d44afb91e2311483c2fe35e6bd32 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Tue, 12 Apr 2022 09:51:29 +0530 Subject: [PATCH 36/41] Updated constants --- riscv_isac/data/constants.py | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/riscv_isac/data/constants.py b/riscv_isac/data/constants.py index e23f3d4..b6a4351 100644 --- a/riscv_isac/data/constants.py +++ b/riscv_isac/data/constants.py @@ -21,6 +21,7 @@ '^\$pseudo_op\s+(?Prv[\d]*_[\w].*)::\s*(?P.*?)\s+(?P.*?)\s+(?P.*)$' , re.M) +imported_regex = re.compile('^\s*\$import\s*(?P.*)\s*::\s*(?P.*)', re.M) # # Trap cause codes @@ -425,12 +426,10 @@ arg_lut['rm'] = (14, 12) arg_lut['funct3'] = (14, 12) arg_lut['funct2'] = (26, 25) - -arg_lut['funct12'] = (31, 20) - arg_lut['imm20'] = (31, 12) arg_lut['jimm20'] = (31, 12) arg_lut['imm12'] = (31, 20) +arg_lut['csr'] = (31, 20) arg_lut['imm12hi'] = (31, 25) arg_lut['bimm12hi'] = (31, 25) arg_lut['imm12lo'] = (11, 7) @@ -573,6 +572,9 @@ latex_inst_type['R-type'] = {} latex_inst_type['R-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ 'rs1', 'rs2', 'funct7'] +latex_inst_type['R4-type'] = {} +latex_inst_type['R4-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ + 'rs1', 'rs2', 'funct2', 'rs3'] latex_inst_type['I-type'] = {} latex_inst_type['I-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ 'rs1', 'imm12'] @@ -586,6 +588,10 @@ latex_inst_type['U-type']['variable_fields'] = ['opcode', 'rd', 'imm20'] latex_inst_type['J-type'] = {} latex_inst_type['J-type']['variable_fields'] = ['opcode', 'rd', 'jimm20'] -latex_inst_type['R4-type'] = {} -latex_inst_type['R4-type']['variable_fields'] = ['opcode', 'rd', 'funct3', \ - 'rs1', 'rs2', 'funct2', 'rs3'] +latex_fixed_fields = [] +latex_fixed_fields.append((31,25)) +latex_fixed_fields.append((24,20)) +latex_fixed_fields.append((19,15)) +latex_fixed_fields.append((14,12)) +latex_fixed_fields.append((11,7)) +latex_fixed_fields.append((6,0)) From 65d1ed005a677a8e7b45b7a14c8b5de9c6f960ad Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Tue, 12 Apr 2022 11:22:19 +0530 Subject: [PATCH 37/41] Handling imports --- riscv_isac/data/rvopcodesdecoder.py | 61 ++++++++++++++++++++++++----- 1 file changed, 52 insertions(+), 9 deletions(-) diff --git a/riscv_isac/data/rvopcodesdecoder.py b/riscv_isac/data/rvopcodesdecoder.py index ec4af44..7a3d05b 100644 --- a/riscv_isac/data/rvopcodesdecoder.py +++ b/riscv_isac/data/rvopcodesdecoder.py @@ -44,10 +44,8 @@ def setup(self, arch: str): # Create nested dictionary nested_dict = lambda: defaultdict(nested_dict) disassembler.INST_DICT = nested_dict() - disassembler.create_inst_dict('_zicsr') - - disassembler.print_instr_dict() - + disassembler.create_inst_dict('*') + def process_enc_line(line: str): functs = [] @@ -107,7 +105,6 @@ def create_inst_dict(file_filter): # Default riscv-opcodes directory opcodes_dir = os.path.join(os.path.dirname(__file__),"riscv_opcodes/") - # file_names contains all files to be parsed in the riscv-opcodes directory file_names = glob.glob(f'{opcodes_dir}/rv{file_filter}') file_names += glob.glob(f'{opcodes_dir}/unratified/rv{file_filter}') @@ -163,9 +160,53 @@ def create_inst_dict(file_filter): # [ [(funct, val)], name, [args] ] disassembler.INST_LIST.append([functs, name, args]) - - # third pass for pseudo-ops + # third pass for imports + for f in file_names: + with open(f) as fp: + lines = (line.rstrip() + for line in fp) # All lines including the blank ones + lines = list(line for line in lines if line) # Non-blank lines + lines = list( + line for line in lines + if not line.startswith("#")) # remove comment lines + + for line in lines: + # if the an instruction needs to be imported then go to the + # respective file and pick the line that has the instruction. + # The variable 'line' will now point to the new line from the + # imported file + + # ignore all lines starting with $import and $pseudo + if '$import' not in line : + continue + + (import_ext, reg_instr) = imported_regex.findall(line)[0] + + path = opcodes_dir + import_ext + # Find the file where the dependent extension exist. + if not os.path.exists(path): + ext1 = f'{opcodes_dir}unratified/{import_ext}' + if not os.path.exists(ext1): + raise SystemExit(1) + else: + ext = ext1 + else: + ext = path + + # Fetch the dependent instruction + for oline in open(ext): + if not re.findall(f'^\s*{reg_instr}',oline): + continue + else: + break + + (functs, (name, args)) = disassembler.process_enc_line(oline) + args.append(os.path.basename(f)) + + # [ [(funct, val)], name, [args] ] + disassembler.INST_LIST.append([functs, name, args]) + # Insert all instructions to the root of the dictionary disassembler.INST_DICT['root'] = disassembler.INST_LIST @@ -349,6 +390,8 @@ def decode(self, instrObj_temp): temp_instrobj.aq = int(get_arg_val(arg)(mcode), 2) if arg == 'rm': temp_instrobj.rm = int(get_arg_val(arg)(mcode), 2) + if arg == 'csr': + temp_instrobj.imm = int(get_arg_val(arg)(mcode), 2) if arg.find('imm') != -1: if arg in ['imm12', 'imm20', 'zimm', 'imm2', 'imm3', 'imm4', 'imm5']: imm = get_arg_val(arg)(mcode) @@ -413,8 +456,8 @@ def print_instr_dict(): if __name__ == '__main__': - intr = instructionObject(0x205073, None, None) - + intr = instructionObject(0xC8002073, None, None) + dec = disassembler() dec.setup('rv32') lala = dec.decode(intr) From 3836ee841343b970daf7b7edba3bb146430246d7 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Tue, 12 Apr 2022 12:13:31 +0530 Subject: [PATCH 38/41] Decoder test code --- riscv_isac/data/rvopcodesdecoder.py | 49 +++++++++++++++++++++++------ 1 file changed, 39 insertions(+), 10 deletions(-) diff --git a/riscv_isac/data/rvopcodesdecoder.py b/riscv_isac/data/rvopcodesdecoder.py index 7a3d05b..7a3d8dc 100644 --- a/riscv_isac/data/rvopcodesdecoder.py +++ b/riscv_isac/data/rvopcodesdecoder.py @@ -3,7 +3,6 @@ from collections import defaultdict import pprint import os -from unicodedata import name from constants import * import riscv_isac.plugins as plugins @@ -11,6 +10,9 @@ from riscv_isac.InstructionObject import instructionObject +import riscv_isac.plugins +from riscv_isac.plugins import internaldecoder + # Closure to get argument value def get_arg_val(arg: str): (msb, lsb) = arg_lut[arg] @@ -45,7 +47,7 @@ def setup(self, arch: str): nested_dict = lambda: defaultdict(nested_dict) disassembler.INST_DICT = nested_dict() disassembler.create_inst_dict('*') - + def process_enc_line(line: str): functs = [] @@ -422,10 +424,9 @@ def decode(self, instrObj_temp): temp_instrobj.imm = disassembler.twos_comp(int(imm, 2), numbits) return temp_instrobj else: - return temp_instrobj + return None # Utility functions - def twos_comp(val, bits): ''' Get the two_complement value @@ -456,10 +457,38 @@ def print_instr_dict(): if __name__ == '__main__': - intr = instructionObject(0xC8002073, None, None) - - dec = disassembler() - dec.setup('rv32') - lala = dec.decode(intr) + new_decoder = disassembler() + new_decoder.setup('arch64') + old_decoder = internaldecoder.disassembler() + old_decoder.setup('rv64') - print(lala.instr_name) \ No newline at end of file + + f1 = open('no_match.txt', 'w+') + f2 = open('matched.txt', 'w+') + + with open('ratified.txt') as fp: + for line in fp: + mcode = int(line, 16) + + instrObj = instructionObject(mcode, None, None) + + new_instrObj = new_decoder.decode(instrObj) + old_instrObj = new_decoder.decode(instrObj) + + if old_instrObj != new_instrObj: + old_name = 'None' + new_name = 'None' + if old_instrObj: + old_name = old_instrObj.instr_name + if new_instrObj: + new_name = new_instrObj.instr_name + + f1.write(f'New decoder gives: {new_name} and Old decoder gives: {old_name} for {hex(mcode)}\n') + else: + name = 'None' + if old_instrObj: + name = old_instrObj.instr_name + f2.write(f'Matched! Found {name} for {hex(mcode)}\n') + + f1.close() + f2.close() \ No newline at end of file From ffd3fa873d8797f3f7a5014dcb934c48c6a6ac67 Mon Sep 17 00:00:00 2001 From: Edwin Joy Date: Tue, 12 Apr 2022 12:14:45 +0530 Subject: [PATCH 39/41] Code cleanup @pawks --- riscv_isac/data/rvopcodesdecoder.py | 43 +---------------------------- 1 file changed, 1 insertion(+), 42 deletions(-) diff --git a/riscv_isac/data/rvopcodesdecoder.py b/riscv_isac/data/rvopcodesdecoder.py index 7a3d8dc..ea421e7 100644 --- a/riscv_isac/data/rvopcodesdecoder.py +++ b/riscv_isac/data/rvopcodesdecoder.py @@ -10,9 +10,6 @@ from riscv_isac.InstructionObject import instructionObject -import riscv_isac.plugins -from riscv_isac.plugins import internaldecoder - # Closure to get argument value def get_arg_val(arg: str): (msb, lsb) = arg_lut[arg] @@ -453,42 +450,4 @@ def print_instr_dict(): s = printer.pformat(disassembler.default_to_regular(disassembler.INST_DICT)) f = open('dict_tree.txt', 'w+') f.write(s) - f.close() - -if __name__ == '__main__': - - new_decoder = disassembler() - new_decoder.setup('arch64') - old_decoder = internaldecoder.disassembler() - old_decoder.setup('rv64') - - - f1 = open('no_match.txt', 'w+') - f2 = open('matched.txt', 'w+') - - with open('ratified.txt') as fp: - for line in fp: - mcode = int(line, 16) - - instrObj = instructionObject(mcode, None, None) - - new_instrObj = new_decoder.decode(instrObj) - old_instrObj = new_decoder.decode(instrObj) - - if old_instrObj != new_instrObj: - old_name = 'None' - new_name = 'None' - if old_instrObj: - old_name = old_instrObj.instr_name - if new_instrObj: - new_name = new_instrObj.instr_name - - f1.write(f'New decoder gives: {new_name} and Old decoder gives: {old_name} for {hex(mcode)}\n') - else: - name = 'None' - if old_instrObj: - name = old_instrObj.instr_name - f2.write(f'Matched! Found {name} for {hex(mcode)}\n') - - f1.close() - f2.close() \ No newline at end of file + f.close() \ No newline at end of file From a3293f0aa7c0a7b5e09ba1dd1724f28947f6902c Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Tue, 12 Apr 2022 22:07:45 +0530 Subject: [PATCH 40/41] Update rvopcodesdecoder.rst --- docs/source/rvopcodesdecoder.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/source/rvopcodesdecoder.rst b/docs/source/rvopcodesdecoder.rst index b25333c..cb87497 100644 --- a/docs/source/rvopcodesdecoder.rst +++ b/docs/source/rvopcodesdecoder.rst @@ -34,4 +34,6 @@ Using the decoder with ISAC for coverage To use `rvopcodesdecoder` as the decoder in RISCV-ISAC, ``rvopcodesdecoder`` should be supplied as argument for ``--decoder-name`` option with the ``--decoder-path`` set to the path of ``rvop-plugin`` generated in the previous step.. For example, :: riscv_isac --verbose info coverage --decoder-name rvopcodesdecoder --decoder-path ./rvop-plugin -t trace.log --parser-name spike -o coverage.rpt -e add-01.out -c rv64i.cgf -x 64 + +.. note:: Pseudo instructions are always decoded into the mnemonics of the base instruction in this plugin. For example, `zext.h` is always decoded as `pack` only. From c152cae7bc11b73f1264431ef78431c71705da48 Mon Sep 17 00:00:00 2001 From: S Pawan Kumar Date: Wed, 13 Apr 2022 09:56:00 +0530 Subject: [PATCH 41/41] Fixed error handling in setup and incase of unsupported representation. --- riscv_isac/data/rvopcodesdecoder.py | 18 +++++++++++------- riscv_isac/main.py | 3 ++- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/riscv_isac/data/rvopcodesdecoder.py b/riscv_isac/data/rvopcodesdecoder.py index ea421e7..22bf061 100644 --- a/riscv_isac/data/rvopcodesdecoder.py +++ b/riscv_isac/data/rvopcodesdecoder.py @@ -159,7 +159,7 @@ def create_inst_dict(file_filter): # [ [(funct, val)], name, [args] ] disassembler.INST_LIST.append([functs, name, args]) - + # third pass for imports for f in file_names: with open(f) as fp: @@ -181,9 +181,9 @@ def create_inst_dict(file_filter): continue (import_ext, reg_instr) = imported_regex.findall(line)[0] - + path = opcodes_dir + import_ext - # Find the file where the dependent extension exist. + # Find the file where the dependent extension exist. if not os.path.exists(path): ext1 = f'{opcodes_dir}unratified/{import_ext}' if not os.path.exists(ext1): @@ -199,13 +199,17 @@ def create_inst_dict(file_filter): continue else: break - + (functs, (name, args)) = disassembler.process_enc_line(oline) args.append(os.path.basename(f)) # [ [(funct, val)], name, [args] ] disassembler.INST_LIST.append([functs, name, args]) + if not disassembler.INST_LIST: + logger.error("No instruction encodings found.") + raise SystemExit + # Insert all instructions to the root of the dictionary disassembler.INST_DICT['root'] = disassembler.INST_LIST @@ -323,7 +327,7 @@ def decode(self, instrObj_temp): ''' global instr instr = None - + temp_instrobj = instrObj_temp mcode = temp_instrobj.instr @@ -335,7 +339,7 @@ def decode(self, instrObj_temp): # Fill out the partially filled instructionObject if name_args: instr_name = name_args[0] - + # Fill instruction name temp_instrobj.instr_name = instr_name # Fill arguments @@ -450,4 +454,4 @@ def print_instr_dict(): s = printer.pformat(disassembler.default_to_regular(disassembler.INST_DICT)) f = open('dict_tree.txt', 'w+') f.write(s) - f.close() \ No newline at end of file + f.close() diff --git a/riscv_isac/main.py b/riscv_isac/main.py index d6ffb9b..1b6ada6 100644 --- a/riscv_isac/main.py +++ b/riscv_isac/main.py @@ -206,6 +206,7 @@ def setup(url,branch, plugin_path, rvop_path): if clone == 'Y' or clone == 'y': logger.debug("Cloning from Git.") repo = Repo.clone_from(url, rvop_path) + repo.git.checkout(branch) else: logger.error("Exiting Setup.") raise SystemExit @@ -213,7 +214,7 @@ def setup(url,branch, plugin_path, rvop_path): else: logger.debug("Cloning from Git.") repo = Repo.clone_from(url, target_dir) - repo.git.checkout(branch) + repo.git.checkout(branch) plugin_file = os.path.join(os.path.dirname(__file__), "data/rvopcodesdecoder.py") constants_file = os.path.join(os.path.dirname(__file__), "data/constants.py") logger.debug("Copying plugin files.")