Bump version: 0.10.0 → 0.10.1

riscv-software-src · Feb 9, 2022 · 720cc74 · 720cc74
1 parent 68d38be
commit 720cc74
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Showing 4 changed files with 8 additions and 3 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -2,6 +2,11 @@
 
 This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+## [0.10.1] - 2022-02-10
+- Added vxsat to supported csr_regs
+- Added comments to coverpoint functions for P-ext
+- Removed unused tuple type for bit_width parameters in P-ext coverpoint functions
+
 ## [0.10.0] - 2022-01-27
 - Added support for instructions from B extension.
 - Bug fix for bgeu instruction.

diff --git a/riscv_isac/__init__.py b/riscv_isac/__init__.py
@@ -4,4 +4,4 @@
 
 __author__ = """InCore Semiconductors Pvt Ltd"""
 __email__ = '[email protected]'
-__version__ = '0.10.0'
+__version__ = '0.10.1'
diff --git a/setup.cfg b/setup.cfg
@@ -1,5 +1,5 @@
 [bumpversion]
-current_version = 0.10.0
+current_version = 0.10.1
 commit = True
 tag = True
 

diff --git a/setup.py b/setup.py
@@ -26,7 +26,7 @@ def read_requires():
 
 setup(
     name='riscv_isac',
-    version='0.10.0',
+    version='0.10.1',
     description="RISC-V ISAC",
     long_description=readme + '\n\n',
     classifiers=[