From cc19a86593e2d90b4e64f9b28dc2e8876a2c02d4 Mon Sep 17 00:00:00 2001 From: Yung-Ching Hsiao Date: Wed, 9 Feb 2022 14:43:19 +0800 Subject: [PATCH 1/3] add vxsat to supported csr_regs --- riscv_isac/coverage.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv_isac/coverage.py b/riscv_isac/coverage.py index bf27d9f..c071da0 100644 --- a/riscv_isac/coverage.py +++ b/riscv_isac/coverage.py @@ -222,7 +222,8 @@ def __init__ (self, xlen): "scause": int('142',16), "stval": int('143',16), "sip": int('144',16), - "satp": int('180',16) + "satp": int('180',16), + "vxsat": int('009',16) } for i in range(16): self.csr_regs["pmpaddr"+str(i)] = int('3B0',16)+i @@ -289,7 +290,6 @@ def __init__ (self, xlen, flen): else: self.f_rf = ['0000000000000000']*32 self.fcsr = 0 - self.vxsat = 0 self.pc = 0 class statistics: From 68d38be732ebdb0a423353782e1e78b360e96d41 Mon Sep 17 00:00:00 2001 From: Yung-Ching Hsiao Date: Wed, 9 Feb 2022 16:38:49 +0800 Subject: [PATCH 2/3] Add comments to coverpoint functions for P-ext and remove unused tuple type for their bit_width parameters --- riscv_isac/cgf_normalize.py | 59 +++++++++++++++++++++++++------------ 1 file changed, 40 insertions(+), 19 deletions(-) diff --git a/riscv_isac/cgf_normalize.py b/riscv_isac/cgf_normalize.py index 7d5bf26..57c0900 100644 --- a/riscv_isac/cgf_normalize.py +++ b/riscv_isac/cgf_normalize.py @@ -28,19 +28,25 @@ def twos(val,bits): return val def simd_val_comb(xlen, bit_width, signed=True): - if type(bit_width)==tuple: - bit_width1, bit_width2 = bit_width - else: - bit_width1, bit_width2 = bit_width, bit_width + ''' + This function returns coverpoints for operands rs1 and rs2 holding SIMD values. A set of coverpoints will be produced for each SIMD element. + + :param xlen: size of the integer registers + :param bit_width: size of each SIMD element + :param signed: whether the SIMD elements are signed or unsigned + + :type xlen: int + :type bit_width: int + :type signed: bool + ''' fmt = {8: 'b', 16: 'h', 32: 'w', 64: 'd'} - sz1 = fmt[bit_width1] - sz2 = fmt[bit_width2] - var_num = xlen//bit_width1 + sz = fmt[bit_width] + var_num = xlen//bit_width coverpoints = [] for i in range(var_num): - var1 = f'rs1_{sz1}{i}_val' - var2 = f'rs2_{sz2}{i}_val' + var1 = f'rs1_{sz}{i}_val' + var2 = f'rs2_{sz}{i}_val' if (signed): coverpoints += [(f'{var1} > 0 and {var2} > 0','simd_val_comb')] coverpoints += [(f'{var1} > 0 and {var2} < 0','simd_val_comb')] @@ -54,16 +60,22 @@ def simd_val_comb(xlen, bit_width, signed=True): return coverpoints -def simd_base_val(rs, xlen, _bit_width, signed=True): - fmt = {8: 'b', 16: 'h', 32: 'w', 64: 'd'} +def simd_base_val(rs, xlen, bit_width, signed=True): + ''' + This function returns datasets for an operand holding SIMD values. One set of data will be produced for each SIMD element. - if type(_bit_width)==tuple: - if (rs=="rs1"): - bit_width, not_used = _bit_width - else: - not_used, bit_width = _bit_width - else: - bit_width, not_used = _bit_width, _bit_width + :param rs: operand name: "rs1" or "rs2" + :param xlen: size of the integer registers + :param bit_width: size of each SIMD element + :param signed: whether the SIMD elements are signed or unsigned + + :type rs: str + :type xlen: int + :type bit_width: int + :type signed: bool + ''' + + fmt = {8: 'b', 16: 'h', 32: 'w', 64: 'd'} sz = fmt[bit_width] var_num = xlen//bit_width @@ -87,7 +99,16 @@ def simd_base_val(rs, xlen, _bit_width, signed=True): return coverpoints def simd_imm_val(imm, bit_width): - usign_val = (2**(bit_width)) + ''' + This function returns coverpoints for unsigned immediate operands, between 0 .. ((2**bit_width)-1) + + :param imm: name of the immediate operand. + :param bit_width: bit width of the immediate operand + + :type imm: str + :type bit_width: int + ''' + usign_val = 2**bit_width coverpoints = [] for i in range(usign_val): coverpoints += [(f'{imm} == {i}','simd_imm_val')] From 720cc7410e0e719a5d391f006a48459939754c67 Mon Sep 17 00:00:00 2001 From: Yung-Ching Hsiao Date: Wed, 9 Feb 2022 17:47:02 +0800 Subject: [PATCH 3/3] =?UTF-8?q?Bump=20version:=200.10.0=20=E2=86=92=200.10?= =?UTF-8?q?.1?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- CHANGELOG.md | 5 +++++ riscv_isac/__init__.py | 2 +- setup.cfg | 2 +- setup.py | 2 +- 4 files changed, 8 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index e42aae3..7d6ef1b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,11 @@ This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). +## [0.10.1] - 2022-02-10 +- Added vxsat to supported csr_regs +- Added comments to coverpoint functions for P-ext +- Removed unused tuple type for bit_width parameters in P-ext coverpoint functions + ## [0.10.0] - 2022-01-27 - Added support for instructions from B extension. - Bug fix for bgeu instruction. diff --git a/riscv_isac/__init__.py b/riscv_isac/__init__.py index d269694..d9a16fc 100644 --- a/riscv_isac/__init__.py +++ b/riscv_isac/__init__.py @@ -4,4 +4,4 @@ __author__ = """InCore Semiconductors Pvt Ltd""" __email__ = 'info@incoresemi.com' -__version__ = '0.10.0' +__version__ = '0.10.1' diff --git a/setup.cfg b/setup.cfg index 193b68f..9021e1a 100644 --- a/setup.cfg +++ b/setup.cfg @@ -1,5 +1,5 @@ [bumpversion] -current_version = 0.10.0 +current_version = 0.10.1 commit = True tag = True diff --git a/setup.py b/setup.py index 4505fd5..86c2f8a 100644 --- a/setup.py +++ b/setup.py @@ -26,7 +26,7 @@ def read_requires(): setup( name='riscv_isac', - version='0.10.0', + version='0.10.1', description="RISC-V ISAC", long_description=readme + '\n\n', classifiers=[