Merge pull request #52 from riscv-software-src/sail-parser-patch

Sail parser patch

CHANGELOG.md

@@ -2,6 +2,10 @@
 
 This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+
+## [0.16.1] - 2022-10-20
+- Fix length of commitval to 32 bits if flen is 32 for f registers in sail parser.
+
 ## [0.16.0] - 2022-09-28
 - Refactored the instruction object class
 

riscv_isac/__init__.py

@@ -4,4 +4,5 @@
 
 __author__ = """InCore Semiconductors Pvt Ltd"""
 __email__ = '[email protected]'
-__version__ = '0.16.0'
+__version__ = '0.16.1'
+

riscv_isac/coverage.py

@@ -883,7 +883,7 @@ def compute(trace_file, test_name, cgf, parser_name, decoder_name, detailed, xle
     parserclass = getattr(parserfile, parser_name)
     parser_pm.register(parserclass())
     parser = parser_pm.hook
-    parser.setup(trace=trace_file,arch="rv"+str(xlen))
+    parser.setup(trace=trace_file,arch=(xlen,flen))
 
     decoder_pm = pluggy.PluginManager("decoder")
     decoder_pm.add_hookspecs(DecoderSpec)

riscv_isac/plugins/c_sail.py

@@ -2,13 +2,17 @@
 import riscv_isac.plugins as plugins
 import riscv_isac.plugins. specification as spec
 from riscv_isac.InstructionObject import instructionObject
+from riscv_isac.log import logger
 
 class c_sail(spec.ParserSpec):
 
     @plugins.parserHookImpl
     def setup(self, trace, arch):
         self.trace = trace
         self.arch = arch
+        if arch[1] == 32:
+            logger.warn('FLEN is set to 32. Commit values in the log will be terminated to 32 bits \
+irrespective of their original size.')
 
     instr_pattern_c_sail= re.compile(
         '\[\d*\]\s\[(.*?)\]:\s(?P<addr>[0-9xABCDEF]+)\s\((?P<instr>[0-9xABCDEF]+)\)\s*(?P<mnemonic>.*)')
@@ -34,7 +38,11 @@ def extractRegisterCommitVal(self, line):
         instr_pattern = self.instr_pattern_c_sail_regt_reg_val
         re_search = instr_pattern.search(line)
         if re_search is not None:
-            return (re_search.group('regt'), re_search.group('reg'), re_search.group('val'))
+            rtype = re_search.group('regt')
+            cval = re_search.group('val')
+            if rtype =='f' and self.arch[1] == 32:
+                cval = cval[0:2]+cval[-8:]
+            return (rtype, re_search.group('reg'), cval)
         else:
             return None
 

setup.cfg

@@ -1,5 +1,5 @@
 [bumpversion]
-current_version = 0.16.0
+current_version = 0.16.1
 commit = True
 tag = True
 

setup.py

@@ -26,7 +26,7 @@ def read_requires():
 
 setup(
     name='riscv_isac',
-    version='0.16.0',
+    version='0.16.1',
     description="RISC-V ISAC",
     long_description=readme + '\n\n',
     classifiers=[