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Why do some checkpoints have a count of 0? #88
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That is very odd. Could you try it again with parser-name sail? I wonder if
there is a parser problem somewhere
…On Mon, Apr 22, 2024 at 3:48 AM zzhai ***@***.***> wrote:
I am using RISCV-ISAC to generate the add instruction coverage. I found
that some checkpoints in CGF are 0, but it is obvious from the assembly
file that this constraint is satisfied. Is this normal?
The riscv_isac was installed by source code. The spike version is
1.1.1-dev. The gcc version is "riscv32-unknown-elf-gcc (g2ee5e430018)
12.2.0".
I used the following command to generate the instruction coverage.
I first cloned arch-test using RISCOF and then created the default
configuration.
riscof --verbose info arch-test --clone
riscof setup --refname=sail_cSim --dutname=spike
Compile:
riscv32-unknown-elf-gcc -march=rv32i -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T ./sail_cSim/env/link.ld -I ./sail_cSim/env/ -I ./riscv-arch-test/riscv-test-suite/env -mabi=ilp32 ./riscv-arch-test/riscv-test-suite/rv32i_m/I/src/add-01.S -o ref.elf -DTEST_CASE_1=True -DXLEN=32
Generate trace:
spike --log-commits --isa=rv32imc +signature=Reference-spike.signature +signature-granularity=4 ref.elf > add-01.log 2>&1
Generate coverage:
riscv_isac --verbose info coverage -d -t add-01.log --parser-name spike -o coverage.rpt -e ref.elf -c ./riscv-arch-test/coverage/dataset.cgf -c ./riscv-arch-test/coverage/rvi.cgf -x32 -l add
From the Coverage report, I see that the constraint, "rs1_val ==
-2147483648", has a count of 0. However, the string can be searched
directly from the assembly file, which indicates there is at least one test
case that satisfies this constraint.
I have packed all the necessary files. If I make a mistake, please let me
know. Thanks.
Test.tar.gz
<https://github.com/riscv-software-src/riscv-isac/files/15061548/Test.tar.gz>
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I've been informed that we only use the Sail parser, so the spike parser likely has problems.
If it still fails, we will look into it further, but we don't have missing coverage when the tests are run before merging them.
Please close the issue if that is the case.
On Tue, Apr 23, 2024 at 9:21 PM Allen Baum ***@***.***>
wrote:
… That is very odd. Could you try it again with parser-name sail? I wonder
if there is a parser problem somewhere
On Mon, Apr 22, 2024 at 3:48 AM zzhai ***@***.***> wrote:
> I am using RISCV-ISAC to generate the add instruction coverage. I found
> that some checkpoints in CGF are 0, but it is obvious from the assembly
> file that this constraint is satisfied. Is this normal?
>
> The riscv_isac was installed by source code. The spike version is
> 1.1.1-dev. The gcc version is "riscv32-unknown-elf-gcc (g2ee5e430018)
> 12.2.0".
> I used the following command to generate the instruction coverage.
> I first cloned arch-test using RISCOF and then created the default
> configuration.
>
> riscof --verbose info arch-test --clone
> riscof setup --refname=sail_cSim --dutname=spike
>
> Compile:
>
> riscv32-unknown-elf-gcc -march=rv32i -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T ./sail_cSim/env/link.ld -I ./sail_cSim/env/ -I ./riscv-arch-test/riscv-test-suite/env -mabi=ilp32 ./riscv-arch-test/riscv-test-suite/rv32i_m/I/src/add-01.S -o ref.elf -DTEST_CASE_1=True -DXLEN=32
>
> Generate trace:
>
> spike --log-commits --isa=rv32imc +signature=Reference-spike.signature +signature-granularity=4 ref.elf > add-01.log 2>&1
>
> Generate coverage:
>
> riscv_isac --verbose info coverage -d -t add-01.log --parser-name spike -o coverage.rpt -e ref.elf -c ./riscv-arch-test/coverage/dataset.cgf -c ./riscv-arch-test/coverage/rvi.cgf -x32 -l add
>
> From the Coverage report, I see that the constraint, "rs1_val ==
> -2147483648", has a count of 0. However, the string can be searched
> directly from the assembly file, which indicates there is at least one test
> case that satisfies this constraint.
>
> I have packed all the necessary files. If I make a mistake, please let me
> know. Thanks.
> Test.tar.gz
> <https://github.com/riscv-software-src/riscv-isac/files/15061548/Test.tar.gz>
>
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> Reply to this email directly, view it on GitHub
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Initially, I used the default parameter of RISCOF, which is Sail, but the count of all checkpoints was 0.
As a result, the count for each checkpoint in val_comb group is 0, while all checkpoints in other groups are normal. I suspect that instructionObject evaluates an incorrect register value. My RISCV-ISAC installation is from source code. Specifically commit: 1bdc0a7. |
This is the generated Coverage file, I changed the suffix. |
@zzh1010016195 I would recommend to use riscof coverage command to evaluate the full coverage against the arch_test. |
Yes, that's what I initially did, but I ended up with incorrect results.
I only test the add instruction. Here are the latest results. Maybe there is some problem with my environment. If anyone runs successfully, please let me know and I will close the issue. |
This command is running successfully at my side. We can have a zoom call to resolve this query. There can be multiple reasons for this, e.g, riscof-plugins are not doing what they intend to do, so probably ISAC wasn't installed correctly. |
Thank you so much for dealing with this!
…On Wed, Apr 24, 2024 at 10:19 PM Umer Shahid ***@***.***> wrote:
This command is running successfully at my side. We can have a zoom call
to resolve this query. There can be multiple reasons for this, e.g,
riscof-plugins are not doing what they intend to do, so probably ISAC
wasn't installed correctly.
Ping me ***@***.***, we will setup a zoom meeting to
discuss this issue.
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Thank you for your assistance. However, it may not be convenient for me to attend the online discussion. I am attempting to recreate the issue in docker container. Once I can successfully replicate it, I will upload the Dockerfile here so others can reproduce the issue. If all goes well, I'll explain it here and close this issue. Thank you once again for your help. |
I have created a Dockerfile and replicated the issue on Ubuntu.
Then run the following command after installing docker.
The coverage file should be here: |
I am using RISCV-ISAC to generate the add instruction coverage. I found that some checkpoints in CGF are 0, but it is obvious from the assembly file that this constraint is satisfied. Is this normal?
The riscv_isac was installed by source code. The spike version is 1.1.1-dev. The gcc version is "riscv32-unknown-elf-gcc (g2ee5e430018) 12.2.0".
I used the following command to generate the instruction coverage.
I first cloned arch-test using RISCOF and then created the default configuration.
Compile:
Generate trace:
Generate coverage:
From the Coverage report, I see that the constraint, "rs1_val == -2147483648", has a count of 0. However, the string can be searched directly from the assembly file, which indicates there is at least one test case that satisfies this constraint.
I have packed all the necessary files. If I make a mistake, please let me know. Thanks.
Test.tar.gz
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